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i386/kvm: hv-stimer requires hv-time and hv-synic
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
b827df58 98
0b368a10
JD		 99static uint32_t has_architectural_pmu_version;
100static uint32_t num_architectural_pmu_gp_counters;
101static uint32_t num_architectural_pmu_fixed_counters;
0d894367 102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9 109static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 110static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 111
28143b40
TH		 112int kvm_has_pit_state2(void)
113{
114 return has_pit_state2;
115}
116
355023f2
PB		 117bool kvm_has_smm(void)
118{
119 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
120}
121
6053a86f
MT		 122bool kvm_has_adjust_clock_stable(void)
123{
124 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
125
126 return (ret == KVM_CLOCK_TSC_STABLE);
127}
128
1d31f66b
PM		 129bool kvm_allows_irq0_override(void)
130{
131 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
132}
133
fb506e70
RK		 134static bool kvm_x2apic_api_set_flags(uint64_t flags)
135{
136 KVMState *s = KVM_STATE(current_machine->accelerator);
137
138 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
139}
140
e391c009 141#define MEMORIZE(fn, _result) \
2a138ec3 142 ({ \
2a138ec3
RK		 143 static bool _memorized; \
144 \
145 if (_memorized) { \
146 return _result; \
147 } \
148 _memorized = true; \
149 _result = fn; \
150 })
151
e391c009
IM		 152static bool has_x2apic_api;
153
154bool kvm_has_x2apic_api(void)
155{
156 return has_x2apic_api;
157}
158
fb506e70
RK		 159bool kvm_enable_x2apic(void)
160{
2a138ec3
RK		 161 return MEMORIZE(
162 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 163 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
164 has_x2apic_api);
fb506e70
RK		 165}
166
e9688fab
RK		 167bool kvm_hv_vpindex_settable(void)
168{
169 return hv_vpindex_settable;
170}
171
0fd7e098
LL		 172static int kvm_get_tsc(CPUState *cs)
173{
174 X86CPU *cpu = X86_CPU(cs);
175 CPUX86State *env = &cpu->env;
176 struct {
177 struct kvm_msrs info;
178 struct kvm_msr_entry entries[1];
179 } msr_data;
180 int ret;
181
182 if (env->tsc_valid) {
183 return 0;
184 }
185
186 msr_data.info.nmsrs = 1;
187 msr_data.entries[0].index = MSR_IA32_TSC;
188 env->tsc_valid = !runstate_is_running();
189
190 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
191 if (ret < 0) {
192 return ret;
193 }
194
48e1a45c 195 assert(ret == 1);
0fd7e098
LL		 196 env->tsc = msr_data.entries[0].data;
197 return 0;
198}
199
14e6fe12 200static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 201{
0fd7e098
LL		 202 kvm_get_tsc(cpu);
203}
204
205void kvm_synchronize_all_tsc(void)
206{
207 CPUState *cpu;
208
209 if (kvm_enabled()) {
210 CPU_FOREACH(cpu) {
14e6fe12 211 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 212 }
213 }
214}
215
b827df58
AK		 216static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
217{
218 struct kvm_cpuid2 *cpuid;
219 int r, size;
220
221 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 222 cpuid = g_malloc0(size);
b827df58
AK		 223 cpuid->nent = max;
224 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 225 if (r == 0 && cpuid->nent >= max) {
226 r = -E2BIG;
227 }
b827df58
AK		 228 if (r < 0) {
229 if (r == -E2BIG) {
7267c094 230 g_free(cpuid);
b827df58
AK		 231 return NULL;
232 } else {
233 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
234 strerror(-r));
235 exit(1);
236 }
237 }
238 return cpuid;
239}
240
dd87f8a6
EH		 241/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
242 * for all entries.
243 */
244static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
245{
246 struct kvm_cpuid2 *cpuid;
247 int max = 1;
494e95e9
CP		 248
249 if (cpuid_cache != NULL) {
250 return cpuid_cache;
251 }
dd87f8a6
EH		 252 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
253 max *= 2;
254 }
494e95e9 255 cpuid_cache = cpuid;
dd87f8a6
EH		 256 return cpuid;
257}
258
a443bc34 259static const struct kvm_para_features {
0c31b744
GC		 260 int cap;
261 int feature;
262} para_features[] = {
263 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
264 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
265 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 266 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 267};
268
ba9bc59e 269static int get_para_features(KVMState *s)
0c31b744
GC		 270{
271 int i, features = 0;
272
8e03c100 273 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 274 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 275 features |= (1 << para_features[i].feature);
276 }
277 }
278
279 return features;
280}
0c31b744 281
40e80ee4
EH		 282static bool host_tsx_blacklisted(void)
283{
284 int family, model, stepping;\
285 char vendor[CPUID_VENDOR_SZ + 1];
286
287 host_vendor_fms(vendor, &family, &model, &stepping);
288
289 /* Check if we are running on a Haswell host known to have broken TSX */
290 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
291 (family == 6) &&
292 ((model == 63 && stepping < 4) ||
293 model == 60 || model == 69 || model == 70);
294}
0c31b744 295
829ae2f9
EH		 296/* Returns the value for a specific register on the cpuid entry
297 */
298static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
299{
300 uint32_t ret = 0;
301 switch (reg) {
302 case R_EAX:
303 ret = entry->eax;
304 break;
305 case R_EBX:
306 ret = entry->ebx;
307 break;
308 case R_ECX:
309 ret = entry->ecx;
310 break;
311 case R_EDX:
312 ret = entry->edx;
313 break;
314 }
315 return ret;
316}
317
4fb73f1d
EH		 318/* Find matching entry for function/index on kvm_cpuid2 struct
319 */
320static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
321 uint32_t function,
322 uint32_t index)
323{
324 int i;
325 for (i = 0; i < cpuid->nent; ++i) {
326 if (cpuid->entries[i].function == function &&
327 cpuid->entries[i].index == index) {
328 return &cpuid->entries[i];
329 }
330 }
331 /* not found: */
332 return NULL;
333}
334
ba9bc59e 335uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 336 uint32_t index, int reg)
b827df58
AK		 337{
338 struct kvm_cpuid2 *cpuid;
b827df58
AK		 339 uint32_t ret = 0;
340 uint32_t cpuid_1_edx;
8c723b79 341 bool found = false;
b827df58 342
dd87f8a6 343 cpuid = get_supported_cpuid(s);
b827df58 344
4fb73f1d
EH		 345 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
346 if (entry) {
347 found = true;
348 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 349 }
350
7b46e5ce
EH		 351 /* Fixups for the data returned by KVM, below */
352
c2acb022
EH		 353 if (function == 1 && reg == R_EDX) {
354 /* KVM before 2.6.30 misreports the following features */
355 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 356 } else if (function == 1 && reg == R_ECX) {
357 /* We can set the hypervisor flag, even if KVM does not return it on
358 * GET_SUPPORTED_CPUID
359 */
360 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 361 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
362 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
363 * and the irqchip is in the kernel.
364 */
365 if (kvm_irqchip_in_kernel() &&
366 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
367 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
368 }
41e5e76d
EH		 369
370 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
371 * without the in-kernel irqchip
372 */
373 if (!kvm_irqchip_in_kernel()) {
374 ret &= ~CPUID_EXT_X2APIC;
b827df58 375 }
2266d443
MT		 376
377 if (enable_cpu_pm) {
378 int disable_exits = kvm_check_extension(s,
379 KVM_CAP_X86_DISABLE_EXITS);
380
381 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
382 ret |= CPUID_EXT_MONITOR;
383 }
384 }
28b8e4d0
JK		 385 } else if (function == 6 && reg == R_EAX) {
386 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 387 } else if (function == 7 && index == 0 && reg == R_EBX) {
388 if (host_tsx_blacklisted()) {
389 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
390 }
485b1d25
EH		 391 } else if (function == 7 && index == 0 && reg == R_EDX) {
392 /*
393 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
394 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
395 * returned by KVM_GET_MSR_INDEX_LIST.
396 */
397 if (!has_msr_arch_capabs) {
398 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
399 }
f98bbd83
BM		 400 } else if (function == 0x80000001 && reg == R_ECX) {
401 /*
402 * It's safe to enable TOPOEXT even if it's not returned by
403 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
404 * us to keep CPU models including TOPOEXT runnable on older kernels.
405 */
406 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 407 } else if (function == 0x80000001 && reg == R_EDX) {
408 /* On Intel, kvm returns cpuid according to the Intel spec,
409 * so add missing bits according to the AMD spec:
410 */
411 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
412 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 413 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
414 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
415 * be enabled without the in-kernel irqchip
416 */
417 if (!kvm_irqchip_in_kernel()) {
418 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
419 }
be777326 420 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 421 ret |= 1U << KVM_HINTS_REALTIME;
be777326 422 found = 1;
b827df58
AK		 423 }
424
0c31b744 425 /* fallback for older kernels */
8c723b79 426 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 427 ret = get_para_features(s);
b9bec74b 428 }
0c31b744
GC		 429
430 return ret;
bb0300dc 431}
bb0300dc 432
f57bceb6
RH		 433uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
434{
435 struct {
436 struct kvm_msrs info;
437 struct kvm_msr_entry entries[1];
438 } msr_data;
439 uint32_t ret;
440
441 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
442 return 0;
443 }
444
445 /* Check if requested MSR is supported feature MSR */
446 int i;
447 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
448 if (kvm_feature_msrs->indices[i] == index) {
449 break;
450 }
451 if (i == kvm_feature_msrs->nmsrs) {
452 return 0; /* if the feature MSR is not supported, simply return 0 */
453 }
454
455 msr_data.info.nmsrs = 1;
456 msr_data.entries[0].index = index;
457
458 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
459 if (ret != 1) {
460 error_report("KVM get MSR (index=0x%x) feature failed, %s",
461 index, strerror(-ret));
462 exit(1);
463 }
464
465 return msr_data.entries[0].data;
466}
467
468
3c85e74f
HY		 469typedef struct HWPoisonPage {
470 ram_addr_t ram_addr;
471 QLIST_ENTRY(HWPoisonPage) list;
472} HWPoisonPage;
473
474static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
475 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
476
477static void kvm_unpoison_all(void *param)
478{
479 HWPoisonPage *page, *next_page;
480
481 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
482 QLIST_REMOVE(page, list);
483 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 484 g_free(page);
3c85e74f
HY		 485 }
486}
487
3c85e74f
HY		 488static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
489{
490 HWPoisonPage *page;
491
492 QLIST_FOREACH(page, &hwpoison_page_list, list) {
493 if (page->ram_addr == ram_addr) {
494 return;
495 }
496 }
ab3ad07f 497 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 498 page->ram_addr = ram_addr;
499 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
500}
501
e7701825
MT		 502static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
503 int *max_banks)
504{
505 int r;
506
14a09518 507 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 508 if (r > 0) {
509 *max_banks = r;
510 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
511 }
512 return -ENOSYS;
513}
514
bee615d4 515static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 516{
87f8b626 517 CPUState *cs = CPU(cpu);
bee615d4 518 CPUX86State *env = &cpu->env;
c34d440a
JK		 519 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
520 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
521 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 522 int flags = 0;
e7701825 523
c34d440a
JK		 524 if (code == BUS_MCEERR_AR) {
525 status |= MCI_STATUS_AR | 0x134;
526 mcg_status |= MCG_STATUS_EIPV;
527 } else {
528 status |= 0xc0;
529 mcg_status |= MCG_STATUS_RIPV;
419fb20a 530 }
87f8b626
AR		 531
532 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
533 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
534 * guest kernel back into env->mcg_ext_ctl.
535 */
536 cpu_synchronize_state(cs);
537 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
538 mcg_status |= MCG_STATUS_LMCE;
539 flags = 0;
540 }
541
8c5cf3b6 542 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 543 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 544}
419fb20a
JK		 545
546static void hardware_memory_error(void)
547{
548 fprintf(stderr, "Hardware memory error!\n");
549 exit(1);
550}
551
2ae41db2 552void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 553{
20d695a9
AF		 554 X86CPU *cpu = X86_CPU(c);
555 CPUX86State *env = &cpu->env;
419fb20a 556 ram_addr_t ram_addr;
a8170e5e 557 hwaddr paddr;
419fb20a 558
4d39892c
PB		 559 /* If we get an action required MCE, it has been injected by KVM
560 * while the VM was running. An action optional MCE instead should
561 * be coming from the main thread, which qemu_init_sigbus identifies
562 * as the "early kill" thread.
563 */
a16fc07e 564 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 565
20e0ff59 566 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 567 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 568 if (ram_addr != RAM_ADDR_INVALID &&
569 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
570 kvm_hwpoison_page_add(ram_addr);
571 kvm_mce_inject(cpu, paddr, code);
2ae41db2 572 return;
419fb20a 573 }
20e0ff59
PB		 574
575 fprintf(stderr, "Hardware memory error for memory used by "
576 "QEMU itself instead of guest system!\n");
419fb20a 577 }
20e0ff59
PB		 578
579 if (code == BUS_MCEERR_AR) {
580 hardware_memory_error();
581 }
582
583 /* Hope we are lucky for AO MCE */
419fb20a
JK		 584}
585
1bc22652 586static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 587{
1bc22652
AF		 588 CPUX86State *env = &cpu->env;
589
ab443475
JK		 590 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
591 unsigned int bank, bank_num = env->mcg_cap & 0xff;
592 struct kvm_x86_mce mce;
593
594 env->exception_injected = -1;
595
596 /*
597 * There must be at least one bank in use if an MCE is pending.
598 * Find it and use its values for the event injection.
599 */
600 for (bank = 0; bank < bank_num; bank++) {
601 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
602 break;
603 }
604 }
605 assert(bank < bank_num);
606
607 mce.bank = bank;
608 mce.status = env->mce_banks[bank * 4 + 1];
609 mce.mcg_status = env->mcg_status;
610 mce.addr = env->mce_banks[bank * 4 + 2];
611 mce.misc = env->mce_banks[bank * 4 + 3];
612
1bc22652 613 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 614 }
ab443475
JK		 615 return 0;
616}
617
1dfb4dd9 618static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 619{
317ac620 620 CPUX86State *env = opaque;
b8cc45d6
GC		 621
622 if (running) {
623 env->tsc_valid = false;
624 }
625}
626
83b17af5 627unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 628{
83b17af5 629 X86CPU *cpu = X86_CPU(cs);
7e72a45c 630 return cpu->apic_id;
b164e48e
EH		 631}
632
92067bf4
IM		 633#ifndef KVM_CPUID_SIGNATURE_NEXT
634#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
635#endif
636
92067bf4
IM		 637static bool hyperv_enabled(X86CPU *cpu)
638{
7bc3d711
PB		 639 CPUState *cs = CPU(cpu);
640 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 641 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 642 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 643}
644
5031283d
HZ		 645static int kvm_arch_set_tsc_khz(CPUState *cs)
646{
647 X86CPU *cpu = X86_CPU(cs);
648 CPUX86State *env = &cpu->env;
649 int r;
650
651 if (!env->tsc_khz) {
652 return 0;
653 }
654
655 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
656 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
657 -ENOTSUP;
658 if (r < 0) {
659 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
660 * TSC frequency doesn't match the one we want.
661 */
662 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
663 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
664 -ENOTSUP;
665 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 666 warn_report("TSC frequency mismatch between "
667 "VM (%" PRId64 " kHz) and host (%d kHz), "
668 "and TSC scaling unavailable",
669 env->tsc_khz, cur_freq);
5031283d
HZ		 670 return r;
671 }
672 }
673
674 return 0;
675}
676
4bb95b82
LP		 677static bool tsc_is_stable_and_known(CPUX86State *env)
678{
679 if (!env->tsc_khz) {
680 return false;
681 }
682 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
683 || env->user_tsc_khz;
684}
685
6760bd20
VK		 686static struct {
687 const char *desc;
688 struct {
689 uint32_t fw;
690 uint32_t bits;
691 } flags[2];
c6861930 692 uint64_t dependencies;
6760bd20
VK		 693} kvm_hyperv_properties[] = {
694 [HYPERV_FEAT_RELAXED] = {
695 .desc = "relaxed timing (hv-relaxed)",
696 .flags = {
697 {.fw = FEAT_HYPERV_EAX,
698 .bits = HV_HYPERCALL_AVAILABLE},
699 {.fw = FEAT_HV_RECOMM_EAX,
700 .bits = HV_RELAXED_TIMING_RECOMMENDED}
701 }
702 },
703 [HYPERV_FEAT_VAPIC] = {
704 .desc = "virtual APIC (hv-vapic)",
705 .flags = {
706 {.fw = FEAT_HYPERV_EAX,
707 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
708 {.fw = FEAT_HV_RECOMM_EAX,
709 .bits = HV_APIC_ACCESS_RECOMMENDED}
710 }
711 },
712 [HYPERV_FEAT_TIME] = {
713 .desc = "clocksources (hv-time)",
714 .flags = {
715 {.fw = FEAT_HYPERV_EAX,
716 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
717 HV_REFERENCE_TSC_AVAILABLE}
718 }
719 },
720 [HYPERV_FEAT_CRASH] = {
721 .desc = "crash MSRs (hv-crash)",
722 .flags = {
723 {.fw = FEAT_HYPERV_EDX,
724 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
725 }
726 },
727 [HYPERV_FEAT_RESET] = {
728 .desc = "reset MSR (hv-reset)",
729 .flags = {
730 {.fw = FEAT_HYPERV_EAX,
731 .bits = HV_RESET_AVAILABLE}
732 }
733 },
734 [HYPERV_FEAT_VPINDEX] = {
735 .desc = "VP_INDEX MSR (hv-vpindex)",
736 .flags = {
737 {.fw = FEAT_HYPERV_EAX,
738 .bits = HV_VP_INDEX_AVAILABLE}
739 }
740 },
741 [HYPERV_FEAT_RUNTIME] = {
742 .desc = "VP_RUNTIME MSR (hv-runtime)",
743 .flags = {
744 {.fw = FEAT_HYPERV_EAX,
745 .bits = HV_VP_RUNTIME_AVAILABLE}
746 }
747 },
748 [HYPERV_FEAT_SYNIC] = {
749 .desc = "synthetic interrupt controller (hv-synic)",
750 .flags = {
751 {.fw = FEAT_HYPERV_EAX,
752 .bits = HV_SYNIC_AVAILABLE}
753 }
754 },
755 [HYPERV_FEAT_STIMER] = {
756 .desc = "synthetic timers (hv-stimer)",
757 .flags = {
758 {.fw = FEAT_HYPERV_EAX,
759 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 760 },
761 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 762 },
763 [HYPERV_FEAT_FREQUENCIES] = {
764 .desc = "frequency MSRs (hv-frequencies)",
765 .flags = {
766 {.fw = FEAT_HYPERV_EAX,
767 .bits = HV_ACCESS_FREQUENCY_MSRS},
768 {.fw = FEAT_HYPERV_EDX,
769 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
770 }
771 },
772 [HYPERV_FEAT_REENLIGHTENMENT] = {
773 .desc = "reenlightenment MSRs (hv-reenlightenment)",
774 .flags = {
775 {.fw = FEAT_HYPERV_EAX,
776 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
777 }
778 },
779 [HYPERV_FEAT_TLBFLUSH] = {
780 .desc = "paravirtualized TLB flush (hv-tlbflush)",
781 .flags = {
782 {.fw = FEAT_HV_RECOMM_EAX,
783 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
784 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
785 }
786 },
787 [HYPERV_FEAT_EVMCS] = {
788 .desc = "enlightened VMCS (hv-evmcs)",
789 .flags = {
790 {.fw = FEAT_HV_RECOMM_EAX,
791 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
792 }
793 },
794 [HYPERV_FEAT_IPI] = {
795 .desc = "paravirtualized IPI (hv-ipi)",
796 .flags = {
797 {.fw = FEAT_HV_RECOMM_EAX,
798 .bits = HV_CLUSTER_IPI_RECOMMENDED |
799 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
800 }
801 },
802};
803
804static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
805{
806 struct kvm_cpuid2 *cpuid;
807 int r, size;
808
809 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
810 cpuid = g_malloc0(size);
811 cpuid->nent = max;
812
813 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
814 if (r == 0 && cpuid->nent >= max) {
815 r = -E2BIG;
816 }
817 if (r < 0) {
818 if (r == -E2BIG) {
819 g_free(cpuid);
820 return NULL;
821 } else {
822 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
823 strerror(-r));
824 exit(1);
825 }
826 }
827 return cpuid;
828}
829
830/*
831 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
832 * for all entries.
833 */
834static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
835{
836 struct kvm_cpuid2 *cpuid;
837 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
838
839 /*
840 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
841 * -E2BIG, however, it doesn't report back the right size. Keep increasing
842 * it and re-trying until we succeed.
843 */
844 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
845 max++;
846 }
847 return cpuid;
848}
849
850/*
851 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
852 * leaves from KVM_CAP_HYPERV* and present MSRs data.
853 */
854static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 855{
856 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 857 struct kvm_cpuid2 *cpuid;
858 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
859
860 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
861 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
862 cpuid->nent = 2;
863
864 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
865 entry_feat = &cpuid->entries[0];
866 entry_feat->function = HV_CPUID_FEATURES;
867
868 entry_recomm = &cpuid->entries[1];
869 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
870 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
871
872 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
873 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
874 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
875 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
876 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
877 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
878 }
c35bd19a 879
6760bd20
VK		 880 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
881 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
882 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 883 }
6760bd20
VK		 884
885 if (has_msr_hv_frequencies) {
886 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
887 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 888 }
6760bd20
VK		 889
890 if (has_msr_hv_crash) {
891 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 892 }
6760bd20
VK		 893
894 if (has_msr_hv_reenlightenment) {
895 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 896 }
6760bd20
VK		 897
898 if (has_msr_hv_reset) {
899 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 900 }
6760bd20
VK		 901
902 if (has_msr_hv_vpindex) {
903 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 904 }
6760bd20
VK		 905
906 if (has_msr_hv_runtime) {
907 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 908 }
6760bd20
VK		 909
910 if (has_msr_hv_synic) {
911 unsigned int cap = cpu->hyperv_synic_kvm_only ?
912 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
913
914 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
915 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 916 }
c35bd19a 917 }
6760bd20
VK		 918
919 if (has_msr_hv_stimer) {
920 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 921 }
9b4cf107 922
6760bd20
VK		 923 if (kvm_check_extension(cs->kvm_state,
924 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
925 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
926 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
927 }
c35bd19a 928
6760bd20
VK		 929 if (kvm_check_extension(cs->kvm_state,
930 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
931 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 932 }
6760bd20
VK		 933
934 if (kvm_check_extension(cs->kvm_state,
935 KVM_CAP_HYPERV_SEND_IPI) > 0) {
936 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
937 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 938 }
6760bd20
VK		 939
940 return cpuid;
941}
942
943static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
944{
945 struct kvm_cpuid_entry2 *entry;
946 uint32_t func;
947 int reg;
948
949 switch (fw) {
950 case FEAT_HYPERV_EAX:
951 reg = R_EAX;
952 func = HV_CPUID_FEATURES;
953 break;
954 case FEAT_HYPERV_EDX:
955 reg = R_EDX;
956 func = HV_CPUID_FEATURES;
957 break;
958 case FEAT_HV_RECOMM_EAX:
959 reg = R_EAX;
960 func = HV_CPUID_ENLIGHTMENT_INFO;
961 break;
962 default:
963 return -EINVAL;
a2b107db 964 }
6760bd20
VK		 965
966 entry = cpuid_find_entry(cpuid, func, 0);
967 if (!entry) {
968 return -ENOENT;
a2b107db 969 }
6760bd20
VK		 970
971 switch (reg) {
972 case R_EAX:
973 *r = entry->eax;
974 break;
975 case R_EDX:
976 *r = entry->edx;
977 break;
978 default:
979 return -EINVAL;
a2b107db 980 }
6760bd20
VK		 981
982 return 0;
983}
984
985static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
986 int feature)
987{
988 X86CPU *cpu = X86_CPU(cs);
989 CPUX86State *env = &cpu->env;
e48ddcc6 990 uint32_t r, fw, bits;
c6861930
VK		 991 uint64_t deps;
992 int i, dep_feat = 0;
6760bd20 993
e48ddcc6 994 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 995 return 0;
996 }
997
c6861930
VK		 998 deps = kvm_hyperv_properties[feature].dependencies;
999 while ((dep_feat = find_next_bit(&deps, 64, dep_feat)) < 64) {
1000 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1001 fprintf(stderr,
1002 "Hyper-V %s requires Hyper-V %s\n",
1003 kvm_hyperv_properties[feature].desc,
1004 kvm_hyperv_properties[dep_feat].desc);
1005 return 1;
1006 }
1007 dep_feat++;
1008 }
1009
6760bd20
VK		 1010 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1011 fw = kvm_hyperv_properties[feature].flags[i].fw;
1012 bits = kvm_hyperv_properties[feature].flags[i].bits;
1013
1014 if (!fw) {
1015 continue;
a2b107db 1016 }
6760bd20
VK		 1017
1018 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1019 if (hyperv_feat_enabled(cpu, feature)) {
1020 fprintf(stderr,
1021 "Hyper-V %s is not supported by kernel\n",
1022 kvm_hyperv_properties[feature].desc);
1023 return 1;
1024 } else {
1025 return 0;
1026 }
6760bd20
VK		 1027 }
1028
1029 env->features[fw] |= bits;
a2b107db 1030 }
6760bd20 1031
e48ddcc6
VK		 1032 if (cpu->hyperv_passthrough) {
1033 cpu->hyperv_features |= BIT(feature);
1034 }
1035
6760bd20
VK		 1036 return 0;
1037}
1038
2344d22e
VK		 1039/*
1040 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1041 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1042 * extentions are enabled.
1043 */
1044static int hyperv_handle_properties(CPUState *cs,
1045 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1046{
1047 X86CPU *cpu = X86_CPU(cs);
1048 CPUX86State *env = &cpu->env;
1049 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1050 struct kvm_cpuid_entry2 *c;
1051 uint32_t signature[3];
1052 uint32_t cpuid_i = 0;
e48ddcc6 1053 int r;
6760bd20 1054
2344d22e
VK		 1055 if (!hyperv_enabled(cpu))
1056 return 0;
1057
e48ddcc6
VK		 1058 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1059 cpu->hyperv_passthrough) {
a2b107db
VK		 1060 uint16_t evmcs_version;
1061
e48ddcc6
VK		 1062 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1063 (uintptr_t)&evmcs_version);
1064
1065 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1066 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1067 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1068 return -ENOSYS;
1069 }
e48ddcc6
VK		 1070
1071 if (!r) {
1072 env->features[FEAT_HV_RECOMM_EAX] |=
1073 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1074 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1075 }
a2b107db
VK		 1076 }
1077
6760bd20
VK		 1078 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1079 cpuid = get_supported_hv_cpuid(cs);
1080 } else {
1081 cpuid = get_supported_hv_cpuid_legacy(cs);
1082 }
1083
e48ddcc6
VK		 1084 if (cpu->hyperv_passthrough) {
1085 memcpy(cpuid_ent, &cpuid->entries[0],
1086 cpuid->nent * sizeof(cpuid->entries[0]));
1087
1088 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1089 if (c) {
1090 env->features[FEAT_HYPERV_EAX] = c->eax;
1091 env->features[FEAT_HYPERV_EBX] = c->ebx;
1092 env->features[FEAT_HYPERV_EDX] = c->eax;
1093 }
1094 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1095 if (c) {
1096 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1097
1098 /* hv-spinlocks may have been overriden */
1099 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1100 c->ebx = cpu->hyperv_spinlock_attempts;
1101 }
1102 }
1103 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1104 if (c) {
1105 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1106 }
1107 }
1108
6760bd20 1109 /* Features */
e48ddcc6 1110 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1111 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1112 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1113 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1114 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1115 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1116 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1117 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1118 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1119 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1120 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1121 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1122 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1123 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1124
c6861930 1125 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1126 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1127 !cpu->hyperv_synic_kvm_only &&
1128 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1129 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1130 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1131 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1132 r |= 1;
1133 }
1134
1135 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1136 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1137
2344d22e
VK		 1138 if (r) {
1139 r = -ENOSYS;
1140 goto free;
1141 }
1142
e48ddcc6
VK		 1143 if (cpu->hyperv_passthrough) {
1144 /* We already copied all feature words from KVM as is */
1145 r = cpuid->nent;
1146 goto free;
1147 }
1148
2344d22e
VK		 1149 c = &cpuid_ent[cpuid_i++];
1150 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1151 if (!cpu->hyperv_vendor_id) {
1152 memcpy(signature, "Microsoft Hv", 12);
1153 } else {
1154 size_t len = strlen(cpu->hyperv_vendor_id);
1155
1156 if (len > 12) {
1157 error_report("hv-vendor-id truncated to 12 characters");
1158 len = 12;
1159 }
1160 memset(signature, 0, 12);
1161 memcpy(signature, cpu->hyperv_vendor_id, len);
1162 }
1163 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1164 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1165 c->ebx = signature[0];
1166 c->ecx = signature[1];
1167 c->edx = signature[2];
1168
1169 c = &cpuid_ent[cpuid_i++];
1170 c->function = HV_CPUID_INTERFACE;
1171 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1172 c->eax = signature[0];
1173 c->ebx = 0;
1174 c->ecx = 0;
1175 c->edx = 0;
1176
1177 c = &cpuid_ent[cpuid_i++];
1178 c->function = HV_CPUID_VERSION;
1179 c->eax = 0x00001bbc;
1180 c->ebx = 0x00060001;
1181
1182 c = &cpuid_ent[cpuid_i++];
1183 c->function = HV_CPUID_FEATURES;
1184 c->eax = env->features[FEAT_HYPERV_EAX];
1185 c->ebx = env->features[FEAT_HYPERV_EBX];
1186 c->edx = env->features[FEAT_HYPERV_EDX];
1187
1188 c = &cpuid_ent[cpuid_i++];
1189 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1190 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1191 c->ebx = cpu->hyperv_spinlock_attempts;
1192
1193 c = &cpuid_ent[cpuid_i++];
1194 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1195 c->eax = cpu->hv_max_vps;
1196 c->ebx = 0x40;
1197
1198 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1199 __u32 function;
1200
1201 /* Create zeroed 0x40000006..0x40000009 leaves */
1202 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1203 function < HV_CPUID_NESTED_FEATURES; function++) {
1204 c = &cpuid_ent[cpuid_i++];
1205 c->function = function;
1206 }
1207
1208 c = &cpuid_ent[cpuid_i++];
1209 c->function = HV_CPUID_NESTED_FEATURES;
1210 c->eax = env->features[FEAT_HV_NESTED_EAX];
1211 }
1212 r = cpuid_i;
1213
1214free:
6760bd20
VK		 1215 g_free(cpuid);
1216
2344d22e 1217 return r;
c35bd19a
EY		 1218}
1219
e48ddcc6
VK		 1220static Error *hv_passthrough_mig_blocker;
1221
e9688fab
RK		 1222static int hyperv_init_vcpu(X86CPU *cpu)
1223{
729ce7e1 1224 CPUState *cs = CPU(cpu);
e48ddcc6 1225 Error *local_err = NULL;
729ce7e1
RK		 1226 int ret;
1227
e48ddcc6
VK		 1228 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1229 error_setg(&hv_passthrough_mig_blocker,
1230 "'hv-passthrough' CPU flag prevents migration, use explicit"
1231 " set of hv-* flags instead");
1232 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1233 if (local_err) {
1234 error_report_err(local_err);
1235 error_free(hv_passthrough_mig_blocker);
1236 return ret;
1237 }
1238 }
1239
2d384d7c 1240 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1241 /*
1242 * the kernel doesn't support setting vp_index; assert that its value
1243 * is in sync
1244 */
e9688fab
RK		 1245 struct {
1246 struct kvm_msrs info;
1247 struct kvm_msr_entry entries[1];
1248 } msr_data = {
1249 .info.nmsrs = 1,
1250 .entries[0].index = HV_X64_MSR_VP_INDEX,
1251 };
1252
729ce7e1 1253 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1254 if (ret < 0) {
1255 return ret;
1256 }
1257 assert(ret == 1);
1258
701189e3 1259 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1260 error_report("kernel's vp_index != QEMU's vp_index");
1261 return -ENXIO;
1262 }
1263 }
1264
2d384d7c 1265 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1266 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1267 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1268 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1269 if (ret < 0) {
1270 error_report("failed to turn on HyperV SynIC in KVM: %s",
1271 strerror(-ret));
1272 return ret;
1273 }
606c34bf 1274
9b4cf107
RK		 1275 if (!cpu->hyperv_synic_kvm_only) {
1276 ret = hyperv_x86_synic_add(cpu);
1277 if (ret < 0) {
1278 error_report("failed to create HyperV SynIC: %s",
1279 strerror(-ret));
1280 return ret;
1281 }
606c34bf 1282 }
729ce7e1
RK		 1283 }
1284
e9688fab
RK		 1285 return 0;
1286}
1287
68bfd0ad 1288static Error *invtsc_mig_blocker;
d98f2607 1289static Error *vmx_mig_blocker;
68bfd0ad 1290
f8bb0565 1291#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1292
20d695a9 1293int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1294{
1295 struct {
486bd5a2 1296 struct kvm_cpuid2 cpuid;
f8bb0565 1297 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1298 } cpuid_data;
1299 /*
1300 * The kernel defines these structs with padding fields so there
1301 * should be no extra padding in our cpuid_data struct.
1302 */
1303 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1304 sizeof(struct kvm_cpuid2) +
1305 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1306
20d695a9
AF		 1307 X86CPU *cpu = X86_CPU(cs);
1308 CPUX86State *env = &cpu->env;
486bd5a2 1309 uint32_t limit, i, j, cpuid_i;
a33609ca 1310 uint32_t unused;
bb0300dc 1311 struct kvm_cpuid_entry2 *c;
bb0300dc 1312 uint32_t signature[3];
234cc647 1313 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 1314 int r;
fe44dc91 1315 Error *local_err = NULL;
05330448 1316
ef4cbe14
SW		 1317 memset(&cpuid_data, 0, sizeof(cpuid_data));
1318
05330448
AL		 1319 cpuid_i = 0;
1320
ddb98b5a
LP		 1321 r = kvm_arch_set_tsc_khz(cs);
1322 if (r < 0) {
1323 goto fail;
1324 }
1325
1326 /* vcpu's TSC frequency is either specified by user, or following
1327 * the value used by KVM if the former is not present. In the
1328 * latter case, we query it from KVM and record in env->tsc_khz,
1329 * so that vcpu's TSC frequency can be migrated later via this field.
1330 */
1331 if (!env->tsc_khz) {
1332 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1333 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1334 -ENOTSUP;
1335 if (r > 0) {
1336 env->tsc_khz = r;
1337 }
1338 }
1339
bb0300dc 1340 /* Paravirtualization CPUIDs */
2344d22e
VK		 1341 r = hyperv_handle_properties(cs, cpuid_data.entries);
1342 if (r < 0) {
1343 return r;
1344 } else if (r > 0) {
1345 cpuid_i = r;
234cc647 1346 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1347 has_msr_hv_hypercall = true;
eab70139
VR		 1348 }
1349
f522d2ac
AW		 1350 if (cpu->expose_kvm) {
1351 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1352 c = &cpuid_data.entries[cpuid_i++];
1353 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1354 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1355 c->ebx = signature[0];
1356 c->ecx = signature[1];
1357 c->edx = signature[2];
234cc647 1358
f522d2ac
AW		 1359 c = &cpuid_data.entries[cpuid_i++];
1360 c->function = KVM_CPUID_FEATURES | kvm_base;
1361 c->eax = env->features[FEAT_KVM];
be777326 1362 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1363 }
917367aa 1364
a33609ca 1365 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1366
1367 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1368 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1369 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1370 abort();
1371 }
bb0300dc 1372 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1373
1374 switch (i) {
a36b1029
AL		 1375 case 2: {
1376 /* Keep reading function 2 till all the input is received */
1377 int times;
1378
a36b1029 1379 c->function = i;
a33609ca
AL		 1380 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1381 KVM_CPUID_FLAG_STATE_READ_NEXT;
1382 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1383 times = c->eax & 0xff;
a36b1029
AL		 1384
1385 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1386 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1387 fprintf(stderr, "cpuid_data is full, no space for "
1388 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1389 abort();
1390 }
a33609ca 1391 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1392 c->function = i;
a33609ca
AL		 1393 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1394 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1395 }
1396 break;
1397 }
486bd5a2
AL		 1398 case 4:
1399 case 0xb:
1400 case 0xd:
1401 for (j = 0; ; j++) {
31e8c696
AP		 1402 if (i == 0xd && j == 64) {
1403 break;
1404 }
486bd5a2
AL		 1405 c->function = i;
1406 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1407 c->index = j;
a33609ca 1408 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1409
b9bec74b 1410 if (i == 4 && c->eax == 0) {
486bd5a2 1411 break;
b9bec74b
JK		 1412 }
1413 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1414 break;
b9bec74b
JK		 1415 }
1416 if (i == 0xd && c->eax == 0) {
31e8c696 1417 continue;
b9bec74b 1418 }
f8bb0565
IM		 1419 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1420 fprintf(stderr, "cpuid_data is full, no space for "
1421 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1422 abort();
1423 }
a33609ca 1424 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1425 }
1426 break;
e37a5c7f
CP		 1427 case 0x14: {
1428 uint32_t times;
1429
1430 c->function = i;
1431 c->index = 0;
1432 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1433 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1434 times = c->eax;
1435
1436 for (j = 1; j <= times; ++j) {
1437 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1438 fprintf(stderr, "cpuid_data is full, no space for "
1439 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1440 abort();
1441 }
1442 c = &cpuid_data.entries[cpuid_i++];
1443 c->function = i;
1444 c->index = j;
1445 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1446 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1447 }
1448 break;
1449 }
486bd5a2 1450 default:
486bd5a2 1451 c->function = i;
a33609ca
AL		 1452 c->flags = 0;
1453 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1454 break;
1455 }
05330448 1456 }
0d894367
PB		 1457
1458 if (limit >= 0x0a) {
0b368a10 1459 uint32_t eax, edx;
0d894367 1460
0b368a10
JD		 1461 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1462
1463 has_architectural_pmu_version = eax & 0xff;
1464 if (has_architectural_pmu_version > 0) {
1465 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1466
1467 /* Shouldn't be more than 32, since that's the number of bits
1468 * available in EBX to tell us _which_ counters are available.
1469 * Play it safe.
1470 */
0b368a10
JD		 1471 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1472 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1473 }
1474
1475 if (has_architectural_pmu_version > 1) {
1476 num_architectural_pmu_fixed_counters = edx & 0x1f;
1477
1478 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1479 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1480 }
0d894367
PB		 1481 }
1482 }
1483 }
1484
a33609ca 1485 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1486
1487 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1488 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1489 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1490 abort();
1491 }
bb0300dc 1492 c = &cpuid_data.entries[cpuid_i++];
05330448 1493
8f4202fb
BM		 1494 switch (i) {
1495 case 0x8000001d:
1496 /* Query for all AMD cache information leaves */
1497 for (j = 0; ; j++) {
1498 c->function = i;
1499 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1500 c->index = j;
1501 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1502
1503 if (c->eax == 0) {
1504 break;
1505 }
1506 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1507 fprintf(stderr, "cpuid_data is full, no space for "
1508 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1509 abort();
1510 }
1511 c = &cpuid_data.entries[cpuid_i++];
1512 }
1513 break;
1514 default:
1515 c->function = i;
1516 c->flags = 0;
1517 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1518 break;
1519 }
05330448
AL		 1520 }
1521
b3baa152
BW		 1522 /* Call Centaur's CPUID instructions they are supported. */
1523 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1524 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1525
1526 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1527 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1528 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1529 abort();
1530 }
b3baa152
BW		 1531 c = &cpuid_data.entries[cpuid_i++];
1532
1533 c->function = i;
1534 c->flags = 0;
1535 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1536 }
1537 }
1538
05330448
AL		 1539 cpuid_data.cpuid.nent = cpuid_i;
1540
e7701825 1541 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1542 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1543 (CPUID_MCE | CPUID_MCA)
a60f24b5 1544 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1545 uint64_t mcg_cap, unsupported_caps;
e7701825 1546 int banks;
32a42024 1547 int ret;
e7701825 1548
a60f24b5 1549 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1550 if (ret < 0) {
1551 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1552 return ret;
e7701825 1553 }
75d49497 1554
2590f15b 1555 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1556 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1557 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1558 return -ENOTSUP;
75d49497 1559 }
49b69cbf 1560
5120901a
EH		 1561 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1562 if (unsupported_caps) {
87f8b626
AR		 1563 if (unsupported_caps & MCG_LMCE_P) {
1564 error_report("kvm: LMCE not supported");
1565 return -ENOTSUP;
1566 }
3dc6f869
AF		 1567 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1568 unsupported_caps);
5120901a
EH		 1569 }
1570
2590f15b
EH		 1571 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1572 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1573 if (ret < 0) {
1574 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1575 return ret;
1576 }
e7701825 1577 }
e7701825 1578
b8cc45d6
GC		 1579 qemu_add_vm_change_state_handler(cpu_update_state, env);
1580
df67696e
LJ		 1581 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1582 if (c) {
1583 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1584 !!(c->ecx & CPUID_EXT_SMX);
1585 }
1586
d98f2607
PB		 1587 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1588 error_setg(&vmx_mig_blocker,
1589 "Nested VMX virtualization does not support live migration yet");
1590 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1591 if (local_err) {
1592 error_report_err(local_err);
1593 error_free(vmx_mig_blocker);
1594 return r;
1595 }
1596 }
1597
87f8b626
AR		 1598 if (env->mcg_cap & MCG_LMCE_P) {
1599 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1600 }
1601
d99569d9
EH		 1602 if (!env->user_tsc_khz) {
1603 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1604 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1605 error_setg(&invtsc_mig_blocker,
1606 "State blocked by non-migratable CPU device"
1607 " (invtsc flag)");
fe44dc91
AA		 1608 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1609 if (local_err) {
1610 error_report_err(local_err);
1611 error_free(invtsc_mig_blocker);
0c2ed83f 1612 return r;
fe44dc91 1613 }
d99569d9 1614 }
68bfd0ad
MT		 1615 }
1616
9954a158
PDJ		 1617 if (cpu->vmware_cpuid_freq
1618 /* Guests depend on 0x40000000 to detect this feature, so only expose
1619 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1620 && cpu->expose_kvm
1621 && kvm_base == KVM_CPUID_SIGNATURE
1622 /* TSC clock must be stable and known for this feature. */
4bb95b82 1623 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1624
1625 c = &cpuid_data.entries[cpuid_i++];
1626 c->function = KVM_CPUID_SIGNATURE | 0x10;
1627 c->eax = env->tsc_khz;
1628 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1629 * APIC_BUS_CYCLE_NS */
1630 c->ebx = 1000000;
1631 c->ecx = c->edx = 0;
1632
1633 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1634 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1635 }
1636
1637 cpuid_data.cpuid.nent = cpuid_i;
1638
1639 cpuid_data.cpuid.padding = 0;
1640 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1641 if (r) {
1642 goto fail;
1643 }
1644
28143b40 1645 if (has_xsave) {
5b8063c4 1646 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1647 }
d71b62a1 1648 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1649
273c515c
PB		 1650 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1651 has_msr_tsc_aux = false;
1652 }
d1ae67f6 1653
e9688fab
RK		 1654 r = hyperv_init_vcpu(cpu);
1655 if (r) {
1656 goto fail;
1657 }
1658
e7429073 1659 return 0;
fe44dc91
AA		 1660
1661 fail:
1662 migrate_del_blocker(invtsc_mig_blocker);
1663 return r;
05330448
AL		 1664}
1665
50a2c6e5 1666void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1667{
20d695a9 1668 CPUX86State *env = &cpu->env;
dd673288 1669
1a5e9d2f 1670 env->xcr0 = 1;
ddced198 1671 if (kvm_irqchip_in_kernel()) {
dd673288 1672 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1673 KVM_MP_STATE_UNINITIALIZED;
1674 } else {
1675 env->mp_state = KVM_MP_STATE_RUNNABLE;
1676 }
689141dd 1677
2d384d7c 1678 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1679 int i;
1680 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1681 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1682 }
606c34bf
RK		 1683
1684 hyperv_x86_synic_reset(cpu);
689141dd 1685 }
caa5af0f
JK		 1686}
1687
e0723c45
PB		 1688void kvm_arch_do_init_vcpu(X86CPU *cpu)
1689{
1690 CPUX86State *env = &cpu->env;
1691
1692 /* APs get directly into wait-for-SIPI state. */
1693 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1694 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1695 }
1696}
1697
f57bceb6
RH		 1698static int kvm_get_supported_feature_msrs(KVMState *s)
1699{
1700 int ret = 0;
1701
1702 if (kvm_feature_msrs != NULL) {
1703 return 0;
1704 }
1705
1706 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1707 return 0;
1708 }
1709
1710 struct kvm_msr_list msr_list;
1711
1712 msr_list.nmsrs = 0;
1713 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1714 if (ret < 0 && ret != -E2BIG) {
1715 error_report("Fetch KVM feature MSR list failed: %s",
1716 strerror(-ret));
1717 return ret;
1718 }
1719
1720 assert(msr_list.nmsrs > 0);
1721 kvm_feature_msrs = (struct kvm_msr_list *) \
1722 g_malloc0(sizeof(msr_list) +
1723 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1724
1725 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1726 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1727
1728 if (ret < 0) {
1729 error_report("Fetch KVM feature MSR list failed: %s",
1730 strerror(-ret));
1731 g_free(kvm_feature_msrs);
1732 kvm_feature_msrs = NULL;
1733 return ret;
1734 }
1735
1736 return 0;
1737}
1738
c3a3a7d3 1739static int kvm_get_supported_msrs(KVMState *s)
05330448 1740{
75b10c43 1741 static int kvm_supported_msrs;
c3a3a7d3 1742 int ret = 0;
05330448
AL		 1743
1744 /* first time */
75b10c43 1745 if (kvm_supported_msrs == 0) {
05330448
AL		 1746 struct kvm_msr_list msr_list, *kvm_msr_list;
1747
75b10c43 1748 kvm_supported_msrs = -1;
05330448
AL		 1749
1750 /* Obtain MSR list from KVM. These are the MSRs that we must
1751 * save/restore */
4c9f7372 1752 msr_list.nmsrs = 0;
c3a3a7d3 1753 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1754 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1755 return ret;
6fb6d245 1756 }
d9db889f
JK		 1757 /* Old kernel modules had a bug and could write beyond the provided
1758 memory. Allocate at least a safe amount of 1K. */
7267c094 1759 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1760 msr_list.nmsrs *
1761 sizeof(msr_list.indices[0])));
05330448 1762
55308450 1763 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1764 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1765 if (ret >= 0) {
1766 int i;
1767
1768 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1769 switch (kvm_msr_list->indices[i]) {
1770 case MSR_STAR:
c3a3a7d3 1771 has_msr_star = true;
1d268dec
LP		 1772 break;
1773 case MSR_VM_HSAVE_PA:
c3a3a7d3 1774 has_msr_hsave_pa = true;
1d268dec
LP		 1775 break;
1776 case MSR_TSC_AUX:
c9b8f6b6 1777 has_msr_tsc_aux = true;
1d268dec
LP		 1778 break;
1779 case MSR_TSC_ADJUST:
f28558d3 1780 has_msr_tsc_adjust = true;
1d268dec
LP		 1781 break;
1782 case MSR_IA32_TSCDEADLINE:
aa82ba54 1783 has_msr_tsc_deadline = true;
1d268dec
LP		 1784 break;
1785 case MSR_IA32_SMBASE:
fc12d72e 1786 has_msr_smbase = true;
1d268dec 1787 break;
e13713db
LA		 1788 case MSR_SMI_COUNT:
1789 has_msr_smi_count = true;
1790 break;
1d268dec 1791 case MSR_IA32_MISC_ENABLE:
21e87c46 1792 has_msr_misc_enable = true;
1d268dec
LP		 1793 break;
1794 case MSR_IA32_BNDCFGS:
79e9ebeb 1795 has_msr_bndcfgs = true;
1d268dec
LP		 1796 break;
1797 case MSR_IA32_XSS:
18cd2c17 1798 has_msr_xss = true;
3c254ab8 1799 break;
1d268dec 1800 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1801 has_msr_hv_crash = true;
1d268dec
LP		 1802 break;
1803 case HV_X64_MSR_RESET:
744b8a94 1804 has_msr_hv_reset = true;
1d268dec
LP		 1805 break;
1806 case HV_X64_MSR_VP_INDEX:
8c145d7c 1807 has_msr_hv_vpindex = true;
1d268dec
LP		 1808 break;
1809 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1810 has_msr_hv_runtime = true;
1d268dec
LP		 1811 break;
1812 case HV_X64_MSR_SCONTROL:
866eea9a 1813 has_msr_hv_synic = true;
1d268dec
LP		 1814 break;
1815 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1816 has_msr_hv_stimer = true;
1d268dec 1817 break;
d72bc7f6
LP		 1818 case HV_X64_MSR_TSC_FREQUENCY:
1819 has_msr_hv_frequencies = true;
1820 break;
ba6a4fd9
VK		 1821 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1822 has_msr_hv_reenlightenment = true;
1823 break;
a33a2cfe
PB		 1824 case MSR_IA32_SPEC_CTRL:
1825 has_msr_spec_ctrl = true;
1826 break;
cfeea0c0
KRW		 1827 case MSR_VIRT_SSBD:
1828 has_msr_virt_ssbd = true;
1829 break;
aec5e9c3
BD		 1830 case MSR_IA32_ARCH_CAPABILITIES:
1831 has_msr_arch_capabs = true;
1832 break;
ff99aa64 1833 }
05330448
AL		 1834 }
1835 }
1836
7267c094 1837 g_free(kvm_msr_list);
05330448
AL		 1838 }
1839
c3a3a7d3 1840 return ret;
05330448
AL		 1841}
1842
6410848b
PB		 1843static Notifier smram_machine_done;
1844static KVMMemoryListener smram_listener;
1845static AddressSpace smram_address_space;
1846static MemoryRegion smram_as_root;
1847static MemoryRegion smram_as_mem;
1848
1849static void register_smram_listener(Notifier *n, void *unused)
1850{
1851 MemoryRegion *smram =
1852 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1853
1854 /* Outer container... */
1855 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1856 memory_region_set_enabled(&smram_as_root, true);
1857
1858 /* ... with two regions inside: normal system memory with low
1859 * priority, and...
1860 */
1861 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1862 get_system_memory(), 0, ~0ull);
1863 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1864 memory_region_set_enabled(&smram_as_mem, true);
1865
1866 if (smram) {
1867 /* ... SMRAM with higher priority */
1868 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1869 memory_region_set_enabled(smram, true);
1870 }
1871
1872 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1873 kvm_memory_listener_register(kvm_state, &smram_listener,
1874 &smram_address_space, 1);
1875}
1876
b16565b3 1877int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1878{
11076198 1879 uint64_t identity_base = 0xfffbc000;
39d6960a 1880 uint64_t shadow_mem;
20420430 1881 int ret;
25d2e361 1882 struct utsname utsname;
20420430 1883
28143b40 1884 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1885 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1886 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1887
e9688fab
RK		 1888 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1889
c3a3a7d3 1890 ret = kvm_get_supported_msrs(s);
20420430 1891 if (ret < 0) {
20420430
SY		 1892 return ret;
1893 }
25d2e361 1894
f57bceb6
RH		 1895 kvm_get_supported_feature_msrs(s);
1896
25d2e361
MT		 1897 uname(&utsname);
1898 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1899
4c5b10b7 1900 /*
11076198
JK		 1901 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1902 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1903 * Since these must be part of guest physical memory, we need to allocate
1904 * them, both by setting their start addresses in the kernel and by
1905 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1906 *
1907 * Older KVM versions may not support setting the identity map base. In
1908 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1909 * size.
4c5b10b7 1910 */
11076198
JK		 1911 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1912 /* Allows up to 16M BIOSes. */
1913 identity_base = 0xfeffc000;
1914
1915 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1916 if (ret < 0) {
1917 return ret;
1918 }
4c5b10b7 1919 }
e56ff191 1920
11076198
JK		 1921 /* Set TSS base one page after EPT identity map. */
1922 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1923 if (ret < 0) {
1924 return ret;
1925 }
1926
11076198
JK		 1927 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1928 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1929 if (ret < 0) {
11076198 1930 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1931 return ret;
1932 }
3c85e74f 1933 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1934
4689b77b 1935 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1936 if (shadow_mem != -1) {
1937 shadow_mem /= 4096;
1938 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1939 if (ret < 0) {
1940 return ret;
39d6960a
JK		 1941 }
1942 }
6410848b 1943
d870cfde
GA		 1944 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1945 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1946 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1947 smram_machine_done.notify = register_smram_listener;
1948 qemu_add_machine_init_done_notifier(&smram_machine_done);
1949 }
6f131f13
MT		 1950
1951 if (enable_cpu_pm) {
1952 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1953 int ret;
1954
1955/* Work around for kernel header with a typo. TODO: fix header and drop. */
1956#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1957#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1958#endif
1959 if (disable_exits) {
1960 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1961 KVM_X86_DISABLE_EXITS_HLT |
1962 KVM_X86_DISABLE_EXITS_PAUSE);
1963 }
1964
1965 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1966 disable_exits);
1967 if (ret < 0) {
1968 error_report("kvm: guest stopping CPU not supported: %s",
1969 strerror(-ret));
1970 }
1971 }
1972
11076198 1973 return 0;
05330448 1974}
b9bec74b 1975
05330448
AL		 1976static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1977{
1978 lhs->selector = rhs->selector;
1979 lhs->base = rhs->base;
1980 lhs->limit = rhs->limit;
1981 lhs->type = 3;
1982 lhs->present = 1;
1983 lhs->dpl = 3;
1984 lhs->db = 0;
1985 lhs->s = 1;
1986 lhs->l = 0;
1987 lhs->g = 0;
1988 lhs->avl = 0;
1989 lhs->unusable = 0;
1990}
1991
1992static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1993{
1994 unsigned flags = rhs->flags;
1995 lhs->selector = rhs->selector;
1996 lhs->base = rhs->base;
1997 lhs->limit = rhs->limit;
1998 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1999 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2000 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2001 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2002 lhs->s = (flags & DESC_S_MASK) != 0;
2003 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2004 lhs->g = (flags & DESC_G_MASK) != 0;
2005 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2006 lhs->unusable = !lhs->present;
7e680753 2007 lhs->padding = 0;
05330448
AL		 2008}
2009
2010static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2011{
2012 lhs->selector = rhs->selector;
2013 lhs->base = rhs->base;
2014 lhs->limit = rhs->limit;
d45fc087
RP		 2015 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2016 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2017 (rhs->dpl << DESC_DPL_SHIFT) |
2018 (rhs->db << DESC_B_SHIFT) |
2019 (rhs->s * DESC_S_MASK) |
2020 (rhs->l << DESC_L_SHIFT) |
2021 (rhs->g * DESC_G_MASK) |
2022 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2023}
2024
2025static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2026{
b9bec74b 2027 if (set) {
05330448 2028 *kvm_reg = *qemu_reg;
b9bec74b 2029 } else {
05330448 2030 *qemu_reg = *kvm_reg;
b9bec74b 2031 }
05330448
AL		 2032}
2033
1bc22652 2034static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2035{
1bc22652 2036 CPUX86State *env = &cpu->env;
05330448
AL		 2037 struct kvm_regs regs;
2038 int ret = 0;
2039
2040 if (!set) {
1bc22652 2041 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2042 if (ret < 0) {
05330448 2043 return ret;
b9bec74b 2044 }
05330448
AL		 2045 }
2046
2047 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2048 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2049 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2050 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2051 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2052 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2053 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2054 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2055#ifdef TARGET_X86_64
2056 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2057 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2058 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2059 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2060 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2061 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2062 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2063 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2064#endif
2065
2066 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2067 kvm_getput_reg(&regs.rip, &env->eip, set);
2068
b9bec74b 2069 if (set) {
1bc22652 2070 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2071 }
05330448
AL		 2072
2073 return ret;
2074}
2075
1bc22652 2076static int kvm_put_fpu(X86CPU *cpu)
05330448 2077{
1bc22652 2078 CPUX86State *env = &cpu->env;
05330448
AL		 2079 struct kvm_fpu fpu;
2080 int i;
2081
2082 memset(&fpu, 0, sizeof fpu);
2083 fpu.fsw = env->fpus & ~(7 << 11);
2084 fpu.fsw |= (env->fpstt & 7) << 11;
2085 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2086 fpu.last_opcode = env->fpop;
2087 fpu.last_ip = env->fpip;
2088 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2089 for (i = 0; i < 8; ++i) {
2090 fpu.ftwx |= (!env->fptags[i]) << i;
2091 }
05330448 2092 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2093 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2094 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2095 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2096 }
05330448
AL		 2097 fpu.mxcsr = env->mxcsr;
2098
1bc22652 2099 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2100}
2101
6b42494b
JK		 2102#define XSAVE_FCW_FSW 0
2103#define XSAVE_FTW_FOP 1
f1665b21
SY		 2104#define XSAVE_CWD_RIP 2
2105#define XSAVE_CWD_RDP 4
2106#define XSAVE_MXCSR 6
2107#define XSAVE_ST_SPACE 8
2108#define XSAVE_XMM_SPACE 40
2109#define XSAVE_XSTATE_BV 128
2110#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2111#define XSAVE_BNDREGS 240
2112#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2113#define XSAVE_OPMASK 272
2114#define XSAVE_ZMM_Hi256 288
2115#define XSAVE_Hi16_ZMM 416
f74eefe0 2116#define XSAVE_PKRU 672
f1665b21 2117
b503717d 2118#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2119 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2120
2121#define ASSERT_OFFSET(word_offset, field) \
2122 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2123 offsetof(X86XSaveArea, field))
2124
2125ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2126ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2127ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2128ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2129ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2130ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2131ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2132ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2133ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2134ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2135ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2136ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2137ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2138ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2139ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2140
1bc22652 2141static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2142{
1bc22652 2143 CPUX86State *env = &cpu->env;
5b8063c4 2144 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2145
28143b40 2146 if (!has_xsave) {
1bc22652 2147 return kvm_put_fpu(cpu);
b9bec74b 2148 }
86a57621 2149 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2150
9be38598 2151 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2152}
2153
1bc22652 2154static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2155{
1bc22652 2156 CPUX86State *env = &cpu->env;
bdfc8480 2157 struct kvm_xcrs xcrs = {};
f1665b21 2158
28143b40 2159 if (!has_xcrs) {
f1665b21 2160 return 0;
b9bec74b 2161 }
f1665b21
SY		 2162
2163 xcrs.nr_xcrs = 1;
2164 xcrs.flags = 0;
2165 xcrs.xcrs[0].xcr = 0;
2166 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2167 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2168}
2169
1bc22652 2170static int kvm_put_sregs(X86CPU *cpu)
05330448 2171{
1bc22652 2172 CPUX86State *env = &cpu->env;
05330448
AL		 2173 struct kvm_sregs sregs;
2174
0e607a80
JK		 2175 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2176 if (env->interrupt_injected >= 0) {
2177 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2178 (uint64_t)1 << (env->interrupt_injected % 64);
2179 }
05330448
AL		 2180
2181 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2182 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2183 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2184 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2185 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2186 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2187 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2188 } else {
b9bec74b
JK		 2189 set_seg(&sregs.cs, &env->segs[R_CS]);
2190 set_seg(&sregs.ds, &env->segs[R_DS]);
2191 set_seg(&sregs.es, &env->segs[R_ES]);
2192 set_seg(&sregs.fs, &env->segs[R_FS]);
2193 set_seg(&sregs.gs, &env->segs[R_GS]);
2194 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2195 }
2196
2197 set_seg(&sregs.tr, &env->tr);
2198 set_seg(&sregs.ldt, &env->ldt);
2199
2200 sregs.idt.limit = env->idt.limit;
2201 sregs.idt.base = env->idt.base;
7e680753 2202 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2203 sregs.gdt.limit = env->gdt.limit;
2204 sregs.gdt.base = env->gdt.base;
7e680753 2205 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2206
2207 sregs.cr0 = env->cr[0];
2208 sregs.cr2 = env->cr[2];
2209 sregs.cr3 = env->cr[3];
2210 sregs.cr4 = env->cr[4];
2211
02e51483
CF		 2212 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2213 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2214
2215 sregs.efer = env->efer;
2216
1bc22652 2217 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2218}
2219
d71b62a1
EH		 2220static void kvm_msr_buf_reset(X86CPU *cpu)
2221{
2222 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2223}
2224
9c600a84
EH		 2225static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2226{
2227 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2228 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2229 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2230
2231 assert((void *)(entry + 1) <= limit);
2232
1abc2cae
EH		 2233 entry->index = index;
2234 entry->reserved = 0;
2235 entry->data = value;
9c600a84
EH		 2236 msrs->nmsrs++;
2237}
2238
73e1b8f2
PB		 2239static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2240{
2241 kvm_msr_buf_reset(cpu);
2242 kvm_msr_entry_add(cpu, index, value);
2243
2244 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2245}
2246
f8d9ccf8
DDAG		 2247void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2248{
2249 int ret;
2250
2251 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2252 assert(ret == 1);
2253}
2254
7477cd38
MT		 2255static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2256{
2257 CPUX86State *env = &cpu->env;
48e1a45c 2258 int ret;
7477cd38
MT		 2259
2260 if (!has_msr_tsc_deadline) {
2261 return 0;
2262 }
2263
73e1b8f2 2264 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2265 if (ret < 0) {
2266 return ret;
2267 }
2268
2269 assert(ret == 1);
2270 return 0;
7477cd38
MT		 2271}
2272
6bdf863d
JK		 2273/*
2274 * Provide a separate write service for the feature control MSR in order to
2275 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2276 * before writing any other state because forcibly leaving nested mode
2277 * invalidates the VCPU state.
2278 */
2279static int kvm_put_msr_feature_control(X86CPU *cpu)
2280{
48e1a45c
PB		 2281 int ret;
2282
2283 if (!has_msr_feature_control) {
2284 return 0;
2285 }
6bdf863d 2286
73e1b8f2
PB		 2287 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2288 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2289 if (ret < 0) {
2290 return ret;
2291 }
2292
2293 assert(ret == 1);
2294 return 0;
6bdf863d
JK		 2295}
2296
1bc22652 2297static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2298{
1bc22652 2299 CPUX86State *env = &cpu->env;
9c600a84 2300 int i;
48e1a45c 2301 int ret;
05330448 2302
d71b62a1
EH		 2303 kvm_msr_buf_reset(cpu);
2304
9c600a84
EH		 2305 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2306 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2307 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2308 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2309 if (has_msr_star) {
9c600a84 2310 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2311 }
c3a3a7d3 2312 if (has_msr_hsave_pa) {
9c600a84 2313 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2314 }
c9b8f6b6 2315 if (has_msr_tsc_aux) {
9c600a84 2316 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2317 }
f28558d3 2318 if (has_msr_tsc_adjust) {
9c600a84 2319 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2320 }
21e87c46 2321 if (has_msr_misc_enable) {
9c600a84 2322 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2323 env->msr_ia32_misc_enable);
2324 }
fc12d72e 2325 if (has_msr_smbase) {
9c600a84 2326 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2327 }
e13713db
LA		 2328 if (has_msr_smi_count) {
2329 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2330 }
439d19f2 2331 if (has_msr_bndcfgs) {
9c600a84 2332 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2333 }
18cd2c17 2334 if (has_msr_xss) {
9c600a84 2335 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2336 }
a33a2cfe
PB		 2337 if (has_msr_spec_ctrl) {
2338 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2339 }
cfeea0c0
KRW		 2340 if (has_msr_virt_ssbd) {
2341 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2342 }
2343
05330448 2344#ifdef TARGET_X86_64
25d2e361 2345 if (lm_capable_kernel) {
9c600a84
EH		 2346 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2347 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2348 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2349 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2350 }
05330448 2351#endif
a33a2cfe 2352
d86f9636 2353 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2354 if (has_msr_arch_capabs) {
2355 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2356 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2357 }
2358
ff5c186b 2359 /*
0d894367
PB		 2360 * The following MSRs have side effects on the guest or are too heavy
2361 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2362 */
2363 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2364 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2365 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2366 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2367 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2368 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2369 }
55c911a5 2370 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2371 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2372 }
55c911a5 2373 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2374 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2375 }
0b368a10
JD		 2376 if (has_architectural_pmu_version > 0) {
2377 if (has_architectural_pmu_version > 1) {
2378 /* Stop the counter. */
2379 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2380 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2381 }
0d894367
PB		 2382
2383 /* Set the counter values. */
0b368a10 2384 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2385 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2386 env->msr_fixed_counters[i]);
2387 }
0b368a10 2388 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2389 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2390 env->msr_gp_counters[i]);
9c600a84 2391 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2392 env->msr_gp_evtsel[i]);
2393 }
0b368a10
JD		 2394 if (has_architectural_pmu_version > 1) {
2395 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2396 env->msr_global_status);
2397 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2398 env->msr_global_ovf_ctrl);
2399
2400 /* Now start the PMU. */
2401 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2402 env->msr_fixed_ctr_ctrl);
2403 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2404 env->msr_global_ctrl);
2405 }
0d894367 2406 }
da1cc323
EY		 2407 /*
2408 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2409 * only sync them to KVM on the first cpu
2410 */
2411 if (current_cpu == first_cpu) {
2412 if (has_msr_hv_hypercall) {
2413 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2414 env->msr_hv_guest_os_id);
2415 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2416 env->msr_hv_hypercall);
2417 }
2d384d7c 2418 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2419 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2420 env->msr_hv_tsc);
2421 }
2d384d7c 2422 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2423 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2424 env->msr_hv_reenlightenment_control);
2425 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2426 env->msr_hv_tsc_emulation_control);
2427 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2428 env->msr_hv_tsc_emulation_status);
2429 }
eab70139 2430 }
2d384d7c 2431 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2432 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2433 env->msr_hv_vapic);
eab70139 2434 }
f2a53c9e
AS		 2435 if (has_msr_hv_crash) {
2436 int j;
2437
5e953812 2438 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2439 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2440 env->msr_hv_crash_params[j]);
2441
5e953812 2442 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2443 }
46eb8f98 2444 if (has_msr_hv_runtime) {
9c600a84 2445 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2446 }
2d384d7c
VK		 2447 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2448 && hv_vpindex_settable) {
701189e3
RK		 2449 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2450 hyperv_vp_index(CPU(cpu)));
e9688fab 2451 }
2d384d7c 2452 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2453 int j;
2454
09df29b6
RK		 2455 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2456
9c600a84 2457 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2458 env->msr_hv_synic_control);
9c600a84 2459 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2460 env->msr_hv_synic_evt_page);
9c600a84 2461 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2462 env->msr_hv_synic_msg_page);
2463
2464 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2465 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2466 env->msr_hv_synic_sint[j]);
2467 }
2468 }
ff99aa64
AS		 2469 if (has_msr_hv_stimer) {
2470 int j;
2471
2472 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2473 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2474 env->msr_hv_stimer_config[j]);
2475 }
2476
2477 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2478 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2479 env->msr_hv_stimer_count[j]);
2480 }
2481 }
1eabfce6 2482 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2483 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2484
9c600a84
EH		 2485 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2486 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2487 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2488 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2489 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2490 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2491 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2492 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2493 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2494 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2495 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2496 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2497 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2498 /* The CPU GPs if we write to a bit above the physical limit of
2499 * the host CPU (and KVM emulates that)
2500 */
2501 uint64_t mask = env->mtrr_var[i].mask;
2502 mask &= phys_mask;
2503
9c600a84
EH		 2504 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2505 env->mtrr_var[i].base);
112dad69 2506 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2507 }
2508 }
b77146e9
CP		 2509 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2510 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2511 0x14, 1, R_EAX) & 0x7;
2512
2513 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2514 env->msr_rtit_ctrl);
2515 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2516 env->msr_rtit_status);
2517 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2518 env->msr_rtit_output_base);
2519 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2520 env->msr_rtit_output_mask);
2521 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2522 env->msr_rtit_cr3_match);
2523 for (i = 0; i < addr_num; i++) {
2524 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2525 env->msr_rtit_addrs[i]);
2526 }
2527 }
6bdf863d
JK		 2528
2529 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2530 * kvm_put_msr_feature_control. */
ea643051 2531 }
57780495 2532 if (env->mcg_cap) {
d8da8574 2533 int i;
b9bec74b 2534
9c600a84
EH		 2535 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2536 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2537 if (has_msr_mcg_ext_ctl) {
2538 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2539 }
c34d440a 2540 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2541 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2542 }
2543 }
1a03675d 2544
d71b62a1 2545 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2546 if (ret < 0) {
2547 return ret;
2548 }
05330448 2549
c70b11d1
EH		 2550 if (ret < cpu->kvm_msr_buf->nmsrs) {
2551 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2552 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2553 (uint32_t)e->index, (uint64_t)e->data);
2554 }
2555
9c600a84 2556 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2557 return 0;
05330448
AL		 2558}
2559
2560
1bc22652 2561static int kvm_get_fpu(X86CPU *cpu)
05330448 2562{
1bc22652 2563 CPUX86State *env = &cpu->env;
05330448
AL		 2564 struct kvm_fpu fpu;
2565 int i, ret;
2566
1bc22652 2567 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2568 if (ret < 0) {
05330448 2569 return ret;
b9bec74b 2570 }
05330448
AL		 2571
2572 env->fpstt = (fpu.fsw >> 11) & 7;
2573 env->fpus = fpu.fsw;
2574 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2575 env->fpop = fpu.last_opcode;
2576 env->fpip = fpu.last_ip;
2577 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2578 for (i = 0; i < 8; ++i) {
2579 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2580 }
05330448 2581 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2582 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2583 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2584 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2585 }
05330448
AL		 2586 env->mxcsr = fpu.mxcsr;
2587
2588 return 0;
2589}
2590
1bc22652 2591static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2592{
1bc22652 2593 CPUX86State *env = &cpu->env;
5b8063c4 2594 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2595 int ret;
f1665b21 2596
28143b40 2597 if (!has_xsave) {
1bc22652 2598 return kvm_get_fpu(cpu);
b9bec74b 2599 }
f1665b21 2600
1bc22652 2601 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2602 if (ret < 0) {
f1665b21 2603 return ret;
0f53994f 2604 }
86a57621 2605 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2606
f1665b21 2607 return 0;
f1665b21
SY		 2608}
2609
1bc22652 2610static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2611{
1bc22652 2612 CPUX86State *env = &cpu->env;
f1665b21
SY		 2613 int i, ret;
2614 struct kvm_xcrs xcrs;
2615
28143b40 2616 if (!has_xcrs) {
f1665b21 2617 return 0;
b9bec74b 2618 }
f1665b21 2619
1bc22652 2620 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2621 if (ret < 0) {
f1665b21 2622 return ret;
b9bec74b 2623 }
f1665b21 2624
b9bec74b 2625 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2626 /* Only support xcr0 now */
0fd53fec
PB		 2627 if (xcrs.xcrs[i].xcr == 0) {
2628 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2629 break;
2630 }
b9bec74b 2631 }
f1665b21 2632 return 0;
f1665b21
SY		 2633}
2634
1bc22652 2635static int kvm_get_sregs(X86CPU *cpu)
05330448 2636{
1bc22652 2637 CPUX86State *env = &cpu->env;
05330448 2638 struct kvm_sregs sregs;
0e607a80 2639 int bit, i, ret;
05330448 2640
1bc22652 2641 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2642 if (ret < 0) {
05330448 2643 return ret;
b9bec74b 2644 }
05330448 2645
0e607a80
JK		 2646 /* There can only be one pending IRQ set in the bitmap at a time, so try
2647 to find it and save its number instead (-1 for none). */
2648 env->interrupt_injected = -1;
2649 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2650 if (sregs.interrupt_bitmap[i]) {
2651 bit = ctz64(sregs.interrupt_bitmap[i]);
2652 env->interrupt_injected = i * 64 + bit;
2653 break;
2654 }
2655 }
05330448
AL		 2656
2657 get_seg(&env->segs[R_CS], &sregs.cs);
2658 get_seg(&env->segs[R_DS], &sregs.ds);
2659 get_seg(&env->segs[R_ES], &sregs.es);
2660 get_seg(&env->segs[R_FS], &sregs.fs);
2661 get_seg(&env->segs[R_GS], &sregs.gs);
2662 get_seg(&env->segs[R_SS], &sregs.ss);
2663
2664 get_seg(&env->tr, &sregs.tr);
2665 get_seg(&env->ldt, &sregs.ldt);
2666
2667 env->idt.limit = sregs.idt.limit;
2668 env->idt.base = sregs.idt.base;
2669 env->gdt.limit = sregs.gdt.limit;
2670 env->gdt.base = sregs.gdt.base;
2671
2672 env->cr[0] = sregs.cr0;
2673 env->cr[2] = sregs.cr2;
2674 env->cr[3] = sregs.cr3;
2675 env->cr[4] = sregs.cr4;
2676
05330448 2677 env->efer = sregs.efer;
cce47516
JK		 2678
2679 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2680 x86_update_hflags(env);
05330448
AL		 2681
2682 return 0;
2683}
2684
1bc22652 2685static int kvm_get_msrs(X86CPU *cpu)
05330448 2686{
1bc22652 2687 CPUX86State *env = &cpu->env;
d71b62a1 2688 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2689 int ret, i;
fcc35e7c 2690 uint64_t mtrr_top_bits;
05330448 2691
d71b62a1
EH		 2692 kvm_msr_buf_reset(cpu);
2693
9c600a84
EH		 2694 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2695 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2696 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2697 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2698 if (has_msr_star) {
9c600a84 2699 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2700 }
c3a3a7d3 2701 if (has_msr_hsave_pa) {
9c600a84 2702 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2703 }
c9b8f6b6 2704 if (has_msr_tsc_aux) {
9c600a84 2705 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2706 }
f28558d3 2707 if (has_msr_tsc_adjust) {
9c600a84 2708 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2709 }
aa82ba54 2710 if (has_msr_tsc_deadline) {
9c600a84 2711 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2712 }
21e87c46 2713 if (has_msr_misc_enable) {
9c600a84 2714 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2715 }
fc12d72e 2716 if (has_msr_smbase) {
9c600a84 2717 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2718 }
e13713db
LA		 2719 if (has_msr_smi_count) {
2720 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2721 }
df67696e 2722 if (has_msr_feature_control) {
9c600a84 2723 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2724 }
79e9ebeb 2725 if (has_msr_bndcfgs) {
9c600a84 2726 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2727 }
18cd2c17 2728 if (has_msr_xss) {
9c600a84 2729 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2730 }
a33a2cfe
PB		 2731 if (has_msr_spec_ctrl) {
2732 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2733 }
cfeea0c0
KRW		 2734 if (has_msr_virt_ssbd) {
2735 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2736 }
b8cc45d6 2737 if (!env->tsc_valid) {
9c600a84 2738 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2739 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2740 }
2741
05330448 2742#ifdef TARGET_X86_64
25d2e361 2743 if (lm_capable_kernel) {
9c600a84
EH		 2744 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2745 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2746 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2747 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2748 }
05330448 2749#endif
9c600a84
EH		 2750 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2751 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2752 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2753 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2754 }
55c911a5 2755 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2756 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2757 }
55c911a5 2758 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2759 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2760 }
0b368a10
JD		 2761 if (has_architectural_pmu_version > 0) {
2762 if (has_architectural_pmu_version > 1) {
2763 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2764 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2765 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2766 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2767 }
2768 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2769 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2770 }
0b368a10 2771 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2772 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2773 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2774 }
2775 }
1a03675d 2776
57780495 2777 if (env->mcg_cap) {
9c600a84
EH		 2778 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2779 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2780 if (has_msr_mcg_ext_ctl) {
2781 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2782 }
b9bec74b 2783 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2784 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2785 }
57780495 2786 }
57780495 2787
1c90ef26 2788 if (has_msr_hv_hypercall) {
9c600a84
EH		 2789 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2790 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2791 }
2d384d7c 2792 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2793 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2794 }
2d384d7c 2795 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2796 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2797 }
2d384d7c 2798 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2799 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2800 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2801 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2802 }
f2a53c9e
AS		 2803 if (has_msr_hv_crash) {
2804 int j;
2805
5e953812 2806 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2807 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2808 }
2809 }
46eb8f98 2810 if (has_msr_hv_runtime) {
9c600a84 2811 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2812 }
2d384d7c 2813 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2814 uint32_t msr;
2815
9c600a84 2816 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2817 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2818 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2819 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2820 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2821 }
2822 }
ff99aa64
AS		 2823 if (has_msr_hv_stimer) {
2824 uint32_t msr;
2825
2826 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2827 msr++) {
9c600a84 2828 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2829 }
2830 }
1eabfce6 2831 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2832 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2833 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2834 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2835 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2836 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2837 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2838 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2839 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2840 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2841 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2842 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2843 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2844 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2845 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2846 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2847 }
2848 }
5ef68987 2849
b77146e9
CP		 2850 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2851 int addr_num =
2852 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2853
2854 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2855 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2856 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2857 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2858 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2859 for (i = 0; i < addr_num; i++) {
2860 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2861 }
2862 }
2863
d71b62a1 2864 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2865 if (ret < 0) {
05330448 2866 return ret;
b9bec74b 2867 }
05330448 2868
c70b11d1
EH		 2869 if (ret < cpu->kvm_msr_buf->nmsrs) {
2870 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2871 error_report("error: failed to get MSR 0x%" PRIx32,
2872 (uint32_t)e->index);
2873 }
2874
9c600a84 2875 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2876 /*
2877 * MTRR masks: Each mask consists of 5 parts
2878 * a 10..0: must be zero
2879 * b 11 : valid bit
2880 * c n-1.12: actual mask bits
2881 * d 51..n: reserved must be zero
2882 * e 63.52: reserved must be zero
2883 *
2884 * 'n' is the number of physical bits supported by the CPU and is
2885 * apparently always <= 52. We know our 'n' but don't know what
2886 * the destinations 'n' is; it might be smaller, in which case
2887 * it masks (c) on loading. It might be larger, in which case
2888 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2889 * we're migrating to.
2890 */
2891
2892 if (cpu->fill_mtrr_mask) {
2893 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2894 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2895 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2896 } else {
2897 mtrr_top_bits = 0;
2898 }
2899
05330448 2900 for (i = 0; i < ret; i++) {
0d894367
PB		 2901 uint32_t index = msrs[i].index;
2902 switch (index) {
05330448
AL		 2903 case MSR_IA32_SYSENTER_CS:
2904 env->sysenter_cs = msrs[i].data;
2905 break;
2906 case MSR_IA32_SYSENTER_ESP:
2907 env->sysenter_esp = msrs[i].data;
2908 break;
2909 case MSR_IA32_SYSENTER_EIP:
2910 env->sysenter_eip = msrs[i].data;
2911 break;
0c03266a
JK		 2912 case MSR_PAT:
2913 env->pat = msrs[i].data;
2914 break;
05330448
AL		 2915 case MSR_STAR:
2916 env->star = msrs[i].data;
2917 break;
2918#ifdef TARGET_X86_64
2919 case MSR_CSTAR:
2920 env->cstar = msrs[i].data;
2921 break;
2922 case MSR_KERNELGSBASE:
2923 env->kernelgsbase = msrs[i].data;
2924 break;
2925 case MSR_FMASK:
2926 env->fmask = msrs[i].data;
2927 break;
2928 case MSR_LSTAR:
2929 env->lstar = msrs[i].data;
2930 break;
2931#endif
2932 case MSR_IA32_TSC:
2933 env->tsc = msrs[i].data;
2934 break;
c9b8f6b6
AS		 2935 case MSR_TSC_AUX:
2936 env->tsc_aux = msrs[i].data;
2937 break;
f28558d3
WA		 2938 case MSR_TSC_ADJUST:
2939 env->tsc_adjust = msrs[i].data;
2940 break;
aa82ba54
LJ		 2941 case MSR_IA32_TSCDEADLINE:
2942 env->tsc_deadline = msrs[i].data;
2943 break;
aa851e36
MT		 2944 case MSR_VM_HSAVE_PA:
2945 env->vm_hsave = msrs[i].data;
2946 break;
1a03675d
GC		 2947 case MSR_KVM_SYSTEM_TIME:
2948 env->system_time_msr = msrs[i].data;
2949 break;
2950 case MSR_KVM_WALL_CLOCK:
2951 env->wall_clock_msr = msrs[i].data;
2952 break;
57780495
MT		 2953 case MSR_MCG_STATUS:
2954 env->mcg_status = msrs[i].data;
2955 break;
2956 case MSR_MCG_CTL:
2957 env->mcg_ctl = msrs[i].data;
2958 break;
87f8b626
AR		 2959 case MSR_MCG_EXT_CTL:
2960 env->mcg_ext_ctl = msrs[i].data;
2961 break;
21e87c46
AK		 2962 case MSR_IA32_MISC_ENABLE:
2963 env->msr_ia32_misc_enable = msrs[i].data;
2964 break;
fc12d72e
PB		 2965 case MSR_IA32_SMBASE:
2966 env->smbase = msrs[i].data;
2967 break;
e13713db
LA		 2968 case MSR_SMI_COUNT:
2969 env->msr_smi_count = msrs[i].data;
2970 break;
0779caeb
ACL		 2971 case MSR_IA32_FEATURE_CONTROL:
2972 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2973 break;
79e9ebeb
LJ		 2974 case MSR_IA32_BNDCFGS:
2975 env->msr_bndcfgs = msrs[i].data;
2976 break;
18cd2c17
WL		 2977 case MSR_IA32_XSS:
2978 env->xss = msrs[i].data;
2979 break;
57780495 2980 default:
57780495
MT		 2981 if (msrs[i].index >= MSR_MC0_CTL &&
2982 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2983 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2984 }
d8da8574 2985 break;
f6584ee2
GN		 2986 case MSR_KVM_ASYNC_PF_EN:
2987 env->async_pf_en_msr = msrs[i].data;
2988 break;
bc9a839d
MT		 2989 case MSR_KVM_PV_EOI_EN:
2990 env->pv_eoi_en_msr = msrs[i].data;
2991 break;
917367aa
MT		 2992 case MSR_KVM_STEAL_TIME:
2993 env->steal_time_msr = msrs[i].data;
2994 break;
0d894367
PB		 2995 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2996 env->msr_fixed_ctr_ctrl = msrs[i].data;
2997 break;
2998 case MSR_CORE_PERF_GLOBAL_CTRL:
2999 env->msr_global_ctrl = msrs[i].data;
3000 break;
3001 case MSR_CORE_PERF_GLOBAL_STATUS:
3002 env->msr_global_status = msrs[i].data;
3003 break;
3004 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3005 env->msr_global_ovf_ctrl = msrs[i].data;
3006 break;
3007 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3008 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3009 break;
3010 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3011 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3012 break;
3013 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3014 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3015 break;
1c90ef26
VR		 3016 case HV_X64_MSR_HYPERCALL:
3017 env->msr_hv_hypercall = msrs[i].data;
3018 break;
3019 case HV_X64_MSR_GUEST_OS_ID:
3020 env->msr_hv_guest_os_id = msrs[i].data;
3021 break;
5ef68987
VR		 3022 case HV_X64_MSR_APIC_ASSIST_PAGE:
3023 env->msr_hv_vapic = msrs[i].data;
3024 break;
48a5f3bc
VR		 3025 case HV_X64_MSR_REFERENCE_TSC:
3026 env->msr_hv_tsc = msrs[i].data;
3027 break;
f2a53c9e
AS		 3028 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3029 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3030 break;
46eb8f98
AS		 3031 case HV_X64_MSR_VP_RUNTIME:
3032 env->msr_hv_runtime = msrs[i].data;
3033 break;
866eea9a
AS		 3034 case HV_X64_MSR_SCONTROL:
3035 env->msr_hv_synic_control = msrs[i].data;
3036 break;
866eea9a
AS		 3037 case HV_X64_MSR_SIEFP:
3038 env->msr_hv_synic_evt_page = msrs[i].data;
3039 break;
3040 case HV_X64_MSR_SIMP:
3041 env->msr_hv_synic_msg_page = msrs[i].data;
3042 break;
3043 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3044 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3045 break;
3046 case HV_X64_MSR_STIMER0_CONFIG:
3047 case HV_X64_MSR_STIMER1_CONFIG:
3048 case HV_X64_MSR_STIMER2_CONFIG:
3049 case HV_X64_MSR_STIMER3_CONFIG:
3050 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3051 msrs[i].data;
3052 break;
3053 case HV_X64_MSR_STIMER0_COUNT:
3054 case HV_X64_MSR_STIMER1_COUNT:
3055 case HV_X64_MSR_STIMER2_COUNT:
3056 case HV_X64_MSR_STIMER3_COUNT:
3057 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3058 msrs[i].data;
866eea9a 3059 break;
ba6a4fd9
VK		 3060 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3061 env->msr_hv_reenlightenment_control = msrs[i].data;
3062 break;
3063 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3064 env->msr_hv_tsc_emulation_control = msrs[i].data;
3065 break;
3066 case HV_X64_MSR_TSC_EMULATION_STATUS:
3067 env->msr_hv_tsc_emulation_status = msrs[i].data;
3068 break;
d1ae67f6
AW		 3069 case MSR_MTRRdefType:
3070 env->mtrr_deftype = msrs[i].data;
3071 break;
3072 case MSR_MTRRfix64K_00000:
3073 env->mtrr_fixed[0] = msrs[i].data;
3074 break;
3075 case MSR_MTRRfix16K_80000:
3076 env->mtrr_fixed[1] = msrs[i].data;
3077 break;
3078 case MSR_MTRRfix16K_A0000:
3079 env->mtrr_fixed[2] = msrs[i].data;
3080 break;
3081 case MSR_MTRRfix4K_C0000:
3082 env->mtrr_fixed[3] = msrs[i].data;
3083 break;
3084 case MSR_MTRRfix4K_C8000:
3085 env->mtrr_fixed[4] = msrs[i].data;
3086 break;
3087 case MSR_MTRRfix4K_D0000:
3088 env->mtrr_fixed[5] = msrs[i].data;
3089 break;
3090 case MSR_MTRRfix4K_D8000:
3091 env->mtrr_fixed[6] = msrs[i].data;
3092 break;
3093 case MSR_MTRRfix4K_E0000:
3094 env->mtrr_fixed[7] = msrs[i].data;
3095 break;
3096 case MSR_MTRRfix4K_E8000:
3097 env->mtrr_fixed[8] = msrs[i].data;
3098 break;
3099 case MSR_MTRRfix4K_F0000:
3100 env->mtrr_fixed[9] = msrs[i].data;
3101 break;
3102 case MSR_MTRRfix4K_F8000:
3103 env->mtrr_fixed[10] = msrs[i].data;
3104 break;
3105 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3106 if (index & 1) {
fcc35e7c
DDAG		 3107 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3108 mtrr_top_bits;
d1ae67f6
AW		 3109 } else {
3110 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3111 }
3112 break;
a33a2cfe
PB		 3113 case MSR_IA32_SPEC_CTRL:
3114 env->spec_ctrl = msrs[i].data;
3115 break;
cfeea0c0
KRW		 3116 case MSR_VIRT_SSBD:
3117 env->virt_ssbd = msrs[i].data;
3118 break;
b77146e9
CP		 3119 case MSR_IA32_RTIT_CTL:
3120 env->msr_rtit_ctrl = msrs[i].data;
3121 break;
3122 case MSR_IA32_RTIT_STATUS:
3123 env->msr_rtit_status = msrs[i].data;
3124 break;
3125 case MSR_IA32_RTIT_OUTPUT_BASE:
3126 env->msr_rtit_output_base = msrs[i].data;
3127 break;
3128 case MSR_IA32_RTIT_OUTPUT_MASK:
3129 env->msr_rtit_output_mask = msrs[i].data;
3130 break;
3131 case MSR_IA32_RTIT_CR3_MATCH:
3132 env->msr_rtit_cr3_match = msrs[i].data;
3133 break;
3134 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3135 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3136 break;
05330448
AL		 3137 }
3138 }
3139
3140 return 0;
3141}
3142
1bc22652 3143static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3144{
1bc22652 3145 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3146
1bc22652 3147 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3148}
3149
23d02d9b 3150static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3151{
259186a7 3152 CPUState *cs = CPU(cpu);
23d02d9b 3153 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3154 struct kvm_mp_state mp_state;
3155 int ret;
3156
259186a7 3157 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3158 if (ret < 0) {
3159 return ret;
3160 }
3161 env->mp_state = mp_state.mp_state;
c14750e8 3162 if (kvm_irqchip_in_kernel()) {
259186a7 3163 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3164 }
9bdbe550
HB		 3165 return 0;
3166}
3167
1bc22652 3168static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3169{
02e51483 3170 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3171 struct kvm_lapic_state kapic;
3172 int ret;
3173
3d4b2649 3174 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3175 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3176 if (ret < 0) {
3177 return ret;
3178 }
3179
3180 kvm_get_apic_state(apic, &kapic);
3181 }
3182 return 0;
3183}
3184
1bc22652 3185static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3186{
fc12d72e 3187 CPUState *cs = CPU(cpu);
1bc22652 3188 CPUX86State *env = &cpu->env;
076796f8 3189 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3190
3191 if (!kvm_has_vcpu_events()) {
3192 return 0;
3193 }
3194
31827373
JK		 3195 events.exception.injected = (env->exception_injected >= 0);
3196 events.exception.nr = env->exception_injected;
a0fb002c
JK		 3197 events.exception.has_error_code = env->has_error_code;
3198 events.exception.error_code = env->error_code;
3199
3200 events.interrupt.injected = (env->interrupt_injected >= 0);
3201 events.interrupt.nr = env->interrupt_injected;
3202 events.interrupt.soft = env->soft_interrupt;
3203
3204 events.nmi.injected = env->nmi_injected;
3205 events.nmi.pending = env->nmi_pending;
3206 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3207
3208 events.sipi_vector = env->sipi_vector;
68c6efe0 3209 events.flags = 0;
a0fb002c 3210
fc12d72e
PB		 3211 if (has_msr_smbase) {
3212 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3213 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3214 if (kvm_irqchip_in_kernel()) {
3215 /* As soon as these are moved to the kernel, remove them
3216 * from cs->interrupt_request.
3217 */
3218 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3219 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3220 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3221 } else {
3222 /* Keep these in cs->interrupt_request. */
3223 events.smi.pending = 0;
3224 events.smi.latched_init = 0;
3225 }
fc3a1fd7
DDAG		 3226 /* Stop SMI delivery on old machine types to avoid a reboot
3227 * on an inward migration of an old VM.
3228 */
3229 if (!cpu->kvm_no_smi_migration) {
3230 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3231 }
fc12d72e
PB		 3232 }
3233
ea643051 3234 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3235 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3236 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3237 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3238 }
ea643051 3239 }
aee028b9 3240
1bc22652 3241 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3242}
3243
1bc22652 3244static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3245{
1bc22652 3246 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3247 struct kvm_vcpu_events events;
3248 int ret;
3249
3250 if (!kvm_has_vcpu_events()) {
3251 return 0;
3252 }
3253
fc12d72e 3254 memset(&events, 0, sizeof(events));
1bc22652 3255 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3256 if (ret < 0) {
3257 return ret;
3258 }
31827373 3259 env->exception_injected =
a0fb002c
JK		 3260 events.exception.injected ? events.exception.nr : -1;
3261 env->has_error_code = events.exception.has_error_code;
3262 env->error_code = events.exception.error_code;
3263
3264 env->interrupt_injected =
3265 events.interrupt.injected ? events.interrupt.nr : -1;
3266 env->soft_interrupt = events.interrupt.soft;
3267
3268 env->nmi_injected = events.nmi.injected;
3269 env->nmi_pending = events.nmi.pending;
3270 if (events.nmi.masked) {
3271 env->hflags2 |= HF2_NMI_MASK;
3272 } else {
3273 env->hflags2 &= ~HF2_NMI_MASK;
3274 }
3275
fc12d72e
PB		 3276 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3277 if (events.smi.smm) {
3278 env->hflags |= HF_SMM_MASK;
3279 } else {
3280 env->hflags &= ~HF_SMM_MASK;
3281 }
3282 if (events.smi.pending) {
3283 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3284 } else {
3285 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3286 }
3287 if (events.smi.smm_inside_nmi) {
3288 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3289 } else {
3290 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3291 }
3292 if (events.smi.latched_init) {
3293 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3294 } else {
3295 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3296 }
3297 }
3298
a0fb002c 3299 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3300
3301 return 0;
3302}
3303
1bc22652 3304static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3305{
ed2803da 3306 CPUState *cs = CPU(cpu);
1bc22652 3307 CPUX86State *env = &cpu->env;
b0b1d690 3308 int ret = 0;
b0b1d690
JK		 3309 unsigned long reinject_trap = 0;
3310
3311 if (!kvm_has_vcpu_events()) {
3312 if (env->exception_injected == 1) {
3313 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3314 } else if (env->exception_injected == 3) {
3315 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3316 }
3317 env->exception_injected = -1;
3318 }
3319
3320 /*
3321 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3322 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3323 * by updating the debug state once again if single-stepping is on.
3324 * Another reason to call kvm_update_guest_debug here is a pending debug
3325 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3326 * reinject them via SET_GUEST_DEBUG.
3327 */
3328 if (reinject_trap ||
ed2803da 3329 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3330 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3331 }
b0b1d690
JK		 3332 return ret;
3333}
3334
1bc22652 3335static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3336{
1bc22652 3337 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3338 struct kvm_debugregs dbgregs;
3339 int i;
3340
3341 if (!kvm_has_debugregs()) {
3342 return 0;
3343 }
3344
3345 for (i = 0; i < 4; i++) {
3346 dbgregs.db[i] = env->dr[i];
3347 }
3348 dbgregs.dr6 = env->dr[6];
3349 dbgregs.dr7 = env->dr[7];
3350 dbgregs.flags = 0;
3351
1bc22652 3352 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3353}
3354
1bc22652 3355static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3356{
1bc22652 3357 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3358 struct kvm_debugregs dbgregs;
3359 int i, ret;
3360
3361 if (!kvm_has_debugregs()) {
3362 return 0;
3363 }
3364
1bc22652 3365 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3366 if (ret < 0) {
b9bec74b 3367 return ret;
ff44f1a3
JK		 3368 }
3369 for (i = 0; i < 4; i++) {
3370 env->dr[i] = dbgregs.db[i];
3371 }
3372 env->dr[4] = env->dr[6] = dbgregs.dr6;
3373 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3374
3375 return 0;
3376}
3377
20d695a9 3378int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3379{
20d695a9 3380 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3381 int ret;
3382
2fa45344 3383 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3384
48e1a45c 3385 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3386 ret = kvm_put_msr_feature_control(x86_cpu);
3387 if (ret < 0) {
3388 return ret;
3389 }
3390 }
3391
36f96c4b
HZ		 3392 if (level == KVM_PUT_FULL_STATE) {
3393 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3394 * because TSC frequency mismatch shouldn't abort migration,
3395 * unless the user explicitly asked for a more strict TSC
3396 * setting (e.g. using an explicit "tsc-freq" option).
3397 */
3398 kvm_arch_set_tsc_khz(cpu);
3399 }
3400
1bc22652 3401 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3402 if (ret < 0) {
05330448 3403 return ret;
b9bec74b 3404 }
1bc22652 3405 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3406 if (ret < 0) {
f1665b21 3407 return ret;
b9bec74b 3408 }
1bc22652 3409 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3410 if (ret < 0) {
05330448 3411 return ret;
b9bec74b 3412 }
1bc22652 3413 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3414 if (ret < 0) {
05330448 3415 return ret;
b9bec74b 3416 }
ab443475 3417 /* must be before kvm_put_msrs */
1bc22652 3418 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3419 if (ret < 0) {
3420 return ret;
3421 }
1bc22652 3422 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3423 if (ret < 0) {
05330448 3424 return ret;
b9bec74b 3425 }
4fadfa00
PH		 3426 ret = kvm_put_vcpu_events(x86_cpu, level);
3427 if (ret < 0) {
3428 return ret;
3429 }
ea643051 3430 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3431 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3432 if (ret < 0) {
680c1c6f
JK		 3433 return ret;
3434 }
ea643051 3435 }
7477cd38
MT		 3436
3437 ret = kvm_put_tscdeadline_msr(x86_cpu);
3438 if (ret < 0) {
3439 return ret;
3440 }
1bc22652 3441 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3442 if (ret < 0) {
b0b1d690 3443 return ret;
b9bec74b 3444 }
b0b1d690 3445 /* must be last */
1bc22652 3446 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3447 if (ret < 0) {
ff44f1a3 3448 return ret;
b9bec74b 3449 }
05330448
AL		 3450 return 0;
3451}
3452
20d695a9 3453int kvm_arch_get_registers(CPUState *cs)
05330448 3454{
20d695a9 3455 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3456 int ret;
3457
20d695a9 3458 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3459
4fadfa00 3460 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3461 if (ret < 0) {
f4f1110e 3462 goto out;
b9bec74b 3463 }
4fadfa00
PH		 3464 /*
3465 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3466 * KVM_GET_REGS and KVM_GET_SREGS.
3467 */
3468 ret = kvm_get_mp_state(cpu);
b9bec74b 3469 if (ret < 0) {
f4f1110e 3470 goto out;
b9bec74b 3471 }
4fadfa00 3472 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3473 if (ret < 0) {
f4f1110e 3474 goto out;
b9bec74b 3475 }
4fadfa00 3476 ret = kvm_get_xsave(cpu);
b9bec74b 3477 if (ret < 0) {
f4f1110e 3478 goto out;
b9bec74b 3479 }
4fadfa00 3480 ret = kvm_get_xcrs(cpu);
b9bec74b 3481 if (ret < 0) {
f4f1110e 3482 goto out;
b9bec74b 3483 }
4fadfa00 3484 ret = kvm_get_sregs(cpu);
b9bec74b 3485 if (ret < 0) {
f4f1110e 3486 goto out;
b9bec74b 3487 }
4fadfa00 3488 ret = kvm_get_msrs(cpu);
680c1c6f 3489 if (ret < 0) {
f4f1110e 3490 goto out;
680c1c6f 3491 }
4fadfa00 3492 ret = kvm_get_apic(cpu);
b9bec74b 3493 if (ret < 0) {
f4f1110e 3494 goto out;
b9bec74b 3495 }
1bc22652 3496 ret = kvm_get_debugregs(cpu);
b9bec74b 3497 if (ret < 0) {
f4f1110e 3498 goto out;
b9bec74b 3499 }
f4f1110e
RH		 3500 ret = 0;
3501 out:
3502 cpu_sync_bndcs_hflags(&cpu->env);
3503 return ret;
05330448
AL		 3504}
3505
20d695a9 3506void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3507{
20d695a9
AF		 3508 X86CPU *x86_cpu = X86_CPU(cpu);
3509 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3510 int ret;
3511
276ce815 3512 /* Inject NMI */
fc12d72e
PB		 3513 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3514 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3515 qemu_mutex_lock_iothread();
3516 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3517 qemu_mutex_unlock_iothread();
3518 DPRINTF("injected NMI\n");
3519 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3520 if (ret < 0) {
3521 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3522 strerror(-ret));
3523 }
3524 }
3525 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3526 qemu_mutex_lock_iothread();
3527 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3528 qemu_mutex_unlock_iothread();
3529 DPRINTF("injected SMI\n");
3530 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3531 if (ret < 0) {
3532 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3533 strerror(-ret));
3534 }
ce377af3 3535 }
276ce815
LJ		 3536 }
3537
15eafc2e 3538 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3539 qemu_mutex_lock_iothread();
3540 }
3541
e0723c45
PB		 3542 /* Force the VCPU out of its inner loop to process any INIT requests
3543 * or (for userspace APIC, but it is cheap to combine the checks here)
3544 * pending TPR access reports.
3545 */
3546 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3547 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3548 !(env->hflags & HF_SMM_MASK)) {
3549 cpu->exit_request = 1;
3550 }
3551 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3552 cpu->exit_request = 1;
3553 }
e0723c45 3554 }
05330448 3555
15eafc2e 3556 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3557 /* Try to inject an interrupt if the guest can accept it */
3558 if (run->ready_for_interrupt_injection &&
259186a7 3559 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3560 (env->eflags & IF_MASK)) {
3561 int irq;
3562
259186a7 3563 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3564 irq = cpu_get_pic_interrupt(env);
3565 if (irq >= 0) {
3566 struct kvm_interrupt intr;
3567
3568 intr.irq = irq;
db1669bc 3569 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3570 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3571 if (ret < 0) {
3572 fprintf(stderr,
3573 "KVM: injection failed, interrupt lost (%s)\n",
3574 strerror(-ret));
3575 }
db1669bc
JK		 3576 }
3577 }
05330448 3578
db1669bc
JK		 3579 /* If we have an interrupt but the guest is not ready to receive an
3580 * interrupt, request an interrupt window exit. This will
3581 * cause a return to userspace as soon as the guest is ready to
3582 * receive interrupts. */
259186a7 3583 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3584 run->request_interrupt_window = 1;
3585 } else {
3586 run->request_interrupt_window = 0;
3587 }
3588
3589 DPRINTF("setting tpr\n");
02e51483 3590 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3591
3592 qemu_mutex_unlock_iothread();
db1669bc 3593 }
05330448
AL		 3594}
3595
4c663752 3596MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3597{
20d695a9
AF		 3598 X86CPU *x86_cpu = X86_CPU(cpu);
3599 CPUX86State *env = &x86_cpu->env;
3600
fc12d72e
PB		 3601 if (run->flags & KVM_RUN_X86_SMM) {
3602 env->hflags |= HF_SMM_MASK;
3603 } else {
f5c052b9 3604 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3605 }
b9bec74b 3606 if (run->if_flag) {
05330448 3607 env->eflags |= IF_MASK;
b9bec74b 3608 } else {
05330448 3609 env->eflags &= ~IF_MASK;
b9bec74b 3610 }
4b8523ee
JK		 3611
3612 /* We need to protect the apic state against concurrent accesses from
3613 * different threads in case the userspace irqchip is used. */
3614 if (!kvm_irqchip_in_kernel()) {
3615 qemu_mutex_lock_iothread();
3616 }
02e51483
CF		 3617 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3618 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3619 if (!kvm_irqchip_in_kernel()) {
3620 qemu_mutex_unlock_iothread();
3621 }
f794aa4a 3622 return cpu_get_mem_attrs(env);
05330448
AL		 3623}
3624
20d695a9 3625int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3626{
20d695a9
AF		 3627 X86CPU *cpu = X86_CPU(cs);
3628 CPUX86State *env = &cpu->env;
232fc23b 3629
259186a7 3630 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3631 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3632 assert(env->mcg_cap);
3633
259186a7 3634 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3635
dd1750d7 3636 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3637
3638 if (env->exception_injected == EXCP08_DBLE) {
3639 /* this means triple fault */
cf83f140 3640 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3641 cs->exit_request = 1;
ab443475
JK		 3642 return 0;
3643 }
3644 env->exception_injected = EXCP12_MCHK;
3645 env->has_error_code = 0;
3646
259186a7 3647 cs->halted = 0;
ab443475
JK		 3648 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3649 env->mp_state = KVM_MP_STATE_RUNNABLE;
3650 }
3651 }
3652
fc12d72e
PB		 3653 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3654 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3655 kvm_cpu_synchronize_state(cs);
3656 do_cpu_init(cpu);
3657 }
3658
db1669bc
JK		 3659 if (kvm_irqchip_in_kernel()) {
3660 return 0;
3661 }
3662
259186a7
AF		 3663 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3664 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3665 apic_poll_irq(cpu->apic_state);
5d62c43a 3666 }
259186a7 3667 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3668 (env->eflags & IF_MASK)) ||
259186a7
AF		 3669 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3670 cs->halted = 0;
6792a57b 3671 }
259186a7 3672 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3673 kvm_cpu_synchronize_state(cs);
232fc23b 3674 do_cpu_sipi(cpu);
0af691d7 3675 }
259186a7
AF		 3676 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3677 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3678 kvm_cpu_synchronize_state(cs);
02e51483 3679 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3680 env->tpr_access_type);
3681 }
0af691d7 3682
259186a7 3683 return cs->halted;
0af691d7
MT		 3684}
3685
839b5630 3686static int kvm_handle_halt(X86CPU *cpu)
05330448 3687{
259186a7 3688 CPUState *cs = CPU(cpu);
839b5630
AF		 3689 CPUX86State *env = &cpu->env;
3690
259186a7 3691 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3692 (env->eflags & IF_MASK)) &&
259186a7
AF		 3693 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3694 cs->halted = 1;
bb4ea393 3695 return EXCP_HLT;
05330448
AL		 3696 }
3697
bb4ea393 3698 return 0;
05330448
AL		 3699}
3700
f7575c96 3701static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3702{
f7575c96
AF		 3703 CPUState *cs = CPU(cpu);
3704 struct kvm_run *run = cs->kvm_run;
d362e757 3705
02e51483 3706 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3707 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3708 : TPR_ACCESS_READ);
3709 return 1;
3710}
3711
f17ec444 3712int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3713{
38972938 3714 static const uint8_t int3 = 0xcc;
64bf3f4e 3715
f17ec444
AF		 3716 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3717 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3718 return -EINVAL;
b9bec74b 3719 }
e22a25c9
AL		 3720 return 0;
3721}
3722
f17ec444 3723int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3724{
3725 uint8_t int3;
3726
f17ec444
AF		 3727 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3728 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3729 return -EINVAL;
b9bec74b 3730 }
e22a25c9
AL		 3731 return 0;
3732}
3733
3734static struct {
3735 target_ulong addr;
3736 int len;
3737 int type;
3738} hw_breakpoint[4];
3739
3740static int nb_hw_breakpoint;
3741
3742static int find_hw_breakpoint(target_ulong addr, int len, int type)
3743{
3744 int n;
3745
b9bec74b 3746 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3747 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3748 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3749 return n;
b9bec74b
JK		 3750 }
3751 }
e22a25c9
AL		 3752 return -1;
3753}
3754
3755int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3756 target_ulong len, int type)
3757{
3758 switch (type) {
3759 case GDB_BREAKPOINT_HW:
3760 len = 1;
3761 break;
3762 case GDB_WATCHPOINT_WRITE:
3763 case GDB_WATCHPOINT_ACCESS:
3764 switch (len) {
3765 case 1:
3766 break;
3767 case 2:
3768 case 4:
3769 case 8:
b9bec74b 3770 if (addr & (len - 1)) {
e22a25c9 3771 return -EINVAL;
b9bec74b 3772 }
e22a25c9
AL		 3773 break;
3774 default:
3775 return -EINVAL;
3776 }
3777 break;
3778 default:
3779 return -ENOSYS;
3780 }
3781
b9bec74b 3782 if (nb_hw_breakpoint == 4) {
e22a25c9 3783 return -ENOBUFS;
b9bec74b
JK		 3784 }
3785 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3786 return -EEXIST;
b9bec74b 3787 }
e22a25c9
AL		 3788 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3789 hw_breakpoint[nb_hw_breakpoint].len = len;
3790 hw_breakpoint[nb_hw_breakpoint].type = type;
3791 nb_hw_breakpoint++;
3792
3793 return 0;
3794}
3795
3796int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3797 target_ulong len, int type)
3798{
3799 int n;
3800
3801 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3802 if (n < 0) {
e22a25c9 3803 return -ENOENT;
b9bec74b 3804 }
e22a25c9
AL		 3805 nb_hw_breakpoint--;
3806 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3807
3808 return 0;
3809}
3810
3811void kvm_arch_remove_all_hw_breakpoints(void)
3812{
3813 nb_hw_breakpoint = 0;
3814}
3815
3816static CPUWatchpoint hw_watchpoint;
3817
a60f24b5 3818static int kvm_handle_debug(X86CPU *cpu,
48405526 3819 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3820{
ed2803da 3821 CPUState *cs = CPU(cpu);
a60f24b5 3822 CPUX86State *env = &cpu->env;
f2574737 3823 int ret = 0;
e22a25c9
AL		 3824 int n;
3825
3826 if (arch_info->exception == 1) {
3827 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3828 if (cs->singlestep_enabled) {
f2574737 3829 ret = EXCP_DEBUG;
b9bec74b 3830 }
e22a25c9 3831 } else {
b9bec74b
JK		 3832 for (n = 0; n < 4; n++) {
3833 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3834 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3835 case 0x0:
f2574737 3836 ret = EXCP_DEBUG;
e22a25c9
AL		 3837 break;
3838 case 0x1:
f2574737 3839 ret = EXCP_DEBUG;
ff4700b0 3840 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3841 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3842 hw_watchpoint.flags = BP_MEM_WRITE;
3843 break;
3844 case 0x3:
f2574737 3845 ret = EXCP_DEBUG;
ff4700b0 3846 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3847 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3848 hw_watchpoint.flags = BP_MEM_ACCESS;
3849 break;
3850 }
b9bec74b
JK		 3851 }
3852 }
e22a25c9 3853 }
ff4700b0 3854 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3855 ret = EXCP_DEBUG;
b9bec74b 3856 }
f2574737 3857 if (ret == 0) {
ff4700b0 3858 cpu_synchronize_state(cs);
48405526 3859 assert(env->exception_injected == -1);
b0b1d690 3860
f2574737 3861 /* pass to guest */
48405526
BS		 3862 env->exception_injected = arch_info->exception;
3863 env->has_error_code = 0;
b0b1d690 3864 }
e22a25c9 3865
f2574737 3866 return ret;
e22a25c9
AL		 3867}
3868
20d695a9 3869void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3870{
3871 const uint8_t type_code[] = {
3872 [GDB_BREAKPOINT_HW] = 0x0,
3873 [GDB_WATCHPOINT_WRITE] = 0x1,
3874 [GDB_WATCHPOINT_ACCESS] = 0x3
3875 };
3876 const uint8_t len_code[] = {
3877 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3878 };
3879 int n;
3880
a60f24b5 3881 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3882 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3883 }
e22a25c9
AL		 3884 if (nb_hw_breakpoint > 0) {
3885 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3886 dbg->arch.debugreg[7] = 0x0600;
3887 for (n = 0; n < nb_hw_breakpoint; n++) {
3888 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3889 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3890 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3891 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3892 }
3893 }
3894}
4513d923 3895
2a4dac83
JK		 3896static bool host_supports_vmx(void)
3897{
3898 uint32_t ecx, unused;
3899
3900 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3901 return ecx & CPUID_EXT_VMX;
3902}
3903
3904#define VMX_INVALID_GUEST_STATE 0x80000021
3905
20d695a9 3906int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3907{
20d695a9 3908 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3909 uint64_t code;
3910 int ret;
3911
3912 switch (run->exit_reason) {
3913 case KVM_EXIT_HLT:
3914 DPRINTF("handle_hlt\n");
4b8523ee 3915 qemu_mutex_lock_iothread();
839b5630 3916 ret = kvm_handle_halt(cpu);
4b8523ee 3917 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3918 break;
3919 case KVM_EXIT_SET_TPR:
3920 ret = 0;
3921 break;
d362e757 3922 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3923 qemu_mutex_lock_iothread();
f7575c96 3924 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3925 qemu_mutex_unlock_iothread();
d362e757 3926 break;
2a4dac83
JK		 3927 case KVM_EXIT_FAIL_ENTRY:
3928 code = run->fail_entry.hardware_entry_failure_reason;
3929 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3930 code);
3931 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3932 fprintf(stderr,
12619721 3933 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3934 "unrestricted mode\n"
3935 "support, the failure can be most likely due to the guest "
3936 "entering an invalid\n"
3937 "state for Intel VT. For example, the guest maybe running "
3938 "in big real mode\n"
3939 "which is not supported on less recent Intel processors."
3940 "\n\n");
3941 }
3942 ret = -1;
3943 break;
3944 case KVM_EXIT_EXCEPTION:
3945 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3946 run->ex.exception, run->ex.error_code);
3947 ret = -1;
3948 break;
f2574737
JK		 3949 case KVM_EXIT_DEBUG:
3950 DPRINTF("kvm_exit_debug\n");
4b8523ee 3951 qemu_mutex_lock_iothread();
a60f24b5 3952 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3953 qemu_mutex_unlock_iothread();
f2574737 3954 break;
50efe82c
AS		 3955 case KVM_EXIT_HYPERV:
3956 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3957 break;
15eafc2e
PB		 3958 case KVM_EXIT_IOAPIC_EOI:
3959 ioapic_eoi_broadcast(run->eoi.vector);
3960 ret = 0;
3961 break;
2a4dac83
JK		 3962 default:
3963 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3964 ret = -1;
3965 break;
3966 }
3967
3968 return ret;
3969}
3970
20d695a9 3971bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3972{
20d695a9
AF		 3973 X86CPU *cpu = X86_CPU(cs);
3974 CPUX86State *env = &cpu->env;
3975
dd1750d7 3976 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3977 return !(env->cr[0] & CR0_PE_MASK) ||
3978 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3979}
84b058d7
JK		 3980
3981void kvm_arch_init_irq_routing(KVMState *s)
3982{
3983 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3984 /* If kernel can't do irq routing, interrupt source
3985 * override 0->2 cannot be set up as required by HPET.
3986 * So we have to disable it.
3987 */
3988 no_hpet = 1;
3989 }
cc7e0ddf 3990 /* We know at this point that we're using the in-kernel
614e41bc 3991 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3992 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3993 */
614e41bc 3994 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3995 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3996
3997 if (kvm_irqchip_is_split()) {
3998 int i;
3999
4000 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4001 MSI routes for signaling interrupts to the local apics. */
4002 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4003 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4004 error_report("Could not enable split IRQ mode.");
4005 exit(1);
4006 }
4007 }
4008 }
4009}
4010
4011int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4012{
4013 int ret;
4014 if (machine_kernel_irqchip_split(ms)) {
4015 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4016 if (ret) {
df3c286c 4017 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4018 strerror(-ret));
4019 exit(1);
4020 } else {
4021 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4022 kvm_split_irqchip = true;
4023 return 1;
4024 }
4025 } else {
4026 return 0;
4027 }
84b058d7 4028}
b139bd30
JK		 4029
4030/* Classic KVM device assignment interface. Will remain x86 only. */
4031int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4032 uint32_t flags, uint32_t *dev_id)
4033{
4034 struct kvm_assigned_pci_dev dev_data = {
4035 .segnr = dev_addr->domain,
4036 .busnr = dev_addr->bus,
4037 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4038 .flags = flags,
4039 };
4040 int ret;
4041
4042 dev_data.assigned_dev_id =
4043 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4044
4045 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4046 if (ret < 0) {
4047 return ret;
4048 }
4049
4050 *dev_id = dev_data.assigned_dev_id;
4051
4052 return 0;
4053}
4054
4055int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4056{
4057 struct kvm_assigned_pci_dev dev_data = {
4058 .assigned_dev_id = dev_id,
4059 };
4060
4061 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4062}
4063
4064static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4065 uint32_t irq_type, uint32_t guest_irq)
4066{
4067 struct kvm_assigned_irq assigned_irq = {
4068 .assigned_dev_id = dev_id,
4069 .guest_irq = guest_irq,
4070 .flags = irq_type,
4071 };
4072
4073 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4074 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4075 } else {
4076 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4077 }
4078}
4079
4080int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4081 uint32_t guest_irq)
4082{
4083 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4084 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4085
4086 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4087}
4088
4089int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4090{
4091 struct kvm_assigned_pci_dev dev_data = {
4092 .assigned_dev_id = dev_id,
4093 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4094 };
4095
4096 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4097}
4098
4099static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4100 uint32_t type)
4101{
4102 struct kvm_assigned_irq assigned_irq = {
4103 .assigned_dev_id = dev_id,
4104 .flags = type,
4105 };
4106
4107 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4108}
4109
4110int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4111{
4112 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4113 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4114}
4115
4116int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4117{
4118 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4119 KVM_DEV_IRQ_GUEST_MSI, virq);
4120}
4121
4122int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4123{
4124 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4125 KVM_DEV_IRQ_HOST_MSI);
4126}
4127
4128bool kvm_device_msix_supported(KVMState *s)
4129{
4130 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4131 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4132 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4133}
4134
4135int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4136 uint32_t nr_vectors)
4137{
4138 struct kvm_assigned_msix_nr msix_nr = {
4139 .assigned_dev_id = dev_id,
4140 .entry_nr = nr_vectors,
4141 };
4142
4143 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4144}
4145
4146int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4147 int virq)
4148{
4149 struct kvm_assigned_msix_entry msix_entry = {
4150 .assigned_dev_id = dev_id,
4151 .gsi = virq,
4152 .entry = vector,
4153 };
4154
4155 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4156}
4157
4158int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4159{
4160 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4161 KVM_DEV_IRQ_GUEST_MSIX, 0);
4162}
4163
4164int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4165{
4166 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4167 KVM_DEV_IRQ_HOST_MSIX);
4168}
9e03a040
FB		 4169
4170int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4171 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4172{
8b5ed7df
PX		 4173 X86IOMMUState *iommu = x86_iommu_get_default();
4174
4175 if (iommu) {
4176 int ret;
4177 MSIMessage src, dst;
4178 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4179
0ea1472d
JK		 4180 if (!class->int_remap) {
4181 return 0;
4182 }
4183
8b5ed7df
PX		 4184 src.address = route->u.msi.address_hi;
4185 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4186 src.address |= route->u.msi.address_lo;
4187 src.data = route->u.msi.data;
4188
4189 ret = class->int_remap(iommu, &src, &dst, dev ? \
4190 pci_requester_id(dev) : \
4191 X86_IOMMU_SID_INVALID);
4192 if (ret) {
4193 trace_kvm_x86_fixup_msi_error(route->gsi);
4194 return 1;
4195 }
4196
4197 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4198 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4199 route->u.msi.data = dst.data;
4200 }
4201
9e03a040
FB		 4202 return 0;
4203}
1850b6b7 4204
38d87493
PX		 4205typedef struct MSIRouteEntry MSIRouteEntry;
4206
4207struct MSIRouteEntry {
4208 PCIDevice *dev; /* Device pointer */
4209 int vector; /* MSI/MSIX vector index */
4210 int virq; /* Virtual IRQ index */
4211 QLIST_ENTRY(MSIRouteEntry) list;
4212};
4213
4214/* List of used GSI routes */
4215static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4216 QLIST_HEAD_INITIALIZER(msi_route_list);
4217
e1d4fb2d
PX		 4218static void kvm_update_msi_routes_all(void *private, bool global,
4219 uint32_t index, uint32_t mask)
4220{
a56de056 4221 int cnt = 0, vector;
e1d4fb2d
PX		 4222 MSIRouteEntry *entry;
4223 MSIMessage msg;
fd563564
PX		 4224 PCIDevice *dev;
4225
e1d4fb2d
PX		 4226 /* TODO: explicit route update */
4227 QLIST_FOREACH(entry, &msi_route_list, list) {
4228 cnt++;
a56de056 4229 vector = entry->vector;
fd563564 4230 dev = entry->dev;
a56de056
PX		 4231 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4232 msg = msix_get_message(dev, vector);
4233 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4234 msg = msi_get_message(dev, vector);
4235 } else {
4236 /*
4237 * Either MSI/MSIX is disabled for the device, or the
4238 * specific message was masked out. Skip this one.
4239 */
fd563564
PX		 4240 continue;
4241 }
fd563564 4242 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4243 }
3f1fea0f 4244 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4245 trace_kvm_x86_update_msi_routes(cnt);
4246}
4247
38d87493
PX		 4248int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4249 int vector, PCIDevice *dev)
4250{
e1d4fb2d 4251 static bool notify_list_inited = false;
38d87493
PX		 4252 MSIRouteEntry *entry;
4253
4254 if (!dev) {
4255 /* These are (possibly) IOAPIC routes only used for split
4256 * kernel irqchip mode, while what we are housekeeping are
4257 * PCI devices only. */
4258 return 0;
4259 }
4260
4261 entry = g_new0(MSIRouteEntry, 1);
4262 entry->dev = dev;
4263 entry->vector = vector;
4264 entry->virq = route->gsi;
4265 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4266
4267 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4268
4269 if (!notify_list_inited) {
4270 /* For the first time we do add route, add ourselves into
4271 * IOMMU's IEC notify list if needed. */
4272 X86IOMMUState *iommu = x86_iommu_get_default();
4273 if (iommu) {
4274 x86_iommu_iec_register_notifier(iommu,
4275 kvm_update_msi_routes_all,
4276 NULL);
4277 }
4278 notify_list_inited = true;
4279 }
38d87493
PX		 4280 return 0;
4281}
4282
4283int kvm_arch_release_virq_post(int virq)
4284{
4285 MSIRouteEntry *entry, *next;
4286 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4287 if (entry->virq == virq) {
4288 trace_kvm_x86_remove_msi_route(virq);
4289 QLIST_REMOVE(entry, list);
01960e6d 4290 g_free(entry);
38d87493
PX		 4291 break;
4292 }
4293 }
9e03a040
FB		 4294 return 0;
4295}
1850b6b7
EA		 4296
4297int kvm_arch_msi_data_to_gsi(uint32_t data)
4298{
4299 abort();
4300}
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