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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
4c822698 | 10 | #include <linux/sched/idle.h> |
b17b0153 | 11 | #include <linux/sched/debug.h> |
29930025 | 12 | #include <linux/sched/task.h> |
186f4360 PG |
13 | #include <linux/init.h> |
14 | #include <linux/export.h> | |
7f424a8b | 15 | #include <linux/pm.h> |
162a688e | 16 | #include <linux/tick.h> |
9d62dcdf | 17 | #include <linux/random.h> |
7c68af6e | 18 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
19 | #include <linux/dmi.h> |
20 | #include <linux/utsname.h> | |
90e24014 RW |
21 | #include <linux/stackprotector.h> |
22 | #include <linux/tick.h> | |
23 | #include <linux/cpuidle.h> | |
61613521 | 24 | #include <trace/events/power.h> |
24f1e32c | 25 | #include <linux/hw_breakpoint.h> |
93789b32 | 26 | #include <asm/cpu.h> |
d3ec5cae | 27 | #include <asm/apic.h> |
2c1b284e | 28 | #include <asm/syscalls.h> |
7c0f6ba6 | 29 | #include <linux/uaccess.h> |
b253149b | 30 | #include <asm/mwait.h> |
78f7f1e5 | 31 | #include <asm/fpu/internal.h> |
66cb5917 | 32 | #include <asm/debugreg.h> |
90e24014 | 33 | #include <asm/nmi.h> |
375074cc | 34 | #include <asm/tlbflush.h> |
8838eb6c | 35 | #include <asm/mce.h> |
9fda6a06 | 36 | #include <asm/vm86.h> |
7b32aead | 37 | #include <asm/switch_to.h> |
b7ffc44d | 38 | #include <asm/desc.h> |
90e24014 | 39 | |
45046892 TG |
40 | /* |
41 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
42 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
43 | * so they are allowed to end up in the .data..cacheline_aligned | |
44 | * section. Since TSS's are completely CPU-local, we want them | |
45 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
46 | */ | |
d0a0de21 AL |
47 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
48 | .x86_tss = { | |
d9e05cc5 | 49 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
50 | #ifdef CONFIG_X86_32 |
51 | .ss0 = __KERNEL_DS, | |
52 | .ss1 = __KERNEL_CS, | |
53 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
54 | #endif | |
55 | }, | |
56 | #ifdef CONFIG_X86_32 | |
57 | /* | |
58 | * Note that the .io_bitmap member must be extra-big. This is because | |
59 | * the CPU will access an additional byte beyond the end of the IO | |
60 | * permission bitmap. The extra byte must be all 1 bits, and must | |
61 | * be within the limit. | |
62 | */ | |
63 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
64 | #endif | |
2a41aa4f AL |
65 | #ifdef CONFIG_X86_32 |
66 | .SYSENTER_stack_canary = STACK_END_MAGIC, | |
67 | #endif | |
d0a0de21 | 68 | }; |
de71ad2c | 69 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 70 | |
b7ffc44d AL |
71 | DEFINE_PER_CPU(bool, need_tr_refresh); |
72 | EXPORT_PER_CPU_SYMBOL_GPL(need_tr_refresh); | |
73 | ||
55ccf3fe SS |
74 | /* |
75 | * this gets called so that we can store lazy state into memory and copy the | |
76 | * current task into the new thread. | |
77 | */ | |
61c4628b SS |
78 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
79 | { | |
5aaeb5c0 | 80 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
81 | #ifdef CONFIG_VM86 |
82 | dst->thread.vm86 = NULL; | |
83 | #endif | |
f1853505 | 84 | |
c69e098b | 85 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 86 | } |
7f424a8b | 87 | |
389d1fb1 JF |
88 | /* |
89 | * Free current thread data structures etc.. | |
90 | */ | |
e6464694 | 91 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 92 | { |
e6464694 | 93 | struct thread_struct *t = &tsk->thread; |
250981e6 | 94 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 95 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 96 | |
250981e6 | 97 | if (bp) { |
24933b82 | 98 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 99 | |
389d1fb1 JF |
100 | t->io_bitmap_ptr = NULL; |
101 | clear_thread_flag(TIF_IO_BITMAP); | |
102 | /* | |
103 | * Careful, clear this in the TSS too: | |
104 | */ | |
105 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
106 | t->io_bitmap_max = 0; | |
107 | put_cpu(); | |
250981e6 | 108 | kfree(bp); |
389d1fb1 | 109 | } |
1dcc8d7b | 110 | |
9fda6a06 BG |
111 | free_vm86(t); |
112 | ||
50338615 | 113 | fpu__drop(fpu); |
389d1fb1 JF |
114 | } |
115 | ||
116 | void flush_thread(void) | |
117 | { | |
118 | struct task_struct *tsk = current; | |
119 | ||
24f1e32c | 120 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 121 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 122 | |
04c8e01d | 123 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
124 | } |
125 | ||
126 | static void hard_disable_TSC(void) | |
127 | { | |
375074cc | 128 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
129 | } |
130 | ||
131 | void disable_TSC(void) | |
132 | { | |
133 | preempt_disable(); | |
134 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
135 | /* | |
136 | * Must flip the CPU state synchronously with | |
137 | * TIF_NOTSC in the current running context. | |
138 | */ | |
139 | hard_disable_TSC(); | |
140 | preempt_enable(); | |
141 | } | |
142 | ||
143 | static void hard_enable_TSC(void) | |
144 | { | |
375074cc | 145 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
146 | } |
147 | ||
148 | static void enable_TSC(void) | |
149 | { | |
150 | preempt_disable(); | |
151 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
152 | /* | |
153 | * Must flip the CPU state synchronously with | |
154 | * TIF_NOTSC in the current running context. | |
155 | */ | |
156 | hard_enable_TSC(); | |
157 | preempt_enable(); | |
158 | } | |
159 | ||
160 | int get_tsc_mode(unsigned long adr) | |
161 | { | |
162 | unsigned int val; | |
163 | ||
164 | if (test_thread_flag(TIF_NOTSC)) | |
165 | val = PR_TSC_SIGSEGV; | |
166 | else | |
167 | val = PR_TSC_ENABLE; | |
168 | ||
169 | return put_user(val, (unsigned int __user *)adr); | |
170 | } | |
171 | ||
172 | int set_tsc_mode(unsigned int val) | |
173 | { | |
174 | if (val == PR_TSC_SIGSEGV) | |
175 | disable_TSC(); | |
176 | else if (val == PR_TSC_ENABLE) | |
177 | enable_TSC(); | |
178 | else | |
179 | return -EINVAL; | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
185 | struct tss_struct *tss) | |
186 | { | |
187 | struct thread_struct *prev, *next; | |
188 | ||
189 | prev = &prev_p->thread; | |
190 | next = &next_p->thread; | |
191 | ||
ea8e61b7 PZ |
192 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
193 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
194 | unsigned long debugctl = get_debugctlmsr(); | |
195 | ||
196 | debugctl &= ~DEBUGCTLMSR_BTF; | |
197 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
198 | debugctl |= DEBUGCTLMSR_BTF; | |
199 | ||
200 | update_debugctlmsr(debugctl); | |
201 | } | |
389d1fb1 | 202 | |
389d1fb1 JF |
203 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
204 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
205 | /* prev and next are different */ | |
206 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
207 | hard_disable_TSC(); | |
208 | else | |
209 | hard_enable_TSC(); | |
210 | } | |
211 | ||
212 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
213 | /* | |
214 | * Copy the relevant range of the IO bitmap. | |
215 | * Normally this is 128 bytes or less: | |
216 | */ | |
217 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
218 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
b7ffc44d AL |
219 | |
220 | /* | |
221 | * Make sure that the TSS limit is correct for the CPU | |
222 | * to notice the IO bitmap. | |
223 | */ | |
224 | refresh_TR(); | |
389d1fb1 JF |
225 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { |
226 | /* | |
227 | * Clear any possible leftover bits: | |
228 | */ | |
229 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
230 | } | |
7c68af6e | 231 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
232 | } |
233 | ||
00dba564 TG |
234 | /* |
235 | * Idle related variables and functions | |
236 | */ | |
d1896049 | 237 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
238 | EXPORT_SYMBOL(boot_option_idle_override); |
239 | ||
a476bda3 | 240 | static void (*x86_idle)(void); |
00dba564 | 241 | |
90e24014 RW |
242 | #ifndef CONFIG_SMP |
243 | static inline void play_dead(void) | |
244 | { | |
245 | BUG(); | |
246 | } | |
247 | #endif | |
248 | ||
7d1a9417 TG |
249 | void arch_cpu_idle_enter(void) |
250 | { | |
6a369583 | 251 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 252 | local_touch_nmi(); |
7d1a9417 | 253 | } |
90e24014 | 254 | |
7d1a9417 TG |
255 | void arch_cpu_idle_dead(void) |
256 | { | |
257 | play_dead(); | |
258 | } | |
90e24014 | 259 | |
7d1a9417 TG |
260 | /* |
261 | * Called from the generic idle code. | |
262 | */ | |
263 | void arch_cpu_idle(void) | |
264 | { | |
16f8b05a | 265 | x86_idle(); |
90e24014 RW |
266 | } |
267 | ||
00dba564 | 268 | /* |
7d1a9417 | 269 | * We use this if we don't have any better idle routine.. |
00dba564 | 270 | */ |
6727ad9e | 271 | void __cpuidle default_idle(void) |
00dba564 | 272 | { |
4d0e42cc | 273 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 274 | safe_halt(); |
4d0e42cc | 275 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 276 | } |
60b8b1de | 277 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
278 | EXPORT_SYMBOL(default_idle); |
279 | #endif | |
280 | ||
6a377ddc LB |
281 | #ifdef CONFIG_XEN |
282 | bool xen_set_default_idle(void) | |
e5fd47bf | 283 | { |
a476bda3 | 284 | bool ret = !!x86_idle; |
e5fd47bf | 285 | |
a476bda3 | 286 | x86_idle = default_idle; |
e5fd47bf KRW |
287 | |
288 | return ret; | |
289 | } | |
6a377ddc | 290 | #endif |
d3ec5cae IV |
291 | void stop_this_cpu(void *dummy) |
292 | { | |
293 | local_irq_disable(); | |
294 | /* | |
295 | * Remove this CPU: | |
296 | */ | |
4f062896 | 297 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 298 | disable_local_APIC(); |
8838eb6c | 299 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 300 | |
27be4570 LB |
301 | for (;;) |
302 | halt(); | |
7f424a8b PZ |
303 | } |
304 | ||
aa276e1c | 305 | /* |
07c94a38 BP |
306 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
307 | * states (local apic timer and TSC stop). | |
aa276e1c | 308 | */ |
02c68a02 | 309 | static void amd_e400_idle(void) |
aa276e1c | 310 | { |
07c94a38 BP |
311 | /* |
312 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
313 | * gets set after static_cpu_has() places have been converted via | |
314 | * alternatives. | |
315 | */ | |
316 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
317 | default_idle(); | |
318 | return; | |
aa276e1c TG |
319 | } |
320 | ||
07c94a38 | 321 | tick_broadcast_enter(); |
aa276e1c | 322 | |
07c94a38 | 323 | default_idle(); |
0beefa20 | 324 | |
07c94a38 BP |
325 | /* |
326 | * The switch back from broadcast mode needs to be called with | |
327 | * interrupts disabled. | |
328 | */ | |
329 | local_irq_disable(); | |
330 | tick_broadcast_exit(); | |
331 | local_irq_enable(); | |
aa276e1c TG |
332 | } |
333 | ||
b253149b LB |
334 | /* |
335 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
336 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
337 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
338 | * | |
339 | * Some AMD machines are the opposite, they depend on using HALT. | |
340 | * | |
341 | * So for default C1, which is used during boot until cpuidle loads, | |
342 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
343 | */ | |
344 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
345 | { | |
346 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
347 | return 0; | |
348 | ||
08e237fa | 349 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
350 | return 0; |
351 | ||
352 | return 1; | |
353 | } | |
354 | ||
355 | /* | |
0fb0328d HR |
356 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
357 | * with interrupts enabled and no flags, which is backwards compatible with the | |
358 | * original MWAIT implementation. | |
b253149b | 359 | */ |
6727ad9e | 360 | static __cpuidle void mwait_idle(void) |
b253149b | 361 | { |
f8e617f4 | 362 | if (!current_set_polling_and_test()) { |
e43d0189 | 363 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 364 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 365 | mb(); /* quirk */ |
b253149b | 366 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 367 | mb(); /* quirk */ |
f8e617f4 | 368 | } |
b253149b LB |
369 | |
370 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
371 | if (!need_resched()) |
372 | __sti_mwait(0, 0); | |
373 | else | |
374 | local_irq_enable(); | |
e43d0189 | 375 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 376 | } else { |
b253149b | 377 | local_irq_enable(); |
f8e617f4 MG |
378 | } |
379 | __current_clr_polling(); | |
b253149b LB |
380 | } |
381 | ||
148f9bb8 | 382 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 383 | { |
3e5095d1 | 384 | #ifdef CONFIG_SMP |
7d1a9417 | 385 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 386 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 387 | #endif |
7d1a9417 | 388 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
389 | return; |
390 | ||
3344ed30 | 391 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 392 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 393 | x86_idle = amd_e400_idle; |
b253149b LB |
394 | } else if (prefer_mwait_c1_over_halt(c)) { |
395 | pr_info("using mwait in idle threads\n"); | |
396 | x86_idle = mwait_idle; | |
6ddd2a27 | 397 | } else |
a476bda3 | 398 | x86_idle = default_idle; |
7f424a8b PZ |
399 | } |
400 | ||
07c94a38 | 401 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 402 | { |
07c94a38 BP |
403 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
404 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
405 | local_irq_disable(); | |
406 | tick_broadcast_force(); | |
407 | local_irq_enable(); | |
408 | } | |
30e1e6d1 RR |
409 | } |
410 | ||
e7ff3a47 TG |
411 | void __init arch_post_acpi_subsys_init(void) |
412 | { | |
413 | u32 lo, hi; | |
414 | ||
415 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
416 | return; | |
417 | ||
418 | /* | |
419 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
420 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
421 | * MSR_K8_INT_PENDING_MSG. | |
422 | */ | |
423 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
424 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
425 | return; | |
426 | ||
427 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
428 | ||
429 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
430 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
431 | pr_info("System has AMD C1E enabled\n"); | |
432 | } | |
433 | ||
7f424a8b PZ |
434 | static int __init idle_setup(char *str) |
435 | { | |
ab6bc3e3 CG |
436 | if (!str) |
437 | return -EINVAL; | |
438 | ||
7f424a8b | 439 | if (!strcmp(str, "poll")) { |
c767a54b | 440 | pr_info("using polling idle threads\n"); |
d1896049 | 441 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 442 | cpu_idle_poll_ctrl(true); |
d1896049 | 443 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
444 | /* |
445 | * When the boot option of idle=halt is added, halt is | |
446 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
447 | * won't be used again. | |
448 | * To continue to load the CPU idle driver, don't touch | |
449 | * the boot_option_idle_override. | |
450 | */ | |
a476bda3 | 451 | x86_idle = default_idle; |
d1896049 | 452 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
453 | } else if (!strcmp(str, "nomwait")) { |
454 | /* | |
455 | * If the boot option of "idle=nomwait" is added, | |
456 | * it means that mwait will be disabled for CPU C2/C3 | |
457 | * states. In such case it won't touch the variable | |
458 | * of boot_option_idle_override. | |
459 | */ | |
d1896049 | 460 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 461 | } else |
7f424a8b PZ |
462 | return -1; |
463 | ||
7f424a8b PZ |
464 | return 0; |
465 | } | |
466 | early_param("idle", idle_setup); | |
467 | ||
9d62dcdf AW |
468 | unsigned long arch_align_stack(unsigned long sp) |
469 | { | |
470 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
471 | sp -= get_random_int() % 8192; | |
472 | return sp & ~0xf; | |
473 | } | |
474 | ||
475 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
476 | { | |
9c6f0902 | 477 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
478 | } |
479 | ||
ffcb043b BG |
480 | /* |
481 | * Return saved PC of a blocked thread. | |
482 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
483 | */ | |
484 | unsigned long thread_saved_pc(struct task_struct *tsk) | |
485 | { | |
486 | struct inactive_task_frame *frame = | |
487 | (struct inactive_task_frame *) READ_ONCE(tsk->thread.sp); | |
488 | return READ_ONCE_NOCHECK(frame->ret_addr); | |
489 | } | |
490 | ||
7ba78053 TG |
491 | /* |
492 | * Called from fs/proc with a reference on @p to find the function | |
493 | * which called into schedule(). This needs to be done carefully | |
494 | * because the task might wake up and we might look at a stack | |
495 | * changing under us. | |
496 | */ | |
497 | unsigned long get_wchan(struct task_struct *p) | |
498 | { | |
74327a3e | 499 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
500 | int count = 0; |
501 | ||
502 | if (!p || p == current || p->state == TASK_RUNNING) | |
503 | return 0; | |
504 | ||
74327a3e AL |
505 | if (!try_get_task_stack(p)) |
506 | return 0; | |
507 | ||
7ba78053 TG |
508 | start = (unsigned long)task_stack_page(p); |
509 | if (!start) | |
74327a3e | 510 | goto out; |
7ba78053 TG |
511 | |
512 | /* | |
513 | * Layout of the stack page: | |
514 | * | |
515 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
516 | * PADDING | |
517 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
518 | * stack | |
15f4eae7 | 519 | * ----------- bottom = start |
7ba78053 TG |
520 | * |
521 | * The tasks stack pointer points at the location where the | |
522 | * framepointer is stored. The data on the stack is: | |
523 | * ... IP FP ... IP FP | |
524 | * | |
525 | * We need to read FP and IP, so we need to adjust the upper | |
526 | * bound by another unsigned long. | |
527 | */ | |
528 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
529 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 530 | bottom = start; |
7ba78053 TG |
531 | |
532 | sp = READ_ONCE(p->thread.sp); | |
533 | if (sp < bottom || sp > top) | |
74327a3e | 534 | goto out; |
7ba78053 | 535 | |
7b32aead | 536 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
537 | do { |
538 | if (fp < bottom || fp > top) | |
74327a3e | 539 | goto out; |
f7d27c35 | 540 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
541 | if (!in_sched_functions(ip)) { |
542 | ret = ip; | |
543 | goto out; | |
544 | } | |
f7d27c35 | 545 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 546 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
547 | |
548 | out: | |
549 | put_task_stack(p); | |
550 | return ret; | |
7ba78053 | 551 | } |