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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1122cc78 | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
da285121 | 35 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 36 | static void __init ssb_select_mitigation(void); |
05516ad8 | 37 | static void __init l1tf_select_mitigation(void); |
fc5ee888 | 38 | static void __init mds_select_mitigation(void); |
da285121 | 39 | |
7011f443 JK |
40 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
41 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 42 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 43 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 44 | |
d0c3bedd KRW |
45 | /* |
46 | * The vendor and possibly platform specific bits which can be modified in | |
47 | * x86_spec_ctrl_base. | |
48 | */ | |
e5f984ed | 49 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 50 | |
c37b94dd KRW |
51 | /* |
52 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 53 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
54 | */ |
55 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 56 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 57 | |
8edb388f | 58 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 59 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
60 | /* Control conditional IBPB in switch_mm() */ |
61 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
62 | /* Control unconditional IBPB in switch_mm() */ | |
63 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 64 | |
5ab15133 TG |
65 | /* Control MDS CPU buffer clear before returning to user space */ |
66 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
abf9852b | 67 | EXPORT_SYMBOL_GPL(mds_user_clear); |
f3eb8f09 TG |
68 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
69 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
70 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
5ab15133 | 71 | |
1353ebb4 JF |
72 | void __init check_bugs(void) |
73 | { | |
74 | identify_boot_cpu(); | |
55a36b65 | 75 | |
483ec3c6 TG |
76 | /* |
77 | * identify_boot_cpu() initialized SMT support information, let the | |
78 | * core code know. | |
79 | */ | |
ade31b9e | 80 | cpu_smt_check_topology_early(); |
483ec3c6 | 81 | |
62a67e12 BP |
82 | if (!IS_ENABLED(CONFIG_SMP)) { |
83 | pr_info("CPU: "); | |
84 | print_cpu_info(&boot_cpu_data); | |
85 | } | |
86 | ||
296b454a KRW |
87 | /* |
88 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
89 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
90 | * init code as it is not enumerated and depends on the family. | |
296b454a | 91 | */ |
50f9b919 | 92 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
93 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
94 | ||
e5f984ed TG |
95 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
96 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
97 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
98 | ||
da285121 DW |
99 | /* Select the proper spectre mitigation before patching alternatives */ |
100 | spectre_v2_select_mitigation(); | |
101 | ||
e63490c8 KRW |
102 | /* |
103 | * Select proper mitigation for any exposure to the Speculative Store | |
104 | * Bypass vulnerability. | |
105 | */ | |
106 | ssb_select_mitigation(); | |
107 | ||
05516ad8 AK |
108 | l1tf_select_mitigation(); |
109 | ||
fc5ee888 TG |
110 | mds_select_mitigation(); |
111 | ||
15ff73d9 JP |
112 | arch_smt_update(); |
113 | ||
62a67e12 | 114 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
115 | /* |
116 | * Check whether we are able to run this kernel safely on SMP. | |
117 | * | |
118 | * - i386 is no longer supported. | |
119 | * - In order to run on anything without a TSC, we need to be | |
120 | * compiled for a i486. | |
121 | */ | |
122 | if (boot_cpu_data.x86 < 4) | |
123 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
124 | ||
bfe4bb15 MV |
125 | init_utsname()->machine[1] = |
126 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 127 | alternative_instructions(); |
304bceda | 128 | |
4d164092 | 129 | fpu__init_check_bugs(); |
62a67e12 BP |
130 | #else /* CONFIG_X86_64 */ |
131 | alternative_instructions(); | |
132 | ||
133 | /* | |
134 | * Make sure the first 2MB area is not mapped by huge pages | |
135 | * There are typically fixed size MTRRs in there and overlapping | |
136 | * MTRRs into large pages causes slow downs. | |
137 | * | |
138 | * Right now we don't do that with gbpages because there seems | |
139 | * very little benefit for that case. | |
140 | */ | |
141 | if (!direct_gbpages) | |
142 | set_memory_4k((unsigned long)__va(0), 1); | |
143 | #endif | |
1353ebb4 | 144 | } |
61dc0f55 | 145 | |
12376b62 BP |
146 | void |
147 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 148 | { |
e5f984ed | 149 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 150 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 151 | |
50f9b919 | 152 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 153 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
154 | /* |
155 | * Restrict guest_spec_ctrl to supported values. Clear the | |
156 | * modifiable bits in the host base value and or the | |
157 | * modifiable bits from the guest value. | |
158 | */ | |
159 | guestval = hostval & ~x86_spec_ctrl_mask; | |
160 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
161 | ||
12376b62 | 162 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
163 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
164 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 165 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 166 | |
e0b04783 TC |
167 | /* Conditional STIBP enabled? */ |
168 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
169 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
170 | ||
e5f984ed TG |
171 | if (hostval != guestval) { |
172 | msrval = setguest ? guestval : hostval; | |
173 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
174 | } |
175 | } | |
1238ed31 TG |
176 | |
177 | /* | |
178 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
179 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
180 | */ | |
181 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
182 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
183 | return; | |
184 | ||
185 | /* | |
186 | * If the host has SSBD mitigation enabled, force it in the host's | |
187 | * virtual MSR value. If its not permanently enabled, evaluate | |
188 | * current's TIF_SSBD thread flag. | |
189 | */ | |
190 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
191 | hostval = SPEC_CTRL_SSBD; | |
192 | else | |
193 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
194 | ||
195 | /* Sanitize the guest value */ | |
196 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
197 | ||
198 | if (hostval != guestval) { | |
199 | unsigned long tif; | |
200 | ||
201 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
202 | ssbd_spec_ctrl_to_tif(hostval); | |
203 | ||
8fce7184 | 204 | speculation_ctrl_update(tif); |
1238ed31 | 205 | } |
19fff03f | 206 | } |
12376b62 | 207 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 208 | |
8fe36c9d | 209 | static void x86_amd_ssb_disable(void) |
c37b94dd | 210 | { |
8fe36c9d | 211 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 212 | |
65e02bbd TL |
213 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
214 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
215 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
216 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
217 | } | |
218 | ||
fc5ee888 TG |
219 | #undef pr_fmt |
220 | #define pr_fmt(fmt) "MDS: " fmt | |
221 | ||
64adee4f | 222 | /* Default mitigation for MDS-affected CPUs */ |
fc5ee888 | 223 | static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; |
e2f3c337 | 224 | static bool mds_nosmt __ro_after_init = false; |
fc5ee888 TG |
225 | |
226 | static const char * const mds_strings[] = { | |
227 | [MDS_MITIGATION_OFF] = "Vulnerable", | |
ebf1e8cb TG |
228 | [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", |
229 | [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
fc5ee888 TG |
230 | }; |
231 | ||
c7ed1048 | 232 | static void __init mds_select_mitigation(void) |
fc5ee888 | 233 | { |
7781f6db | 234 | if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { |
fc5ee888 TG |
235 | mds_mitigation = MDS_MITIGATION_OFF; |
236 | return; | |
237 | } | |
238 | ||
239 | if (mds_mitigation == MDS_MITIGATION_FULL) { | |
ebf1e8cb TG |
240 | if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) |
241 | mds_mitigation = MDS_MITIGATION_VMWERV; | |
e2f3c337 | 242 | |
ebf1e8cb | 243 | static_branch_enable(&mds_user_clear); |
e2f3c337 | 244 | |
7781f6db JP |
245 | if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && |
246 | (mds_nosmt || cpu_mitigations_auto_nosmt())) | |
e2f3c337 | 247 | cpu_smt_disable(false); |
fc5ee888 | 248 | } |
e2f3c337 | 249 | |
fc5ee888 TG |
250 | pr_info("%s\n", mds_strings[mds_mitigation]); |
251 | } | |
252 | ||
253 | static int __init mds_cmdline(char *str) | |
254 | { | |
255 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
256 | return 0; | |
257 | ||
258 | if (!str) | |
259 | return -EINVAL; | |
260 | ||
261 | if (!strcmp(str, "off")) | |
262 | mds_mitigation = MDS_MITIGATION_OFF; | |
263 | else if (!strcmp(str, "full")) | |
264 | mds_mitigation = MDS_MITIGATION_FULL; | |
e2f3c337 JP |
265 | else if (!strcmp(str, "full,nosmt")) { |
266 | mds_mitigation = MDS_MITIGATION_FULL; | |
267 | mds_nosmt = true; | |
268 | } | |
fc5ee888 TG |
269 | |
270 | return 0; | |
271 | } | |
272 | early_param("mds", mds_cmdline); | |
273 | ||
aef0bebc TG |
274 | #undef pr_fmt |
275 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
276 | ||
277 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
278 | SPECTRE_V2_NONE; | |
279 | ||
6cd930f0 TG |
280 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
281 | SPECTRE_V2_USER_NONE; | |
282 | ||
e9a556ad | 283 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
284 | static bool spectre_v2_bad_module; |
285 | ||
d280282b AK |
286 | bool retpoline_module_ok(bool has_retpoline) |
287 | { | |
288 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
289 | return true; | |
290 | ||
c8b8e109 | 291 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
292 | spectre_v2_bad_module = true; |
293 | return false; | |
294 | } | |
bb3c2578 TG |
295 | |
296 | static inline const char *spectre_v2_module_string(void) | |
297 | { | |
298 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
299 | } | |
300 | #else | |
301 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 302 | #endif |
da285121 | 303 | |
da285121 DW |
304 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
305 | { | |
306 | int len = strlen(opt); | |
307 | ||
308 | return len == arglen && !strncmp(arg, opt, len); | |
309 | } | |
310 | ||
aef0bebc TG |
311 | /* The kernel command line selection for spectre v2 */ |
312 | enum spectre_v2_mitigation_cmd { | |
313 | SPECTRE_V2_CMD_NONE, | |
314 | SPECTRE_V2_CMD_AUTO, | |
315 | SPECTRE_V2_CMD_FORCE, | |
316 | SPECTRE_V2_CMD_RETPOLINE, | |
317 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
318 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
319 | }; | |
320 | ||
6cd930f0 TG |
321 | enum spectre_v2_user_cmd { |
322 | SPECTRE_V2_USER_CMD_NONE, | |
323 | SPECTRE_V2_USER_CMD_AUTO, | |
324 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 325 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 326 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 327 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 328 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
329 | }; |
330 | ||
331 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
332 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
333 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
334 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
335 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
336 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
337 | }; |
338 | ||
339 | static const struct { | |
340 | const char *option; | |
341 | enum spectre_v2_user_cmd cmd; | |
342 | bool secure; | |
343 | } v2_user_options[] __initdata = { | |
fd1b7023 TG |
344 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
345 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
346 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
347 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
348 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
349 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
350 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
351 | }; |
352 | ||
353 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
354 | { | |
355 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
356 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
357 | } | |
358 | ||
359 | static enum spectre_v2_user_cmd __init | |
360 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
361 | { | |
362 | char arg[20]; | |
363 | int ret, i; | |
364 | ||
365 | switch (v2_cmd) { | |
366 | case SPECTRE_V2_CMD_NONE: | |
367 | return SPECTRE_V2_USER_CMD_NONE; | |
368 | case SPECTRE_V2_CMD_FORCE: | |
369 | return SPECTRE_V2_USER_CMD_FORCE; | |
370 | default: | |
371 | break; | |
372 | } | |
373 | ||
374 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
375 | arg, sizeof(arg)); | |
376 | if (ret < 0) | |
377 | return SPECTRE_V2_USER_CMD_AUTO; | |
378 | ||
379 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
380 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
381 | spec_v2_user_print_cond(v2_user_options[i].option, | |
382 | v2_user_options[i].secure); | |
383 | return v2_user_options[i].cmd; | |
384 | } | |
385 | } | |
386 | ||
387 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
388 | return SPECTRE_V2_USER_CMD_AUTO; | |
389 | } | |
390 | ||
391 | static void __init | |
392 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
393 | { | |
394 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
395 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 396 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
397 | |
398 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
399 | return; | |
400 | ||
401 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
402 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
403 | smt_possible = false; | |
404 | ||
fd1b7023 TG |
405 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
406 | switch (cmd) { | |
6cd930f0 TG |
407 | case SPECTRE_V2_USER_CMD_NONE: |
408 | goto set_mode; | |
409 | case SPECTRE_V2_USER_CMD_FORCE: | |
410 | mode = SPECTRE_V2_USER_STRICT; | |
411 | break; | |
2cdf6a58 | 412 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 413 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
414 | mode = SPECTRE_V2_USER_PRCTL; |
415 | break; | |
1c3cf627 TG |
416 | case SPECTRE_V2_USER_CMD_AUTO: |
417 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 418 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
419 | if (IS_ENABLED(CONFIG_SECCOMP)) |
420 | mode = SPECTRE_V2_USER_SECCOMP; | |
421 | else | |
422 | mode = SPECTRE_V2_USER_PRCTL; | |
423 | break; | |
6cd930f0 TG |
424 | } |
425 | ||
fbed8eca TL |
426 | /* |
427 | * At this point, an STIBP mode other than "off" has been set. | |
428 | * If STIBP support is not being forced, check if STIBP always-on | |
429 | * is preferred. | |
430 | */ | |
431 | if (mode != SPECTRE_V2_USER_STRICT && | |
432 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
433 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
434 | ||
6cd930f0 TG |
435 | /* Initialize Indirect Branch Prediction Barrier */ |
436 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
437 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 438 | |
fd1b7023 TG |
439 | switch (cmd) { |
440 | case SPECTRE_V2_USER_CMD_FORCE: | |
441 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
442 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
443 | static_branch_enable(&switch_mm_always_ibpb); |
444 | break; | |
fd1b7023 TG |
445 | case SPECTRE_V2_USER_CMD_PRCTL: |
446 | case SPECTRE_V2_USER_CMD_AUTO: | |
447 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
448 | static_branch_enable(&switch_mm_cond_ibpb); |
449 | break; | |
58b2d4c8 TG |
450 | default: |
451 | break; | |
452 | } | |
453 | ||
454 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
455 | static_key_enabled(&switch_mm_always_ibpb) ? |
456 | "always-on" : "conditional"); | |
6cd930f0 TG |
457 | } |
458 | ||
8edb388f | 459 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
460 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
461 | return; | |
462 | ||
2cdf6a58 | 463 | /* |
8edb388f | 464 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
465 | * mode. |
466 | */ | |
467 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
468 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
469 | set_mode: |
470 | spectre_v2_user = mode; | |
471 | /* Only print the STIBP mode when SMT possible */ | |
472 | if (smt_possible) | |
473 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
474 | } | |
475 | ||
0eb5928b | 476 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
477 | [SPECTRE_V2_NONE] = "Vulnerable", |
478 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
479 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
480 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
481 | }; | |
482 | ||
17c33e7c KA |
483 | static const struct { |
484 | const char *option; | |
485 | enum spectre_v2_mitigation_cmd cmd; | |
486 | bool secure; | |
5a76cb46 | 487 | } mitigation_options[] __initdata = { |
aef0bebc TG |
488 | { "off", SPECTRE_V2_CMD_NONE, false }, |
489 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
490 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
491 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
492 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
493 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
494 | }; |
495 | ||
10640103 | 496 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 497 | { |
10640103 | 498 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
499 | pr_info("%s selected on command line.\n", reason); |
500 | } | |
501 | ||
da285121 DW |
502 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
503 | { | |
aef0bebc | 504 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 505 | char arg[20]; |
17c33e7c | 506 | int ret, i; |
17c33e7c | 507 | |
2a56e210 JP |
508 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || |
509 | cpu_mitigations_off()) | |
17c33e7c | 510 | return SPECTRE_V2_CMD_NONE; |
17c33e7c | 511 | |
4e8e955a TC |
512 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
513 | if (ret < 0) | |
514 | return SPECTRE_V2_CMD_AUTO; | |
515 | ||
516 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
517 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
518 | continue; | |
519 | cmd = mitigation_options[i].cmd; | |
520 | break; | |
521 | } | |
522 | ||
523 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
524 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
525 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
526 | } |
527 | ||
17c33e7c KA |
528 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
529 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
530 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
531 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 532 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 533 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
534 | } |
535 | ||
536 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
537 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
538 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
539 | return SPECTRE_V2_CMD_AUTO; | |
540 | } | |
541 | ||
10640103 TG |
542 | spec_v2_print_cond(mitigation_options[i].option, |
543 | mitigation_options[i].secure); | |
17c33e7c | 544 | return cmd; |
da285121 DW |
545 | } |
546 | ||
547 | static void __init spectre_v2_select_mitigation(void) | |
548 | { | |
549 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
550 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
551 | ||
552 | /* | |
553 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
554 | * then nothing to do. | |
555 | */ | |
556 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
557 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
558 | return; | |
559 | ||
560 | switch (cmd) { | |
561 | case SPECTRE_V2_CMD_NONE: | |
562 | return; | |
563 | ||
564 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 565 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
566 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
567 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
568 | /* Force it so VMEXIT will restore correctly */ | |
569 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
570 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
571 | goto specv2_set_mode; | |
572 | } | |
d0f293e0 DL |
573 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
574 | goto retpoline_auto; | |
575 | break; | |
da285121 DW |
576 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
577 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
578 | goto retpoline_amd; | |
579 | break; | |
580 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
581 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
582 | goto retpoline_generic; | |
583 | break; | |
584 | case SPECTRE_V2_CMD_RETPOLINE: | |
585 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
586 | goto retpoline_auto; | |
587 | break; | |
588 | } | |
713f1b95 | 589 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
590 | return; |
591 | ||
592 | retpoline_auto: | |
593 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
594 | retpoline_amd: | |
595 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 596 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
597 | goto retpoline_generic; |
598 | } | |
51dd01b5 | 599 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
600 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
601 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
602 | } else { | |
603 | retpoline_generic: | |
51dd01b5 | 604 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
605 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
606 | } | |
607 | ||
1044fde9 | 608 | specv2_set_mode: |
da285121 DW |
609 | spectre_v2_enabled = mode; |
610 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
611 | |
612 | /* | |
14623a43 JK |
613 | * If spectre v2 protection has been enabled, unconditionally fill |
614 | * RSB during a context switch; this protects against two independent | |
615 | * issues: | |
c995efd5 | 616 | * |
14623a43 JK |
617 | * - RSB underflow (and switch to BTB) on Skylake+ |
618 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 619 | */ |
14623a43 JK |
620 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
621 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 622 | |
390b99c3 DW |
623 | /* |
624 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
625 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
626 | * speculation around firmware calls only when Enhanced IBRS isn't | |
627 | * supported. | |
628 | * | |
629 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
630 | * the user might select retpoline on the kernel command line and if | |
631 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
632 | * enable IBRS around firmware calls. | |
390b99c3 | 633 | */ |
1044fde9 | 634 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
635 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
636 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
637 | } | |
7011f443 | 638 | |
6cd930f0 TG |
639 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
640 | spectre_v2_user_select_mitigation(cmd); | |
da285121 DW |
641 | } |
642 | ||
984d266f | 643 | static void update_stibp_msr(void * __unused) |
aef0bebc | 644 | { |
984d266f | 645 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
646 | } |
647 | ||
984d266f TG |
648 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
649 | static void update_stibp_strict(void) | |
aef0bebc | 650 | { |
984d266f TG |
651 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
652 | ||
653 | if (sched_smt_active()) | |
654 | mask |= SPEC_CTRL_STIBP; | |
655 | ||
656 | if (mask == x86_spec_ctrl_base) | |
657 | return; | |
658 | ||
659 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
660 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
661 | x86_spec_ctrl_base = mask; | |
662 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
663 | } |
664 | ||
2cdf6a58 TG |
665 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
666 | static void update_indir_branch_cond(void) | |
667 | { | |
668 | if (sched_smt_active()) | |
669 | static_branch_enable(&switch_to_cond_stibp); | |
670 | else | |
671 | static_branch_disable(&switch_to_cond_stibp); | |
672 | } | |
673 | ||
0923e77e JP |
674 | #undef pr_fmt |
675 | #define pr_fmt(fmt) fmt | |
676 | ||
fc5ee888 TG |
677 | /* Update the static key controlling the MDS CPU buffer clear in idle */ |
678 | static void update_mds_branch_idle(void) | |
679 | { | |
680 | /* | |
c7ed1048 TH |
681 | * Enable the idle clearing if SMT is active on CPUs which are |
682 | * affected only by MSBDS and not any other MDS variant. | |
683 | * | |
684 | * The other variants cannot be mitigated when SMT is enabled, so | |
685 | * clearing the buffers on idle just to prevent the Store Buffer | |
686 | * repartitioning leak would be a window dressing exercise. | |
fc5ee888 | 687 | */ |
c7ed1048 | 688 | if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) |
fc5ee888 TG |
689 | return; |
690 | ||
691 | if (sched_smt_active()) | |
692 | static_branch_enable(&mds_idle_clear); | |
693 | else | |
694 | static_branch_disable(&mds_idle_clear); | |
695 | } | |
696 | ||
0923e77e JP |
697 | #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" |
698 | ||
aef0bebc TG |
699 | void arch_smt_update(void) |
700 | { | |
984d266f TG |
701 | /* Enhanced IBRS implies STIBP. No update required. */ |
702 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
703 | return; |
704 | ||
705 | mutex_lock(&spec_ctrl_mutex); | |
706 | ||
984d266f TG |
707 | switch (spectre_v2_user) { |
708 | case SPECTRE_V2_USER_NONE: | |
709 | break; | |
710 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 711 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
712 | update_stibp_strict(); |
713 | break; | |
ac40ad3b | 714 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 715 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 716 | update_indir_branch_cond(); |
ac40ad3b | 717 | break; |
aef0bebc | 718 | } |
984d266f | 719 | |
c7ed1048 | 720 | switch (mds_mitigation) { |
ebf1e8cb TG |
721 | case MDS_MITIGATION_FULL: |
722 | case MDS_MITIGATION_VMWERV: | |
0923e77e JP |
723 | if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) |
724 | pr_warn_once(MDS_MSG_SMT); | |
fc5ee888 | 725 | update_mds_branch_idle(); |
ebf1e8cb TG |
726 | break; |
727 | case MDS_MITIGATION_OFF: | |
728 | break; | |
729 | } | |
fc5ee888 | 730 | |
aef0bebc TG |
731 | mutex_unlock(&spec_ctrl_mutex); |
732 | } | |
733 | ||
e63490c8 KRW |
734 | #undef pr_fmt |
735 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
736 | ||
b5e6d77d | 737 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
738 | |
739 | /* The kernel command line selection */ | |
740 | enum ssb_mitigation_cmd { | |
741 | SPEC_STORE_BYPASS_CMD_NONE, | |
742 | SPEC_STORE_BYPASS_CMD_AUTO, | |
743 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 744 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 745 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
746 | }; |
747 | ||
0eb5928b | 748 | static const char * const ssb_strings[] = { |
e63490c8 | 749 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 750 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
751 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
752 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
753 | }; |
754 | ||
755 | static const struct { | |
756 | const char *option; | |
757 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 758 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
759 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
760 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
761 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
762 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
763 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
764 | }; |
765 | ||
766 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
767 | { | |
768 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
769 | char arg[20]; | |
770 | int ret, i; | |
771 | ||
2a56e210 JP |
772 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || |
773 | cpu_mitigations_off()) { | |
e63490c8 KRW |
774 | return SPEC_STORE_BYPASS_CMD_NONE; |
775 | } else { | |
776 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
777 | arg, sizeof(arg)); | |
778 | if (ret < 0) | |
779 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
780 | ||
781 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
782 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
783 | continue; | |
784 | ||
785 | cmd = ssb_mitigation_options[i].cmd; | |
786 | break; | |
787 | } | |
788 | ||
789 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
790 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
791 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
792 | } | |
793 | } | |
794 | ||
795 | return cmd; | |
796 | } | |
797 | ||
dbe3009d | 798 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
799 | { |
800 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
801 | enum ssb_mitigation_cmd cmd; | |
802 | ||
8fe36c9d | 803 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
804 | return mode; |
805 | ||
806 | cmd = ssb_parse_cmdline(); | |
807 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
808 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
809 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
810 | return mode; | |
811 | ||
812 | switch (cmd) { | |
813 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
814 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
815 | /* | |
816 | * Choose prctl+seccomp as the default mode if seccomp is | |
817 | * enabled. | |
818 | */ | |
819 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
820 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
821 | else | |
822 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 823 | break; |
e63490c8 KRW |
824 | case SPEC_STORE_BYPASS_CMD_ON: |
825 | mode = SPEC_STORE_BYPASS_DISABLE; | |
826 | break; | |
574dcf89 TG |
827 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
828 | mode = SPEC_STORE_BYPASS_PRCTL; | |
829 | break; | |
e63490c8 KRW |
830 | case SPEC_STORE_BYPASS_CMD_NONE: |
831 | break; | |
832 | } | |
833 | ||
23b9eab9 KRW |
834 | /* |
835 | * We have three CPU feature flags that are in play here: | |
836 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 837 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
838 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
839 | */ | |
574dcf89 | 840 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 841 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 842 | /* |
3b881627 KRW |
843 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
844 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 845 | */ |
5005c716 TL |
846 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
847 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 848 | x86_amd_ssb_disable(); |
5005c716 | 849 | } else { |
8fe36c9d | 850 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 851 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 852 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
853 | } |
854 | } | |
855 | ||
e63490c8 KRW |
856 | return mode; |
857 | } | |
858 | ||
043d480e | 859 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
860 | { |
861 | ssb_mode = __ssb_select_mitigation(); | |
862 | ||
863 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
864 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
865 | } | |
866 | ||
da285121 | 867 | #undef pr_fmt |
c7416003 | 868 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 869 | |
801d6893 | 870 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 871 | { |
801d6893 TG |
872 | /* Force the update of the real TIF bits */ |
873 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
874 | |
875 | /* | |
876 | * Immediately update the speculation control MSRs for the current | |
877 | * task, but for a non-current task delay setting the CPU | |
878 | * mitigation until it is scheduled next. | |
879 | * | |
880 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
881 | * always the current task. | |
882 | */ | |
801d6893 | 883 | if (tsk == current) |
d4595948 TG |
884 | speculation_ctrl_update_current(); |
885 | } | |
886 | ||
887 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
888 | { | |
c7416003 KC |
889 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
890 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
891 | return -ENXIO; |
892 | ||
733f4234 TG |
893 | switch (ctrl) { |
894 | case PR_SPEC_ENABLE: | |
895 | /* If speculation is force disabled, enable is not allowed */ | |
896 | if (task_spec_ssb_force_disable(task)) | |
897 | return -EPERM; | |
898 | task_clear_spec_ssb_disable(task); | |
801d6893 | 899 | task_update_spec_tif(task); |
733f4234 TG |
900 | break; |
901 | case PR_SPEC_DISABLE: | |
902 | task_set_spec_ssb_disable(task); | |
801d6893 | 903 | task_update_spec_tif(task); |
733f4234 TG |
904 | break; |
905 | case PR_SPEC_FORCE_DISABLE: | |
906 | task_set_spec_ssb_disable(task); | |
907 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 908 | task_update_spec_tif(task); |
733f4234 TG |
909 | break; |
910 | default: | |
911 | return -ERANGE; | |
912 | } | |
574dcf89 TG |
913 | return 0; |
914 | } | |
915 | ||
ac40ad3b TG |
916 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
917 | { | |
918 | switch (ctrl) { | |
919 | case PR_SPEC_ENABLE: | |
920 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
921 | return 0; | |
922 | /* | |
923 | * Indirect branch speculation is always disabled in strict | |
924 | * mode. | |
925 | */ | |
fbed8eca TL |
926 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
927 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
928 | return -EPERM; |
929 | task_clear_spec_ib_disable(task); | |
930 | task_update_spec_tif(task); | |
931 | break; | |
932 | case PR_SPEC_DISABLE: | |
933 | case PR_SPEC_FORCE_DISABLE: | |
934 | /* | |
935 | * Indirect branch speculation is always allowed when | |
936 | * mitigation is force disabled. | |
937 | */ | |
938 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
939 | return -EPERM; | |
fbed8eca TL |
940 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
941 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
942 | return 0; |
943 | task_set_spec_ib_disable(task); | |
944 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
945 | task_set_spec_ib_force_disable(task); | |
946 | task_update_spec_tif(task); | |
947 | break; | |
948 | default: | |
949 | return -ERANGE; | |
950 | } | |
951 | return 0; | |
952 | } | |
953 | ||
5b38e244 TG |
954 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
955 | unsigned long ctrl) | |
956 | { | |
957 | switch (which) { | |
958 | case PR_SPEC_STORE_BYPASS: | |
959 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
960 | case PR_SPEC_INDIRECT_BRANCH: |
961 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
962 | default: |
963 | return -ENODEV; | |
964 | } | |
965 | } | |
966 | ||
967 | #ifdef CONFIG_SECCOMP | |
968 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
969 | { | |
c7416003 KC |
970 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
971 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
972 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
973 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
974 | } |
975 | #endif | |
976 | ||
199bfed2 | 977 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
978 | { |
979 | switch (ssb_mode) { | |
980 | case SPEC_STORE_BYPASS_DISABLE: | |
981 | return PR_SPEC_DISABLE; | |
c7416003 | 982 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 983 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
984 | if (task_spec_ssb_force_disable(task)) |
985 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
986 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
987 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
988 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
989 | default: | |
990 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
991 | return PR_SPEC_ENABLE; | |
992 | return PR_SPEC_NOT_AFFECTED; | |
993 | } | |
994 | } | |
995 | ||
ac40ad3b TG |
996 | static int ib_prctl_get(struct task_struct *task) |
997 | { | |
998 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
999 | return PR_SPEC_NOT_AFFECTED; | |
1000 | ||
1001 | switch (spectre_v2_user) { | |
1002 | case SPECTRE_V2_USER_NONE: | |
1003 | return PR_SPEC_ENABLE; | |
1004 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 1005 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
1006 | if (task_spec_ib_force_disable(task)) |
1007 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1008 | if (task_spec_ib_disable(task)) | |
1009 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
1010 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1011 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 1012 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
1013 | return PR_SPEC_DISABLE; |
1014 | default: | |
1015 | return PR_SPEC_NOT_AFFECTED; | |
1016 | } | |
1017 | } | |
1018 | ||
199bfed2 | 1019 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
1020 | { |
1021 | switch (which) { | |
1022 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 1023 | return ssb_prctl_get(task); |
ac40ad3b TG |
1024 | case PR_SPEC_INDIRECT_BRANCH: |
1025 | return ib_prctl_get(task); | |
574dcf89 TG |
1026 | default: |
1027 | return -ENODEV; | |
1028 | } | |
1029 | } | |
1030 | ||
23b9eab9 KRW |
1031 | void x86_spec_ctrl_setup_ap(void) |
1032 | { | |
50f9b919 | 1033 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 1034 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
1035 | |
1036 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 1037 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
1038 | } |
1039 | ||
73ca9f47 KRW |
1040 | #undef pr_fmt |
1041 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 1042 | |
24fcb53c JK |
1043 | /* Default mitigation for L1TF-affected CPUs */ |
1044 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 1045 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
1046 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1047 | ||
522c7bed | 1048 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
1049 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
1050 | #endif | |
1051 | ||
f1f016ed AK |
1052 | /* |
1053 | * These CPUs all support 44bits physical address space internally in the | |
1054 | * cache but CPUID can report a smaller number of physical address bits. | |
1055 | * | |
1056 | * The L1TF mitigation uses the top most address bit for the inversion of | |
1057 | * non present PTEs. When the installed memory reaches into the top most | |
1058 | * address bit due to memory holes, which has been observed on machines | |
1059 | * which report 36bits physical address bits and have 32G RAM installed, | |
1060 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
1061 | * This is a false positive because the mitigation is still possible due to | |
1062 | * the fact that the cache uses 44bit internally. Use the cache bits | |
1063 | * instead of the reported physical bits and adjust them on the affected | |
1064 | * machines to 44bit if the reported bits are less than 44. | |
1065 | */ | |
1066 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
1067 | { | |
1068 | if (c->x86 != 6) | |
1069 | return; | |
1070 | ||
1071 | switch (c->x86_model) { | |
1072 | case INTEL_FAM6_NEHALEM: | |
1073 | case INTEL_FAM6_WESTMERE: | |
1074 | case INTEL_FAM6_SANDYBRIDGE: | |
1075 | case INTEL_FAM6_IVYBRIDGE: | |
1076 | case INTEL_FAM6_HASWELL_CORE: | |
1077 | case INTEL_FAM6_HASWELL_ULT: | |
1078 | case INTEL_FAM6_HASWELL_GT3E: | |
1079 | case INTEL_FAM6_BROADWELL_CORE: | |
1080 | case INTEL_FAM6_BROADWELL_GT3E: | |
1081 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
1082 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
1083 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
1084 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
1085 | if (c->x86_cache_bits < 44) | |
1086 | c->x86_cache_bits = 44; | |
1087 | break; | |
1088 | } | |
1089 | } | |
1090 | ||
73ca9f47 KRW |
1091 | static void __init l1tf_select_mitigation(void) |
1092 | { | |
1093 | u64 half_pa; | |
1094 | ||
1095 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1096 | return; | |
1097 | ||
2a56e210 JP |
1098 | if (cpu_mitigations_off()) |
1099 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1100 | else if (cpu_mitigations_auto_nosmt()) | |
1101 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1102 | ||
f1f016ed AK |
1103 | override_cache_bits(&boot_cpu_data); |
1104 | ||
24fcb53c JK |
1105 | switch (l1tf_mitigation) { |
1106 | case L1TF_MITIGATION_OFF: | |
1107 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1108 | case L1TF_MITIGATION_FLUSH: | |
1109 | break; | |
1110 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1111 | case L1TF_MITIGATION_FULL: | |
1112 | cpu_smt_disable(false); | |
1113 | break; | |
1114 | case L1TF_MITIGATION_FULL_FORCE: | |
1115 | cpu_smt_disable(true); | |
1116 | break; | |
1117 | } | |
1118 | ||
73ca9f47 KRW |
1119 | #if CONFIG_PGTABLE_LEVELS == 2 |
1120 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1121 | return; | |
1122 | #endif | |
1123 | ||
73ca9f47 KRW |
1124 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
1125 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
1126 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
f80e341a VB |
1127 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1128 | half_pa); | |
1129 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
c7ed1048 | 1130 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); |
73ca9f47 KRW |
1131 | return; |
1132 | } | |
1133 | ||
1134 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1135 | } | |
24fcb53c JK |
1136 | |
1137 | static int __init l1tf_cmdline(char *str) | |
1138 | { | |
1139 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1140 | return 0; | |
1141 | ||
1142 | if (!str) | |
1143 | return -EINVAL; | |
1144 | ||
1145 | if (!strcmp(str, "off")) | |
1146 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1147 | else if (!strcmp(str, "flush,nowarn")) | |
1148 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1149 | else if (!strcmp(str, "flush")) | |
1150 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1151 | else if (!strcmp(str, "flush,nosmt")) | |
1152 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1153 | else if (!strcmp(str, "full")) | |
1154 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1155 | else if (!strcmp(str, "full,force")) | |
1156 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | early_param("l1tf", l1tf_cmdline); | |
1161 | ||
73ca9f47 | 1162 | #undef pr_fmt |
0923e77e | 1163 | #define pr_fmt(fmt) fmt |
73ca9f47 | 1164 | |
61dc0f55 | 1165 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1166 | |
b9cfedcd TG |
1167 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1168 | ||
1169 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1170 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1171 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1172 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1173 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1174 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1175 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1176 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1177 | }; |
1178 | ||
1179 | static ssize_t l1tf_show_state(char *buf) | |
1180 | { | |
1181 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1182 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1183 | ||
3899f7b1 PB |
1184 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1185 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1186 | sched_smt_active())) { |
3899f7b1 PB |
1187 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1188 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1189 | } |
3899f7b1 PB |
1190 | |
1191 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1192 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1193 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1194 | } |
1195 | #else | |
1196 | static ssize_t l1tf_show_state(char *buf) | |
1197 | { | |
1198 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1199 | } | |
1200 | #endif | |
1201 | ||
1122cc78 TG |
1202 | static ssize_t mds_show_state(char *buf) |
1203 | { | |
1204 | if (!hypervisor_is_type(X86_HYPER_NATIVE)) { | |
1205 | return sprintf(buf, "%s; SMT Host state unknown\n", | |
1206 | mds_strings[mds_mitigation]); | |
1207 | } | |
1208 | ||
1209 | if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { | |
1210 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
5c89a99c KRW |
1211 | (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : |
1212 | sched_smt_active() ? "mitigated" : "disabled")); | |
1122cc78 TG |
1213 | } |
1214 | ||
1215 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1216 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1217 | } | |
1218 | ||
2daa53e8 TC |
1219 | static char *stibp_state(void) |
1220 | { | |
4a8d91c8 TC |
1221 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1222 | return ""; | |
1223 | ||
6cd930f0 TG |
1224 | switch (spectre_v2_user) { |
1225 | case SPECTRE_V2_USER_NONE: | |
1226 | return ", STIBP: disabled"; | |
1227 | case SPECTRE_V2_USER_STRICT: | |
1228 | return ", STIBP: forced"; | |
fbed8eca TL |
1229 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1230 | return ", STIBP: always-on"; | |
ac40ad3b | 1231 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1232 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1233 | if (static_key_enabled(&switch_to_cond_stibp)) |
1234 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1235 | } |
1236 | return ""; | |
2daa53e8 TC |
1237 | } |
1238 | ||
1239 | static char *ibpb_state(void) | |
1240 | { | |
58b2d4c8 | 1241 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1242 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1243 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1244 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1245 | return ", IBPB: conditional"; | |
1246 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1247 | } |
1248 | return ""; | |
2daa53e8 TC |
1249 | } |
1250 | ||
ace051d5 | 1251 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1252 | char *buf, unsigned int bug) |
61dc0f55 | 1253 | { |
d2b8fc2d | 1254 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1255 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1256 | |
1257 | switch (bug) { | |
1258 | case X86_BUG_CPU_MELTDOWN: | |
1259 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1260 | return sprintf(buf, "Mitigation: PTI\n"); | |
1261 | ||
1262 | break; | |
1263 | ||
1264 | case X86_BUG_SPECTRE_V1: | |
1265 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1266 | ||
1267 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1268 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1269 | ibpb_state(), |
d2b8fc2d | 1270 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1271 | stibp_state(), |
5e2fafd5 | 1272 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1273 | spectre_v2_module_string()); |
1274 | ||
e63490c8 KRW |
1275 | case X86_BUG_SPEC_STORE_BYPASS: |
1276 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1277 | ||
05516ad8 AK |
1278 | case X86_BUG_L1TF: |
1279 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1280 | return l1tf_show_state(buf); |
05516ad8 | 1281 | break; |
1122cc78 TG |
1282 | |
1283 | case X86_BUG_MDS: | |
1284 | return mds_show_state(buf); | |
1285 | ||
d2b8fc2d KRW |
1286 | default: |
1287 | break; | |
1288 | } | |
1289 | ||
61dc0f55 TG |
1290 | return sprintf(buf, "Vulnerable\n"); |
1291 | } | |
1292 | ||
d2b8fc2d KRW |
1293 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1294 | { | |
1295 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1296 | } | |
1297 | ||
713f1b95 | 1298 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1299 | { |
d2b8fc2d | 1300 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1301 | } |
1302 | ||
713f1b95 | 1303 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1304 | { |
d2b8fc2d | 1305 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1306 | } |
d7de9182 KRW |
1307 | |
1308 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1309 | { | |
1310 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1311 | } | |
05516ad8 AK |
1312 | |
1313 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1314 | { | |
1315 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1316 | } | |
1122cc78 TG |
1317 | |
1318 | ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) | |
1319 | { | |
1320 | return cpu_show_common(dev, attr, buf, X86_BUG_MDS); | |
1321 | } | |
61dc0f55 | 1322 | #endif |