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KVM: SVM: Add MSR-based feature support for serializing LFENCE
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
3de1e176 113unsigned int min_timer_period_us = 200;
9ed96e87
MT		 114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
f0ace387 187 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 200 { NULL }
201};
202
2acf923e
DC		 203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN		 207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK		 214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK		 217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA		 220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK		 237 }
238 }
18863bdd
AK		 239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY		 247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK		 270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH		 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK		 288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK		 294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT		 299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO		 306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK		 312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM		 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO		 332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED		 342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA		 363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED		 391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK		 395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA		 399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL		 401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED		 416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED		 440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK		 450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR		 456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP		 464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH		 467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP		 470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL		 476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK		 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 492
493 return fault->nested_page_fault;
d4f8cf66
JR		 494}
495
3419ffc8
SY		 496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK		 498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK		 503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR		 509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK		 515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK		 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA		 528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR		 538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR		 548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO		 569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR		 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO		 603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR		 612 int offset;
613 gfn_t gfn;
d835dfec
AK		 614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK		 619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB		 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK		 631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK		 641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN		 644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN		 646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN		 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN		 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO		 655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 659 int cs_db, cs_l;
660
0f12244f
GN		 661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 664 if (cs_l)
665 return 1;
a03490ed
CO		 666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO		 671 }
672
ad756a16
MJ		 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY		 683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE		 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN		 691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT		 701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709}
710
711static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712{
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718}
719
69b0049a 720static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 721{
56c103ec
LJ		 722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 724 u64 valid_bits;
2acf923e
DC		 725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
d91cab78 729 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 730 return 1;
d91cab78 731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 732 return 1;
46c34cb0
PB		 733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
d91cab78 739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 740 if (xcr0 & ~valid_bits)
2acf923e 741 return 1;
46c34cb0 742
d91cab78
DH		 743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 745 return 1;
746
d91cab78
DH		 747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 749 return 1;
d91cab78 750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 751 return 1;
752 }
2acf923e 753 vcpu->arch.xcr0 = xcr0;
56c103ec 754
d91cab78 755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 756 kvm_update_cpuid(vcpu);
2acf923e
DC		 757 return 0;
758}
759
760int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761{
764bcbc5
Z		 762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768}
769EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
a83b29c6 771int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 772{
fc78f519 773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 776
0f12244f
GN		 777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
a03490ed 779
d6321d49 780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 781 return 1;
782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 793 return 1;
794
fd8cb433 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 796 return 1;
797
df9b1e03
PB		 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
799 return 1;
800
a03490ed 801 if (is_long_mode(vcpu)) {
0f12244f
GN		 802 if (!(cr4 & X86_CR4_PAE))
803 return 1;
a2edf57f
AK		 804 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
805 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 806 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
807 kvm_read_cr3(vcpu)))
0f12244f
GN		 808 return 1;
809
ad756a16 810 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 811 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 812 return 1;
813
814 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
815 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
816 return 1;
817 }
818
5e1746d6 819 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 820 return 1;
a03490ed 821
ad756a16
MJ		 822 if (((cr4 ^ old_cr4) & pdptr_bits) ||
823 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 824 kvm_mmu_reset_context(vcpu);
0f12244f 825
b9baba86 826 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 827 kvm_update_cpuid(vcpu);
2acf923e 828
0f12244f
GN		 829 return 0;
830}
2d3ad1f4 831EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 832
2390218b 833int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 834{
ac146235 835#ifdef CONFIG_X86_64
9d88fca7 836 cr3 &= ~CR3_PCID_INVD;
ac146235 837#endif
9d88fca7 838
9f8fe504 839 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 840 kvm_mmu_sync_roots(vcpu);
77c3913b 841 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 842 return 0;
d835dfec
AK		 843 }
844
d1cd3ce9 845 if (is_long_mode(vcpu) &&
c7df6072 846 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 847 return 1;
848 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 849 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 850 return 1;
a03490ed 851
0f12244f 852 vcpu->arch.cr3 = cr3;
aff48baa 853 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 854 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 855 return 0;
856}
2d3ad1f4 857EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 858
eea1cff9 859int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 860{
0f12244f
GN		 861 if (cr8 & CR8_RESERVED_BITS)
862 return 1;
35754c98 863 if (lapic_in_kernel(vcpu))
a03490ed
CO		 864 kvm_lapic_set_tpr(vcpu, cr8);
865 else
ad312c7c 866 vcpu->arch.cr8 = cr8;
0f12244f
GN		 867 return 0;
868}
2d3ad1f4 869EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 870
2d3ad1f4 871unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 872{
35754c98 873 if (lapic_in_kernel(vcpu))
a03490ed
CO		 874 return kvm_lapic_get_cr8(vcpu);
875 else
ad312c7c 876 return vcpu->arch.cr8;
a03490ed 877}
2d3ad1f4 878EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 879
ae561ede
NA		 880static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
881{
882 int i;
883
884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
885 for (i = 0; i < KVM_NR_DB_REGS; i++)
886 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
887 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
888 }
889}
890
73aaf249
JK		 891static void kvm_update_dr6(struct kvm_vcpu *vcpu)
892{
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
895}
896
c8639010
JK		 897static void kvm_update_dr7(struct kvm_vcpu *vcpu)
898{
899 unsigned long dr7;
900
901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 dr7 = vcpu->arch.guest_debug_dr7;
903 else
904 dr7 = vcpu->arch.dr7;
905 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 906 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
907 if (dr7 & DR7_BP_EN_MASK)
908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 909}
910
6f43ed01
NA		 911static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
912{
913 u64 fixed = DR6_FIXED_1;
914
d6321d49 915 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 916 fixed |= DR6_RTM;
917 return fixed;
918}
919
338dbc97 920static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 921{
922 switch (dr) {
923 case 0 ... 3:
924 vcpu->arch.db[dr] = val;
925 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
926 vcpu->arch.eff_db[dr] = val;
927 break;
928 case 4:
020df079
GN		 929 /* fall through */
930 case 6:
338dbc97
GN		 931 if (val & 0xffffffff00000000ULL)
932 return -1; /* #GP */
6f43ed01 933 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 934 kvm_update_dr6(vcpu);
020df079
GN		 935 break;
936 case 5:
020df079
GN		 937 /* fall through */
938 default: /* 7 */
338dbc97
GN		 939 if (val & 0xffffffff00000000ULL)
940 return -1; /* #GP */
020df079 941 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 942 kvm_update_dr7(vcpu);
020df079
GN		 943 break;
944 }
945
946 return 0;
947}
338dbc97
GN		 948
949int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
950{
16f8a6f9 951 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 952 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 953 return 1;
954 }
955 return 0;
338dbc97 956}
020df079
GN		 957EXPORT_SYMBOL_GPL(kvm_set_dr);
958
16f8a6f9 959int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 960{
961 switch (dr) {
962 case 0 ... 3:
963 *val = vcpu->arch.db[dr];
964 break;
965 case 4:
020df079
GN		 966 /* fall through */
967 case 6:
73aaf249
JK		 968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
969 *val = vcpu->arch.dr6;
970 else
971 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 972 break;
973 case 5:
020df079
GN		 974 /* fall through */
975 default: /* 7 */
976 *val = vcpu->arch.dr7;
977 break;
978 }
338dbc97
GN		 979 return 0;
980}
020df079
GN		 981EXPORT_SYMBOL_GPL(kvm_get_dr);
982
022cd0e8
AK		 983bool kvm_rdpmc(struct kvm_vcpu *vcpu)
984{
985 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
986 u64 data;
987 int err;
988
c6702c9d 989 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 990 if (err)
991 return err;
992 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
993 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
994 return err;
995}
996EXPORT_SYMBOL_GPL(kvm_rdpmc);
997
043405e1
CO		 998/*
999 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1000 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1001 *
1002 * This list is modified at module load time to reflect the
e3267cbb 1003 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1004 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1005 * may depend on host virtualization features rather than host cpu features.
043405e1 1006 */
e3267cbb 1007
043405e1
CO		 1008static u32 msrs_to_save[] = {
1009 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1010 MSR_STAR,
043405e1
CO		 1011#ifdef CONFIG_X86_64
1012 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1013#endif
b3897a49 1014 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1015 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
74469996 1016 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1017};
1018
1019static unsigned num_msrs_to_save;
1020
62ef68bb
PB		 1021static u32 emulated_msrs[] = {
1022 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1023 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1024 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1025 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1026 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1027 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1028 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1029 HV_X64_MSR_RESET,
11c4b1ca 1030 HV_X64_MSR_VP_INDEX,
9eec50b8 1031 HV_X64_MSR_VP_RUNTIME,
5c919412 1032 HV_X64_MSR_SCONTROL,
1f4b34f8 1033 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1034 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1035 MSR_KVM_PV_EOI_EN,
1036
ba904635 1037 MSR_IA32_TSC_ADJUST,
a3e06bbe 1038 MSR_IA32_TSCDEADLINE,
043405e1 1039 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1040 MSR_IA32_MCG_STATUS,
1041 MSR_IA32_MCG_CTL,
c45dcc71 1042 MSR_IA32_MCG_EXT_CTL,
64d60670 1043 MSR_IA32_SMBASE,
db2336a8
KH		 1044 MSR_PLATFORM_INFO,
1045 MSR_MISC_FEATURES_ENABLES,
4d5c8a07 1046 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1047};
1048
62ef68bb
PB		 1049static unsigned num_emulated_msrs;
1050
ab1bebf8
TL		 1051/*
1052 * List of msr numbers which are used to expose MSR-based features that
1053 * can be used by a hypervisor to validate requested CPU features.
1054 */
1055static u32 msr_based_features[] = {
09c0663d 1056 MSR_F10H_DECFG,
47ae8501 1057 MSR_IA32_ARCH_CAPABILITIES,
ab1bebf8
TL		 1058};
1059
1060static unsigned int num_msr_based_features;
1061
1ccd9994
PB		 1062u64 kvm_get_arch_capabilities(void)
1063{
1064 u64 data;
1065
1066 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1067
1068 /*
1069 * If we're doing cache flushes (either "always" or "cond")
1070 * we will do one whenever the guest does a vmlaunch/vmresume.
1071 * If an outer hypervisor is doing the cache flush for us
1072 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1073 * capability to the guest too, and if EPT is disabled we're not
1074 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1075 * require a nested hypervisor to do a flush of its own.
1076 */
1077 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1078 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1079
1080 return data;
1081}
1082EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1083
08215b9d
WL		 1084static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1085{
1086 switch (msr->index) {
47ae8501 1087 case MSR_IA32_ARCH_CAPABILITIES:
1ccd9994 1088 msr->data = kvm_get_arch_capabilities();
47ae8501 1089 break;
08215b9d
WL		 1090 default:
1091 if (kvm_x86_ops->get_msr_feature(msr))
1092 return 1;
1093 }
1094 return 0;
1095}
1096
ab1bebf8
TL		 1097static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1098{
1099 struct kvm_msr_entry msr;
08215b9d 1100 int r;
ab1bebf8
TL		 1101
1102 msr.index = index;
08215b9d
WL		 1103 r = kvm_get_msr_feature(&msr);
1104 if (r)
1105 return r;
ab1bebf8
TL		 1106
1107 *data = msr.data;
1108
1109 return 0;
1110}
1111
384bb783 1112bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1113{
b69e8cae 1114 if (efer & efer_reserved_bits)
384bb783 1115 return false;
15c4a640 1116
1b4d56b8 1117 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1118 return false;
1b2fd70c 1119
1b4d56b8 1120 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1121 return false;
d8017474 1122
384bb783
JK		 1123 return true;
1124}
1125EXPORT_SYMBOL_GPL(kvm_valid_efer);
1126
1127static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1128{
1129 u64 old_efer = vcpu->arch.efer;
1130
1131 if (!kvm_valid_efer(vcpu, efer))
1132 return 1;
1133
1134 if (is_paging(vcpu)
1135 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1136 return 1;
1137
15c4a640 1138 efer &= ~EFER_LMA;
f6801dff 1139 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1140
a3d204e2
SY		 1141 kvm_x86_ops->set_efer(vcpu, efer);
1142
aad82703
SY		 1143 /* Update reserved bits */
1144 if ((efer ^ old_efer) & EFER_NX)
1145 kvm_mmu_reset_context(vcpu);
1146
b69e8cae 1147 return 0;
15c4a640
CO		 1148}
1149
f2b4b7dd
JR		 1150void kvm_enable_efer_bits(u64 mask)
1151{
1152 efer_reserved_bits &= ~mask;
1153}
1154EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1155
15c4a640
CO		 1156/*
1157 * Writes msr value into into the appropriate "register".
1158 * Returns 0 on success, non-0 otherwise.
1159 * Assumes vcpu_load() was already called.
1160 */
8fe8ab46 1161int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1162{
854e8bb1
NA		 1163 switch (msr->index) {
1164 case MSR_FS_BASE:
1165 case MSR_GS_BASE:
1166 case MSR_KERNEL_GS_BASE:
1167 case MSR_CSTAR:
1168 case MSR_LSTAR:
fd8cb433 1169 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1170 return 1;
1171 break;
1172 case MSR_IA32_SYSENTER_EIP:
1173 case MSR_IA32_SYSENTER_ESP:
1174 /*
1175 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1176 * non-canonical address is written on Intel but not on
1177 * AMD (which ignores the top 32-bits, because it does
1178 * not implement 64-bit SYSENTER).
1179 *
1180 * 64-bit code should hence be able to write a non-canonical
1181 * value on AMD. Making the address canonical ensures that
1182 * vmentry does not fail on Intel after writing a non-canonical
1183 * value, and that something deterministic happens if the guest
1184 * invokes 64-bit SYSENTER.
1185 */
fd8cb433 1186 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1187 }
8fe8ab46 1188 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1189}
854e8bb1 1190EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1191
313a3dc7
CO		 1192/*
1193 * Adapt set_msr() to msr_io()'s calling convention
1194 */
609e36d3
PB		 1195static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1196{
1197 struct msr_data msr;
1198 int r;
1199
1200 msr.index = index;
1201 msr.host_initiated = true;
1202 r = kvm_get_msr(vcpu, &msr);
1203 if (r)
1204 return r;
1205
1206 *data = msr.data;
1207 return 0;
1208}
1209
313a3dc7
CO		 1210static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1211{
8fe8ab46
WA		 1212 struct msr_data msr;
1213
1214 msr.data = *data;
1215 msr.index = index;
1216 msr.host_initiated = true;
1217 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1218}
1219
16e8d74d
MT		 1220#ifdef CONFIG_X86_64
1221struct pvclock_gtod_data {
1222 seqcount_t seq;
1223
1224 struct { /* extract of a clocksource struct */
1225 int vclock_mode;
a5a1d1c2
TG		 1226 u64 cycle_last;
1227 u64 mask;
16e8d74d
MT		 1228 u32 mult;
1229 u32 shift;
1230 } clock;
1231
cbcf2dd3
TG		 1232 u64 boot_ns;
1233 u64 nsec_base;
55dd00a7 1234 u64 wall_time_sec;
16e8d74d
MT		 1235};
1236
1237static struct pvclock_gtod_data pvclock_gtod_data;
1238
1239static void update_pvclock_gtod(struct timekeeper *tk)
1240{
1241 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1242 u64 boot_ns;
1243
876e7881 1244 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1245
1246 write_seqcount_begin(&vdata->seq);
1247
1248 /* copy pvclock gtod data */
876e7881
PZ		 1249 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1250 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1251 vdata->clock.mask = tk->tkr_mono.mask;
1252 vdata->clock.mult = tk->tkr_mono.mult;
1253 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1254
cbcf2dd3 1255 vdata->boot_ns = boot_ns;
876e7881 1256 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1257
55dd00a7
MT		 1258 vdata->wall_time_sec = tk->xtime_sec;
1259
16e8d74d
MT		 1260 write_seqcount_end(&vdata->seq);
1261}
1262#endif
1263
bab5bb39
NK		 1264void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1265{
1266 /*
1267 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1268 * vcpu_enter_guest. This function is only called from
1269 * the physical CPU that is running vcpu.
1270 */
1271 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1272}
16e8d74d 1273
18068523
GOC		 1274static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1275{
9ed3c444
AK		 1276 int version;
1277 int r;
50d0a0f9 1278 struct pvclock_wall_clock wc;
87aeb54f 1279 struct timespec64 boot;
18068523
GOC		 1280
1281 if (!wall_clock)
1282 return;
1283
9ed3c444
AK		 1284 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1285 if (r)
1286 return;
1287
1288 if (version & 1)
1289 ++version; /* first time write, random junk */
1290
1291 ++version;
18068523 1292
1dab1345
NK		 1293 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1294 return;
18068523 1295
50d0a0f9
GH		 1296 /*
1297 * The guest calculates current wall clock time by adding
34c238a1 1298 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1299 * wall clock specified here. guest system time equals host
1300 * system time for us, thus we must fill in host boot time here.
1301 */
87aeb54f 1302 getboottime64(&boot);
50d0a0f9 1303
4b648665 1304 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1305 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1306 boot = timespec64_sub(boot, ts);
4b648665 1307 }
87aeb54f 1308 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1309 wc.nsec = boot.tv_nsec;
1310 wc.version = version;
18068523
GOC		 1311
1312 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1313
1314 version++;
1315 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1316}
1317
50d0a0f9
GH		 1318static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1319{
b51012de
PB		 1320 do_shl32_div32(dividend, divisor);
1321 return dividend;
50d0a0f9
GH		 1322}
1323
3ae13faa 1324static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1325 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1326{
5f4e3f88 1327 uint64_t scaled64;
50d0a0f9
GH		 1328 int32_t shift = 0;
1329 uint64_t tps64;
1330 uint32_t tps32;
1331
3ae13faa
PB		 1332 tps64 = base_hz;
1333 scaled64 = scaled_hz;
50933623 1334 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1335 tps64 >>= 1;
1336 shift--;
1337 }
1338
1339 tps32 = (uint32_t)tps64;
50933623
JK		 1340 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1341 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1342 scaled64 >>= 1;
1343 else
1344 tps32 <<= 1;
50d0a0f9
GH		 1345 shift++;
1346 }
1347
5f4e3f88
ZA		 1348 *pshift = shift;
1349 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1350
3ae13faa
PB		 1351 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1352 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1353}
1354
d828199e 1355#ifdef CONFIG_X86_64
16e8d74d 1356static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1357#endif
16e8d74d 1358
c8076604 1359static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1360static unsigned long max_tsc_khz;
c8076604 1361
cc578287 1362static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1363{
cc578287
ZA		 1364 u64 v = (u64)khz * (1000000 + ppm);
1365 do_div(v, 1000000);
1366 return v;
1e993611
JR		 1367}
1368
381d585c
HZ		 1369static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1370{
1371 u64 ratio;
1372
1373 /* Guest TSC same frequency as host TSC? */
1374 if (!scale) {
1375 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1376 return 0;
1377 }
1378
1379 /* TSC scaling supported? */
1380 if (!kvm_has_tsc_control) {
1381 if (user_tsc_khz > tsc_khz) {
1382 vcpu->arch.tsc_catchup = 1;
1383 vcpu->arch.tsc_always_catchup = 1;
1384 return 0;
1385 } else {
1386 WARN(1, "user requested TSC rate below hardware speed\n");
1387 return -1;
1388 }
1389 }
1390
1391 /* TSC scaling required - calculate ratio */
1392 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1393 user_tsc_khz, tsc_khz);
1394
1395 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1396 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1397 user_tsc_khz);
1398 return -1;
1399 }
1400
1401 vcpu->arch.tsc_scaling_ratio = ratio;
1402 return 0;
1403}
1404
4941b8cb 1405static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1406{
cc578287
ZA		 1407 u32 thresh_lo, thresh_hi;
1408 int use_scaling = 0;
217fc9cf 1409
03ba32ca 1410 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1411 if (user_tsc_khz == 0) {
ad721883
HZ		 1412 /* set tsc_scaling_ratio to a safe value */
1413 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1414 return -1;
ad721883 1415 }
03ba32ca 1416
c285545f 1417 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1418 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1419 &vcpu->arch.virtual_tsc_shift,
1420 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1421 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1422
1423 /*
1424 * Compute the variation in TSC rate which is acceptable
1425 * within the range of tolerance and decide if the
1426 * rate being applied is within that bounds of the hardware
1427 * rate. If so, no scaling or compensation need be done.
1428 */
1429 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1430 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1431 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1432 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1433 use_scaling = 1;
1434 }
4941b8cb 1435 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1436}
1437
1438static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1439{
e26101b1 1440 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1441 vcpu->arch.virtual_tsc_mult,
1442 vcpu->arch.virtual_tsc_shift);
e26101b1 1443 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1444 return tsc;
1445}
1446
69b0049a 1447static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1448{
1449#ifdef CONFIG_X86_64
1450 bool vcpus_matched;
b48aa97e
MT		 1451 struct kvm_arch *ka = &vcpu->kvm->arch;
1452 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1453
1454 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1455 atomic_read(&vcpu->kvm->online_vcpus));
1456
7f187922
MT		 1457 /*
1458 * Once the masterclock is enabled, always perform request in
1459 * order to update it.
1460 *
1461 * In order to enable masterclock, the host clocksource must be TSC
1462 * and the vcpus need to have matched TSCs. When that happens,
1463 * perform request to enable masterclock.
1464 */
1465 if (ka->use_master_clock ||
1466 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1467 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1468
1469 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1470 atomic_read(&vcpu->kvm->online_vcpus),
1471 ka->use_master_clock, gtod->clock.vclock_mode);
1472#endif
1473}
1474
ba904635
WA		 1475static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1476{
f7f5542f 1477 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1478 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1479}
1480
35181e86
HZ		 1481/*
1482 * Multiply tsc by a fixed point number represented by ratio.
1483 *
1484 * The most significant 64-N bits (mult) of ratio represent the
1485 * integral part of the fixed point number; the remaining N bits
1486 * (frac) represent the fractional part, ie. ratio represents a fixed
1487 * point number (mult + frac * 2^(-N)).
1488 *
1489 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1490 */
1491static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1492{
1493 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1494}
1495
1496u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1497{
1498 u64 _tsc = tsc;
1499 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1500
1501 if (ratio != kvm_default_tsc_scaling_ratio)
1502 _tsc = __scale_tsc(ratio, tsc);
1503
1504 return _tsc;
1505}
1506EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1507
07c1419a
HZ		 1508static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1509{
1510 u64 tsc;
1511
1512 tsc = kvm_scale_tsc(vcpu, rdtsc());
1513
1514 return target_tsc - tsc;
1515}
1516
4ba76538
HZ		 1517u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1518{
f7f5542f
KA		 1519 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1520
1521 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1522}
1523EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1524
a545ab6a
LC		 1525static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1526{
1527 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1528 vcpu->arch.tsc_offset = offset;
1529}
1530
8fe8ab46 1531void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1532{
1533 struct kvm *kvm = vcpu->kvm;
f38e098f 1534 u64 offset, ns, elapsed;
99e3e30a 1535 unsigned long flags;
b48aa97e 1536 bool matched;
0d3da0d2 1537 bool already_matched;
8fe8ab46 1538 u64 data = msr->data;
c5e8ec8e 1539 bool synchronizing = false;
99e3e30a 1540
038f8c11 1541 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1542 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1543 ns = ktime_get_boot_ns();
f38e098f 1544 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1545
03ba32ca 1546 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1547 if (data == 0 && msr->host_initiated) {
1548 /*
1549 * detection of vcpu initialization -- need to sync
1550 * with other vCPUs. This particularly helps to keep
1551 * kvm_clock stable after CPU hotplug
1552 */
1553 synchronizing = true;
1554 } else {
1555 u64 tsc_exp = kvm->arch.last_tsc_write +
1556 nsec_to_cycles(vcpu, elapsed);
1557 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1558 /*
1559 * Special case: TSC write with a small delta (1 second)
1560 * of virtual cycle time against real time is
1561 * interpreted as an attempt to synchronize the CPU.
1562 */
1563 synchronizing = data < tsc_exp + tsc_hz &&
1564 data + tsc_hz > tsc_exp;
1565 }
c5e8ec8e 1566 }
f38e098f
ZA		 1567
1568 /*
5d3cb0f6
ZA		 1569 * For a reliable TSC, we can match TSC offsets, and for an unstable
1570 * TSC, we add elapsed time in this computation. We could let the
1571 * compensation code attempt to catch up if we fall behind, but
1572 * it's better to try to match offsets from the beginning.
1573 */
c5e8ec8e 1574 if (synchronizing &&
5d3cb0f6 1575 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1576 if (!check_tsc_unstable()) {
e26101b1 1577 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1578 pr_debug("kvm: matched tsc offset for %llu\n", data);
1579 } else {
857e4099 1580 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1581 data += delta;
07c1419a 1582 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1583 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1584 }
b48aa97e 1585 matched = true;
0d3da0d2 1586 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1587 } else {
1588 /*
1589 * We split periods of matched TSC writes into generations.
1590 * For each generation, we track the original measured
1591 * nanosecond time, offset, and write, so if TSCs are in
1592 * sync, we can match exact offset, and if not, we can match
4a969980 1593 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1594 *
1595 * These values are tracked in kvm->arch.cur_xxx variables.
1596 */
1597 kvm->arch.cur_tsc_generation++;
1598 kvm->arch.cur_tsc_nsec = ns;
1599 kvm->arch.cur_tsc_write = data;
1600 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1601 matched = false;
0d3da0d2 1602 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1603 kvm->arch.cur_tsc_generation, data);
f38e098f 1604 }
e26101b1
ZA		 1605
1606 /*
1607 * We also track th most recent recorded KHZ, write and time to
1608 * allow the matching interval to be extended at each write.
1609 */
f38e098f
ZA		 1610 kvm->arch.last_tsc_nsec = ns;
1611 kvm->arch.last_tsc_write = data;
5d3cb0f6 1612 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1613
b183aa58 1614 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1615
1616 /* Keep track of which generation this VCPU has synchronized to */
1617 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1618 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1619 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1620
d6321d49 1621 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1622 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1623
a545ab6a 1624 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1625 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1626
1627 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1628 if (!matched) {
b48aa97e 1629 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1630 } else if (!already_matched) {
1631 kvm->arch.nr_vcpus_matched_tsc++;
1632 }
b48aa97e
MT		 1633
1634 kvm_track_tsc_matching(vcpu);
1635 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1636}
e26101b1 1637
99e3e30a
ZA		 1638EXPORT_SYMBOL_GPL(kvm_write_tsc);
1639
58ea6767
HZ		 1640static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1641 s64 adjustment)
1642{
ea26e4ec 1643 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1644}
1645
1646static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1647{
1648 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1649 WARN_ON(adjustment < 0);
1650 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1651 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1652}
1653
d828199e
MT		 1654#ifdef CONFIG_X86_64
1655
a5a1d1c2 1656static u64 read_tsc(void)
d828199e 1657{
a5a1d1c2 1658 u64 ret = (u64)rdtsc_ordered();
03b9730b 1659 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1660
1661 if (likely(ret >= last))
1662 return ret;
1663
1664 /*
1665 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1666 * predictable (it's just a function of time and the likely is
d828199e
MT		 1667 * very likely) and there's a data dependence, so force GCC
1668 * to generate a branch instead. I don't barrier() because
1669 * we don't actually need a barrier, and if this function
1670 * ever gets inlined it will generate worse code.
1671 */
1672 asm volatile ("");
1673 return last;
1674}
1675
a5a1d1c2 1676static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1677{
1678 long v;
1679 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1680
1681 *cycle_now = read_tsc();
1682
1683 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1684 return v * gtod->clock.mult;
1685}
1686
a5a1d1c2 1687static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1688{
cbcf2dd3 1689 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1690 unsigned long seq;
d828199e 1691 int mode;
cbcf2dd3 1692 u64 ns;
d828199e 1693
d828199e
MT		 1694 do {
1695 seq = read_seqcount_begin(&gtod->seq);
1696 mode = gtod->clock.vclock_mode;
cbcf2dd3 1697 ns = gtod->nsec_base;
d828199e
MT		 1698 ns += vgettsc(cycle_now);
1699 ns >>= gtod->clock.shift;
cbcf2dd3 1700 ns += gtod->boot_ns;
d828199e 1701 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1702 *t = ns;
d828199e
MT		 1703
1704 return mode;
1705}
1706
55dd00a7
MT		 1707static int do_realtime(struct timespec *ts, u64 *cycle_now)
1708{
1709 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1710 unsigned long seq;
1711 int mode;
1712 u64 ns;
1713
1714 do {
1715 seq = read_seqcount_begin(&gtod->seq);
1716 mode = gtod->clock.vclock_mode;
1717 ts->tv_sec = gtod->wall_time_sec;
1718 ns = gtod->nsec_base;
1719 ns += vgettsc(cycle_now);
1720 ns >>= gtod->clock.shift;
1721 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1722
1723 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1724 ts->tv_nsec = ns;
1725
1726 return mode;
1727}
1728
d828199e 1729/* returns true if host is using tsc clocksource */
a5a1d1c2 1730static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1731{
d828199e
MT		 1732 /* checked again under seqlock below */
1733 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1734 return false;
1735
cbcf2dd3 1736 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1737}
55dd00a7
MT		 1738
1739/* returns true if host is using tsc clocksource */
1740static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1741 u64 *cycle_now)
1742{
1743 /* checked again under seqlock below */
1744 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1745 return false;
1746
1747 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1748}
d828199e
MT		 1749#endif
1750
1751/*
1752 *
b48aa97e
MT		 1753 * Assuming a stable TSC across physical CPUS, and a stable TSC
1754 * across virtual CPUs, the following condition is possible.
1755 * Each numbered line represents an event visible to both
d828199e
MT		 1756 * CPUs at the next numbered event.
1757 *
1758 * "timespecX" represents host monotonic time. "tscX" represents
1759 * RDTSC value.
1760 *
1761 * VCPU0 on CPU0 | VCPU1 on CPU1
1762 *
1763 * 1. read timespec0,tsc0
1764 * 2. | timespec1 = timespec0 + N
1765 * | tsc1 = tsc0 + M
1766 * 3. transition to guest | transition to guest
1767 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1768 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1769 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1770 *
1771 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1772 *
1773 * - ret0 < ret1
1774 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1775 * ...
1776 * - 0 < N - M => M < N
1777 *
1778 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1779 * always the case (the difference between two distinct xtime instances
1780 * might be smaller then the difference between corresponding TSC reads,
1781 * when updating guest vcpus pvclock areas).
1782 *
1783 * To avoid that problem, do not allow visibility of distinct
1784 * system_timestamp/tsc_timestamp values simultaneously: use a master
1785 * copy of host monotonic time values. Update that master copy
1786 * in lockstep.
1787 *
b48aa97e 1788 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1789 *
1790 */
1791
1792static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1793{
1794#ifdef CONFIG_X86_64
1795 struct kvm_arch *ka = &kvm->arch;
1796 int vclock_mode;
b48aa97e
MT		 1797 bool host_tsc_clocksource, vcpus_matched;
1798
1799 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1800 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1801
1802 /*
1803 * If the host uses TSC clock, then passthrough TSC as stable
1804 * to the guest.
1805 */
b48aa97e 1806 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1807 &ka->master_kernel_ns,
1808 &ka->master_cycle_now);
1809
16a96021 1810 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1811 && !ka->backwards_tsc_observed
54750f2c 1812 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1813
d828199e
MT		 1814 if (ka->use_master_clock)
1815 atomic_set(&kvm_guest_has_master_clock, 1);
1816
1817 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1818 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1819 vcpus_matched);
d828199e
MT		 1820#endif
1821}
1822
2860c4b1
PB		 1823void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1824{
1825 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1826}
1827
2e762ff7
MT		 1828static void kvm_gen_update_masterclock(struct kvm *kvm)
1829{
1830#ifdef CONFIG_X86_64
1831 int i;
1832 struct kvm_vcpu *vcpu;
1833 struct kvm_arch *ka = &kvm->arch;
1834
1835 spin_lock(&ka->pvclock_gtod_sync_lock);
1836 kvm_make_mclock_inprogress_request(kvm);
1837 /* no guest entries from this point */
1838 pvclock_update_vm_gtod_copy(kvm);
1839
1840 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1841 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1842
1843 /* guest entries allowed */
1844 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1845 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1846
1847 spin_unlock(&ka->pvclock_gtod_sync_lock);
1848#endif
1849}
1850
e891a32e 1851u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1852{
108b249c 1853 struct kvm_arch *ka = &kvm->arch;
8b953440 1854 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1855 u64 ret;
108b249c 1856
8b953440
PB		 1857 spin_lock(&ka->pvclock_gtod_sync_lock);
1858 if (!ka->use_master_clock) {
1859 spin_unlock(&ka->pvclock_gtod_sync_lock);
1860 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1861 }
1862
8b953440
PB		 1863 hv_clock.tsc_timestamp = ka->master_cycle_now;
1864 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1865 spin_unlock(&ka->pvclock_gtod_sync_lock);
1866
e2c2206a
WL		 1867 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1868 get_cpu();
1869
e70b57a6
WL		 1870 if (__this_cpu_read(cpu_tsc_khz)) {
1871 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1872 &hv_clock.tsc_shift,
1873 &hv_clock.tsc_to_system_mul);
1874 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1875 } else
1876 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1877
1878 put_cpu();
1879
1880 return ret;
108b249c
PB		 1881}
1882
0d6dd2ff
PB		 1883static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1884{
1885 struct kvm_vcpu_arch *vcpu = &v->arch;
1886 struct pvclock_vcpu_time_info guest_hv_clock;
1887
4e335d9e 1888 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1889 &guest_hv_clock, sizeof(guest_hv_clock))))
1890 return;
1891
1892 /* This VCPU is paused, but it's legal for a guest to read another
1893 * VCPU's kvmclock, so we really have to follow the specification where
1894 * it says that version is odd if data is being modified, and even after
1895 * it is consistent.
1896 *
1897 * Version field updates must be kept separate. This is because
1898 * kvm_write_guest_cached might use a "rep movs" instruction, and
1899 * writes within a string instruction are weakly ordered. So there
1900 * are three writes overall.
1901 *
1902 * As a small optimization, only write the version field in the first
1903 * and third write. The vcpu->pv_time cache is still valid, because the
1904 * version field is the first in the struct.
1905 */
1906 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1907
51c4b8bb
LA		 1908 if (guest_hv_clock.version & 1)
1909 ++guest_hv_clock.version; /* first time write, random junk */
1910
0d6dd2ff 1911 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1912 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1913 &vcpu->hv_clock,
1914 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1915
1916 smp_wmb();
1917
1918 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1919 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1920
1921 if (vcpu->pvclock_set_guest_stopped_request) {
1922 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1923 vcpu->pvclock_set_guest_stopped_request = false;
1924 }
1925
1926 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1927
4e335d9e
PB		 1928 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1929 &vcpu->hv_clock,
1930 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1931
1932 smp_wmb();
1933
1934 vcpu->hv_clock.version++;
4e335d9e
PB		 1935 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1936 &vcpu->hv_clock,
1937 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1938}
1939
34c238a1 1940static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1941{
78db6a50 1942 unsigned long flags, tgt_tsc_khz;
18068523 1943 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1944 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1945 s64 kernel_ns;
d828199e 1946 u64 tsc_timestamp, host_tsc;
51d59c6b 1947 u8 pvclock_flags;
d828199e
MT		 1948 bool use_master_clock;
1949
1950 kernel_ns = 0;
1951 host_tsc = 0;
18068523 1952
d828199e
MT		 1953 /*
1954 * If the host uses TSC clock, then passthrough TSC as stable
1955 * to the guest.
1956 */
1957 spin_lock(&ka->pvclock_gtod_sync_lock);
1958 use_master_clock = ka->use_master_clock;
1959 if (use_master_clock) {
1960 host_tsc = ka->master_cycle_now;
1961 kernel_ns = ka->master_kernel_ns;
1962 }
1963 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1964
1965 /* Keep irq disabled to prevent changes to the clock */
1966 local_irq_save(flags);
78db6a50
PB		 1967 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1968 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1969 local_irq_restore(flags);
1970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1971 return 1;
1972 }
d828199e 1973 if (!use_master_clock) {
4ea1636b 1974 host_tsc = rdtsc();
108b249c 1975 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1976 }
1977
4ba76538 1978 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1979
c285545f
ZA		 1980 /*
1981 * We may have to catch up the TSC to match elapsed wall clock
1982 * time for two reasons, even if kvmclock is used.
1983 * 1) CPU could have been running below the maximum TSC rate
1984 * 2) Broken TSC compensation resets the base at each VCPU
1985 * entry to avoid unknown leaps of TSC even when running
1986 * again on the same CPU. This may cause apparent elapsed
1987 * time to disappear, and the guest to stand still or run
1988 * very slowly.
1989 */
1990 if (vcpu->tsc_catchup) {
1991 u64 tsc = compute_guest_tsc(v, kernel_ns);
1992 if (tsc > tsc_timestamp) {
f1e2b260 1993 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1994 tsc_timestamp = tsc;
1995 }
50d0a0f9
GH		 1996 }
1997
18068523
GOC		 1998 local_irq_restore(flags);
1999
0d6dd2ff 2000 /* With all the info we got, fill in the values */
18068523 2001
78db6a50
PB		 2002 if (kvm_has_tsc_control)
2003 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2004
2005 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2006 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2007 &vcpu->hv_clock.tsc_shift,
2008 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2009 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2010 }
2011
1d5f066e 2012 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2013 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2014 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2015
d828199e 2016 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2017 pvclock_flags = 0;
d828199e
MT		 2018 if (use_master_clock)
2019 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2020
78c0337a
MT		 2021 vcpu->hv_clock.flags = pvclock_flags;
2022
095cf55d
PB		 2023 if (vcpu->pv_time_enabled)
2024 kvm_setup_pvclock_page(v);
2025 if (v == kvm_get_vcpu(v->kvm, 0))
2026 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2027 return 0;
c8076604
GH		 2028}
2029
0061d53d
MT		 2030/*
2031 * kvmclock updates which are isolated to a given vcpu, such as
2032 * vcpu->cpu migration, should not allow system_timestamp from
2033 * the rest of the vcpus to remain static. Otherwise ntp frequency
2034 * correction applies to one vcpu's system_timestamp but not
2035 * the others.
2036 *
2037 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2038 * We need to rate-limit these requests though, as they can
2039 * considerably slow guests that have a large number of vcpus.
2040 * The time for a remote vcpu to update its kvmclock is bound
2041 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2042 */
2043
7e44e449
AJ		 2044#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2045
2046static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2047{
2048 int i;
7e44e449
AJ		 2049 struct delayed_work *dwork = to_delayed_work(work);
2050 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2051 kvmclock_update_work);
2052 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2053 struct kvm_vcpu *vcpu;
2054
2055 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2056 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2057 kvm_vcpu_kick(vcpu);
2058 }
2059}
2060
7e44e449
AJ		 2061static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2062{
2063 struct kvm *kvm = v->kvm;
2064
105b21bb 2065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2066 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2067 KVMCLOCK_UPDATE_DELAY);
2068}
2069
332967a3
AJ		 2070#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2071
2072static void kvmclock_sync_fn(struct work_struct *work)
2073{
2074 struct delayed_work *dwork = to_delayed_work(work);
2075 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2076 kvmclock_sync_work);
2077 struct kvm *kvm = container_of(ka, struct kvm, arch);
2078
630994b3
MT		 2079 if (!kvmclock_periodic_sync)
2080 return;
2081
332967a3
AJ		 2082 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2083 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2084 KVMCLOCK_SYNC_PERIOD);
2085}
2086
9ffd986c 2087static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2088{
890ca9ae
HY		 2089 u64 mcg_cap = vcpu->arch.mcg_cap;
2090 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2091 u32 msr = msr_info->index;
2092 u64 data = msr_info->data;
890ca9ae 2093
15c4a640 2094 switch (msr) {
15c4a640 2095 case MSR_IA32_MCG_STATUS:
890ca9ae 2096 vcpu->arch.mcg_status = data;
15c4a640 2097 break;
c7ac679c 2098 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2099 if (!(mcg_cap & MCG_CTL_P))
2100 return 1;
2101 if (data != 0 && data != ~(u64)0)
2102 return -1;
2103 vcpu->arch.mcg_ctl = data;
2104 break;
2105 default:
2106 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2107 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2108 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2109 /* only 0 or all 1s can be written to IA32_MCi_CTL
2110 * some Linux kernels though clear bit 10 in bank 4 to
2111 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2112 * this to avoid an uncatched #GP in the guest
2113 */
890ca9ae 2114 if ((offset & 0x3) == 0 &&
114be429 2115 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2116 return -1;
9ffd986c
WL		 2117 if (!msr_info->host_initiated &&
2118 (offset & 0x3) == 1 && data != 0)
2119 return -1;
890ca9ae
HY		 2120 vcpu->arch.mce_banks[offset] = data;
2121 break;
2122 }
2123 return 1;
2124 }
2125 return 0;
2126}
2127
ffde22ac
ES		 2128static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2129{
2130 struct kvm *kvm = vcpu->kvm;
2131 int lm = is_long_mode(vcpu);
2132 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2133 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2134 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2135 : kvm->arch.xen_hvm_config.blob_size_32;
2136 u32 page_num = data & ~PAGE_MASK;
2137 u64 page_addr = data & PAGE_MASK;
2138 u8 *page;
2139 int r;
2140
2141 r = -E2BIG;
2142 if (page_num >= blob_size)
2143 goto out;
2144 r = -ENOMEM;
ff5c2c03
SL		 2145 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2146 if (IS_ERR(page)) {
2147 r = PTR_ERR(page);
ffde22ac 2148 goto out;
ff5c2c03 2149 }
54bf36aa 2150 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2151 goto out_free;
2152 r = 0;
2153out_free:
2154 kfree(page);
2155out:
2156 return r;
2157}
2158
344d9588
GN		 2159static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2160{
2161 gpa_t gpa = data & ~0x3f;
2162
52a5c155
WL		 2163 /* Bits 3:5 are reserved, Should be zero */
2164 if (data & 0x38)
344d9588
GN		 2165 return 1;
2166
2167 vcpu->arch.apf.msr_val = data;
2168
2169 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2170 kvm_clear_async_pf_completion_queue(vcpu);
2171 kvm_async_pf_hash_reset(vcpu);
2172 return 0;
2173 }
2174
4e335d9e 2175 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2176 sizeof(u32)))
344d9588
GN		 2177 return 1;
2178
6adba527 2179 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2180 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2181 kvm_async_pf_wakeup_all(vcpu);
2182 return 0;
2183}
2184
12f9a48f
GC		 2185static void kvmclock_reset(struct kvm_vcpu *vcpu)
2186{
0b79459b 2187 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2188}
2189
c9aaa895
GC		 2190static void record_steal_time(struct kvm_vcpu *vcpu)
2191{
2192 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2193 return;
2194
4e335d9e 2195 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2196 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2197 return;
2198
0b9f6c46
PX		 2199 vcpu->arch.st.steal.preempted = 0;
2200
35f3fae1
WL		 2201 if (vcpu->arch.st.steal.version & 1)
2202 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2203
2204 vcpu->arch.st.steal.version += 1;
2205
4e335d9e 2206 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2207 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2208
2209 smp_wmb();
2210
c54cdf14
LC		 2211 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2212 vcpu->arch.st.last_steal;
2213 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2214
4e335d9e 2215 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2216 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2217
2218 smp_wmb();
2219
2220 vcpu->arch.st.steal.version += 1;
c9aaa895 2221
4e335d9e 2222 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2223 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2224}
2225
8fe8ab46 2226int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2227{
5753785f 2228 bool pr = false;
8fe8ab46
WA		 2229 u32 msr = msr_info->index;
2230 u64 data = msr_info->data;
5753785f 2231
15c4a640 2232 switch (msr) {
2e32b719
BP		 2233 case MSR_AMD64_NB_CFG:
2234 case MSR_IA32_UCODE_REV:
2235 case MSR_IA32_UCODE_WRITE:
2236 case MSR_VM_HSAVE_PA:
2237 case MSR_AMD64_PATCH_LOADER:
2238 case MSR_AMD64_BU_CFG2:
405a353a 2239 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2240 break;
2241
15c4a640 2242 case MSR_EFER:
b69e8cae 2243 return set_efer(vcpu, data);
8f1589d9
AP		 2244 case MSR_K7_HWCR:
2245 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2246 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2247 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2248 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2249 if (data != 0) {
a737f256
CD		 2250 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2251 data);
8f1589d9
AP		 2252 return 1;
2253 }
15c4a640 2254 break;
f7c6d140
AP		 2255 case MSR_FAM10H_MMIO_CONF_BASE:
2256 if (data != 0) {
a737f256
CD		 2257 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2258 "0x%llx\n", data);
f7c6d140
AP		 2259 return 1;
2260 }
15c4a640 2261 break;
b5e2fec0
AG		 2262 case MSR_IA32_DEBUGCTLMSR:
2263 if (!data) {
2264 /* We support the non-activated case already */
2265 break;
2266 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2267 /* Values other than LBR and BTF are vendor-specific,
2268 thus reserved and should throw a #GP */
2269 return 1;
2270 }
a737f256
CD		 2271 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2272 __func__, data);
b5e2fec0 2273 break;
9ba075a6 2274 case 0x200 ... 0x2ff:
ff53604b 2275 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2276 case MSR_IA32_APICBASE:
58cb628d 2277 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2278 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2279 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2280 case MSR_IA32_TSCDEADLINE:
2281 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2282 break;
ba904635 2283 case MSR_IA32_TSC_ADJUST:
d6321d49 2284 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2285 if (!msr_info->host_initiated) {
d913b904 2286 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2287 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2288 }
2289 vcpu->arch.ia32_tsc_adjust_msr = data;
2290 }
2291 break;
15c4a640 2292 case MSR_IA32_MISC_ENABLE:
ad312c7c 2293 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2294 break;
64d60670
PB		 2295 case MSR_IA32_SMBASE:
2296 if (!msr_info->host_initiated)
2297 return 1;
2298 vcpu->arch.smbase = data;
2299 break;
4019c94a
PB		 2300 case MSR_IA32_TSC:
2301 kvm_write_tsc(vcpu, msr_info);
2302 break;
11c6bffa 2303 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2304 case MSR_KVM_WALL_CLOCK:
2305 vcpu->kvm->arch.wall_clock = data;
2306 kvm_write_wall_clock(vcpu->kvm, data);
2307 break;
11c6bffa 2308 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2309 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2310 struct kvm_arch *ka = &vcpu->kvm->arch;
2311
12f9a48f 2312 kvmclock_reset(vcpu);
18068523 2313
54750f2c
MT		 2314 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2315 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2316
2317 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2318 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2319
2320 ka->boot_vcpu_runs_old_kvmclock = tmp;
2321 }
2322
18068523 2323 vcpu->arch.time = data;
0061d53d 2324 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2325
2326 /* we verify if the enable bit is set... */
2327 if (!(data & 1))
2328 break;
2329
4e335d9e 2330 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2331 &vcpu->arch.pv_time, data & ~1ULL,
2332 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2333 vcpu->arch.pv_time_enabled = false;
2334 else
2335 vcpu->arch.pv_time_enabled = true;
32cad84f 2336
18068523
GOC		 2337 break;
2338 }
344d9588
GN		 2339 case MSR_KVM_ASYNC_PF_EN:
2340 if (kvm_pv_enable_async_pf(vcpu, data))
2341 return 1;
2342 break;
c9aaa895
GC		 2343 case MSR_KVM_STEAL_TIME:
2344
2345 if (unlikely(!sched_info_on()))
2346 return 1;
2347
2348 if (data & KVM_STEAL_RESERVED_MASK)
2349 return 1;
2350
4e335d9e 2351 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2352 data & KVM_STEAL_VALID_BITS,
2353 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2354 return 1;
2355
2356 vcpu->arch.st.msr_val = data;
2357
2358 if (!(data & KVM_MSR_ENABLED))
2359 break;
2360
c9aaa895
GC		 2361 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2362
2363 break;
ae7a2a3f
MT		 2364 case MSR_KVM_PV_EOI_EN:
2365 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2366 return 1;
2367 break;
c9aaa895 2368
890ca9ae
HY		 2369 case MSR_IA32_MCG_CTL:
2370 case MSR_IA32_MCG_STATUS:
81760dcc 2371 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2372 return set_msr_mce(vcpu, msr_info);
71db6023 2373
6912ac32
WH		 2374 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2375 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2376 pr = true; /* fall through */
2377 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2378 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2379 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2380 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2381
2382 if (pr || data != 0)
a737f256
CD		 2383 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2384 "0x%x data 0x%llx\n", msr, data);
5753785f 2385 break;
84e0cefa
JS		 2386 case MSR_K7_CLK_CTL:
2387 /*
2388 * Ignore all writes to this no longer documented MSR.
2389 * Writes are only relevant for old K7 processors,
2390 * all pre-dating SVM, but a recommended workaround from
4a969980 2391 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2392 * affected processor models on the command line, hence
2393 * the need to ignore the workaround.
2394 */
2395 break;
55cd8e5a 2396 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2397 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2398 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2399 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2400 return kvm_hv_set_msr_common(vcpu, msr, data,
2401 msr_info->host_initiated);
91c9c3ed 2402 case MSR_IA32_BBL_CR_CTL3:
2403 /* Drop writes to this legacy MSR -- see rdmsr
2404 * counterpart for further detail.
2405 */
fab0aa3b
EM		 2406 if (report_ignored_msrs)
2407 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2408 msr, data);
91c9c3ed 2409 break;
2b036c6b 2410 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2411 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2412 return 1;
2413 vcpu->arch.osvw.length = data;
2414 break;
2415 case MSR_AMD64_OSVW_STATUS:
d6321d49 2416 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2417 return 1;
2418 vcpu->arch.osvw.status = data;
2419 break;
db2336a8
KH		 2420 case MSR_PLATFORM_INFO:
2421 if (!msr_info->host_initiated ||
2422 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2423 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2424 cpuid_fault_enabled(vcpu)))
2425 return 1;
2426 vcpu->arch.msr_platform_info = data;
2427 break;
2428 case MSR_MISC_FEATURES_ENABLES:
2429 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2430 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2431 !supports_cpuid_fault(vcpu)))
2432 return 1;
2433 vcpu->arch.msr_misc_features_enables = data;
2434 break;
15c4a640 2435 default:
ffde22ac
ES		 2436 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2437 return xen_hvm_config(vcpu, data);
c6702c9d 2438 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2439 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2440 if (!ignore_msrs) {
ae0f5499 2441 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2442 msr, data);
ed85c068
AP		 2443 return 1;
2444 } else {
fab0aa3b
EM		 2445 if (report_ignored_msrs)
2446 vcpu_unimpl(vcpu,
2447 "ignored wrmsr: 0x%x data 0x%llx\n",
2448 msr, data);
ed85c068
AP		 2449 break;
2450 }
15c4a640
CO		 2451 }
2452 return 0;
2453}
2454EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2455
2456
2457/*
2458 * Reads an msr value (of 'msr_index') into 'pdata'.
2459 * Returns 0 on success, non-0 otherwise.
2460 * Assumes vcpu_load() was already called.
2461 */
609e36d3 2462int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2463{
609e36d3 2464 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2465}
ff651cb6 2466EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2467
890ca9ae 2468static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2469{
2470 u64 data;
890ca9ae
HY		 2471 u64 mcg_cap = vcpu->arch.mcg_cap;
2472 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2473
2474 switch (msr) {
15c4a640
CO		 2475 case MSR_IA32_P5_MC_ADDR:
2476 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2477 data = 0;
2478 break;
15c4a640 2479 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2480 data = vcpu->arch.mcg_cap;
2481 break;
c7ac679c 2482 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2483 if (!(mcg_cap & MCG_CTL_P))
2484 return 1;
2485 data = vcpu->arch.mcg_ctl;
2486 break;
2487 case MSR_IA32_MCG_STATUS:
2488 data = vcpu->arch.mcg_status;
2489 break;
2490 default:
2491 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2492 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2493 u32 offset = msr - MSR_IA32_MC0_CTL;
2494 data = vcpu->arch.mce_banks[offset];
2495 break;
2496 }
2497 return 1;
2498 }
2499 *pdata = data;
2500 return 0;
2501}
2502
609e36d3 2503int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2504{
609e36d3 2505 switch (msr_info->index) {
890ca9ae 2506 case MSR_IA32_PLATFORM_ID:
15c4a640 2507 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2508 case MSR_IA32_DEBUGCTLMSR:
2509 case MSR_IA32_LASTBRANCHFROMIP:
2510 case MSR_IA32_LASTBRANCHTOIP:
2511 case MSR_IA32_LASTINTFROMIP:
2512 case MSR_IA32_LASTINTTOIP:
60af2ecd 2513 case MSR_K8_SYSCFG:
3afb1121
PB		 2514 case MSR_K8_TSEG_ADDR:
2515 case MSR_K8_TSEG_MASK:
60af2ecd 2516 case MSR_K7_HWCR:
61a6bd67 2517 case MSR_VM_HSAVE_PA:
1fdbd48c 2518 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2519 case MSR_AMD64_NB_CFG:
f7c6d140 2520 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2521 case MSR_AMD64_BU_CFG2:
0c2df2a1 2522 case MSR_IA32_PERF_CTL:
405a353a 2523 case MSR_AMD64_DC_CFG:
609e36d3 2524 msr_info->data = 0;
15c4a640 2525 break;
6912ac32
WH		 2526 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2527 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2528 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2529 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2530 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2531 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2532 msr_info->data = 0;
5753785f 2533 break;
742bc670 2534 case MSR_IA32_UCODE_REV:
609e36d3 2535 msr_info->data = 0x100000000ULL;
742bc670 2536 break;
4019c94a
PB		 2537 case MSR_IA32_TSC:
2538 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2539 break;
9ba075a6 2540 case MSR_MTRRcap:
9ba075a6 2541 case 0x200 ... 0x2ff:
ff53604b 2542 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2543 case 0xcd: /* fsb frequency */
609e36d3 2544 msr_info->data = 3;
15c4a640 2545 break;
7b914098
JS		 2546 /*
2547 * MSR_EBC_FREQUENCY_ID
2548 * Conservative value valid for even the basic CPU models.
2549 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2550 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2551 * and 266MHz for model 3, or 4. Set Core Clock
2552 * Frequency to System Bus Frequency Ratio to 1 (bits
2553 * 31:24) even though these are only valid for CPU
2554 * models > 2, however guests may end up dividing or
2555 * multiplying by zero otherwise.
2556 */
2557 case MSR_EBC_FREQUENCY_ID:
609e36d3 2558 msr_info->data = 1 << 24;
7b914098 2559 break;
15c4a640 2560 case MSR_IA32_APICBASE:
609e36d3 2561 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2562 break;
0105d1a5 2563 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2564 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2565 break;
a3e06bbe 2566 case MSR_IA32_TSCDEADLINE:
609e36d3 2567 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2568 break;
ba904635 2569 case MSR_IA32_TSC_ADJUST:
609e36d3 2570 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2571 break;
15c4a640 2572 case MSR_IA32_MISC_ENABLE:
609e36d3 2573 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2574 break;
64d60670
PB		 2575 case MSR_IA32_SMBASE:
2576 if (!msr_info->host_initiated)
2577 return 1;
2578 msr_info->data = vcpu->arch.smbase;
15c4a640 2579 break;
847f0ad8
AG		 2580 case MSR_IA32_PERF_STATUS:
2581 /* TSC increment by tick */
609e36d3 2582 msr_info->data = 1000ULL;
847f0ad8 2583 /* CPU multiplier */
b0996ae4 2584 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2585 break;
15c4a640 2586 case MSR_EFER:
609e36d3 2587 msr_info->data = vcpu->arch.efer;
15c4a640 2588 break;
18068523 2589 case MSR_KVM_WALL_CLOCK:
11c6bffa 2590 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2591 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2592 break;
2593 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2594 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2595 msr_info->data = vcpu->arch.time;
18068523 2596 break;
344d9588 2597 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2598 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2599 break;
c9aaa895 2600 case MSR_KVM_STEAL_TIME:
609e36d3 2601 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2602 break;
1d92128f 2603 case MSR_KVM_PV_EOI_EN:
609e36d3 2604 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2605 break;
890ca9ae
HY		 2606 case MSR_IA32_P5_MC_ADDR:
2607 case MSR_IA32_P5_MC_TYPE:
2608 case MSR_IA32_MCG_CAP:
2609 case MSR_IA32_MCG_CTL:
2610 case MSR_IA32_MCG_STATUS:
81760dcc 2611 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2612 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2613 case MSR_K7_CLK_CTL:
2614 /*
2615 * Provide expected ramp-up count for K7. All other
2616 * are set to zero, indicating minimum divisors for
2617 * every field.
2618 *
2619 * This prevents guest kernels on AMD host with CPU
2620 * type 6, model 8 and higher from exploding due to
2621 * the rdmsr failing.
2622 */
609e36d3 2623 msr_info->data = 0x20000000;
84e0cefa 2624 break;
55cd8e5a 2625 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2626 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2627 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2628 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2629 return kvm_hv_get_msr_common(vcpu,
2630 msr_info->index, &msr_info->data);
55cd8e5a 2631 break;
91c9c3ed 2632 case MSR_IA32_BBL_CR_CTL3:
2633 /* This legacy MSR exists but isn't fully documented in current
2634 * silicon. It is however accessed by winxp in very narrow
2635 * scenarios where it sets bit #19, itself documented as
2636 * a "reserved" bit. Best effort attempt to source coherent
2637 * read data here should the balance of the register be
2638 * interpreted by the guest:
2639 *
2640 * L2 cache control register 3: 64GB range, 256KB size,
2641 * enabled, latency 0x1, configured
2642 */
609e36d3 2643 msr_info->data = 0xbe702111;
91c9c3ed 2644 break;
2b036c6b 2645 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2646 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2647 return 1;
609e36d3 2648 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2649 break;
2650 case MSR_AMD64_OSVW_STATUS:
d6321d49 2651 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2652 return 1;
609e36d3 2653 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2654 break;
db2336a8
KH		 2655 case MSR_PLATFORM_INFO:
2656 msr_info->data = vcpu->arch.msr_platform_info;
2657 break;
2658 case MSR_MISC_FEATURES_ENABLES:
2659 msr_info->data = vcpu->arch.msr_misc_features_enables;
2660 break;
15c4a640 2661 default:
c6702c9d 2662 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2663 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2664 if (!ignore_msrs) {
ae0f5499
BD		 2665 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2666 msr_info->index);
ed85c068
AP		 2667 return 1;
2668 } else {
fab0aa3b
EM		 2669 if (report_ignored_msrs)
2670 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2671 msr_info->index);
609e36d3 2672 msr_info->data = 0;
ed85c068
AP		 2673 }
2674 break;
15c4a640 2675 }
15c4a640
CO		 2676 return 0;
2677}
2678EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2679
313a3dc7
CO		 2680/*
2681 * Read or write a bunch of msrs. All parameters are kernel addresses.
2682 *
2683 * @return number of msrs set successfully.
2684 */
2685static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2686 struct kvm_msr_entry *entries,
2687 int (*do_msr)(struct kvm_vcpu *vcpu,
2688 unsigned index, u64 *data))
2689{
ab1bebf8 2690 int i;
313a3dc7 2691
313a3dc7
CO		 2692 for (i = 0; i < msrs->nmsrs; ++i)
2693 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2694 break;
2695
313a3dc7
CO		 2696 return i;
2697}
2698
2699/*
2700 * Read or write a bunch of msrs. Parameters are user addresses.
2701 *
2702 * @return number of msrs set successfully.
2703 */
2704static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2705 int (*do_msr)(struct kvm_vcpu *vcpu,
2706 unsigned index, u64 *data),
2707 int writeback)
2708{
2709 struct kvm_msrs msrs;
2710 struct kvm_msr_entry *entries;
2711 int r, n;
2712 unsigned size;
2713
2714 r = -EFAULT;
2715 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2716 goto out;
2717
2718 r = -E2BIG;
2719 if (msrs.nmsrs >= MAX_IO_MSRS)
2720 goto out;
2721
313a3dc7 2722 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2723 entries = memdup_user(user_msrs->entries, size);
2724 if (IS_ERR(entries)) {
2725 r = PTR_ERR(entries);
313a3dc7 2726 goto out;
ff5c2c03 2727 }
313a3dc7
CO		 2728
2729 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2730 if (r < 0)
2731 goto out_free;
2732
2733 r = -EFAULT;
2734 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2735 goto out_free;
2736
2737 r = n;
2738
2739out_free:
7a73c028 2740 kfree(entries);
313a3dc7
CO		 2741out:
2742 return r;
2743}
2744
784aa3d7 2745int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2746{
2747 int r;
2748
2749 switch (ext) {
2750 case KVM_CAP_IRQCHIP:
2751 case KVM_CAP_HLT:
2752 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2753 case KVM_CAP_SET_TSS_ADDR:
07716717 2754 case KVM_CAP_EXT_CPUID:
9c15bb1d 2755 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2756 case KVM_CAP_CLOCKSOURCE:
7837699f 2757 case KVM_CAP_PIT:
a28e4f5a 2758 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2759 case KVM_CAP_MP_STATE:
ed848624 2760 case KVM_CAP_SYNC_MMU:
a355c85c 2761 case KVM_CAP_USER_NMI:
52d939a0 2762 case KVM_CAP_REINJECT_CONTROL:
4925663a 2763 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2764 case KVM_CAP_IOEVENTFD:
f848a5a8 2765 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2766 case KVM_CAP_PIT2:
e9f42757 2767 case KVM_CAP_PIT_STATE2:
b927a3ce 2768 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2769 case KVM_CAP_XEN_HVM:
3cfc3092 2770 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2771 case KVM_CAP_HYPERV:
10388a07 2772 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2773 case KVM_CAP_HYPERV_SPIN:
5c919412 2774 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2775 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2776 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2777 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2778 case KVM_CAP_DEBUGREGS:
d2be1651 2779 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2780 case KVM_CAP_XSAVE:
344d9588 2781 case KVM_CAP_ASYNC_PF:
92a1f12d 2782 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2783 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2784 case KVM_CAP_READONLY_MEM:
5f66b620 2785 case KVM_CAP_HYPERV_TIME:
100943c5 2786 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2787 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2788 case KVM_CAP_ENABLE_CAP_VM:
2789 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2790 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2791 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2792 case KVM_CAP_IMMEDIATE_EXIT:
ab1bebf8 2793 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2794 r = 1;
2795 break;
e3fd9a93
PB		 2796 case KVM_CAP_ADJUST_CLOCK:
2797 r = KVM_CLOCK_TSC_STABLE;
2798 break;
668fffa3
MT		 2799 case KVM_CAP_X86_GUEST_MWAIT:
2800 r = kvm_mwait_in_guest();
2801 break;
6d396b55
PB		 2802 case KVM_CAP_X86_SMM:
2803 /* SMBASE is usually relocated above 1M on modern chipsets,
2804 * and SMM handlers might indeed rely on 4G segment limits,
2805 * so do not report SMM to be available if real mode is
2806 * emulated via vm86 mode. Still, do not go to great lengths
2807 * to avoid userspace's usage of the feature, because it is a
2808 * fringe case that is not enabled except via specific settings
2809 * of the module parameters.
2810 */
4d5c8a07 2811 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2812 break;
774ead3a
AK		 2813 case KVM_CAP_VAPIC:
2814 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2815 break;
f725230a 2816 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2817 r = KVM_SOFT_MAX_VCPUS;
2818 break;
2819 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2820 r = KVM_MAX_VCPUS;
2821 break;
a988b910 2822 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2823 r = KVM_USER_MEM_SLOTS;
a988b910 2824 break;
a68a6a72
MT		 2825 case KVM_CAP_PV_MMU: /* obsolete */
2826 r = 0;
2f333bcb 2827 break;
890ca9ae
HY		 2828 case KVM_CAP_MCE:
2829 r = KVM_MAX_MCE_BANKS;
2830 break;
2d5b5a66 2831 case KVM_CAP_XCRS:
d366bf7e 2832 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2833 break;
92a1f12d
JR		 2834 case KVM_CAP_TSC_CONTROL:
2835 r = kvm_has_tsc_control;
2836 break;
37131313
RK		 2837 case KVM_CAP_X2APIC_API:
2838 r = KVM_X2APIC_API_VALID_FLAGS;
2839 break;
018d00d2
ZX		 2840 default:
2841 r = 0;
2842 break;
2843 }
2844 return r;
2845
2846}
2847
043405e1
CO		 2848long kvm_arch_dev_ioctl(struct file *filp,
2849 unsigned int ioctl, unsigned long arg)
2850{
2851 void __user *argp = (void __user *)arg;
2852 long r;
2853
2854 switch (ioctl) {
2855 case KVM_GET_MSR_INDEX_LIST: {
2856 struct kvm_msr_list __user *user_msr_list = argp;
2857 struct kvm_msr_list msr_list;
2858 unsigned n;
2859
2860 r = -EFAULT;
2861 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2862 goto out;
2863 n = msr_list.nmsrs;
62ef68bb 2864 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2865 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2866 goto out;
2867 r = -E2BIG;
e125e7b6 2868 if (n < msr_list.nmsrs)
043405e1
CO		 2869 goto out;
2870 r = -EFAULT;
2871 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2872 num_msrs_to_save * sizeof(u32)))
2873 goto out;
e125e7b6 2874 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2875 &emulated_msrs,
62ef68bb 2876 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2877 goto out;
2878 r = 0;
2879 break;
2880 }
9c15bb1d
BP		 2881 case KVM_GET_SUPPORTED_CPUID:
2882 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2883 struct kvm_cpuid2 __user *cpuid_arg = argp;
2884 struct kvm_cpuid2 cpuid;
2885
2886 r = -EFAULT;
2887 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2888 goto out;
9c15bb1d
BP		 2889
2890 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2891 ioctl);
674eea0f
AK		 2892 if (r)
2893 goto out;
2894
2895 r = -EFAULT;
2896 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2897 goto out;
2898 r = 0;
2899 break;
2900 }
890ca9ae 2901 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2902 r = -EFAULT;
c45dcc71
AR		 2903 if (copy_to_user(argp, &kvm_mce_cap_supported,
2904 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2905 goto out;
2906 r = 0;
2907 break;
ab1bebf8
TL		 2908 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2909 struct kvm_msr_list __user *user_msr_list = argp;
2910 struct kvm_msr_list msr_list;
2911 unsigned int n;
2912
2913 r = -EFAULT;
2914 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2915 goto out;
2916 n = msr_list.nmsrs;
2917 msr_list.nmsrs = num_msr_based_features;
2918 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2919 goto out;
2920 r = -E2BIG;
2921 if (n < msr_list.nmsrs)
2922 goto out;
2923 r = -EFAULT;
2924 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2925 num_msr_based_features * sizeof(u32)))
2926 goto out;
2927 r = 0;
2928 break;
2929 }
2930 case KVM_GET_MSRS:
2931 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2932 break;
890ca9ae 2933 }
043405e1
CO		 2934 default:
2935 r = -EINVAL;
2936 }
2937out:
2938 return r;
2939}
2940
f5f48ee1
SY		 2941static void wbinvd_ipi(void *garbage)
2942{
2943 wbinvd();
2944}
2945
2946static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2947{
e0f0bbc5 2948 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2949}
2950
313a3dc7
CO		 2951void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2952{
f5f48ee1
SY		 2953 /* Address WBINVD may be executed by guest */
2954 if (need_emulate_wbinvd(vcpu)) {
2955 if (kvm_x86_ops->has_wbinvd_exit())
2956 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2957 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2958 smp_call_function_single(vcpu->cpu,
2959 wbinvd_ipi, NULL, 1);
2960 }
2961
313a3dc7 2962 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2963
0dd6a6ed
ZA		 2964 /* Apply any externally detected TSC adjustments (due to suspend) */
2965 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2966 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2967 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2968 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2969 }
8f6055cb 2970
48434c20 2971 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2972 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2973 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2974 if (tsc_delta < 0)
2975 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2976
c285545f 2977 if (check_tsc_unstable()) {
07c1419a 2978 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2979 vcpu->arch.last_guest_tsc);
a545ab6a 2980 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2981 vcpu->arch.tsc_catchup = 1;
c285545f 2982 }
a749e247
PB		 2983
2984 if (kvm_lapic_hv_timer_in_use(vcpu))
2985 kvm_lapic_restart_hv_timer(vcpu);
2986
d98d07ca
MT		 2987 /*
2988 * On a host with synchronized TSC, there is no need to update
2989 * kvmclock on vcpu->cpu migration
2990 */
2991 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2992 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2993 if (vcpu->cpu != cpu)
1bd2009e 2994 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2995 vcpu->cpu = cpu;
6b7d7e76 2996 }
c9aaa895 2997
c9aaa895 2998 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2999}
3000
0b9f6c46
PX		 3001static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3002{
3003 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3004 return;
3005
3006 vcpu->arch.st.steal.preempted = 1;
3007
4e335d9e 3008 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3009 &vcpu->arch.st.steal.preempted,
3010 offsetof(struct kvm_steal_time, preempted),
3011 sizeof(vcpu->arch.st.steal.preempted));
3012}
3013
313a3dc7
CO		 3014void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3015{
cc0d907c 3016 int idx;
de63ad4c
LM		 3017
3018 if (vcpu->preempted)
3019 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3020
931f261b
AA		 3021 /*
3022 * Disable page faults because we're in atomic context here.
3023 * kvm_write_guest_offset_cached() would call might_fault()
3024 * that relies on pagefault_disable() to tell if there's a
3025 * bug. NOTE: the write to guest memory may not go through if
3026 * during postcopy live migration or if there's heavy guest
3027 * paging.
3028 */
3029 pagefault_disable();
cc0d907c
AA		 3030 /*
3031 * kvm_memslots() will be called by
3032 * kvm_write_guest_offset_cached() so take the srcu lock.
3033 */
3034 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3035 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3036 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3037 pagefault_enable();
02daab21 3038 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3039 vcpu->arch.last_host_tsc = rdtsc();
7046f30e
WL		 3040 /*
3041 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3042 * on every vmexit, but if not, we might have a stale dr6 from the
3043 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3044 */
3045 set_debugreg(0, 6);
313a3dc7
CO		 3046}
3047
313a3dc7
CO		 3048static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3049 struct kvm_lapic_state *s)
3050{
76dfafd5 3051 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 3052 kvm_x86_ops->sync_pir_to_irr(vcpu);
3053
a92e2543 3054 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3055}
3056
3057static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3058 struct kvm_lapic_state *s)
3059{
a92e2543
RK		 3060 int r;
3061
3062 r = kvm_apic_set_state(vcpu, s);
3063 if (r)
3064 return r;
cb142eb7 3065 update_cr8_intercept(vcpu);
313a3dc7
CO		 3066
3067 return 0;
3068}
3069
127a457a
MG		 3070static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3071{
3072 return (!lapic_in_kernel(vcpu) ||
3073 kvm_apic_accept_pic_intr(vcpu));
3074}
3075
782d422b
MG		 3076/*
3077 * if userspace requested an interrupt window, check that the
3078 * interrupt window is open.
3079 *
3080 * No need to exit to userspace if we already have an interrupt queued.
3081 */
3082static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3083{
3084 return kvm_arch_interrupt_allowed(vcpu) &&
3085 !kvm_cpu_has_interrupt(vcpu) &&
3086 !kvm_event_needs_reinjection(vcpu) &&
3087 kvm_cpu_accept_dm_intr(vcpu);
3088}
3089
f77bc6a4
ZX		 3090static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3091 struct kvm_interrupt *irq)
3092{
02cdb50f 3093 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3094 return -EINVAL;
1c1a9ce9
SR		 3095
3096 if (!irqchip_in_kernel(vcpu->kvm)) {
3097 kvm_queue_interrupt(vcpu, irq->irq, false);
3098 kvm_make_request(KVM_REQ_EVENT, vcpu);
3099 return 0;
3100 }
3101
3102 /*
3103 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3104 * fail for in-kernel 8259.
3105 */
3106 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3107 return -ENXIO;
f77bc6a4 3108
1c1a9ce9
SR		 3109 if (vcpu->arch.pending_external_vector != -1)
3110 return -EEXIST;
f77bc6a4 3111
1c1a9ce9 3112 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3113 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3114 return 0;
3115}
3116
c4abb7c9
JK		 3117static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3118{
c4abb7c9 3119 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3120
3121 return 0;
3122}
3123
f077825a
PB		 3124static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3125{
64d60670
PB		 3126 kvm_make_request(KVM_REQ_SMI, vcpu);
3127
f077825a
PB		 3128 return 0;
3129}
3130
b209749f
AK		 3131static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3132 struct kvm_tpr_access_ctl *tac)
3133{
3134 if (tac->flags)
3135 return -EINVAL;
3136 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3137 return 0;
3138}
3139
890ca9ae
HY		 3140static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3141 u64 mcg_cap)
3142{
3143 int r;
3144 unsigned bank_num = mcg_cap & 0xff, bank;
3145
3146 r = -EINVAL;
a9e38c3e 3147 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3148 goto out;
c45dcc71 3149 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3150 goto out;
3151 r = 0;
3152 vcpu->arch.mcg_cap = mcg_cap;
3153 /* Init IA32_MCG_CTL to all 1s */
3154 if (mcg_cap & MCG_CTL_P)
3155 vcpu->arch.mcg_ctl = ~(u64)0;
3156 /* Init IA32_MCi_CTL to all 1s */
3157 for (bank = 0; bank < bank_num; bank++)
3158 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3159
3160 if (kvm_x86_ops->setup_mce)
3161 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3162out:
3163 return r;
3164}
3165
3166static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3167 struct kvm_x86_mce *mce)
3168{
3169 u64 mcg_cap = vcpu->arch.mcg_cap;
3170 unsigned bank_num = mcg_cap & 0xff;
3171 u64 *banks = vcpu->arch.mce_banks;
3172
3173 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3174 return -EINVAL;
3175 /*
3176 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3177 * reporting is disabled
3178 */
3179 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3180 vcpu->arch.mcg_ctl != ~(u64)0)
3181 return 0;
3182 banks += 4 * mce->bank;
3183 /*
3184 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3185 * reporting is disabled for the bank
3186 */
3187 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3188 return 0;
3189 if (mce->status & MCI_STATUS_UC) {
3190 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3191 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3192 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3193 return 0;
3194 }
3195 if (banks[1] & MCI_STATUS_VAL)
3196 mce->status |= MCI_STATUS_OVER;
3197 banks[2] = mce->addr;
3198 banks[3] = mce->misc;
3199 vcpu->arch.mcg_status = mce->mcg_status;
3200 banks[1] = mce->status;
3201 kvm_queue_exception(vcpu, MC_VECTOR);
3202 } else if (!(banks[1] & MCI_STATUS_VAL)
3203 || !(banks[1] & MCI_STATUS_UC)) {
3204 if (banks[1] & MCI_STATUS_VAL)
3205 mce->status |= MCI_STATUS_OVER;
3206 banks[2] = mce->addr;
3207 banks[3] = mce->misc;
3208 banks[1] = mce->status;
3209 } else
3210 banks[1] |= MCI_STATUS_OVER;
3211 return 0;
3212}
3213
3cfc3092
JK		 3214static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3215 struct kvm_vcpu_events *events)
3216{
7460fb4a 3217 process_nmi(vcpu);
664f8e26
WL		 3218 /*
3219 * FIXME: pass injected and pending separately. This is only
3220 * needed for nested virtualization, whose state cannot be
3221 * migrated yet. For now we can combine them.
3222 */
03b82a30 3223 events->exception.injected =
664f8e26
WL		 3224 (vcpu->arch.exception.pending ||
3225 vcpu->arch.exception.injected) &&
03b82a30 3226 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3227 events->exception.nr = vcpu->arch.exception.nr;
3228 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3229 events->exception.pad = 0;
3cfc3092
JK		 3230 events->exception.error_code = vcpu->arch.exception.error_code;
3231
03b82a30
JK		 3232 events->interrupt.injected =
3233 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3234 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3235 events->interrupt.soft = 0;
37ccdcbe 3236 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3237
3238 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3239 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3240 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3241 events->nmi.pad = 0;
3cfc3092 3242
66450a21 3243 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3244
f077825a
PB		 3245 events->smi.smm = is_smm(vcpu);
3246 events->smi.pending = vcpu->arch.smi_pending;
3247 events->smi.smm_inside_nmi =
3248 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3249 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3250
dab4b911 3251 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3252 | KVM_VCPUEVENT_VALID_SHADOW
3253 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3254 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3255}
3256
6ef4e07e
XG		 3257static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3258
3cfc3092
JK		 3259static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3260 struct kvm_vcpu_events *events)
3261{
dab4b911 3262 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3263 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3264 | KVM_VCPUEVENT_VALID_SHADOW
3265 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3266 return -EINVAL;
3267
78e546c8 3268 if (events->exception.injected &&
28d06353
JM		 3269 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3270 is_guest_mode(vcpu)))
78e546c8
PB		 3271 return -EINVAL;
3272
28bf2888
DH		 3273 /* INITs are latched while in SMM */
3274 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3275 (events->smi.smm || events->smi.pending) &&
3276 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3277 return -EINVAL;
3278
7460fb4a 3279 process_nmi(vcpu);
664f8e26 3280 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3281 vcpu->arch.exception.pending = events->exception.injected;
3282 vcpu->arch.exception.nr = events->exception.nr;
3283 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3284 vcpu->arch.exception.error_code = events->exception.error_code;
3285
3286 vcpu->arch.interrupt.pending = events->interrupt.injected;
3287 vcpu->arch.interrupt.nr = events->interrupt.nr;
3288 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3289 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3290 kvm_x86_ops->set_interrupt_shadow(vcpu,
3291 events->interrupt.shadow);
3cfc3092
JK		 3292
3293 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3294 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3295 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3296 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3297
66450a21 3298 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3299 lapic_in_kernel(vcpu))
66450a21 3300 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3301
f077825a 3302 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3303 u32 hflags = vcpu->arch.hflags;
f077825a 3304 if (events->smi.smm)
6ef4e07e 3305 hflags |= HF_SMM_MASK;
f077825a 3306 else
6ef4e07e
XG		 3307 hflags &= ~HF_SMM_MASK;
3308 kvm_set_hflags(vcpu, hflags);
3309
f077825a 3310 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3311
3312 if (events->smi.smm) {
3313 if (events->smi.smm_inside_nmi)
3314 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3315 else
f4ef1910
WL		 3316 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3317 if (lapic_in_kernel(vcpu)) {
3318 if (events->smi.latched_init)
3319 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3320 else
3321 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3322 }
f077825a
PB		 3323 }
3324 }
3325
3842d135
AK		 3326 kvm_make_request(KVM_REQ_EVENT, vcpu);
3327
3cfc3092
JK		 3328 return 0;
3329}
3330
a1efbe77
JK		 3331static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3332 struct kvm_debugregs *dbgregs)
3333{
73aaf249
JK		 3334 unsigned long val;
3335
a1efbe77 3336 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3337 kvm_get_dr(vcpu, 6, &val);
73aaf249 3338 dbgregs->dr6 = val;
a1efbe77
JK		 3339 dbgregs->dr7 = vcpu->arch.dr7;
3340 dbgregs->flags = 0;
97e69aa6 3341 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3342}
3343
3344static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3345 struct kvm_debugregs *dbgregs)
3346{
3347 if (dbgregs->flags)
3348 return -EINVAL;
3349
d14bdb55
PB		 3350 if (dbgregs->dr6 & ~0xffffffffull)
3351 return -EINVAL;
3352 if (dbgregs->dr7 & ~0xffffffffull)
3353 return -EINVAL;
3354
a1efbe77 3355 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3356 kvm_update_dr0123(vcpu);
a1efbe77 3357 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3358 kvm_update_dr6(vcpu);
a1efbe77 3359 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3360 kvm_update_dr7(vcpu);
a1efbe77 3361
a1efbe77
JK		 3362 return 0;
3363}
3364
df1daba7
PB		 3365#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3366
3367static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3368{
c47ada30 3369 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3370 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3371 u64 valid;
3372
3373 /*
3374 * Copy legacy XSAVE area, to avoid complications with CPUID
3375 * leaves 0 and 1 in the loop below.
3376 */
3377 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3378
3379 /* Set XSTATE_BV */
00c87e9a 3380 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3381 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3382
3383 /*
3384 * Copy each region from the possibly compacted offset to the
3385 * non-compacted offset.
3386 */
d91cab78 3387 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3388 while (valid) {
3389 u64 feature = valid & -valid;
3390 int index = fls64(feature) - 1;
3391 void *src = get_xsave_addr(xsave, feature);
3392
3393 if (src) {
3394 u32 size, offset, ecx, edx;
3395 cpuid_count(XSTATE_CPUID, index,
3396 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3397 if (feature == XFEATURE_MASK_PKRU)
3398 memcpy(dest + offset, &vcpu->arch.pkru,
3399 sizeof(vcpu->arch.pkru));
3400 else
3401 memcpy(dest + offset, src, size);
3402
df1daba7
PB		 3403 }
3404
3405 valid -= feature;
3406 }
3407}
3408
3409static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3410{
c47ada30 3411 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3412 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3413 u64 valid;
3414
3415 /*
3416 * Copy legacy XSAVE area, to avoid complications with CPUID
3417 * leaves 0 and 1 in the loop below.
3418 */
3419 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3420
3421 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3422 xsave->header.xfeatures = xstate_bv;
782511b0 3423 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3424 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3425
3426 /*
3427 * Copy each region from the non-compacted offset to the
3428 * possibly compacted offset.
3429 */
d91cab78 3430 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3431 while (valid) {
3432 u64 feature = valid & -valid;
3433 int index = fls64(feature) - 1;
3434 void *dest = get_xsave_addr(xsave, feature);
3435
3436 if (dest) {
3437 u32 size, offset, ecx, edx;
3438 cpuid_count(XSTATE_CPUID, index,
3439 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3440 if (feature == XFEATURE_MASK_PKRU)
3441 memcpy(&vcpu->arch.pkru, src + offset,
3442 sizeof(vcpu->arch.pkru));
3443 else
3444 memcpy(dest, src + offset, size);
ee4100da 3445 }
df1daba7
PB		 3446
3447 valid -= feature;
3448 }
3449}
3450
2d5b5a66
SY		 3451static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3452 struct kvm_xsave *guest_xsave)
3453{
d366bf7e 3454 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3455 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3456 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3457 } else {
2d5b5a66 3458 memcpy(guest_xsave->region,
7366ed77 3459 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3460 sizeof(struct fxregs_state));
2d5b5a66 3461 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3462 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3463 }
3464}
3465
a575813b
WL		 3466#define XSAVE_MXCSR_OFFSET 24
3467
2d5b5a66
SY		 3468static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3469 struct kvm_xsave *guest_xsave)
3470{
3471 u64 xstate_bv =
3472 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3473 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3474
d366bf7e 3475 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3476 /*
3477 * Here we allow setting states that are not present in
3478 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3479 * with old userspace.
3480 */
a575813b
WL		 3481 if (xstate_bv & ~kvm_supported_xcr0() ||
3482 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3483 return -EINVAL;
df1daba7 3484 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3485 } else {
a575813b
WL		 3486 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3487 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3488 return -EINVAL;
7366ed77 3489 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3490 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3491 }
3492 return 0;
3493}
3494
3495static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3496 struct kvm_xcrs *guest_xcrs)
3497{
d366bf7e 3498 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3499 guest_xcrs->nr_xcrs = 0;
3500 return;
3501 }
3502
3503 guest_xcrs->nr_xcrs = 1;
3504 guest_xcrs->flags = 0;
3505 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3506 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3507}
3508
3509static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3510 struct kvm_xcrs *guest_xcrs)
3511{
3512 int i, r = 0;
3513
d366bf7e 3514 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3515 return -EINVAL;
3516
3517 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3518 return -EINVAL;
3519
3520 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3521 /* Only support XCR0 currently */
c67a04cb 3522 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3523 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3524 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3525 break;
3526 }
3527 if (r)
3528 r = -EINVAL;
3529 return r;
3530}
3531
1c0b28c2
EM		 3532/*
3533 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3534 * stopped by the hypervisor. This function will be called from the host only.
3535 * EINVAL is returned when the host attempts to set the flag for a guest that
3536 * does not support pv clocks.
3537 */
3538static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3539{
0b79459b 3540 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3541 return -EINVAL;
51d59c6b 3542 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3543 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3544 return 0;
3545}
3546
5c919412
AS		 3547static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3548 struct kvm_enable_cap *cap)
3549{
3550 if (cap->flags)
3551 return -EINVAL;
3552
3553 switch (cap->cap) {
efc479e6
RK		 3554 case KVM_CAP_HYPERV_SYNIC2:
3555 if (cap->args[0])
3556 return -EINVAL;
5c919412 3557 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3558 if (!irqchip_in_kernel(vcpu->kvm))
3559 return -EINVAL;
efc479e6
RK		 3560 return kvm_hv_activate_synic(vcpu, cap->cap ==
3561 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3562 default:
3563 return -EINVAL;
3564 }
3565}
3566
313a3dc7
CO		 3567long kvm_arch_vcpu_ioctl(struct file *filp,
3568 unsigned int ioctl, unsigned long arg)
3569{
3570 struct kvm_vcpu *vcpu = filp->private_data;
3571 void __user *argp = (void __user *)arg;
3572 int r;
d1ac91d8
AK		 3573 union {
3574 struct kvm_lapic_state *lapic;
3575 struct kvm_xsave *xsave;
3576 struct kvm_xcrs *xcrs;
3577 void *buffer;
3578 } u;
3579
3580 u.buffer = NULL;
313a3dc7
CO		 3581 switch (ioctl) {
3582 case KVM_GET_LAPIC: {
2204ae3c 3583 r = -EINVAL;
bce87cce 3584 if (!lapic_in_kernel(vcpu))
2204ae3c 3585 goto out;
d1ac91d8 3586 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3587
b772ff36 3588 r = -ENOMEM;
d1ac91d8 3589 if (!u.lapic)
b772ff36 3590 goto out;
d1ac91d8 3591 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3592 if (r)
3593 goto out;
3594 r = -EFAULT;
d1ac91d8 3595 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3596 goto out;
3597 r = 0;
3598 break;
3599 }
3600 case KVM_SET_LAPIC: {
2204ae3c 3601 r = -EINVAL;
bce87cce 3602 if (!lapic_in_kernel(vcpu))
2204ae3c 3603 goto out;
ff5c2c03 3604 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3605 if (IS_ERR(u.lapic))
3606 return PTR_ERR(u.lapic);
ff5c2c03 3607
d1ac91d8 3608 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3609 break;
3610 }
f77bc6a4
ZX		 3611 case KVM_INTERRUPT: {
3612 struct kvm_interrupt irq;
3613
3614 r = -EFAULT;
3615 if (copy_from_user(&irq, argp, sizeof irq))
3616 goto out;
3617 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3618 break;
3619 }
c4abb7c9
JK		 3620 case KVM_NMI: {
3621 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3622 break;
3623 }
f077825a
PB		 3624 case KVM_SMI: {
3625 r = kvm_vcpu_ioctl_smi(vcpu);
3626 break;
3627 }
313a3dc7
CO		 3628 case KVM_SET_CPUID: {
3629 struct kvm_cpuid __user *cpuid_arg = argp;
3630 struct kvm_cpuid cpuid;
3631
3632 r = -EFAULT;
3633 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3634 goto out;
3635 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3636 break;
3637 }
07716717
DK		 3638 case KVM_SET_CPUID2: {
3639 struct kvm_cpuid2 __user *cpuid_arg = argp;
3640 struct kvm_cpuid2 cpuid;
3641
3642 r = -EFAULT;
3643 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3644 goto out;
3645 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3646 cpuid_arg->entries);
07716717
DK		 3647 break;
3648 }
3649 case KVM_GET_CPUID2: {
3650 struct kvm_cpuid2 __user *cpuid_arg = argp;
3651 struct kvm_cpuid2 cpuid;
3652
3653 r = -EFAULT;
3654 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3655 goto out;
3656 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3657 cpuid_arg->entries);
07716717
DK		 3658 if (r)
3659 goto out;
3660 r = -EFAULT;
3661 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3662 goto out;
3663 r = 0;
3664 break;
3665 }
ab1bebf8
TL		 3666 case KVM_GET_MSRS: {
3667 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3668 r = msr_io(vcpu, argp, do_get_msr, 1);
ab1bebf8 3669 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3670 break;
ab1bebf8
TL		 3671 }
3672 case KVM_SET_MSRS: {
3673 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3674 r = msr_io(vcpu, argp, do_set_msr, 0);
ab1bebf8 3675 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3676 break;
ab1bebf8 3677 }
b209749f
AK		 3678 case KVM_TPR_ACCESS_REPORTING: {
3679 struct kvm_tpr_access_ctl tac;
3680
3681 r = -EFAULT;
3682 if (copy_from_user(&tac, argp, sizeof tac))
3683 goto out;
3684 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3685 if (r)
3686 goto out;
3687 r = -EFAULT;
3688 if (copy_to_user(argp, &tac, sizeof tac))
3689 goto out;
3690 r = 0;
3691 break;
3692 };
b93463aa
AK		 3693 case KVM_SET_VAPIC_ADDR: {
3694 struct kvm_vapic_addr va;
7301d6ab 3695 int idx;
b93463aa
AK		 3696
3697 r = -EINVAL;
35754c98 3698 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3699 goto out;
3700 r = -EFAULT;
3701 if (copy_from_user(&va, argp, sizeof va))
3702 goto out;
7301d6ab 3703 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3704 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3705 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3706 break;
3707 }
890ca9ae
HY		 3708 case KVM_X86_SETUP_MCE: {
3709 u64 mcg_cap;
3710
3711 r = -EFAULT;
3712 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3713 goto out;
3714 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3715 break;
3716 }
3717 case KVM_X86_SET_MCE: {
3718 struct kvm_x86_mce mce;
3719
3720 r = -EFAULT;
3721 if (copy_from_user(&mce, argp, sizeof mce))
3722 goto out;
3723 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3724 break;
3725 }
3cfc3092
JK		 3726 case KVM_GET_VCPU_EVENTS: {
3727 struct kvm_vcpu_events events;
3728
3729 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3730
3731 r = -EFAULT;
3732 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3733 break;
3734 r = 0;
3735 break;
3736 }
3737 case KVM_SET_VCPU_EVENTS: {
3738 struct kvm_vcpu_events events;
3739
3740 r = -EFAULT;
3741 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3742 break;
3743
3744 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3745 break;
3746 }
a1efbe77
JK		 3747 case KVM_GET_DEBUGREGS: {
3748 struct kvm_debugregs dbgregs;
3749
3750 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3751
3752 r = -EFAULT;
3753 if (copy_to_user(argp, &dbgregs,
3754 sizeof(struct kvm_debugregs)))
3755 break;
3756 r = 0;
3757 break;
3758 }
3759 case KVM_SET_DEBUGREGS: {
3760 struct kvm_debugregs dbgregs;
3761
3762 r = -EFAULT;
3763 if (copy_from_user(&dbgregs, argp,
3764 sizeof(struct kvm_debugregs)))
3765 break;
3766
3767 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3768 break;
3769 }
2d5b5a66 3770 case KVM_GET_XSAVE: {
d1ac91d8 3771 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3772 r = -ENOMEM;
d1ac91d8 3773 if (!u.xsave)
2d5b5a66
SY		 3774 break;
3775
d1ac91d8 3776 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3777
3778 r = -EFAULT;
d1ac91d8 3779 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3780 break;
3781 r = 0;
3782 break;
3783 }
3784 case KVM_SET_XSAVE: {
ff5c2c03 3785 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3786 if (IS_ERR(u.xsave))
3787 return PTR_ERR(u.xsave);
2d5b5a66 3788
d1ac91d8 3789 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3790 break;
3791 }
3792 case KVM_GET_XCRS: {
d1ac91d8 3793 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3794 r = -ENOMEM;
d1ac91d8 3795 if (!u.xcrs)
2d5b5a66
SY		 3796 break;
3797
d1ac91d8 3798 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3799
3800 r = -EFAULT;
d1ac91d8 3801 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3802 sizeof(struct kvm_xcrs)))
3803 break;
3804 r = 0;
3805 break;
3806 }
3807 case KVM_SET_XCRS: {
ff5c2c03 3808 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3809 if (IS_ERR(u.xcrs))
3810 return PTR_ERR(u.xcrs);
2d5b5a66 3811
d1ac91d8 3812 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3813 break;
3814 }
92a1f12d
JR		 3815 case KVM_SET_TSC_KHZ: {
3816 u32 user_tsc_khz;
3817
3818 r = -EINVAL;
92a1f12d
JR		 3819 user_tsc_khz = (u32)arg;
3820
3821 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3822 goto out;
3823
cc578287
ZA		 3824 if (user_tsc_khz == 0)
3825 user_tsc_khz = tsc_khz;
3826
381d585c
HZ		 3827 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3828 r = 0;
92a1f12d 3829
92a1f12d
JR		 3830 goto out;
3831 }
3832 case KVM_GET_TSC_KHZ: {
cc578287 3833 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3834 goto out;
3835 }
1c0b28c2
EM		 3836 case KVM_KVMCLOCK_CTRL: {
3837 r = kvm_set_guest_paused(vcpu);
3838 goto out;
3839 }
5c919412
AS		 3840 case KVM_ENABLE_CAP: {
3841 struct kvm_enable_cap cap;
3842
3843 r = -EFAULT;
3844 if (copy_from_user(&cap, argp, sizeof(cap)))
3845 goto out;
3846 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3847 break;
3848 }
313a3dc7
CO		 3849 default:
3850 r = -EINVAL;
3851 }
3852out:
d1ac91d8 3853 kfree(u.buffer);
313a3dc7
CO		 3854 return r;
3855}
3856
5b1c1493
CO		 3857int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3858{
3859 return VM_FAULT_SIGBUS;
3860}
3861
1fe779f8
CO		 3862static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3863{
3864 int ret;
3865
3866 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3867 return -EINVAL;
1fe779f8
CO		 3868 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3869 return ret;
3870}
3871
b927a3ce
SY		 3872static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3873 u64 ident_addr)
3874{
3875 kvm->arch.ept_identity_map_addr = ident_addr;
3876 return 0;
3877}
3878
1fe779f8
CO		 3879static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3880 u32 kvm_nr_mmu_pages)
3881{
3882 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3883 return -EINVAL;
3884
79fac95e 3885 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3886
3887 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3888 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3889
79fac95e 3890 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3891 return 0;
3892}
3893
3894static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3895{
39de71ec 3896 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3897}
3898
1fe779f8
CO		 3899static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3900{
90bca052 3901 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3902 int r;
3903
3904 r = 0;
3905 switch (chip->chip_id) {
3906 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3907 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3908 sizeof(struct kvm_pic_state));
3909 break;
3910 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3911 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3912 sizeof(struct kvm_pic_state));
3913 break;
3914 case KVM_IRQCHIP_IOAPIC:
33392b49 3915 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3916 break;
3917 default:
3918 r = -EINVAL;
3919 break;
3920 }
3921 return r;
3922}
3923
3924static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3925{
90bca052 3926 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3927 int r;
3928
3929 r = 0;
3930 switch (chip->chip_id) {
3931 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3932 spin_lock(&pic->lock);
3933 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3934 sizeof(struct kvm_pic_state));
90bca052 3935 spin_unlock(&pic->lock);
1fe779f8
CO		 3936 break;
3937 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3938 spin_lock(&pic->lock);
3939 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3940 sizeof(struct kvm_pic_state));
90bca052 3941 spin_unlock(&pic->lock);
1fe779f8
CO		 3942 break;
3943 case KVM_IRQCHIP_IOAPIC:
33392b49 3944 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3945 break;
3946 default:
3947 r = -EINVAL;
3948 break;
3949 }
90bca052 3950 kvm_pic_update_irq(pic);
1fe779f8
CO		 3951 return r;
3952}
3953
e0f63cb9
SY		 3954static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3955{
34f3941c
RK		 3956 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3957
3958 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3959
3960 mutex_lock(&kps->lock);
3961 memcpy(ps, &kps->channels, sizeof(*ps));
3962 mutex_unlock(&kps->lock);
2da29bcc 3963 return 0;
e0f63cb9
SY		 3964}
3965
3966static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3967{
0185604c 3968 int i;
09edea72
RK		 3969 struct kvm_pit *pit = kvm->arch.vpit;
3970
3971 mutex_lock(&pit->pit_state.lock);
34f3941c 3972 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3973 for (i = 0; i < 3; i++)
09edea72
RK		 3974 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3975 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3976 return 0;
e9f42757
BK		 3977}
3978
3979static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3980{
e9f42757
BK		 3981 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3982 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3983 sizeof(ps->channels));
3984 ps->flags = kvm->arch.vpit->pit_state.flags;
3985 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3986 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3987 return 0;
e9f42757
BK		 3988}
3989
3990static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3991{
2da29bcc 3992 int start = 0;
0185604c 3993 int i;
e9f42757 3994 u32 prev_legacy, cur_legacy;
09edea72
RK		 3995 struct kvm_pit *pit = kvm->arch.vpit;
3996
3997 mutex_lock(&pit->pit_state.lock);
3998 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3999 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4000 if (!prev_legacy && cur_legacy)
4001 start = 1;
09edea72
RK		 4002 memcpy(&pit->pit_state.channels, &ps->channels,
4003 sizeof(pit->pit_state.channels));
4004 pit->pit_state.flags = ps->flags;
0185604c 4005 for (i = 0; i < 3; i++)
09edea72 4006 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4007 start && i == 0);
09edea72 4008 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4009 return 0;
e0f63cb9
SY		 4010}
4011
52d939a0
MT		 4012static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4013 struct kvm_reinject_control *control)
4014{
71474e2f
RK		 4015 struct kvm_pit *pit = kvm->arch.vpit;
4016
4017 if (!pit)
52d939a0 4018 return -ENXIO;
b39c90b6 4019
71474e2f
RK		 4020 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4021 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4022 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4023 */
4024 mutex_lock(&pit->pit_state.lock);
4025 kvm_pit_set_reinject(pit, control->pit_reinject);
4026 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4027
52d939a0
MT		 4028 return 0;
4029}
4030
95d4c16c 4031/**
60c34612
TY		 4032 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4033 * @kvm: kvm instance
4034 * @log: slot id and address to which we copy the log
95d4c16c 4035 *
e108ff2f
PB		 4036 * Steps 1-4 below provide general overview of dirty page logging. See
4037 * kvm_get_dirty_log_protect() function description for additional details.
4038 *
4039 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4040 * always flush the TLB (step 4) even if previous step failed and the dirty
4041 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4042 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4043 * writes will be marked dirty for next log read.
95d4c16c 4044 *
60c34612
TY		 4045 * 1. Take a snapshot of the bit and clear it if needed.
4046 * 2. Write protect the corresponding page.
e108ff2f
PB		 4047 * 3. Copy the snapshot to the userspace.
4048 * 4. Flush TLB's if needed.
5bb064dc 4049 */
60c34612 4050int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4051{
60c34612 4052 bool is_dirty = false;
e108ff2f 4053 int r;
5bb064dc 4054
79fac95e 4055 mutex_lock(&kvm->slots_lock);
5bb064dc 4056
88178fd4
KH		 4057 /*
4058 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4059 */
4060 if (kvm_x86_ops->flush_log_dirty)
4061 kvm_x86_ops->flush_log_dirty(kvm);
4062
e108ff2f 4063 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4064
4065 /*
4066 * All the TLBs can be flushed out of mmu lock, see the comments in
4067 * kvm_mmu_slot_remove_write_access().
4068 */
e108ff2f 4069 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4070 if (is_dirty)
4071 kvm_flush_remote_tlbs(kvm);
4072
79fac95e 4073 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4074 return r;
4075}
4076
aa2fbe6d
YZ		 4077int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4078 bool line_status)
23d43cf9
CD		 4079{
4080 if (!irqchip_in_kernel(kvm))
4081 return -ENXIO;
4082
4083 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4084 irq_event->irq, irq_event->level,
4085 line_status);
23d43cf9
CD		 4086 return 0;
4087}
4088
90de4a18
NA		 4089static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4090 struct kvm_enable_cap *cap)
4091{
4092 int r;
4093
4094 if (cap->flags)
4095 return -EINVAL;
4096
4097 switch (cap->cap) {
4098 case KVM_CAP_DISABLE_QUIRKS:
4099 kvm->arch.disabled_quirks = cap->args[0];
4100 r = 0;
4101 break;
49df6397
SR		 4102 case KVM_CAP_SPLIT_IRQCHIP: {
4103 mutex_lock(&kvm->lock);
b053b2ae
SR		 4104 r = -EINVAL;
4105 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4106 goto split_irqchip_unlock;
49df6397
SR		 4107 r = -EEXIST;
4108 if (irqchip_in_kernel(kvm))
4109 goto split_irqchip_unlock;
557abc40 4110 if (kvm->created_vcpus)
49df6397
SR		 4111 goto split_irqchip_unlock;
4112 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4113 if (r)
49df6397
SR		 4114 goto split_irqchip_unlock;
4115 /* Pairs with irqchip_in_kernel. */
4116 smp_wmb();
49776faf 4117 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4118 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4119 r = 0;
4120split_irqchip_unlock:
4121 mutex_unlock(&kvm->lock);
4122 break;
4123 }
37131313
RK		 4124 case KVM_CAP_X2APIC_API:
4125 r = -EINVAL;
4126 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4127 break;
4128
4129 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4130 kvm->arch.x2apic_format = true;
c519265f
RK		 4131 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4132 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4133
4134 r = 0;
4135 break;
90de4a18
NA		 4136 default:
4137 r = -EINVAL;
4138 break;
4139 }
4140 return r;
4141}
4142
1fe779f8
CO		 4143long kvm_arch_vm_ioctl(struct file *filp,
4144 unsigned int ioctl, unsigned long arg)
4145{
4146 struct kvm *kvm = filp->private_data;
4147 void __user *argp = (void __user *)arg;
367e1319 4148 int r = -ENOTTY;
f0d66275
DH		 4149 /*
4150 * This union makes it completely explicit to gcc-3.x
4151 * that these two variables' stack usage should be
4152 * combined, not added together.
4153 */
4154 union {
4155 struct kvm_pit_state ps;
e9f42757 4156 struct kvm_pit_state2 ps2;
c5ff41ce 4157 struct kvm_pit_config pit_config;
f0d66275 4158 } u;
1fe779f8
CO		 4159
4160 switch (ioctl) {
4161 case KVM_SET_TSS_ADDR:
4162 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4163 break;
b927a3ce
SY		 4164 case KVM_SET_IDENTITY_MAP_ADDR: {
4165 u64 ident_addr;
4166
1af1ac91
DH		 4167 mutex_lock(&kvm->lock);
4168 r = -EINVAL;
4169 if (kvm->created_vcpus)
4170 goto set_identity_unlock;
b927a3ce
SY		 4171 r = -EFAULT;
4172 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4173 goto set_identity_unlock;
b927a3ce 4174 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4175set_identity_unlock:
4176 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4177 break;
4178 }
1fe779f8
CO		 4179 case KVM_SET_NR_MMU_PAGES:
4180 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4181 break;
4182 case KVM_GET_NR_MMU_PAGES:
4183 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4184 break;
3ddea128 4185 case KVM_CREATE_IRQCHIP: {
3ddea128 4186 mutex_lock(&kvm->lock);
09941366 4187
3ddea128 4188 r = -EEXIST;
35e6eaa3 4189 if (irqchip_in_kernel(kvm))
3ddea128 4190 goto create_irqchip_unlock;
09941366 4191
3e515705 4192 r = -EINVAL;
557abc40 4193 if (kvm->created_vcpus)
3e515705 4194 goto create_irqchip_unlock;
09941366
RK		 4195
4196 r = kvm_pic_init(kvm);
4197 if (r)
3ddea128 4198 goto create_irqchip_unlock;
09941366
RK		 4199
4200 r = kvm_ioapic_init(kvm);
4201 if (r) {
09941366 4202 kvm_pic_destroy(kvm);
3ddea128 4203 goto create_irqchip_unlock;
09941366
RK		 4204 }
4205
399ec807
AK		 4206 r = kvm_setup_default_irq_routing(kvm);
4207 if (r) {
72bb2fcd 4208 kvm_ioapic_destroy(kvm);
09941366 4209 kvm_pic_destroy(kvm);
71ba994c 4210 goto create_irqchip_unlock;
399ec807 4211 }
49776faf 4212 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4213 smp_wmb();
49776faf 4214 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4215 create_irqchip_unlock:
4216 mutex_unlock(&kvm->lock);
1fe779f8 4217 break;
3ddea128 4218 }
7837699f 4219 case KVM_CREATE_PIT:
c5ff41ce
JK		 4220 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4221 goto create_pit;
4222 case KVM_CREATE_PIT2:
4223 r = -EFAULT;
4224 if (copy_from_user(&u.pit_config, argp,
4225 sizeof(struct kvm_pit_config)))
4226 goto out;
4227 create_pit:
250715a6 4228 mutex_lock(&kvm->lock);
269e05e4
AK		 4229 r = -EEXIST;
4230 if (kvm->arch.vpit)
4231 goto create_pit_unlock;
7837699f 4232 r = -ENOMEM;
c5ff41ce 4233 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4234 if (kvm->arch.vpit)
4235 r = 0;
269e05e4 4236 create_pit_unlock:
250715a6 4237 mutex_unlock(&kvm->lock);
7837699f 4238 break;
1fe779f8
CO		 4239 case KVM_GET_IRQCHIP: {
4240 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4241 struct kvm_irqchip *chip;
1fe779f8 4242
ff5c2c03
SL		 4243 chip = memdup_user(argp, sizeof(*chip));
4244 if (IS_ERR(chip)) {
4245 r = PTR_ERR(chip);
1fe779f8 4246 goto out;
ff5c2c03
SL		 4247 }
4248
1fe779f8 4249 r = -ENXIO;
826da321 4250 if (!irqchip_kernel(kvm))
f0d66275
DH		 4251 goto get_irqchip_out;
4252 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4253 if (r)
f0d66275 4254 goto get_irqchip_out;
1fe779f8 4255 r = -EFAULT;
f0d66275
DH		 4256 if (copy_to_user(argp, chip, sizeof *chip))
4257 goto get_irqchip_out;
1fe779f8 4258 r = 0;
f0d66275
DH		 4259 get_irqchip_out:
4260 kfree(chip);
1fe779f8
CO		 4261 break;
4262 }
4263 case KVM_SET_IRQCHIP: {
4264 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4265 struct kvm_irqchip *chip;
1fe779f8 4266
ff5c2c03
SL		 4267 chip = memdup_user(argp, sizeof(*chip));
4268 if (IS_ERR(chip)) {
4269 r = PTR_ERR(chip);
1fe779f8 4270 goto out;
ff5c2c03
SL		 4271 }
4272
1fe779f8 4273 r = -ENXIO;
826da321 4274 if (!irqchip_kernel(kvm))
f0d66275
DH		 4275 goto set_irqchip_out;
4276 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4277 if (r)
f0d66275 4278 goto set_irqchip_out;
1fe779f8 4279 r = 0;
f0d66275
DH		 4280 set_irqchip_out:
4281 kfree(chip);
1fe779f8
CO		 4282 break;
4283 }
e0f63cb9 4284 case KVM_GET_PIT: {
e0f63cb9 4285 r = -EFAULT;
f0d66275 4286 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4287 goto out;
4288 r = -ENXIO;
4289 if (!kvm->arch.vpit)
4290 goto out;
f0d66275 4291 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4292 if (r)
4293 goto out;
4294 r = -EFAULT;
f0d66275 4295 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4296 goto out;
4297 r = 0;
4298 break;
4299 }
4300 case KVM_SET_PIT: {
e0f63cb9 4301 r = -EFAULT;
f0d66275 4302 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4303 goto out;
4304 r = -ENXIO;
4305 if (!kvm->arch.vpit)
4306 goto out;
f0d66275 4307 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4308 break;
4309 }
e9f42757
BK		 4310 case KVM_GET_PIT2: {
4311 r = -ENXIO;
4312 if (!kvm->arch.vpit)
4313 goto out;
4314 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4315 if (r)
4316 goto out;
4317 r = -EFAULT;
4318 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4319 goto out;
4320 r = 0;
4321 break;
4322 }
4323 case KVM_SET_PIT2: {
4324 r = -EFAULT;
4325 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4326 goto out;
4327 r = -ENXIO;
4328 if (!kvm->arch.vpit)
4329 goto out;
4330 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4331 break;
4332 }
52d939a0
MT		 4333 case KVM_REINJECT_CONTROL: {
4334 struct kvm_reinject_control control;
4335 r = -EFAULT;
4336 if (copy_from_user(&control, argp, sizeof(control)))
4337 goto out;
4338 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4339 break;
4340 }
d71ba788
PB		 4341 case KVM_SET_BOOT_CPU_ID:
4342 r = 0;
4343 mutex_lock(&kvm->lock);
557abc40 4344 if (kvm->created_vcpus)
d71ba788
PB		 4345 r = -EBUSY;
4346 else
4347 kvm->arch.bsp_vcpu_id = arg;
4348 mutex_unlock(&kvm->lock);
4349 break;
ffde22ac 4350 case KVM_XEN_HVM_CONFIG: {
df92b316 4351 struct kvm_xen_hvm_config xhc;
ffde22ac 4352 r = -EFAULT;
df92b316 4353 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4354 goto out;
4355 r = -EINVAL;
df92b316 4356 if (xhc.flags)
ffde22ac 4357 goto out;
df92b316 4358 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4359 r = 0;
4360 break;
4361 }
afbcf7ab 4362 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4363 struct kvm_clock_data user_ns;
4364 u64 now_ns;
afbcf7ab
GC		 4365
4366 r = -EFAULT;
4367 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4368 goto out;
4369
4370 r = -EINVAL;
4371 if (user_ns.flags)
4372 goto out;
4373
4374 r = 0;
0bc48bea
RK		 4375 /*
4376 * TODO: userspace has to take care of races with VCPU_RUN, so
4377 * kvm_gen_update_masterclock() can be cut down to locked
4378 * pvclock_update_vm_gtod_copy().
4379 */
4380 kvm_gen_update_masterclock(kvm);
e891a32e 4381 now_ns = get_kvmclock_ns(kvm);
108b249c 4382 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4383 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4384 break;
4385 }
4386 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4387 struct kvm_clock_data user_ns;
4388 u64 now_ns;
4389
e891a32e 4390 now_ns = get_kvmclock_ns(kvm);
108b249c 4391 user_ns.clock = now_ns;
e3fd9a93 4392 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4393 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4394
4395 r = -EFAULT;
4396 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4397 goto out;
4398 r = 0;
4399 break;
4400 }
90de4a18
NA		 4401 case KVM_ENABLE_CAP: {
4402 struct kvm_enable_cap cap;
afbcf7ab 4403
90de4a18
NA		 4404 r = -EFAULT;
4405 if (copy_from_user(&cap, argp, sizeof(cap)))
4406 goto out;
4407 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4408 break;
4409 }
1fe779f8 4410 default:
ad6260da 4411 r = -ENOTTY;
1fe779f8
CO		 4412 }
4413out:
4414 return r;
4415}
4416
a16b043c 4417static void kvm_init_msr_list(void)
043405e1
CO		 4418{
4419 u32 dummy[2];
4420 unsigned i, j;
4421
62ef68bb 4422 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4423 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4424 continue;
93c4adc7
PB		 4425
4426 /*
4427 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4428 * to the guests in some cases.
93c4adc7
PB		 4429 */
4430 switch (msrs_to_save[i]) {
4431 case MSR_IA32_BNDCFGS:
4432 if (!kvm_x86_ops->mpx_supported())
4433 continue;
4434 break;
9dbe6cf9
PB		 4435 case MSR_TSC_AUX:
4436 if (!kvm_x86_ops->rdtscp_supported())
4437 continue;
4438 break;
93c4adc7
PB		 4439 default:
4440 break;
4441 }
4442
043405e1
CO		 4443 if (j < i)
4444 msrs_to_save[j] = msrs_to_save[i];
4445 j++;
4446 }
4447 num_msrs_to_save = j;
62ef68bb
PB		 4448
4449 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4d5c8a07
TL		 4450 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4451 continue;
62ef68bb
PB		 4452
4453 if (j < i)
4454 emulated_msrs[j] = emulated_msrs[i];
4455 j++;
4456 }
4457 num_emulated_msrs = j;
ab1bebf8
TL		 4458
4459 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4460 struct kvm_msr_entry msr;
4461
4462 msr.index = msr_based_features[i];
08215b9d 4463 if (kvm_get_msr_feature(&msr))
ab1bebf8
TL		 4464 continue;
4465
4466 if (j < i)
4467 msr_based_features[j] = msr_based_features[i];
4468 j++;
4469 }
4470 num_msr_based_features = j;
043405e1
CO		 4471}
4472
bda9020e
MT		 4473static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4474 const void *v)
bbd9b64e 4475{
70252a10
AK		 4476 int handled = 0;
4477 int n;
4478
4479 do {
4480 n = min(len, 8);
bce87cce 4481 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4482 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4483 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4484 break;
4485 handled += n;
4486 addr += n;
4487 len -= n;
4488 v += n;
4489 } while (len);
bbd9b64e 4490
70252a10 4491 return handled;
bbd9b64e
CO		 4492}
4493
bda9020e 4494static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4495{
70252a10
AK		 4496 int handled = 0;
4497 int n;
4498
4499 do {
4500 n = min(len, 8);
bce87cce 4501 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4502 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4503 addr, n, v))
4504 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4505 break;
e39d200f 4506 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4507 handled += n;
4508 addr += n;
4509 len -= n;
4510 v += n;
4511 } while (len);
bbd9b64e 4512
70252a10 4513 return handled;
bbd9b64e
CO		 4514}
4515
2dafc6c2
GN		 4516static void kvm_set_segment(struct kvm_vcpu *vcpu,
4517 struct kvm_segment *var, int seg)
4518{
4519 kvm_x86_ops->set_segment(vcpu, var, seg);
4520}
4521
4522void kvm_get_segment(struct kvm_vcpu *vcpu,
4523 struct kvm_segment *var, int seg)
4524{
4525 kvm_x86_ops->get_segment(vcpu, var, seg);
4526}
4527
54987b7a
PB		 4528gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4529 struct x86_exception *exception)
02f59dc9
JR		 4530{
4531 gpa_t t_gpa;
02f59dc9
JR		 4532
4533 BUG_ON(!mmu_is_nested(vcpu));
4534
4535 /* NPT walks are always user-walks */
4536 access |= PFERR_USER_MASK;
54987b7a 4537 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4538
4539 return t_gpa;
4540}
4541
ab9ae313
AK		 4542gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4543 struct x86_exception *exception)
1871c602
GN		 4544{
4545 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4546 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4547}
4548
ab9ae313
AK		 4549 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4550 struct x86_exception *exception)
1871c602
GN		 4551{
4552 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4553 access |= PFERR_FETCH_MASK;
ab9ae313 4554 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4555}
4556
ab9ae313
AK		 4557gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4558 struct x86_exception *exception)
1871c602
GN		 4559{
4560 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4561 access |= PFERR_WRITE_MASK;
ab9ae313 4562 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4563}
4564
4565/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4566gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4567 struct x86_exception *exception)
1871c602 4568{
ab9ae313 4569 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4570}
4571
4572static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4573 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4574 struct x86_exception *exception)
bbd9b64e
CO		 4575{
4576 void *data = val;
10589a46 4577 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4578
4579 while (bytes) {
14dfe855 4580 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4581 exception);
bbd9b64e 4582 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4583 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4584 int ret;
4585
bcc55cba 4586 if (gpa == UNMAPPED_GVA)
ab9ae313 4587 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4588 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4589 offset, toread);
10589a46 4590 if (ret < 0) {
c3cd7ffa 4591 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4592 goto out;
4593 }
bbd9b64e 4594
77c2002e
IE		 4595 bytes -= toread;
4596 data += toread;
4597 addr += toread;
bbd9b64e 4598 }
10589a46 4599out:
10589a46 4600 return r;
bbd9b64e 4601}
77c2002e 4602
1871c602 4603/* used for instruction fetching */
0f65dd70
AK		 4604static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4605 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4606 struct x86_exception *exception)
1871c602 4607{
0f65dd70 4608 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4609 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4610 unsigned offset;
4611 int ret;
0f65dd70 4612
44583cba
PB		 4613 /* Inline kvm_read_guest_virt_helper for speed. */
4614 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4615 exception);
4616 if (unlikely(gpa == UNMAPPED_GVA))
4617 return X86EMUL_PROPAGATE_FAULT;
4618
4619 offset = addr & (PAGE_SIZE-1);
4620 if (WARN_ON(offset + bytes > PAGE_SIZE))
4621 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4622 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4623 offset, bytes);
44583cba
PB		 4624 if (unlikely(ret < 0))
4625 return X86EMUL_IO_NEEDED;
4626
4627 return X86EMUL_CONTINUE;
1871c602
GN		 4628}
4629
40d2dba3 4630int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4631 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4632 struct x86_exception *exception)
1871c602
GN		 4633{
4634 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4635
97ecb1a4
PB		 4636 /*
4637 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
4638 * is returned, but our callers are not ready for that and they blindly
4639 * call kvm_inject_page_fault. Ensure that they at least do not leak
4640 * uninitialized kernel stack memory into cr2 and error code.
4641 */
4642 memset(exception, 0, sizeof(*exception));
1871c602 4643 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4644 exception);
1871c602 4645}
064aea77 4646EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4647
40d2dba3
PB		 4648static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4649 gva_t addr, void *val, unsigned int bytes,
5579778e 4650 struct x86_exception *exception, bool system)
1871c602 4651{
0f65dd70 4652 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5579778e
PB		 4653 u32 access = 0;
4654
4655 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4656 access |= PFERR_USER_MASK;
4657
4658 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4659}
4660
7a036a6f
RK		 4661static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4662 unsigned long addr, void *val, unsigned int bytes)
4663{
4664 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4665 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4666
4667 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4668}
4669
40d2dba3
PB		 4670static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4671 struct kvm_vcpu *vcpu, u32 access,
4672 struct x86_exception *exception)
77c2002e
IE		 4673{
4674 void *data = val;
4675 int r = X86EMUL_CONTINUE;
4676
f0ace387
PB		 4677 /* kvm_write_guest_virt_system can pull in tons of pages. */
4678 vcpu->arch.l1tf_flush_l1d = true;
4679
77c2002e 4680 while (bytes) {
14dfe855 4681 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
40d2dba3 4682 access,
ab9ae313 4683 exception);
77c2002e
IE		 4684 unsigned offset = addr & (PAGE_SIZE-1);
4685 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4686 int ret;
4687
bcc55cba 4688 if (gpa == UNMAPPED_GVA)
ab9ae313 4689 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4690 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4691 if (ret < 0) {
c3cd7ffa 4692 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4693 goto out;
4694 }
4695
4696 bytes -= towrite;
4697 data += towrite;
4698 addr += towrite;
4699 }
4700out:
4701 return r;
4702}
40d2dba3
PB		 4703
4704static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5579778e
PB		 4705 unsigned int bytes, struct x86_exception *exception,
4706 bool system)
40d2dba3
PB		 4707{
4708 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5579778e
PB		 4709 u32 access = PFERR_WRITE_MASK;
4710
4711 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4712 access |= PFERR_USER_MASK;
40d2dba3
PB		 4713
4714 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5579778e 4715 access, exception);
40d2dba3
PB		 4716}
4717
4718int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4719 unsigned int bytes, struct x86_exception *exception)
4720{
4721 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4722 PFERR_WRITE_MASK, exception);
4723}
6a4d7550 4724EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4725
0f89b207
TL		 4726static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4727 gpa_t gpa, bool write)
4728{
4729 /* For APIC access vmexit */
4730 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4731 return 1;
4732
4733 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4734 trace_vcpu_match_mmio(gva, gpa, write, true);
4735 return 1;
4736 }
4737
4738 return 0;
4739}
4740
af7cc7d1
XG		 4741static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4742 gpa_t *gpa, struct x86_exception *exception,
4743 bool write)
4744{
97d64b78
AK		 4745 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4746 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4747
be94f6b7
HH		 4748 /*
4749 * currently PKRU is only applied to ept enabled guest so
4750 * there is no pkey in EPT page table for L1 guest or EPT
4751 * shadow page table for L2 guest.
4752 */
97d64b78 4753 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4754 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4755 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4756 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4757 (gva & (PAGE_SIZE - 1));
4f022648 4758 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4759 return 1;
4760 }
4761
af7cc7d1
XG		 4762 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4763
4764 if (*gpa == UNMAPPED_GVA)
4765 return -1;
4766
0f89b207 4767 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4768}
4769
3200f405 4770int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4771 const void *val, int bytes)
bbd9b64e
CO		 4772{
4773 int ret;
4774
54bf36aa 4775 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4776 if (ret < 0)
bbd9b64e 4777 return 0;
0eb05bf2 4778 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4779 return 1;
4780}
4781
77d197b2
XG		 4782struct read_write_emulator_ops {
4783 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4784 int bytes);
4785 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4786 void *val, int bytes);
4787 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4788 int bytes, void *val);
4789 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4790 void *val, int bytes);
4791 bool write;
4792};
4793
4794static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4795{
4796 if (vcpu->mmio_read_completed) {
77d197b2 4797 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4798 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4799 vcpu->mmio_read_completed = 0;
4800 return 1;
4801 }
4802
4803 return 0;
4804}
4805
4806static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4807 void *val, int bytes)
4808{
54bf36aa 4809 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4810}
4811
4812static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4813 void *val, int bytes)
4814{
4815 return emulator_write_phys(vcpu, gpa, val, bytes);
4816}
4817
4818static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4819{
e39d200f 4820 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4821 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4822}
4823
4824static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4825 void *val, int bytes)
4826{
e39d200f 4827 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4828 return X86EMUL_IO_NEEDED;
4829}
4830
4831static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4832 void *val, int bytes)
4833{
f78146b0
AK		 4834 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4835
87da7e66 4836 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4837 return X86EMUL_CONTINUE;
4838}
4839
0fbe9b0b 4840static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4841 .read_write_prepare = read_prepare,
4842 .read_write_emulate = read_emulate,
4843 .read_write_mmio = vcpu_mmio_read,
4844 .read_write_exit_mmio = read_exit_mmio,
4845};
4846
0fbe9b0b 4847static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4848 .read_write_emulate = write_emulate,
4849 .read_write_mmio = write_mmio,
4850 .read_write_exit_mmio = write_exit_mmio,
4851 .write = true,
4852};
4853
22388a3c
XG		 4854static int emulator_read_write_onepage(unsigned long addr, void *val,
4855 unsigned int bytes,
4856 struct x86_exception *exception,
4857 struct kvm_vcpu *vcpu,
0fbe9b0b 4858 const struct read_write_emulator_ops *ops)
bbd9b64e 4859{
af7cc7d1
XG		 4860 gpa_t gpa;
4861 int handled, ret;
22388a3c 4862 bool write = ops->write;
f78146b0 4863 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4864 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4865
4866 /*
4867 * If the exit was due to a NPF we may already have a GPA.
4868 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4869 * Note, this cannot be used on string operations since string
4870 * operation using rep will only have the initial GPA from the NPF
4871 * occurred.
4872 */
4873 if (vcpu->arch.gpa_available &&
4874 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4875 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4876 gpa = vcpu->arch.gpa_val;
4877 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4878 } else {
4879 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4880 if (ret < 0)
4881 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4882 }
10589a46 4883
618232e2 4884 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4885 return X86EMUL_CONTINUE;
4886
bbd9b64e
CO		 4887 /*
4888 * Is this MMIO handled locally?
4889 */
22388a3c 4890 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4891 if (handled == bytes)
bbd9b64e 4892 return X86EMUL_CONTINUE;
bbd9b64e 4893
70252a10
AK		 4894 gpa += handled;
4895 bytes -= handled;
4896 val += handled;
4897
87da7e66
XG		 4898 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4899 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4900 frag->gpa = gpa;
4901 frag->data = val;
4902 frag->len = bytes;
f78146b0 4903 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4904}
4905
52eb5a6d
XL		 4906static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4907 unsigned long addr,
22388a3c
XG		 4908 void *val, unsigned int bytes,
4909 struct x86_exception *exception,
0fbe9b0b 4910 const struct read_write_emulator_ops *ops)
bbd9b64e 4911{
0f65dd70 4912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4913 gpa_t gpa;
4914 int rc;
4915
4916 if (ops->read_write_prepare &&
4917 ops->read_write_prepare(vcpu, val, bytes))
4918 return X86EMUL_CONTINUE;
4919
4920 vcpu->mmio_nr_fragments = 0;
0f65dd70 4921
bbd9b64e
CO		 4922 /* Crossing a page boundary? */
4923 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4924 int now;
bbd9b64e
CO		 4925
4926 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4927 rc = emulator_read_write_onepage(addr, val, now, exception,
4928 vcpu, ops);
4929
bbd9b64e
CO		 4930 if (rc != X86EMUL_CONTINUE)
4931 return rc;
4932 addr += now;
bac15531
NA		 4933 if (ctxt->mode != X86EMUL_MODE_PROT64)
4934 addr = (u32)addr;
bbd9b64e
CO		 4935 val += now;
4936 bytes -= now;
4937 }
22388a3c 4938
f78146b0
AK		 4939 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4940 vcpu, ops);
4941 if (rc != X86EMUL_CONTINUE)
4942 return rc;
4943
4944 if (!vcpu->mmio_nr_fragments)
4945 return rc;
4946
4947 gpa = vcpu->mmio_fragments[0].gpa;
4948
4949 vcpu->mmio_needed = 1;
4950 vcpu->mmio_cur_fragment = 0;
4951
87da7e66 4952 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4953 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4954 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4955 vcpu->run->mmio.phys_addr = gpa;
4956
4957 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4958}
4959
4960static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4961 unsigned long addr,
4962 void *val,
4963 unsigned int bytes,
4964 struct x86_exception *exception)
4965{
4966 return emulator_read_write(ctxt, addr, val, bytes,
4967 exception, &read_emultor);
4968}
4969
52eb5a6d 4970static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4971 unsigned long addr,
4972 const void *val,
4973 unsigned int bytes,
4974 struct x86_exception *exception)
4975{
4976 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4977 exception, &write_emultor);
bbd9b64e 4978}
bbd9b64e 4979
daea3e73
AK		 4980#define CMPXCHG_TYPE(t, ptr, old, new) \
4981 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4982
4983#ifdef CONFIG_X86_64
4984# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4985#else
4986# define CMPXCHG64(ptr, old, new) \
9749a6c0 4987 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4988#endif
4989
0f65dd70
AK		 4990static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4991 unsigned long addr,
bbd9b64e
CO		 4992 const void *old,
4993 const void *new,
4994 unsigned int bytes,
0f65dd70 4995 struct x86_exception *exception)
bbd9b64e 4996{
0f65dd70 4997 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4998 gpa_t gpa;
4999 struct page *page;
5000 char *kaddr;
5001 bool exchanged;
2bacc55c 5002
daea3e73
AK		 5003 /* guests cmpxchg8b have to be emulated atomically */
5004 if (bytes > 8 || (bytes & (bytes - 1)))
5005 goto emul_write;
10589a46 5006
daea3e73 5007 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5008
daea3e73
AK		 5009 if (gpa == UNMAPPED_GVA ||
5010 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5011 goto emul_write;
2bacc55c 5012
daea3e73
AK		 5013 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5014 goto emul_write;
72dc67a6 5015
54bf36aa 5016 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5017 if (is_error_page(page))
c19b8bd6 5018 goto emul_write;
72dc67a6 5019
8fd75e12 5020 kaddr = kmap_atomic(page);
daea3e73
AK		 5021 kaddr += offset_in_page(gpa);
5022 switch (bytes) {
5023 case 1:
5024 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5025 break;
5026 case 2:
5027 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5028 break;
5029 case 4:
5030 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5031 break;
5032 case 8:
5033 exchanged = CMPXCHG64(kaddr, old, new);
5034 break;
5035 default:
5036 BUG();
2bacc55c 5037 }
8fd75e12 5038 kunmap_atomic(kaddr);
daea3e73
AK		 5039 kvm_release_page_dirty(page);
5040
5041 if (!exchanged)
5042 return X86EMUL_CMPXCHG_FAILED;
5043
54bf36aa 5044 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5045 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5046
5047 return X86EMUL_CONTINUE;
4a5f48f6 5048
3200f405 5049emul_write:
daea3e73 5050 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5051
0f65dd70 5052 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5053}
5054
cf8f70bf
GN		 5055static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5056{
cbfc6c91 5057 int r = 0, i;
cf8f70bf 5058
cbfc6c91
WL		 5059 for (i = 0; i < vcpu->arch.pio.count; i++) {
5060 if (vcpu->arch.pio.in)
5061 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5062 vcpu->arch.pio.size, pd);
5063 else
5064 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5065 vcpu->arch.pio.port, vcpu->arch.pio.size,
5066 pd);
5067 if (r)
5068 break;
5069 pd += vcpu->arch.pio.size;
5070 }
cf8f70bf
GN		 5071 return r;
5072}
5073
6f6fbe98
XG		 5074static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5075 unsigned short port, void *val,
5076 unsigned int count, bool in)
cf8f70bf 5077{
cf8f70bf 5078 vcpu->arch.pio.port = port;
6f6fbe98 5079 vcpu->arch.pio.in = in;
7972995b 5080 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5081 vcpu->arch.pio.size = size;
5082
5083 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5084 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5085 return 1;
5086 }
5087
5088 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5089 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5090 vcpu->run->io.size = size;
5091 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5092 vcpu->run->io.count = count;
5093 vcpu->run->io.port = port;
5094
5095 return 0;
5096}
5097
6f6fbe98
XG		 5098static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5099 int size, unsigned short port, void *val,
5100 unsigned int count)
cf8f70bf 5101{
ca1d4a9e 5102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5103 int ret;
ca1d4a9e 5104
6f6fbe98
XG		 5105 if (vcpu->arch.pio.count)
5106 goto data_avail;
cf8f70bf 5107
cbfc6c91
WL		 5108 memset(vcpu->arch.pio_data, 0, size * count);
5109
6f6fbe98
XG		 5110 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5111 if (ret) {
5112data_avail:
5113 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5114 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5115 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5116 return 1;
5117 }
5118
cf8f70bf
GN		 5119 return 0;
5120}
5121
6f6fbe98
XG		 5122static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5123 int size, unsigned short port,
5124 const void *val, unsigned int count)
5125{
5126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5127
5128 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5129 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5130 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5131}
5132
bbd9b64e
CO		 5133static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5134{
5135 return kvm_x86_ops->get_segment_base(vcpu, seg);
5136}
5137
3cb16fe7 5138static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5139{
3cb16fe7 5140 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5141}
5142
ae6a2375 5143static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5144{
5145 if (!need_emulate_wbinvd(vcpu))
5146 return X86EMUL_CONTINUE;
5147
5148 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5149 int cpu = get_cpu();
5150
5151 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5152 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5153 wbinvd_ipi, NULL, 1);
2eec7343 5154 put_cpu();
f5f48ee1 5155 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5156 } else
5157 wbinvd();
f5f48ee1
SY		 5158 return X86EMUL_CONTINUE;
5159}
5cb56059
JS		 5160
5161int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5162{
6affcbed
KH		 5163 kvm_emulate_wbinvd_noskip(vcpu);
5164 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5165}
f5f48ee1
SY		 5166EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5167
5cb56059
JS		 5168
5169
bcaf5cc5
AK		 5170static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5171{
5cb56059 5172 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5173}
5174
52eb5a6d
XL		 5175static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5176 unsigned long *dest)
bbd9b64e 5177{
16f8a6f9 5178 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5179}
5180
52eb5a6d
XL		 5181static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5182 unsigned long value)
bbd9b64e 5183{
338dbc97 5184
717746e3 5185 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5186}
5187
52a46617 5188static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5189{
52a46617 5190 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5191}
5192
717746e3 5193static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5194{
717746e3 5195 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5196 unsigned long value;
5197
5198 switch (cr) {
5199 case 0:
5200 value = kvm_read_cr0(vcpu);
5201 break;
5202 case 2:
5203 value = vcpu->arch.cr2;
5204 break;
5205 case 3:
9f8fe504 5206 value = kvm_read_cr3(vcpu);
52a46617
GN		 5207 break;
5208 case 4:
5209 value = kvm_read_cr4(vcpu);
5210 break;
5211 case 8:
5212 value = kvm_get_cr8(vcpu);
5213 break;
5214 default:
a737f256 5215 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5216 return 0;
5217 }
5218
5219 return value;
5220}
5221
717746e3 5222static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5223{
717746e3 5224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5225 int res = 0;
5226
52a46617
GN		 5227 switch (cr) {
5228 case 0:
49a9b07e 5229 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5230 break;
5231 case 2:
5232 vcpu->arch.cr2 = val;
5233 break;
5234 case 3:
2390218b 5235 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5236 break;
5237 case 4:
a83b29c6 5238 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5239 break;
5240 case 8:
eea1cff9 5241 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5242 break;
5243 default:
a737f256 5244 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5245 res = -1;
52a46617 5246 }
0f12244f
GN		 5247
5248 return res;
52a46617
GN		 5249}
5250
717746e3 5251static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5252{
717746e3 5253 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5254}
5255
4bff1e86 5256static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5257{
4bff1e86 5258 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5259}
5260
4bff1e86 5261static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5262{
4bff1e86 5263 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5264}
5265
1ac9d0cf
AK		 5266static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5267{
5268 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5269}
5270
5271static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5272{
5273 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5274}
5275
4bff1e86
AK		 5276static unsigned long emulator_get_cached_segment_base(
5277 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5278{
4bff1e86 5279 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5280}
5281
1aa36616
AK		 5282static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5283 struct desc_struct *desc, u32 *base3,
5284 int seg)
2dafc6c2
GN		 5285{
5286 struct kvm_segment var;
5287
4bff1e86 5288 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5289 *selector = var.selector;
2dafc6c2 5290
378a8b09
GN		 5291 if (var.unusable) {
5292 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5293 if (base3)
5294 *base3 = 0;
2dafc6c2 5295 return false;
378a8b09 5296 }
2dafc6c2
GN		 5297
5298 if (var.g)
5299 var.limit >>= 12;
5300 set_desc_limit(desc, var.limit);
5301 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5302#ifdef CONFIG_X86_64
5303 if (base3)
5304 *base3 = var.base >> 32;
5305#endif
2dafc6c2
GN		 5306 desc->type = var.type;
5307 desc->s = var.s;
5308 desc->dpl = var.dpl;
5309 desc->p = var.present;
5310 desc->avl = var.avl;
5311 desc->l = var.l;
5312 desc->d = var.db;
5313 desc->g = var.g;
5314
5315 return true;
5316}
5317
1aa36616
AK		 5318static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5319 struct desc_struct *desc, u32 base3,
5320 int seg)
2dafc6c2 5321{
4bff1e86 5322 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5323 struct kvm_segment var;
5324
1aa36616 5325 var.selector = selector;
2dafc6c2 5326 var.base = get_desc_base(desc);
5601d05b
GN		 5327#ifdef CONFIG_X86_64
5328 var.base |= ((u64)base3) << 32;
5329#endif
2dafc6c2
GN		 5330 var.limit = get_desc_limit(desc);
5331 if (desc->g)
5332 var.limit = (var.limit << 12) | 0xfff;
5333 var.type = desc->type;
2dafc6c2
GN		 5334 var.dpl = desc->dpl;
5335 var.db = desc->d;
5336 var.s = desc->s;
5337 var.l = desc->l;
5338 var.g = desc->g;
5339 var.avl = desc->avl;
5340 var.present = desc->p;
5341 var.unusable = !var.present;
5342 var.padding = 0;
5343
5344 kvm_set_segment(vcpu, &var, seg);
5345 return;
5346}
5347
717746e3
AK		 5348static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5349 u32 msr_index, u64 *pdata)
5350{
609e36d3
PB		 5351 struct msr_data msr;
5352 int r;
5353
5354 msr.index = msr_index;
5355 msr.host_initiated = false;
5356 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5357 if (r)
5358 return r;
5359
5360 *pdata = msr.data;
5361 return 0;
717746e3
AK		 5362}
5363
5364static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5365 u32 msr_index, u64 data)
5366{
8fe8ab46
WA		 5367 struct msr_data msr;
5368
5369 msr.data = data;
5370 msr.index = msr_index;
5371 msr.host_initiated = false;
5372 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5373}
5374
64d60670
PB		 5375static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5376{
5377 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5378
5379 return vcpu->arch.smbase;
5380}
5381
5382static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5383{
5384 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5385
5386 vcpu->arch.smbase = smbase;
5387}
5388
67f4d428
NA		 5389static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5390 u32 pmc)
5391{
c6702c9d 5392 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5393}
5394
222d21aa
AK		 5395static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5396 u32 pmc, u64 *pdata)
5397{
c6702c9d 5398 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5399}
5400
6c3287f7
AK		 5401static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5402{
5403 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5404}
5405
2953538e 5406static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5407 struct x86_instruction_info *info,
c4f035c6
AK		 5408 enum x86_intercept_stage stage)
5409{
2953538e 5410 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5411}
5412
e911eb3b
YZ		 5413static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5414 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5415{
e911eb3b 5416 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5417}
5418
dd856efa
AK		 5419static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5420{
5421 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5422}
5423
5424static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5425{
5426 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5427}
5428
801806d9
NA		 5429static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5430{
5431 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5432}
5433
6ed071f0
LP		 5434static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5435{
5436 return emul_to_vcpu(ctxt)->arch.hflags;
5437}
5438
5439static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5440{
5441 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5442}
5443
0234bf88
LP		 5444static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5445{
5446 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5447}
5448
0225fb50 5449static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5450 .read_gpr = emulator_read_gpr,
5451 .write_gpr = emulator_write_gpr,
40d2dba3
PB		 5452 .read_std = emulator_read_std,
5453 .write_std = emulator_write_std,
7a036a6f 5454 .read_phys = kvm_read_guest_phys_system,
1871c602 5455 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5456 .read_emulated = emulator_read_emulated,
5457 .write_emulated = emulator_write_emulated,
5458 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5459 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5460 .pio_in_emulated = emulator_pio_in_emulated,
5461 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5462 .get_segment = emulator_get_segment,
5463 .set_segment = emulator_set_segment,
5951c442 5464 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5465 .get_gdt = emulator_get_gdt,
160ce1f1 5466 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5467 .set_gdt = emulator_set_gdt,
5468 .set_idt = emulator_set_idt,
52a46617
GN		 5469 .get_cr = emulator_get_cr,
5470 .set_cr = emulator_set_cr,
9c537244 5471 .cpl = emulator_get_cpl,
35aa5375
GN		 5472 .get_dr = emulator_get_dr,
5473 .set_dr = emulator_set_dr,
64d60670
PB		 5474 .get_smbase = emulator_get_smbase,
5475 .set_smbase = emulator_set_smbase,
717746e3
AK		 5476 .set_msr = emulator_set_msr,
5477 .get_msr = emulator_get_msr,
67f4d428 5478 .check_pmc = emulator_check_pmc,
222d21aa 5479 .read_pmc = emulator_read_pmc,
6c3287f7 5480 .halt = emulator_halt,
bcaf5cc5 5481 .wbinvd = emulator_wbinvd,
d6aa1000 5482 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5483 .intercept = emulator_intercept,
bdb42f5a 5484 .get_cpuid = emulator_get_cpuid,
801806d9 5485 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5486 .get_hflags = emulator_get_hflags,
5487 .set_hflags = emulator_set_hflags,
0234bf88 5488 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5489};
5490
95cb2295
GN		 5491static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5492{
37ccdcbe 5493 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5494 /*
5495 * an sti; sti; sequence only disable interrupts for the first
5496 * instruction. So, if the last instruction, be it emulated or
5497 * not, left the system with the INT_STI flag enabled, it
5498 * means that the last instruction is an sti. We should not
5499 * leave the flag on in this case. The same goes for mov ss
5500 */
37ccdcbe
PB		 5501 if (int_shadow & mask)
5502 mask = 0;
6addfc42 5503 if (unlikely(int_shadow || mask)) {
95cb2295 5504 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5505 if (!mask)
5506 kvm_make_request(KVM_REQ_EVENT, vcpu);
5507 }
95cb2295
GN		 5508}
5509
ef54bcfe 5510static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5511{
5512 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5513 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5514 return kvm_propagate_fault(vcpu, &ctxt->exception);
5515
5516 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5517 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5518 ctxt->exception.error_code);
54b8486f 5519 else
da9cb575 5520 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5521 return false;
54b8486f
GN		 5522}
5523
8ec4722d
MG		 5524static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5525{
adf52235 5526 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5527 int cs_db, cs_l;
5528
8ec4722d
MG		 5529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5530
adf52235 5531 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5532 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5533
adf52235
TY		 5534 ctxt->eip = kvm_rip_read(vcpu);
5535 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5536 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5537 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5538 cs_db ? X86EMUL_MODE_PROT32 :
5539 X86EMUL_MODE_PROT16;
a584539b 5540 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5541 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5542 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5543
dd856efa 5544 init_decode_cache(ctxt);
7ae441ea 5545 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5546}
5547
71f9833b 5548int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5549{
9d74191a 5550 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5551 int ret;
5552
5553 init_emulate_ctxt(vcpu);
5554
9dac77fa
AK		 5555 ctxt->op_bytes = 2;
5556 ctxt->ad_bytes = 2;
5557 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5558 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5559
5560 if (ret != X86EMUL_CONTINUE)
5561 return EMULATE_FAIL;
5562
9dac77fa 5563 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5564 kvm_rip_write(vcpu, ctxt->eip);
5565 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5566
5567 if (irq == NMI_VECTOR)
7460fb4a 5568 vcpu->arch.nmi_pending = 0;
63995653
MG		 5569 else
5570 vcpu->arch.interrupt.pending = false;
5571
5572 return EMULATE_DONE;
5573}
5574EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5575
6d77dbfc
GN		 5576static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5577{
fc3a9157
JR		 5578 int r = EMULATE_DONE;
5579
6d77dbfc
GN		 5580 ++vcpu->stat.insn_emulation_fail;
5581 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5582 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5583 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5584 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5585 vcpu->run->internal.ndata = 0;
1f4dcb3b 5586 r = EMULATE_USER_EXIT;
fc3a9157 5587 }
6d77dbfc 5588 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5589
5590 return r;
6d77dbfc
GN		 5591}
5592
93c05d3e 5593static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5594 bool write_fault_to_shadow_pgtable,
5595 int emulation_type)
a6f177ef 5596{
95b3cf69 5597 gpa_t gpa = cr2;
ba049e93 5598 kvm_pfn_t pfn;
a6f177ef 5599
991eebf9
GN		 5600 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5601 return false;
5602
95b3cf69
XG		 5603 if (!vcpu->arch.mmu.direct_map) {
5604 /*
5605 * Write permission should be allowed since only
5606 * write access need to be emulated.
5607 */
5608 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5609
95b3cf69
XG		 5610 /*
5611 * If the mapping is invalid in guest, let cpu retry
5612 * it to generate fault.
5613 */
5614 if (gpa == UNMAPPED_GVA)
5615 return true;
5616 }
a6f177ef 5617
8e3d9d06
XG		 5618 /*
5619 * Do not retry the unhandleable instruction if it faults on the
5620 * readonly host memory, otherwise it will goto a infinite loop:
5621 * retry instruction -> write #PF -> emulation fail -> retry
5622 * instruction -> ...
5623 */
5624 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5625
5626 /*
5627 * If the instruction failed on the error pfn, it can not be fixed,
5628 * report the error to userspace.
5629 */
5630 if (is_error_noslot_pfn(pfn))
5631 return false;
5632
5633 kvm_release_pfn_clean(pfn);
5634
5635 /* The instructions are well-emulated on direct mmu. */
5636 if (vcpu->arch.mmu.direct_map) {
5637 unsigned int indirect_shadow_pages;
5638
5639 spin_lock(&vcpu->kvm->mmu_lock);
5640 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5641 spin_unlock(&vcpu->kvm->mmu_lock);
5642
5643 if (indirect_shadow_pages)
5644 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5645
a6f177ef 5646 return true;
8e3d9d06 5647 }
a6f177ef 5648
95b3cf69
XG		 5649 /*
5650 * if emulation was due to access to shadowed page table
5651 * and it failed try to unshadow page and re-enter the
5652 * guest to let CPU execute the instruction.
5653 */
5654 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5655
5656 /*
5657 * If the access faults on its page table, it can not
5658 * be fixed by unprotecting shadow page and it should
5659 * be reported to userspace.
5660 */
5661 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5662}
5663
1cb3f3ae
XG		 5664static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5665 unsigned long cr2, int emulation_type)
5666{
5667 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5668 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5669
5670 last_retry_eip = vcpu->arch.last_retry_eip;
5671 last_retry_addr = vcpu->arch.last_retry_addr;
5672
5673 /*
5674 * If the emulation is caused by #PF and it is non-page_table
5675 * writing instruction, it means the VM-EXIT is caused by shadow
5676 * page protected, we can zap the shadow page and retry this
5677 * instruction directly.
5678 *
5679 * Note: if the guest uses a non-page-table modifying instruction
5680 * on the PDE that points to the instruction, then we will unmap
5681 * the instruction and go to an infinite loop. So, we cache the
5682 * last retried eip and the last fault address, if we meet the eip
5683 * and the address again, we can break out of the potential infinite
5684 * loop.
5685 */
5686 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5687
5688 if (!(emulation_type & EMULTYPE_RETRY))
5689 return false;
5690
5691 if (x86_page_table_writing_insn(ctxt))
5692 return false;
5693
5694 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5695 return false;
5696
5697 vcpu->arch.last_retry_eip = ctxt->eip;
5698 vcpu->arch.last_retry_addr = cr2;
5699
5700 if (!vcpu->arch.mmu.direct_map)
5701 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5702
22368028 5703 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5704
5705 return true;
5706}
5707
716d51ab
GN		 5708static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5709static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5710
64d60670 5711static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5712{
64d60670 5713 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5714 /* This is a good place to trace that we are exiting SMM. */
5715 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5716
c43203ca
PB		 5717 /* Process a latched INIT or SMI, if any. */
5718 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5719 }
699023e2
PB		 5720
5721 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5722}
5723
5724static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5725{
5726 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5727
a584539b 5728 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5729
5730 if (changed & HF_SMM_MASK)
5731 kvm_smm_changed(vcpu);
a584539b
PB		 5732}
5733
4a1e10d5
PB		 5734static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5735 unsigned long *db)
5736{
5737 u32 dr6 = 0;
5738 int i;
5739 u32 enable, rwlen;
5740
5741 enable = dr7;
5742 rwlen = dr7 >> 16;
5743 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5744 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5745 dr6 |= (1 << i);
5746 return dr6;
5747}
5748
c8401dda 5749static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5750{
5751 struct kvm_run *kvm_run = vcpu->run;
5752
c8401dda
PB		 5753 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5754 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5755 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5756 kvm_run->debug.arch.exception = DB_VECTOR;
5757 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5758 *r = EMULATE_USER_EXIT;
5759 } else {
5760 /*
5761 * "Certain debug exceptions may clear bit 0-3. The
5762 * remaining contents of the DR6 register are never
5763 * cleared by the processor".
5764 */
5765 vcpu->arch.dr6 &= ~15;
5766 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5767 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5768 }
5769}
5770
6affcbed
KH		 5771int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5772{
5773 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5774 int r = EMULATE_DONE;
5775
5776 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5777
5778 /*
5779 * rflags is the old, "raw" value of the flags. The new value has
5780 * not been saved yet.
5781 *
5782 * This is correct even for TF set by the guest, because "the
5783 * processor will not generate this exception after the instruction
5784 * that sets the TF flag".
5785 */
5786 if (unlikely(rflags & X86_EFLAGS_TF))
5787 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5788 return r == EMULATE_DONE;
5789}
5790EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5791
4a1e10d5
PB		 5792static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5793{
4a1e10d5
PB		 5794 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5795 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5796 struct kvm_run *kvm_run = vcpu->run;
5797 unsigned long eip = kvm_get_linear_rip(vcpu);
5798 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5799 vcpu->arch.guest_debug_dr7,
5800 vcpu->arch.eff_db);
5801
5802 if (dr6 != 0) {
6f43ed01 5803 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5804 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5805 kvm_run->debug.arch.exception = DB_VECTOR;
5806 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5807 *r = EMULATE_USER_EXIT;
5808 return true;
5809 }
5810 }
5811
4161a569
NA		 5812 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5813 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5814 unsigned long eip = kvm_get_linear_rip(vcpu);
5815 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5816 vcpu->arch.dr7,
5817 vcpu->arch.db);
5818
5819 if (dr6 != 0) {
5820 vcpu->arch.dr6 &= ~15;
6f43ed01 5821 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5822 kvm_queue_exception(vcpu, DB_VECTOR);
5823 *r = EMULATE_DONE;
5824 return true;
5825 }
5826 }
5827
5828 return false;
5829}
5830
51d8b661
AP		 5831int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5832 unsigned long cr2,
dc25e89e
AP		 5833 int emulation_type,
5834 void *insn,
5835 int insn_len)
bbd9b64e 5836{
95cb2295 5837 int r;
9d74191a 5838 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5839 bool writeback = true;
93c05d3e 5840 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5841
f0ace387
PB		 5842 vcpu->arch.l1tf_flush_l1d = true;
5843
93c05d3e
XG		 5844 /*
5845 * Clear write_fault_to_shadow_pgtable here to ensure it is
5846 * never reused.
5847 */
5848 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5849 kvm_clear_exception_queue(vcpu);
8d7d8102 5850
571008da 5851 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5852 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5853
5854 /*
5855 * We will reenter on the same instruction since
5856 * we do not set complete_userspace_io. This does not
5857 * handle watchpoints yet, those would be handled in
5858 * the emulate_ops.
5859 */
60165b0a
VK		 5860 if (!(emulation_type & EMULTYPE_SKIP) &&
5861 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5862 return r;
5863
9d74191a
TY		 5864 ctxt->interruptibility = 0;
5865 ctxt->have_exception = false;
e0ad0b47 5866 ctxt->exception.vector = -1;
9d74191a 5867 ctxt->perm_ok = false;
bbd9b64e 5868
b51e974f 5869 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5870
9d74191a 5871 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5872
e46479f8 5873 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5874 ++vcpu->stat.insn_emulation;
1d2887e2 5875 if (r != EMULATION_OK) {
4005996e
AK		 5876 if (emulation_type & EMULTYPE_TRAP_UD)
5877 return EMULATE_FAIL;
991eebf9
GN		 5878 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5879 emulation_type))
bbd9b64e 5880 return EMULATE_DONE;
6ea6e843
PB		 5881 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5882 return EMULATE_DONE;
6d77dbfc
GN		 5883 if (emulation_type & EMULTYPE_SKIP)
5884 return EMULATE_FAIL;
5885 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5886 }
5887 }
5888
ba8afb6b 5889 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5890 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5891 if (ctxt->eflags & X86_EFLAGS_RF)
5892 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5893 return EMULATE_DONE;
5894 }
5895
1cb3f3ae
XG		 5896 if (retry_instruction(ctxt, cr2, emulation_type))
5897 return EMULATE_DONE;
5898
7ae441ea 5899 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5900 changes registers values during IO operation */
7ae441ea
GN		 5901 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5902 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5903 emulator_invalidate_register_cache(ctxt);
7ae441ea 5904 }
4d2179e1 5905
5cd21917 5906restart:
0f89b207
TL		 5907 /* Save the faulting GPA (cr2) in the address field */
5908 ctxt->exception.address = cr2;
5909
9d74191a 5910 r = x86_emulate_insn(ctxt);
bbd9b64e 5911
775fde86
JR		 5912 if (r == EMULATION_INTERCEPTED)
5913 return EMULATE_DONE;
5914
d2ddd1c4 5915 if (r == EMULATION_FAILED) {
991eebf9
GN		 5916 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5917 emulation_type))
c3cd7ffa
GN		 5918 return EMULATE_DONE;
5919
6d77dbfc 5920 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5921 }
5922
9d74191a 5923 if (ctxt->have_exception) {
d2ddd1c4 5924 r = EMULATE_DONE;
ef54bcfe
PB		 5925 if (inject_emulated_exception(vcpu))
5926 return r;
d2ddd1c4 5927 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5928 if (!vcpu->arch.pio.in) {
5929 /* FIXME: return into emulator if single-stepping. */
3457e419 5930 vcpu->arch.pio.count = 0;
0912c977 5931 } else {
7ae441ea 5932 writeback = false;
716d51ab
GN		 5933 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5934 }
ac0a48c3 5935 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5936 } else if (vcpu->mmio_needed) {
5937 if (!vcpu->mmio_is_write)
5938 writeback = false;
ac0a48c3 5939 r = EMULATE_USER_EXIT;
716d51ab 5940 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5941 } else if (r == EMULATION_RESTART)
5cd21917 5942 goto restart;
d2ddd1c4
GN		 5943 else
5944 r = EMULATE_DONE;
f850e2e6 5945
7ae441ea 5946 if (writeback) {
6addfc42 5947 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5948 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5949 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5950 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5951 if (r == EMULATE_DONE &&
5952 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5953 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5954 if (!ctxt->have_exception ||
5955 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5956 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5957
5958 /*
5959 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5960 * do nothing, and it will be requested again as soon as
5961 * the shadow expires. But we still need to check here,
5962 * because POPF has no interrupt shadow.
5963 */
5964 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5965 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5966 } else
5967 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5968
5969 return r;
de7d789a 5970}
51d8b661 5971EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5972
cf8f70bf 5973int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5974{
cf8f70bf 5975 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5976 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5977 size, port, &val, 1);
cf8f70bf 5978 /* do not return to emulator after return from userspace */
7972995b 5979 vcpu->arch.pio.count = 0;
de7d789a
CO		 5980 return ret;
5981}
cf8f70bf 5982EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5983
8370c3d0
TL		 5984static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5985{
5986 unsigned long val;
5987
5988 /* We should only ever be called with arch.pio.count equal to 1 */
5989 BUG_ON(vcpu->arch.pio.count != 1);
5990
5991 /* For size less than 4 we merge, else we zero extend */
5992 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5993 : 0;
5994
5995 /*
5996 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5997 * the copy and tracing
5998 */
5999 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6000 vcpu->arch.pio.port, &val, 1);
6001 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6002
6003 return 1;
6004}
6005
6006int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6007{
6008 unsigned long val;
6009 int ret;
6010
6011 /* For size less than 4 we merge, else we zero extend */
6012 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6013
6014 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6015 &val, 1);
6016 if (ret) {
6017 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6018 return ret;
6019 }
6020
6021 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6022
6023 return 0;
6024}
6025EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6026
251a5fd6 6027static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6028{
0a3aee0d 6029 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6030 return 0;
8cfdc000
ZA		 6031}
6032
6033static void tsc_khz_changed(void *data)
c8076604 6034{
8cfdc000
ZA		 6035 struct cpufreq_freqs *freq = data;
6036 unsigned long khz = 0;
6037
6038 if (data)
6039 khz = freq->new;
6040 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6041 khz = cpufreq_quick_get(raw_smp_processor_id());
6042 if (!khz)
6043 khz = tsc_khz;
0a3aee0d 6044 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6045}
6046
c8076604
GH		 6047static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6048 void *data)
6049{
6050 struct cpufreq_freqs *freq = data;
6051 struct kvm *kvm;
6052 struct kvm_vcpu *vcpu;
6053 int i, send_ipi = 0;
6054
8cfdc000
ZA		 6055 /*
6056 * We allow guests to temporarily run on slowing clocks,
6057 * provided we notify them after, or to run on accelerating
6058 * clocks, provided we notify them before. Thus time never
6059 * goes backwards.
6060 *
6061 * However, we have a problem. We can't atomically update
6062 * the frequency of a given CPU from this function; it is
6063 * merely a notifier, which can be called from any CPU.
6064 * Changing the TSC frequency at arbitrary points in time
6065 * requires a recomputation of local variables related to
6066 * the TSC for each VCPU. We must flag these local variables
6067 * to be updated and be sure the update takes place with the
6068 * new frequency before any guests proceed.
6069 *
6070 * Unfortunately, the combination of hotplug CPU and frequency
6071 * change creates an intractable locking scenario; the order
6072 * of when these callouts happen is undefined with respect to
6073 * CPU hotplug, and they can race with each other. As such,
6074 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6075 * undefined; you can actually have a CPU frequency change take
6076 * place in between the computation of X and the setting of the
6077 * variable. To protect against this problem, all updates of
6078 * the per_cpu tsc_khz variable are done in an interrupt
6079 * protected IPI, and all callers wishing to update the value
6080 * must wait for a synchronous IPI to complete (which is trivial
6081 * if the caller is on the CPU already). This establishes the
6082 * necessary total order on variable updates.
6083 *
6084 * Note that because a guest time update may take place
6085 * anytime after the setting of the VCPU's request bit, the
6086 * correct TSC value must be set before the request. However,
6087 * to ensure the update actually makes it to any guest which
6088 * starts running in hardware virtualization between the set
6089 * and the acquisition of the spinlock, we must also ping the
6090 * CPU after setting the request bit.
6091 *
6092 */
6093
c8076604
GH		 6094 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6095 return 0;
6096 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6097 return 0;
8cfdc000
ZA		 6098
6099 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6100
2f303b74 6101 spin_lock(&kvm_lock);
c8076604 6102 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6103 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6104 if (vcpu->cpu != freq->cpu)
6105 continue;
c285545f 6106 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6107 if (vcpu->cpu != smp_processor_id())
8cfdc000 6108 send_ipi = 1;
c8076604
GH		 6109 }
6110 }
2f303b74 6111 spin_unlock(&kvm_lock);
c8076604
GH		 6112
6113 if (freq->old < freq->new && send_ipi) {
6114 /*
6115 * We upscale the frequency. Must make the guest
6116 * doesn't see old kvmclock values while running with
6117 * the new frequency, otherwise we risk the guest sees
6118 * time go backwards.
6119 *
6120 * In case we update the frequency for another cpu
6121 * (which might be in guest context) send an interrupt
6122 * to kick the cpu out of guest context. Next time
6123 * guest context is entered kvmclock will be updated,
6124 * so the guest will not see stale values.
6125 */
8cfdc000 6126 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6127 }
6128 return 0;
6129}
6130
6131static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6132 .notifier_call = kvmclock_cpufreq_notifier
6133};
6134
251a5fd6 6135static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6136{
251a5fd6
SAS		 6137 tsc_khz_changed(NULL);
6138 return 0;
8cfdc000
ZA		 6139}
6140
b820cc0c
ZA		 6141static void kvm_timer_init(void)
6142{
c285545f 6143 max_tsc_khz = tsc_khz;
460dd42e 6144
b820cc0c 6145 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6146#ifdef CONFIG_CPU_FREQ
6147 struct cpufreq_policy policy;
758f588d
BP		 6148 int cpu;
6149
c285545f 6150 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6151 cpu = get_cpu();
6152 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6153 if (policy.cpuinfo.max_freq)
6154 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6155 put_cpu();
c285545f 6156#endif
b820cc0c
ZA		 6157 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6158 CPUFREQ_TRANSITION_NOTIFIER);
6159 }
c285545f 6160 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6161
73c1b41e 6162 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6163 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6164}
6165
ff9d07a0
ZY		 6166static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6167
f5132b01 6168int kvm_is_in_guest(void)
ff9d07a0 6169{
086c9855 6170 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6171}
6172
6173static int kvm_is_user_mode(void)
6174{
6175 int user_mode = 3;
dcf46b94 6176
086c9855
AS		 6177 if (__this_cpu_read(current_vcpu))
6178 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6179
ff9d07a0
ZY		 6180 return user_mode != 0;
6181}
6182
6183static unsigned long kvm_get_guest_ip(void)
6184{
6185 unsigned long ip = 0;
dcf46b94 6186
086c9855
AS		 6187 if (__this_cpu_read(current_vcpu))
6188 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6189
ff9d07a0
ZY		 6190 return ip;
6191}
6192
6193static struct perf_guest_info_callbacks kvm_guest_cbs = {
6194 .is_in_guest = kvm_is_in_guest,
6195 .is_user_mode = kvm_is_user_mode,
6196 .get_guest_ip = kvm_get_guest_ip,
6197};
6198
6199void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6200{
086c9855 6201 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6202}
6203EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6204
6205void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6206{
086c9855 6207 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6208}
6209EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6210
ce88decf
XG		 6211static void kvm_set_mmio_spte_mask(void)
6212{
6213 u64 mask;
6214 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6215
6216 /*
6217 * Set the reserved bits and the present bit of an paging-structure
6218 * entry to generate page fault with PFER.RSV = 1.
6219 */
885032b9 6220 /* Mask the reserved physical address bits. */
d1431483 6221 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6222
885032b9 6223 /* Set the present bit. */
ce88decf
XG		 6224 mask |= 1ull;
6225
6226#ifdef CONFIG_X86_64
6227 /*
6228 * If reserved bit is not supported, clear the present bit to disable
6229 * mmio page fault.
6230 */
6231 if (maxphyaddr == 52)
6232 mask &= ~1ull;
6233#endif
6234
dcdca5fe 6235 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6236}
6237
16e8d74d
MT		 6238#ifdef CONFIG_X86_64
6239static void pvclock_gtod_update_fn(struct work_struct *work)
6240{
d828199e
MT		 6241 struct kvm *kvm;
6242
6243 struct kvm_vcpu *vcpu;
6244 int i;
6245
2f303b74 6246 spin_lock(&kvm_lock);
d828199e
MT		 6247 list_for_each_entry(kvm, &vm_list, vm_list)
6248 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6249 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6250 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6251 spin_unlock(&kvm_lock);
16e8d74d
MT		 6252}
6253
6254static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6255
6256/*
6257 * Notification about pvclock gtod data update.
6258 */
6259static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6260 void *priv)
6261{
6262 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6263 struct timekeeper *tk = priv;
6264
6265 update_pvclock_gtod(tk);
6266
6267 /* disable master clock if host does not trust, or does not
6268 * use, TSC clocksource
6269 */
6270 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6271 atomic_read(&kvm_guest_has_master_clock) != 0)
6272 queue_work(system_long_wq, &pvclock_gtod_work);
6273
6274 return 0;
6275}
6276
6277static struct notifier_block pvclock_gtod_notifier = {
6278 .notifier_call = pvclock_gtod_notify,
6279};
6280#endif
6281
f8c16bba 6282int kvm_arch_init(void *opaque)
043405e1 6283{
b820cc0c 6284 int r;
6b61edf7 6285 struct kvm_x86_ops *ops = opaque;
f8c16bba 6286
f8c16bba
ZX		 6287 if (kvm_x86_ops) {
6288 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6289 r = -EEXIST;
6290 goto out;
f8c16bba
ZX		 6291 }
6292
6293 if (!ops->cpu_has_kvm_support()) {
6294 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6295 r = -EOPNOTSUPP;
6296 goto out;
f8c16bba
ZX		 6297 }
6298 if (ops->disabled_by_bios()) {
1cdfde02 6299 printk(KERN_WARNING "kvm: disabled by bios\n");
56c6d28a
ZX		 6300 r = -EOPNOTSUPP;
6301 goto out;
f8c16bba
ZX		 6302 }
6303
013f6a5d
MT		 6304 r = -ENOMEM;
6305 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6306 if (!shared_msrs) {
6307 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6308 goto out;
6309 }
6310
97db56ce
AK		 6311 r = kvm_mmu_module_init();
6312 if (r)
013f6a5d 6313 goto out_free_percpu;
97db56ce 6314
ce88decf 6315 kvm_set_mmio_spte_mask();
97db56ce 6316
f8c16bba 6317 kvm_x86_ops = ops;
920c8377 6318
7b52345e 6319 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6320 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6321 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6322 kvm_timer_init();
c8076604 6323
ff9d07a0
ZY		 6324 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6325
d366bf7e 6326 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6327 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6328
c5cc421b 6329 kvm_lapic_init();
16e8d74d
MT		 6330#ifdef CONFIG_X86_64
6331 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6332#endif
6333
f8c16bba 6334 return 0;
56c6d28a 6335
013f6a5d
MT		 6336out_free_percpu:
6337 free_percpu(shared_msrs);
56c6d28a 6338out:
56c6d28a 6339 return r;
043405e1 6340}
8776e519 6341
f8c16bba
ZX		 6342void kvm_arch_exit(void)
6343{
cef84c30 6344 kvm_lapic_exit();
ff9d07a0
ZY		 6345 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6346
888d256e
JK		 6347 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6348 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6349 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6350 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6351#ifdef CONFIG_X86_64
6352 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6353#endif
f8c16bba 6354 kvm_x86_ops = NULL;
56c6d28a 6355 kvm_mmu_module_exit();
013f6a5d 6356 free_percpu(shared_msrs);
56c6d28a 6357}
f8c16bba 6358
5cb56059 6359int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6360{
6361 ++vcpu->stat.halt_exits;
35754c98 6362 if (lapic_in_kernel(vcpu)) {
a4535290 6363 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6364 return 1;
6365 } else {
6366 vcpu->run->exit_reason = KVM_EXIT_HLT;
6367 return 0;
6368 }
6369}
5cb56059
JS		 6370EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6371
6372int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6373{
6affcbed
KH		 6374 int ret = kvm_skip_emulated_instruction(vcpu);
6375 /*
6376 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6377 * KVM_EXIT_DEBUG here.
6378 */
6379 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6380}
8776e519
HB		 6381EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6382
8ef81a9a 6383#ifdef CONFIG_X86_64
55dd00a7
MT		 6384static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6385 unsigned long clock_type)
6386{
6387 struct kvm_clock_pairing clock_pairing;
6388 struct timespec ts;
80fbd89c 6389 u64 cycle;
55dd00a7
MT		 6390 int ret;
6391
6392 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6393 return -KVM_EOPNOTSUPP;
6394
6395 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6396 return -KVM_EOPNOTSUPP;
6397
6398 clock_pairing.sec = ts.tv_sec;
6399 clock_pairing.nsec = ts.tv_nsec;
6400 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6401 clock_pairing.flags = 0;
6402
6403 ret = 0;
6404 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6405 sizeof(struct kvm_clock_pairing)))
6406 ret = -KVM_EFAULT;
6407
6408 return ret;
6409}
8ef81a9a 6410#endif
55dd00a7 6411
6aef266c
SV		 6412/*
6413 * kvm_pv_kick_cpu_op: Kick a vcpu.
6414 *
6415 * @apicid - apicid of vcpu to be kicked.
6416 */
6417static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6418{
24d2166b 6419 struct kvm_lapic_irq lapic_irq;
6aef266c 6420
24d2166b
R		 6421 lapic_irq.shorthand = 0;
6422 lapic_irq.dest_mode = 0;
ebd28fcb 6423 lapic_irq.level = 0;
24d2166b 6424 lapic_irq.dest_id = apicid;
93bbf0b8 6425 lapic_irq.msi_redir_hint = false;
6aef266c 6426
24d2166b 6427 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6428 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6429}
6430
d62caabb
AS		 6431void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6432{
6433 vcpu->arch.apicv_active = false;
6434 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6435}
6436
8776e519
HB		 6437int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6438{
6439 unsigned long nr, a0, a1, a2, a3, ret;
ba30a6df 6440 int op_64_bit;
8776e519 6441
ba30a6df
MR		 6442 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6443 if (!kvm_hv_hypercall(vcpu))
6444 return 0;
6445 goto out;
6446 }
55cd8e5a 6447
5fdbf976
MT		 6448 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6449 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6450 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6451 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6452 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6453
229456fc 6454 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6455
a449c7aa
NA		 6456 op_64_bit = is_64_bit_mode(vcpu);
6457 if (!op_64_bit) {
8776e519
HB		 6458 nr &= 0xFFFFFFFF;
6459 a0 &= 0xFFFFFFFF;
6460 a1 &= 0xFFFFFFFF;
6461 a2 &= 0xFFFFFFFF;
6462 a3 &= 0xFFFFFFFF;
6463 }
6464
07708c4a
JK		 6465 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6466 ret = -KVM_EPERM;
ba30a6df 6467 goto out_error;
07708c4a
JK		 6468 }
6469
8776e519 6470 switch (nr) {
b93463aa
AK		 6471 case KVM_HC_VAPIC_POLL_IRQ:
6472 ret = 0;
6473 break;
6aef266c
SV		 6474 case KVM_HC_KICK_CPU:
6475 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6476 ret = 0;
6477 break;
8ef81a9a 6478#ifdef CONFIG_X86_64
55dd00a7
MT		 6479 case KVM_HC_CLOCK_PAIRING:
6480 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6481 break;
8ef81a9a 6482#endif
8776e519
HB		 6483 default:
6484 ret = -KVM_ENOSYS;
6485 break;
6486 }
ba30a6df 6487out_error:
a449c7aa
NA		 6488 if (!op_64_bit)
6489 ret = (u32)ret;
5fdbf976 6490 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
ba30a6df
MR		 6491
6492out:
f11c3a8d 6493 ++vcpu->stat.hypercalls;
ba30a6df 6494 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6495}
6496EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6497
b6785def 6498static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6499{
d6aa1000 6500 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6501 char instruction[3];
5fdbf976 6502 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6503
8776e519 6504 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6505
ce2e852e
DV		 6506 return emulator_write_emulated(ctxt, rip, instruction, 3,
6507 &ctxt->exception);
8776e519
HB		 6508}
6509
851ba692 6510static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6511{
782d422b
MG		 6512 return vcpu->run->request_interrupt_window &&
6513 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6514}
6515
851ba692 6516static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6517{
851ba692
AK		 6518 struct kvm_run *kvm_run = vcpu->run;
6519
91586a3b 6520 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6521 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6522 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6523 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6524 kvm_run->ready_for_interrupt_injection =
6525 pic_in_kernel(vcpu->kvm) ||
782d422b 6526 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6527}
6528
95ba8273
GN		 6529static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6530{
6531 int max_irr, tpr;
6532
6533 if (!kvm_x86_ops->update_cr8_intercept)
6534 return;
6535
bce87cce 6536 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6537 return;
6538
d62caabb
AS		 6539 if (vcpu->arch.apicv_active)
6540 return;
6541
8db3baa2
GN		 6542 if (!vcpu->arch.apic->vapic_addr)
6543 max_irr = kvm_lapic_find_highest_irr(vcpu);
6544 else
6545 max_irr = -1;
95ba8273
GN		 6546
6547 if (max_irr != -1)
6548 max_irr >>= 4;
6549
6550 tpr = kvm_lapic_get_cr8(vcpu);
6551
6552 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6553}
6554
b6b8a145 6555static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6556{
b6b8a145
JK		 6557 int r;
6558
95ba8273 6559 /* try to reinject previous events if any */
664f8e26
WL		 6560 if (vcpu->arch.exception.injected) {
6561 kvm_x86_ops->queue_exception(vcpu);
6562 return 0;
6563 }
6564
6565 /*
6566 * Exceptions must be injected immediately, or the exception
6567 * frame will have the address of the NMI or interrupt handler.
6568 */
6569 if (!vcpu->arch.exception.pending) {
6570 if (vcpu->arch.nmi_injected) {
6571 kvm_x86_ops->set_nmi(vcpu);
6572 return 0;
6573 }
6574
6575 if (vcpu->arch.interrupt.pending) {
6576 kvm_x86_ops->set_irq(vcpu);
6577 return 0;
6578 }
6579 }
6580
6581 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6582 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6583 if (r != 0)
6584 return r;
6585 }
6586
6587 /* try to inject new event if pending */
b59bb7bd 6588 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6589 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6590 vcpu->arch.exception.has_error_code,
6591 vcpu->arch.exception.error_code);
d6e8c854 6592
664f8e26
WL		 6593 vcpu->arch.exception.pending = false;
6594 vcpu->arch.exception.injected = true;
6595
d6e8c854
NA		 6596 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6597 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6598 X86_EFLAGS_RF);
6599
6bdf0662
NA		 6600 if (vcpu->arch.exception.nr == DB_VECTOR &&
6601 (vcpu->arch.dr7 & DR7_GD)) {
6602 vcpu->arch.dr7 &= ~DR7_GD;
6603 kvm_update_dr7(vcpu);
6604 }
6605
cfcd20e5 6606 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6607 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6608 vcpu->arch.smi_pending = false;
ee2cd4b7 6609 enter_smm(vcpu);
c43203ca 6610 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6611 --vcpu->arch.nmi_pending;
6612 vcpu->arch.nmi_injected = true;
6613 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6614 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6615 /*
6616 * Because interrupts can be injected asynchronously, we are
6617 * calling check_nested_events again here to avoid a race condition.
6618 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6619 * proposal and current concerns. Perhaps we should be setting
6620 * KVM_REQ_EVENT only on certain events and not unconditionally?
6621 */
6622 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6623 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6624 if (r != 0)
6625 return r;
6626 }
95ba8273 6627 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6628 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6629 false);
6630 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6631 }
6632 }
ee2cd4b7 6633
b6b8a145 6634 return 0;
95ba8273
GN		 6635}
6636
7460fb4a
AK		 6637static void process_nmi(struct kvm_vcpu *vcpu)
6638{
6639 unsigned limit = 2;
6640
6641 /*
6642 * x86 is limited to one NMI running, and one NMI pending after it.
6643 * If an NMI is already in progress, limit further NMIs to just one.
6644 * Otherwise, allow two (and we'll inject the first one immediately).
6645 */
6646 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6647 limit = 1;
6648
6649 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6650 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6651 kvm_make_request(KVM_REQ_EVENT, vcpu);
6652}
6653
ee2cd4b7 6654static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6655{
6656 u32 flags = 0;
6657 flags |= seg->g << 23;
6658 flags |= seg->db << 22;
6659 flags |= seg->l << 21;
6660 flags |= seg->avl << 20;
6661 flags |= seg->present << 15;
6662 flags |= seg->dpl << 13;
6663 flags |= seg->s << 12;
6664 flags |= seg->type << 8;
6665 return flags;
6666}
6667
ee2cd4b7 6668static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6669{
6670 struct kvm_segment seg;
6671 int offset;
6672
6673 kvm_get_segment(vcpu, &seg, n);
6674 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6675
6676 if (n < 3)
6677 offset = 0x7f84 + n * 12;
6678 else
6679 offset = 0x7f2c + (n - 3) * 12;
6680
6681 put_smstate(u32, buf, offset + 8, seg.base);
6682 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6683 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6684}
6685
efbb288a 6686#ifdef CONFIG_X86_64
ee2cd4b7 6687static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6688{
6689 struct kvm_segment seg;
6690 int offset;
6691 u16 flags;
6692
6693 kvm_get_segment(vcpu, &seg, n);
6694 offset = 0x7e00 + n * 16;
6695
ee2cd4b7 6696 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6697 put_smstate(u16, buf, offset, seg.selector);
6698 put_smstate(u16, buf, offset + 2, flags);
6699 put_smstate(u32, buf, offset + 4, seg.limit);
6700 put_smstate(u64, buf, offset + 8, seg.base);
6701}
efbb288a 6702#endif
660a5d51 6703
ee2cd4b7 6704static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6705{
6706 struct desc_ptr dt;
6707 struct kvm_segment seg;
6708 unsigned long val;
6709 int i;
6710
6711 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6712 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6713 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6714 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6715
6716 for (i = 0; i < 8; i++)
6717 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6718
6719 kvm_get_dr(vcpu, 6, &val);
6720 put_smstate(u32, buf, 0x7fcc, (u32)val);
6721 kvm_get_dr(vcpu, 7, &val);
6722 put_smstate(u32, buf, 0x7fc8, (u32)val);
6723
6724 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6725 put_smstate(u32, buf, 0x7fc4, seg.selector);
6726 put_smstate(u32, buf, 0x7f64, seg.base);
6727 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6728 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6729
6730 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6731 put_smstate(u32, buf, 0x7fc0, seg.selector);
6732 put_smstate(u32, buf, 0x7f80, seg.base);
6733 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6734 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6735
6736 kvm_x86_ops->get_gdt(vcpu, &dt);
6737 put_smstate(u32, buf, 0x7f74, dt.address);
6738 put_smstate(u32, buf, 0x7f70, dt.size);
6739
6740 kvm_x86_ops->get_idt(vcpu, &dt);
6741 put_smstate(u32, buf, 0x7f58, dt.address);
6742 put_smstate(u32, buf, 0x7f54, dt.size);
6743
6744 for (i = 0; i < 6; i++)
ee2cd4b7 6745 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6746
6747 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6748
6749 /* revision id */
6750 put_smstate(u32, buf, 0x7efc, 0x00020000);
6751 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6752}
6753
ee2cd4b7 6754static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6755{
6756#ifdef CONFIG_X86_64
6757 struct desc_ptr dt;
6758 struct kvm_segment seg;
6759 unsigned long val;
6760 int i;
6761
6762 for (i = 0; i < 16; i++)
6763 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6764
6765 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6766 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6767
6768 kvm_get_dr(vcpu, 6, &val);
6769 put_smstate(u64, buf, 0x7f68, val);
6770 kvm_get_dr(vcpu, 7, &val);
6771 put_smstate(u64, buf, 0x7f60, val);
6772
6773 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6774 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6775 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6776
6777 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6778
6779 /* revision id */
6780 put_smstate(u32, buf, 0x7efc, 0x00020064);
6781
6782 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6783
6784 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6785 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6786 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6787 put_smstate(u32, buf, 0x7e94, seg.limit);
6788 put_smstate(u64, buf, 0x7e98, seg.base);
6789
6790 kvm_x86_ops->get_idt(vcpu, &dt);
6791 put_smstate(u32, buf, 0x7e84, dt.size);
6792 put_smstate(u64, buf, 0x7e88, dt.address);
6793
6794 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6795 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6796 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6797 put_smstate(u32, buf, 0x7e74, seg.limit);
6798 put_smstate(u64, buf, 0x7e78, seg.base);
6799
6800 kvm_x86_ops->get_gdt(vcpu, &dt);
6801 put_smstate(u32, buf, 0x7e64, dt.size);
6802 put_smstate(u64, buf, 0x7e68, dt.address);
6803
6804 for (i = 0; i < 6; i++)
ee2cd4b7 6805 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6806#else
6807 WARN_ON_ONCE(1);
6808#endif
6809}
6810
ee2cd4b7 6811static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6812{
660a5d51 6813 struct kvm_segment cs, ds;
18c3626e 6814 struct desc_ptr dt;
660a5d51
PB		 6815 char buf[512];
6816 u32 cr0;
6817
660a5d51 6818 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6819 memset(buf, 0, 512);
d6321d49 6820 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6821 enter_smm_save_state_64(vcpu, buf);
660a5d51 6822 else
ee2cd4b7 6823 enter_smm_save_state_32(vcpu, buf);
660a5d51 6824
0234bf88
LP		 6825 /*
6826 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6827 * vCPU state (e.g. leave guest mode) after we've saved the state into
6828 * the SMM state-save area.
6829 */
6830 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6831
6832 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6833 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6834
6835 if (kvm_x86_ops->get_nmi_mask(vcpu))
6836 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6837 else
6838 kvm_x86_ops->set_nmi_mask(vcpu, true);
6839
6840 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6841 kvm_rip_write(vcpu, 0x8000);
6842
6843 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6844 kvm_x86_ops->set_cr0(vcpu, cr0);
6845 vcpu->arch.cr0 = cr0;
6846
6847 kvm_x86_ops->set_cr4(vcpu, 0);
6848
18c3626e
PB		 6849 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6850 dt.address = dt.size = 0;
6851 kvm_x86_ops->set_idt(vcpu, &dt);
6852
660a5d51
PB		 6853 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6854
6855 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6856 cs.base = vcpu->arch.smbase;
6857
6858 ds.selector = 0;
6859 ds.base = 0;
6860
6861 cs.limit = ds.limit = 0xffffffff;
6862 cs.type = ds.type = 0x3;
6863 cs.dpl = ds.dpl = 0;
6864 cs.db = ds.db = 0;
6865 cs.s = ds.s = 1;
6866 cs.l = ds.l = 0;
6867 cs.g = ds.g = 1;
6868 cs.avl = ds.avl = 0;
6869 cs.present = ds.present = 1;
6870 cs.unusable = ds.unusable = 0;
6871 cs.padding = ds.padding = 0;
6872
6873 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6874 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6875 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6876 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6877 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6878 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6879
d6321d49 6880 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6881 kvm_x86_ops->set_efer(vcpu, 0);
6882
6883 kvm_update_cpuid(vcpu);
6884 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6885}
6886
ee2cd4b7 6887static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6888{
6889 vcpu->arch.smi_pending = true;
6890 kvm_make_request(KVM_REQ_EVENT, vcpu);
6891}
6892
2860c4b1
PB		 6893void kvm_make_scan_ioapic_request(struct kvm *kvm)
6894{
6895 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6896}
6897
3d81bc7e 6898static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6899{
5c919412
AS		 6900 u64 eoi_exit_bitmap[4];
6901
3d81bc7e
YZ		 6902 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6903 return;
c7c9c56c 6904
6308630b 6905 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6906
b053b2ae 6907 if (irqchip_split(vcpu->kvm))
6308630b 6908 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6909 else {
76dfafd5 6910 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6911 kvm_x86_ops->sync_pir_to_irr(vcpu);
56a8dee5
WL		 6912 if (ioapic_in_kernel(vcpu->kvm))
6913 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6914 }
5c919412
AS		 6915 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6916 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6917 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6918}
6919
a70656b6
RK		 6920static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6921{
6922 ++vcpu->stat.tlb_flush;
6923 kvm_x86_ops->tlb_flush(vcpu);
6924}
6925
b1394e74
RK		 6926void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6927 unsigned long start, unsigned long end)
6928{
6929 unsigned long apic_address;
6930
6931 /*
6932 * The physical address of apic access page is stored in the VMCS.
6933 * Update it when it becomes invalid.
6934 */
6935 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6936 if (start <= apic_address && apic_address < end)
6937 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6938}
6939
4256f43f
TC		 6940void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6941{
c24ae0dc
TC		 6942 struct page *page = NULL;
6943
35754c98 6944 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6945 return;
6946
4256f43f
TC		 6947 if (!kvm_x86_ops->set_apic_access_page_addr)
6948 return;
6949
c24ae0dc 6950 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6951 if (is_error_page(page))
6952 return;
c24ae0dc
TC		 6953 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6954
6955 /*
6956 * Do not pin apic access page in memory, the MMU notifier
6957 * will call us again if it is migrated or swapped out.
6958 */
6959 put_page(page);
4256f43f
TC		 6960}
6961EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6962
9357d939 6963/*
362c698f 6964 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6965 * exiting to the userspace. Otherwise, the value will be returned to the
6966 * userspace.
6967 */
851ba692 6968static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6969{
6970 int r;
62a193ed
MG		 6971 bool req_int_win =
6972 dm_request_for_irq_injection(vcpu) &&
6973 kvm_cpu_accept_dm_intr(vcpu);
6974
730dca42 6975 bool req_immediate_exit = false;
b6c7a5dc 6976
2fa6e1e1 6977 if (kvm_request_pending(vcpu)) {
a8eeb04a 6978 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6979 kvm_mmu_unload(vcpu);
a8eeb04a 6980 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6981 __kvm_migrate_timers(vcpu);
d828199e
MT		 6982 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6983 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6984 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6985 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6986 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6987 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6988 if (unlikely(r))
6989 goto out;
6990 }
a8eeb04a 6991 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6992 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6993 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6994 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6995 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6996 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6997 r = 0;
6998 goto out;
6999 }
a8eeb04a 7000 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7001 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7002 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7003 r = 0;
7004 goto out;
7005 }
af585b92
GN		 7006 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7007 /* Page is swapped out. Do synthetic halt */
7008 vcpu->arch.apf.halted = true;
7009 r = 1;
7010 goto out;
7011 }
c9aaa895
GC		 7012 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7013 record_steal_time(vcpu);
64d60670
PB		 7014 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7015 process_smi(vcpu);
7460fb4a
AK		 7016 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7017 process_nmi(vcpu);
f5132b01 7018 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7019 kvm_pmu_handle_event(vcpu);
f5132b01 7020 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7021 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7022 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7023 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7024 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7025 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7026 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7027 vcpu->run->eoi.vector =
7028 vcpu->arch.pending_ioapic_eoi;
7029 r = 0;
7030 goto out;
7031 }
7032 }
3d81bc7e
YZ		 7033 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7034 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7035 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7036 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7037 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7038 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7039 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7040 r = 0;
7041 goto out;
7042 }
e516cebb
AS		 7043 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7044 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7045 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7046 r = 0;
7047 goto out;
7048 }
db397571
AS		 7049 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7050 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7051 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7052 r = 0;
7053 goto out;
7054 }
f3b138c5
AS		 7055
7056 /*
7057 * KVM_REQ_HV_STIMER has to be processed after
7058 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7059 * depend on the guest clock being up-to-date
7060 */
1f4b34f8
AS		 7061 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7062 kvm_hv_process_stimers(vcpu);
2f52d58c 7063 }
b93463aa 7064
b463a6f7 7065 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7066 ++vcpu->stat.req_event;
66450a21
JK		 7067 kvm_apic_accept_events(vcpu);
7068 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7069 r = 1;
7070 goto out;
7071 }
7072
b6b8a145
JK		 7073 if (inject_pending_event(vcpu, req_int_win) != 0)
7074 req_immediate_exit = true;
321c5658 7075 else {
cc3d967f 7076 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7077 *
cc3d967f
LP		 7078 * SMIs have three cases:
7079 * 1) They can be nested, and then there is nothing to
7080 * do here because RSM will cause a vmexit anyway.
7081 * 2) There is an ISA-specific reason why SMI cannot be
7082 * injected, and the moment when this changes can be
7083 * intercepted.
7084 * 3) Or the SMI can be pending because
7085 * inject_pending_event has completed the injection
7086 * of an IRQ or NMI from the previous vmexit, and
7087 * then we request an immediate exit to inject the
7088 * SMI.
c43203ca
PB		 7089 */
7090 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7091 if (!kvm_x86_ops->enable_smi_window(vcpu))
7092 req_immediate_exit = true;
321c5658
YS		 7093 if (vcpu->arch.nmi_pending)
7094 kvm_x86_ops->enable_nmi_window(vcpu);
7095 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7096 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7097 WARN_ON(vcpu->arch.exception.pending);
321c5658 7098 }
b463a6f7
AK		 7099
7100 if (kvm_lapic_enabled(vcpu)) {
7101 update_cr8_intercept(vcpu);
7102 kvm_lapic_sync_to_vapic(vcpu);
7103 }
7104 }
7105
d8368af8
AK		 7106 r = kvm_mmu_reload(vcpu);
7107 if (unlikely(r)) {
d905c069 7108 goto cancel_injection;
d8368af8
AK		 7109 }
7110
b6c7a5dc
HB		 7111 preempt_disable();
7112
7113 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7114
7115 /*
7116 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7117 * IPI are then delayed after guest entry, which ensures that they
7118 * result in virtual interrupt delivery.
7119 */
7120 local_irq_disable();
6b7e2d09
XG		 7121 vcpu->mode = IN_GUEST_MODE;
7122
01b71917
MT		 7123 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7124
0f127d12 7125 /*
b95234c8 7126 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7127 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7128 *
7129 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7130 * pairs with the memory barrier implicit in pi_test_and_set_on
7131 * (see vmx_deliver_posted_interrupt).
7132 *
7133 * 3) This also orders the write to mode from any reads to the page
7134 * tables done while the VCPU is running. Please see the comment
7135 * in kvm_flush_remote_tlbs.
6b7e2d09 7136 */
01b71917 7137 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7138
b95234c8
PB		 7139 /*
7140 * This handles the case where a posted interrupt was
7141 * notified with kvm_vcpu_kick.
7142 */
7143 if (kvm_lapic_enabled(vcpu)) {
7144 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7145 kvm_x86_ops->sync_pir_to_irr(vcpu);
7146 }
32f88400 7147
2fa6e1e1 7148 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7149 || need_resched() || signal_pending(current)) {
6b7e2d09 7150 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7151 smp_wmb();
6c142801
AK		 7152 local_irq_enable();
7153 preempt_enable();
01b71917 7154 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7155 r = 1;
d905c069 7156 goto cancel_injection;
6c142801
AK		 7157 }
7158
fc5b7f3b
DM		 7159 kvm_load_guest_xcr0(vcpu);
7160
c43203ca
PB		 7161 if (req_immediate_exit) {
7162 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7163 smp_send_reschedule(vcpu->cpu);
c43203ca 7164 }
d6185f20 7165
8b89fe1f
PB		 7166 trace_kvm_entry(vcpu->vcpu_id);
7167 wait_lapic_expire(vcpu);
6edaa530 7168 guest_enter_irqoff();
b6c7a5dc 7169
42dbaa5a 7170 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7171 set_debugreg(0, 7);
7172 set_debugreg(vcpu->arch.eff_db[0], 0);
7173 set_debugreg(vcpu->arch.eff_db[1], 1);
7174 set_debugreg(vcpu->arch.eff_db[2], 2);
7175 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7176 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7177 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7178 }
b6c7a5dc 7179
851ba692 7180 kvm_x86_ops->run(vcpu);
b6c7a5dc 7181
c77fb5fe
PB		 7182 /*
7183 * Do this here before restoring debug registers on the host. And
7184 * since we do this before handling the vmexit, a DR access vmexit
7185 * can (a) read the correct value of the debug registers, (b) set
7186 * KVM_DEBUGREG_WONT_EXIT again.
7187 */
7188 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7189 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7190 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7191 kvm_update_dr0123(vcpu);
7192 kvm_update_dr6(vcpu);
7193 kvm_update_dr7(vcpu);
7194 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7195 }
7196
24f1e32c
FW		 7197 /*
7198 * If the guest has used debug registers, at least dr7
7199 * will be disabled while returning to the host.
7200 * If we don't have active breakpoints in the host, we don't
7201 * care about the messed up debug address registers. But if
7202 * we have some of them active, restore the old state.
7203 */
59d8eb53 7204 if (hw_breakpoint_active())
24f1e32c 7205 hw_breakpoint_restore();
42dbaa5a 7206
4ba76538 7207 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7208
6b7e2d09 7209 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7210 smp_wmb();
a547c6db 7211
fc5b7f3b
DM		 7212 kvm_put_guest_xcr0(vcpu);
7213
a547c6db 7214 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7215
7216 ++vcpu->stat.exits;
7217
f2485b3e 7218 guest_exit_irqoff();
b6c7a5dc 7219
f2485b3e 7220 local_irq_enable();
b6c7a5dc
HB		 7221 preempt_enable();
7222
f656ce01 7223 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7224
b6c7a5dc
HB		 7225 /*
7226 * Profile KVM exit RIPs:
7227 */
7228 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7229 unsigned long rip = kvm_rip_read(vcpu);
7230 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7231 }
7232
cc578287
ZA		 7233 if (unlikely(vcpu->arch.tsc_always_catchup))
7234 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7235
5cfb1d5a
MT		 7236 if (vcpu->arch.apic_attention)
7237 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7238
618232e2 7239 vcpu->arch.gpa_available = false;
851ba692 7240 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7241 return r;
7242
7243cancel_injection:
7244 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7245 if (unlikely(vcpu->arch.apic_attention))
7246 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7247out:
7248 return r;
7249}
b6c7a5dc 7250
362c698f
PB		 7251static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7252{
bf9f6ac8
FW		 7253 if (!kvm_arch_vcpu_runnable(vcpu) &&
7254 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7255 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7256 kvm_vcpu_block(vcpu);
7257 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7258
7259 if (kvm_x86_ops->post_block)
7260 kvm_x86_ops->post_block(vcpu);
7261
9c8fd1ba
PB		 7262 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7263 return 1;
7264 }
362c698f
PB		 7265
7266 kvm_apic_accept_events(vcpu);
7267 switch(vcpu->arch.mp_state) {
7268 case KVM_MP_STATE_HALTED:
7269 vcpu->arch.pv.pv_unhalted = false;
7270 vcpu->arch.mp_state =
7271 KVM_MP_STATE_RUNNABLE;
7272 case KVM_MP_STATE_RUNNABLE:
7273 vcpu->arch.apf.halted = false;
7274 break;
7275 case KVM_MP_STATE_INIT_RECEIVED:
7276 break;
7277 default:
7278 return -EINTR;
7279 break;
7280 }
7281 return 1;
7282}
09cec754 7283
5d9bc648
PB		 7284static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7285{
0ad3bed6
PB		 7286 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7287 kvm_x86_ops->check_nested_events(vcpu, false);
7288
5d9bc648
PB		 7289 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7290 !vcpu->arch.apf.halted);
7291}
7292
362c698f 7293static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7294{
7295 int r;
f656ce01 7296 struct kvm *kvm = vcpu->kvm;
d7690175 7297
f656ce01 7298 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
f0ace387 7299 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7300
362c698f 7301 for (;;) {
58f800d5 7302 if (kvm_vcpu_running(vcpu)) {
851ba692 7303 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7304 } else {
362c698f 7305 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7306 }
7307
09cec754
GN		 7308 if (r <= 0)
7309 break;
7310
72875d8a 7311 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7312 if (kvm_cpu_has_pending_timer(vcpu))
7313 kvm_inject_pending_timer_irqs(vcpu);
7314
782d422b
MG		 7315 if (dm_request_for_irq_injection(vcpu) &&
7316 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7317 r = 0;
7318 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7319 ++vcpu->stat.request_irq_exits;
362c698f 7320 break;
09cec754 7321 }
af585b92
GN		 7322
7323 kvm_check_async_pf_completion(vcpu);
7324
09cec754
GN		 7325 if (signal_pending(current)) {
7326 r = -EINTR;
851ba692 7327 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7328 ++vcpu->stat.signal_exits;
362c698f 7329 break;
09cec754
GN		 7330 }
7331 if (need_resched()) {
f656ce01 7332 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7333 cond_resched();
f656ce01 7334 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7335 }
b6c7a5dc
HB		 7336 }
7337
f656ce01 7338 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7339
7340 return r;
7341}
7342
716d51ab
GN		 7343static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7344{
7345 int r;
7346 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7347 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7348 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7349 if (r != EMULATE_DONE)
7350 return 0;
7351 return 1;
7352}
7353
7354static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7355{
7356 BUG_ON(!vcpu->arch.pio.count);
7357
7358 return complete_emulated_io(vcpu);
7359}
7360
f78146b0
AK		 7361/*
7362 * Implements the following, as a state machine:
7363 *
7364 * read:
7365 * for each fragment
87da7e66
XG		 7366 * for each mmio piece in the fragment
7367 * write gpa, len
7368 * exit
7369 * copy data
f78146b0
AK		 7370 * execute insn
7371 *
7372 * write:
7373 * for each fragment
87da7e66
XG		 7374 * for each mmio piece in the fragment
7375 * write gpa, len
7376 * copy data
7377 * exit
f78146b0 7378 */
716d51ab 7379static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7380{
7381 struct kvm_run *run = vcpu->run;
f78146b0 7382 struct kvm_mmio_fragment *frag;
87da7e66 7383 unsigned len;
5287f194 7384
716d51ab 7385 BUG_ON(!vcpu->mmio_needed);
5287f194 7386
716d51ab 7387 /* Complete previous fragment */
87da7e66
XG		 7388 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7389 len = min(8u, frag->len);
716d51ab 7390 if (!vcpu->mmio_is_write)
87da7e66
XG		 7391 memcpy(frag->data, run->mmio.data, len);
7392
7393 if (frag->len <= 8) {
7394 /* Switch to the next fragment. */
7395 frag++;
7396 vcpu->mmio_cur_fragment++;
7397 } else {
7398 /* Go forward to the next mmio piece. */
7399 frag->data += len;
7400 frag->gpa += len;
7401 frag->len -= len;
7402 }
7403
a08d3b3b 7404 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7405 vcpu->mmio_needed = 0;
0912c977
PB		 7406
7407 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7408 if (vcpu->mmio_is_write)
716d51ab
GN		 7409 return 1;
7410 vcpu->mmio_read_completed = 1;
7411 return complete_emulated_io(vcpu);
7412 }
87da7e66 7413
716d51ab
GN		 7414 run->exit_reason = KVM_EXIT_MMIO;
7415 run->mmio.phys_addr = frag->gpa;
7416 if (vcpu->mmio_is_write)
87da7e66
XG		 7417 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7418 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7419 run->mmio.is_write = vcpu->mmio_is_write;
7420 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7421 return 0;
5287f194
AK		 7422}
7423
716d51ab 7424
b6c7a5dc
HB		 7425int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7426{
7427 int r;
b6c7a5dc 7428
20b7035c 7429 kvm_sigset_activate(vcpu);
ac9f6dc0 7430
5663d8f9
PX		 7431 kvm_load_guest_fpu(vcpu);
7432
a4535290 7433 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7434 if (kvm_run->immediate_exit) {
7435 r = -EINTR;
7436 goto out;
7437 }
b6c7a5dc 7438 kvm_vcpu_block(vcpu);
66450a21 7439 kvm_apic_accept_events(vcpu);
72875d8a 7440 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7441 r = -EAGAIN;
a0595000
JS		 7442 if (signal_pending(current)) {
7443 r = -EINTR;
7444 vcpu->run->exit_reason = KVM_EXIT_INTR;
7445 ++vcpu->stat.signal_exits;
7446 }
ac9f6dc0 7447 goto out;
b6c7a5dc
HB		 7448 }
7449
b6c7a5dc 7450 /* re-sync apic's tpr */
35754c98 7451 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7452 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7453 r = -EINVAL;
7454 goto out;
7455 }
7456 }
b6c7a5dc 7457
716d51ab
GN		 7458 if (unlikely(vcpu->arch.complete_userspace_io)) {
7459 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7460 vcpu->arch.complete_userspace_io = NULL;
7461 r = cui(vcpu);
7462 if (r <= 0)
5663d8f9 7463 goto out;
716d51ab
GN		 7464 } else
7465 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7466
460df4c1
PB		 7467 if (kvm_run->immediate_exit)
7468 r = -EINTR;
7469 else
7470 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7471
7472out:
5663d8f9 7473 kvm_put_guest_fpu(vcpu);
f1d86e46 7474 post_kvm_run_save(vcpu);
20b7035c 7475 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7476
b6c7a5dc
HB		 7477 return r;
7478}
7479
7480int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7481{
7ae441ea
GN		 7482 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7483 /*
7484 * We are here if userspace calls get_regs() in the middle of
7485 * instruction emulation. Registers state needs to be copied
4a969980 7486 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7487 * that usually, but some bad designed PV devices (vmware
7488 * backdoor interface) need this to work
7489 */
dd856efa 7490 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7491 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7492 }
5fdbf976
MT		 7493 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7494 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7495 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7496 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7497 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7498 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7499 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7500 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7501#ifdef CONFIG_X86_64
5fdbf976
MT		 7502 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7503 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7504 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7505 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7506 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7507 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7508 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7509 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7510#endif
7511
5fdbf976 7512 regs->rip = kvm_rip_read(vcpu);
91586a3b 7513 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7514
b6c7a5dc
HB		 7515 return 0;
7516}
7517
7518int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7519{
7ae441ea
GN		 7520 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7521 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7522
5fdbf976
MT		 7523 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7524 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7525 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7526 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7527 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7528 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7529 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7530 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7531#ifdef CONFIG_X86_64
5fdbf976
MT		 7532 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7533 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7534 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7535 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7536 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7537 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7538 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7539 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7540#endif
7541
5fdbf976 7542 kvm_rip_write(vcpu, regs->rip);
d73235d1 7543 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7544
b4f14abd
JK		 7545 vcpu->arch.exception.pending = false;
7546
3842d135
AK		 7547 kvm_make_request(KVM_REQ_EVENT, vcpu);
7548
b6c7a5dc
HB		 7549 return 0;
7550}
7551
b6c7a5dc
HB		 7552void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7553{
7554 struct kvm_segment cs;
7555
3e6e0aab 7556 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7557 *db = cs.db;
7558 *l = cs.l;
7559}
7560EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7561
7562int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7563 struct kvm_sregs *sregs)
7564{
89a27f4d 7565 struct desc_ptr dt;
b6c7a5dc 7566
3e6e0aab
GT		 7567 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7568 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7569 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7570 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7571 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7572 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7573
3e6e0aab
GT		 7574 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7575 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7576
7577 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7578 sregs->idt.limit = dt.size;
7579 sregs->idt.base = dt.address;
b6c7a5dc 7580 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7581 sregs->gdt.limit = dt.size;
7582 sregs->gdt.base = dt.address;
b6c7a5dc 7583
4d4ec087 7584 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7585 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7586 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7587 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7588 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7589 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7590 sregs->apic_base = kvm_get_apic_base(vcpu);
7591
923c61bb 7592 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7593
36752c9b 7594 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7595 set_bit(vcpu->arch.interrupt.nr,
7596 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7597
b6c7a5dc
HB		 7598 return 0;
7599}
7600
62d9f0db
MT		 7601int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7602 struct kvm_mp_state *mp_state)
7603{
66450a21 7604 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7605 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7606 vcpu->arch.pv.pv_unhalted)
7607 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7608 else
7609 mp_state->mp_state = vcpu->arch.mp_state;
7610
62d9f0db
MT		 7611 return 0;
7612}
7613
7614int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7615 struct kvm_mp_state *mp_state)
7616{
bce87cce 7617 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7618 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7619 return -EINVAL;
7620
28bf2888
DH		 7621 /* INITs are latched while in SMM */
7622 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7623 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7624 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7625 return -EINVAL;
7626
66450a21
JK		 7627 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7628 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7629 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7630 } else
7631 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7632 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7633 return 0;
7634}
7635
7f3d35fd
KW		 7636int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7637 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7638{
9d74191a 7639 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7640 int ret;
e01c2426 7641
8ec4722d 7642 init_emulate_ctxt(vcpu);
c697518a 7643
7f3d35fd 7644 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7645 has_error_code, error_code);
c697518a 7646
c697518a 7647 if (ret)
19d04437 7648 return EMULATE_FAIL;
37817f29 7649
9d74191a
TY		 7650 kvm_rip_write(vcpu, ctxt->eip);
7651 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7652 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7653 return EMULATE_DONE;
37817f29
IE		 7654}
7655EXPORT_SYMBOL_GPL(kvm_task_switch);
7656
f2981033
LT		 7657int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7658{
37b95951 7659 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7660 /*
7661 * When EFER.LME and CR0.PG are set, the processor is in
7662 * 64-bit mode (though maybe in a 32-bit code segment).
7663 * CR4.PAE and EFER.LMA must be set.
7664 */
37b95951 7665 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7666 || !(sregs->efer & EFER_LMA))
7667 return -EINVAL;
7668 } else {
7669 /*
7670 * Not in 64-bit mode: EFER.LMA is clear and the code
7671 * segment cannot be 64-bit.
7672 */
7673 if (sregs->efer & EFER_LMA || sregs->cs.l)
7674 return -EINVAL;
7675 }
7676
7677 return 0;
7678}
7679
b6c7a5dc
HB		 7680int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7681 struct kvm_sregs *sregs)
7682{
58cb628d 7683 struct msr_data apic_base_msr;
b6c7a5dc 7684 int mmu_reset_needed = 0;
00648597 7685 int cpuid_update_needed = 0;
63f42e02 7686 int pending_vec, max_bits, idx;
89a27f4d 7687 struct desc_ptr dt;
b6c7a5dc 7688
d6321d49
RK		 7689 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7690 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7691 return -EINVAL;
7692
f2981033
LT		 7693 if (kvm_valid_sregs(vcpu, sregs))
7694 return -EINVAL;
7695
d3802286
JM		 7696 apic_base_msr.data = sregs->apic_base;
7697 apic_base_msr.host_initiated = true;
7698 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7699 return -EINVAL;
7700
89a27f4d
GN		 7701 dt.size = sregs->idt.limit;
7702 dt.address = sregs->idt.base;
b6c7a5dc 7703 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7704 dt.size = sregs->gdt.limit;
7705 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7706 kvm_x86_ops->set_gdt(vcpu, &dt);
7707
ad312c7c 7708 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7709 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7710 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7711 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7712
2d3ad1f4 7713 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7714
f6801dff 7715 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7716 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7717
4d4ec087 7718 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7719 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7720 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7721
fc78f519 7722 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
00648597
WH		 7723 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
7724 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 7725 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
00648597 7726 if (cpuid_update_needed)
00b27a3e 7727 kvm_update_cpuid(vcpu);
63f42e02
XG		 7728
7729 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7730 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7731 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7732 mmu_reset_needed = 1;
7733 }
63f42e02 7734 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7735
7736 if (mmu_reset_needed)
7737 kvm_mmu_reset_context(vcpu);
7738
a50abc3b 7739 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7740 pending_vec = find_first_bit(
7741 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7742 if (pending_vec < max_bits) {
66fd3f7f 7743 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7744 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7745 }
7746
3e6e0aab
GT		 7747 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7748 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7749 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7750 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7751 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7752 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7753
3e6e0aab
GT		 7754 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7755 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7756
5f0269f5
ME		 7757 update_cr8_intercept(vcpu);
7758
9c3e4aab 7759 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7760 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7761 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7762 !is_protmode(vcpu))
9c3e4aab
MT		 7763 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7764
3842d135
AK		 7765 kvm_make_request(KVM_REQ_EVENT, vcpu);
7766
b6c7a5dc
HB		 7767 return 0;
7768}
7769
d0bfb940
JK		 7770int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7771 struct kvm_guest_debug *dbg)
b6c7a5dc 7772{
355be0b9 7773 unsigned long rflags;
ae675ef0 7774 int i, r;
b6c7a5dc 7775
4f926bf2
JK		 7776 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7777 r = -EBUSY;
7778 if (vcpu->arch.exception.pending)
2122ff5e 7779 goto out;
4f926bf2
JK		 7780 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7781 kvm_queue_exception(vcpu, DB_VECTOR);
7782 else
7783 kvm_queue_exception(vcpu, BP_VECTOR);
7784 }
7785
91586a3b
JK		 7786 /*
7787 * Read rflags as long as potentially injected trace flags are still
7788 * filtered out.
7789 */
7790 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7791
7792 vcpu->guest_debug = dbg->control;
7793 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7794 vcpu->guest_debug = 0;
7795
7796 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7797 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7798 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7799 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7800 } else {
7801 for (i = 0; i < KVM_NR_DB_REGS; i++)
7802 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7803 }
c8639010 7804 kvm_update_dr7(vcpu);
ae675ef0 7805
f92653ee
JK		 7806 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7807 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7808 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7809
91586a3b
JK		 7810 /*
7811 * Trigger an rflags update that will inject or remove the trace
7812 * flags.
7813 */
7814 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7815
a96036b8 7816 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7817
4f926bf2 7818 r = 0;
d0bfb940 7819
2122ff5e 7820out:
b6c7a5dc
HB		 7821
7822 return r;
7823}
7824
8b006791
ZX		 7825/*
7826 * Translate a guest virtual address to a guest physical address.
7827 */
7828int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7829 struct kvm_translation *tr)
7830{
7831 unsigned long vaddr = tr->linear_address;
7832 gpa_t gpa;
f656ce01 7833 int idx;
8b006791 7834
f656ce01 7835 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7836 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7837 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7838 tr->physical_address = gpa;
7839 tr->valid = gpa != UNMAPPED_GVA;
7840 tr->writeable = 1;
7841 tr->usermode = 0;
8b006791
ZX		 7842
7843 return 0;
7844}
7845
d0752060
HB		 7846int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7847{
c47ada30 7848 struct fxregs_state *fxsave =
7366ed77 7849 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7850
d0752060
HB		 7851 memcpy(fpu->fpr, fxsave->st_space, 128);
7852 fpu->fcw = fxsave->cwd;
7853 fpu->fsw = fxsave->swd;
7854 fpu->ftwx = fxsave->twd;
7855 fpu->last_opcode = fxsave->fop;
7856 fpu->last_ip = fxsave->rip;
7857 fpu->last_dp = fxsave->rdp;
7858 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7859
d0752060
HB		 7860 return 0;
7861}
7862
7863int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7864{
c47ada30 7865 struct fxregs_state *fxsave =
7366ed77 7866 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7867
d0752060
HB		 7868 memcpy(fxsave->st_space, fpu->fpr, 128);
7869 fxsave->cwd = fpu->fcw;
7870 fxsave->swd = fpu->fsw;
7871 fxsave->twd = fpu->ftwx;
7872 fxsave->fop = fpu->last_opcode;
7873 fxsave->rip = fpu->last_ip;
7874 fxsave->rdp = fpu->last_dp;
7875 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7876
d0752060
HB		 7877 return 0;
7878}
7879
0ee6a517 7880static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7881{
bf935b0b 7882 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7883 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7884 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7885 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7886
2acf923e
DC		 7887 /*
7888 * Ensure guest xcr0 is valid for loading
7889 */
d91cab78 7890 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7891
ad312c7c 7892 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7893}
d0752060 7894
f775b13e 7895/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7896void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7897{
f775b13e
RR		 7898 preempt_disable();
7899 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7900 /* PKRU is separately restored in kvm_x86_ops->run. */
7901 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7902 ~XFEATURE_MASK_PKRU);
f775b13e 7903 preempt_enable();
0c04851c 7904 trace_kvm_fpu(1);
d0752060 7905}
d0752060 7906
f775b13e 7907/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7908void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7909{
f775b13e 7910 preempt_disable();
4f836347 7911 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7912 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7913 preempt_enable();
f096ed85 7914 ++vcpu->stat.fpu_reload;
0c04851c 7915 trace_kvm_fpu(0);
d0752060 7916}
e9b11c17
ZX		 7917
7918void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7919{
bd768e14
IY		 7920 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7921
12f9a48f 7922 kvmclock_reset(vcpu);
7f1ea208 7923
e9b11c17 7924 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7925 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7926}
7927
7928struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7929 unsigned int id)
7930{
c447e76b
LL		 7931 struct kvm_vcpu *vcpu;
7932
6755bae8
ZA		 7933 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7934 printk_once(KERN_WARNING
7935 "kvm: SMP vm created on host with unstable TSC; "
7936 "guest TSC will not be reliable\n");
c447e76b
LL		 7937
7938 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7939
c447e76b 7940 return vcpu;
26e5215f 7941}
e9b11c17 7942
26e5215f
AK		 7943int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7944{
7945 int r;
e9b11c17 7946
19efffa2 7947 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7948 r = vcpu_load(vcpu);
7949 if (r)
7950 return r;
d28bc9dd 7951 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7952 kvm_mmu_setup(vcpu);
e9b11c17 7953 vcpu_put(vcpu);
26e5215f 7954 return r;
e9b11c17
ZX		 7955}
7956
31928aa5 7957void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7958{
8fe8ab46 7959 struct msr_data msr;
332967a3 7960 struct kvm *kvm = vcpu->kvm;
42897d86 7961
d3457c87
RK		 7962 kvm_hv_vcpu_postcreate(vcpu);
7963
31928aa5
DD		 7964 if (vcpu_load(vcpu))
7965 return;
8fe8ab46
WA		 7966 msr.data = 0x0;
7967 msr.index = MSR_IA32_TSC;
7968 msr.host_initiated = true;
7969 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7970 vcpu_put(vcpu);
7971
630994b3
MT		 7972 if (!kvmclock_periodic_sync)
7973 return;
7974
332967a3
AJ		 7975 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7976 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7977}
7978
d40ccc62 7979void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7980{
9fc77441 7981 int r;
344d9588
GN		 7982 vcpu->arch.apf.msr_val = 0;
7983
9fc77441
MT		 7984 r = vcpu_load(vcpu);
7985 BUG_ON(r);
e9b11c17
ZX		 7986 kvm_mmu_unload(vcpu);
7987 vcpu_put(vcpu);
7988
7989 kvm_x86_ops->vcpu_free(vcpu);
7990}
7991
d28bc9dd 7992void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7993{
a04c389c
RK		 7994 kvm_lapic_reset(vcpu, init_event);
7995
e69fab5d
PB		 7996 vcpu->arch.hflags = 0;
7997
c43203ca 7998 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7999 atomic_set(&vcpu->arch.nmi_queued, 0);
8000 vcpu->arch.nmi_pending = 0;
448fa4a9 8001 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8002 kvm_clear_interrupt_queue(vcpu);
8003 kvm_clear_exception_queue(vcpu);
664f8e26 8004 vcpu->arch.exception.pending = false;
448fa4a9 8005
42dbaa5a 8006 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8007 kvm_update_dr0123(vcpu);
6f43ed01 8008 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8009 kvm_update_dr6(vcpu);
42dbaa5a 8010 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8011 kvm_update_dr7(vcpu);
42dbaa5a 8012
1119022c
NA		 8013 vcpu->arch.cr2 = 0;
8014
3842d135 8015 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8016 vcpu->arch.apf.msr_val = 0;
c9aaa895 8017 vcpu->arch.st.msr_val = 0;
3842d135 8018
12f9a48f
GC		 8019 kvmclock_reset(vcpu);
8020
af585b92
GN		 8021 kvm_clear_async_pf_completion_queue(vcpu);
8022 kvm_async_pf_hash_reset(vcpu);
8023 vcpu->arch.apf.halted = false;
3842d135 8024
a554d207
WL		 8025 if (kvm_mpx_supported()) {
8026 void *mpx_state_buffer;
8027
8028 /*
8029 * To avoid have the INIT path from kvm_apic_has_events() that be
8030 * called with loaded FPU and does not let userspace fix the state.
8031 */
f775b13e
RR		 8032 if (init_event)
8033 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8034 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8035 XFEATURE_MASK_BNDREGS);
8036 if (mpx_state_buffer)
8037 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8038 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8039 XFEATURE_MASK_BNDCSR);
8040 if (mpx_state_buffer)
8041 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8042 if (init_event)
8043 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8044 }
8045
64d60670 8046 if (!init_event) {
d28bc9dd 8047 kvm_pmu_reset(vcpu);
64d60670 8048 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8049
8050 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8051 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8052
8053 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8054 }
f5132b01 8055
66f7b72e
JS		 8056 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8057 vcpu->arch.regs_avail = ~0;
8058 vcpu->arch.regs_dirty = ~0;
8059
a554d207
WL		 8060 vcpu->arch.ia32_xss = 0;
8061
d28bc9dd 8062 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8063}
8064
2b4a273b 8065void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8066{
8067 struct kvm_segment cs;
8068
8069 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8070 cs.selector = vector << 8;
8071 cs.base = vector << 12;
8072 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8073 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8074}
8075
13a34e06 8076int kvm_arch_hardware_enable(void)
e9b11c17 8077{
ca84d1a2
ZA		 8078 struct kvm *kvm;
8079 struct kvm_vcpu *vcpu;
8080 int i;
0dd6a6ed
ZA		 8081 int ret;
8082 u64 local_tsc;
8083 u64 max_tsc = 0;
8084 bool stable, backwards_tsc = false;
18863bdd
AK		 8085
8086 kvm_shared_msr_cpu_online();
13a34e06 8087 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8088 if (ret != 0)
8089 return ret;
8090
4ea1636b 8091 local_tsc = rdtsc();
0dd6a6ed
ZA		 8092 stable = !check_tsc_unstable();
8093 list_for_each_entry(kvm, &vm_list, vm_list) {
8094 kvm_for_each_vcpu(i, vcpu, kvm) {
8095 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8096 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8097 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8098 backwards_tsc = true;
8099 if (vcpu->arch.last_host_tsc > max_tsc)
8100 max_tsc = vcpu->arch.last_host_tsc;
8101 }
8102 }
8103 }
8104
8105 /*
8106 * Sometimes, even reliable TSCs go backwards. This happens on
8107 * platforms that reset TSC during suspend or hibernate actions, but
8108 * maintain synchronization. We must compensate. Fortunately, we can
8109 * detect that condition here, which happens early in CPU bringup,
8110 * before any KVM threads can be running. Unfortunately, we can't
8111 * bring the TSCs fully up to date with real time, as we aren't yet far
8112 * enough into CPU bringup that we know how much real time has actually
108b249c 8113 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8114 * variables that haven't been updated yet.
8115 *
8116 * So we simply find the maximum observed TSC above, then record the
8117 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8118 * the adjustment will be applied. Note that we accumulate
8119 * adjustments, in case multiple suspend cycles happen before some VCPU
8120 * gets a chance to run again. In the event that no KVM threads get a
8121 * chance to run, we will miss the entire elapsed period, as we'll have
8122 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8123 * loose cycle time. This isn't too big a deal, since the loss will be
8124 * uniform across all VCPUs (not to mention the scenario is extremely
8125 * unlikely). It is possible that a second hibernate recovery happens
8126 * much faster than a first, causing the observed TSC here to be
8127 * smaller; this would require additional padding adjustment, which is
8128 * why we set last_host_tsc to the local tsc observed here.
8129 *
8130 * N.B. - this code below runs only on platforms with reliable TSC,
8131 * as that is the only way backwards_tsc is set above. Also note
8132 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8133 * have the same delta_cyc adjustment applied if backwards_tsc
8134 * is detected. Note further, this adjustment is only done once,
8135 * as we reset last_host_tsc on all VCPUs to stop this from being
8136 * called multiple times (one for each physical CPU bringup).
8137 *
4a969980 8138 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8139 * will be compensated by the logic in vcpu_load, which sets the TSC to
8140 * catchup mode. This will catchup all VCPUs to real time, but cannot
8141 * guarantee that they stay in perfect synchronization.
8142 */
8143 if (backwards_tsc) {
8144 u64 delta_cyc = max_tsc - local_tsc;
8145 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8146 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8147 kvm_for_each_vcpu(i, vcpu, kvm) {
8148 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8149 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8150 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8151 }
8152
8153 /*
8154 * We have to disable TSC offset matching.. if you were
8155 * booting a VM while issuing an S4 host suspend....
8156 * you may have some problem. Solving this issue is
8157 * left as an exercise to the reader.
8158 */
8159 kvm->arch.last_tsc_nsec = 0;
8160 kvm->arch.last_tsc_write = 0;
8161 }
8162
8163 }
8164 return 0;
e9b11c17
ZX		 8165}
8166
13a34e06 8167void kvm_arch_hardware_disable(void)
e9b11c17 8168{
13a34e06
RK		 8169 kvm_x86_ops->hardware_disable();
8170 drop_user_return_notifiers();
e9b11c17
ZX		 8171}
8172
8173int kvm_arch_hardware_setup(void)
8174{
9e9c3fe4
NA		 8175 int r;
8176
8177 r = kvm_x86_ops->hardware_setup();
8178 if (r != 0)
8179 return r;
8180
35181e86
HZ		 8181 if (kvm_has_tsc_control) {
8182 /*
8183 * Make sure the user can only configure tsc_khz values that
8184 * fit into a signed integer.
8185 * A min value is not calculated needed because it will always
8186 * be 1 on all machines.
8187 */
8188 u64 max = min(0x7fffffffULL,
8189 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8190 kvm_max_guest_tsc_khz = max;
8191
ad721883 8192 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8193 }
ad721883 8194
9e9c3fe4
NA		 8195 kvm_init_msr_list();
8196 return 0;
e9b11c17
ZX		 8197}
8198
8199void kvm_arch_hardware_unsetup(void)
8200{
8201 kvm_x86_ops->hardware_unsetup();
8202}
8203
8204void kvm_arch_check_processor_compat(void *rtn)
8205{
8206 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8207}
8208
8209bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8210{
8211 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8212}
8213EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8214
8215bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8216{
8217 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8218}
8219
54e9818f 8220struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8221EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8222
e9b11c17
ZX		 8223int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8224{
8225 struct page *page;
e9b11c17
ZX		 8226 int r;
8227
b2a05fef 8228 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8229 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8230 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8231 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8232 else
a4535290 8233 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8234
8235 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8236 if (!page) {
8237 r = -ENOMEM;
8238 goto fail;
8239 }
ad312c7c 8240 vcpu->arch.pio_data = page_address(page);
e9b11c17 8241
cc578287 8242 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8243
e9b11c17
ZX		 8244 r = kvm_mmu_create(vcpu);
8245 if (r < 0)
8246 goto fail_free_pio_data;
8247
26de7988 8248 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8249 r = kvm_create_lapic(vcpu);
8250 if (r < 0)
8251 goto fail_mmu_destroy;
54e9818f
GN		 8252 } else
8253 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8254
890ca9ae
HY		 8255 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8256 GFP_KERNEL);
8257 if (!vcpu->arch.mce_banks) {
8258 r = -ENOMEM;
443c39bc 8259 goto fail_free_lapic;
890ca9ae
HY		 8260 }
8261 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8262
f1797359
WY		 8263 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8264 r = -ENOMEM;
f5f48ee1 8265 goto fail_free_mce_banks;
f1797359 8266 }
f5f48ee1 8267
0ee6a517 8268 fx_init(vcpu);
66f7b72e 8269
4344ee98 8270 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8271
5a4f55cd
EK		 8272 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8273
74545705
RK		 8274 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8275
af585b92 8276 kvm_async_pf_hash_reset(vcpu);
f5132b01 8277 kvm_pmu_init(vcpu);
af585b92 8278
1c1a9ce9 8279 vcpu->arch.pending_external_vector = -1;
de63ad4c 8280 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8281
5c919412
AS		 8282 kvm_hv_vcpu_init(vcpu);
8283
e9b11c17 8284 return 0;
0ee6a517 8285
f5f48ee1
SY		 8286fail_free_mce_banks:
8287 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8288fail_free_lapic:
8289 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8290fail_mmu_destroy:
8291 kvm_mmu_destroy(vcpu);
8292fail_free_pio_data:
ad312c7c 8293 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8294fail:
8295 return r;
8296}
8297
8298void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8299{
f656ce01
MT		 8300 int idx;
8301
1f4b34f8 8302 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8303 kvm_pmu_destroy(vcpu);
36cb93fd 8304 kfree(vcpu->arch.mce_banks);
e9b11c17 8305 kvm_free_lapic(vcpu);
f656ce01 8306 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8307 kvm_mmu_destroy(vcpu);
f656ce01 8308 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8309 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8310 if (!lapic_in_kernel(vcpu))
54e9818f 8311 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8312}
d19a9cd2 8313
e790d9ef
RK		 8314void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8315{
f0ace387 8316 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8317 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8318}
8319
e08b9637 8320int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8321{
e08b9637
CO		 8322 if (type)
8323 return -EINVAL;
8324
6ef768fa 8325 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8326 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8327 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8328 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8329 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8330
5550af4d
SY		 8331 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8332 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8333 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8334 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8335 &kvm->arch.irq_sources_bitmap);
5550af4d 8336
038f8c11 8337 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8338 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8339 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8340 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8341
108b249c 8342 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8343 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8344
7e44e449 8345 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8346 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8347
0eb05bf2 8348 kvm_page_track_init(kvm);
13d268ca 8349 kvm_mmu_init_vm(kvm);
0eb05bf2 8350
03543133
SS		 8351 if (kvm_x86_ops->vm_init)
8352 return kvm_x86_ops->vm_init(kvm);
8353
d89f5eff 8354 return 0;
d19a9cd2
ZX		 8355}
8356
8357static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8358{
9fc77441
MT		 8359 int r;
8360 r = vcpu_load(vcpu);
8361 BUG_ON(r);
d19a9cd2
ZX		 8362 kvm_mmu_unload(vcpu);
8363 vcpu_put(vcpu);
8364}
8365
8366static void kvm_free_vcpus(struct kvm *kvm)
8367{
8368 unsigned int i;
988a2cae 8369 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8370
8371 /*
8372 * Unpin any mmu pages first.
8373 */
af585b92
GN		 8374 kvm_for_each_vcpu(i, vcpu, kvm) {
8375 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8376 kvm_unload_vcpu_mmu(vcpu);
af585b92 8377 }
988a2cae
GN		 8378 kvm_for_each_vcpu(i, vcpu, kvm)
8379 kvm_arch_vcpu_free(vcpu);
8380
8381 mutex_lock(&kvm->lock);
8382 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8383 kvm->vcpus[i] = NULL;
d19a9cd2 8384
988a2cae
GN		 8385 atomic_set(&kvm->online_vcpus, 0);
8386 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8387}
8388
ad8ba2cd
SY		 8389void kvm_arch_sync_events(struct kvm *kvm)
8390{
332967a3 8391 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8392 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8393 kvm_free_pit(kvm);
ad8ba2cd
SY		 8394}
8395
1d8007bd 8396int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8397{
8398 int i, r;
25188b99 8399 unsigned long hva;
f0d648bd
PB		 8400 struct kvm_memslots *slots = kvm_memslots(kvm);
8401 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8402
8403 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8404 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8405 return -EINVAL;
9da0e4d5 8406
f0d648bd
PB		 8407 slot = id_to_memslot(slots, id);
8408 if (size) {
b21629da 8409 if (slot->npages)
f0d648bd
PB		 8410 return -EEXIST;
8411
8412 /*
8413 * MAP_SHARED to prevent internal slot pages from being moved
8414 * by fork()/COW.
8415 */
8416 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8417 MAP_SHARED | MAP_ANONYMOUS, 0);
8418 if (IS_ERR((void *)hva))
8419 return PTR_ERR((void *)hva);
8420 } else {
8421 if (!slot->npages)
8422 return 0;
8423
8424 hva = 0;
8425 }
8426
8427 old = *slot;
9da0e4d5 8428 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8429 struct kvm_userspace_memory_region m;
9da0e4d5 8430
1d8007bd
PB		 8431 m.slot = id | (i << 16);
8432 m.flags = 0;
8433 m.guest_phys_addr = gpa;
f0d648bd 8434 m.userspace_addr = hva;
1d8007bd 8435 m.memory_size = size;
9da0e4d5
PB		 8436 r = __kvm_set_memory_region(kvm, &m);
8437 if (r < 0)
8438 return r;
8439 }
8440
55a4a47b
EB		 8441 if (!size)
8442 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8443
9da0e4d5
PB		 8444 return 0;
8445}
8446EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8447
1d8007bd 8448int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8449{
8450 int r;
8451
8452 mutex_lock(&kvm->slots_lock);
1d8007bd 8453 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8454 mutex_unlock(&kvm->slots_lock);
8455
8456 return r;
8457}
8458EXPORT_SYMBOL_GPL(x86_set_memory_region);
8459
d19a9cd2
ZX		 8460void kvm_arch_destroy_vm(struct kvm *kvm)
8461{
27469d29
AH		 8462 if (current->mm == kvm->mm) {
8463 /*
8464 * Free memory regions allocated on behalf of userspace,
8465 * unless the the memory map has changed due to process exit
8466 * or fd copying.
8467 */
1d8007bd
PB		 8468 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8469 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8470 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8471 }
03543133
SS		 8472 if (kvm_x86_ops->vm_destroy)
8473 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8474 kvm_pic_destroy(kvm);
8475 kvm_ioapic_destroy(kvm);
d19a9cd2 8476 kvm_free_vcpus(kvm);
af1bae54 8477 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8478 kvm_mmu_uninit_vm(kvm);
2beb6dad 8479 kvm_page_track_cleanup(kvm);
d19a9cd2 8480}
0de10343 8481
5587027c 8482void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8483 struct kvm_memory_slot *dont)
8484{
8485 int i;
8486
d89cc617
TY		 8487 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8488 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8489 kvfree(free->arch.rmap[i]);
d89cc617 8490 free->arch.rmap[i] = NULL;
77d11309 8491 }
d89cc617
TY		 8492 if (i == 0)
8493 continue;
8494
8495 if (!dont || free->arch.lpage_info[i - 1] !=
8496 dont->arch.lpage_info[i - 1]) {
548ef284 8497 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8498 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8499 }
8500 }
21ebbeda
XG		 8501
8502 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8503}
8504
5587027c
AK		 8505int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8506 unsigned long npages)
db3fe4eb
TY		 8507{
8508 int i;
8509
d89cc617 8510 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8511 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8512 unsigned long ugfn;
8513 int lpages;
d89cc617 8514 int level = i + 1;
db3fe4eb
TY		 8515
8516 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8517 slot->base_gfn, level) + 1;
8518
d89cc617 8519 slot->arch.rmap[i] =
a7c3e901 8520 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8521 if (!slot->arch.rmap[i])
77d11309 8522 goto out_free;
d89cc617
TY		 8523 if (i == 0)
8524 continue;
77d11309 8525
a7c3e901 8526 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8527 if (!linfo)
db3fe4eb
TY		 8528 goto out_free;
8529
92f94f1e
XG		 8530 slot->arch.lpage_info[i - 1] = linfo;
8531
db3fe4eb 8532 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8533 linfo[0].disallow_lpage = 1;
db3fe4eb 8534 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8535 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8536 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8537 /*
8538 * If the gfn and userspace address are not aligned wrt each
8539 * other, or if explicitly asked to, disable large page
8540 * support for this slot
8541 */
8542 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8543 !kvm_largepages_enabled()) {
8544 unsigned long j;
8545
8546 for (j = 0; j < lpages; ++j)
92f94f1e 8547 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8548 }
8549 }
8550
21ebbeda
XG		 8551 if (kvm_page_track_create_memslot(slot, npages))
8552 goto out_free;
8553
db3fe4eb
TY		 8554 return 0;
8555
8556out_free:
d89cc617 8557 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8558 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8559 slot->arch.rmap[i] = NULL;
8560 if (i == 0)
8561 continue;
8562
548ef284 8563 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8564 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8565 }
8566 return -ENOMEM;
8567}
8568
15f46015 8569void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8570{
e6dff7d1
TY		 8571 /*
8572 * memslots->generation has been incremented.
8573 * mmio generation may have reached its maximum value.
8574 */
54bf36aa 8575 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8576}
8577
f7784b8e
MT		 8578int kvm_arch_prepare_memory_region(struct kvm *kvm,
8579 struct kvm_memory_slot *memslot,
09170a49 8580 const struct kvm_userspace_memory_region *mem,
7b6195a9 8581 enum kvm_mr_change change)
0de10343 8582{
f7784b8e
MT		 8583 return 0;
8584}
8585
88178fd4
KH		 8586static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8587 struct kvm_memory_slot *new)
8588{
8589 /* Still write protect RO slot */
8590 if (new->flags & KVM_MEM_READONLY) {
8591 kvm_mmu_slot_remove_write_access(kvm, new);
8592 return;
8593 }
8594
8595 /*
8596 * Call kvm_x86_ops dirty logging hooks when they are valid.
8597 *
8598 * kvm_x86_ops->slot_disable_log_dirty is called when:
8599 *
8600 * - KVM_MR_CREATE with dirty logging is disabled
8601 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8602 *
8603 * The reason is, in case of PML, we need to set D-bit for any slots
8604 * with dirty logging disabled in order to eliminate unnecessary GPA
8605 * logging in PML buffer (and potential PML buffer full VMEXT). This
8606 * guarantees leaving PML enabled during guest's lifetime won't have
8607 * any additonal overhead from PML when guest is running with dirty
8608 * logging disabled for memory slots.
8609 *
8610 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8611 * to dirty logging mode.
8612 *
8613 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8614 *
8615 * In case of write protect:
8616 *
8617 * Write protect all pages for dirty logging.
8618 *
8619 * All the sptes including the large sptes which point to this
8620 * slot are set to readonly. We can not create any new large
8621 * spte on this slot until the end of the logging.
8622 *
8623 * See the comments in fast_page_fault().
8624 */
8625 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8626 if (kvm_x86_ops->slot_enable_log_dirty)
8627 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8628 else
8629 kvm_mmu_slot_remove_write_access(kvm, new);
8630 } else {
8631 if (kvm_x86_ops->slot_disable_log_dirty)
8632 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8633 }
8634}
8635
f7784b8e 8636void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8637 const struct kvm_userspace_memory_region *mem,
8482644a 8638 const struct kvm_memory_slot *old,
f36f3f28 8639 const struct kvm_memory_slot *new,
8482644a 8640 enum kvm_mr_change change)
f7784b8e 8641{
8482644a 8642 int nr_mmu_pages = 0;
f7784b8e 8643
48c0e4e9
XG		 8644 if (!kvm->arch.n_requested_mmu_pages)
8645 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8646
48c0e4e9 8647 if (nr_mmu_pages)
0de10343 8648 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8649
3ea3b7fa
WL		 8650 /*
8651 * Dirty logging tracks sptes in 4k granularity, meaning that large
8652 * sptes have to be split. If live migration is successful, the guest
8653 * in the source machine will be destroyed and large sptes will be
8654 * created in the destination. However, if the guest continues to run
8655 * in the source machine (for example if live migration fails), small
8656 * sptes will remain around and cause bad performance.
8657 *
8658 * Scan sptes if dirty logging has been stopped, dropping those
8659 * which can be collapsed into a single large-page spte. Later
8660 * page faults will create the large-page sptes.
8661 */
8662 if ((change != KVM_MR_DELETE) &&
8663 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8664 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8665 kvm_mmu_zap_collapsible_sptes(kvm, new);
8666
c972f3b1 8667 /*
88178fd4 8668 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8669 *
88178fd4
KH		 8670 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8671 * been zapped so no dirty logging staff is needed for old slot. For
8672 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8673 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8674 *
8675 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8676 */
88178fd4 8677 if (change != KVM_MR_DELETE)
f36f3f28 8678 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8679}
1d737c8a 8680
2df72e9b 8681void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8682{
6ca18b69 8683 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8684}
8685
2df72e9b
MT		 8686void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8687 struct kvm_memory_slot *slot)
8688{
ae7cd873 8689 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8690}
8691
5d9bc648
PB		 8692static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8693{
8694 if (!list_empty_careful(&vcpu->async_pf.done))
8695 return true;
8696
8697 if (kvm_apic_has_events(vcpu))
8698 return true;
8699
8700 if (vcpu->arch.pv.pv_unhalted)
8701 return true;
8702
a5f01f8e
WL		 8703 if (vcpu->arch.exception.pending)
8704 return true;
8705
47a66eed
Z		 8706 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8707 (vcpu->arch.nmi_pending &&
8708 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8709 return true;
8710
47a66eed
Z		 8711 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8712 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8713 return true;
8714
5d9bc648
PB		 8715 if (kvm_arch_interrupt_allowed(vcpu) &&
8716 kvm_cpu_has_interrupt(vcpu))
8717 return true;
8718
1f4b34f8
AS		 8719 if (kvm_hv_has_stimer_pending(vcpu))
8720 return true;
8721
5d9bc648
PB		 8722 return false;
8723}
8724
1d737c8a
ZX		 8725int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8726{
5d9bc648 8727 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8728}
5736199a 8729
199b5763
LM		 8730bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8731{
de63ad4c 8732 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8733}
8734
b6d33834 8735int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8736{
b6d33834 8737 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8738}
78646121
GN		 8739
8740int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8741{
8742 return kvm_x86_ops->interrupt_allowed(vcpu);
8743}
229456fc 8744
82b32774 8745unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8746{
82b32774
NA		 8747 if (is_64_bit_mode(vcpu))
8748 return kvm_rip_read(vcpu);
8749 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8750 kvm_rip_read(vcpu));
8751}
8752EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8753
82b32774
NA		 8754bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8755{
8756 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8757}
8758EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8759
94fe45da
JK		 8760unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8761{
8762 unsigned long rflags;
8763
8764 rflags = kvm_x86_ops->get_rflags(vcpu);
8765 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8766 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8767 return rflags;
8768}
8769EXPORT_SYMBOL_GPL(kvm_get_rflags);
8770
6addfc42 8771static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8772{
8773 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8774 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8775 rflags |= X86_EFLAGS_TF;
94fe45da 8776 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8777}
8778
8779void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8780{
8781 __kvm_set_rflags(vcpu, rflags);
3842d135 8782 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8783}
8784EXPORT_SYMBOL_GPL(kvm_set_rflags);
8785
56028d08
GN		 8786void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8787{
8788 int r;
8789
fb67e14f 8790 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8791 work->wakeup_all)
56028d08
GN		 8792 return;
8793
8794 r = kvm_mmu_reload(vcpu);
8795 if (unlikely(r))
8796 return;
8797
fb67e14f
XG		 8798 if (!vcpu->arch.mmu.direct_map &&
8799 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8800 return;
8801
56028d08
GN		 8802 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8803}
8804
af585b92
GN		 8805static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8806{
8807 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8808}
8809
8810static inline u32 kvm_async_pf_next_probe(u32 key)
8811{
8812 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8813}
8814
8815static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8816{
8817 u32 key = kvm_async_pf_hash_fn(gfn);
8818
8819 while (vcpu->arch.apf.gfns[key] != ~0)
8820 key = kvm_async_pf_next_probe(key);
8821
8822 vcpu->arch.apf.gfns[key] = gfn;
8823}
8824
8825static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8826{
8827 int i;
8828 u32 key = kvm_async_pf_hash_fn(gfn);
8829
8830 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8831 (vcpu->arch.apf.gfns[key] != gfn &&
8832 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8833 key = kvm_async_pf_next_probe(key);
8834
8835 return key;
8836}
8837
8838bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8839{
8840 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8841}
8842
8843static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8844{
8845 u32 i, j, k;
8846
8847 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8848 while (true) {
8849 vcpu->arch.apf.gfns[i] = ~0;
8850 do {
8851 j = kvm_async_pf_next_probe(j);
8852 if (vcpu->arch.apf.gfns[j] == ~0)
8853 return;
8854 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8855 /*
8856 * k lies cyclically in ]i,j]
8857 * | i.k.j |
8858 * |....j i.k.| or |.k..j i...|
8859 */
8860 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8861 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8862 i = j;
8863 }
8864}
8865
7c90705b
GN		 8866static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8867{
4e335d9e
PB		 8868
8869 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8870 sizeof(val));
7c90705b
GN		 8871}
8872
9a6e7c39
WL		 8873static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8874{
8875
8876 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8877 sizeof(u32));
8878}
8879
af585b92
GN		 8880void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8881 struct kvm_async_pf *work)
8882{
6389ee94
AK		 8883 struct x86_exception fault;
8884
7c90705b 8885 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8886 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8887
8888 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8889 (vcpu->arch.apf.send_user_only &&
8890 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8891 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8892 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8893 fault.vector = PF_VECTOR;
8894 fault.error_code_valid = true;
8895 fault.error_code = 0;
8896 fault.nested_page_fault = false;
8897 fault.address = work->arch.token;
adfe20fb 8898 fault.async_page_fault = true;
6389ee94 8899 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8900 }
af585b92
GN		 8901}
8902
8903void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8904 struct kvm_async_pf *work)
8905{
6389ee94 8906 struct x86_exception fault;
9a6e7c39 8907 u32 val;
6389ee94 8908
f2e10669 8909 if (work->wakeup_all)
7c90705b
GN		 8910 work->arch.token = ~0; /* broadcast wakeup */
8911 else
8912 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8913 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8914
9a6e7c39
WL		 8915 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8916 !apf_get_user(vcpu, &val)) {
8917 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8918 vcpu->arch.exception.pending &&
8919 vcpu->arch.exception.nr == PF_VECTOR &&
8920 !apf_put_user(vcpu, 0)) {
8921 vcpu->arch.exception.injected = false;
8922 vcpu->arch.exception.pending = false;
8923 vcpu->arch.exception.nr = 0;
8924 vcpu->arch.exception.has_error_code = false;
8925 vcpu->arch.exception.error_code = 0;
8926 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8927 fault.vector = PF_VECTOR;
8928 fault.error_code_valid = true;
8929 fault.error_code = 0;
8930 fault.nested_page_fault = false;
8931 fault.address = work->arch.token;
8932 fault.async_page_fault = true;
8933 kvm_inject_page_fault(vcpu, &fault);
8934 }
7c90705b 8935 }
e6d53e3b 8936 vcpu->arch.apf.halted = false;
a4fa1635 8937 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8938}
8939
8940bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8941{
8942 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8943 return true;
8944 else
9bc1f09f 8945 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8946}
8947
5544eb9b
PB		 8948void kvm_arch_start_assignment(struct kvm *kvm)
8949{
8950 atomic_inc(&kvm->arch.assigned_device_count);
8951}
8952EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8953
8954void kvm_arch_end_assignment(struct kvm *kvm)
8955{
8956 atomic_dec(&kvm->arch.assigned_device_count);
8957}
8958EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8959
8960bool kvm_arch_has_assigned_device(struct kvm *kvm)
8961{
8962 return atomic_read(&kvm->arch.assigned_device_count);
8963}
8964EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8965
e0f0bbc5
AW		 8966void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8967{
8968 atomic_inc(&kvm->arch.noncoherent_dma_count);
8969}
8970EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8971
8972void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8973{
8974 atomic_dec(&kvm->arch.noncoherent_dma_count);
8975}
8976EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8977
8978bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8979{
8980 return atomic_read(&kvm->arch.noncoherent_dma_count);
8981}
8982EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8983
14717e20
AW		 8984bool kvm_arch_has_irq_bypass(void)
8985{
8986 return kvm_x86_ops->update_pi_irte != NULL;
8987}
8988
87276880
FW		 8989int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8990 struct irq_bypass_producer *prod)
8991{
8992 struct kvm_kernel_irqfd *irqfd =
8993 container_of(cons, struct kvm_kernel_irqfd, consumer);
8994
14717e20 8995 irqfd->producer = prod;
87276880 8996
14717e20
AW		 8997 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8998 prod->irq, irqfd->gsi, 1);
87276880
FW		 8999}
9000
9001void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9002 struct irq_bypass_producer *prod)
9003{
9004 int ret;
9005 struct kvm_kernel_irqfd *irqfd =
9006 container_of(cons, struct kvm_kernel_irqfd, consumer);
9007
87276880
FW		 9008 WARN_ON(irqfd->producer != prod);
9009 irqfd->producer = NULL;
9010
9011 /*
9012 * When producer of consumer is unregistered, we change back to
9013 * remapped mode, so we can re-use the current implementation
bb3541f1 9014 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9015 * int this case doesn't want to receive the interrupts.
9016 */
9017 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9018 if (ret)
9019 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9020 " fails: %d\n", irqfd->consumer.token, ret);
9021}
9022
9023int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9024 uint32_t guest_irq, bool set)
9025{
9026 if (!kvm_x86_ops->update_pi_irte)
9027 return -EINVAL;
9028
9029 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9030}
9031
52004014
FW		 9032bool kvm_vector_hashing_enabled(void)
9033{
9034 return vector_hashing;
9035}
9036EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9037
229456fc 9038EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9039EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9040EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9041EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9042EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9043EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9044EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9045EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9046EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9047EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9048EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9049EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9050EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9051EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9052EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9053EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9054EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9055EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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