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nvme: consolidate synchronous command submission helpers
[mirror_ubuntu-bionic-kernel.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b3fffdef 45#define NVME_MINORS (1U << MINORBITS)
9d43cf64 46#define NVME_Q_DEPTH 1024
d31af0a3 47#define NVME_AQ_DEPTH 256
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 51#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
bd67608a
MW		 57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
2484f407
DM		 61static unsigned char shutdown_timeout = 5;
62module_param(shutdown_timeout, byte, 0644);
63MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
64
b60503ba
MW		 65static int nvme_major;
66module_param(nvme_major, int, 0);
67
b3fffdef
KB		 68static int nvme_char_major;
69module_param(nvme_char_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
1fa6aead 79
b3fffdef
KB		 80static struct class *nvme_class;
81
d4b4ff8e 82static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 83static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 84
4d115420
KB		 85struct async_cmd_info {
86 struct kthread_work work;
87 struct kthread_worker *worker;
a4aea562 88 struct request *req;
4d115420
KB		 89 u32 result;
90 int status;
91 void *ctx;
92};
1fa6aead 93
b60503ba
MW		 94/*
95 * An NVM Express queue. Each device has at least two (one for admin
96 * commands and one for I/O commands).
97 */
98struct nvme_queue {
99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
6222d172 109 s16 cq_vector;
b60503ba
MW		 110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
ac3dd5bd 147 struct nvme_iod iod[0];
e85248e5
MW		 148};
149
ac3dd5bd
JA		 150/*
151 * Max size of iod being embedded in the request payload
152 */
153#define NVME_INT_PAGES 2
154#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 155#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 156
157/*
158 * Will slightly overestimate the number of pages needed. This is OK
159 * as it only leads to a small amount of wasted memory for the lifetime of
160 * the I/O.
161 */
162static int nvme_npages(unsigned size, struct nvme_dev *dev)
163{
164 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
165 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
166}
167
168static unsigned int nvme_cmd_size(struct nvme_dev *dev)
169{
170 unsigned int ret = sizeof(struct nvme_cmd_info);
171
172 ret += sizeof(struct nvme_iod);
173 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
174 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
175
176 return ret;
177}
178
a4aea562
MB		 179static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
180 unsigned int hctx_idx)
e85248e5 181{
a4aea562
MB		 182 struct nvme_dev *dev = data;
183 struct nvme_queue *nvmeq = dev->queues[0];
184
185 WARN_ON(nvmeq->hctx);
186 nvmeq->hctx = hctx;
187 hctx->driver_data = nvmeq;
188 return 0;
e85248e5
MW		 189}
190
a4aea562
MB		 191static int nvme_admin_init_request(void *data, struct request *req,
192 unsigned int hctx_idx, unsigned int rq_idx,
193 unsigned int numa_node)
22404274 194{
a4aea562
MB		 195 struct nvme_dev *dev = data;
196 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
197 struct nvme_queue *nvmeq = dev->queues[0];
198
199 BUG_ON(!nvmeq);
200 cmd->nvmeq = nvmeq;
201 return 0;
22404274
KB		 202}
203
2c30540b
JA		 204static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
205{
206 struct nvme_queue *nvmeq = hctx->driver_data;
207
208 nvmeq->hctx = NULL;
209}
210
a4aea562
MB		 211static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
212 unsigned int hctx_idx)
b60503ba 213{
a4aea562
MB		 214 struct nvme_dev *dev = data;
215 struct nvme_queue *nvmeq = dev->queues[
216 (hctx_idx % dev->queue_count) + 1];
b60503ba 217
a4aea562
MB		 218 if (!nvmeq->hctx)
219 nvmeq->hctx = hctx;
220
221 /* nvmeq queues are shared between namespaces. We assume here that
222 * blk-mq map the tags so they match up with the nvme queue tags. */
223 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 224
a4aea562
MB		 225 hctx->driver_data = nvmeq;
226 return 0;
b60503ba
MW		 227}
228
a4aea562
MB		 229static int nvme_init_request(void *data, struct request *req,
230 unsigned int hctx_idx, unsigned int rq_idx,
231 unsigned int numa_node)
b60503ba 232{
a4aea562
MB		 233 struct nvme_dev *dev = data;
234 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
235 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
236
237 BUG_ON(!nvmeq);
238 cmd->nvmeq = nvmeq;
239 return 0;
240}
241
242static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
243 nvme_completion_fn handler)
244{
245 cmd->fn = handler;
246 cmd->ctx = ctx;
247 cmd->aborted = 0;
c917dfe5 248 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 249}
250
ac3dd5bd
JA		 251static void *iod_get_private(struct nvme_iod *iod)
252{
253 return (void *) (iod->private & ~0x1UL);
254}
255
256/*
257 * If bit 0 is set, the iod is embedded in the request payload.
258 */
259static bool iod_should_kfree(struct nvme_iod *iod)
260{
fda631ff 261 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 262}
263
c2f5b650
MW		 264/* Special values must be less than 0x1000 */
265#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 266#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
267#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
268#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 269
edd10d33 270static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 271 struct nvme_completion *cqe)
272{
273 if (ctx == CMD_CTX_CANCELLED)
274 return;
c2f5b650 275 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 276 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 277 "completed id %d twice on queue %d\n",
278 cqe->command_id, le16_to_cpup(&cqe->sq_id));
279 return;
280 }
281 if (ctx == CMD_CTX_INVALID) {
edd10d33 282 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 283 "invalid id %d completed on queue %d\n",
284 cqe->command_id, le16_to_cpup(&cqe->sq_id));
285 return;
286 }
edd10d33 287 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 288}
289
a4aea562 290static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 291{
c2f5b650 292 void *ctx;
b60503ba 293
859361a2 294 if (fn)
a4aea562
MB		 295 *fn = cmd->fn;
296 ctx = cmd->ctx;
297 cmd->fn = special_completion;
298 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 299 return ctx;
b60503ba
MW		 300}
301
a4aea562
MB		 302static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
303 struct nvme_completion *cqe)
3c0cf138 304{
a4aea562
MB		 305 u32 result = le32_to_cpup(&cqe->result);
306 u16 status = le16_to_cpup(&cqe->status) >> 1;
307
308 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
309 ++nvmeq->dev->event_limit;
310 if (status == NVME_SC_SUCCESS)
311 dev_warn(nvmeq->q_dmadev,
312 "async event result %08x\n", result);
b60503ba
MW		 313}
314
a4aea562
MB		 315static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
316 struct nvme_completion *cqe)
5a92e700 317{
a4aea562
MB		 318 struct request *req = ctx;
319
320 u16 status = le16_to_cpup(&cqe->status) >> 1;
321 u32 result = le32_to_cpup(&cqe->result);
a51afb54 322
9d135bb8 323 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 324
a4aea562
MB		 325 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
326 ++nvmeq->dev->abort_limit;
5a92e700
KB		 327}
328
a4aea562
MB		 329static void async_completion(struct nvme_queue *nvmeq, void *ctx,
330 struct nvme_completion *cqe)
b60503ba 331{
a4aea562
MB		 332 struct async_cmd_info *cmdinfo = ctx;
333 cmdinfo->result = le32_to_cpup(&cqe->result);
334 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
335 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 336 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 337}
338
a4aea562
MB		 339static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
340 unsigned int tag)
b60503ba 341{
a4aea562
MB		 342 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
343 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 344
a4aea562 345 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 346}
347
a4aea562
MB		 348/*
349 * Called with local interrupts disabled and the q_lock held. May not sleep.
350 */
351static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
352 nvme_completion_fn *fn)
4f5099af 353{
a4aea562
MB		 354 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
355 void *ctx;
356 if (tag >= nvmeq->q_depth) {
357 *fn = special_completion;
358 return CMD_CTX_INVALID;
359 }
360 if (fn)
361 *fn = cmd->fn;
362 ctx = cmd->ctx;
363 cmd->fn = special_completion;
364 cmd->ctx = CMD_CTX_COMPLETED;
365 return ctx;
b60503ba
MW		 366}
367
368/**
714a7a22 369 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 370 * @nvmeq: The queue to use
371 * @cmd: The command to send
372 *
373 * Safe to use from interrupt context
374 */
a4aea562 375static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 376{
a4aea562
MB		 377 u16 tail = nvmeq->sq_tail;
378
b60503ba 379 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 380 if (++tail == nvmeq->q_depth)
381 tail = 0;
7547881d 382 writel(tail, nvmeq->q_db);
b60503ba 383 nvmeq->sq_tail = tail;
b60503ba
MW		 384
385 return 0;
386}
387
a4aea562
MB		 388static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
389{
390 unsigned long flags;
391 int ret;
392 spin_lock_irqsave(&nvmeq->q_lock, flags);
393 ret = __nvme_submit_cmd(nvmeq, cmd);
394 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
395 return ret;
396}
397
eca18b23 398static __le64 **iod_list(struct nvme_iod *iod)
e025344c 399{
eca18b23 400 return ((void *)iod) + iod->offset;
e025344c
SMM		 401}
402
ac3dd5bd
JA		 403static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
404 unsigned nseg, unsigned long private)
eca18b23 405{
ac3dd5bd
JA		 406 iod->private = private;
407 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
408 iod->npages = -1;
409 iod->length = nbytes;
410 iod->nents = 0;
eca18b23 411}
b60503ba 412
eca18b23 413static struct nvme_iod *
ac3dd5bd
JA		 414__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
415 unsigned long priv, gfp_t gfp)
b60503ba 416{
eca18b23 417 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 418 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 419 sizeof(struct scatterlist) * nseg, gfp);
420
ac3dd5bd
JA		 421 if (iod)
422 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 423
424 return iod;
b60503ba
MW		 425}
426
ac3dd5bd
JA		 427static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
428 gfp_t gfp)
429{
430 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
431 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 432 struct nvme_iod *iod;
433
434 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
435 size <= NVME_INT_BYTES(dev)) {
436 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
437
438 iod = cmd->iod;
ac3dd5bd 439 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 440 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 441 return iod;
442 }
443
444 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
445 (unsigned long) rq, gfp);
446}
447
5d0f6131 448void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 449{
1d090624 450 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 451 int i;
452 __le64 **list = iod_list(iod);
453 dma_addr_t prp_dma = iod->first_dma;
454
455 if (iod->npages == 0)
456 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
457 for (i = 0; i < iod->npages; i++) {
458 __le64 *prp_list = list[i];
459 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
460 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
461 prp_dma = next_prp_dma;
462 }
ac3dd5bd
JA		 463
464 if (iod_should_kfree(iod))
465 kfree(iod);
b60503ba
MW		 466}
467
b4ff9c8d
KB		 468static int nvme_error_status(u16 status)
469{
470 switch (status & 0x7ff) {
471 case NVME_SC_SUCCESS:
472 return 0;
473 case NVME_SC_CAP_EXCEEDED:
474 return -ENOSPC;
475 default:
476 return -EIO;
477 }
478}
479
52b68d7e 480#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 481static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
482{
483 if (be32_to_cpu(pi->ref_tag) == v)
484 pi->ref_tag = cpu_to_be32(p);
485}
486
487static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
488{
489 if (be32_to_cpu(pi->ref_tag) == p)
490 pi->ref_tag = cpu_to_be32(v);
491}
492
493/**
494 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
495 *
496 * The virtual start sector is the one that was originally submitted by the
497 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
498 * start sector may be different. Remap protection information to match the
499 * physical LBA on writes, and back to the original seed on reads.
500 *
501 * Type 0 and 3 do not have a ref tag, so no remapping required.
502 */
503static void nvme_dif_remap(struct request *req,
504 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
505{
506 struct nvme_ns *ns = req->rq_disk->private_data;
507 struct bio_integrity_payload *bip;
508 struct t10_pi_tuple *pi;
509 void *p, *pmap;
510 u32 i, nlb, ts, phys, virt;
511
512 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
513 return;
514
515 bip = bio_integrity(req->bio);
516 if (!bip)
517 return;
518
519 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 520
521 p = pmap;
522 virt = bip_get_seed(bip);
523 phys = nvme_block_nr(ns, blk_rq_pos(req));
524 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
525 ts = ns->disk->integrity->tuple_size;
526
527 for (i = 0; i < nlb; i++, virt++, phys++) {
528 pi = (struct t10_pi_tuple *)p;
529 dif_swap(phys, virt, pi);
530 p += ts;
531 }
532 kunmap_atomic(pmap);
533}
534
52b68d7e
KB		 535static int nvme_noop_verify(struct blk_integrity_iter *iter)
536{
537 return 0;
538}
539
540static int nvme_noop_generate(struct blk_integrity_iter *iter)
541{
542 return 0;
543}
544
545struct blk_integrity nvme_meta_noop = {
546 .name = "NVME_META_NOOP",
547 .generate_fn = nvme_noop_generate,
548 .verify_fn = nvme_noop_verify,
549};
550
551static void nvme_init_integrity(struct nvme_ns *ns)
552{
553 struct blk_integrity integrity;
554
555 switch (ns->pi_type) {
556 case NVME_NS_DPS_PI_TYPE3:
557 integrity = t10_pi_type3_crc;
558 break;
559 case NVME_NS_DPS_PI_TYPE1:
560 case NVME_NS_DPS_PI_TYPE2:
561 integrity = t10_pi_type1_crc;
562 break;
563 default:
564 integrity = nvme_meta_noop;
565 break;
566 }
567 integrity.tuple_size = ns->ms;
568 blk_integrity_register(ns->disk, &integrity);
569 blk_queue_max_integrity_segments(ns->queue, 1);
570}
571#else /* CONFIG_BLK_DEV_INTEGRITY */
572static void nvme_dif_remap(struct request *req,
573 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
574{
575}
576static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
577{
578}
579static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
580{
581}
582static void nvme_init_integrity(struct nvme_ns *ns)
583{
584}
585#endif
586
a4aea562 587static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 588 struct nvme_completion *cqe)
589{
eca18b23 590 struct nvme_iod *iod = ctx;
ac3dd5bd 591 struct request *req = iod_get_private(iod);
a4aea562
MB		 592 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
593
b60503ba
MW		 594 u16 status = le16_to_cpup(&cqe->status) >> 1;
595
edd10d33 596 if (unlikely(status)) {
a4aea562
MB		 597 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
598 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 599 unsigned long flags;
600
a4aea562 601 blk_mq_requeue_request(req);
c9d3bf88
KB		 602 spin_lock_irqsave(req->q->queue_lock, flags);
603 if (!blk_queue_stopped(req->q))
604 blk_mq_kick_requeue_list(req->q);
605 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 606 return;
607 }
a4aea562
MB		 608 req->errors = nvme_error_status(status);
609 } else
610 req->errors = 0;
611
612 if (cmd_rq->aborted)
613 dev_warn(&nvmeq->dev->pci_dev->dev,
614 "completing aborted command with status:%04x\n",
615 status);
616
e1e5e564 617 if (iod->nents) {
a4aea562
MB		 618 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
619 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 620 if (blk_integrity_rq(req)) {
621 if (!rq_data_dir(req))
622 nvme_dif_remap(req, nvme_dif_complete);
623 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
624 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
625 }
626 }
edd10d33 627 nvme_free_iod(nvmeq->dev, iod);
3291fa57 628
a4aea562 629 blk_mq_complete_request(req);
b60503ba
MW		 630}
631
184d2944 632/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 633int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
634 gfp_t gfp)
ff22b54f 635{
99802a7a 636 struct dma_pool *pool;
eca18b23
MW		 637 int length = total_len;
638 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 639 int dma_len = sg_dma_len(sg);
640 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 641 u32 page_size = dev->page_size;
642 int offset = dma_addr & (page_size - 1);
e025344c 643 __le64 *prp_list;
eca18b23 644 __le64 **list = iod_list(iod);
e025344c 645 dma_addr_t prp_dma;
eca18b23 646 int nprps, i;
ff22b54f 647
1d090624 648 length -= (page_size - offset);
ff22b54f 649 if (length <= 0)
eca18b23 650 return total_len;
ff22b54f 651
1d090624 652 dma_len -= (page_size - offset);
ff22b54f 653 if (dma_len) {
1d090624 654 dma_addr += (page_size - offset);
ff22b54f
MW		 655 } else {
656 sg = sg_next(sg);
657 dma_addr = sg_dma_address(sg);
658 dma_len = sg_dma_len(sg);
659 }
660
1d090624 661 if (length <= page_size) {
edd10d33 662 iod->first_dma = dma_addr;
eca18b23 663 return total_len;
e025344c
SMM		 664 }
665
1d090624 666 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 667 if (nprps <= (256 / 8)) {
668 pool = dev->prp_small_pool;
eca18b23 669 iod->npages = 0;
99802a7a
MW		 670 } else {
671 pool = dev->prp_page_pool;
eca18b23 672 iod->npages = 1;
99802a7a
MW		 673 }
674
b77954cb
MW		 675 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
676 if (!prp_list) {
edd10d33 677 iod->first_dma = dma_addr;
eca18b23 678 iod->npages = -1;
1d090624 679 return (total_len - length) + page_size;
b77954cb 680 }
eca18b23
MW		 681 list[0] = prp_list;
682 iod->first_dma = prp_dma;
e025344c
SMM		 683 i = 0;
684 for (;;) {
1d090624 685 if (i == page_size >> 3) {
e025344c 686 __le64 *old_prp_list = prp_list;
b77954cb 687 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 688 if (!prp_list)
689 return total_len - length;
690 list[iod->npages++] = prp_list;
7523d834
MW		 691 prp_list[0] = old_prp_list[i - 1];
692 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
693 i = 1;
e025344c
SMM		 694 }
695 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 696 dma_len -= page_size;
697 dma_addr += page_size;
698 length -= page_size;
e025344c
SMM		 699 if (length <= 0)
700 break;
701 if (dma_len > 0)
702 continue;
703 BUG_ON(dma_len < 0);
704 sg = sg_next(sg);
705 dma_addr = sg_dma_address(sg);
706 dma_len = sg_dma_len(sg);
ff22b54f
MW		 707 }
708
eca18b23 709 return total_len;
ff22b54f
MW		 710}
711
a4aea562
MB		 712/*
713 * We reuse the small pool to allocate the 16-byte range here as it is not
714 * worth having a special pool for these or additional cases to handle freeing
715 * the iod.
716 */
717static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
718 struct request *req, struct nvme_iod *iod)
0e5e4f0e 719{
edd10d33
KB		 720 struct nvme_dsm_range *range =
721 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 722 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
723
0e5e4f0e 724 range->cattr = cpu_to_le32(0);
a4aea562
MB		 725 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
726 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 727
728 memset(cmnd, 0, sizeof(*cmnd));
729 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 730 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 731 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
732 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
733 cmnd->dsm.nr = 0;
734 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
735
736 if (++nvmeq->sq_tail == nvmeq->q_depth)
737 nvmeq->sq_tail = 0;
738 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 739}
740
a4aea562 741static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 742 int cmdid)
743{
744 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
745
746 memset(cmnd, 0, sizeof(*cmnd));
747 cmnd->common.opcode = nvme_cmd_flush;
748 cmnd->common.command_id = cmdid;
749 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
750
751 if (++nvmeq->sq_tail == nvmeq->q_depth)
752 nvmeq->sq_tail = 0;
753 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 754}
755
a4aea562
MB		 756static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
757 struct nvme_ns *ns)
b60503ba 758{
ac3dd5bd 759 struct request *req = iod_get_private(iod);
ff22b54f 760 struct nvme_command *cmnd;
a4aea562
MB		 761 u16 control = 0;
762 u32 dsmgmt = 0;
00df5cb4 763
a4aea562 764 if (req->cmd_flags & REQ_FUA)
b60503ba 765 control |= NVME_RW_FUA;
a4aea562 766 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 767 control |= NVME_RW_LR;
768
a4aea562 769 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 770 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
771
ff22b54f 772 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 773 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 774
a4aea562
MB		 775 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
776 cmnd->rw.command_id = req->tag;
ff22b54f 777 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 778 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
779 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 780 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
781 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 782
783 if (blk_integrity_rq(req)) {
784 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
785 switch (ns->pi_type) {
786 case NVME_NS_DPS_PI_TYPE3:
787 control |= NVME_RW_PRINFO_PRCHK_GUARD;
788 break;
789 case NVME_NS_DPS_PI_TYPE1:
790 case NVME_NS_DPS_PI_TYPE2:
791 control |= NVME_RW_PRINFO_PRCHK_GUARD |
792 NVME_RW_PRINFO_PRCHK_REF;
793 cmnd->rw.reftag = cpu_to_le32(
794 nvme_block_nr(ns, blk_rq_pos(req)));
795 break;
796 }
797 } else if (ns->ms)
798 control |= NVME_RW_PRINFO_PRACT;
799
ff22b54f
MW		 800 cmnd->rw.control = cpu_to_le16(control);
801 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 802
b60503ba
MW		 803 if (++nvmeq->sq_tail == nvmeq->q_depth)
804 nvmeq->sq_tail = 0;
7547881d 805 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 806
1974b1ae 807 return 0;
edd10d33
KB		 808}
809
a4aea562
MB		 810static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
811 const struct blk_mq_queue_data *bd)
edd10d33 812{
a4aea562
MB		 813 struct nvme_ns *ns = hctx->queue->queuedata;
814 struct nvme_queue *nvmeq = hctx->driver_data;
815 struct request *req = bd->rq;
816 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 817 struct nvme_iod *iod;
a4aea562 818 enum dma_data_direction dma_dir;
edd10d33 819
e1e5e564
KB		 820 /*
821 * If formated with metadata, require the block layer provide a buffer
822 * unless this namespace is formated such that the metadata can be
823 * stripped/generated by the controller with PRACT=1.
824 */
825 if (ns->ms && !blk_integrity_rq(req)) {
826 if (!(ns->pi_type && ns->ms == 8)) {
827 req->errors = -EFAULT;
828 blk_mq_complete_request(req);
829 return BLK_MQ_RQ_QUEUE_OK;
830 }
831 }
832
ac3dd5bd 833 iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
edd10d33 834 if (!iod)
fe54303e 835 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 836
a4aea562 837 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 838 void *range;
839 /*
840 * We reuse the small pool to allocate the 16-byte range here
841 * as it is not worth having a special pool for these or
842 * additional cases to handle freeing the iod.
843 */
844 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
845 GFP_ATOMIC,
846 &iod->first_dma);
a4aea562 847 if (!range)
fe54303e 848 goto retry_cmd;
edd10d33
KB		 849 iod_list(iod)[0] = (__le64 *)range;
850 iod->npages = 0;
ac3dd5bd 851 } else if (req->nr_phys_segments) {
a4aea562
MB		 852 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
853
ac3dd5bd 854 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 855 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 856 if (!iod->nents)
857 goto error_cmd;
a4aea562
MB		 858
859 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 860 goto retry_cmd;
a4aea562 861
fe54303e
JA		 862 if (blk_rq_bytes(req) !=
863 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
864 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
865 iod->nents, dma_dir);
866 goto retry_cmd;
867 }
e1e5e564
KB		 868 if (blk_integrity_rq(req)) {
869 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
870 goto error_cmd;
871
872 sg_init_table(iod->meta_sg, 1);
873 if (blk_rq_map_integrity_sg(
874 req->q, req->bio, iod->meta_sg) != 1)
875 goto error_cmd;
876
877 if (rq_data_dir(req))
878 nvme_dif_remap(req, nvme_dif_prep);
879
880 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
881 goto error_cmd;
882 }
edd10d33 883 }
1974b1ae 884
9af8785a 885 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 886 spin_lock_irq(&nvmeq->q_lock);
887 if (req->cmd_flags & REQ_DISCARD)
888 nvme_submit_discard(nvmeq, ns, req, iod);
889 else if (req->cmd_flags & REQ_FLUSH)
890 nvme_submit_flush(nvmeq, ns, req->tag);
891 else
892 nvme_submit_iod(nvmeq, iod, ns);
893
894 nvme_process_cq(nvmeq);
895 spin_unlock_irq(&nvmeq->q_lock);
896 return BLK_MQ_RQ_QUEUE_OK;
897
fe54303e
JA		 898 error_cmd:
899 nvme_free_iod(nvmeq->dev, iod);
900 return BLK_MQ_RQ_QUEUE_ERROR;
901 retry_cmd:
eca18b23 902 nvme_free_iod(nvmeq->dev, iod);
fe54303e 903 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 904}
905
e9539f47 906static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 907{
82123460 908 u16 head, phase;
b60503ba 909
b60503ba 910 head = nvmeq->cq_head;
82123460 911 phase = nvmeq->cq_phase;
b60503ba
MW		 912
913 for (;;) {
c2f5b650
MW		 914 void *ctx;
915 nvme_completion_fn fn;
b60503ba 916 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 917 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 918 break;
919 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
920 if (++head == nvmeq->q_depth) {
921 head = 0;
82123460 922 phase = !phase;
b60503ba 923 }
a4aea562 924 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 925 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 926 }
927
928 /* If the controller ignores the cq head doorbell and continuously
929 * writes to the queue, it is theoretically possible to wrap around
930 * the queue twice and mistakenly return IRQ_NONE. Linux only
931 * requires that 0.1% of your interrupts are handled, so this isn't
932 * a big problem.
933 */
82123460 934 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 935 return 0;
b60503ba 936
b80d5ccc 937 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 938 nvmeq->cq_head = head;
82123460 939 nvmeq->cq_phase = phase;
b60503ba 940
e9539f47
MW		 941 nvmeq->cqe_seen = 1;
942 return 1;
b60503ba
MW		 943}
944
a4aea562
MB		 945/* Admin queue isn't initialized as a request queue. If at some point this
946 * happens anyway, make sure to notify the user */
947static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
948 const struct blk_mq_queue_data *bd)
7d822457 949{
a4aea562
MB		 950 WARN_ON_ONCE(1);
951 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 952}
953
b60503ba 954static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 955{
956 irqreturn_t result;
957 struct nvme_queue *nvmeq = data;
958 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 959 nvme_process_cq(nvmeq);
960 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
961 nvmeq->cqe_seen = 0;
58ffacb5
MW		 962 spin_unlock(&nvmeq->q_lock);
963 return result;
964}
965
966static irqreturn_t nvme_irq_check(int irq, void *data)
967{
968 struct nvme_queue *nvmeq = data;
969 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
970 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
971 return IRQ_NONE;
972 return IRQ_WAKE_THREAD;
973}
974
c2f5b650
MW		 975struct sync_cmd_info {
976 struct task_struct *task;
977 u32 result;
978 int status;
979};
980
edd10d33 981static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 982 struct nvme_completion *cqe)
983{
984 struct sync_cmd_info *cmdinfo = ctx;
985 cmdinfo->result = le32_to_cpup(&cqe->result);
986 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
987 wake_up_process(cmdinfo->task);
988}
989
b60503ba
MW		 990/*
991 * Returns 0 on success. If the result is negative, it's a Linux error code;
992 * if the result is positive, it's an NVM Express status code
993 */
f705f837
CH		 994static int __nvme_submit_sync_cmd(struct request_queue *q,
995 struct nvme_command *cmd, u32 *result, unsigned timeout)
b60503ba 996{
b60503ba 997 struct sync_cmd_info cmdinfo;
f705f837
CH		 998 struct nvme_cmd_info *cmd_rq;
999 struct request *req;
1000 int res;
1001
1002 req = blk_mq_alloc_request(q, WRITE, GFP_KERNEL, false);
1003 if (IS_ERR(req))
1004 return PTR_ERR(req);
b60503ba
MW		 1005
1006 cmdinfo.task = current;
1007 cmdinfo.status = -EINTR;
1008
a4aea562
MB		 1009 cmd->common.command_id = req->tag;
1010
f705f837 1011 cmd_rq = blk_mq_rq_to_pdu(req);
a4aea562 1012 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 1013
0c0f9b95 1014 set_current_state(TASK_UNINTERRUPTIBLE);
f705f837 1015 nvme_submit_cmd(cmd_rq->nvmeq, cmd);
0c0f9b95 1016 schedule();
3c0cf138 1017
b60503ba
MW		 1018 if (result)
1019 *result = cmdinfo.result;
f705f837
CH		 1020 res = cmdinfo.status;
1021 blk_mq_free_request(req);
1022 return res;
1023}
1024
1025int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd)
1026{
1027 return __nvme_submit_sync_cmd(q, cmd, NULL, 0);
b60503ba
MW		 1028}
1029
a4aea562
MB		 1030static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1031{
1032 struct nvme_queue *nvmeq = dev->queues[0];
1033 struct nvme_command c;
1034 struct nvme_cmd_info *cmd_info;
1035 struct request *req;
1036
1efccc9d 1037 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1038 if (IS_ERR(req))
1039 return PTR_ERR(req);
a4aea562 1040
c917dfe5 1041 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1042 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1043 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1044
1045 memset(&c, 0, sizeof(c));
1046 c.common.opcode = nvme_admin_async_event;
1047 c.common.command_id = req->tag;
1048
1efccc9d 1049 blk_mq_free_hctx_request(nvmeq->hctx, req);
a4aea562
MB		 1050 return __nvme_submit_cmd(nvmeq, &c);
1051}
1052
1053static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1054 struct nvme_command *cmd,
1055 struct async_cmd_info *cmdinfo, unsigned timeout)
1056{
a4aea562
MB		 1057 struct nvme_queue *nvmeq = dev->queues[0];
1058 struct request *req;
1059 struct nvme_cmd_info *cmd_rq;
4d115420 1060
a4aea562 1061 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1062 if (IS_ERR(req))
1063 return PTR_ERR(req);
a4aea562
MB		 1064
1065 req->timeout = timeout;
1066 cmd_rq = blk_mq_rq_to_pdu(req);
1067 cmdinfo->req = req;
1068 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1069 cmdinfo->status = -EINTR;
a4aea562
MB		 1070
1071 cmd->common.command_id = req->tag;
1072
4f5099af 1073 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1074}
1075
b60503ba
MW		 1076static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1077{
b60503ba
MW		 1078 struct nvme_command c;
1079
1080 memset(&c, 0, sizeof(c));
1081 c.delete_queue.opcode = opcode;
1082 c.delete_queue.qid = cpu_to_le16(id);
1083
f705f837 1084 return nvme_submit_sync_cmd(dev->admin_q, &c);
b60503ba
MW		 1085}
1086
1087static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1088 struct nvme_queue *nvmeq)
1089{
b60503ba
MW		 1090 struct nvme_command c;
1091 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1092
1093 memset(&c, 0, sizeof(c));
1094 c.create_cq.opcode = nvme_admin_create_cq;
1095 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1096 c.create_cq.cqid = cpu_to_le16(qid);
1097 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1098 c.create_cq.cq_flags = cpu_to_le16(flags);
1099 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1100
f705f837 1101 return nvme_submit_sync_cmd(dev->admin_q, &c);
b60503ba
MW		 1102}
1103
1104static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1105 struct nvme_queue *nvmeq)
1106{
b60503ba
MW		 1107 struct nvme_command c;
1108 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1109
1110 memset(&c, 0, sizeof(c));
1111 c.create_sq.opcode = nvme_admin_create_sq;
1112 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1113 c.create_sq.sqid = cpu_to_le16(qid);
1114 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1115 c.create_sq.sq_flags = cpu_to_le16(flags);
1116 c.create_sq.cqid = cpu_to_le16(qid);
1117
f705f837 1118 return nvme_submit_sync_cmd(dev->admin_q, &c);
b60503ba
MW		 1119}
1120
1121static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1122{
1123 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1124}
1125
1126static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1127{
1128 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1129}
1130
5d0f6131 1131int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1132 dma_addr_t dma_addr)
1133{
1134 struct nvme_command c;
1135
1136 memset(&c, 0, sizeof(c));
1137 c.identify.opcode = nvme_admin_identify;
1138 c.identify.nsid = cpu_to_le32(nsid);
1139 c.identify.prp1 = cpu_to_le64(dma_addr);
1140 c.identify.cns = cpu_to_le32(cns);
1141
f705f837 1142 return nvme_submit_sync_cmd(dev->admin_q, &c);
bc5fc7e4
MW		 1143}
1144
5d0f6131 1145int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1146 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1147{
1148 struct nvme_command c;
1149
1150 memset(&c, 0, sizeof(c));
1151 c.features.opcode = nvme_admin_get_features;
a42cecce 1152 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1153 c.features.prp1 = cpu_to_le64(dma_addr);
1154 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1155
f705f837 1156 return __nvme_submit_sync_cmd(dev->admin_q, &c, result, 0);
df348139
MW		 1157}
1158
5d0f6131
VV		 1159int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1160 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1161{
1162 struct nvme_command c;
1163
1164 memset(&c, 0, sizeof(c));
1165 c.features.opcode = nvme_admin_set_features;
1166 c.features.prp1 = cpu_to_le64(dma_addr);
1167 c.features.fid = cpu_to_le32(fid);
1168 c.features.dword11 = cpu_to_le32(dword11);
1169
f705f837 1170 return __nvme_submit_sync_cmd(dev->admin_q, &c, result, 0);
bc5fc7e4
MW		 1171}
1172
c30341dc 1173/**
a4aea562 1174 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1175 *
1176 * Schedule controller reset if the command was already aborted once before and
1177 * still hasn't been returned to the driver, or if this is the admin queue.
1178 */
a4aea562 1179static void nvme_abort_req(struct request *req)
c30341dc 1180{
a4aea562
MB		 1181 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1182 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1183 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1184 struct request *abort_req;
1185 struct nvme_cmd_info *abort_cmd;
1186 struct nvme_command cmd;
c30341dc 1187
a4aea562 1188 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1189 unsigned long flags;
1190
1191 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1192 if (work_busy(&dev->reset_work))
7a509a6b 1193 goto out;
c30341dc
KB		 1194 list_del_init(&dev->node);
1195 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1196 "I/O %d QID %d timeout, reset controller\n",
1197 req->tag, nvmeq->qid);
9ca97374 1198 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1199 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1200 out:
1201 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1202 return;
1203 }
1204
1205 if (!dev->abort_limit)
1206 return;
1207
a4aea562
MB		 1208 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1209 false);
9f173b33 1210 if (IS_ERR(abort_req))
c30341dc
KB		 1211 return;
1212
a4aea562
MB		 1213 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1214 nvme_set_info(abort_cmd, abort_req, abort_completion);
1215
c30341dc
KB		 1216 memset(&cmd, 0, sizeof(cmd));
1217 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1218 cmd.abort.cid = req->tag;
c30341dc 1219 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1220 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1221
1222 --dev->abort_limit;
a4aea562 1223 cmd_rq->aborted = 1;
c30341dc 1224
a4aea562 1225 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1226 nvmeq->qid);
a4aea562
MB		 1227 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1228 dev_warn(nvmeq->q_dmadev,
1229 "Could not abort I/O %d QID %d",
1230 req->tag, nvmeq->qid);
c87fd540 1231 blk_mq_free_request(abort_req);
a4aea562 1232 }
c30341dc
KB		 1233}
1234
a4aea562
MB		 1235static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1236 struct request *req, void *data, bool reserved)
a09115b2 1237{
a4aea562
MB		 1238 struct nvme_queue *nvmeq = data;
1239 void *ctx;
1240 nvme_completion_fn fn;
1241 struct nvme_cmd_info *cmd;
cef6a948
KB		 1242 struct nvme_completion cqe;
1243
1244 if (!blk_mq_request_started(req))
1245 return;
a09115b2 1246
a4aea562 1247 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1248
a4aea562
MB		 1249 if (cmd->ctx == CMD_CTX_CANCELLED)
1250 return;
1251
cef6a948
KB		 1252 if (blk_queue_dying(req->q))
1253 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1254 else
1255 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1256
1257
a4aea562
MB		 1258 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1259 req->tag, nvmeq->qid);
1260 ctx = cancel_cmd_info(cmd, &fn);
1261 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1262}
1263
a4aea562 1264static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1265{
a4aea562
MB		 1266 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1267 struct nvme_queue *nvmeq = cmd->nvmeq;
1268
1269 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1270 nvmeq->qid);
7a509a6b 1271 spin_lock_irq(&nvmeq->q_lock);
07836e65 1272 nvme_abort_req(req);
7a509a6b 1273 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1274
07836e65
KB		 1275 /*
1276 * The aborted req will be completed on receiving the abort req.
1277 * We enable the timer again. If hit twice, it'll cause a device reset,
1278 * as the device then is in a faulty state.
1279 */
1280 return BLK_EH_RESET_TIMER;
a4aea562 1281}
22404274 1282
a4aea562
MB		 1283static void nvme_free_queue(struct nvme_queue *nvmeq)
1284{
9e866774
MW		 1285 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1286 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1287 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1288 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1289 kfree(nvmeq);
1290}
1291
a1a5ef99 1292static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1293{
1294 int i;
1295
a1a5ef99 1296 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1297 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1298 dev->queue_count--;
a4aea562 1299 dev->queues[i] = NULL;
f435c282 1300 nvme_free_queue(nvmeq);
121c7ad4 1301 }
22404274
KB		 1302}
1303
4d115420
KB		 1304/**
1305 * nvme_suspend_queue - put queue into suspended state
1306 * @nvmeq - queue to suspend
4d115420
KB		 1307 */
1308static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1309{
2b25d981 1310 int vector;
b60503ba 1311
a09115b2 1312 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1313 if (nvmeq->cq_vector == -1) {
1314 spin_unlock_irq(&nvmeq->q_lock);
1315 return 1;
1316 }
1317 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1318 nvmeq->dev->online_queues--;
2b25d981 1319 nvmeq->cq_vector = -1;
a09115b2
MW		 1320 spin_unlock_irq(&nvmeq->q_lock);
1321
6df3dbc8
KB		 1322 if (!nvmeq->qid && nvmeq->dev->admin_q)
1323 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1324
aba2080f
MW		 1325 irq_set_affinity_hint(vector, NULL);
1326 free_irq(vector, nvmeq);
b60503ba 1327
4d115420
KB		 1328 return 0;
1329}
b60503ba 1330
4d115420
KB		 1331static void nvme_clear_queue(struct nvme_queue *nvmeq)
1332{
a4aea562
MB		 1333 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1334
22404274 1335 spin_lock_irq(&nvmeq->q_lock);
a4aea562
MB		 1336 if (hctx && hctx->tags)
1337 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1338 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1339}
1340
4d115420
KB		 1341static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1342{
a4aea562 1343 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1344
1345 if (!nvmeq)
1346 return;
1347 if (nvme_suspend_queue(nvmeq))
1348 return;
1349
0e53d180
KB		 1350 /* Don't tell the adapter to delete the admin queue.
1351 * Don't tell a removed adapter to delete IO queues. */
1352 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1353 adapter_delete_sq(dev, qid);
1354 adapter_delete_cq(dev, qid);
1355 }
07836e65
KB		 1356
1357 spin_lock_irq(&nvmeq->q_lock);
1358 nvme_process_cq(nvmeq);
1359 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1360}
1361
1362static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1363 int depth)
b60503ba
MW		 1364{
1365 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1366 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1367 if (!nvmeq)
1368 return NULL;
1369
4d51abf9
JP		 1370 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1371 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1372 if (!nvmeq->cqes)
1373 goto free_nvmeq;
b60503ba
MW		 1374
1375 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1376 &nvmeq->sq_dma_addr, GFP_KERNEL);
1377 if (!nvmeq->sq_cmds)
1378 goto free_cqdma;
1379
1380 nvmeq->q_dmadev = dmadev;
091b6092 1381 nvmeq->dev = dev;
3193f07b
MW		 1382 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1383 dev->instance, qid);
b60503ba
MW		 1384 spin_lock_init(&nvmeq->q_lock);
1385 nvmeq->cq_head = 0;
82123460 1386 nvmeq->cq_phase = 1;
b80d5ccc 1387 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1388 nvmeq->q_depth = depth;
c30341dc 1389 nvmeq->qid = qid;
22404274 1390 dev->queue_count++;
a4aea562 1391 dev->queues[qid] = nvmeq;
b60503ba
MW		 1392
1393 return nvmeq;
1394
1395 free_cqdma:
68b8eca5 1396 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1397 nvmeq->cq_dma_addr);
1398 free_nvmeq:
1399 kfree(nvmeq);
1400 return NULL;
1401}
1402
3001082c
MW		 1403static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1404 const char *name)
1405{
58ffacb5
MW		 1406 if (use_threaded_interrupts)
1407 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1408 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1409 name, nvmeq);
3001082c 1410 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1411 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1412}
1413
22404274 1414static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1415{
22404274 1416 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1417
7be50e93 1418 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1419 nvmeq->sq_tail = 0;
1420 nvmeq->cq_head = 0;
1421 nvmeq->cq_phase = 1;
b80d5ccc 1422 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1423 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1424 dev->online_queues++;
7be50e93 1425 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1426}
1427
1428static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1429{
1430 struct nvme_dev *dev = nvmeq->dev;
1431 int result;
3f85d50b 1432
2b25d981 1433 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1434 result = adapter_alloc_cq(dev, qid, nvmeq);
1435 if (result < 0)
22404274 1436 return result;
b60503ba
MW		 1437
1438 result = adapter_alloc_sq(dev, qid, nvmeq);
1439 if (result < 0)
1440 goto release_cq;
1441
3193f07b 1442 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1443 if (result < 0)
1444 goto release_sq;
1445
22404274 1446 nvme_init_queue(nvmeq, qid);
22404274 1447 return result;
b60503ba
MW		 1448
1449 release_sq:
1450 adapter_delete_sq(dev, qid);
1451 release_cq:
1452 adapter_delete_cq(dev, qid);
22404274 1453 return result;
b60503ba
MW		 1454}
1455
ba47e386
MW		 1456static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1457{
1458 unsigned long timeout;
1459 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1460
1461 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1462
1463 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1464 msleep(100);
1465 if (fatal_signal_pending(current))
1466 return -EINTR;
1467 if (time_after(jiffies, timeout)) {
1468 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1469 "Device not ready; aborting %s\n", enabled ?
1470 "initialisation" : "reset");
ba47e386
MW		 1471 return -ENODEV;
1472 }
1473 }
1474
1475 return 0;
1476}
1477
1478/*
1479 * If the device has been passed off to us in an enabled state, just clear
1480 * the enabled bit. The spec says we should set the 'shutdown notification
1481 * bits', but doing so may cause the device to complete commands to the
1482 * admin queue ... and we don't know what memory that might be pointing at!
1483 */
1484static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1485{
01079522
DM		 1486 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1487 dev->ctrl_config &= ~NVME_CC_ENABLE;
1488 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1489
ba47e386
MW		 1490 return nvme_wait_ready(dev, cap, false);
1491}
1492
1493static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1494{
01079522
DM		 1495 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1496 dev->ctrl_config |= NVME_CC_ENABLE;
1497 writel(dev->ctrl_config, &dev->bar->cc);
1498
ba47e386
MW		 1499 return nvme_wait_ready(dev, cap, true);
1500}
1501
1894d8f1
KB		 1502static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1503{
1504 unsigned long timeout;
1894d8f1 1505
01079522
DM		 1506 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1507 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1508
1509 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1510
2484f407 1511 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1512 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1513 NVME_CSTS_SHST_CMPLT) {
1514 msleep(100);
1515 if (fatal_signal_pending(current))
1516 return -EINTR;
1517 if (time_after(jiffies, timeout)) {
1518 dev_err(&dev->pci_dev->dev,
1519 "Device shutdown incomplete; abort shutdown\n");
1520 return -ENODEV;
1521 }
1522 }
1523
1524 return 0;
1525}
1526
a4aea562
MB		 1527static struct blk_mq_ops nvme_mq_admin_ops = {
1528 .queue_rq = nvme_admin_queue_rq,
1529 .map_queue = blk_mq_map_queue,
1530 .init_hctx = nvme_admin_init_hctx,
2c30540b 1531 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1532 .init_request = nvme_admin_init_request,
1533 .timeout = nvme_timeout,
1534};
1535
1536static struct blk_mq_ops nvme_mq_ops = {
1537 .queue_rq = nvme_queue_rq,
1538 .map_queue = blk_mq_map_queue,
1539 .init_hctx = nvme_init_hctx,
2c30540b 1540 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1541 .init_request = nvme_init_request,
1542 .timeout = nvme_timeout,
1543};
1544
ea191d2f
KB		 1545static void nvme_dev_remove_admin(struct nvme_dev *dev)
1546{
1547 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1548 blk_cleanup_queue(dev->admin_q);
1549 blk_mq_free_tag_set(&dev->admin_tagset);
1550 }
1551}
1552
a4aea562
MB		 1553static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1554{
1555 if (!dev->admin_q) {
1556 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1557 dev->admin_tagset.nr_hw_queues = 1;
1558 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1559 dev->admin_tagset.reserved_tags = 1;
a4aea562
MB		 1560 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1561 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
ac3dd5bd 1562 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1563 dev->admin_tagset.driver_data = dev;
1564
1565 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1566 return -ENOMEM;
1567
1568 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1569 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1570 blk_mq_free_tag_set(&dev->admin_tagset);
1571 return -ENOMEM;
1572 }
ea191d2f
KB		 1573 if (!blk_get_queue(dev->admin_q)) {
1574 nvme_dev_remove_admin(dev);
1575 return -ENODEV;
1576 }
0fb59cbc
KB		 1577 } else
1578 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1579
1580 return 0;
1581}
1582
8d85fce7 1583static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1584{
ba47e386 1585 int result;
b60503ba 1586 u32 aqa;
ba47e386 1587 u64 cap = readq(&dev->bar->cap);
b60503ba 1588 struct nvme_queue *nvmeq;
1d090624
KB		 1589 unsigned page_shift = PAGE_SHIFT;
1590 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1591 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1592
1593 if (page_shift < dev_page_min) {
1594 dev_err(&dev->pci_dev->dev,
1595 "Minimum device page size (%u) too large for "
1596 "host (%u)\n", 1 << dev_page_min,
1597 1 << page_shift);
1598 return -ENODEV;
1599 }
1600 if (page_shift > dev_page_max) {
1601 dev_info(&dev->pci_dev->dev,
1602 "Device maximum page size (%u) smaller than "
1603 "host (%u); enabling work-around\n",
1604 1 << dev_page_max, 1 << page_shift);
1605 page_shift = dev_page_max;
1606 }
b60503ba 1607
ba47e386
MW		 1608 result = nvme_disable_ctrl(dev, cap);
1609 if (result < 0)
1610 return result;
b60503ba 1611
a4aea562 1612 nvmeq = dev->queues[0];
cd638946 1613 if (!nvmeq) {
2b25d981 1614 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1615 if (!nvmeq)
1616 return -ENOMEM;
cd638946 1617 }
b60503ba
MW		 1618
1619 aqa = nvmeq->q_depth - 1;
1620 aqa |= aqa << 16;
1621
1d090624
KB		 1622 dev->page_size = 1 << page_shift;
1623
01079522 1624 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1625 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1626 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1627 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1628
1629 writel(aqa, &dev->bar->aqa);
1630 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1631 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1632
ba47e386 1633 result = nvme_enable_ctrl(dev, cap);
025c557a 1634 if (result)
a4aea562
MB		 1635 goto free_nvmeq;
1636
2b25d981 1637 nvmeq->cq_vector = 0;
3193f07b 1638 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1639 if (result)
0fb59cbc 1640 goto free_nvmeq;
025c557a 1641
b60503ba 1642 return result;
a4aea562 1643
a4aea562
MB		 1644 free_nvmeq:
1645 nvme_free_queues(dev, 0);
1646 return result;
b60503ba
MW		 1647}
1648
5d0f6131 1649struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1650 unsigned long addr, unsigned length)
b60503ba 1651{
36c14ed9 1652 int i, err, count, nents, offset;
7fc3cdab
MW		 1653 struct scatterlist *sg;
1654 struct page **pages;
eca18b23 1655 struct nvme_iod *iod;
36c14ed9
MW		 1656
1657 if (addr & 3)
eca18b23 1658 return ERR_PTR(-EINVAL);
5460fc03 1659 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1660 return ERR_PTR(-EINVAL);
7fc3cdab 1661
36c14ed9 1662 offset = offset_in_page(addr);
7fc3cdab
MW		 1663 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1664 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1665 if (!pages)
1666 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1667
1668 err = get_user_pages_fast(addr, count, 1, pages);
1669 if (err < count) {
1670 count = err;
1671 err = -EFAULT;
1672 goto put_pages;
1673 }
7fc3cdab 1674
6808c5fb 1675 err = -ENOMEM;
ac3dd5bd 1676 iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
6808c5fb
S		 1677 if (!iod)
1678 goto put_pages;
1679
eca18b23 1680 sg = iod->sg;
36c14ed9 1681 sg_init_table(sg, count);
d0ba1e49
MW		 1682 for (i = 0; i < count; i++) {
1683 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1684 min_t(unsigned, length, PAGE_SIZE - offset),
1685 offset);
d0ba1e49
MW		 1686 length -= (PAGE_SIZE - offset);
1687 offset = 0;
7fc3cdab 1688 }
fe304c43 1689 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1690 iod->nents = count;
7fc3cdab 1691
7fc3cdab
MW		 1692 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1693 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1694 if (!nents)
eca18b23 1695 goto free_iod;
b60503ba 1696
7fc3cdab 1697 kfree(pages);
eca18b23 1698 return iod;
b60503ba 1699
eca18b23
MW		 1700 free_iod:
1701 kfree(iod);
7fc3cdab
MW		 1702 put_pages:
1703 for (i = 0; i < count; i++)
1704 put_page(pages[i]);
1705 kfree(pages);
eca18b23 1706 return ERR_PTR(err);
7fc3cdab 1707}
b60503ba 1708
5d0f6131 1709void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1710 struct nvme_iod *iod)
7fc3cdab 1711{
1c2ad9fa 1712 int i;
b60503ba 1713
1c2ad9fa
MW		 1714 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1715 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1716
1c2ad9fa
MW		 1717 for (i = 0; i < iod->nents; i++)
1718 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1719}
b60503ba 1720
a53295b6
MW		 1721static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1722{
1723 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1724 struct nvme_user_io io;
1725 struct nvme_command c;
a67a9513
KB		 1726 unsigned length, meta_len, prp_len;
1727 int status, write;
1728 struct nvme_iod *iod;
1729 dma_addr_t meta_dma = 0;
1730 void *meta = NULL;
a53295b6
MW		 1731
1732 if (copy_from_user(&io, uio, sizeof(io)))
1733 return -EFAULT;
6c7d4945 1734 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1735 meta_len = (io.nblocks + 1) * ns->ms;
1736
a67a9513 1737 if (meta_len && ((io.metadata & 3) || !io.metadata) && !ns->ext)
f410c680 1738 return -EINVAL;
a67a9513
KB		 1739 else if (meta_len && ns->ext) {
1740 length += meta_len;
1741 meta_len = 0;
1742 }
1743
1744 write = io.opcode & 1;
6c7d4945
MW		 1745
1746 switch (io.opcode) {
1747 case nvme_cmd_write:
1748 case nvme_cmd_read:
6bbf1acd 1749 case nvme_cmd_compare:
a67a9513 1750 iod = nvme_map_user_pages(dev, write, io.addr, length);
6413214c 1751 break;
6c7d4945 1752 default:
6bbf1acd 1753 return -EINVAL;
6c7d4945
MW		 1754 }
1755
eca18b23
MW		 1756 if (IS_ERR(iod))
1757 return PTR_ERR(iod);
a53295b6 1758
a67a9513
KB		 1759 prp_len = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1760 if (length != prp_len) {
1761 status = -ENOMEM;
1762 goto unmap;
1763 }
1764 if (meta_len) {
1765 meta = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1766 &meta_dma, GFP_KERNEL);
1767 if (!meta) {
1768 status = -ENOMEM;
1769 goto unmap;
1770 }
1771 if (write) {
1772 if (copy_from_user(meta, (void __user *)io.metadata,
1773 meta_len)) {
1774 status = -EFAULT;
1775 goto unmap;
1776 }
1777 }
1778 }
1779
a53295b6
MW		 1780 memset(&c, 0, sizeof(c));
1781 c.rw.opcode = io.opcode;
1782 c.rw.flags = io.flags;
6c7d4945 1783 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1784 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1785 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1786 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1787 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1788 c.rw.reftag = cpu_to_le32(io.reftag);
1789 c.rw.apptag = cpu_to_le16(io.apptag);
1790 c.rw.appmask = cpu_to_le16(io.appmask);
edd10d33
KB		 1791 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1792 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a67a9513 1793 c.rw.metadata = cpu_to_le64(meta_dma);
f705f837 1794 status = nvme_submit_sync_cmd(ns->queue, &c);
f410c680 1795 unmap:
a67a9513 1796 nvme_unmap_user_pages(dev, write, iod);
eca18b23 1797 nvme_free_iod(dev, iod);
a67a9513
KB		 1798 if (meta) {
1799 if (status == NVME_SC_SUCCESS && !write) {
1800 if (copy_to_user((void __user *)io.metadata, meta,
1801 meta_len))
1802 status = -EFAULT;
1803 }
1804 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta, meta_dma);
f410c680 1805 }
a53295b6
MW		 1806 return status;
1807}
1808
a4aea562
MB		 1809static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1810 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1811{
7963e521 1812 struct nvme_passthru_cmd cmd;
6ee44cdc 1813 struct nvme_command c;
eca18b23 1814 int status, length;
c7d36ab8 1815 struct nvme_iod *uninitialized_var(iod);
94f370ca 1816 unsigned timeout;
6ee44cdc 1817
6bbf1acd
MW		 1818 if (!capable(CAP_SYS_ADMIN))
1819 return -EACCES;
1820 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1821 return -EFAULT;
6ee44cdc
MW		 1822
1823 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1824 c.common.opcode = cmd.opcode;
1825 c.common.flags = cmd.flags;
1826 c.common.nsid = cpu_to_le32(cmd.nsid);
1827 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1828 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1829 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1830 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1831 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1832 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1833 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1834 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1835
1836 length = cmd.data_len;
1837 if (cmd.data_len) {
49742188
MW		 1838 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1839 length);
eca18b23
MW		 1840 if (IS_ERR(iod))
1841 return PTR_ERR(iod);
edd10d33
KB		 1842 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1843 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1844 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1845 }
1846
94f370ca
KB		 1847 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1848 ADMIN_TIMEOUT;
a4aea562 1849
f705f837 1850 if (length != cmd.data_len) {
b77954cb 1851 status = -ENOMEM;
f705f837
CH		 1852 goto out;
1853 }
1854
1855 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1856 &cmd.result, timeout);
eca18b23 1857
f705f837 1858out:
6bbf1acd 1859 if (cmd.data_len) {
1c2ad9fa 1860 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1861 nvme_free_iod(dev, iod);
6bbf1acd 1862 }
f4f117f6 1863
cf90bc48 1864 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1865 sizeof(cmd.result)))
1866 status = -EFAULT;
1867
6ee44cdc
MW		 1868 return status;
1869}
1870
b60503ba
MW		 1871static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1872 unsigned long arg)
1873{
1874 struct nvme_ns *ns = bdev->bd_disk->private_data;
1875
1876 switch (cmd) {
6bbf1acd 1877 case NVME_IOCTL_ID:
c3bfe717 1878 force_successful_syscall_return();
6bbf1acd
MW		 1879 return ns->ns_id;
1880 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1881 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1882 case NVME_IOCTL_IO_CMD:
a4aea562 1883 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1884 case NVME_IOCTL_SUBMIT_IO:
1885 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1886 case SG_GET_VERSION_NUM:
1887 return nvme_sg_get_version_num((void __user *)arg);
1888 case SG_IO:
1889 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1890 default:
1891 return -ENOTTY;
1892 }
1893}
1894
320a3827
KB		 1895#ifdef CONFIG_COMPAT
1896static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1897 unsigned int cmd, unsigned long arg)
1898{
320a3827
KB		 1899 switch (cmd) {
1900 case SG_IO:
e179729a 1901 return -ENOIOCTLCMD;
320a3827
KB		 1902 }
1903 return nvme_ioctl(bdev, mode, cmd, arg);
1904}
1905#else
1906#define nvme_compat_ioctl NULL
1907#endif
1908
9ac27090
KB		 1909static int nvme_open(struct block_device *bdev, fmode_t mode)
1910{
9e60352c
KB		 1911 int ret = 0;
1912 struct nvme_ns *ns;
9ac27090 1913
9e60352c
KB		 1914 spin_lock(&dev_list_lock);
1915 ns = bdev->bd_disk->private_data;
1916 if (!ns)
1917 ret = -ENXIO;
1918 else if (!kref_get_unless_zero(&ns->dev->kref))
1919 ret = -ENXIO;
1920 spin_unlock(&dev_list_lock);
1921
1922 return ret;
9ac27090
KB		 1923}
1924
1925static void nvme_free_dev(struct kref *kref);
1926
1927static void nvme_release(struct gendisk *disk, fmode_t mode)
1928{
1929 struct nvme_ns *ns = disk->private_data;
1930 struct nvme_dev *dev = ns->dev;
1931
1932 kref_put(&dev->kref, nvme_free_dev);
1933}
1934
4cc09e2d
KB		 1935static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1936{
1937 /* some standard values */
1938 geo->heads = 1 << 6;
1939 geo->sectors = 1 << 5;
1940 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1941 return 0;
1942}
1943
e1e5e564
KB		 1944static void nvme_config_discard(struct nvme_ns *ns)
1945{
1946 u32 logical_block_size = queue_logical_block_size(ns->queue);
1947 ns->queue->limits.discard_zeroes_data = 0;
1948 ns->queue->limits.discard_alignment = logical_block_size;
1949 ns->queue->limits.discard_granularity = logical_block_size;
1950 ns->queue->limits.max_discard_sectors = 0xffffffff;
1951 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1952}
1953
1b9dbf7f
KB		 1954static int nvme_revalidate_disk(struct gendisk *disk)
1955{
1956 struct nvme_ns *ns = disk->private_data;
1957 struct nvme_dev *dev = ns->dev;
1958 struct nvme_id_ns *id;
1959 dma_addr_t dma_addr;
a67a9513
KB		 1960 u8 lbaf, pi_type;
1961 u16 old_ms;
e1e5e564 1962 unsigned short bs;
1b9dbf7f
KB		 1963
1964 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1965 GFP_KERNEL);
1966 if (!id) {
1967 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1968 __func__);
1969 return 0;
1970 }
e1e5e564
KB		 1971 if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
1972 dev_warn(&dev->pci_dev->dev,
1973 "identify failed ns:%d, setting capacity to 0\n",
1974 ns->ns_id);
1975 memset(id, 0, sizeof(*id));
1976 }
1b9dbf7f 1977
e1e5e564
KB		 1978 old_ms = ns->ms;
1979 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 1980 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 1981 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 1982 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 1983
1984 /*
1985 * If identify namespace failed, use default 512 byte block size so
1986 * block layer can use before failing read/write for 0 capacity.
1987 */
1988 if (ns->lba_shift == 0)
1989 ns->lba_shift = 9;
1990 bs = 1 << ns->lba_shift;
1991
1992 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1993 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1994 id->dps & NVME_NS_DPS_PI_MASK : 0;
1995
52b68d7e
KB		 1996 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1997 ns->ms != old_ms ||
e1e5e564 1998 bs != queue_logical_block_size(disk->queue) ||
a67a9513 1999 (ns->ms && ns->ext)))
e1e5e564
KB		 2000 blk_integrity_unregister(disk);
2001
2002 ns->pi_type = pi_type;
2003 blk_queue_logical_block_size(ns->queue, bs);
2004
52b68d7e 2005 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 2006 !ns->ext)
e1e5e564
KB		 2007 nvme_init_integrity(ns);
2008
52b68d7e 2009 if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
e1e5e564
KB		 2010 set_capacity(disk, 0);
2011 else
2012 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2013
2014 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2015 nvme_config_discard(ns);
1b9dbf7f 2016
1b9dbf7f
KB		 2017 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2018 return 0;
2019}
2020
b60503ba
MW		 2021static const struct block_device_operations nvme_fops = {
2022 .owner = THIS_MODULE,
2023 .ioctl = nvme_ioctl,
320a3827 2024 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2025 .open = nvme_open,
2026 .release = nvme_release,
4cc09e2d 2027 .getgeo = nvme_getgeo,
1b9dbf7f 2028 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2029};
2030
1fa6aead
MW		 2031static int nvme_kthread(void *data)
2032{
d4b4ff8e 2033 struct nvme_dev *dev, *next;
1fa6aead
MW		 2034
2035 while (!kthread_should_stop()) {
564a232c 2036 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2037 spin_lock(&dev_list_lock);
d4b4ff8e 2038 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2039 int i;
07836e65 2040 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 2041 if (work_busy(&dev->reset_work))
2042 continue;
2043 list_del_init(&dev->node);
2044 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 2045 "Failed status: %x, reset controller\n",
2046 readl(&dev->bar->csts));
9ca97374 2047 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2048 queue_work(nvme_workq, &dev->reset_work);
2049 continue;
2050 }
1fa6aead 2051 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2052 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2053 if (!nvmeq)
2054 continue;
1fa6aead 2055 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2056 nvme_process_cq(nvmeq);
6fccf938
KB		 2057
2058 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2059 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2060 break;
2061 dev->event_limit--;
2062 }
1fa6aead
MW		 2063 spin_unlock_irq(&nvmeq->q_lock);
2064 }
2065 }
2066 spin_unlock(&dev_list_lock);
acb7aa0d 2067 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2068 }
2069 return 0;
2070}
2071
e1e5e564 2072static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2073{
2074 struct nvme_ns *ns;
2075 struct gendisk *disk;
a4aea562 2076 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba 2077
a4aea562 2078 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2079 if (!ns)
e1e5e564
KB		 2080 return;
2081
a4aea562 2082 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2083 if (IS_ERR(ns->queue))
b60503ba 2084 goto out_free_ns;
4eeb9215
MW		 2085 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2086 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2087 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2088 ns->dev = dev;
2089 ns->queue->queuedata = ns;
2090
a4aea562 2091 disk = alloc_disk_node(0, node);
b60503ba
MW		 2092 if (!disk)
2093 goto out_free_queue;
a4aea562 2094
5aff9382 2095 ns->ns_id = nsid;
b60503ba 2096 ns->disk = disk;
e1e5e564
KB		 2097 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2098 list_add_tail(&ns->list, &dev->namespaces);
2099
e9ef4636 2100 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2101 if (dev->max_hw_sectors)
2102 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2103 if (dev->stripe_size)
2104 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2105 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2106 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2107
2108 disk->major = nvme_major;
469071a3 2109 disk->first_minor = 0;
b60503ba
MW		 2110 disk->fops = &nvme_fops;
2111 disk->private_data = ns;
2112 disk->queue = ns->queue;
b3fffdef 2113 disk->driverfs_dev = dev->device;
469071a3 2114 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2115 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2116
e1e5e564
KB		 2117 /*
2118 * Initialize capacity to 0 until we establish the namespace format and
2119 * setup integrity extentions if necessary. The revalidate_disk after
2120 * add_disk allows the driver to register with integrity if the format
2121 * requires it.
2122 */
2123 set_capacity(disk, 0);
2124 nvme_revalidate_disk(ns->disk);
2125 add_disk(ns->disk);
2126 if (ns->ms)
2127 revalidate_disk(ns->disk);
2128 return;
b60503ba
MW		 2129 out_free_queue:
2130 blk_cleanup_queue(ns->queue);
2131 out_free_ns:
2132 kfree(ns);
b60503ba
MW		 2133}
2134
42f61420
KB		 2135static void nvme_create_io_queues(struct nvme_dev *dev)
2136{
a4aea562 2137 unsigned i;
42f61420 2138
a4aea562 2139 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2140 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2141 break;
2142
a4aea562
MB		 2143 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2144 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2145 break;
2146}
2147
b3b06812 2148static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2149{
2150 int status;
2151 u32 result;
b3b06812 2152 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2153
df348139 2154 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2155 &result);
27e8166c
MW		 2156 if (status < 0)
2157 return status;
2158 if (status > 0) {
2159 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2160 status);
badc34d4 2161 return 0;
27e8166c 2162 }
b60503ba
MW		 2163 return min(result & 0xffff, result >> 16) + 1;
2164}
2165
9d713c2b
KB		 2166static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2167{
b80d5ccc 2168 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2169}
2170
8d85fce7 2171static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2172{
a4aea562 2173 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2174 struct pci_dev *pdev = dev->pci_dev;
42f61420 2175 int result, i, vecs, nr_io_queues, size;
b60503ba 2176
42f61420 2177 nr_io_queues = num_possible_cpus();
b348b7d5 2178 result = set_queue_count(dev, nr_io_queues);
badc34d4 2179 if (result <= 0)
1b23484b 2180 return result;
b348b7d5
MW		 2181 if (result < nr_io_queues)
2182 nr_io_queues = result;
b60503ba 2183
9d713c2b
KB		 2184 size = db_bar_size(dev, nr_io_queues);
2185 if (size > 8192) {
f1938f6e 2186 iounmap(dev->bar);
9d713c2b
KB		 2187 do {
2188 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2189 if (dev->bar)
2190 break;
2191 if (!--nr_io_queues)
2192 return -ENOMEM;
2193 size = db_bar_size(dev, nr_io_queues);
2194 } while (1);
f1938f6e 2195 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2196 adminq->q_db = dev->dbs;
f1938f6e
MW		 2197 }
2198
9d713c2b 2199 /* Deregister the admin queue's interrupt */
3193f07b 2200 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2201
e32efbfc
JA		 2202 /*
2203 * If we enable msix early due to not intx, disable it again before
2204 * setting up the full range we need.
2205 */
2206 if (!pdev->irq)
2207 pci_disable_msix(pdev);
2208
be577fab 2209 for (i = 0; i < nr_io_queues; i++)
1b23484b 2210 dev->entry[i].entry = i;
be577fab
AG		 2211 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2212 if (vecs < 0) {
2213 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2214 if (vecs < 0) {
2215 vecs = 1;
2216 } else {
2217 for (i = 0; i < vecs; i++)
2218 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2219 }
2220 }
2221
063a8096
MW		 2222 /*
2223 * Should investigate if there's a performance win from allocating
2224 * more queues than interrupt vectors; it might allow the submission
2225 * path to scale better, even if the receive path is limited by the
2226 * number of interrupts.
2227 */
2228 nr_io_queues = vecs;
42f61420 2229 dev->max_qid = nr_io_queues;
063a8096 2230
3193f07b 2231 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2232 if (result)
22404274 2233 goto free_queues;
1b23484b 2234
cd638946 2235 /* Free previously allocated queues that are no longer usable */
42f61420 2236 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2237 nvme_create_io_queues(dev);
9ecdc946 2238
22404274 2239 return 0;
b60503ba 2240
22404274 2241 free_queues:
a1a5ef99 2242 nvme_free_queues(dev, 1);
22404274 2243 return result;
b60503ba
MW		 2244}
2245
422ef0c7
MW		 2246/*
2247 * Return: error value if an error occurred setting up the queues or calling
2248 * Identify Device. 0 if these succeeded, even if adding some of the
2249 * namespaces failed. At the moment, these failures are silent. TBD which
2250 * failures should be reported.
2251 */
8d85fce7 2252static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2253{
68608c26 2254 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2255 int res;
2256 unsigned nn, i;
51814232 2257 struct nvme_id_ctrl *ctrl;
bc5fc7e4 2258 void *mem;
b60503ba 2259 dma_addr_t dma_addr;
159b67d7 2260 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2261
e1e5e564 2262 mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2263 if (!mem)
2264 return -ENOMEM;
b60503ba 2265
bc5fc7e4 2266 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2267 if (res) {
27e8166c 2268 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564
KB		 2269 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2270 return -EIO;
b60503ba
MW		 2271 }
2272
bc5fc7e4 2273 ctrl = mem;
51814232 2274 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2275 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2276 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2277 dev->vwc = ctrl->vwc;
51814232
MW		 2278 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2279 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2280 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2281 if (ctrl->mdts)
8fc23e03 2282 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2283 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2284 (pdev->device == 0x0953) && ctrl->vs[3]) {
2285 unsigned int max_hw_sectors;
2286
159b67d7 2287 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2288 max_hw_sectors = dev->stripe_size >> (shift - 9);
2289 if (dev->max_hw_sectors) {
2290 dev->max_hw_sectors = min(max_hw_sectors,
2291 dev->max_hw_sectors);
2292 } else
2293 dev->max_hw_sectors = max_hw_sectors;
2294 }
e1e5e564 2295 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
a4aea562
MB		 2296
2297 dev->tagset.ops = &nvme_mq_ops;
2298 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2299 dev->tagset.timeout = NVME_IO_TIMEOUT;
2300 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2301 dev->tagset.queue_depth =
2302 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2303 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2304 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2305 dev->tagset.driver_data = dev;
2306
2307 if (blk_mq_alloc_tag_set(&dev->tagset))
e1e5e564 2308 return 0;
b60503ba 2309
e1e5e564
KB		 2310 for (i = 1; i <= nn; i++)
2311 nvme_alloc_ns(dev, i);
b60503ba 2312
e1e5e564 2313 return 0;
b60503ba
MW		 2314}
2315
0877cb0d
KB		 2316static int nvme_dev_map(struct nvme_dev *dev)
2317{
42f61420 2318 u64 cap;
0877cb0d
KB		 2319 int bars, result = -ENOMEM;
2320 struct pci_dev *pdev = dev->pci_dev;
2321
2322 if (pci_enable_device_mem(pdev))
2323 return result;
2324
2325 dev->entry[0].vector = pdev->irq;
2326 pci_set_master(pdev);
2327 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2328 if (!bars)
2329 goto disable_pci;
2330
0877cb0d
KB		 2331 if (pci_request_selected_regions(pdev, bars, "nvme"))
2332 goto disable_pci;
2333
052d0efa
RK		 2334 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2335 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2336 goto disable;
0877cb0d 2337
0877cb0d
KB		 2338 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2339 if (!dev->bar)
2340 goto disable;
e32efbfc 2341
0e53d180
KB		 2342 if (readl(&dev->bar->csts) == -1) {
2343 result = -ENODEV;
2344 goto unmap;
2345 }
e32efbfc
JA		 2346
2347 /*
2348 * Some devices don't advertse INTx interrupts, pre-enable a single
2349 * MSIX vec for setup. We'll adjust this later.
2350 */
2351 if (!pdev->irq) {
2352 result = pci_enable_msix(pdev, dev->entry, 1);
2353 if (result < 0)
2354 goto unmap;
2355 }
2356
42f61420
KB		 2357 cap = readq(&dev->bar->cap);
2358 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2359 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2360 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2361
2362 return 0;
2363
0e53d180
KB		 2364 unmap:
2365 iounmap(dev->bar);
2366 dev->bar = NULL;
0877cb0d
KB		 2367 disable:
2368 pci_release_regions(pdev);
2369 disable_pci:
2370 pci_disable_device(pdev);
2371 return result;
2372}
2373
2374static void nvme_dev_unmap(struct nvme_dev *dev)
2375{
2376 if (dev->pci_dev->msi_enabled)
2377 pci_disable_msi(dev->pci_dev);
2378 else if (dev->pci_dev->msix_enabled)
2379 pci_disable_msix(dev->pci_dev);
2380
2381 if (dev->bar) {
2382 iounmap(dev->bar);
2383 dev->bar = NULL;
9a6b9458 2384 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2385 }
2386
0877cb0d
KB		 2387 if (pci_is_enabled(dev->pci_dev))
2388 pci_disable_device(dev->pci_dev);
2389}
2390
4d115420
KB		 2391struct nvme_delq_ctx {
2392 struct task_struct *waiter;
2393 struct kthread_worker *worker;
2394 atomic_t refcount;
2395};
2396
2397static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2398{
2399 dq->waiter = current;
2400 mb();
2401
2402 for (;;) {
2403 set_current_state(TASK_KILLABLE);
2404 if (!atomic_read(&dq->refcount))
2405 break;
2406 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2407 fatal_signal_pending(current)) {
0fb59cbc
KB		 2408 /*
2409 * Disable the controller first since we can't trust it
2410 * at this point, but leave the admin queue enabled
2411 * until all queue deletion requests are flushed.
2412 * FIXME: This may take a while if there are more h/w
2413 * queues than admin tags.
2414 */
4d115420 2415 set_current_state(TASK_RUNNING);
4d115420 2416 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2417 nvme_clear_queue(dev->queues[0]);
4d115420 2418 flush_kthread_worker(dq->worker);
0fb59cbc 2419 nvme_disable_queue(dev, 0);
4d115420
KB		 2420 return;
2421 }
2422 }
2423 set_current_state(TASK_RUNNING);
2424}
2425
2426static void nvme_put_dq(struct nvme_delq_ctx *dq)
2427{
2428 atomic_dec(&dq->refcount);
2429 if (dq->waiter)
2430 wake_up_process(dq->waiter);
2431}
2432
2433static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2434{
2435 atomic_inc(&dq->refcount);
2436 return dq;
2437}
2438
2439static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2440{
2441 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2442 nvme_put_dq(dq);
2443}
2444
2445static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2446 kthread_work_func_t fn)
2447{
2448 struct nvme_command c;
2449
2450 memset(&c, 0, sizeof(c));
2451 c.delete_queue.opcode = opcode;
2452 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2453
2454 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2455 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2456 ADMIN_TIMEOUT);
4d115420
KB		 2457}
2458
2459static void nvme_del_cq_work_handler(struct kthread_work *work)
2460{
2461 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2462 cmdinfo.work);
2463 nvme_del_queue_end(nvmeq);
2464}
2465
2466static int nvme_delete_cq(struct nvme_queue *nvmeq)
2467{
2468 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2469 nvme_del_cq_work_handler);
2470}
2471
2472static void nvme_del_sq_work_handler(struct kthread_work *work)
2473{
2474 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2475 cmdinfo.work);
2476 int status = nvmeq->cmdinfo.status;
2477
2478 if (!status)
2479 status = nvme_delete_cq(nvmeq);
2480 if (status)
2481 nvme_del_queue_end(nvmeq);
2482}
2483
2484static int nvme_delete_sq(struct nvme_queue *nvmeq)
2485{
2486 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2487 nvme_del_sq_work_handler);
2488}
2489
2490static void nvme_del_queue_start(struct kthread_work *work)
2491{
2492 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2493 cmdinfo.work);
4d115420
KB		 2494 if (nvme_delete_sq(nvmeq))
2495 nvme_del_queue_end(nvmeq);
2496}
2497
2498static void nvme_disable_io_queues(struct nvme_dev *dev)
2499{
2500 int i;
2501 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2502 struct nvme_delq_ctx dq;
2503 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2504 &worker, "nvme%d", dev->instance);
2505
2506 if (IS_ERR(kworker_task)) {
2507 dev_err(&dev->pci_dev->dev,
2508 "Failed to create queue del task\n");
2509 for (i = dev->queue_count - 1; i > 0; i--)
2510 nvme_disable_queue(dev, i);
2511 return;
2512 }
2513
2514 dq.waiter = NULL;
2515 atomic_set(&dq.refcount, 0);
2516 dq.worker = &worker;
2517 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2518 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2519
2520 if (nvme_suspend_queue(nvmeq))
2521 continue;
2522 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2523 nvmeq->cmdinfo.worker = dq.worker;
2524 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2525 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2526 }
2527 nvme_wait_dq(&dq, dev);
2528 kthread_stop(kworker_task);
2529}
2530
b9afca3e
DM		 2531/*
2532* Remove the node from the device list and check
2533* for whether or not we need to stop the nvme_thread.
2534*/
2535static void nvme_dev_list_remove(struct nvme_dev *dev)
2536{
2537 struct task_struct *tmp = NULL;
2538
2539 spin_lock(&dev_list_lock);
2540 list_del_init(&dev->node);
2541 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2542 tmp = nvme_thread;
2543 nvme_thread = NULL;
2544 }
2545 spin_unlock(&dev_list_lock);
2546
2547 if (tmp)
2548 kthread_stop(tmp);
2549}
2550
c9d3bf88
KB		 2551static void nvme_freeze_queues(struct nvme_dev *dev)
2552{
2553 struct nvme_ns *ns;
2554
2555 list_for_each_entry(ns, &dev->namespaces, list) {
2556 blk_mq_freeze_queue_start(ns->queue);
2557
cddcd72b 2558 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2559 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2560 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2561
2562 blk_mq_cancel_requeue_work(ns->queue);
2563 blk_mq_stop_hw_queues(ns->queue);
2564 }
2565}
2566
2567static void nvme_unfreeze_queues(struct nvme_dev *dev)
2568{
2569 struct nvme_ns *ns;
2570
2571 list_for_each_entry(ns, &dev->namespaces, list) {
2572 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2573 blk_mq_unfreeze_queue(ns->queue);
2574 blk_mq_start_stopped_hw_queues(ns->queue, true);
2575 blk_mq_kick_requeue_list(ns->queue);
2576 }
2577}
2578
f0b50732 2579static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2580{
22404274 2581 int i;
7c1b2450 2582 u32 csts = -1;
22404274 2583
b9afca3e 2584 nvme_dev_list_remove(dev);
1fa6aead 2585
c9d3bf88
KB		 2586 if (dev->bar) {
2587 nvme_freeze_queues(dev);
7c1b2450 2588 csts = readl(&dev->bar->csts);
c9d3bf88 2589 }
7c1b2450 2590 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2591 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2592 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2593 nvme_suspend_queue(nvmeq);
4d115420
KB		 2594 }
2595 } else {
2596 nvme_disable_io_queues(dev);
1894d8f1 2597 nvme_shutdown_ctrl(dev);
4d115420
KB		 2598 nvme_disable_queue(dev, 0);
2599 }
f0b50732 2600 nvme_dev_unmap(dev);
07836e65
KB		 2601
2602 for (i = dev->queue_count - 1; i >= 0; i--)
2603 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2604}
2605
2606static void nvme_dev_remove(struct nvme_dev *dev)
2607{
9ac27090 2608 struct nvme_ns *ns;
f0b50732 2609
9ac27090 2610 list_for_each_entry(ns, &dev->namespaces, list) {
e1e5e564 2611 if (ns->disk->flags & GENHD_FL_UP) {
52b68d7e 2612 if (blk_get_integrity(ns->disk))
e1e5e564 2613 blk_integrity_unregister(ns->disk);
9ac27090 2614 del_gendisk(ns->disk);
e1e5e564 2615 }
cef6a948
KB		 2616 if (!blk_queue_dying(ns->queue)) {
2617 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2618 blk_cleanup_queue(ns->queue);
cef6a948 2619 }
b60503ba 2620 }
b60503ba
MW		 2621}
2622
091b6092
MW		 2623static int nvme_setup_prp_pools(struct nvme_dev *dev)
2624{
2625 struct device *dmadev = &dev->pci_dev->dev;
2626 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2627 PAGE_SIZE, PAGE_SIZE, 0);
2628 if (!dev->prp_page_pool)
2629 return -ENOMEM;
2630
99802a7a
MW		 2631 /* Optimisation for I/Os between 4k and 128k */
2632 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2633 256, 256, 0);
2634 if (!dev->prp_small_pool) {
2635 dma_pool_destroy(dev->prp_page_pool);
2636 return -ENOMEM;
2637 }
091b6092
MW		 2638 return 0;
2639}
2640
2641static void nvme_release_prp_pools(struct nvme_dev *dev)
2642{
2643 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2644 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2645}
2646
cd58ad7d
QSA		 2647static DEFINE_IDA(nvme_instance_ida);
2648
2649static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2650{
cd58ad7d
QSA		 2651 int instance, error;
2652
2653 do {
2654 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2655 return -ENODEV;
2656
2657 spin_lock(&dev_list_lock);
2658 error = ida_get_new(&nvme_instance_ida, &instance);
2659 spin_unlock(&dev_list_lock);
2660 } while (error == -EAGAIN);
2661
2662 if (error)
2663 return -ENODEV;
2664
2665 dev->instance = instance;
2666 return 0;
b60503ba
MW		 2667}
2668
2669static void nvme_release_instance(struct nvme_dev *dev)
2670{
cd58ad7d
QSA		 2671 spin_lock(&dev_list_lock);
2672 ida_remove(&nvme_instance_ida, dev->instance);
2673 spin_unlock(&dev_list_lock);
b60503ba
MW		 2674}
2675
9ac27090
KB		 2676static void nvme_free_namespaces(struct nvme_dev *dev)
2677{
2678 struct nvme_ns *ns, *next;
2679
2680 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2681 list_del(&ns->list);
9e60352c
KB		 2682
2683 spin_lock(&dev_list_lock);
2684 ns->disk->private_data = NULL;
2685 spin_unlock(&dev_list_lock);
2686
9ac27090
KB		 2687 put_disk(ns->disk);
2688 kfree(ns);
2689 }
2690}
2691
5e82e952
KB		 2692static void nvme_free_dev(struct kref *kref)
2693{
2694 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2695
a96d4f5c 2696 pci_dev_put(dev->pci_dev);
b3fffdef 2697 put_device(dev->device);
9ac27090 2698 nvme_free_namespaces(dev);
285dffc9 2699 nvme_release_instance(dev);
a4aea562 2700 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2701 blk_put_queue(dev->admin_q);
5e82e952
KB		 2702 kfree(dev->queues);
2703 kfree(dev->entry);
2704 kfree(dev);
2705}
2706
2707static int nvme_dev_open(struct inode *inode, struct file *f)
2708{
b3fffdef
KB		 2709 struct nvme_dev *dev;
2710 int instance = iminor(inode);
2711 int ret = -ENODEV;
2712
2713 spin_lock(&dev_list_lock);
2714 list_for_each_entry(dev, &dev_list, node) {
2715 if (dev->instance == instance) {
2e1d8448
KB		 2716 if (!dev->admin_q) {
2717 ret = -EWOULDBLOCK;
2718 break;
2719 }
b3fffdef
KB		 2720 if (!kref_get_unless_zero(&dev->kref))
2721 break;
2722 f->private_data = dev;
2723 ret = 0;
2724 break;
2725 }
2726 }
2727 spin_unlock(&dev_list_lock);
2728
2729 return ret;
5e82e952
KB		 2730}
2731
2732static int nvme_dev_release(struct inode *inode, struct file *f)
2733{
2734 struct nvme_dev *dev = f->private_data;
2735 kref_put(&dev->kref, nvme_free_dev);
2736 return 0;
2737}
2738
2739static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2740{
2741 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2742 struct nvme_ns *ns;
2743
5e82e952
KB		 2744 switch (cmd) {
2745 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2746 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2747 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2748 if (list_empty(&dev->namespaces))
2749 return -ENOTTY;
2750 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2751 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2752 default:
2753 return -ENOTTY;
2754 }
2755}
2756
2757static const struct file_operations nvme_dev_fops = {
2758 .owner = THIS_MODULE,
2759 .open = nvme_dev_open,
2760 .release = nvme_dev_release,
2761 .unlocked_ioctl = nvme_dev_ioctl,
2762 .compat_ioctl = nvme_dev_ioctl,
2763};
2764
a4aea562
MB		 2765static void nvme_set_irq_hints(struct nvme_dev *dev)
2766{
2767 struct nvme_queue *nvmeq;
2768 int i;
2769
2770 for (i = 0; i < dev->online_queues; i++) {
2771 nvmeq = dev->queues[i];
2772
2773 if (!nvmeq->hctx)
2774 continue;
2775
2776 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2777 nvmeq->hctx->cpumask);
2778 }
2779}
2780
f0b50732
KB		 2781static int nvme_dev_start(struct nvme_dev *dev)
2782{
2783 int result;
b9afca3e 2784 bool start_thread = false;
f0b50732
KB		 2785
2786 result = nvme_dev_map(dev);
2787 if (result)
2788 return result;
2789
2790 result = nvme_configure_admin_queue(dev);
2791 if (result)
2792 goto unmap;
2793
2794 spin_lock(&dev_list_lock);
b9afca3e
DM		 2795 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2796 start_thread = true;
2797 nvme_thread = NULL;
2798 }
f0b50732
KB		 2799 list_add(&dev->node, &dev_list);
2800 spin_unlock(&dev_list_lock);
2801
b9afca3e
DM		 2802 if (start_thread) {
2803 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2804 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2805 } else
2806 wait_event_killable(nvme_kthread_wait, nvme_thread);
2807
2808 if (IS_ERR_OR_NULL(nvme_thread)) {
2809 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2810 goto disable;
2811 }
a4aea562
MB		 2812
2813 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2814 result = nvme_alloc_admin_tags(dev);
2815 if (result)
2816 goto disable;
b9afca3e 2817
f0b50732 2818 result = nvme_setup_io_queues(dev);
badc34d4 2819 if (result)
0fb59cbc 2820 goto free_tags;
f0b50732 2821
a4aea562
MB		 2822 nvme_set_irq_hints(dev);
2823
1efccc9d 2824 dev->event_limit = 1;
d82e8bfd 2825 return result;
f0b50732 2826
0fb59cbc
KB		 2827 free_tags:
2828 nvme_dev_remove_admin(dev);
f0b50732 2829 disable:
a1a5ef99 2830 nvme_disable_queue(dev, 0);
b9afca3e 2831 nvme_dev_list_remove(dev);
f0b50732
KB		 2832 unmap:
2833 nvme_dev_unmap(dev);
2834 return result;
2835}
2836
9a6b9458
KB		 2837static int nvme_remove_dead_ctrl(void *arg)
2838{
2839 struct nvme_dev *dev = (struct nvme_dev *)arg;
2840 struct pci_dev *pdev = dev->pci_dev;
2841
2842 if (pci_get_drvdata(pdev))
c81f4975 2843 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2844 kref_put(&dev->kref, nvme_free_dev);
2845 return 0;
2846}
2847
2848static void nvme_remove_disks(struct work_struct *ws)
2849{
9a6b9458
KB		 2850 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2851
5a92e700 2852 nvme_free_queues(dev, 1);
302c6727 2853 nvme_dev_remove(dev);
9a6b9458
KB		 2854}
2855
2856static int nvme_dev_resume(struct nvme_dev *dev)
2857{
2858 int ret;
2859
2860 ret = nvme_dev_start(dev);
badc34d4 2861 if (ret)
9a6b9458 2862 return ret;
badc34d4 2863 if (dev->online_queues < 2) {
9a6b9458 2864 spin_lock(&dev_list_lock);
9ca97374 2865 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2866 queue_work(nvme_workq, &dev->reset_work);
2867 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2868 } else {
2869 nvme_unfreeze_queues(dev);
2870 nvme_set_irq_hints(dev);
9a6b9458
KB		 2871 }
2872 return 0;
2873}
2874
2875static void nvme_dev_reset(struct nvme_dev *dev)
2876{
2877 nvme_dev_shutdown(dev);
2878 if (nvme_dev_resume(dev)) {
a4aea562 2879 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2880 kref_get(&dev->kref);
2881 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2882 dev->instance))) {
2883 dev_err(&dev->pci_dev->dev,
2884 "Failed to start controller remove task\n");
2885 kref_put(&dev->kref, nvme_free_dev);
2886 }
2887 }
2888}
2889
2890static void nvme_reset_failed_dev(struct work_struct *ws)
2891{
2892 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2893 nvme_dev_reset(dev);
2894}
2895
9ca97374
TH		 2896static void nvme_reset_workfn(struct work_struct *work)
2897{
2898 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2899 dev->reset_workfn(work);
2900}
2901
2e1d8448 2902static void nvme_async_probe(struct work_struct *work);
8d85fce7 2903static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2904{
a4aea562 2905 int node, result = -ENOMEM;
b60503ba
MW		 2906 struct nvme_dev *dev;
2907
a4aea562
MB		 2908 node = dev_to_node(&pdev->dev);
2909 if (node == NUMA_NO_NODE)
2910 set_dev_node(&pdev->dev, 0);
2911
2912 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2913 if (!dev)
2914 return -ENOMEM;
a4aea562
MB		 2915 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2916 GFP_KERNEL, node);
b60503ba
MW		 2917 if (!dev->entry)
2918 goto free;
a4aea562
MB		 2919 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2920 GFP_KERNEL, node);
b60503ba
MW		 2921 if (!dev->queues)
2922 goto free;
2923
2924 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2925 dev->reset_workfn = nvme_reset_failed_dev;
2926 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2927 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2928 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2929 result = nvme_set_instance(dev);
2930 if (result)
a96d4f5c 2931 goto put_pci;
b60503ba 2932
091b6092
MW		 2933 result = nvme_setup_prp_pools(dev);
2934 if (result)
0877cb0d 2935 goto release;
091b6092 2936
fb35e914 2937 kref_init(&dev->kref);
b3fffdef
KB		 2938 dev->device = device_create(nvme_class, &pdev->dev,
2939 MKDEV(nvme_char_major, dev->instance),
2940 dev, "nvme%d", dev->instance);
2941 if (IS_ERR(dev->device)) {
2942 result = PTR_ERR(dev->device);
2e1d8448 2943 goto release_pools;
b3fffdef
KB		 2944 }
2945 get_device(dev->device);
740216fc 2946
e6e96d73 2947 INIT_LIST_HEAD(&dev->node);
2e1d8448
KB		 2948 INIT_WORK(&dev->probe_work, nvme_async_probe);
2949 schedule_work(&dev->probe_work);
b60503ba
MW		 2950 return 0;
2951
0877cb0d 2952 release_pools:
091b6092 2953 nvme_release_prp_pools(dev);
0877cb0d
KB		 2954 release:
2955 nvme_release_instance(dev);
a96d4f5c
KB		 2956 put_pci:
2957 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2958 free:
2959 kfree(dev->queues);
2960 kfree(dev->entry);
2961 kfree(dev);
2962 return result;
2963}
2964
2e1d8448
KB		 2965static void nvme_async_probe(struct work_struct *work)
2966{
2967 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2968 int result;
2969
2970 result = nvme_dev_start(dev);
2971 if (result)
2972 goto reset;
2973
2974 if (dev->online_queues > 1)
2975 result = nvme_dev_add(dev);
2976 if (result)
2977 goto reset;
2978
2979 nvme_set_irq_hints(dev);
2e1d8448
KB		 2980 return;
2981 reset:
07836e65
KB		 2982 if (!work_busy(&dev->reset_work)) {
2983 dev->reset_workfn = nvme_reset_failed_dev;
2984 queue_work(nvme_workq, &dev->reset_work);
2985 }
2e1d8448
KB		 2986}
2987
f0d54a54
KB		 2988static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2989{
a6739479 2990 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2991
a6739479
KB		 2992 if (prepare)
2993 nvme_dev_shutdown(dev);
2994 else
2995 nvme_dev_resume(dev);
f0d54a54
KB		 2996}
2997
09ece142
KB		 2998static void nvme_shutdown(struct pci_dev *pdev)
2999{
3000 struct nvme_dev *dev = pci_get_drvdata(pdev);
3001 nvme_dev_shutdown(dev);
3002}
3003
8d85fce7 3004static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3005{
3006 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3007
3008 spin_lock(&dev_list_lock);
3009 list_del_init(&dev->node);
3010 spin_unlock(&dev_list_lock);
3011
3012 pci_set_drvdata(pdev, NULL);
2e1d8448 3013 flush_work(&dev->probe_work);
9a6b9458 3014 flush_work(&dev->reset_work);
9a6b9458 3015 nvme_dev_shutdown(dev);
c9d3bf88 3016 nvme_dev_remove(dev);
a4aea562 3017 nvme_dev_remove_admin(dev);
b3fffdef 3018 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3019 nvme_free_queues(dev, 0);
9a6b9458 3020 nvme_release_prp_pools(dev);
5e82e952 3021 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3022}
3023
3024/* These functions are yet to be implemented */
3025#define nvme_error_detected NULL
3026#define nvme_dump_registers NULL
3027#define nvme_link_reset NULL
3028#define nvme_slot_reset NULL
3029#define nvme_error_resume NULL
cd638946 3030
671a6018 3031#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3032static int nvme_suspend(struct device *dev)
3033{
3034 struct pci_dev *pdev = to_pci_dev(dev);
3035 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3036
3037 nvme_dev_shutdown(ndev);
3038 return 0;
3039}
3040
3041static int nvme_resume(struct device *dev)
3042{
3043 struct pci_dev *pdev = to_pci_dev(dev);
3044 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3045
9a6b9458 3046 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3047 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3048 queue_work(nvme_workq, &ndev->reset_work);
3049 }
3050 return 0;
cd638946 3051}
671a6018 3052#endif
cd638946
KB		 3053
3054static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3055
1d352035 3056static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3057 .error_detected = nvme_error_detected,
3058 .mmio_enabled = nvme_dump_registers,
3059 .link_reset = nvme_link_reset,
3060 .slot_reset = nvme_slot_reset,
3061 .resume = nvme_error_resume,
f0d54a54 3062 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3063};
3064
3065/* Move to pci_ids.h later */
3066#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3067
6eb0d698 3068static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3069 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3070 { 0, }
3071};
3072MODULE_DEVICE_TABLE(pci, nvme_id_table);
3073
3074static struct pci_driver nvme_driver = {
3075 .name = "nvme",
3076 .id_table = nvme_id_table,
3077 .probe = nvme_probe,
8d85fce7 3078 .remove = nvme_remove,
09ece142 3079 .shutdown = nvme_shutdown,
cd638946
KB		 3080 .driver = {
3081 .pm = &nvme_dev_pm_ops,
3082 },
b60503ba
MW		 3083 .err_handler = &nvme_err_handler,
3084};
3085
3086static int __init nvme_init(void)
3087{
0ac13140 3088 int result;
1fa6aead 3089
b9afca3e 3090 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3091
9a6b9458
KB		 3092 nvme_workq = create_singlethread_workqueue("nvme");
3093 if (!nvme_workq)
b9afca3e 3094 return -ENOMEM;
9a6b9458 3095
5c42ea16
KB		 3096 result = register_blkdev(nvme_major, "nvme");
3097 if (result < 0)
9a6b9458 3098 goto kill_workq;
5c42ea16 3099 else if (result > 0)
0ac13140 3100 nvme_major = result;
b60503ba 3101
b3fffdef
KB		 3102 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3103 &nvme_dev_fops);
3104 if (result < 0)
3105 goto unregister_blkdev;
3106 else if (result > 0)
3107 nvme_char_major = result;
3108
3109 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3110 if (IS_ERR(nvme_class)) {
3111 result = PTR_ERR(nvme_class);
b3fffdef 3112 goto unregister_chrdev;
c727040b 3113 }
b3fffdef 3114
f3db22fe
KB		 3115 result = pci_register_driver(&nvme_driver);
3116 if (result)
b3fffdef 3117 goto destroy_class;
1fa6aead 3118 return 0;
b60503ba 3119
b3fffdef
KB		 3120 destroy_class:
3121 class_destroy(nvme_class);
3122 unregister_chrdev:
3123 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3124 unregister_blkdev:
b60503ba 3125 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3126 kill_workq:
3127 destroy_workqueue(nvme_workq);
b60503ba
MW		 3128 return result;
3129}
3130
3131static void __exit nvme_exit(void)
3132{
3133 pci_unregister_driver(&nvme_driver);
3134 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3135 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3136 class_destroy(nvme_class);
3137 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3138 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3139 _nvme_check_size();
b60503ba
MW		 3140}
3141
3142MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3143MODULE_LICENSE("GPL");
c78b4713 3144MODULE_VERSION("1.0");
b60503ba
MW		 3145module_init(nvme_init);
3146module_exit(nvme_exit);
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