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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
4ff4b44c | 40 | #include <linux/hash.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
d07f0e59 | 44 | #include <linux/reservation.h> |
e73bdd20 CW |
45 | #include <linux/shmem_fs.h> |
46 | ||
47 | #include <drm/drmP.h> | |
48 | #include <drm/intel-gtt.h> | |
49 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
50 | #include <drm/drm_gem.h> | |
3b96a0b1 | 51 | #include <drm/drm_auth.h> |
f9a87bd7 | 52 | #include <drm/drm_cache.h> |
e73bdd20 CW |
53 | |
54 | #include "i915_params.h" | |
55 | #include "i915_reg.h" | |
40b326ee | 56 | #include "i915_utils.h" |
e73bdd20 | 57 | |
16586fcd | 58 | #include "intel_uncore.h" |
e73bdd20 | 59 | #include "intel_bios.h" |
ac7f11c6 | 60 | #include "intel_dpll_mgr.h" |
8c4f24f9 | 61 | #include "intel_uc.h" |
e73bdd20 CW |
62 | #include "intel_lrc.h" |
63 | #include "intel_ringbuffer.h" | |
64 | ||
d501b1d2 | 65 | #include "i915_gem.h" |
6095868a | 66 | #include "i915_gem_context.h" |
b42fe9ca JL |
67 | #include "i915_gem_fence_reg.h" |
68 | #include "i915_gem_object.h" | |
e73bdd20 CW |
69 | #include "i915_gem_gtt.h" |
70 | #include "i915_gem_render_state.h" | |
05235c53 | 71 | #include "i915_gem_request.h" |
73cb9701 | 72 | #include "i915_gem_timeline.h" |
585fb111 | 73 | |
b42fe9ca JL |
74 | #include "i915_vma.h" |
75 | ||
0ad35fed ZW |
76 | #include "intel_gvt.h" |
77 | ||
1da177e4 LT |
78 | /* General customization: |
79 | */ | |
80 | ||
1da177e4 LT |
81 | #define DRIVER_NAME "i915" |
82 | #define DRIVER_DESC "Intel Graphics" | |
cdc1cdca JN |
83 | #define DRIVER_DATE "20171023" |
84 | #define DRIVER_TIMESTAMP 1508748913 | |
1da177e4 | 85 | |
e2c719b7 RC |
86 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
87 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
88 | * which may not necessarily be a user visible problem. This will either | |
89 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
90 | * enable distros and users to tailor their preferred amount of i915 abrt | |
91 | * spam. | |
92 | */ | |
93 | #define I915_STATE_WARN(condition, format...) ({ \ | |
94 | int __ret_warn_on = !!(condition); \ | |
32753cb8 | 95 | if (unlikely(__ret_warn_on)) \ |
4f044a88 | 96 | if (!WARN(i915_modparams.verbose_state_checks, format)) \ |
e2c719b7 | 97 | DRM_ERROR(format); \ |
e2c719b7 RC |
98 | unlikely(__ret_warn_on); \ |
99 | }) | |
100 | ||
152b2262 JL |
101 | #define I915_STATE_WARN_ON(x) \ |
102 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 103 | |
4fec15d1 ID |
104 | bool __i915_inject_load_failure(const char *func, int line); |
105 | #define i915_inject_load_failure() \ | |
106 | __i915_inject_load_failure(__func__, __LINE__) | |
107 | ||
b95320bd MK |
108 | typedef struct { |
109 | uint32_t val; | |
110 | } uint_fixed_16_16_t; | |
111 | ||
112 | #define FP_16_16_MAX ({ \ | |
113 | uint_fixed_16_16_t fp; \ | |
114 | fp.val = UINT_MAX; \ | |
115 | fp; \ | |
116 | }) | |
117 | ||
d555cb58 KM |
118 | static inline bool is_fixed16_zero(uint_fixed_16_16_t val) |
119 | { | |
120 | if (val.val == 0) | |
121 | return true; | |
122 | return false; | |
123 | } | |
124 | ||
eac2cb81 | 125 | static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) |
b95320bd MK |
126 | { |
127 | uint_fixed_16_16_t fp; | |
128 | ||
0b4d7cbf | 129 | WARN_ON(val > U16_MAX); |
b95320bd MK |
130 | |
131 | fp.val = val << 16; | |
132 | return fp; | |
133 | } | |
134 | ||
eac2cb81 | 135 | static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp) |
b95320bd MK |
136 | { |
137 | return DIV_ROUND_UP(fp.val, 1 << 16); | |
138 | } | |
139 | ||
eac2cb81 | 140 | static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp) |
b95320bd MK |
141 | { |
142 | return fp.val >> 16; | |
143 | } | |
144 | ||
eac2cb81 | 145 | static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1, |
b95320bd MK |
146 | uint_fixed_16_16_t min2) |
147 | { | |
148 | uint_fixed_16_16_t min; | |
149 | ||
150 | min.val = min(min1.val, min2.val); | |
151 | return min; | |
152 | } | |
153 | ||
eac2cb81 | 154 | static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1, |
b95320bd MK |
155 | uint_fixed_16_16_t max2) |
156 | { | |
157 | uint_fixed_16_16_t max; | |
158 | ||
159 | max.val = max(max1.val, max2.val); | |
160 | return max; | |
161 | } | |
162 | ||
07ab976d KM |
163 | static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) |
164 | { | |
165 | uint_fixed_16_16_t fp; | |
0b4d7cbf KM |
166 | WARN_ON(val > U32_MAX); |
167 | fp.val = (uint32_t) val; | |
07ab976d KM |
168 | return fp; |
169 | } | |
170 | ||
a9d055de KM |
171 | static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, |
172 | uint_fixed_16_16_t d) | |
173 | { | |
174 | return DIV_ROUND_UP(val.val, d.val); | |
175 | } | |
176 | ||
177 | static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, | |
178 | uint_fixed_16_16_t mul) | |
179 | { | |
180 | uint64_t intermediate_val; | |
a9d055de KM |
181 | |
182 | intermediate_val = (uint64_t) val * mul.val; | |
183 | intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); | |
0b4d7cbf KM |
184 | WARN_ON(intermediate_val > U32_MAX); |
185 | return (uint32_t) intermediate_val; | |
a9d055de KM |
186 | } |
187 | ||
188 | static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, | |
189 | uint_fixed_16_16_t mul) | |
190 | { | |
191 | uint64_t intermediate_val; | |
a9d055de KM |
192 | |
193 | intermediate_val = (uint64_t) val.val * mul.val; | |
194 | intermediate_val = intermediate_val >> 16; | |
07ab976d | 195 | return clamp_u64_to_fixed16(intermediate_val); |
a9d055de KM |
196 | } |
197 | ||
eac2cb81 | 198 | static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d) |
b95320bd | 199 | { |
b95320bd MK |
200 | uint64_t interm_val; |
201 | ||
202 | interm_val = (uint64_t)val << 16; | |
203 | interm_val = DIV_ROUND_UP_ULL(interm_val, d); | |
07ab976d | 204 | return clamp_u64_to_fixed16(interm_val); |
b95320bd MK |
205 | } |
206 | ||
a9d055de KM |
207 | static inline uint32_t div_round_up_u32_fixed16(uint32_t val, |
208 | uint_fixed_16_16_t d) | |
209 | { | |
210 | uint64_t interm_val; | |
211 | ||
212 | interm_val = (uint64_t)val << 16; | |
213 | interm_val = DIV_ROUND_UP_ULL(interm_val, d.val); | |
0b4d7cbf KM |
214 | WARN_ON(interm_val > U32_MAX); |
215 | return (uint32_t) interm_val; | |
a9d055de KM |
216 | } |
217 | ||
eac2cb81 | 218 | static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val, |
b95320bd MK |
219 | uint_fixed_16_16_t mul) |
220 | { | |
221 | uint64_t intermediate_val; | |
b95320bd MK |
222 | |
223 | intermediate_val = (uint64_t) val * mul.val; | |
07ab976d | 224 | return clamp_u64_to_fixed16(intermediate_val); |
b95320bd MK |
225 | } |
226 | ||
6ea593c0 KM |
227 | static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1, |
228 | uint_fixed_16_16_t add2) | |
229 | { | |
230 | uint64_t interm_sum; | |
231 | ||
232 | interm_sum = (uint64_t) add1.val + add2.val; | |
233 | return clamp_u64_to_fixed16(interm_sum); | |
234 | } | |
235 | ||
236 | static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1, | |
237 | uint32_t add2) | |
238 | { | |
239 | uint64_t interm_sum; | |
240 | uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2); | |
241 | ||
242 | interm_sum = (uint64_t) add1.val + interm_add2.val; | |
243 | return clamp_u64_to_fixed16(interm_sum); | |
244 | } | |
245 | ||
42a8ca4c JN |
246 | static inline const char *yesno(bool v) |
247 | { | |
248 | return v ? "yes" : "no"; | |
249 | } | |
250 | ||
87ad3212 JN |
251 | static inline const char *onoff(bool v) |
252 | { | |
253 | return v ? "on" : "off"; | |
254 | } | |
255 | ||
08c4d7fc TU |
256 | static inline const char *enableddisabled(bool v) |
257 | { | |
258 | return v ? "enabled" : "disabled"; | |
259 | } | |
260 | ||
317c35d1 | 261 | enum pipe { |
752aa88a | 262 | INVALID_PIPE = -1, |
317c35d1 JB |
263 | PIPE_A = 0, |
264 | PIPE_B, | |
9db4a9c7 | 265 | PIPE_C, |
a57c774a AK |
266 | _PIPE_EDP, |
267 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 268 | }; |
9db4a9c7 | 269 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 270 | |
a5c961d1 PZ |
271 | enum transcoder { |
272 | TRANSCODER_A = 0, | |
273 | TRANSCODER_B, | |
274 | TRANSCODER_C, | |
a57c774a | 275 | TRANSCODER_EDP, |
4d1de975 JN |
276 | TRANSCODER_DSI_A, |
277 | TRANSCODER_DSI_C, | |
a57c774a | 278 | I915_MAX_TRANSCODERS |
a5c961d1 | 279 | }; |
da205630 JN |
280 | |
281 | static inline const char *transcoder_name(enum transcoder transcoder) | |
282 | { | |
283 | switch (transcoder) { | |
284 | case TRANSCODER_A: | |
285 | return "A"; | |
286 | case TRANSCODER_B: | |
287 | return "B"; | |
288 | case TRANSCODER_C: | |
289 | return "C"; | |
290 | case TRANSCODER_EDP: | |
291 | return "EDP"; | |
4d1de975 JN |
292 | case TRANSCODER_DSI_A: |
293 | return "DSI A"; | |
294 | case TRANSCODER_DSI_C: | |
295 | return "DSI C"; | |
da205630 JN |
296 | default: |
297 | return "<invalid>"; | |
298 | } | |
299 | } | |
a5c961d1 | 300 | |
4d1de975 JN |
301 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
302 | { | |
303 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
304 | } | |
305 | ||
84139d1e | 306 | /* |
b14e5848 VS |
307 | * Global legacy plane identifier. Valid only for primary/sprite |
308 | * planes on pre-g4x, and only for primary planes on g4x+. | |
84139d1e | 309 | */ |
80824003 | 310 | enum plane { |
b14e5848 | 311 | PLANE_A, |
80824003 | 312 | PLANE_B, |
9db4a9c7 | 313 | PLANE_C, |
80824003 | 314 | }; |
9db4a9c7 | 315 | #define plane_name(p) ((p) + 'A') |
52440211 | 316 | |
580503c7 | 317 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 318 | |
b14e5848 VS |
319 | /* |
320 | * Per-pipe plane identifier. | |
321 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) | |
322 | * number of planes per CRTC. Not all platforms really have this many planes, | |
323 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
324 | * between the topmost sprite plane and the cursor plane. | |
325 | * | |
326 | * This is expected to be passed to various register macros | |
327 | * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. | |
328 | */ | |
329 | enum plane_id { | |
330 | PLANE_PRIMARY, | |
331 | PLANE_SPRITE0, | |
332 | PLANE_SPRITE1, | |
19c3164d | 333 | PLANE_SPRITE2, |
b14e5848 VS |
334 | PLANE_CURSOR, |
335 | I915_MAX_PLANES, | |
336 | }; | |
337 | ||
d97d7b48 VS |
338 | #define for_each_plane_id_on_crtc(__crtc, __p) \ |
339 | for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ | |
340 | for_each_if ((__crtc)->plane_ids_mask & BIT(__p)) | |
341 | ||
2b139522 | 342 | enum port { |
03cdc1d4 | 343 | PORT_NONE = -1, |
2b139522 ED |
344 | PORT_A = 0, |
345 | PORT_B, | |
346 | PORT_C, | |
347 | PORT_D, | |
348 | PORT_E, | |
349 | I915_MAX_PORTS | |
350 | }; | |
351 | #define port_name(p) ((p) + 'A') | |
352 | ||
a09caddd | 353 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
354 | |
355 | enum dpio_channel { | |
356 | DPIO_CH0, | |
357 | DPIO_CH1 | |
358 | }; | |
359 | ||
360 | enum dpio_phy { | |
361 | DPIO_PHY0, | |
0a116ce8 ACO |
362 | DPIO_PHY1, |
363 | DPIO_PHY2, | |
e4607fcf CML |
364 | }; |
365 | ||
b97186f0 PZ |
366 | enum intel_display_power_domain { |
367 | POWER_DOMAIN_PIPE_A, | |
368 | POWER_DOMAIN_PIPE_B, | |
369 | POWER_DOMAIN_PIPE_C, | |
370 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
371 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
372 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
373 | POWER_DOMAIN_TRANSCODER_A, | |
374 | POWER_DOMAIN_TRANSCODER_B, | |
375 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 376 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
377 | POWER_DOMAIN_TRANSCODER_DSI_A, |
378 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
379 | POWER_DOMAIN_PORT_DDI_A_LANES, |
380 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
381 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
382 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
383 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
62b69566 ACO |
384 | POWER_DOMAIN_PORT_DDI_A_IO, |
385 | POWER_DOMAIN_PORT_DDI_B_IO, | |
386 | POWER_DOMAIN_PORT_DDI_C_IO, | |
387 | POWER_DOMAIN_PORT_DDI_D_IO, | |
388 | POWER_DOMAIN_PORT_DDI_E_IO, | |
319be8ae ID |
389 | POWER_DOMAIN_PORT_DSI, |
390 | POWER_DOMAIN_PORT_CRT, | |
391 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 392 | POWER_DOMAIN_VGA, |
fbeeaa23 | 393 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 394 | POWER_DOMAIN_PLLS, |
1407121a S |
395 | POWER_DOMAIN_AUX_A, |
396 | POWER_DOMAIN_AUX_B, | |
397 | POWER_DOMAIN_AUX_C, | |
398 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 399 | POWER_DOMAIN_GMBUS, |
dfa57627 | 400 | POWER_DOMAIN_MODESET, |
baa70707 | 401 | POWER_DOMAIN_INIT, |
bddc7645 ID |
402 | |
403 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
404 | }; |
405 | ||
406 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
407 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
408 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
409 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
410 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
411 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 412 | |
1d843f9d EE |
413 | enum hpd_pin { |
414 | HPD_NONE = 0, | |
1d843f9d EE |
415 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
416 | HPD_CRT, | |
417 | HPD_SDVO_B, | |
418 | HPD_SDVO_C, | |
cc24fcdc | 419 | HPD_PORT_A, |
1d843f9d EE |
420 | HPD_PORT_B, |
421 | HPD_PORT_C, | |
422 | HPD_PORT_D, | |
26951caf | 423 | HPD_PORT_E, |
1d843f9d EE |
424 | HPD_NUM_PINS |
425 | }; | |
426 | ||
c91711f9 JN |
427 | #define for_each_hpd_pin(__pin) \ |
428 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
429 | ||
317eaa95 L |
430 | #define HPD_STORM_DEFAULT_THRESHOLD 5 |
431 | ||
5fcece80 JN |
432 | struct i915_hotplug { |
433 | struct work_struct hotplug_work; | |
434 | ||
435 | struct { | |
436 | unsigned long last_jiffies; | |
437 | int count; | |
438 | enum { | |
439 | HPD_ENABLED = 0, | |
440 | HPD_DISABLED = 1, | |
441 | HPD_MARK_DISABLED = 2 | |
442 | } state; | |
443 | } stats[HPD_NUM_PINS]; | |
444 | u32 event_bits; | |
445 | struct delayed_work reenable_work; | |
446 | ||
447 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
448 | u32 long_port_mask; | |
449 | u32 short_port_mask; | |
450 | struct work_struct dig_port_work; | |
451 | ||
19625e85 L |
452 | struct work_struct poll_init_work; |
453 | bool poll_enabled; | |
454 | ||
317eaa95 L |
455 | unsigned int hpd_storm_threshold; |
456 | ||
5fcece80 JN |
457 | /* |
458 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
459 | * the non-DP HPD could block the workqueue on a mode config | |
460 | * mutex getting, that userspace may have taken. However | |
461 | * userspace is waiting on the DP workqueue to run which is | |
462 | * blocked behind the non-DP one. | |
463 | */ | |
464 | struct workqueue_struct *dp_wq; | |
465 | }; | |
466 | ||
2a2d5482 CW |
467 | #define I915_GEM_GPU_DOMAINS \ |
468 | (I915_GEM_DOMAIN_RENDER | \ | |
469 | I915_GEM_DOMAIN_SAMPLER | \ | |
470 | I915_GEM_DOMAIN_COMMAND | \ | |
471 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
472 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 473 | |
055e393f DL |
474 | #define for_each_pipe(__dev_priv, __p) \ |
475 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
476 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
477 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
478 | for_each_if ((__mask) & (1 << (__p))) | |
8b364b41 | 479 | #define for_each_universal_plane(__dev_priv, __pipe, __p) \ |
dd740780 DL |
480 | for ((__p) = 0; \ |
481 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
482 | (__p)++) | |
3bdcfc0c DL |
483 | #define for_each_sprite(__dev_priv, __p, __s) \ |
484 | for ((__s) = 0; \ | |
485 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
486 | (__s)++) | |
9db4a9c7 | 487 | |
c3aeadc8 JN |
488 | #define for_each_port_masked(__port, __ports_mask) \ |
489 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
490 | for_each_if ((__ports_mask) & (1 << (__port))) | |
491 | ||
d79b814d | 492 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 493 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 494 | |
27321ae8 ML |
495 | #define for_each_intel_plane(dev, intel_plane) \ |
496 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 497 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
498 | base.head) |
499 | ||
c107acfe | 500 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
501 | list_for_each_entry(intel_plane, \ |
502 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
503 | base.head) \ |
504 | for_each_if ((plane_mask) & \ | |
505 | (1 << drm_plane_index(&intel_plane->base))) | |
506 | ||
262cd2e1 VS |
507 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
508 | list_for_each_entry(intel_plane, \ | |
509 | &(dev)->mode_config.plane_list, \ | |
510 | base.head) \ | |
95150bdf | 511 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 512 | |
91c8a326 CW |
513 | #define for_each_intel_crtc(dev, intel_crtc) \ |
514 | list_for_each_entry(intel_crtc, \ | |
515 | &(dev)->mode_config.crtc_list, \ | |
516 | base.head) | |
d063ae48 | 517 | |
91c8a326 CW |
518 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
519 | list_for_each_entry(intel_crtc, \ | |
520 | &(dev)->mode_config.crtc_list, \ | |
521 | base.head) \ | |
98d39494 MR |
522 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
523 | ||
b2784e15 DL |
524 | #define for_each_intel_encoder(dev, intel_encoder) \ |
525 | list_for_each_entry(intel_encoder, \ | |
526 | &(dev)->mode_config.encoder_list, \ | |
527 | base.head) | |
528 | ||
3f6a5e1e DV |
529 | #define for_each_intel_connector_iter(intel_connector, iter) \ |
530 | while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) | |
531 | ||
6c2b7c12 DV |
532 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
533 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 534 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 535 | |
53f5e3ca JB |
536 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
537 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 538 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 539 | |
b04c5bd6 BF |
540 | #define for_each_power_domain(domain, mask) \ |
541 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
d8fc70b7 | 542 | for_each_if (BIT_ULL(domain) & (mask)) |
b04c5bd6 | 543 | |
75ccb2ec ID |
544 | #define for_each_power_well(__dev_priv, __power_well) \ |
545 | for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ | |
546 | (__power_well) - (__dev_priv)->power_domains.power_wells < \ | |
547 | (__dev_priv)->power_domains.power_well_count; \ | |
548 | (__power_well)++) | |
549 | ||
550 | #define for_each_power_well_rev(__dev_priv, __power_well) \ | |
551 | for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ | |
552 | (__dev_priv)->power_domains.power_well_count - 1; \ | |
553 | (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ | |
554 | (__power_well)--) | |
555 | ||
556 | #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ | |
557 | for_each_power_well(__dev_priv, __power_well) \ | |
558 | for_each_if ((__power_well)->domains & (__domain_mask)) | |
559 | ||
560 | #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \ | |
561 | for_each_power_well_rev(__dev_priv, __power_well) \ | |
562 | for_each_if ((__power_well)->domains & (__domain_mask)) | |
563 | ||
ff32c54e VS |
564 | #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \ |
565 | for ((__i) = 0; \ | |
566 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
567 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
568 | (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \ | |
569 | (__i)++) \ | |
570 | for_each_if (plane_state) | |
571 | ||
d305e061 VS |
572 | #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ |
573 | for ((__i) = 0; \ | |
574 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
575 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
576 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
577 | (__i)++) \ | |
578 | for_each_if (crtc) | |
579 | ||
580 | ||
7b510451 VS |
581 | #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ |
582 | for ((__i) = 0; \ | |
583 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
584 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
585 | (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ | |
586 | (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ | |
587 | (__i)++) \ | |
588 | for_each_if (plane) | |
589 | ||
e7b903d2 | 590 | struct drm_i915_private; |
ad46cb53 | 591 | struct i915_mm_struct; |
5cc9ed4b | 592 | struct i915_mmu_object; |
e7b903d2 | 593 | |
a6f766f3 CW |
594 | struct drm_i915_file_private { |
595 | struct drm_i915_private *dev_priv; | |
596 | struct drm_file *file; | |
597 | ||
598 | struct { | |
599 | spinlock_t lock; | |
600 | struct list_head request_list; | |
d0bc54f2 CW |
601 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
602 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
603 | * (when using lax throttling for the frontbuffer). We also use it to | |
604 | * offer free GPU waitboosts for severely congested workloads. | |
605 | */ | |
606 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
607 | } mm; |
608 | struct idr context_idr; | |
609 | ||
2e1b8730 | 610 | struct intel_rps_client { |
7b92c1bd | 611 | atomic_t boosts; |
562d9bae | 612 | } rps_client; |
a6f766f3 | 613 | |
c80ff16e | 614 | unsigned int bsd_engine; |
b083a087 MK |
615 | |
616 | /* Client can have a maximum of 3 contexts banned before | |
617 | * it is denied of creating new contexts. As one context | |
618 | * ban needs 4 consecutive hangs, and more if there is | |
619 | * progress in between, this is a last resort stop gap measure | |
620 | * to limit the badly behaving clients access to gpu. | |
621 | */ | |
622 | #define I915_MAX_CLIENT_CONTEXT_BANS 3 | |
77b25a97 | 623 | atomic_t context_bans; |
a6f766f3 CW |
624 | }; |
625 | ||
e69d0bc1 DV |
626 | /* Used by dp and fdi links */ |
627 | struct intel_link_m_n { | |
628 | uint32_t tu; | |
629 | uint32_t gmch_m; | |
630 | uint32_t gmch_n; | |
631 | uint32_t link_m; | |
632 | uint32_t link_n; | |
633 | }; | |
634 | ||
635 | void intel_link_compute_m_n(int bpp, int nlanes, | |
636 | int pixel_clock, int link_clock, | |
b31e85ed JN |
637 | struct intel_link_m_n *m_n, |
638 | bool reduce_m_n); | |
e69d0bc1 | 639 | |
1da177e4 LT |
640 | /* Interface history: |
641 | * | |
642 | * 1.1: Original. | |
0d6aa60b DA |
643 | * 1.2: Add Power Management |
644 | * 1.3: Add vblank support | |
de227f5f | 645 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 646 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
647 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
648 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
649 | */ |
650 | #define DRIVER_MAJOR 1 | |
2228ed67 | 651 | #define DRIVER_MINOR 6 |
1da177e4 LT |
652 | #define DRIVER_PATCHLEVEL 0 |
653 | ||
0a3e67a4 JB |
654 | struct opregion_header; |
655 | struct opregion_acpi; | |
656 | struct opregion_swsci; | |
657 | struct opregion_asle; | |
658 | ||
8ee1c3db | 659 | struct intel_opregion { |
115719fc WD |
660 | struct opregion_header *header; |
661 | struct opregion_acpi *acpi; | |
662 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
663 | u32 swsci_gbda_sub_functions; |
664 | u32 swsci_sbcb_sub_functions; | |
115719fc | 665 | struct opregion_asle *asle; |
04ebaadb | 666 | void *rvda; |
ab3595bc | 667 | void *vbt_firmware; |
82730385 | 668 | const void *vbt; |
ada8f955 | 669 | u32 vbt_size; |
115719fc | 670 | u32 *lid_state; |
91a60f20 | 671 | struct work_struct asle_work; |
8ee1c3db | 672 | }; |
44834a67 | 673 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 674 | |
6ef3d427 CW |
675 | struct intel_overlay; |
676 | struct intel_overlay_error_state; | |
677 | ||
9b9d172d | 678 | struct sdvo_device_mapping { |
e957d772 | 679 | u8 initialized; |
9b9d172d | 680 | u8 dvo_port; |
681 | u8 slave_addr; | |
682 | u8 dvo_wiring; | |
e957d772 | 683 | u8 i2c_pin; |
b1083333 | 684 | u8 ddc_pin; |
9b9d172d | 685 | }; |
686 | ||
7bd688cd | 687 | struct intel_connector; |
820d2d77 | 688 | struct intel_encoder; |
ccf010fb | 689 | struct intel_atomic_state; |
5cec258b | 690 | struct intel_crtc_state; |
5724dbd1 | 691 | struct intel_initial_plane_config; |
0e8ffe1b | 692 | struct intel_crtc; |
ee9300bb DV |
693 | struct intel_limit; |
694 | struct dpll; | |
49cd97a3 | 695 | struct intel_cdclk_state; |
b8cecdf5 | 696 | |
e70236a8 | 697 | struct drm_i915_display_funcs { |
49cd97a3 VS |
698 | void (*get_cdclk)(struct drm_i915_private *dev_priv, |
699 | struct intel_cdclk_state *cdclk_state); | |
b0587e4d VS |
700 | void (*set_cdclk)(struct drm_i915_private *dev_priv, |
701 | const struct intel_cdclk_state *cdclk_state); | |
ef0f5e93 | 702 | int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); |
e3bddded | 703 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
704 | int (*compute_intermediate_wm)(struct drm_device *dev, |
705 | struct intel_crtc *intel_crtc, | |
706 | struct intel_crtc_state *newstate); | |
ccf010fb ML |
707 | void (*initial_watermarks)(struct intel_atomic_state *state, |
708 | struct intel_crtc_state *cstate); | |
709 | void (*atomic_update_watermarks)(struct intel_atomic_state *state, | |
710 | struct intel_crtc_state *cstate); | |
711 | void (*optimize_watermarks)(struct intel_atomic_state *state, | |
712 | struct intel_crtc_state *cstate); | |
98d39494 | 713 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
432081bc | 714 | void (*update_wm)(struct intel_crtc *crtc); |
27c329ed | 715 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
0e8ffe1b DV |
716 | /* Returns the active state of the crtc, and if the crtc is active, |
717 | * fills out the pipe-config with the hw state. */ | |
718 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 719 | struct intel_crtc_state *); |
5724dbd1 DL |
720 | void (*get_initial_plane_config)(struct intel_crtc *, |
721 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
722 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
723 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
724 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
725 | struct drm_atomic_state *old_state); | |
726 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
727 | struct drm_atomic_state *old_state); | |
b44d5c0c | 728 | void (*update_crtcs)(struct drm_atomic_state *state); |
69bfe1a9 JN |
729 | void (*audio_codec_enable)(struct drm_connector *connector, |
730 | struct intel_encoder *encoder, | |
5e7234c9 | 731 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 732 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
dc4a1094 ACO |
733 | void (*fdi_link_train)(struct intel_crtc *crtc, |
734 | const struct intel_crtc_state *crtc_state); | |
46f16e63 | 735 | void (*init_clock_gating)(struct drm_i915_private *dev_priv); |
91d14251 | 736 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
737 | /* clock updates for mode set */ |
738 | /* cursor updates */ | |
739 | /* render clock increase/decrease */ | |
740 | /* display clock increase/decrease */ | |
741 | /* pll clock increase/decrease */ | |
8563b1e8 | 742 | |
b95c5321 ML |
743 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
744 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
745 | }; |
746 | ||
b6e7d894 DL |
747 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
748 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
749 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
750 | ||
eb805623 | 751 | struct intel_csr { |
8144ac59 | 752 | struct work_struct work; |
eb805623 | 753 | const char *fw_path; |
a7f749f9 | 754 | uint32_t *dmc_payload; |
eb805623 | 755 | uint32_t dmc_fw_size; |
b6e7d894 | 756 | uint32_t version; |
eb805623 | 757 | uint32_t mmio_count; |
f0f59a00 | 758 | i915_reg_t mmioaddr[8]; |
eb805623 | 759 | uint32_t mmiodata[8]; |
832dba88 | 760 | uint32_t dc_state; |
a37baf3b | 761 | uint32_t allowed_dc_mask; |
eb805623 DV |
762 | }; |
763 | ||
604db650 JL |
764 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
765 | func(is_mobile); \ | |
3e4274f8 | 766 | func(is_lp); \ |
c007fb4a | 767 | func(is_alpha_support); \ |
566c56a4 | 768 | /* Keep has_* in alphabetical order */ \ |
dfc5148f | 769 | func(has_64bit_reloc); \ |
9e1d0e60 | 770 | func(has_aliasing_ppgtt); \ |
604db650 | 771 | func(has_csr); \ |
566c56a4 | 772 | func(has_ddi); \ |
604db650 | 773 | func(has_dp_mst); \ |
142bc7d9 | 774 | func(has_reset_engine); \ |
566c56a4 JL |
775 | func(has_fbc); \ |
776 | func(has_fpga_dbg); \ | |
9e1d0e60 MT |
777 | func(has_full_ppgtt); \ |
778 | func(has_full_48bit_ppgtt); \ | |
604db650 JL |
779 | func(has_gmch_display); \ |
780 | func(has_guc); \ | |
f8a58d63 | 781 | func(has_guc_ct); \ |
604db650 | 782 | func(has_hotplug); \ |
566c56a4 | 783 | func(has_l3_dpf); \ |
604db650 | 784 | func(has_llc); \ |
566c56a4 | 785 | func(has_logical_ring_contexts); \ |
e7af3116 | 786 | func(has_logical_ring_preemption); \ |
566c56a4 | 787 | func(has_overlay); \ |
566c56a4 JL |
788 | func(has_pooled_eu); \ |
789 | func(has_psr); \ | |
790 | func(has_rc6); \ | |
791 | func(has_rc6p); \ | |
792 | func(has_resource_streamer); \ | |
793 | func(has_runtime_pm); \ | |
604db650 | 794 | func(has_snoop); \ |
f4ce766f | 795 | func(unfenced_needs_alignment); \ |
566c56a4 JL |
796 | func(cursor_needs_physical); \ |
797 | func(hws_needs_physical); \ | |
798 | func(overlay_needs_physical); \ | |
e57f1c02 MK |
799 | func(supports_tv); \ |
800 | func(has_ipc); | |
c96ea64e | 801 | |
915490d5 | 802 | struct sseu_dev_info { |
f08a0c92 | 803 | u8 slice_mask; |
57ec171e | 804 | u8 subslice_mask; |
915490d5 ID |
805 | u8 eu_total; |
806 | u8 eu_per_subslice; | |
43b67998 ID |
807 | u8 min_eu_in_pool; |
808 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
809 | u8 subslice_7eu[3]; | |
810 | u8 has_slice_pg:1; | |
811 | u8 has_subslice_pg:1; | |
812 | u8 has_eu_pg:1; | |
915490d5 ID |
813 | }; |
814 | ||
57ec171e ID |
815 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) |
816 | { | |
817 | return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); | |
818 | } | |
819 | ||
2e0d26f8 JN |
820 | /* Keep in gen based order, and chronological order within a gen */ |
821 | enum intel_platform { | |
822 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
823 | INTEL_I830, | |
824 | INTEL_I845G, | |
825 | INTEL_I85X, | |
826 | INTEL_I865G, | |
827 | INTEL_I915G, | |
828 | INTEL_I915GM, | |
829 | INTEL_I945G, | |
830 | INTEL_I945GM, | |
831 | INTEL_G33, | |
832 | INTEL_PINEVIEW, | |
c0f86832 JN |
833 | INTEL_I965G, |
834 | INTEL_I965GM, | |
f69c11ae JN |
835 | INTEL_G45, |
836 | INTEL_GM45, | |
2e0d26f8 JN |
837 | INTEL_IRONLAKE, |
838 | INTEL_SANDYBRIDGE, | |
839 | INTEL_IVYBRIDGE, | |
840 | INTEL_VALLEYVIEW, | |
841 | INTEL_HASWELL, | |
842 | INTEL_BROADWELL, | |
843 | INTEL_CHERRYVIEW, | |
844 | INTEL_SKYLAKE, | |
845 | INTEL_BROXTON, | |
846 | INTEL_KABYLAKE, | |
847 | INTEL_GEMINILAKE, | |
71851fa8 | 848 | INTEL_COFFEELAKE, |
413f3c19 | 849 | INTEL_CANNONLAKE, |
9160095c | 850 | INTEL_MAX_PLATFORMS |
2e0d26f8 JN |
851 | }; |
852 | ||
cfdf1fa2 | 853 | struct intel_device_info { |
87f1f465 | 854 | u16 device_id; |
ae5702d2 | 855 | u16 gen_mask; |
4d34b11e TU |
856 | |
857 | u8 gen; | |
0890540e | 858 | u8 gt; /* GT number, 0 if undefined */ |
c1bb1145 | 859 | u8 num_rings; |
4d34b11e TU |
860 | u8 ring_mask; /* Rings supported by the HW */ |
861 | ||
862 | enum intel_platform platform; | |
ae7617f0 | 863 | u32 platform_mask; |
4d34b11e TU |
864 | |
865 | u32 display_mmio_offset; | |
866 | ||
867 | u8 num_pipes; | |
868 | u8 num_sprites[I915_MAX_PIPES]; | |
869 | u8 num_scalers[I915_MAX_PIPES]; | |
870 | ||
2a9654b2 MA |
871 | unsigned int page_sizes; /* page sizes supported by the HW */ |
872 | ||
604db650 JL |
873 | #define DEFINE_FLAG(name) u8 name:1 |
874 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
875 | #undef DEFINE_FLAG | |
6f3fff60 | 876 | u16 ddb_size; /* in blocks */ |
4d34b11e | 877 | |
a57c774a AK |
878 | /* Register offsets for the various display pipes and transcoders */ |
879 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
880 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 881 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 882 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
883 | |
884 | /* Slice/subslice/EU info */ | |
43b67998 | 885 | struct sseu_dev_info sseu; |
82cf435b LL |
886 | |
887 | struct color_luts { | |
888 | u16 degamma_lut_size; | |
889 | u16 gamma_lut_size; | |
890 | } color; | |
cfdf1fa2 KH |
891 | }; |
892 | ||
2bd160a1 CW |
893 | struct intel_display_error_state; |
894 | ||
5a4c6f1b | 895 | struct i915_gpu_state { |
2bd160a1 CW |
896 | struct kref ref; |
897 | struct timeval time; | |
de867c20 CW |
898 | struct timeval boottime; |
899 | struct timeval uptime; | |
2bd160a1 | 900 | |
9f267eb8 CW |
901 | struct drm_i915_private *i915; |
902 | ||
2bd160a1 CW |
903 | char error_msg[128]; |
904 | bool simulated; | |
f73b5674 | 905 | bool awake; |
e5aac87e CW |
906 | bool wakelock; |
907 | bool suspended; | |
2bd160a1 CW |
908 | int iommu; |
909 | u32 reset_count; | |
910 | u32 suspend_count; | |
911 | struct intel_device_info device_info; | |
642c8a72 | 912 | struct i915_params params; |
2bd160a1 CW |
913 | |
914 | /* Generic register state */ | |
915 | u32 eir; | |
916 | u32 pgtbl_er; | |
917 | u32 ier; | |
5a4c6f1b | 918 | u32 gtier[4], ngtier; |
2bd160a1 CW |
919 | u32 ccid; |
920 | u32 derrmr; | |
921 | u32 forcewake; | |
922 | u32 error; /* gen6+ */ | |
923 | u32 err_int; /* gen7 */ | |
924 | u32 fault_data0; /* gen8, gen9 */ | |
925 | u32 fault_data1; /* gen8, gen9 */ | |
926 | u32 done_reg; | |
927 | u32 gac_eco; | |
928 | u32 gam_ecochk; | |
929 | u32 gab_ctl; | |
930 | u32 gfx_mode; | |
d636951e | 931 | |
5a4c6f1b | 932 | u32 nfence; |
2bd160a1 CW |
933 | u64 fence[I915_MAX_NUM_FENCES]; |
934 | struct intel_overlay_error_state *overlay; | |
935 | struct intel_display_error_state *display; | |
51d545d0 | 936 | struct drm_i915_error_object *semaphore; |
27b85bea | 937 | struct drm_i915_error_object *guc_log; |
2bd160a1 CW |
938 | |
939 | struct drm_i915_error_engine { | |
940 | int engine_id; | |
941 | /* Software tracked state */ | |
942 | bool waiting; | |
943 | int num_waiters; | |
3fe3b030 MK |
944 | unsigned long hangcheck_timestamp; |
945 | bool hangcheck_stalled; | |
2bd160a1 CW |
946 | enum intel_engine_hangcheck_action hangcheck_action; |
947 | struct i915_address_space *vm; | |
948 | int num_requests; | |
702c8f8e | 949 | u32 reset_count; |
2bd160a1 | 950 | |
cdb324bd CW |
951 | /* position of active request inside the ring */ |
952 | u32 rq_head, rq_post, rq_tail; | |
953 | ||
2bd160a1 CW |
954 | /* our own tracking of ring head and tail */ |
955 | u32 cpu_ring_head; | |
956 | u32 cpu_ring_tail; | |
957 | ||
958 | u32 last_seqno; | |
2bd160a1 CW |
959 | |
960 | /* Register state */ | |
961 | u32 start; | |
962 | u32 tail; | |
963 | u32 head; | |
964 | u32 ctl; | |
21a2c58a | 965 | u32 mode; |
2bd160a1 CW |
966 | u32 hws; |
967 | u32 ipeir; | |
968 | u32 ipehr; | |
2bd160a1 CW |
969 | u32 bbstate; |
970 | u32 instpm; | |
971 | u32 instps; | |
972 | u32 seqno; | |
973 | u64 bbaddr; | |
974 | u64 acthd; | |
975 | u32 fault_reg; | |
976 | u64 faddr; | |
977 | u32 rc_psmi; /* sleep state */ | |
978 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
d636951e | 979 | struct intel_instdone instdone; |
2bd160a1 | 980 | |
4fa6053e CW |
981 | struct drm_i915_error_context { |
982 | char comm[TASK_COMM_LEN]; | |
983 | pid_t pid; | |
984 | u32 handle; | |
985 | u32 hw_id; | |
1f181225 | 986 | int priority; |
4fa6053e CW |
987 | int ban_score; |
988 | int active; | |
989 | int guilty; | |
990 | } context; | |
991 | ||
2bd160a1 | 992 | struct drm_i915_error_object { |
2bd160a1 | 993 | u64 gtt_offset; |
03382dfb | 994 | u64 gtt_size; |
0a97015d CW |
995 | int page_count; |
996 | int unused; | |
2bd160a1 CW |
997 | u32 *pages[0]; |
998 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
999 | ||
b0fd47ad CW |
1000 | struct drm_i915_error_object **user_bo; |
1001 | long user_bo_count; | |
1002 | ||
2bd160a1 CW |
1003 | struct drm_i915_error_object *wa_ctx; |
1004 | ||
1005 | struct drm_i915_error_request { | |
1006 | long jiffies; | |
c84455b4 | 1007 | pid_t pid; |
35ca039e | 1008 | u32 context; |
1f181225 | 1009 | int priority; |
84102171 | 1010 | int ban_score; |
2bd160a1 CW |
1011 | u32 seqno; |
1012 | u32 head; | |
1013 | u32 tail; | |
76e70087 MK |
1014 | } *requests, execlist[EXECLIST_MAX_PORTS]; |
1015 | unsigned int num_ports; | |
2bd160a1 CW |
1016 | |
1017 | struct drm_i915_error_waiter { | |
1018 | char comm[TASK_COMM_LEN]; | |
1019 | pid_t pid; | |
1020 | u32 seqno; | |
1021 | } *waiters; | |
1022 | ||
1023 | struct { | |
1024 | u32 gfx_mode; | |
1025 | union { | |
1026 | u64 pdp[4]; | |
1027 | u32 pp_dir_base; | |
1028 | }; | |
1029 | } vm_info; | |
2bd160a1 CW |
1030 | } engine[I915_NUM_ENGINES]; |
1031 | ||
1032 | struct drm_i915_error_buffer { | |
1033 | u32 size; | |
1034 | u32 name; | |
1035 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
1036 | u64 gtt_offset; | |
1037 | u32 read_domains; | |
1038 | u32 write_domain; | |
1039 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
1040 | u32 tiling:2; | |
1041 | u32 dirty:1; | |
1042 | u32 purgeable:1; | |
1043 | u32 userptr:1; | |
1044 | s32 engine:4; | |
1045 | u32 cache_level:3; | |
1046 | } *active_bo[I915_NUM_ENGINES], *pinned_bo; | |
1047 | u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; | |
1048 | struct i915_address_space *active_vm[I915_NUM_ENGINES]; | |
1049 | }; | |
1050 | ||
7faf1ab2 DV |
1051 | enum i915_cache_level { |
1052 | I915_CACHE_NONE = 0, | |
350ec881 CW |
1053 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
1054 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
1055 | caches, eg sampler/render caches, and the | |
1056 | large Last-Level-Cache. LLC is coherent with | |
1057 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 1058 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
1059 | }; |
1060 | ||
85fd4f58 CW |
1061 | #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ |
1062 | ||
a4001f1b PZ |
1063 | enum fb_op_origin { |
1064 | ORIGIN_GTT, | |
1065 | ORIGIN_CPU, | |
1066 | ORIGIN_CS, | |
1067 | ORIGIN_FLIP, | |
74b4ea1e | 1068 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
1069 | }; |
1070 | ||
ab34a7e8 | 1071 | struct intel_fbc { |
25ad93fd PZ |
1072 | /* This is always the inner lock when overlapping with struct_mutex and |
1073 | * it's the outer lock when overlapping with stolen_lock. */ | |
1074 | struct mutex lock; | |
5e59f717 | 1075 | unsigned threshold; |
dbef0f15 PZ |
1076 | unsigned int possible_framebuffer_bits; |
1077 | unsigned int busy_bits; | |
010cf73d | 1078 | unsigned int visible_pipes_mask; |
e35fef21 | 1079 | struct intel_crtc *crtc; |
5c3fe8b0 | 1080 | |
c4213885 | 1081 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
1082 | struct drm_mm_node *compressed_llb; |
1083 | ||
da46f936 RV |
1084 | bool false_color; |
1085 | ||
d029bcad | 1086 | bool enabled; |
0e631adc | 1087 | bool active; |
9adccc60 | 1088 | |
61a585d6 PZ |
1089 | bool underrun_detected; |
1090 | struct work_struct underrun_work; | |
1091 | ||
525a4f93 PZ |
1092 | /* |
1093 | * Due to the atomic rules we can't access some structures without the | |
1094 | * appropriate locking, so we cache information here in order to avoid | |
1095 | * these problems. | |
1096 | */ | |
aaf78d27 | 1097 | struct intel_fbc_state_cache { |
be1e3415 CW |
1098 | struct i915_vma *vma; |
1099 | ||
aaf78d27 PZ |
1100 | struct { |
1101 | unsigned int mode_flags; | |
1102 | uint32_t hsw_bdw_pixel_rate; | |
1103 | } crtc; | |
1104 | ||
1105 | struct { | |
1106 | unsigned int rotation; | |
1107 | int src_w; | |
1108 | int src_h; | |
1109 | bool visible; | |
bf0a5d4b JPH |
1110 | /* |
1111 | * Display surface base address adjustement for | |
1112 | * pageflips. Note that on gen4+ this only adjusts up | |
1113 | * to a tile, offsets within a tile are handled in | |
1114 | * the hw itself (with the TILEOFF register). | |
1115 | */ | |
1116 | int adjusted_x; | |
1117 | int adjusted_y; | |
31d1d3c8 JPH |
1118 | |
1119 | int y; | |
aaf78d27 PZ |
1120 | } plane; |
1121 | ||
1122 | struct { | |
801c8fe8 | 1123 | const struct drm_format_info *format; |
aaf78d27 | 1124 | unsigned int stride; |
aaf78d27 PZ |
1125 | } fb; |
1126 | } state_cache; | |
1127 | ||
525a4f93 PZ |
1128 | /* |
1129 | * This structure contains everything that's relevant to program the | |
1130 | * hardware registers. When we want to figure out if we need to disable | |
1131 | * and re-enable FBC for a new configuration we just check if there's | |
1132 | * something different in the struct. The genx_fbc_activate functions | |
1133 | * are supposed to read from it in order to program the registers. | |
1134 | */ | |
b183b3f1 | 1135 | struct intel_fbc_reg_params { |
be1e3415 CW |
1136 | struct i915_vma *vma; |
1137 | ||
b183b3f1 PZ |
1138 | struct { |
1139 | enum pipe pipe; | |
1140 | enum plane plane; | |
1141 | unsigned int fence_y_offset; | |
1142 | } crtc; | |
1143 | ||
1144 | struct { | |
801c8fe8 | 1145 | const struct drm_format_info *format; |
b183b3f1 | 1146 | unsigned int stride; |
b183b3f1 PZ |
1147 | } fb; |
1148 | ||
1149 | int cfb_size; | |
5654a162 | 1150 | unsigned int gen9_wa_cfb_stride; |
b183b3f1 PZ |
1151 | } params; |
1152 | ||
5c3fe8b0 | 1153 | struct intel_fbc_work { |
128d7356 | 1154 | bool scheduled; |
ca18d51d | 1155 | u32 scheduled_vblank; |
128d7356 | 1156 | struct work_struct work; |
128d7356 | 1157 | } work; |
5c3fe8b0 | 1158 | |
bf6189c6 | 1159 | const char *no_fbc_reason; |
b5e50c3f JB |
1160 | }; |
1161 | ||
fe88d122 | 1162 | /* |
96178eeb VK |
1163 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
1164 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
1165 | * parsing for same resolution. | |
1166 | */ | |
1167 | enum drrs_refresh_rate_type { | |
1168 | DRRS_HIGH_RR, | |
1169 | DRRS_LOW_RR, | |
1170 | DRRS_MAX_RR, /* RR count */ | |
1171 | }; | |
1172 | ||
1173 | enum drrs_support_type { | |
1174 | DRRS_NOT_SUPPORTED = 0, | |
1175 | STATIC_DRRS_SUPPORT = 1, | |
1176 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1177 | }; |
1178 | ||
2807cf69 | 1179 | struct intel_dp; |
96178eeb VK |
1180 | struct i915_drrs { |
1181 | struct mutex mutex; | |
1182 | struct delayed_work work; | |
1183 | struct intel_dp *dp; | |
1184 | unsigned busy_frontbuffer_bits; | |
1185 | enum drrs_refresh_rate_type refresh_rate_type; | |
1186 | enum drrs_support_type type; | |
1187 | }; | |
1188 | ||
a031d709 | 1189 | struct i915_psr { |
f0355c4a | 1190 | struct mutex lock; |
a031d709 RV |
1191 | bool sink_support; |
1192 | bool source_ok; | |
2807cf69 | 1193 | struct intel_dp *enabled; |
7c8f8a70 RV |
1194 | bool active; |
1195 | struct delayed_work work; | |
9ca15301 | 1196 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1197 | bool psr2_support; |
1198 | bool aux_frame_sync; | |
60e5ffe3 | 1199 | bool link_standby; |
97da2ef4 NV |
1200 | bool y_cord_support; |
1201 | bool colorimetry_support; | |
340c93c0 | 1202 | bool alpm; |
424644c2 | 1203 | |
d0d5e0d7 RV |
1204 | void (*enable_source)(struct intel_dp *, |
1205 | const struct intel_crtc_state *); | |
424644c2 RV |
1206 | void (*disable_source)(struct intel_dp *, |
1207 | const struct intel_crtc_state *); | |
49ad316f | 1208 | void (*enable_sink)(struct intel_dp *); |
e3702ac9 | 1209 | void (*activate)(struct intel_dp *); |
2a5db87f | 1210 | void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *); |
3f51e471 | 1211 | }; |
5c3fe8b0 | 1212 | |
3bad0781 | 1213 | enum intel_pch { |
f0350830 | 1214 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 | 1215 | PCH_IBX, /* Ibexpeak PCH */ |
243dec58 VS |
1216 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ |
1217 | PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ | |
e7e7ea20 | 1218 | PCH_SPT, /* Sunrisepoint PCH */ |
23247d71 RV |
1219 | PCH_KBP, /* Kaby Lake PCH */ |
1220 | PCH_CNP, /* Cannon Lake PCH */ | |
40c7ead9 | 1221 | PCH_NOP, |
3bad0781 ZW |
1222 | }; |
1223 | ||
988d6ee8 PZ |
1224 | enum intel_sbi_destination { |
1225 | SBI_ICLK, | |
1226 | SBI_MPHY, | |
1227 | }; | |
1228 | ||
435793df | 1229 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1230 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1231 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
656bfa3a | 1232 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
c99a259b | 1233 | #define QUIRK_INCREASE_T12_DELAY (1<<6) |
af25065b | 1234 | #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) |
b690e96c | 1235 | |
8be48d92 | 1236 | struct intel_fbdev; |
1630fe75 | 1237 | struct intel_fbc_work; |
38651674 | 1238 | |
c2b9152f DV |
1239 | struct intel_gmbus { |
1240 | struct i2c_adapter adapter; | |
3e4d44e0 | 1241 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1242 | u32 force_bit; |
c2b9152f | 1243 | u32 reg0; |
f0f59a00 | 1244 | i915_reg_t gpio_reg; |
c167a6fc | 1245 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1246 | struct drm_i915_private *dev_priv; |
1247 | }; | |
1248 | ||
f4c956ad | 1249 | struct i915_suspend_saved_registers { |
e948e994 | 1250 | u32 saveDSPARB; |
ba8bbcf6 | 1251 | u32 saveFBC_CONTROL; |
1f84e550 | 1252 | u32 saveCACHE_MODE_0; |
1f84e550 | 1253 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1254 | u32 saveSWF0[16]; |
1255 | u32 saveSWF1[16]; | |
85fa792b | 1256 | u32 saveSWF3[3]; |
4b9de737 | 1257 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1258 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1259 | u16 saveGCDGMBUS; |
f4c956ad | 1260 | }; |
c85aa885 | 1261 | |
ddeea5b0 ID |
1262 | struct vlv_s0ix_state { |
1263 | /* GAM */ | |
1264 | u32 wr_watermark; | |
1265 | u32 gfx_prio_ctrl; | |
1266 | u32 arb_mode; | |
1267 | u32 gfx_pend_tlb0; | |
1268 | u32 gfx_pend_tlb1; | |
1269 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1270 | u32 media_max_req_count; | |
1271 | u32 gfx_max_req_count; | |
1272 | u32 render_hwsp; | |
1273 | u32 ecochk; | |
1274 | u32 bsd_hwsp; | |
1275 | u32 blt_hwsp; | |
1276 | u32 tlb_rd_addr; | |
1277 | ||
1278 | /* MBC */ | |
1279 | u32 g3dctl; | |
1280 | u32 gsckgctl; | |
1281 | u32 mbctl; | |
1282 | ||
1283 | /* GCP */ | |
1284 | u32 ucgctl1; | |
1285 | u32 ucgctl3; | |
1286 | u32 rcgctl1; | |
1287 | u32 rcgctl2; | |
1288 | u32 rstctl; | |
1289 | u32 misccpctl; | |
1290 | ||
1291 | /* GPM */ | |
1292 | u32 gfxpause; | |
1293 | u32 rpdeuhwtc; | |
1294 | u32 rpdeuc; | |
1295 | u32 ecobus; | |
1296 | u32 pwrdwnupctl; | |
1297 | u32 rp_down_timeout; | |
1298 | u32 rp_deucsw; | |
1299 | u32 rcubmabdtmr; | |
1300 | u32 rcedata; | |
1301 | u32 spare2gh; | |
1302 | ||
1303 | /* Display 1 CZ domain */ | |
1304 | u32 gt_imr; | |
1305 | u32 gt_ier; | |
1306 | u32 pm_imr; | |
1307 | u32 pm_ier; | |
1308 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1309 | ||
1310 | /* GT SA CZ domain */ | |
1311 | u32 tilectl; | |
1312 | u32 gt_fifoctl; | |
1313 | u32 gtlc_wake_ctrl; | |
1314 | u32 gtlc_survive; | |
1315 | u32 pmwgicz; | |
1316 | ||
1317 | /* Display 2 CZ domain */ | |
1318 | u32 gu_ctl0; | |
1319 | u32 gu_ctl1; | |
9c25210f | 1320 | u32 pcbr; |
ddeea5b0 ID |
1321 | u32 clock_gate_dis2; |
1322 | }; | |
1323 | ||
bf225f20 | 1324 | struct intel_rps_ei { |
679cb6c1 | 1325 | ktime_t ktime; |
bf225f20 CW |
1326 | u32 render_c0; |
1327 | u32 media_c0; | |
31685c25 D |
1328 | }; |
1329 | ||
562d9bae | 1330 | struct intel_rps { |
d4d70aa5 ID |
1331 | /* |
1332 | * work, interrupts_enabled and pm_iir are protected by | |
1333 | * dev_priv->irq_lock | |
1334 | */ | |
c85aa885 | 1335 | struct work_struct work; |
d4d70aa5 | 1336 | bool interrupts_enabled; |
c85aa885 | 1337 | u32 pm_iir; |
59cdb63d | 1338 | |
b20e3cfe | 1339 | /* PM interrupt bits that should never be masked */ |
5dd04556 | 1340 | u32 pm_intrmsk_mbz; |
1800ad25 | 1341 | |
b39fb297 BW |
1342 | /* Frequencies are stored in potentially platform dependent multiples. |
1343 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1344 | * Soft limits are those which are used for the dynamic reclocking done | |
1345 | * by the driver (raise frequencies under heavy loads, and lower for | |
1346 | * lighter loads). Hard limits are those imposed by the hardware. | |
1347 | * | |
1348 | * A distinction is made for overclocking, which is never enabled by | |
1349 | * default, and is considered to be above the hard limit if it's | |
1350 | * possible at all. | |
1351 | */ | |
1352 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1353 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1354 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1355 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1356 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 1357 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 1358 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1359 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1360 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1361 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1362 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1363 | |
8fb55197 CW |
1364 | u8 up_threshold; /* Current %busy required to uplock */ |
1365 | u8 down_threshold; /* Current %busy required to downclock */ | |
1366 | ||
dd75fdc8 CW |
1367 | int last_adj; |
1368 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1369 | ||
c0951f0c | 1370 | bool enabled; |
7b92c1bd CW |
1371 | atomic_t num_waiters; |
1372 | atomic_t boosts; | |
4fc688ce | 1373 | |
bf225f20 | 1374 | /* manual wa residency calculations */ |
e0e8c7cb | 1375 | struct intel_rps_ei ei; |
c85aa885 DV |
1376 | }; |
1377 | ||
37d933fc SAK |
1378 | struct intel_rc6 { |
1379 | bool enabled; | |
1380 | }; | |
1381 | ||
1382 | struct intel_llc_pstate { | |
1383 | bool enabled; | |
1384 | }; | |
1385 | ||
562d9bae SAK |
1386 | struct intel_gen6_power_mgmt { |
1387 | struct intel_rps rps; | |
37d933fc SAK |
1388 | struct intel_rc6 rc6; |
1389 | struct intel_llc_pstate llc_pstate; | |
562d9bae SAK |
1390 | struct delayed_work autoenable_work; |
1391 | }; | |
1392 | ||
1a240d4d DV |
1393 | /* defined intel_pm.c */ |
1394 | extern spinlock_t mchdev_lock; | |
1395 | ||
c85aa885 DV |
1396 | struct intel_ilk_power_mgmt { |
1397 | u8 cur_delay; | |
1398 | u8 min_delay; | |
1399 | u8 max_delay; | |
1400 | u8 fmax; | |
1401 | u8 fstart; | |
1402 | ||
1403 | u64 last_count1; | |
1404 | unsigned long last_time1; | |
1405 | unsigned long chipset_power; | |
1406 | u64 last_count2; | |
5ed0bdf2 | 1407 | u64 last_time2; |
c85aa885 DV |
1408 | unsigned long gfx_power; |
1409 | u8 corr; | |
1410 | ||
1411 | int c_m; | |
1412 | int r_t; | |
1413 | }; | |
1414 | ||
c6cb582e ID |
1415 | struct drm_i915_private; |
1416 | struct i915_power_well; | |
1417 | ||
1418 | struct i915_power_well_ops { | |
1419 | /* | |
1420 | * Synchronize the well's hw state to match the current sw state, for | |
1421 | * example enable/disable it based on the current refcount. Called | |
1422 | * during driver init and resume time, possibly after first calling | |
1423 | * the enable/disable handlers. | |
1424 | */ | |
1425 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1426 | struct i915_power_well *power_well); | |
1427 | /* | |
1428 | * Enable the well and resources that depend on it (for example | |
1429 | * interrupts located on the well). Called after the 0->1 refcount | |
1430 | * transition. | |
1431 | */ | |
1432 | void (*enable)(struct drm_i915_private *dev_priv, | |
1433 | struct i915_power_well *power_well); | |
1434 | /* | |
1435 | * Disable the well and resources that depend on it. Called after | |
1436 | * the 1->0 refcount transition. | |
1437 | */ | |
1438 | void (*disable)(struct drm_i915_private *dev_priv, | |
1439 | struct i915_power_well *power_well); | |
1440 | /* Returns the hw enabled state. */ | |
1441 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1442 | struct i915_power_well *power_well); | |
1443 | }; | |
1444 | ||
a38911a3 WX |
1445 | /* Power well structure for haswell */ |
1446 | struct i915_power_well { | |
c1ca727f | 1447 | const char *name; |
6f3ef5dd | 1448 | bool always_on; |
a38911a3 WX |
1449 | /* power well enable/disable usage count */ |
1450 | int count; | |
bfafe93a ID |
1451 | /* cached hw enabled state */ |
1452 | bool hw_enabled; | |
d8fc70b7 | 1453 | u64 domains; |
01c3faa7 | 1454 | /* unique identifier for this power well */ |
438b8dc4 | 1455 | enum i915_power_well_id id; |
362624c9 ACO |
1456 | /* |
1457 | * Arbitraty data associated with this power well. Platform and power | |
1458 | * well specific. | |
1459 | */ | |
b5565a2e ID |
1460 | union { |
1461 | struct { | |
1462 | enum dpio_phy phy; | |
1463 | } bxt; | |
001bd2cb ID |
1464 | struct { |
1465 | /* Mask of pipes whose IRQ logic is backed by the pw */ | |
1466 | u8 irq_pipe_mask; | |
1467 | /* The pw is backing the VGA functionality */ | |
1468 | bool has_vga:1; | |
b2891eb2 | 1469 | bool has_fuses:1; |
001bd2cb | 1470 | } hsw; |
b5565a2e | 1471 | }; |
c6cb582e | 1472 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1473 | }; |
1474 | ||
83c00f55 | 1475 | struct i915_power_domains { |
baa70707 ID |
1476 | /* |
1477 | * Power wells needed for initialization at driver init and suspend | |
1478 | * time are on. They are kept on until after the first modeset. | |
1479 | */ | |
1480 | bool init_power_on; | |
0d116a29 | 1481 | bool initializing; |
c1ca727f | 1482 | int power_well_count; |
baa70707 | 1483 | |
83c00f55 | 1484 | struct mutex lock; |
1da51581 | 1485 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1486 | struct i915_power_well *power_wells; |
83c00f55 ID |
1487 | }; |
1488 | ||
35a85ac6 | 1489 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1490 | struct intel_l3_parity { |
35a85ac6 | 1491 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1492 | struct work_struct error_work; |
35a85ac6 | 1493 | int which_slice; |
a4da4fa4 DV |
1494 | }; |
1495 | ||
4b5aed62 | 1496 | struct i915_gem_mm { |
4b5aed62 DV |
1497 | /** Memory allocator for GTT stolen memory */ |
1498 | struct drm_mm stolen; | |
92e97d2f PZ |
1499 | /** Protects the usage of the GTT stolen memory allocator. This is |
1500 | * always the inner lock when overlapping with struct_mutex. */ | |
1501 | struct mutex stolen_lock; | |
1502 | ||
f2123818 CW |
1503 | /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ |
1504 | spinlock_t obj_lock; | |
1505 | ||
4b5aed62 DV |
1506 | /** List of all objects in gtt_space. Used to restore gtt |
1507 | * mappings on resume */ | |
1508 | struct list_head bound_list; | |
1509 | /** | |
1510 | * List of objects which are not bound to the GTT (thus | |
fbbd37b3 CW |
1511 | * are idle and not used by the GPU). These objects may or may |
1512 | * not actually have any pages attached. | |
4b5aed62 DV |
1513 | */ |
1514 | struct list_head unbound_list; | |
1515 | ||
275f039d CW |
1516 | /** List of all objects in gtt_space, currently mmaped by userspace. |
1517 | * All objects within this list must also be on bound_list. | |
1518 | */ | |
1519 | struct list_head userfault_list; | |
1520 | ||
fbbd37b3 CW |
1521 | /** |
1522 | * List of objects which are pending destruction. | |
1523 | */ | |
1524 | struct llist_head free_list; | |
1525 | struct work_struct free_work; | |
87701b4b | 1526 | spinlock_t free_lock; |
fbbd37b3 | 1527 | |
66df1014 CW |
1528 | /** |
1529 | * Small stash of WC pages | |
1530 | */ | |
1531 | struct pagevec wc_stash; | |
1532 | ||
4b5aed62 | 1533 | /** Usable portion of the GTT for GEM */ |
c8847387 | 1534 | dma_addr_t stolen_base; /* limited to low memory (32-bit) */ |
4b5aed62 | 1535 | |
465c403c MA |
1536 | /** |
1537 | * tmpfs instance used for shmem backed objects | |
1538 | */ | |
1539 | struct vfsmount *gemfs; | |
1540 | ||
4b5aed62 DV |
1541 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1542 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1543 | ||
2cfcd32a | 1544 | struct notifier_block oom_notifier; |
e87666b5 | 1545 | struct notifier_block vmap_notifier; |
ceabbba5 | 1546 | struct shrinker shrinker; |
4b5aed62 | 1547 | |
4b5aed62 DV |
1548 | /** LRU list of objects with fence regs on them. */ |
1549 | struct list_head fence_list; | |
1550 | ||
8a2421bd CW |
1551 | /** |
1552 | * Workqueue to fault in userptr pages, flushed by the execbuf | |
1553 | * when required but otherwise left to userspace to try again | |
1554 | * on EAGAIN. | |
1555 | */ | |
1556 | struct workqueue_struct *userptr_wq; | |
1557 | ||
94312828 CW |
1558 | u64 unordered_timeline; |
1559 | ||
bdf1e7e3 | 1560 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 1561 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 1562 | |
4b5aed62 DV |
1563 | /** Bit 6 swizzling required for X tiling */ |
1564 | uint32_t bit_6_swizzle_x; | |
1565 | /** Bit 6 swizzling required for Y tiling */ | |
1566 | uint32_t bit_6_swizzle_y; | |
1567 | ||
4b5aed62 | 1568 | /* accounting, useful for userland debugging */ |
c20e8355 | 1569 | spinlock_t object_stat_lock; |
3ef7f228 | 1570 | u64 object_memory; |
4b5aed62 DV |
1571 | u32 object_count; |
1572 | }; | |
1573 | ||
edc3d884 | 1574 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1575 | struct drm_i915_private *i915; |
edc3d884 MK |
1576 | unsigned bytes; |
1577 | unsigned size; | |
1578 | int err; | |
1579 | u8 *buf; | |
1580 | loff_t start; | |
1581 | loff_t pos; | |
1582 | }; | |
1583 | ||
b52992c0 CW |
1584 | #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ |
1585 | #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ | |
1586 | ||
3fe3b030 MK |
1587 | #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ |
1588 | #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ | |
1589 | ||
99584db3 DV |
1590 | struct i915_gpu_error { |
1591 | /* For hangcheck timer */ | |
1592 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1593 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 | 1594 | |
737b1506 | 1595 | struct delayed_work hangcheck_work; |
99584db3 DV |
1596 | |
1597 | /* For reset and error_state handling. */ | |
1598 | spinlock_t lock; | |
1599 | /* Protected by the above dev->gpu_error.lock. */ | |
5a4c6f1b | 1600 | struct i915_gpu_state *first_error; |
094f9a54 | 1601 | |
9db529aa DV |
1602 | atomic_t pending_fb_pin; |
1603 | ||
094f9a54 CW |
1604 | unsigned long missed_irq_rings; |
1605 | ||
1f83fee0 | 1606 | /** |
2ac0f450 | 1607 | * State variable controlling the reset flow and count |
1f83fee0 | 1608 | * |
2ac0f450 | 1609 | * This is a counter which gets incremented when reset is triggered, |
8af29b0c | 1610 | * |
56306c6e | 1611 | * Before the reset commences, the I915_RESET_BACKOFF bit is set |
8af29b0c CW |
1612 | * meaning that any waiters holding onto the struct_mutex should |
1613 | * relinquish the lock immediately in order for the reset to start. | |
2ac0f450 MK |
1614 | * |
1615 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1616 | * set meaning that hardware is terminally sour and there is no | |
1617 | * recovery. All waiters on the reset_queue will be woken when | |
1618 | * that happens. | |
1619 | * | |
1620 | * This counter is used by the wait_seqno code to notice that reset | |
1621 | * event happened and it needs to restart the entire ioctl (since most | |
1622 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1623 | * |
1624 | * This is important for lock-free wait paths, where no contended lock | |
1625 | * naturally enforces the correct ordering between the bail-out of the | |
1626 | * waiter and the gpu reset work code. | |
1f83fee0 | 1627 | */ |
8af29b0c | 1628 | unsigned long reset_count; |
1f83fee0 | 1629 | |
8c185eca CW |
1630 | /** |
1631 | * flags: Control various stages of the GPU reset | |
1632 | * | |
1633 | * #I915_RESET_BACKOFF - When we start a reset, we want to stop any | |
1634 | * other users acquiring the struct_mutex. To do this we set the | |
1635 | * #I915_RESET_BACKOFF bit in the error flags when we detect a reset | |
1636 | * and then check for that bit before acquiring the struct_mutex (in | |
1637 | * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a | |
1638 | * secondary role in preventing two concurrent global reset attempts. | |
1639 | * | |
1640 | * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the | |
1641 | * struct_mutex. We try to acquire the struct_mutex in the reset worker, | |
1642 | * but it may be held by some long running waiter (that we cannot | |
1643 | * interrupt without causing trouble). Once we are ready to do the GPU | |
1644 | * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If | |
1645 | * they already hold the struct_mutex and want to participate they can | |
1646 | * inspect the bit and do the reset directly, otherwise the worker | |
1647 | * waits for the struct_mutex. | |
1648 | * | |
142bc7d9 MT |
1649 | * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to |
1650 | * acquire the struct_mutex to reset an engine, we need an explicit | |
1651 | * flag to prevent two concurrent reset attempts in the same engine. | |
1652 | * As the number of engines continues to grow, allocate the flags from | |
1653 | * the most significant bits. | |
1654 | * | |
8c185eca CW |
1655 | * #I915_WEDGED - If reset fails and we can no longer use the GPU, |
1656 | * we set the #I915_WEDGED bit. Prior to command submission, e.g. | |
1657 | * i915_gem_request_alloc(), this bit is checked and the sequence | |
1658 | * aborted (with -EIO reported to userspace) if set. | |
1659 | */ | |
8af29b0c | 1660 | unsigned long flags; |
8c185eca CW |
1661 | #define I915_RESET_BACKOFF 0 |
1662 | #define I915_RESET_HANDOFF 1 | |
9db529aa | 1663 | #define I915_RESET_MODESET 2 |
8af29b0c | 1664 | #define I915_WEDGED (BITS_PER_LONG - 1) |
142bc7d9 | 1665 | #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) |
1f83fee0 | 1666 | |
702c8f8e MT |
1667 | /** Number of times an engine has been reset */ |
1668 | u32 reset_engine_count[I915_NUM_ENGINES]; | |
1669 | ||
1f15b76f CW |
1670 | /** |
1671 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1672 | * to release the struct_mutex for the reset to procede. | |
1673 | */ | |
1674 | wait_queue_head_t wait_queue; | |
1675 | ||
1f83fee0 DV |
1676 | /** |
1677 | * Waitqueue to signal when the reset has completed. Used by clients | |
1678 | * that wait for dev_priv->mm.wedged to settle. | |
1679 | */ | |
1680 | wait_queue_head_t reset_queue; | |
33196ded | 1681 | |
094f9a54 | 1682 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1683 | unsigned long test_irq_rings; |
99584db3 DV |
1684 | }; |
1685 | ||
b8efb17b ZR |
1686 | enum modeset_restore { |
1687 | MODESET_ON_LID_OPEN, | |
1688 | MODESET_DONE, | |
1689 | MODESET_SUSPENDED, | |
1690 | }; | |
1691 | ||
500ea70d RV |
1692 | #define DP_AUX_A 0x40 |
1693 | #define DP_AUX_B 0x10 | |
1694 | #define DP_AUX_C 0x20 | |
1695 | #define DP_AUX_D 0x30 | |
1696 | ||
11c1b657 XZ |
1697 | #define DDC_PIN_B 0x05 |
1698 | #define DDC_PIN_C 0x04 | |
1699 | #define DDC_PIN_D 0x06 | |
1700 | ||
6acab15a | 1701 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1702 | /* |
1703 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1704 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1705 | * populate this field. | |
1706 | */ | |
1707 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1708 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1709 | |
1710 | uint8_t supports_dvi:1; | |
1711 | uint8_t supports_hdmi:1; | |
1712 | uint8_t supports_dp:1; | |
a98d9c1d | 1713 | uint8_t supports_edp:1; |
500ea70d RV |
1714 | |
1715 | uint8_t alternate_aux_channel; | |
11c1b657 | 1716 | uint8_t alternate_ddc_pin; |
75067dde AK |
1717 | |
1718 | uint8_t dp_boost_level; | |
1719 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1720 | }; |
1721 | ||
bfd7ebda RV |
1722 | enum psr_lines_to_wait { |
1723 | PSR_0_LINES_TO_WAIT = 0, | |
1724 | PSR_1_LINE_TO_WAIT, | |
1725 | PSR_4_LINES_TO_WAIT, | |
1726 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1727 | }; |
1728 | ||
41aa3448 RV |
1729 | struct intel_vbt_data { |
1730 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1731 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1732 | ||
1733 | /* Feature bits */ | |
1734 | unsigned int int_tv_support:1; | |
1735 | unsigned int lvds_dither:1; | |
1736 | unsigned int lvds_vbt:1; | |
1737 | unsigned int int_crt_support:1; | |
1738 | unsigned int lvds_use_ssc:1; | |
1739 | unsigned int display_clock_mode:1; | |
1740 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1741 | unsigned int panel_type:4; |
41aa3448 RV |
1742 | int lvds_ssc_freq; |
1743 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1744 | ||
83a7280e PB |
1745 | enum drrs_support_type drrs_type; |
1746 | ||
6aa23e65 JN |
1747 | struct { |
1748 | int rate; | |
1749 | int lanes; | |
1750 | int preemphasis; | |
1751 | int vswing; | |
06411f08 | 1752 | bool low_vswing; |
6aa23e65 JN |
1753 | bool initialized; |
1754 | bool support; | |
1755 | int bpp; | |
1756 | struct edp_power_seq pps; | |
1757 | } edp; | |
41aa3448 | 1758 | |
bfd7ebda RV |
1759 | struct { |
1760 | bool full_link; | |
1761 | bool require_aux_wakeup; | |
1762 | int idle_frames; | |
1763 | enum psr_lines_to_wait lines_to_wait; | |
1764 | int tp1_wakeup_time; | |
1765 | int tp2_tp3_wakeup_time; | |
1766 | } psr; | |
1767 | ||
f00076d2 JN |
1768 | struct { |
1769 | u16 pwm_freq_hz; | |
39fbc9c8 | 1770 | bool present; |
f00076d2 | 1771 | bool active_low_pwm; |
1de6068e | 1772 | u8 min_brightness; /* min_brightness/255 of max */ |
add03379 | 1773 | u8 controller; /* brightness controller number */ |
9a41e17d | 1774 | enum intel_backlight_type type; |
f00076d2 JN |
1775 | } backlight; |
1776 | ||
d17c5443 SK |
1777 | /* MIPI DSI */ |
1778 | struct { | |
1779 | u16 panel_id; | |
d3b542fc SK |
1780 | struct mipi_config *config; |
1781 | struct mipi_pps_data *pps; | |
46e58320 MC |
1782 | u16 bl_ports; |
1783 | u16 cabc_ports; | |
d3b542fc SK |
1784 | u8 seq_version; |
1785 | u32 size; | |
1786 | u8 *data; | |
8d3ed2f3 | 1787 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1788 | } dsi; |
1789 | ||
41aa3448 RV |
1790 | int crt_ddc_pin; |
1791 | ||
1792 | int child_dev_num; | |
cc998589 | 1793 | struct child_device_config *child_dev; |
6acab15a PZ |
1794 | |
1795 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1796 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1797 | }; |
1798 | ||
77c122bc VS |
1799 | enum intel_ddb_partitioning { |
1800 | INTEL_DDB_PART_1_2, | |
1801 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1802 | }; | |
1803 | ||
1fd527cc VS |
1804 | struct intel_wm_level { |
1805 | bool enable; | |
1806 | uint32_t pri_val; | |
1807 | uint32_t spr_val; | |
1808 | uint32_t cur_val; | |
1809 | uint32_t fbc_val; | |
1810 | }; | |
1811 | ||
820c1980 | 1812 | struct ilk_wm_values { |
609cedef VS |
1813 | uint32_t wm_pipe[3]; |
1814 | uint32_t wm_lp[3]; | |
1815 | uint32_t wm_lp_spr[3]; | |
1816 | uint32_t wm_linetime[3]; | |
1817 | bool enable_fbc_wm; | |
1818 | enum intel_ddb_partitioning partitioning; | |
1819 | }; | |
1820 | ||
114d7dc0 | 1821 | struct g4x_pipe_wm { |
1b31389c | 1822 | uint16_t plane[I915_MAX_PLANES]; |
04548cba | 1823 | uint16_t fbc; |
262cd2e1 | 1824 | }; |
ae80152d | 1825 | |
114d7dc0 | 1826 | struct g4x_sr_wm { |
262cd2e1 | 1827 | uint16_t plane; |
1b31389c | 1828 | uint16_t cursor; |
04548cba | 1829 | uint16_t fbc; |
1b31389c VS |
1830 | }; |
1831 | ||
1832 | struct vlv_wm_ddl_values { | |
1833 | uint8_t plane[I915_MAX_PLANES]; | |
262cd2e1 | 1834 | }; |
ae80152d | 1835 | |
262cd2e1 | 1836 | struct vlv_wm_values { |
114d7dc0 VS |
1837 | struct g4x_pipe_wm pipe[3]; |
1838 | struct g4x_sr_wm sr; | |
1b31389c | 1839 | struct vlv_wm_ddl_values ddl[3]; |
6eb1a681 VS |
1840 | uint8_t level; |
1841 | bool cxsr; | |
0018fda1 VS |
1842 | }; |
1843 | ||
04548cba VS |
1844 | struct g4x_wm_values { |
1845 | struct g4x_pipe_wm pipe[2]; | |
1846 | struct g4x_sr_wm sr; | |
1847 | struct g4x_sr_wm hpll; | |
1848 | bool cxsr; | |
1849 | bool hpll_en; | |
1850 | bool fbc_en; | |
1851 | }; | |
1852 | ||
c193924e | 1853 | struct skl_ddb_entry { |
16160e3d | 1854 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1855 | }; |
1856 | ||
1857 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1858 | { | |
16160e3d | 1859 | return entry->end - entry->start; |
c193924e DL |
1860 | } |
1861 | ||
08db6652 DL |
1862 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1863 | const struct skl_ddb_entry *e2) | |
1864 | { | |
1865 | if (e1->start == e2->start && e1->end == e2->end) | |
1866 | return true; | |
1867 | ||
1868 | return false; | |
1869 | } | |
1870 | ||
c193924e | 1871 | struct skl_ddb_allocation { |
2cd601c6 | 1872 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1873 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1874 | }; |
1875 | ||
2ac96d2a | 1876 | struct skl_wm_values { |
2b4b9f35 | 1877 | unsigned dirty_pipes; |
c193924e | 1878 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1879 | }; |
1880 | ||
1881 | struct skl_wm_level { | |
a62163e9 L |
1882 | bool plane_en; |
1883 | uint16_t plane_res_b; | |
1884 | uint8_t plane_res_l; | |
2ac96d2a PB |
1885 | }; |
1886 | ||
7e452fdb KM |
1887 | /* Stores plane specific WM parameters */ |
1888 | struct skl_wm_params { | |
1889 | bool x_tiled, y_tiled; | |
1890 | bool rc_surface; | |
1891 | uint32_t width; | |
1892 | uint8_t cpp; | |
1893 | uint32_t plane_pixel_rate; | |
1894 | uint32_t y_min_scanlines; | |
1895 | uint32_t plane_bytes_per_line; | |
1896 | uint_fixed_16_16_t plane_blocks_per_line; | |
1897 | uint_fixed_16_16_t y_tile_minimum; | |
1898 | uint32_t linetime_us; | |
1899 | }; | |
1900 | ||
c67a470b | 1901 | /* |
765dab67 PZ |
1902 | * This struct helps tracking the state needed for runtime PM, which puts the |
1903 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1904 | * graphics device works, even register access, so we don't get interrupts nor | |
1905 | * anything else. | |
c67a470b | 1906 | * |
765dab67 PZ |
1907 | * Every piece of our code that needs to actually touch the hardware needs to |
1908 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1909 | * appropriate power domain. | |
a8a8bd54 | 1910 | * |
765dab67 PZ |
1911 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1912 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1913 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1914 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1915 | * |
1916 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1917 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1918 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1919 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1920 | * case it happens. |
c67a470b | 1921 | * |
765dab67 | 1922 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1923 | */ |
5d584b2e | 1924 | struct i915_runtime_pm { |
1f814dac | 1925 | atomic_t wakeref_count; |
5d584b2e | 1926 | bool suspended; |
2aeb7d3a | 1927 | bool irqs_enabled; |
c67a470b PZ |
1928 | }; |
1929 | ||
926321d5 DV |
1930 | enum intel_pipe_crc_source { |
1931 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1932 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1933 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1934 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1935 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1936 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1937 | INTEL_PIPE_CRC_SOURCE_TV, | |
1938 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1939 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1940 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1941 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1942 | INTEL_PIPE_CRC_SOURCE_MAX, |
1943 | }; | |
1944 | ||
8bf1e9f1 | 1945 | struct intel_pipe_crc_entry { |
ac2300d4 | 1946 | uint32_t frame; |
8bf1e9f1 SH |
1947 | uint32_t crc[5]; |
1948 | }; | |
1949 | ||
b2c88f5b | 1950 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1951 | struct intel_pipe_crc { |
d538bbdf DL |
1952 | spinlock_t lock; |
1953 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1954 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1955 | enum intel_pipe_crc_source source; |
d538bbdf | 1956 | int head, tail; |
07144428 | 1957 | wait_queue_head_t wq; |
8c6b709d | 1958 | int skipped; |
8bf1e9f1 SH |
1959 | }; |
1960 | ||
f99d7069 | 1961 | struct i915_frontbuffer_tracking { |
b5add959 | 1962 | spinlock_t lock; |
f99d7069 DV |
1963 | |
1964 | /* | |
1965 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1966 | * scheduled flips. | |
1967 | */ | |
1968 | unsigned busy_bits; | |
1969 | unsigned flip_bits; | |
1970 | }; | |
1971 | ||
7225342a | 1972 | struct i915_wa_reg { |
f0f59a00 | 1973 | i915_reg_t addr; |
7225342a MK |
1974 | u32 value; |
1975 | /* bitmask representing WA bits */ | |
1976 | u32 mask; | |
1977 | }; | |
1978 | ||
d6242aeb | 1979 | #define I915_MAX_WA_REGS 16 |
7225342a MK |
1980 | |
1981 | struct i915_workarounds { | |
1982 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1983 | u32 count; | |
666796da | 1984 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1985 | }; |
1986 | ||
cf9d2890 YZ |
1987 | struct i915_virtual_gpu { |
1988 | bool active; | |
8a4ab66f | 1989 | u32 caps; |
cf9d2890 YZ |
1990 | }; |
1991 | ||
aa363136 MR |
1992 | /* used in computing the new watermarks state */ |
1993 | struct intel_wm_config { | |
1994 | unsigned int num_pipes_active; | |
1995 | bool sprites_enabled; | |
1996 | bool sprites_scaled; | |
1997 | }; | |
1998 | ||
d7965152 RB |
1999 | struct i915_oa_format { |
2000 | u32 format; | |
2001 | int size; | |
2002 | }; | |
2003 | ||
8a3003dd RB |
2004 | struct i915_oa_reg { |
2005 | i915_reg_t addr; | |
2006 | u32 value; | |
2007 | }; | |
2008 | ||
701f8231 LL |
2009 | struct i915_oa_config { |
2010 | char uuid[UUID_STRING_LEN + 1]; | |
2011 | int id; | |
2012 | ||
2013 | const struct i915_oa_reg *mux_regs; | |
2014 | u32 mux_regs_len; | |
2015 | const struct i915_oa_reg *b_counter_regs; | |
2016 | u32 b_counter_regs_len; | |
2017 | const struct i915_oa_reg *flex_regs; | |
2018 | u32 flex_regs_len; | |
2019 | ||
2020 | struct attribute_group sysfs_metric; | |
2021 | struct attribute *attrs[2]; | |
2022 | struct device_attribute sysfs_metric_id; | |
f89823c2 LL |
2023 | |
2024 | atomic_t ref_count; | |
701f8231 LL |
2025 | }; |
2026 | ||
eec688e1 RB |
2027 | struct i915_perf_stream; |
2028 | ||
16d98b31 RB |
2029 | /** |
2030 | * struct i915_perf_stream_ops - the OPs to support a specific stream type | |
2031 | */ | |
eec688e1 | 2032 | struct i915_perf_stream_ops { |
16d98b31 RB |
2033 | /** |
2034 | * @enable: Enables the collection of HW samples, either in response to | |
2035 | * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened | |
2036 | * without `I915_PERF_FLAG_DISABLED`. | |
eec688e1 RB |
2037 | */ |
2038 | void (*enable)(struct i915_perf_stream *stream); | |
2039 | ||
16d98b31 RB |
2040 | /** |
2041 | * @disable: Disables the collection of HW samples, either in response | |
2042 | * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying | |
2043 | * the stream. | |
eec688e1 RB |
2044 | */ |
2045 | void (*disable)(struct i915_perf_stream *stream); | |
2046 | ||
16d98b31 RB |
2047 | /** |
2048 | * @poll_wait: Call poll_wait, passing a wait queue that will be woken | |
eec688e1 RB |
2049 | * once there is something ready to read() for the stream |
2050 | */ | |
2051 | void (*poll_wait)(struct i915_perf_stream *stream, | |
2052 | struct file *file, | |
2053 | poll_table *wait); | |
2054 | ||
16d98b31 RB |
2055 | /** |
2056 | * @wait_unlocked: For handling a blocking read, wait until there is | |
2057 | * something to ready to read() for the stream. E.g. wait on the same | |
d7965152 | 2058 | * wait queue that would be passed to poll_wait(). |
eec688e1 RB |
2059 | */ |
2060 | int (*wait_unlocked)(struct i915_perf_stream *stream); | |
2061 | ||
16d98b31 RB |
2062 | /** |
2063 | * @read: Copy buffered metrics as records to userspace | |
2064 | * **buf**: the userspace, destination buffer | |
2065 | * **count**: the number of bytes to copy, requested by userspace | |
2066 | * **offset**: zero at the start of the read, updated as the read | |
2067 | * proceeds, it represents how many bytes have been copied so far and | |
2068 | * the buffer offset for copying the next record. | |
eec688e1 | 2069 | * |
16d98b31 RB |
2070 | * Copy as many buffered i915 perf samples and records for this stream |
2071 | * to userspace as will fit in the given buffer. | |
eec688e1 | 2072 | * |
16d98b31 RB |
2073 | * Only write complete records; returning -%ENOSPC if there isn't room |
2074 | * for a complete record. | |
eec688e1 | 2075 | * |
16d98b31 RB |
2076 | * Return any error condition that results in a short read such as |
2077 | * -%ENOSPC or -%EFAULT, even though these may be squashed before | |
2078 | * returning to userspace. | |
eec688e1 RB |
2079 | */ |
2080 | int (*read)(struct i915_perf_stream *stream, | |
2081 | char __user *buf, | |
2082 | size_t count, | |
2083 | size_t *offset); | |
2084 | ||
16d98b31 RB |
2085 | /** |
2086 | * @destroy: Cleanup any stream specific resources. | |
eec688e1 RB |
2087 | * |
2088 | * The stream will always be disabled before this is called. | |
2089 | */ | |
2090 | void (*destroy)(struct i915_perf_stream *stream); | |
2091 | }; | |
2092 | ||
16d98b31 RB |
2093 | /** |
2094 | * struct i915_perf_stream - state for a single open stream FD | |
2095 | */ | |
eec688e1 | 2096 | struct i915_perf_stream { |
16d98b31 RB |
2097 | /** |
2098 | * @dev_priv: i915 drm device | |
2099 | */ | |
eec688e1 RB |
2100 | struct drm_i915_private *dev_priv; |
2101 | ||
16d98b31 RB |
2102 | /** |
2103 | * @link: Links the stream into ``&drm_i915_private->streams`` | |
2104 | */ | |
eec688e1 RB |
2105 | struct list_head link; |
2106 | ||
16d98b31 RB |
2107 | /** |
2108 | * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` | |
2109 | * properties given when opening a stream, representing the contents | |
2110 | * of a single sample as read() by userspace. | |
2111 | */ | |
eec688e1 | 2112 | u32 sample_flags; |
16d98b31 RB |
2113 | |
2114 | /** | |
2115 | * @sample_size: Considering the configured contents of a sample | |
2116 | * combined with the required header size, this is the total size | |
2117 | * of a single sample record. | |
2118 | */ | |
d7965152 | 2119 | int sample_size; |
eec688e1 | 2120 | |
16d98b31 RB |
2121 | /** |
2122 | * @ctx: %NULL if measuring system-wide across all contexts or a | |
2123 | * specific context that is being monitored. | |
2124 | */ | |
eec688e1 | 2125 | struct i915_gem_context *ctx; |
16d98b31 RB |
2126 | |
2127 | /** | |
2128 | * @enabled: Whether the stream is currently enabled, considering | |
2129 | * whether the stream was opened in a disabled state and based | |
2130 | * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. | |
2131 | */ | |
eec688e1 RB |
2132 | bool enabled; |
2133 | ||
16d98b31 RB |
2134 | /** |
2135 | * @ops: The callbacks providing the implementation of this specific | |
2136 | * type of configured stream. | |
2137 | */ | |
d7965152 | 2138 | const struct i915_perf_stream_ops *ops; |
701f8231 LL |
2139 | |
2140 | /** | |
2141 | * @oa_config: The OA configuration used by the stream. | |
2142 | */ | |
2143 | struct i915_oa_config *oa_config; | |
d7965152 RB |
2144 | }; |
2145 | ||
16d98b31 RB |
2146 | /** |
2147 | * struct i915_oa_ops - Gen specific implementation of an OA unit stream | |
2148 | */ | |
d7965152 | 2149 | struct i915_oa_ops { |
f89823c2 LL |
2150 | /** |
2151 | * @is_valid_b_counter_reg: Validates register's address for | |
2152 | * programming boolean counters for a particular platform. | |
2153 | */ | |
2154 | bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, | |
2155 | u32 addr); | |
2156 | ||
2157 | /** | |
2158 | * @is_valid_mux_reg: Validates register's address for programming mux | |
2159 | * for a particular platform. | |
2160 | */ | |
2161 | bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
2162 | ||
2163 | /** | |
2164 | * @is_valid_flex_reg: Validates register's address for programming | |
2165 | * flex EU filtering for a particular platform. | |
2166 | */ | |
2167 | bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
2168 | ||
16d98b31 RB |
2169 | /** |
2170 | * @init_oa_buffer: Resets the head and tail pointers of the | |
2171 | * circular buffer for periodic OA reports. | |
2172 | * | |
2173 | * Called when first opening a stream for OA metrics, but also may be | |
2174 | * called in response to an OA buffer overflow or other error | |
2175 | * condition. | |
2176 | * | |
2177 | * Note it may be necessary to clear the full OA buffer here as part of | |
2178 | * maintaining the invariable that new reports must be written to | |
2179 | * zeroed memory for us to be able to reliable detect if an expected | |
2180 | * report has not yet landed in memory. (At least on Haswell the OA | |
2181 | * buffer tail pointer is not synchronized with reports being visible | |
2182 | * to the CPU) | |
2183 | */ | |
d7965152 | 2184 | void (*init_oa_buffer)(struct drm_i915_private *dev_priv); |
16d98b31 | 2185 | |
19f81df2 RB |
2186 | /** |
2187 | * @enable_metric_set: Selects and applies any MUX configuration to set | |
2188 | * up the Boolean and Custom (B/C) counters that are part of the | |
2189 | * counter reports being sampled. May apply system constraints such as | |
16d98b31 RB |
2190 | * disabling EU clock gating as required. |
2191 | */ | |
701f8231 LL |
2192 | int (*enable_metric_set)(struct drm_i915_private *dev_priv, |
2193 | const struct i915_oa_config *oa_config); | |
16d98b31 RB |
2194 | |
2195 | /** | |
2196 | * @disable_metric_set: Remove system constraints associated with using | |
2197 | * the OA unit. | |
2198 | */ | |
d7965152 | 2199 | void (*disable_metric_set)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2200 | |
2201 | /** | |
2202 | * @oa_enable: Enable periodic sampling | |
2203 | */ | |
d7965152 | 2204 | void (*oa_enable)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2205 | |
2206 | /** | |
2207 | * @oa_disable: Disable periodic sampling | |
2208 | */ | |
d7965152 | 2209 | void (*oa_disable)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2210 | |
2211 | /** | |
2212 | * @read: Copy data from the circular OA buffer into a given userspace | |
2213 | * buffer. | |
2214 | */ | |
d7965152 RB |
2215 | int (*read)(struct i915_perf_stream *stream, |
2216 | char __user *buf, | |
2217 | size_t count, | |
2218 | size_t *offset); | |
16d98b31 RB |
2219 | |
2220 | /** | |
19f81df2 | 2221 | * @oa_hw_tail_read: read the OA tail pointer register |
16d98b31 | 2222 | * |
19f81df2 RB |
2223 | * In particular this enables us to share all the fiddly code for |
2224 | * handling the OA unit tail pointer race that affects multiple | |
2225 | * generations. | |
16d98b31 | 2226 | */ |
19f81df2 | 2227 | u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv); |
eec688e1 RB |
2228 | }; |
2229 | ||
49cd97a3 VS |
2230 | struct intel_cdclk_state { |
2231 | unsigned int cdclk, vco, ref; | |
2232 | }; | |
2233 | ||
77fec556 | 2234 | struct drm_i915_private { |
8f460e2c CW |
2235 | struct drm_device drm; |
2236 | ||
efab6d8d | 2237 | struct kmem_cache *objects; |
e20d2ab7 | 2238 | struct kmem_cache *vmas; |
d1b48c1e | 2239 | struct kmem_cache *luts; |
efab6d8d | 2240 | struct kmem_cache *requests; |
52e54209 | 2241 | struct kmem_cache *dependencies; |
c5cf9a91 | 2242 | struct kmem_cache *priorities; |
f4c956ad | 2243 | |
5c969aa7 | 2244 | const struct intel_device_info info; |
f4c956ad | 2245 | |
f4c956ad DV |
2246 | void __iomem *regs; |
2247 | ||
907b28c5 | 2248 | struct intel_uncore uncore; |
f4c956ad | 2249 | |
cf9d2890 YZ |
2250 | struct i915_virtual_gpu vgpu; |
2251 | ||
feddf6e8 | 2252 | struct intel_gvt *gvt; |
0ad35fed | 2253 | |
bd132858 | 2254 | struct intel_huc huc; |
33a732f4 AD |
2255 | struct intel_guc guc; |
2256 | ||
eb805623 DV |
2257 | struct intel_csr csr; |
2258 | ||
5ea6e5e3 | 2259 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 2260 | |
f4c956ad DV |
2261 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
2262 | * controller on different i2c buses. */ | |
2263 | struct mutex gmbus_mutex; | |
2264 | ||
2265 | /** | |
2266 | * Base address of the gmbus and gpio block. | |
2267 | */ | |
2268 | uint32_t gpio_mmio_base; | |
2269 | ||
b6fdd0f2 SS |
2270 | /* MMIO base address for MIPI regs */ |
2271 | uint32_t mipi_mmio_base; | |
2272 | ||
443a389f VS |
2273 | uint32_t psr_mmio_base; |
2274 | ||
44cb734c ID |
2275 | uint32_t pps_mmio_base; |
2276 | ||
28c70f16 DV |
2277 | wait_queue_head_t gmbus_wait_queue; |
2278 | ||
f4c956ad | 2279 | struct pci_dev *bridge_dev; |
3b3f1650 | 2280 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; |
e7af3116 CW |
2281 | /* Context used internally to idle the GPU and setup initial state */ |
2282 | struct i915_gem_context *kernel_context; | |
2283 | /* Context only to be used for injecting preemption commands */ | |
2284 | struct i915_gem_context *preempt_context; | |
51d545d0 | 2285 | struct i915_vma *semaphore; |
f4c956ad | 2286 | |
ba8286fa | 2287 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
2288 | struct resource mch_res; |
2289 | ||
f4c956ad DV |
2290 | /* protects the irq masks */ |
2291 | spinlock_t irq_lock; | |
2292 | ||
f8b79e58 ID |
2293 | bool display_irqs_enabled; |
2294 | ||
9ee32fea DV |
2295 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
2296 | struct pm_qos_request pm_qos; | |
2297 | ||
a580516d VS |
2298 | /* Sideband mailbox protection */ |
2299 | struct mutex sb_lock; | |
f4c956ad DV |
2300 | |
2301 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
2302 | union { |
2303 | u32 irq_mask; | |
2304 | u32 de_irq_mask[I915_MAX_PIPES]; | |
2305 | }; | |
f4c956ad | 2306 | u32 gt_irq_mask; |
f4e9af4f AG |
2307 | u32 pm_imr; |
2308 | u32 pm_ier; | |
a6706b45 | 2309 | u32 pm_rps_events; |
26705e20 | 2310 | u32 pm_guc_events; |
91d181dd | 2311 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 2312 | |
5fcece80 | 2313 | struct i915_hotplug hotplug; |
ab34a7e8 | 2314 | struct intel_fbc fbc; |
439d7ac0 | 2315 | struct i915_drrs drrs; |
f4c956ad | 2316 | struct intel_opregion opregion; |
41aa3448 | 2317 | struct intel_vbt_data vbt; |
f4c956ad | 2318 | |
d9ceb816 JB |
2319 | bool preserve_bios_swizzle; |
2320 | ||
f4c956ad DV |
2321 | /* overlay */ |
2322 | struct intel_overlay *overlay; | |
f4c956ad | 2323 | |
58c68779 | 2324 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 2325 | struct mutex backlight_lock; |
31ad8ec6 | 2326 | |
f4c956ad | 2327 | /* LVDS info */ |
f4c956ad DV |
2328 | bool no_aux_handshake; |
2329 | ||
e39b999a VS |
2330 | /* protects panel power sequencer state */ |
2331 | struct mutex pps_mutex; | |
2332 | ||
f4c956ad | 2333 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
2334 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
2335 | ||
2336 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 2337 | unsigned int skl_preferred_vco_freq; |
49cd97a3 | 2338 | unsigned int max_cdclk_freq; |
8d96561a | 2339 | |
adafdc6f | 2340 | unsigned int max_dotclk_freq; |
e7dc33f3 | 2341 | unsigned int rawclk_freq; |
6bcda4f0 | 2342 | unsigned int hpll_freq; |
bfa7df01 | 2343 | unsigned int czclk_freq; |
f4c956ad | 2344 | |
63911d72 | 2345 | struct { |
bb0f4aab VS |
2346 | /* |
2347 | * The current logical cdclk state. | |
2348 | * See intel_atomic_state.cdclk.logical | |
2349 | * | |
2350 | * For reading holding any crtc lock is sufficient, | |
2351 | * for writing must hold all of them. | |
2352 | */ | |
2353 | struct intel_cdclk_state logical; | |
2354 | /* | |
2355 | * The current actual cdclk state. | |
2356 | * See intel_atomic_state.cdclk.actual | |
2357 | */ | |
2358 | struct intel_cdclk_state actual; | |
2359 | /* The current hardware cdclk state */ | |
49cd97a3 | 2360 | struct intel_cdclk_state hw; |
68b342c9 VS |
2361 | |
2362 | int force_min_cdclk; | |
49cd97a3 | 2363 | } cdclk; |
63911d72 | 2364 | |
645416f5 DV |
2365 | /** |
2366 | * wq - Driver workqueue for GEM. | |
2367 | * | |
2368 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
2369 | * locks, for otherwise the flushing done in the pageflip code will | |
2370 | * result in deadlocks. | |
2371 | */ | |
f4c956ad DV |
2372 | struct workqueue_struct *wq; |
2373 | ||
eda41bdc VS |
2374 | /* ordered wq for modesets */ |
2375 | struct workqueue_struct *modeset_wq; | |
2376 | ||
f4c956ad DV |
2377 | /* Display functions */ |
2378 | struct drm_i915_display_funcs display; | |
2379 | ||
2380 | /* PCH chipset type */ | |
2381 | enum intel_pch pch_type; | |
17a303ec | 2382 | unsigned short pch_id; |
f4c956ad DV |
2383 | |
2384 | unsigned long quirks; | |
2385 | ||
b8efb17b ZR |
2386 | enum modeset_restore modeset_restore; |
2387 | struct mutex modeset_restore_lock; | |
e2c8b870 | 2388 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 2389 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 2390 | |
a7bbbd63 | 2391 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 2392 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 2393 | |
4b5aed62 | 2394 | struct i915_gem_mm mm; |
ad46cb53 CW |
2395 | DECLARE_HASHTABLE(mm_structs, 7); |
2396 | struct mutex mm_lock; | |
8781342d | 2397 | |
4395890a ZW |
2398 | struct intel_ppat ppat; |
2399 | ||
8781342d DV |
2400 | /* Kernel Modesetting */ |
2401 | ||
e2af48c6 VS |
2402 | struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
2403 | struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 | 2404 | |
c4597872 DV |
2405 | #ifdef CONFIG_DEBUG_FS |
2406 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
2407 | #endif | |
2408 | ||
565602d7 | 2409 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
2410 | int num_shared_dpll; |
2411 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 2412 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 2413 | |
fbf6d879 ML |
2414 | /* |
2415 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
2416 | * Must be global rather than per dpll, because on some platforms | |
2417 | * plls share registers. | |
2418 | */ | |
2419 | struct mutex dpll_lock; | |
2420 | ||
565602d7 | 2421 | unsigned int active_crtcs; |
d305e061 VS |
2422 | /* minimum acceptable cdclk for each pipe */ |
2423 | int min_cdclk[I915_MAX_PIPES]; | |
565602d7 | 2424 | |
e4607fcf | 2425 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 2426 | |
7225342a | 2427 | struct i915_workarounds workarounds; |
888b5995 | 2428 | |
f99d7069 DV |
2429 | struct i915_frontbuffer_tracking fb_tracking; |
2430 | ||
eb955eee CW |
2431 | struct intel_atomic_helper { |
2432 | struct llist_head free_list; | |
2433 | struct work_struct free_work; | |
2434 | } atomic_helper; | |
2435 | ||
652c393a | 2436 | u16 orig_clock; |
f97108d1 | 2437 | |
c4804411 | 2438 | bool mchbar_need_disable; |
f97108d1 | 2439 | |
a4da4fa4 DV |
2440 | struct intel_l3_parity l3_parity; |
2441 | ||
59124506 | 2442 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 2443 | u32 edram_cap; |
59124506 | 2444 | |
9f817501 SAK |
2445 | /* |
2446 | * Protects RPS/RC6 register access and PCU communication. | |
2447 | * Must be taken after struct_mutex if nested. Note that | |
2448 | * this lock may be held for long periods of time when | |
2449 | * talking to hw - so only take it when talking to hw! | |
2450 | */ | |
2451 | struct mutex pcu_lock; | |
2452 | ||
562d9bae SAK |
2453 | /* gen6+ GT PM state */ |
2454 | struct intel_gen6_power_mgmt gt_pm; | |
c6a828d3 | 2455 | |
20e4d407 DV |
2456 | /* ilk-only ips/rps state. Everything in here is protected by the global |
2457 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 2458 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 2459 | |
83c00f55 | 2460 | struct i915_power_domains power_domains; |
a38911a3 | 2461 | |
a031d709 | 2462 | struct i915_psr psr; |
3f51e471 | 2463 | |
99584db3 | 2464 | struct i915_gpu_error gpu_error; |
ae681d96 | 2465 | |
c9cddffc JB |
2466 | struct drm_i915_gem_object *vlv_pctx; |
2467 | ||
8be48d92 DA |
2468 | /* list of fbdev register on this device */ |
2469 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 2470 | struct work_struct fbdev_suspend_work; |
e953fd7b CW |
2471 | |
2472 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 2473 | struct drm_property *force_audio_property; |
e3689190 | 2474 | |
58fddc28 | 2475 | /* hda/i915 audio component */ |
51e1d83c | 2476 | struct i915_audio_component *audio_component; |
58fddc28 | 2477 | bool audio_component_registered; |
4a21ef7d LY |
2478 | /** |
2479 | * av_mutex - mutex for audio/video sync | |
2480 | * | |
2481 | */ | |
2482 | struct mutex av_mutex; | |
68b342c9 | 2483 | int audio_power_refcount; |
58fddc28 | 2484 | |
829a0af2 CW |
2485 | struct { |
2486 | struct list_head list; | |
5f09a9c8 CW |
2487 | struct llist_head free_list; |
2488 | struct work_struct free_work; | |
829a0af2 CW |
2489 | |
2490 | /* The hw wants to have a stable context identifier for the | |
2491 | * lifetime of the context (for OA, PASID, faults, etc). | |
2492 | * This is limited in execlists to 21 bits. | |
2493 | */ | |
2494 | struct ida hw_ida; | |
2495 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
2496 | } contexts; | |
f4c956ad | 2497 | |
3e68320e | 2498 | u32 fdi_rx_config; |
68d18ad7 | 2499 | |
c231775c | 2500 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 2501 | u32 chv_phy_control; |
c231775c VS |
2502 | /* |
2503 | * Shadows for CHV DPLL_MD regs to keep the state | |
2504 | * checker somewhat working in the presence hardware | |
2505 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
2506 | */ | |
2507 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 2508 | u32 bxt_phy_grc; |
70722468 | 2509 | |
842f1c8b | 2510 | u32 suspend_count; |
84647cf7 | 2511 | bool power_domains_suspended; |
f4c956ad | 2512 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 2513 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 2514 | |
656d1b89 | 2515 | enum { |
16dcdc4e PZ |
2516 | I915_SAGV_UNKNOWN = 0, |
2517 | I915_SAGV_DISABLED, | |
2518 | I915_SAGV_ENABLED, | |
2519 | I915_SAGV_NOT_CONTROLLED | |
2520 | } sagv_status; | |
656d1b89 | 2521 | |
53615a5e VS |
2522 | struct { |
2523 | /* | |
2524 | * Raw watermark latency values: | |
2525 | * in 0.1us units for WM0, | |
2526 | * in 0.5us units for WM1+. | |
2527 | */ | |
2528 | /* primary */ | |
2529 | uint16_t pri_latency[5]; | |
2530 | /* sprite */ | |
2531 | uint16_t spr_latency[5]; | |
2532 | /* cursor */ | |
2533 | uint16_t cur_latency[5]; | |
2af30a5c PB |
2534 | /* |
2535 | * Raw watermark memory latency values | |
2536 | * for SKL for all 8 levels | |
2537 | * in 1us units. | |
2538 | */ | |
2539 | uint16_t skl_latency[8]; | |
609cedef VS |
2540 | |
2541 | /* current hardware state */ | |
2d41c0b5 PB |
2542 | union { |
2543 | struct ilk_wm_values hw; | |
2544 | struct skl_wm_values skl_hw; | |
0018fda1 | 2545 | struct vlv_wm_values vlv; |
04548cba | 2546 | struct g4x_wm_values g4x; |
2d41c0b5 | 2547 | }; |
58590c14 VS |
2548 | |
2549 | uint8_t max_level; | |
ed4a6a7c MR |
2550 | |
2551 | /* | |
2552 | * Should be held around atomic WM register writing; also | |
2553 | * protects * intel_crtc->wm.active and | |
2554 | * cstate->wm.need_postvbl_update. | |
2555 | */ | |
2556 | struct mutex wm_mutex; | |
279e99d7 MR |
2557 | |
2558 | /* | |
2559 | * Set during HW readout of watermarks/DDB. Some platforms | |
2560 | * need to know when we're still using BIOS-provided values | |
2561 | * (which we don't fully trust). | |
2562 | */ | |
2563 | bool distrust_bios_wm; | |
53615a5e VS |
2564 | } wm; |
2565 | ||
ad1443f0 | 2566 | struct i915_runtime_pm runtime_pm; |
8a187455 | 2567 | |
eec688e1 RB |
2568 | struct { |
2569 | bool initialized; | |
d7965152 | 2570 | |
442b8c06 | 2571 | struct kobject *metrics_kobj; |
ccdf6341 | 2572 | struct ctl_table_header *sysctl_header; |
442b8c06 | 2573 | |
f89823c2 LL |
2574 | /* |
2575 | * Lock associated with adding/modifying/removing OA configs | |
2576 | * in dev_priv->perf.metrics_idr. | |
2577 | */ | |
2578 | struct mutex metrics_lock; | |
2579 | ||
2580 | /* | |
2581 | * List of dynamic configurations, you need to hold | |
2582 | * dev_priv->perf.metrics_lock to access it. | |
2583 | */ | |
2584 | struct idr metrics_idr; | |
2585 | ||
2586 | /* | |
2587 | * Lock associated with anything below within this structure | |
2588 | * except exclusive_stream. | |
2589 | */ | |
eec688e1 RB |
2590 | struct mutex lock; |
2591 | struct list_head streams; | |
8a3003dd RB |
2592 | |
2593 | struct { | |
f89823c2 LL |
2594 | /* |
2595 | * The stream currently using the OA unit. If accessed | |
2596 | * outside a syscall associated to its file | |
2597 | * descriptor, you need to hold | |
2598 | * dev_priv->drm.struct_mutex. | |
2599 | */ | |
d7965152 RB |
2600 | struct i915_perf_stream *exclusive_stream; |
2601 | ||
2602 | u32 specific_ctx_id; | |
d7965152 RB |
2603 | |
2604 | struct hrtimer poll_check_timer; | |
2605 | wait_queue_head_t poll_wq; | |
2606 | bool pollin; | |
2607 | ||
712122ea RB |
2608 | /** |
2609 | * For rate limiting any notifications of spurious | |
2610 | * invalid OA reports | |
2611 | */ | |
2612 | struct ratelimit_state spurious_report_rs; | |
2613 | ||
d7965152 RB |
2614 | bool periodic; |
2615 | int period_exponent; | |
155e941f | 2616 | int timestamp_frequency; |
d7965152 | 2617 | |
701f8231 | 2618 | struct i915_oa_config test_config; |
d7965152 RB |
2619 | |
2620 | struct { | |
2621 | struct i915_vma *vma; | |
2622 | u8 *vaddr; | |
19f81df2 | 2623 | u32 last_ctx_id; |
d7965152 RB |
2624 | int format; |
2625 | int format_size; | |
f279020a | 2626 | |
0dd860cf RB |
2627 | /** |
2628 | * Locks reads and writes to all head/tail state | |
2629 | * | |
2630 | * Consider: the head and tail pointer state | |
2631 | * needs to be read consistently from a hrtimer | |
2632 | * callback (atomic context) and read() fop | |
2633 | * (user context) with tail pointer updates | |
2634 | * happening in atomic context and head updates | |
2635 | * in user context and the (unlikely) | |
2636 | * possibility of read() errors needing to | |
2637 | * reset all head/tail state. | |
2638 | * | |
2639 | * Note: Contention or performance aren't | |
2640 | * currently a significant concern here | |
2641 | * considering the relatively low frequency of | |
2642 | * hrtimer callbacks (5ms period) and that | |
2643 | * reads typically only happen in response to a | |
2644 | * hrtimer event and likely complete before the | |
2645 | * next callback. | |
2646 | * | |
2647 | * Note: This lock is not held *while* reading | |
2648 | * and copying data to userspace so the value | |
2649 | * of head observed in htrimer callbacks won't | |
2650 | * represent any partial consumption of data. | |
2651 | */ | |
2652 | spinlock_t ptr_lock; | |
2653 | ||
2654 | /** | |
2655 | * One 'aging' tail pointer and one 'aged' | |
2656 | * tail pointer ready to used for reading. | |
2657 | * | |
2658 | * Initial values of 0xffffffff are invalid | |
2659 | * and imply that an update is required | |
2660 | * (and should be ignored by an attempted | |
2661 | * read) | |
2662 | */ | |
2663 | struct { | |
2664 | u32 offset; | |
2665 | } tails[2]; | |
2666 | ||
2667 | /** | |
2668 | * Index for the aged tail ready to read() | |
2669 | * data up to. | |
2670 | */ | |
2671 | unsigned int aged_tail_idx; | |
2672 | ||
2673 | /** | |
2674 | * A monotonic timestamp for when the current | |
2675 | * aging tail pointer was read; used to | |
2676 | * determine when it is old enough to trust. | |
2677 | */ | |
2678 | u64 aging_timestamp; | |
2679 | ||
f279020a RB |
2680 | /** |
2681 | * Although we can always read back the head | |
2682 | * pointer register, we prefer to avoid | |
2683 | * trusting the HW state, just to avoid any | |
2684 | * risk that some hardware condition could | |
2685 | * somehow bump the head pointer unpredictably | |
2686 | * and cause us to forward the wrong OA buffer | |
2687 | * data to userspace. | |
2688 | */ | |
2689 | u32 head; | |
d7965152 RB |
2690 | } oa_buffer; |
2691 | ||
2692 | u32 gen7_latched_oastatus1; | |
19f81df2 RB |
2693 | u32 ctx_oactxctrl_offset; |
2694 | u32 ctx_flexeu0_offset; | |
2695 | ||
2696 | /** | |
2697 | * The RPT_ID/reason field for Gen8+ includes a bit | |
2698 | * to determine if the CTX ID in the report is valid | |
2699 | * but the specific bit differs between Gen 8 and 9 | |
2700 | */ | |
2701 | u32 gen8_valid_ctx_bit; | |
d7965152 RB |
2702 | |
2703 | struct i915_oa_ops ops; | |
2704 | const struct i915_oa_format *oa_formats; | |
8a3003dd | 2705 | } oa; |
eec688e1 RB |
2706 | } perf; |
2707 | ||
a83014d3 OM |
2708 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2709 | struct { | |
821ed7df | 2710 | void (*resume)(struct drm_i915_private *); |
117897f4 | 2711 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 | 2712 | |
73cb9701 CW |
2713 | struct list_head timelines; |
2714 | struct i915_gem_timeline global_timeline; | |
28176ef4 | 2715 | u32 active_requests; |
73cb9701 | 2716 | |
67d97da3 CW |
2717 | /** |
2718 | * Is the GPU currently considered idle, or busy executing | |
2719 | * userspace requests? Whilst idle, we allow runtime power | |
2720 | * management to power down the hardware and display clocks. | |
2721 | * In order to reduce the effect on performance, there | |
2722 | * is a slight delay before we do so. | |
2723 | */ | |
67d97da3 CW |
2724 | bool awake; |
2725 | ||
2726 | /** | |
2727 | * We leave the user IRQ off as much as possible, | |
2728 | * but this means that requests will finish and never | |
2729 | * be retired once the system goes idle. Set a timer to | |
2730 | * fire periodically while the ring is running. When it | |
2731 | * fires, go retire requests. | |
2732 | */ | |
2733 | struct delayed_work retire_work; | |
2734 | ||
2735 | /** | |
2736 | * When we detect an idle GPU, we want to turn on | |
2737 | * powersaving features. So once we see that there | |
2738 | * are no more requests outstanding and no more | |
2739 | * arrive within a small period of time, we fire | |
2740 | * off the idle_work. | |
2741 | */ | |
2742 | struct delayed_work idle_work; | |
de867c20 CW |
2743 | |
2744 | ktime_t last_init_time; | |
a83014d3 OM |
2745 | } gt; |
2746 | ||
3be60de9 VS |
2747 | /* perform PHY state sanity checks? */ |
2748 | bool chv_phy_assert[2]; | |
2749 | ||
a3a8986c MK |
2750 | bool ipc_enabled; |
2751 | ||
febaeb48 AM |
2752 | /* Hack to bypass TMDS_OE write on DP->HDMI dongle */ |
2753 | bool bypass_tmds_oe; | |
2754 | ||
f9318941 PD |
2755 | /* Used to save the pipe-to-encoder mapping for audio */ |
2756 | struct intel_encoder *av_enc_map[I915_MAX_PIPES]; | |
0bdf5a05 | 2757 | |
eef57324 JA |
2758 | /* necessary resource sharing with HDMI LPE audio driver. */ |
2759 | struct { | |
2760 | struct platform_device *platdev; | |
2761 | int irq; | |
2762 | } lpe_audio; | |
2763 | ||
bdf1e7e3 DV |
2764 | /* |
2765 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2766 | * will be rejected. Instead look for a better place. | |
2767 | */ | |
77fec556 | 2768 | }; |
1da177e4 | 2769 | |
2c1792a1 CW |
2770 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2771 | { | |
091387c1 | 2772 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2773 | } |
2774 | ||
c49d13ee | 2775 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2776 | { |
c49d13ee | 2777 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2778 | } |
2779 | ||
33a732f4 AD |
2780 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2781 | { | |
2782 | return container_of(guc, struct drm_i915_private, guc); | |
2783 | } | |
2784 | ||
50beba55 AH |
2785 | static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) |
2786 | { | |
2787 | return container_of(huc, struct drm_i915_private, huc); | |
2788 | } | |
2789 | ||
b4ac5afc | 2790 | /* Simple iterator over all initialised engines */ |
3b3f1650 AG |
2791 | #define for_each_engine(engine__, dev_priv__, id__) \ |
2792 | for ((id__) = 0; \ | |
2793 | (id__) < I915_NUM_ENGINES; \ | |
2794 | (id__)++) \ | |
2795 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) | |
c3232b18 DG |
2796 | |
2797 | /* Iterator over subset of engines selected by mask */ | |
bafb0fce CW |
2798 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
2799 | for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ | |
3b3f1650 | 2800 | tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) |
ee4b6faf | 2801 | |
b1d7e4b4 WF |
2802 | enum hdmi_force_audio { |
2803 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2804 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2805 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2806 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2807 | }; | |
2808 | ||
190d6cd5 | 2809 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2810 | |
a071fa00 DV |
2811 | /* |
2812 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2813 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2814 | * doesn't mean that the hw necessarily already scans it out, but that any |
2815 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2816 | * | |
2817 | * We have one bit per pipe and per scanout plane type. | |
2818 | */ | |
d1b9d039 SAK |
2819 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2820 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2821 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2822 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2823 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2824 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2825 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2826 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2827 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2828 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2829 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2830 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2831 | |
85d1225e DG |
2832 | /* |
2833 | * Optimised SGL iterator for GEM objects | |
2834 | */ | |
2835 | static __always_inline struct sgt_iter { | |
2836 | struct scatterlist *sgp; | |
2837 | union { | |
2838 | unsigned long pfn; | |
2839 | dma_addr_t dma; | |
2840 | }; | |
2841 | unsigned int curr; | |
2842 | unsigned int max; | |
2843 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2844 | struct sgt_iter s = { .sgp = sgl }; | |
2845 | ||
2846 | if (s.sgp) { | |
2847 | s.max = s.curr = s.sgp->offset; | |
2848 | s.max += s.sgp->length; | |
2849 | if (dma) | |
2850 | s.dma = sg_dma_address(s.sgp); | |
2851 | else | |
2852 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2853 | } | |
2854 | ||
2855 | return s; | |
2856 | } | |
2857 | ||
96d77634 CW |
2858 | static inline struct scatterlist *____sg_next(struct scatterlist *sg) |
2859 | { | |
2860 | ++sg; | |
2861 | if (unlikely(sg_is_chain(sg))) | |
2862 | sg = sg_chain_ptr(sg); | |
2863 | return sg; | |
2864 | } | |
2865 | ||
63d15326 DG |
2866 | /** |
2867 | * __sg_next - return the next scatterlist entry in a list | |
2868 | * @sg: The current sg entry | |
2869 | * | |
2870 | * Description: | |
2871 | * If the entry is the last, return NULL; otherwise, step to the next | |
2872 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2873 | * otherwise just return the pointer to the current element. | |
2874 | **/ | |
2875 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2876 | { | |
2877 | #ifdef CONFIG_DEBUG_SG | |
2878 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2879 | #endif | |
96d77634 | 2880 | return sg_is_last(sg) ? NULL : ____sg_next(sg); |
63d15326 DG |
2881 | } |
2882 | ||
85d1225e DG |
2883 | /** |
2884 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2885 | * @__dmap: DMA address (output) | |
2886 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2887 | * @__sgt: sg_table to iterate over (input) | |
2888 | */ | |
2889 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2890 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2891 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
e60b36f7 CW |
2892 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ |
2893 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0) | |
85d1225e DG |
2894 | |
2895 | /** | |
2896 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2897 | * @__pp: page pointer (output) | |
2898 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2899 | * @__sgt: sg_table to iterate over (input) | |
2900 | */ | |
2901 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2902 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2903 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2904 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
e60b36f7 CW |
2905 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ |
2906 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0) | |
a071fa00 | 2907 | |
a5c08166 MA |
2908 | static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg) |
2909 | { | |
2910 | unsigned int page_sizes; | |
2911 | ||
2912 | page_sizes = 0; | |
2913 | while (sg) { | |
2914 | GEM_BUG_ON(sg->offset); | |
2915 | GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE)); | |
2916 | page_sizes |= sg->length; | |
2917 | sg = __sg_next(sg); | |
2918 | } | |
2919 | ||
2920 | return page_sizes; | |
2921 | } | |
2922 | ||
5602452e TU |
2923 | static inline unsigned int i915_sg_segment_size(void) |
2924 | { | |
2925 | unsigned int size = swiotlb_max_segment(); | |
2926 | ||
2927 | if (size == 0) | |
2928 | return SCATTERLIST_MAX_SEGMENT; | |
2929 | ||
2930 | size = rounddown(size, PAGE_SIZE); | |
2931 | /* swiotlb_max_segment_size can return 1 byte when it means one page. */ | |
2932 | if (size < PAGE_SIZE) | |
2933 | size = PAGE_SIZE; | |
2934 | ||
2935 | return size; | |
2936 | } | |
2937 | ||
5ca43ef0 TU |
2938 | static inline const struct intel_device_info * |
2939 | intel_info(const struct drm_i915_private *dev_priv) | |
2940 | { | |
2941 | return &dev_priv->info; | |
2942 | } | |
2943 | ||
2944 | #define INTEL_INFO(dev_priv) intel_info((dev_priv)) | |
50a0bc90 | 2945 | |
55b8f2a7 | 2946 | #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) |
50a0bc90 | 2947 | #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) |
cae5852d | 2948 | |
e87a005d | 2949 | #define REVID_FOREVER 0xff |
4805fe82 | 2950 | #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) |
ac657f64 TU |
2951 | |
2952 | #define GEN_FOREVER (0) | |
fe52e597 JL |
2953 | |
2954 | #define INTEL_GEN_MASK(s, e) ( \ | |
2955 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ | |
2956 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ | |
2957 | GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ | |
2958 | (s) != GEN_FOREVER ? (s) - 1 : 0) \ | |
2959 | ) | |
2960 | ||
ac657f64 TU |
2961 | /* |
2962 | * Returns true if Gen is in inclusive range [Start, End]. | |
2963 | * | |
2964 | * Use GEN_FOREVER for unbound start and or end. | |
2965 | */ | |
fe52e597 JL |
2966 | #define IS_GEN(dev_priv, s, e) \ |
2967 | (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) | |
ac657f64 | 2968 | |
e87a005d JN |
2969 | /* |
2970 | * Return true if revision is in range [since,until] inclusive. | |
2971 | * | |
2972 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2973 | */ | |
2974 | #define IS_REVID(p, since, until) \ | |
2975 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2976 | ||
ae7617f0 | 2977 | #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) |
5a127a8c TU |
2978 | |
2979 | #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) | |
2980 | #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) | |
2981 | #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) | |
2982 | #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) | |
2983 | #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) | |
2984 | #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) | |
2985 | #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) | |
2986 | #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) | |
2987 | #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) | |
2988 | #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) | |
2989 | #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) | |
2990 | #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) | |
f69c11ae | 2991 | #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) |
50a0bc90 TU |
2992 | #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) |
2993 | #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) | |
5a127a8c TU |
2994 | #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) |
2995 | #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) | |
50a0bc90 | 2996 | #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) |
5a127a8c | 2997 | #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) |
18b53818 LL |
2998 | #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ |
2999 | (dev_priv)->info.gt == 1) | |
5a127a8c TU |
3000 | #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) |
3001 | #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) | |
3002 | #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) | |
3003 | #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) | |
3004 | #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) | |
3005 | #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) | |
3006 | #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) | |
3007 | #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) | |
3008 | #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) | |
3009 | #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) | |
646d5772 | 3010 | #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) |
50a0bc90 TU |
3011 | #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ |
3012 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) | |
3013 | #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
3014 | ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ | |
3015 | (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ | |
3016 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) | |
ebb72aad | 3017 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
3018 | #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ |
3019 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe) | |
3020 | #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
18b53818 | 3021 | (dev_priv)->info.gt == 3) |
50a0bc90 TU |
3022 | #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ |
3023 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) | |
3024 | #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ | |
18b53818 | 3025 | (dev_priv)->info.gt == 3) |
9bbfd20a | 3026 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
3027 | #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ |
3028 | INTEL_DEVID(dev_priv) == 0x0A1E) | |
3029 | #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ | |
3030 | INTEL_DEVID(dev_priv) == 0x1913 || \ | |
3031 | INTEL_DEVID(dev_priv) == 0x1916 || \ | |
3032 | INTEL_DEVID(dev_priv) == 0x1921 || \ | |
3033 | INTEL_DEVID(dev_priv) == 0x1926) | |
3034 | #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ | |
3035 | INTEL_DEVID(dev_priv) == 0x1915 || \ | |
3036 | INTEL_DEVID(dev_priv) == 0x191E) | |
3037 | #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ | |
3038 | INTEL_DEVID(dev_priv) == 0x5913 || \ | |
3039 | INTEL_DEVID(dev_priv) == 0x5916 || \ | |
3040 | INTEL_DEVID(dev_priv) == 0x5921 || \ | |
3041 | INTEL_DEVID(dev_priv) == 0x5926) | |
3042 | #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ | |
3043 | INTEL_DEVID(dev_priv) == 0x5915 || \ | |
3044 | INTEL_DEVID(dev_priv) == 0x591E) | |
19f81df2 | 3045 | #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 3046 | (dev_priv)->info.gt == 2) |
50a0bc90 | 3047 | #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 3048 | (dev_priv)->info.gt == 3) |
50a0bc90 | 3049 | #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 3050 | (dev_priv)->info.gt == 4) |
3891589e | 3051 | #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
18b53818 | 3052 | (dev_priv)->info.gt == 2) |
3891589e | 3053 | #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
18b53818 | 3054 | (dev_priv)->info.gt == 3) |
da411a48 RV |
3055 | #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
3056 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) | |
22ea4f35 LL |
3057 | #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
3058 | (dev_priv)->info.gt == 2) | |
7a58bad0 | 3059 | |
c007fb4a | 3060 | #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) |
cae5852d | 3061 | |
ef712bb4 JN |
3062 | #define SKL_REVID_A0 0x0 |
3063 | #define SKL_REVID_B0 0x1 | |
3064 | #define SKL_REVID_C0 0x2 | |
3065 | #define SKL_REVID_D0 0x3 | |
3066 | #define SKL_REVID_E0 0x4 | |
3067 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
3068 | #define SKL_REVID_G0 0x6 |
3069 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 3070 | |
e87a005d JN |
3071 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
3072 | ||
ef712bb4 | 3073 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 3074 | #define BXT_REVID_A1 0x1 |
ef712bb4 | 3075 | #define BXT_REVID_B0 0x3 |
a3f79ca6 | 3076 | #define BXT_REVID_B_LAST 0x8 |
ef712bb4 | 3077 | #define BXT_REVID_C0 0x9 |
6c74c87f | 3078 | |
e2d214ae TU |
3079 | #define IS_BXT_REVID(dev_priv, since, until) \ |
3080 | (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) | |
e87a005d | 3081 | |
c033a37c MK |
3082 | #define KBL_REVID_A0 0x0 |
3083 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
3084 | #define KBL_REVID_C0 0x2 |
3085 | #define KBL_REVID_D0 0x3 | |
3086 | #define KBL_REVID_E0 0x4 | |
c033a37c | 3087 | |
0853723b TU |
3088 | #define IS_KBL_REVID(dev_priv, since, until) \ |
3089 | (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
c033a37c | 3090 | |
f4f4b59b ACO |
3091 | #define GLK_REVID_A0 0x0 |
3092 | #define GLK_REVID_A1 0x1 | |
3093 | ||
3094 | #define IS_GLK_REVID(dev_priv, since, until) \ | |
3095 | (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
3096 | ||
3c2e0fd9 PZ |
3097 | #define CNL_REVID_A0 0x0 |
3098 | #define CNL_REVID_B0 0x1 | |
e4ffc83d | 3099 | #define CNL_REVID_C0 0x2 |
3c2e0fd9 PZ |
3100 | |
3101 | #define IS_CNL_REVID(p, since, until) \ | |
3102 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) | |
3103 | ||
85436696 JB |
3104 | /* |
3105 | * The genX designation typically refers to the render engine, so render | |
3106 | * capability related checks should use IS_GEN, while display and other checks | |
3107 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
3108 | * chips, etc.). | |
3109 | */ | |
5db94019 TU |
3110 | #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) |
3111 | #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) | |
3112 | #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) | |
3113 | #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) | |
3114 | #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) | |
3115 | #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) | |
3116 | #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) | |
3117 | #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) | |
413f3c19 | 3118 | #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) |
cae5852d | 3119 | |
8727dc09 | 3120 | #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) |
b976dc53 RV |
3121 | #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) |
3122 | #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) | |
3e4274f8 | 3123 | |
a19d6ff2 TU |
3124 | #define ENGINE_MASK(id) BIT(id) |
3125 | #define RENDER_RING ENGINE_MASK(RCS) | |
3126 | #define BSD_RING ENGINE_MASK(VCS) | |
3127 | #define BLT_RING ENGINE_MASK(BCS) | |
3128 | #define VEBOX_RING ENGINE_MASK(VECS) | |
3129 | #define BSD2_RING ENGINE_MASK(VCS2) | |
3130 | #define ALL_ENGINES (~0) | |
3131 | ||
3132 | #define HAS_ENGINE(dev_priv, id) \ | |
0031fb96 | 3133 | (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
3134 | |
3135 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
3136 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
3137 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
3138 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
3139 | ||
0031fb96 TU |
3140 | #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) |
3141 | #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) | |
3142 | #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) | |
8652744b TU |
3143 | #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ |
3144 | IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) | |
cae5852d | 3145 | |
0031fb96 | 3146 | #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) |
1d2a314c | 3147 | |
0031fb96 TU |
3148 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ |
3149 | ((dev_priv)->info.has_logical_ring_contexts) | |
4f044a88 MW |
3150 | #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) |
3151 | #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) | |
3152 | #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3) | |
a5c08166 MA |
3153 | #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ |
3154 | GEM_BUG_ON((sizes) == 0); \ | |
3155 | ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ | |
3156 | }) | |
0031fb96 TU |
3157 | |
3158 | #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) | |
3159 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ | |
3160 | ((dev_priv)->info.overlay_needs_physical) | |
cae5852d | 3161 | |
b45305fc | 3162 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2a307c2e | 3163 | #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
06e668ac MK |
3164 | |
3165 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 | 3166 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
f2254d29 | 3167 | (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) |
185c66e5 | 3168 | |
4e6b788c DV |
3169 | /* |
3170 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
3171 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
3172 | * legacy irq no. is shared with another device. The kernel then disables that | |
3173 | * interrupt source and so prevents the other device from working properly. | |
309bd8ed VS |
3174 | * |
3175 | * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX | |
3176 | * interrupts. | |
4e6b788c | 3177 | */ |
309bd8ed VS |
3178 | #define HAS_AUX_IRQ(dev_priv) true |
3179 | #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) | |
b45305fc | 3180 | |
cae5852d ZN |
3181 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
3182 | * rows, which changed the alignment requirements and fence programming. | |
3183 | */ | |
50a0bc90 TU |
3184 | #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ |
3185 | !(IS_I915G(dev_priv) || \ | |
3186 | IS_I915GM(dev_priv))) | |
56b857a5 TU |
3187 | #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) |
3188 | #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) | |
cae5852d | 3189 | |
56b857a5 | 3190 | #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) |
56b857a5 | 3191 | #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) |
024faac7 | 3192 | #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7) |
cae5852d | 3193 | |
50a0bc90 | 3194 | #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) |
f5adf94e | 3195 | |
56b857a5 | 3196 | #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) |
0c9b3715 | 3197 | |
56b857a5 TU |
3198 | #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) |
3199 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) | |
3200 | #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) | |
3201 | #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) | |
3202 | #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) | |
affa9354 | 3203 | |
56b857a5 | 3204 | #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) |
eb805623 | 3205 | |
6772ffe0 | 3206 | #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) |
dfc5148f JL |
3207 | #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) |
3208 | ||
e57f1c02 MK |
3209 | #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) |
3210 | ||
1a3d1898 DG |
3211 | /* |
3212 | * For now, anything with a GuC requires uCode loading, and then supports | |
3213 | * command submission once loaded. But these are logically independent | |
3214 | * properties, so we have separate macros to test them. | |
3215 | */ | |
4805fe82 | 3216 | #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) |
f8a58d63 | 3217 | #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) |
4805fe82 TU |
3218 | #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
3219 | #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) | |
bd132858 | 3220 | #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
33a732f4 | 3221 | |
4805fe82 | 3222 | #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) |
a9ed33ca | 3223 | |
4805fe82 | 3224 | #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) |
33e141ed | 3225 | |
c5e855d0 | 3226 | #define INTEL_PCH_DEVICE_ID_MASK 0xff80 |
17a303ec PZ |
3227 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3228 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
3229 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
3230 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
3231 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
c5e855d0 VS |
3232 | #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 |
3233 | #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 | |
e7e7ea20 S |
3234 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
3235 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
c5e855d0 | 3236 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 |
7b22b8c4 | 3237 | #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 |
ec7e0bb3 | 3238 | #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 |
30c964a6 | 3239 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 3240 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 3241 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 3242 | |
6e266956 | 3243 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) |
7b22b8c4 | 3244 | #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) |
ec7e0bb3 DP |
3245 | #define HAS_PCH_CNP_LP(dev_priv) \ |
3246 | ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) | |
6e266956 TU |
3247 | #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) |
3248 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) | |
3249 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) | |
4f8036a2 | 3250 | #define HAS_PCH_LPT_LP(dev_priv) \ |
c5e855d0 VS |
3251 | ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ |
3252 | (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) | |
4f8036a2 | 3253 | #define HAS_PCH_LPT_H(dev_priv) \ |
c5e855d0 VS |
3254 | ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ |
3255 | (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE) | |
6e266956 TU |
3256 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) |
3257 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) | |
3258 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) | |
3259 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) | |
cae5852d | 3260 | |
49cff963 | 3261 | #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) |
5fafe292 | 3262 | |
ff15947e | 3263 | #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) |
6389dd83 | 3264 | |
040d2baa | 3265 | /* DPF == dynamic parity feature */ |
3c9192bc | 3266 | #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) |
50a0bc90 TU |
3267 | #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ |
3268 | 2 : HAS_L3_DPF(dev_priv)) | |
e1ef7cc2 | 3269 | |
c8735b0c | 3270 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 3271 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 3272 | |
05394f39 CW |
3273 | #include "i915_trace.h" |
3274 | ||
80debff8 | 3275 | static inline bool intel_vtd_active(void) |
48f112fe CW |
3276 | { |
3277 | #ifdef CONFIG_INTEL_IOMMU | |
80debff8 | 3278 | if (intel_iommu_gfx_mapped) |
48f112fe CW |
3279 | return true; |
3280 | #endif | |
3281 | return false; | |
3282 | } | |
3283 | ||
80debff8 CW |
3284 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
3285 | { | |
3286 | return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); | |
3287 | } | |
3288 | ||
0ef34ad6 JB |
3289 | static inline bool |
3290 | intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
3291 | { | |
80debff8 | 3292 | return IS_BROXTON(dev_priv) && intel_vtd_active(); |
0ef34ad6 JB |
3293 | } |
3294 | ||
c033666a | 3295 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
351c3b53 | 3296 | int enable_ppgtt); |
0e4ca100 | 3297 | |
39df9190 CW |
3298 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); |
3299 | ||
0673ad47 | 3300 | /* i915_drv.c */ |
d15d7538 ID |
3301 | void __printf(3, 4) |
3302 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
3303 | const char *fmt, ...); | |
3304 | ||
3305 | #define i915_report_error(dev_priv, fmt, ...) \ | |
3306 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
3307 | ||
c43b5634 | 3308 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
3309 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
3310 | unsigned long arg); | |
55edf41b JN |
3311 | #else |
3312 | #define i915_compat_ioctl NULL | |
c43b5634 | 3313 | #endif |
efab0698 JN |
3314 | extern const struct dev_pm_ops i915_pm_ops; |
3315 | ||
3316 | extern int i915_driver_load(struct pci_dev *pdev, | |
3317 | const struct pci_device_id *ent); | |
3318 | extern void i915_driver_unload(struct drm_device *dev); | |
dc97997a CW |
3319 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
3320 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
535275d3 CW |
3321 | |
3322 | #define I915_RESET_QUIET BIT(0) | |
3323 | extern void i915_reset(struct drm_i915_private *i915, unsigned int flags); | |
3324 | extern int i915_reset_engine(struct intel_engine_cs *engine, | |
3325 | unsigned int flags); | |
3326 | ||
142bc7d9 | 3327 | extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); |
6b332fa2 | 3328 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 3329 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
3ac168a7 | 3330 | extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); |
7648fa99 JB |
3331 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
3332 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
3333 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
3334 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 3335 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 3336 | |
63ffbcda | 3337 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv); |
bb8f0f5a CW |
3338 | int intel_engines_init(struct drm_i915_private *dev_priv); |
3339 | ||
77913b39 | 3340 | /* intel_hotplug.c */ |
91d14251 TU |
3341 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
3342 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
3343 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
3344 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
3345 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
256cfdde | 3346 | enum port intel_hpd_pin_to_port(enum hpd_pin pin); |
f761bef2 | 3347 | enum hpd_pin intel_hpd_pin(enum port port); |
b236d7c8 L |
3348 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
3349 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 3350 | |
1da177e4 | 3351 | /* i915_irq.c */ |
26a02b8f CW |
3352 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
3353 | { | |
3354 | unsigned long delay; | |
3355 | ||
4f044a88 | 3356 | if (unlikely(!i915_modparams.enable_hangcheck)) |
26a02b8f CW |
3357 | return; |
3358 | ||
3359 | /* Don't continually defer the hangcheck so that it is always run at | |
3360 | * least once after work has been scheduled on any ring. Otherwise, | |
3361 | * we will ignore a hung ring if a second ring is kept busy. | |
3362 | */ | |
3363 | ||
3364 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
3365 | queue_delayed_work(system_long_wq, | |
3366 | &dev_priv->gpu_error.hangcheck_work, delay); | |
3367 | } | |
3368 | ||
58174462 | 3369 | __printf(3, 4) |
c033666a CW |
3370 | void i915_handle_error(struct drm_i915_private *dev_priv, |
3371 | u32 engine_mask, | |
58174462 | 3372 | const char *fmt, ...); |
1da177e4 | 3373 | |
b963291c | 3374 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
cefcff8f | 3375 | extern void intel_irq_fini(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
3376 | int intel_irq_install(struct drm_i915_private *dev_priv); |
3377 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 3378 | |
0ad35fed ZW |
3379 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
3380 | { | |
feddf6e8 | 3381 | return dev_priv->gvt; |
0ad35fed ZW |
3382 | } |
3383 | ||
c033666a | 3384 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 3385 | { |
c033666a | 3386 | return dev_priv->vgpu.active; |
cf9d2890 | 3387 | } |
b1f14ad0 | 3388 | |
6b12ca56 VS |
3389 | u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, |
3390 | enum pipe pipe); | |
7c463586 | 3391 | void |
50227e1c | 3392 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 3393 | u32 status_mask); |
7c463586 KP |
3394 | |
3395 | void | |
50227e1c | 3396 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 3397 | u32 status_mask); |
7c463586 | 3398 | |
f8b79e58 ID |
3399 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
3400 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
3401 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
3402 | uint32_t mask, | |
3403 | uint32_t bits); | |
fbdedaea VS |
3404 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
3405 | uint32_t interrupt_mask, | |
3406 | uint32_t enabled_irq_mask); | |
3407 | static inline void | |
3408 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3409 | { | |
3410 | ilk_update_display_irq(dev_priv, bits, bits); | |
3411 | } | |
3412 | static inline void | |
3413 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3414 | { | |
3415 | ilk_update_display_irq(dev_priv, bits, 0); | |
3416 | } | |
013d3752 VS |
3417 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
3418 | enum pipe pipe, | |
3419 | uint32_t interrupt_mask, | |
3420 | uint32_t enabled_irq_mask); | |
3421 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
3422 | enum pipe pipe, uint32_t bits) | |
3423 | { | |
3424 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
3425 | } | |
3426 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
3427 | enum pipe pipe, uint32_t bits) | |
3428 | { | |
3429 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
3430 | } | |
47339cd9 DV |
3431 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
3432 | uint32_t interrupt_mask, | |
3433 | uint32_t enabled_irq_mask); | |
14443261 VS |
3434 | static inline void |
3435 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3436 | { | |
3437 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3438 | } | |
3439 | static inline void | |
3440 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3441 | { | |
3442 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3443 | } | |
3444 | ||
673a394b | 3445 | /* i915_gem.c */ |
673a394b EA |
3446 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
3447 | struct drm_file *file_priv); | |
3448 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3449 | struct drm_file *file_priv); | |
3450 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3451 | struct drm_file *file_priv); | |
3452 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3453 | struct drm_file *file_priv); | |
de151cf6 JB |
3454 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
3455 | struct drm_file *file_priv); | |
673a394b EA |
3456 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
3457 | struct drm_file *file_priv); | |
3458 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3459 | struct drm_file *file_priv); | |
3460 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3461 | struct drm_file *file_priv); | |
76446cac JB |
3462 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
3463 | struct drm_file *file_priv); | |
673a394b EA |
3464 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3465 | struct drm_file *file_priv); | |
199adf40 BW |
3466 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3467 | struct drm_file *file); | |
3468 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3469 | struct drm_file *file); | |
673a394b EA |
3470 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3471 | struct drm_file *file_priv); | |
3ef94daa CW |
3472 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3473 | struct drm_file *file_priv); | |
111dbcab CW |
3474 | int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
3475 | struct drm_file *file_priv); | |
3476 | int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
3477 | struct drm_file *file_priv); | |
8a2421bd CW |
3478 | int i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
3479 | void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); | |
5cc9ed4b CW |
3480 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
3481 | struct drm_file *file); | |
5a125c3c EA |
3482 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
3483 | struct drm_file *file_priv); | |
23ba4fd0 BW |
3484 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
3485 | struct drm_file *file_priv); | |
24145517 | 3486 | void i915_gem_sanitize(struct drm_i915_private *i915); |
cb15d9f8 TU |
3487 | int i915_gem_load_init(struct drm_i915_private *dev_priv); |
3488 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv); | |
40ae4e16 | 3489 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
6a800eab | 3490 | int i915_gem_freeze(struct drm_i915_private *dev_priv); |
461fb99c CW |
3491 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
3492 | ||
187685cb | 3493 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); |
42dcedd4 | 3494 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
37e680a1 CW |
3495 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3496 | const struct drm_i915_gem_object_ops *ops); | |
12d79d78 TU |
3497 | struct drm_i915_gem_object * |
3498 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); | |
3499 | struct drm_i915_gem_object * | |
3500 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, | |
3501 | const void *data, size_t size); | |
b1f788c6 | 3502 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 3503 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 3504 | |
bdeb9785 CW |
3505 | static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) |
3506 | { | |
3507 | /* A single pass should suffice to release all the freed objects (along | |
3508 | * most call paths) , but be a little more paranoid in that freeing | |
3509 | * the objects does take a little amount of time, during which the rcu | |
3510 | * callbacks could have added new objects into the freed list, and | |
3511 | * armed the work again. | |
3512 | */ | |
3513 | do { | |
3514 | rcu_barrier(); | |
3515 | } while (flush_work(&i915->mm.free_work)); | |
3516 | } | |
3517 | ||
3b19f16a CW |
3518 | static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) |
3519 | { | |
3520 | /* | |
3521 | * Similar to objects above (see i915_gem_drain_freed-objects), in | |
3522 | * general we have workers that are armed by RCU and then rearm | |
3523 | * themselves in their callbacks. To be paranoid, we need to | |
3524 | * drain the workqueue a second time after waiting for the RCU | |
3525 | * grace period so that we catch work queued via RCU from the first | |
3526 | * pass. As neither drain_workqueue() nor flush_workqueue() report | |
3527 | * a result, we make an assumption that we only don't require more | |
3528 | * than 2 passes to catch all recursive RCU delayed work. | |
3529 | * | |
3530 | */ | |
3531 | int pass = 2; | |
3532 | do { | |
3533 | rcu_barrier(); | |
3534 | drain_workqueue(i915->wq); | |
3535 | } while (--pass); | |
3536 | } | |
3537 | ||
058d88c4 | 3538 | struct i915_vma * __must_check |
ec7adb6e JL |
3539 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3540 | const struct i915_ggtt_view *view, | |
91b2db6f | 3541 | u64 size, |
2ffffd0f CW |
3542 | u64 alignment, |
3543 | u64 flags); | |
fe14d5f4 | 3544 | |
aa653a68 | 3545 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 3546 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 3547 | |
7c108fd8 CW |
3548 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); |
3549 | ||
a4f5ea64 | 3550 | static inline int __sg_page_count(const struct scatterlist *sg) |
9da3da66 | 3551 | { |
ee286370 CW |
3552 | return sg->length >> PAGE_SHIFT; |
3553 | } | |
67d5a50c | 3554 | |
96d77634 CW |
3555 | struct scatterlist * |
3556 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
3557 | unsigned int n, unsigned int *offset); | |
341be1cd | 3558 | |
96d77634 CW |
3559 | struct page * |
3560 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, | |
3561 | unsigned int n); | |
67d5a50c | 3562 | |
96d77634 CW |
3563 | struct page * |
3564 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
3565 | unsigned int n); | |
67d5a50c | 3566 | |
96d77634 CW |
3567 | dma_addr_t |
3568 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
3569 | unsigned long n); | |
ee286370 | 3570 | |
03ac84f1 | 3571 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, |
a5c08166 | 3572 | struct sg_table *pages, |
84e8978e | 3573 | unsigned int sg_page_sizes); |
a4f5ea64 CW |
3574 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
3575 | ||
3576 | static inline int __must_check | |
3577 | i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
3578 | { | |
1233e2db | 3579 | might_lock(&obj->mm.lock); |
a4f5ea64 | 3580 | |
1233e2db | 3581 | if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) |
a4f5ea64 CW |
3582 | return 0; |
3583 | ||
3584 | return __i915_gem_object_get_pages(obj); | |
3585 | } | |
3586 | ||
f1fa4f44 CW |
3587 | static inline bool |
3588 | i915_gem_object_has_pages(struct drm_i915_gem_object *obj) | |
3589 | { | |
3590 | return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages)); | |
3591 | } | |
3592 | ||
a4f5ea64 CW |
3593 | static inline void |
3594 | __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3595 | { |
f1fa4f44 | 3596 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
a4f5ea64 | 3597 | |
1233e2db | 3598 | atomic_inc(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3599 | } |
3600 | ||
3601 | static inline bool | |
3602 | i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) | |
3603 | { | |
1233e2db | 3604 | return atomic_read(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3605 | } |
3606 | ||
3607 | static inline void | |
3608 | __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3609 | { | |
f1fa4f44 | 3610 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
a4f5ea64 | 3611 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
a4f5ea64 | 3612 | |
1233e2db | 3613 | atomic_dec(&obj->mm.pages_pin_count); |
a5570178 | 3614 | } |
0a798eb9 | 3615 | |
1233e2db CW |
3616 | static inline void |
3617 | i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3618 | { |
a4f5ea64 | 3619 | __i915_gem_object_unpin_pages(obj); |
a5570178 CW |
3620 | } |
3621 | ||
548625ee CW |
3622 | enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ |
3623 | I915_MM_NORMAL = 0, | |
3624 | I915_MM_SHRINKER | |
3625 | }; | |
3626 | ||
3627 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, | |
3628 | enum i915_mm_subclass subclass); | |
03ac84f1 | 3629 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); |
a4f5ea64 | 3630 | |
d31d7cb1 CW |
3631 | enum i915_map_type { |
3632 | I915_MAP_WB = 0, | |
3633 | I915_MAP_WC, | |
a575c676 CW |
3634 | #define I915_MAP_OVERRIDE BIT(31) |
3635 | I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE, | |
3636 | I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE, | |
d31d7cb1 CW |
3637 | }; |
3638 | ||
0a798eb9 CW |
3639 | /** |
3640 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
a73c7a44 CW |
3641 | * @obj: the object to map into kernel address space |
3642 | * @type: the type of mapping, used to select pgprot_t | |
0a798eb9 CW |
3643 | * |
3644 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3645 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
3646 | * the kernel address space. Based on the @type of mapping, the PTE will be |
3647 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 3648 | * |
1233e2db CW |
3649 | * The caller is responsible for calling i915_gem_object_unpin_map() when the |
3650 | * mapping is no longer required. | |
0a798eb9 | 3651 | * |
8305216f DG |
3652 | * Returns the pointer through which to access the mapped object, or an |
3653 | * ERR_PTR() on error. | |
0a798eb9 | 3654 | */ |
d31d7cb1 CW |
3655 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
3656 | enum i915_map_type type); | |
0a798eb9 CW |
3657 | |
3658 | /** | |
3659 | * i915_gem_object_unpin_map - releases an earlier mapping | |
a73c7a44 | 3660 | * @obj: the object to unmap |
0a798eb9 CW |
3661 | * |
3662 | * After pinning the object and mapping its pages, once you are finished | |
3663 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3664 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3665 | * removed. | |
0a798eb9 CW |
3666 | */ |
3667 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3668 | { | |
0a798eb9 CW |
3669 | i915_gem_object_unpin_pages(obj); |
3670 | } | |
3671 | ||
43394c7d CW |
3672 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3673 | unsigned int *needs_clflush); | |
3674 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3675 | unsigned int *needs_clflush); | |
7f5f95d8 CW |
3676 | #define CLFLUSH_BEFORE BIT(0) |
3677 | #define CLFLUSH_AFTER BIT(1) | |
3678 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
43394c7d CW |
3679 | |
3680 | static inline void | |
3681 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3682 | { | |
3683 | i915_gem_object_unpin_pages(obj); | |
3684 | } | |
3685 | ||
54cf91dc | 3686 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
e2d05a8b | 3687 | void i915_vma_move_to_active(struct i915_vma *vma, |
5cf3d280 CW |
3688 | struct drm_i915_gem_request *req, |
3689 | unsigned int flags); | |
ff72145b DA |
3690 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3691 | struct drm_device *dev, | |
3692 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3693 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3694 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3695 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3696 | |
3697 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3698 | struct drm_i915_gem_object *new, | |
3699 | unsigned frontbuffer_bits); | |
3700 | ||
73cb9701 | 3701 | int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3702 | |
8d9fc7fd | 3703 | struct drm_i915_gem_request * |
0bc40be8 | 3704 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3705 | |
67d97da3 | 3706 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
84c33a64 | 3707 | |
8c185eca CW |
3708 | static inline bool i915_reset_backoff(struct i915_gpu_error *error) |
3709 | { | |
3710 | return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags)); | |
3711 | } | |
3712 | ||
3713 | static inline bool i915_reset_handoff(struct i915_gpu_error *error) | |
1f83fee0 | 3714 | { |
8c185eca | 3715 | return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags)); |
c19ae989 CW |
3716 | } |
3717 | ||
8af29b0c | 3718 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
c19ae989 | 3719 | { |
8af29b0c | 3720 | return unlikely(test_bit(I915_WEDGED, &error->flags)); |
1f83fee0 DV |
3721 | } |
3722 | ||
8c185eca | 3723 | static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error) |
1f83fee0 | 3724 | { |
8c185eca | 3725 | return i915_reset_backoff(error) | i915_terminally_wedged(error); |
2ac0f450 MK |
3726 | } |
3727 | ||
3728 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3729 | { | |
8af29b0c | 3730 | return READ_ONCE(error->reset_count); |
1f83fee0 | 3731 | } |
a71d8d94 | 3732 | |
702c8f8e MT |
3733 | static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, |
3734 | struct intel_engine_cs *engine) | |
3735 | { | |
3736 | return READ_ONCE(error->reset_engine_count[engine->id]); | |
3737 | } | |
3738 | ||
a1ef70e1 MT |
3739 | struct drm_i915_gem_request * |
3740 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine); | |
0e178aef | 3741 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); |
d8027093 | 3742 | void i915_gem_reset(struct drm_i915_private *dev_priv); |
a1ef70e1 | 3743 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine); |
b1ed35d9 | 3744 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv); |
821ed7df | 3745 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); |
2e8f9d32 | 3746 | bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv); |
a1ef70e1 MT |
3747 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
3748 | struct drm_i915_gem_request *request); | |
57822dc6 | 3749 | |
24145517 | 3750 | void i915_gem_init_mmio(struct drm_i915_private *i915); |
bf9e8429 TU |
3751 | int __must_check i915_gem_init(struct drm_i915_private *dev_priv); |
3752 | int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); | |
c6be607a | 3753 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); |
cb15d9f8 | 3754 | void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv); |
496b575e CW |
3755 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
3756 | unsigned int flags); | |
bf9e8429 TU |
3757 | int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv); |
3758 | void i915_gem_resume(struct drm_i915_private *dev_priv); | |
11bac800 | 3759 | int i915_gem_fault(struct vm_fault *vmf); |
e95433c7 CW |
3760 | int i915_gem_object_wait(struct drm_i915_gem_object *obj, |
3761 | unsigned int flags, | |
3762 | long timeout, | |
3763 | struct intel_rps_client *rps); | |
6b5e90f5 CW |
3764 | int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, |
3765 | unsigned int flags, | |
3766 | int priority); | |
3767 | #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX | |
3768 | ||
2e2f351d | 3769 | int __must_check |
e22d8e3c CW |
3770 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); |
3771 | int __must_check | |
3772 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); | |
2021746e | 3773 | int __must_check |
dabdfe02 | 3774 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3775 | struct i915_vma * __must_check |
2da3b9b9 CW |
3776 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3777 | u32 alignment, | |
e6617330 | 3778 | const struct i915_ggtt_view *view); |
058d88c4 | 3779 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3780 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3781 | int align); |
829a0af2 | 3782 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); |
05394f39 | 3783 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3784 | |
e4ffd173 CW |
3785 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3786 | enum i915_cache_level cache_level); | |
3787 | ||
1286ff73 DV |
3788 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3789 | struct dma_buf *dma_buf); | |
3790 | ||
3791 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3792 | struct drm_gem_object *gem_obj, int flags); | |
3793 | ||
841cd773 DV |
3794 | static inline struct i915_hw_ppgtt * |
3795 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3796 | { | |
841cd773 DV |
3797 | return container_of(vm, struct i915_hw_ppgtt, base); |
3798 | } | |
3799 | ||
b42fe9ca | 3800 | /* i915_gem_fence_reg.c */ |
969b0950 CD |
3801 | struct drm_i915_fence_reg * |
3802 | i915_reserve_fence(struct drm_i915_private *dev_priv); | |
3803 | void i915_unreserve_fence(struct drm_i915_fence_reg *fence); | |
49ef5294 | 3804 | |
b1ed35d9 | 3805 | void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); |
4362f4f6 | 3806 | void i915_gem_restore_fences(struct drm_i915_private *dev_priv); |
41a36b73 | 3807 | |
4362f4f6 | 3808 | void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); |
03ac84f1 CW |
3809 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, |
3810 | struct sg_table *pages); | |
3811 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3812 | struct sg_table *pages); | |
7f96ecaf | 3813 | |
1acfc104 CW |
3814 | static inline struct i915_gem_context * |
3815 | __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) | |
3816 | { | |
3817 | return idr_find(&file_priv->context_idr, id); | |
3818 | } | |
3819 | ||
ca585b5d CW |
3820 | static inline struct i915_gem_context * |
3821 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3822 | { | |
3823 | struct i915_gem_context *ctx; | |
3824 | ||
1acfc104 CW |
3825 | rcu_read_lock(); |
3826 | ctx = __i915_gem_context_lookup_rcu(file_priv, id); | |
3827 | if (ctx && !kref_get_unless_zero(&ctx->ref)) | |
3828 | ctx = NULL; | |
3829 | rcu_read_unlock(); | |
ca585b5d CW |
3830 | |
3831 | return ctx; | |
3832 | } | |
3833 | ||
80b204bc CW |
3834 | static inline struct intel_timeline * |
3835 | i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, | |
3836 | struct intel_engine_cs *engine) | |
3837 | { | |
3838 | struct i915_address_space *vm; | |
3839 | ||
3840 | vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base; | |
3841 | return &vm->timeline.engine[engine->id]; | |
3842 | } | |
3843 | ||
eec688e1 RB |
3844 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, |
3845 | struct drm_file *file); | |
f89823c2 LL |
3846 | int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, |
3847 | struct drm_file *file); | |
3848 | int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, | |
3849 | struct drm_file *file); | |
19f81df2 RB |
3850 | void i915_oa_init_reg_state(struct intel_engine_cs *engine, |
3851 | struct i915_gem_context *ctx, | |
3852 | uint32_t *reg_state); | |
eec688e1 | 3853 | |
679845ed | 3854 | /* i915_gem_evict.c */ |
e522ac23 | 3855 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3856 | u64 min_size, u64 alignment, |
679845ed | 3857 | unsigned cache_level, |
2ffffd0f | 3858 | u64 start, u64 end, |
1ec9e26d | 3859 | unsigned flags); |
625d988a CW |
3860 | int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, |
3861 | struct drm_mm_node *node, | |
3862 | unsigned int flags); | |
2889caa9 | 3863 | int i915_gem_evict_vm(struct i915_address_space *vm); |
1d2a314c | 3864 | |
0260c420 | 3865 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3866 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3867 | { |
600f4368 | 3868 | wmb(); |
c033666a | 3869 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3870 | intel_gtt_chipset_flush(); |
3871 | } | |
246cbfb5 | 3872 | |
9797fbfb | 3873 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3874 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3875 | struct drm_mm_node *node, u64 size, | |
3876 | unsigned alignment); | |
a9da512b PZ |
3877 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3878 | struct drm_mm_node *node, u64 size, | |
3879 | unsigned alignment, u64 start, | |
3880 | u64 end); | |
d713fd49 PZ |
3881 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3882 | struct drm_mm_node *node); | |
7ace3d30 | 3883 | int i915_gem_init_stolen(struct drm_i915_private *dev_priv); |
9797fbfb | 3884 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb | 3885 | struct drm_i915_gem_object * |
187685cb | 3886 | i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size); |
866d12b4 | 3887 | struct drm_i915_gem_object * |
187685cb | 3888 | i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, |
866d12b4 CW |
3889 | u32 stolen_offset, |
3890 | u32 gtt_offset, | |
3891 | u32 size); | |
9797fbfb | 3892 | |
920cf419 CW |
3893 | /* i915_gem_internal.c */ |
3894 | struct drm_i915_gem_object * | |
3895 | i915_gem_object_create_internal(struct drm_i915_private *dev_priv, | |
fcd46e53 | 3896 | phys_addr_t size); |
920cf419 | 3897 | |
be6a0376 DV |
3898 | /* i915_gem_shrinker.c */ |
3899 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3900 | unsigned long target, |
912d572d | 3901 | unsigned long *nr_scanned, |
be6a0376 DV |
3902 | unsigned flags); |
3903 | #define I915_SHRINK_PURGEABLE 0x1 | |
3904 | #define I915_SHRINK_UNBOUND 0x2 | |
3905 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3906 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3907 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3908 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3909 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3910 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3911 | |
3912 | ||
673a394b | 3913 | /* i915_gem_tiling.c */ |
2c1792a1 | 3914 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3915 | { |
091387c1 | 3916 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3917 | |
3918 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3919 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3920 | } |
3921 | ||
91d4e0aa CW |
3922 | u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, |
3923 | unsigned int tiling, unsigned int stride); | |
3924 | u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, | |
3925 | unsigned int tiling, unsigned int stride); | |
3926 | ||
2017263e | 3927 | /* i915_debugfs.c */ |
f8c168fa | 3928 | #ifdef CONFIG_DEBUG_FS |
1dac891c | 3929 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
249e87de | 3930 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3931 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3932 | #else |
8d35acba | 3933 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
101057fa DV |
3934 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3935 | { return 0; } | |
ce5e2ac1 | 3936 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3937 | #endif |
84734a04 MK |
3938 | |
3939 | /* i915_gpu_error.c */ | |
98a2f411 CW |
3940 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
3941 | ||
edc3d884 MK |
3942 | __printf(2, 3) |
3943 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b | 3944 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
5a4c6f1b | 3945 | const struct i915_gpu_state *gpu); |
4dc955f7 | 3946 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3947 | struct drm_i915_private *i915, |
4dc955f7 MK |
3948 | size_t count, loff_t pos); |
3949 | static inline void i915_error_state_buf_release( | |
3950 | struct drm_i915_error_state_buf *eb) | |
3951 | { | |
3952 | kfree(eb->buf); | |
3953 | } | |
5a4c6f1b CW |
3954 | |
3955 | struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915); | |
c033666a CW |
3956 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3957 | u32 engine_mask, | |
58174462 | 3958 | const char *error_msg); |
5a4c6f1b CW |
3959 | |
3960 | static inline struct i915_gpu_state * | |
3961 | i915_gpu_state_get(struct i915_gpu_state *gpu) | |
3962 | { | |
3963 | kref_get(&gpu->ref); | |
3964 | return gpu; | |
3965 | } | |
3966 | ||
3967 | void __i915_gpu_state_free(struct kref *kref); | |
3968 | static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) | |
3969 | { | |
3970 | if (gpu) | |
3971 | kref_put(&gpu->ref, __i915_gpu_state_free); | |
3972 | } | |
3973 | ||
3974 | struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915); | |
3975 | void i915_reset_error_state(struct drm_i915_private *i915); | |
84734a04 | 3976 | |
98a2f411 CW |
3977 | #else |
3978 | ||
3979 | static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, | |
3980 | u32 engine_mask, | |
3981 | const char *error_msg) | |
3982 | { | |
3983 | } | |
3984 | ||
5a4c6f1b CW |
3985 | static inline struct i915_gpu_state * |
3986 | i915_first_error_state(struct drm_i915_private *i915) | |
3987 | { | |
3988 | return NULL; | |
3989 | } | |
3990 | ||
3991 | static inline void i915_reset_error_state(struct drm_i915_private *i915) | |
98a2f411 CW |
3992 | { |
3993 | } | |
3994 | ||
3995 | #endif | |
3996 | ||
0a4cd7c8 | 3997 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3998 | |
351e3db2 | 3999 | /* i915_cmd_parser.c */ |
1ca3712c | 4000 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 4001 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 | 4002 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
4003 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
4004 | struct drm_i915_gem_object *batch_obj, | |
4005 | struct drm_i915_gem_object *shadow_batch_obj, | |
4006 | u32 batch_start_offset, | |
4007 | u32 batch_len, | |
4008 | bool is_master); | |
351e3db2 | 4009 | |
eec688e1 RB |
4010 | /* i915_perf.c */ |
4011 | extern void i915_perf_init(struct drm_i915_private *dev_priv); | |
4012 | extern void i915_perf_fini(struct drm_i915_private *dev_priv); | |
442b8c06 RB |
4013 | extern void i915_perf_register(struct drm_i915_private *dev_priv); |
4014 | extern void i915_perf_unregister(struct drm_i915_private *dev_priv); | |
eec688e1 | 4015 | |
317c35d1 | 4016 | /* i915_suspend.c */ |
af6dc742 TU |
4017 | extern int i915_save_state(struct drm_i915_private *dev_priv); |
4018 | extern int i915_restore_state(struct drm_i915_private *dev_priv); | |
0a3e67a4 | 4019 | |
0136db58 | 4020 | /* i915_sysfs.c */ |
694c2828 DW |
4021 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
4022 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 4023 | |
eef57324 JA |
4024 | /* intel_lpe_audio.c */ |
4025 | int intel_lpe_audio_init(struct drm_i915_private *dev_priv); | |
4026 | void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); | |
4027 | void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); | |
46d196ec | 4028 | void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, |
20be551e VS |
4029 | enum pipe pipe, enum port port, |
4030 | const void *eld, int ls_clock, bool dp_output); | |
eef57324 | 4031 | |
f899fc64 | 4032 | /* intel_i2c.c */ |
40196446 TU |
4033 | extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); |
4034 | extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); | |
88ac7939 JN |
4035 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
4036 | unsigned int pin); | |
3bd7d909 | 4037 | |
0184df46 JN |
4038 | extern struct i2c_adapter * |
4039 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
4040 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
4041 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 4042 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
4043 | { |
4044 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
4045 | } | |
af6dc742 | 4046 | extern void intel_i2c_reset(struct drm_i915_private *dev_priv); |
f899fc64 | 4047 | |
8b8e1a89 | 4048 | /* intel_bios.c */ |
66578857 | 4049 | void intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 4050 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 4051 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 4052 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 4053 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 4054 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 4055 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 4056 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
4057 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
4058 | enum port port); | |
6389dd83 SS |
4059 | bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, |
4060 | enum port port); | |
4061 | ||
8b8e1a89 | 4062 | |
3b617967 | 4063 | /* intel_opregion.c */ |
44834a67 | 4064 | #ifdef CONFIG_ACPI |
6f9f4b7a | 4065 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
4066 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
4067 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 4068 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
4069 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
4070 | bool enable); | |
6f9f4b7a | 4071 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 4072 | pci_power_t state); |
6f9f4b7a | 4073 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 4074 | #else |
6f9f4b7a | 4075 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
4076 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
4077 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
4078 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
4079 | { | |
4080 | } | |
9c4b0a68 JN |
4081 | static inline int |
4082 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
4083 | { | |
4084 | return 0; | |
4085 | } | |
ecbc5cf3 | 4086 | static inline int |
6f9f4b7a | 4087 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
4088 | { |
4089 | return 0; | |
4090 | } | |
6f9f4b7a | 4091 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
4092 | { |
4093 | return -ENODEV; | |
4094 | } | |
65e082c9 | 4095 | #endif |
8ee1c3db | 4096 | |
723bfd70 JB |
4097 | /* intel_acpi.c */ |
4098 | #ifdef CONFIG_ACPI | |
4099 | extern void intel_register_dsm_handler(void); | |
4100 | extern void intel_unregister_dsm_handler(void); | |
4101 | #else | |
4102 | static inline void intel_register_dsm_handler(void) { return; } | |
4103 | static inline void intel_unregister_dsm_handler(void) { return; } | |
4104 | #endif /* CONFIG_ACPI */ | |
4105 | ||
94b4f3ba CW |
4106 | /* intel_device_info.c */ |
4107 | static inline struct intel_device_info * | |
4108 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
4109 | { | |
4110 | return (struct intel_device_info *)&dev_priv->info; | |
4111 | } | |
4112 | ||
2e0d26f8 | 4113 | const char *intel_platform_name(enum intel_platform platform); |
94b4f3ba CW |
4114 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
4115 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
4116 | ||
79e53945 | 4117 | /* modesetting */ |
f817586c | 4118 | extern void intel_modeset_init_hw(struct drm_device *dev); |
b079bd17 | 4119 | extern int intel_modeset_init(struct drm_device *dev); |
2c7111db | 4120 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 4121 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 4122 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 4123 | extern void intel_connector_unregister(struct drm_connector *); |
6315b5d3 TU |
4124 | extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, |
4125 | bool state); | |
043e9bda | 4126 | extern void intel_display_resume(struct drm_device *dev); |
29b74b7f TU |
4127 | extern void i915_redisable_vga(struct drm_i915_private *dev_priv); |
4128 | extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); | |
91d14251 | 4129 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
c39055b0 | 4130 | extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); |
9fcee2f7 | 4131 | extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
11a85d6a | 4132 | extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
5209b1f4 | 4133 | bool enable); |
3bad0781 | 4134 | |
c0c7babc BW |
4135 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
4136 | struct drm_file *file); | |
575155a9 | 4137 | |
6ef3d427 | 4138 | /* overlay */ |
c033666a CW |
4139 | extern struct intel_overlay_error_state * |
4140 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
4141 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
4142 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 4143 | |
c033666a CW |
4144 | extern struct intel_display_error_state * |
4145 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 4146 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 | 4147 | struct intel_display_error_state *error); |
6ef3d427 | 4148 | |
151a49d0 | 4149 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
a6a44fad ID |
4150 | int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox, |
4151 | u32 val, int timeout_us); | |
4152 | #define sandybridge_pcode_write(dev_priv, mbox, val) \ | |
4153 | sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500) | |
4154 | ||
a0b8a1fe ID |
4155 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, |
4156 | u32 reply_mask, u32 reply, int timeout_base_ms); | |
59de0813 JN |
4157 | |
4158 | /* intel_sideband.c */ | |
707b6e3d | 4159 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
9fcee2f7 | 4160 | int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
64936258 | 4161 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
4162 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
4163 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
4164 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
4165 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
4166 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
4167 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
4168 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
4169 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
4170 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
4171 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
4172 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
4173 | enum intel_sbi_destination destination); | |
4174 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
4175 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
4176 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
4177 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 4178 | |
b7fa22d8 | 4179 | /* intel_dpio_phy.c */ |
0a116ce8 | 4180 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, |
ed37892e | 4181 | enum dpio_phy *phy, enum dpio_channel *ch); |
b6e08203 ACO |
4182 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
4183 | enum port port, u32 margin, u32 scale, | |
4184 | u32 enable, u32 deemphasis); | |
47a6bc61 ACO |
4185 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
4186 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
4187 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, | |
4188 | enum dpio_phy phy); | |
4189 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
4190 | enum dpio_phy phy); | |
4191 | uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
4192 | uint8_t lane_count); | |
4193 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
4194 | uint8_t lane_lat_optim_mask); | |
4195 | uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); | |
4196 | ||
b7fa22d8 ACO |
4197 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
4198 | u32 deemph_reg_value, u32 margin_reg_value, | |
4199 | bool uniq_trans_scale); | |
844b2f9a ACO |
4200 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
4201 | bool reset); | |
419b1b7a | 4202 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
4203 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
4204 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 4205 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 4206 | |
53d98725 ACO |
4207 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
4208 | u32 demph_reg_value, u32 preemph_reg_value, | |
4209 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 4210 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 4211 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 4212 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 4213 | |
616bc820 VS |
4214 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
4215 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c5a0ad11 MK |
4216 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
4217 | const i915_reg_t reg); | |
c8d9a590 | 4218 | |
0b274481 BW |
4219 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
4220 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
4221 | ||
4222 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
4223 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
4224 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
4225 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
4226 | ||
4227 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
4228 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
4229 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
4230 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
4231 | ||
698b3135 CW |
4232 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
4233 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
4234 | * an arbitrary delay between them. This can cause the hardware to | |
4235 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
4236 | * machine death. For this reason we do not support I915_WRITE64, or |
4237 | * dev_priv->uncore.funcs.mmio_writeq. | |
4238 | * | |
4239 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
4240 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
4241 | * occasionally a 64-bit register does not actualy support a full readq | |
4242 | * and must be read using two 32-bit reads. | |
4243 | * | |
4244 | * You have been warned. | |
698b3135 | 4245 | */ |
0b274481 | 4246 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 4247 | |
50877445 | 4248 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
4249 | u32 upper, lower, old_upper, loop = 0; \ |
4250 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 4251 | do { \ |
acd29f7b | 4252 | old_upper = upper; \ |
ee0a227b | 4253 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
4254 | upper = I915_READ(upper_reg); \ |
4255 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 4256 | (u64)upper << 32 | lower; }) |
50877445 | 4257 | |
cae5852d ZN |
4258 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
4259 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
4260 | ||
75aa3f63 | 4261 | #define __raw_read(x, s) \ |
6e3955a5 | 4262 | static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 4263 | i915_reg_t reg) \ |
75aa3f63 | 4264 | { \ |
f0f59a00 | 4265 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
4266 | } |
4267 | ||
4268 | #define __raw_write(x, s) \ | |
6e3955a5 | 4269 | static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 4270 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 4271 | { \ |
f0f59a00 | 4272 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
4273 | } |
4274 | __raw_read(8, b) | |
4275 | __raw_read(16, w) | |
4276 | __raw_read(32, l) | |
4277 | __raw_read(64, q) | |
4278 | ||
4279 | __raw_write(8, b) | |
4280 | __raw_write(16, w) | |
4281 | __raw_write(32, l) | |
4282 | __raw_write(64, q) | |
4283 | ||
4284 | #undef __raw_read | |
4285 | #undef __raw_write | |
4286 | ||
a6111f7b | 4287 | /* These are untraced mmio-accessors that are only valid to be used inside |
aafee2eb | 4288 | * critical sections, such as inside IRQ handlers, where forcewake is explicitly |
a6111f7b | 4289 | * controlled. |
aafee2eb | 4290 | * |
a6111f7b | 4291 | * Think twice, and think again, before using these. |
aafee2eb AH |
4292 | * |
4293 | * As an example, these accessors can possibly be used between: | |
4294 | * | |
4295 | * spin_lock_irq(&dev_priv->uncore.lock); | |
4296 | * intel_uncore_forcewake_get__locked(); | |
4297 | * | |
4298 | * and | |
4299 | * | |
4300 | * intel_uncore_forcewake_put__locked(); | |
4301 | * spin_unlock_irq(&dev_priv->uncore.lock); | |
4302 | * | |
4303 | * | |
4304 | * Note: some registers may not need forcewake held, so | |
4305 | * intel_uncore_forcewake_{get,put} can be omitted, see | |
4306 | * intel_uncore_forcewake_for_reg(). | |
4307 | * | |
4308 | * Certain architectures will die if the same cacheline is concurrently accessed | |
4309 | * by different clients (e.g. on Ivybridge). Access to registers should | |
4310 | * therefore generally be serialised, by either the dev_priv->uncore.lock or | |
4311 | * a more localised lock guarding all access to that bank of registers. | |
a6111f7b | 4312 | */ |
75aa3f63 VS |
4313 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
4314 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 4315 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
4316 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
4317 | ||
55bc60db VS |
4318 | /* "Broadcast RGB" property */ |
4319 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
4320 | #define INTEL_BROADCAST_RGB_FULL 1 | |
4321 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 4322 | |
920a14b2 | 4323 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) |
766aa1c4 | 4324 | { |
920a14b2 | 4325 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
766aa1c4 | 4326 | return VLV_VGACNTRL; |
920a14b2 | 4327 | else if (INTEL_GEN(dev_priv) >= 5) |
92e23b99 | 4328 | return CPU_VGACNTRL; |
766aa1c4 VS |
4329 | else |
4330 | return VGACNTRL; | |
4331 | } | |
4332 | ||
df97729f ID |
4333 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
4334 | { | |
4335 | unsigned long j = msecs_to_jiffies(m); | |
4336 | ||
4337 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
4338 | } | |
4339 | ||
7bd0e226 DV |
4340 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
4341 | { | |
b8050148 CW |
4342 | /* nsecs_to_jiffies64() does not guard against overflow */ |
4343 | if (NSEC_PER_SEC % HZ && | |
4344 | div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) | |
4345 | return MAX_JIFFY_OFFSET; | |
4346 | ||
7bd0e226 DV |
4347 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); |
4348 | } | |
4349 | ||
df97729f ID |
4350 | static inline unsigned long |
4351 | timespec_to_jiffies_timeout(const struct timespec *value) | |
4352 | { | |
4353 | unsigned long j = timespec_to_jiffies(value); | |
4354 | ||
4355 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
4356 | } | |
4357 | ||
dce56b3c PZ |
4358 | /* |
4359 | * If you need to wait X milliseconds between events A and B, but event B | |
4360 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
4361 | * when event A happened, then just before event B you call this function and | |
4362 | * pass the timestamp as the first argument, and X as the second argument. | |
4363 | */ | |
4364 | static inline void | |
4365 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
4366 | { | |
ec5e0cfb | 4367 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
4368 | |
4369 | /* | |
4370 | * Don't re-read the value of "jiffies" every time since it may change | |
4371 | * behind our back and break the math. | |
4372 | */ | |
4373 | tmp_jiffies = jiffies; | |
4374 | target_jiffies = timestamp_jiffies + | |
4375 | msecs_to_jiffies_timeout(to_wait_ms); | |
4376 | ||
4377 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
4378 | remaining_jiffies = target_jiffies - tmp_jiffies; |
4379 | while (remaining_jiffies) | |
4380 | remaining_jiffies = | |
4381 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
4382 | } |
4383 | } | |
221fe799 CW |
4384 | |
4385 | static inline bool | |
754c9fd5 | 4386 | __i915_request_irq_complete(const struct drm_i915_gem_request *req) |
688e6c72 | 4387 | { |
f69a02c9 | 4388 | struct intel_engine_cs *engine = req->engine; |
754c9fd5 | 4389 | u32 seqno; |
f69a02c9 | 4390 | |
309663ab CW |
4391 | /* Note that the engine may have wrapped around the seqno, and |
4392 | * so our request->global_seqno will be ahead of the hardware, | |
4393 | * even though it completed the request before wrapping. We catch | |
4394 | * this by kicking all the waiters before resetting the seqno | |
4395 | * in hardware, and also signal the fence. | |
4396 | */ | |
4397 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags)) | |
4398 | return true; | |
4399 | ||
754c9fd5 CW |
4400 | /* The request was dequeued before we were awoken. We check after |
4401 | * inspecting the hw to confirm that this was the same request | |
4402 | * that generated the HWS update. The memory barriers within | |
4403 | * the request execution are sufficient to ensure that a check | |
4404 | * after reading the value from hw matches this request. | |
4405 | */ | |
4406 | seqno = i915_gem_request_global_seqno(req); | |
4407 | if (!seqno) | |
4408 | return false; | |
4409 | ||
7ec2c73b CW |
4410 | /* Before we do the heavier coherent read of the seqno, |
4411 | * check the value (hopefully) in the CPU cacheline. | |
4412 | */ | |
754c9fd5 | 4413 | if (__i915_gem_request_completed(req, seqno)) |
7ec2c73b CW |
4414 | return true; |
4415 | ||
688e6c72 CW |
4416 | /* Ensure our read of the seqno is coherent so that we |
4417 | * do not "miss an interrupt" (i.e. if this is the last | |
4418 | * request and the seqno write from the GPU is not visible | |
4419 | * by the time the interrupt fires, we will see that the | |
4420 | * request is incomplete and go back to sleep awaiting | |
4421 | * another interrupt that will never come.) | |
4422 | * | |
4423 | * Strictly, we only need to do this once after an interrupt, | |
4424 | * but it is easier and safer to do it every time the waiter | |
4425 | * is woken. | |
4426 | */ | |
3d5564e9 | 4427 | if (engine->irq_seqno_barrier && |
538b257d | 4428 | test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { |
56299fb7 | 4429 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
99fe4a5f | 4430 | |
3d5564e9 CW |
4431 | /* The ordering of irq_posted versus applying the barrier |
4432 | * is crucial. The clearing of the current irq_posted must | |
4433 | * be visible before we perform the barrier operation, | |
4434 | * such that if a subsequent interrupt arrives, irq_posted | |
4435 | * is reasserted and our task rewoken (which causes us to | |
4436 | * do another __i915_request_irq_complete() immediately | |
4437 | * and reapply the barrier). Conversely, if the clear | |
4438 | * occurs after the barrier, then an interrupt that arrived | |
4439 | * whilst we waited on the barrier would not trigger a | |
4440 | * barrier on the next pass, and the read may not see the | |
4441 | * seqno update. | |
4442 | */ | |
f69a02c9 | 4443 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
4444 | |
4445 | /* If we consume the irq, but we are no longer the bottom-half, | |
4446 | * the real bottom-half may not have serialised their own | |
4447 | * seqno check with the irq-barrier (i.e. may have inspected | |
4448 | * the seqno before we believe it coherent since they see | |
4449 | * irq_posted == false but we are still running). | |
4450 | */ | |
2c33b541 | 4451 | spin_lock_irq(&b->irq_lock); |
61d3dc70 | 4452 | if (b->irq_wait && b->irq_wait->tsk != current) |
99fe4a5f CW |
4453 | /* Note that if the bottom-half is changed as we |
4454 | * are sending the wake-up, the new bottom-half will | |
4455 | * be woken by whomever made the change. We only have | |
4456 | * to worry about when we steal the irq-posted for | |
4457 | * ourself. | |
4458 | */ | |
61d3dc70 | 4459 | wake_up_process(b->irq_wait->tsk); |
2c33b541 | 4460 | spin_unlock_irq(&b->irq_lock); |
99fe4a5f | 4461 | |
754c9fd5 | 4462 | if (__i915_gem_request_completed(req, seqno)) |
7ec2c73b CW |
4463 | return true; |
4464 | } | |
688e6c72 | 4465 | |
688e6c72 CW |
4466 | return false; |
4467 | } | |
4468 | ||
0b1de5d5 CW |
4469 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
4470 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
4471 | ||
c4d3ae68 CW |
4472 | /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment, |
4473 | * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot | |
4474 | * perform the operation. To check beforehand, pass in the parameters to | |
4475 | * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits, | |
4476 | * you only need to pass in the minor offsets, page-aligned pointers are | |
4477 | * always valid. | |
4478 | * | |
4479 | * For just checking for SSE4.1, in the foreknowledge that the future use | |
4480 | * will be correctly aligned, just use i915_has_memcpy_from_wc(). | |
4481 | */ | |
4482 | #define i915_can_memcpy_from_wc(dst, src, len) \ | |
4483 | i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0) | |
4484 | ||
4485 | #define i915_has_memcpy_from_wc() \ | |
4486 | i915_memcpy_from_wc(NULL, NULL, 0) | |
4487 | ||
c58305af CW |
4488 | /* i915_mm.c */ |
4489 | int remap_io_mapping(struct vm_area_struct *vma, | |
4490 | unsigned long addr, unsigned long pfn, unsigned long size, | |
4491 | struct io_mapping *iomap); | |
4492 | ||
767a983a CW |
4493 | static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) |
4494 | { | |
4495 | if (INTEL_GEN(i915) >= 10) | |
4496 | return CNL_HWS_CSB_WRITE_INDEX; | |
4497 | else | |
4498 | return I915_HWS_CSB_WRITE_INDEX; | |
4499 | } | |
4500 | ||
1da177e4 | 4501 | #endif |