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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda | 21 | /* |
57f26649 NP |
22 | * There are a few constraints to be concerned with. |
23 | * - Real mode exceptions code/data must be located at their physical location. | |
24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
25 | * - Fixed location code must not call directly beyond the __end_interrupts | |
26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
27 | * must be used. | |
28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
29 | * virtual 0xc00... | |
30 | * - Conditional branch targets must be within +/-32K of caller. | |
31 | * | |
32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
33 | * therefore don't have to run in physically located code or rfid to | |
34 | * virtual mode kernel code. However on relocatable kernels they do have | |
35 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
36 | * the exception vectors) may be located elsewhere. | |
37 | * | |
38 | * Virtual exceptions correspond with physical, except their entry points | |
39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
40 | * offset applied. Virtual exceptions are enabled with the Alternate | |
41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
43 | * cause exceptions to be delivered in real mode. | |
44 | * | |
45 | * It's impossible to receive interrupts below 0x300 via AIL. | |
46 | * | |
47 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
49 | * | |
50 | * | |
0ebc4cda BH |
51 | * We layout physical memory as follows: |
52 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
54 | * 0x1900 - 0x3fff : Real mode trampolines | |
55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
56 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 57 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
59 | * setup code, rest of kernel. | |
e0319829 NP |
60 | * |
61 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
62 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
63 | * vectors there. | |
57f26649 NP |
64 | */ |
65 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
66 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
67 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
68 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
69 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
70 | /* | |
71 | * Data area reserved for FWNMI option. | |
72 | * This address (0x7000) is fixed by the RPA. | |
73 | * pseries and powernv need to keep the whole page from | |
74 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 75 | */ |
57f26649 NP |
76 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
77 | OPEN_TEXT_SECTION(0x8000) | |
78 | #else | |
79 | OPEN_TEXT_SECTION(0x7000) | |
80 | #endif | |
81 | ||
82 | USE_FIXED_SECTION(real_vectors) | |
83 | ||
0ebc4cda BH |
84 | /* |
85 | * This is the start of the interrupt handlers for pSeries | |
86 | * This code runs with relocation off. | |
87 | * Code from here to __end_interrupts gets copied down to real | |
88 | * address 0x100 when we are running a relocatable kernel. | |
89 | * Therefore any relative branches in this section must only | |
90 | * branch to labels in this section. | |
91 | */ | |
0ebc4cda BH |
92 | .globl __start_interrupts |
93 | __start_interrupts: | |
94 | ||
e0319829 NP |
95 | /* No virt vectors corresponding with 0x0..0x100 */ |
96 | EXC_VIRT_NONE(0x4000, 0x4100) | |
97 | ||
da2bc464 | 98 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
948cf67c BH |
99 | SET_SCRATCH0(r13) |
100 | #ifdef CONFIG_PPC_P7_NAP | |
101 | BEGIN_FTR_SECTION | |
102 | /* Running native on arch 2.06 or later, check if we are | |
77b54e9f | 103 | * waking up from nap/sleep/winkle. |
948cf67c BH |
104 | */ |
105 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
106 | rlwinm. r13,r13,47-31,30,31 |
107 | beq 9f | |
108 | ||
7cba160a | 109 | cmpwi cr3,r13,2 |
371fefd6 | 110 | GET_PACA(r13) |
5fa6b6bd | 111 | bl pnv_restore_hyp_resource |
77b54e9f | 112 | |
7cba160a SP |
113 | li r0,PNV_THREAD_RUNNING |
114 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
371fefd6 | 115 | |
3a167bea | 116 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
117 | li r0,KVM_HWTHREAD_IN_KERNEL |
118 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
119 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
120 | sync | |
121 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
122 | cmpwi r0,0 | |
123 | beq 1f | |
371fefd6 PM |
124 | b kvm_start_guest |
125 | 1: | |
126 | #endif | |
127 | ||
56548fc0 PM |
128 | /* Return SRR1 from power7_nap() */ |
129 | mfspr r3,SPRN_SRR1 | |
17065671 | 130 | blt cr3,2f |
5fa6b6bd SP |
131 | b pnv_wakeup_loss |
132 | 2: b pnv_wakeup_noloss | |
aca79d2b | 133 | |
371fefd6 | 134 | 9: |
969391c5 | 135 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 136 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
137 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
138 | NOTEST, 0x100) | |
da2bc464 | 139 | EXC_REAL_END(system_reset, 0x100, 0x200) |
582baf44 NP |
140 | EXC_VIRT_NONE(0x4100, 0x4200) |
141 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) | |
142 | ||
143 | #ifdef CONFIG_PPC_PSERIES | |
144 | /* | |
145 | * Vectors for the FWNMI option. Share common code. | |
146 | */ | |
147 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
148 | SET_SCRATCH0(r13) /* save r13 */ | |
149 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, | |
150 | NOTEST, 0x100) | |
151 | #endif /* CONFIG_PPC_PSERIES */ | |
152 | ||
0ebc4cda | 153 | |
da2bc464 | 154 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
b01c8b54 PM |
155 | /* This is moved out of line as it can be patched by FW, but |
156 | * some code path might still want to branch into the original | |
157 | * vector | |
158 | */ | |
1707dd16 | 159 | SET_SCRATCH0(r13) /* save r13 */ |
bc14c491 MS |
160 | /* |
161 | * Running native on arch 2.06 or later, we may wakeup from winkle | |
162 | * inside machine check. If yes, then last bit of HSPGR0 would be set | |
163 | * to 1. Hence clear it unconditionally. | |
1c51089f | 164 | */ |
bc14c491 MS |
165 | GET_PACA(r13) |
166 | clrrdi r13,r13,1 | |
167 | SET_PACA(r13) | |
1707dd16 | 168 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 | 169 | BEGIN_FTR_SECTION |
2513767d | 170 | b machine_check_powernv_early |
1e9b4507 | 171 | FTR_SECTION_ELSE |
1707dd16 | 172 | b machine_check_pSeries_0 |
1e9b4507 | 173 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 | 174 | EXC_REAL_END(machine_check, 0x200, 0x300) |
afcf0095 NP |
175 | EXC_VIRT_NONE(0x4200, 0x4300) |
176 | TRAMP_REAL_BEGIN(machine_check_powernv_early) | |
177 | BEGIN_FTR_SECTION | |
178 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
179 | /* | |
180 | * Register contents: | |
181 | * R13 = PACA | |
182 | * R9 = CR | |
183 | * Original R9 to R13 is saved on PACA_EXMC | |
184 | * | |
185 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
186 | * the nested MCE upto level 4 to avoid stack overflow). | |
187 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
188 | * | |
189 | * We use paca->in_mce to check whether this is the first entry or | |
190 | * nested machine check. We increment paca->in_mce to track nested | |
191 | * machine checks. | |
192 | * | |
193 | * If this is the first entry then set stack pointer to | |
194 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
195 | * stack frame on mc_emergency stack. | |
196 | * | |
197 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
198 | * checkstop if we get another machine check exception before we do | |
199 | * rfid with MSR_ME=1. | |
200 | */ | |
201 | mr r11,r1 /* Save r1 */ | |
202 | lhz r10,PACA_IN_MCE(r13) | |
203 | cmpwi r10,0 /* Are we in nested machine check */ | |
204 | bne 0f /* Yes, we are. */ | |
205 | /* First machine check entry */ | |
206 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
207 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
208 | addi r10,r10,1 /* increment paca->in_mce */ | |
209 | sth r10,PACA_IN_MCE(r13) | |
210 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
211 | cmpwi r10,4 | |
212 | bgt 2f /* Check if we hit limit of 4 */ | |
213 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
214 | std r11,0(r1) /* make stack chain pointer */ | |
215 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
216 | std r11,_NIP(r1) | |
217 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
218 | std r11,_MSR(r1) | |
219 | mfspr r11,SPRN_DAR /* Save DAR */ | |
220 | std r11,_DAR(r1) | |
221 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
222 | std r11,_DSISR(r1) | |
223 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
224 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
225 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
226 | mfmsr r11 /* get MSR value */ | |
227 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
228 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
229 | LOAD_HANDLER(r12, machine_check_handle_early) | |
230 | 1: mtspr SPRN_SRR0,r12 | |
231 | mtspr SPRN_SRR1,r11 | |
232 | rfid | |
233 | b . /* prevent speculative execution */ | |
234 | 2: | |
235 | /* Stack overflow. Stay on emergency stack and panic. | |
236 | * Keep the ME bit off while panic-ing, so that if we hit | |
237 | * another machine check we checkstop. | |
238 | */ | |
239 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
240 | ld r11,PACAKMSR(r13) | |
241 | LOAD_HANDLER(r12, unrecover_mce) | |
242 | li r10,MSR_ME | |
243 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
244 | b 1b | |
245 | b . /* prevent speculative execution */ | |
246 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
247 | ||
248 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
249 | .globl machine_check_fwnmi | |
250 | machine_check_fwnmi: | |
251 | SET_SCRATCH0(r13) /* save r13 */ | |
252 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
253 | machine_check_pSeries_0: | |
254 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
255 | /* | |
256 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
257 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
258 | * used, so nested machine check corrupts it. machine_check_common | |
259 | * enables MSR_RI. | |
260 | */ | |
261 | ld r10,PACAKMSR(r13) | |
262 | xori r10,r10,MSR_RI | |
263 | mfspr r11,SPRN_SRR0 | |
264 | LOAD_HANDLER(r12, machine_check_common) | |
265 | mtspr SPRN_SRR0,r12 | |
266 | mfspr r12,SPRN_SRR1 | |
267 | mtspr SPRN_SRR1,r10 | |
268 | rfid | |
269 | b . /* prevent speculative execution */ | |
270 | ||
271 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
272 | ||
273 | EXC_COMMON_BEGIN(machine_check_common) | |
274 | /* | |
275 | * Machine check is different because we use a different | |
276 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
277 | */ | |
278 | mfspr r10,SPRN_DAR | |
279 | std r10,PACA_EXMC+EX_DAR(r13) | |
280 | mfspr r10,SPRN_DSISR | |
281 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
282 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
283 | FINISH_NAP | |
284 | RECONCILE_IRQ_STATE(r10, r11) | |
285 | ld r3,PACA_EXMC+EX_DAR(r13) | |
286 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
287 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
288 | li r10,MSR_RI | |
289 | mtmsrd r10,1 | |
290 | std r3,_DAR(r1) | |
291 | std r4,_DSISR(r1) | |
292 | bl save_nvgprs | |
293 | addi r3,r1,STACK_FRAME_OVERHEAD | |
294 | bl machine_check_exception | |
295 | b ret_from_except | |
296 | ||
297 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
298 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
299 | li r0,MSR_RI; \ | |
300 | mfmsr r9; /* get MSR value */ \ | |
301 | andc r9,r9,r0; \ | |
302 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
303 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
304 | ld r9,_MSR(r1); \ | |
305 | mtspr SPRN_SRR1,r9; \ | |
306 | ld r3,_NIP(r1); \ | |
307 | mtspr SPRN_SRR0,r3; \ | |
308 | ld r9,_CTR(r1); \ | |
309 | mtctr r9; \ | |
310 | ld r9,_XER(r1); \ | |
311 | mtxer r9; \ | |
312 | ld r9,_LINK(r1); \ | |
313 | mtlr r9; \ | |
314 | REST_GPR(0, r1); \ | |
315 | REST_8GPRS(2, r1); \ | |
316 | REST_GPR(10, r1); \ | |
317 | ld r11,_CCR(r1); \ | |
318 | mtcr r11; \ | |
319 | /* Decrement paca->in_mce. */ \ | |
320 | lhz r12,PACA_IN_MCE(r13); \ | |
321 | subi r12,r12,1; \ | |
322 | sth r12,PACA_IN_MCE(r13); \ | |
323 | REST_GPR(11, r1); \ | |
324 | REST_2GPRS(12, r1); \ | |
325 | /* restore original r1. */ \ | |
326 | ld r1,GPR1(r1) | |
327 | ||
328 | /* | |
329 | * Handle machine check early in real mode. We come here with | |
330 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
331 | */ | |
332 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
333 | std r0,GPR0(r1) /* Save r0 */ | |
334 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
335 | bl save_nvgprs | |
336 | addi r3,r1,STACK_FRAME_OVERHEAD | |
337 | bl machine_check_early | |
338 | std r3,RESULT(r1) /* Save result */ | |
339 | ld r12,_MSR(r1) | |
340 | #ifdef CONFIG_PPC_P7_NAP | |
341 | /* | |
342 | * Check if thread was in power saving mode. We come here when any | |
343 | * of the following is true: | |
344 | * a. thread wasn't in power saving mode | |
345 | * b. thread was in power saving mode with no state loss, | |
346 | * supervisor state loss or hypervisor state loss. | |
347 | * | |
348 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
349 | */ | |
350 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
351 | beq 4f /* No, it wasn;t */ | |
352 | /* Thread was in power saving mode. Go back to nap again. */ | |
353 | cmpwi r11,2 | |
354 | blt 3f | |
355 | /* Supervisor/Hypervisor state loss */ | |
356 | li r0,1 | |
357 | stb r0,PACA_NAPSTATELOST(r13) | |
358 | 3: bl machine_check_queue_event | |
359 | MACHINE_CHECK_HANDLER_WINDUP | |
360 | GET_PACA(r13) | |
361 | ld r1,PACAR1(r13) | |
362 | /* | |
363 | * Check what idle state this CPU was in and go back to same mode | |
364 | * again. | |
365 | */ | |
366 | lbz r3,PACA_THREAD_IDLE_STATE(r13) | |
367 | cmpwi r3,PNV_THREAD_NAP | |
368 | bgt 10f | |
369 | IDLE_STATE_ENTER_SEQ(PPC_NAP) | |
370 | /* No return */ | |
371 | 10: | |
372 | cmpwi r3,PNV_THREAD_SLEEP | |
373 | bgt 2f | |
374 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) | |
375 | /* No return */ | |
376 | ||
377 | 2: | |
378 | /* | |
379 | * Go back to winkle. Please note that this thread was woken up in | |
380 | * machine check from winkle and have not restored the per-subcore | |
381 | * state. Hence before going back to winkle, set last bit of HSPGR0 | |
382 | * to 1. This will make sure that if this thread gets woken up | |
383 | * again at reset vector 0x100 then it will get chance to restore | |
384 | * the subcore state. | |
385 | */ | |
386 | ori r13,r13,1 | |
387 | SET_PACA(r13) | |
388 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) | |
389 | /* No return */ | |
390 | 4: | |
391 | #endif | |
392 | /* | |
393 | * Check if we are coming from hypervisor userspace. If yes then we | |
394 | * continue in host kernel in V mode to deliver the MC event. | |
395 | */ | |
396 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
397 | beq 5f | |
398 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
399 | bne 9f /* continue in V mode if we are. */ | |
400 | ||
401 | 5: | |
402 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
403 | /* | |
404 | * We are coming from kernel context. Check if we are coming from | |
405 | * guest. if yes, then we can continue. We will fall through | |
406 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
407 | */ | |
408 | lbz r11,HSTATE_IN_GUEST(r13) | |
409 | cmpwi r11,0 /* Check if coming from guest */ | |
410 | bne 9f /* continue if we are. */ | |
411 | #endif | |
412 | /* | |
413 | * At this point we are not sure about what context we come from. | |
414 | * Queue up the MCE event and return from the interrupt. | |
415 | * But before that, check if this is an un-recoverable exception. | |
416 | * If yes, then stay on emergency stack and panic. | |
417 | */ | |
418 | andi. r11,r12,MSR_RI | |
419 | bne 2f | |
420 | 1: mfspr r11,SPRN_SRR0 | |
421 | LOAD_HANDLER(r10,unrecover_mce) | |
422 | mtspr SPRN_SRR0,r10 | |
423 | ld r10,PACAKMSR(r13) | |
424 | /* | |
425 | * We are going down. But there are chances that we might get hit by | |
426 | * another MCE during panic path and we may run into unstable state | |
427 | * with no way out. Hence, turn ME bit off while going down, so that | |
428 | * when another MCE is hit during panic path, system will checkstop | |
429 | * and hypervisor will get restarted cleanly by SP. | |
430 | */ | |
431 | li r3,MSR_ME | |
432 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
433 | mtspr SPRN_SRR1,r10 | |
434 | rfid | |
435 | b . | |
436 | 2: | |
437 | /* | |
438 | * Check if we have successfully handled/recovered from error, if not | |
439 | * then stay on emergency stack and panic. | |
440 | */ | |
441 | ld r3,RESULT(r1) /* Load result */ | |
442 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
443 | ||
444 | beq 1b /* if !handled then panic */ | |
445 | /* | |
446 | * Return from MC interrupt. | |
447 | * Queue up the MCE event so that we can log it later, while | |
448 | * returning from kernel or opal call. | |
449 | */ | |
450 | bl machine_check_queue_event | |
451 | MACHINE_CHECK_HANDLER_WINDUP | |
452 | rfid | |
453 | 9: | |
454 | /* Deliver the machine check to host kernel in V mode. */ | |
455 | MACHINE_CHECK_HANDLER_WINDUP | |
456 | b machine_check_pSeries | |
457 | ||
458 | EXC_COMMON_BEGIN(unrecover_mce) | |
459 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
460 | addi r3,r1,STACK_FRAME_OVERHEAD | |
461 | bl machine_check_exception | |
462 | /* | |
463 | * We will not reach here. Even if we did, there is no way out. Call | |
464 | * unrecoverable_exception and die. | |
465 | */ | |
466 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
467 | bl unrecoverable_exception | |
468 | b 1b | |
469 | ||
0ebc4cda | 470 | |
da2bc464 | 471 | EXC_REAL(data_access, 0x300, 0x380) |
80795e6c NP |
472 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) |
473 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) | |
474 | ||
475 | EXC_COMMON_BEGIN(data_access_common) | |
476 | /* | |
477 | * Here r13 points to the paca, r9 contains the saved CR, | |
478 | * SRR0 and SRR1 are saved in r11 and r12, | |
479 | * r9 - r13 are saved in paca->exgen. | |
480 | */ | |
481 | mfspr r10,SPRN_DAR | |
482 | std r10,PACA_EXGEN+EX_DAR(r13) | |
483 | mfspr r10,SPRN_DSISR | |
484 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
485 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
486 | RECONCILE_IRQ_STATE(r10, r11) | |
487 | ld r12,_MSR(r1) | |
488 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
489 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
490 | li r5,0x300 | |
491 | std r3,_DAR(r1) | |
492 | std r4,_DSISR(r1) | |
493 | BEGIN_MMU_FTR_SECTION | |
494 | b do_hash_page /* Try to handle as hpte fault */ | |
495 | MMU_FTR_SECTION_ELSE | |
496 | b handle_page_fault | |
497 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
498 | ||
0ebc4cda | 499 | |
da2bc464 | 500 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
673b189a | 501 | SET_SCRATCH0(r13) |
1707dd16 | 502 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 503 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
504 | std r3,PACA_EXSLB+EX_R3(r13) |
505 | mfspr r3,SPRN_DAR | |
b01c8b54 | 506 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 507 | crset 4*cr6+eq |
0ebc4cda | 508 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 509 | b slb_miss_realmode |
0ebc4cda BH |
510 | #else |
511 | /* | |
ad0289e4 | 512 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
513 | * because the distance from here to there depends on where |
514 | * the kernel ends up being put. | |
515 | */ | |
516 | mfctr r11 | |
ad0289e4 | 517 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
518 | mtctr r10 |
519 | bctr | |
520 | #endif | |
da2bc464 | 521 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
0ebc4cda | 522 | |
2b9af6e4 NP |
523 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) |
524 | SET_SCRATCH0(r13) | |
525 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
526 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
527 | std r3,PACA_EXSLB+EX_R3(r13) | |
528 | mfspr r3,SPRN_DAR | |
529 | mfspr r12,SPRN_SRR1 | |
530 | crset 4*cr6+eq | |
531 | #ifndef CONFIG_RELOCATABLE | |
532 | b slb_miss_realmode | |
533 | #else | |
534 | /* | |
535 | * We can't just use a direct branch to slb_miss_realmode | |
536 | * because the distance from here to there depends on where | |
537 | * the kernel ends up being put. | |
538 | */ | |
539 | mfctr r11 | |
540 | LOAD_HANDLER(r10, slb_miss_realmode) | |
541 | mtctr r10 | |
542 | bctr | |
543 | #endif | |
544 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) | |
545 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) | |
546 | ||
547 | ||
da2bc464 | 548 | EXC_REAL(instruction_access, 0x400, 0x480) |
27ce77df NP |
549 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
550 | TRAMP_KVM(PACA_EXGEN, 0x400) | |
551 | ||
552 | EXC_COMMON_BEGIN(instruction_access_common) | |
553 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
554 | RECONCILE_IRQ_STATE(r10, r11) | |
555 | ld r12,_MSR(r1) | |
556 | ld r3,_NIP(r1) | |
557 | andis. r4,r12,0x5820 | |
558 | li r5,0x400 | |
559 | std r3,_DAR(r1) | |
560 | std r4,_DSISR(r1) | |
561 | BEGIN_MMU_FTR_SECTION | |
562 | b do_hash_page /* Try to handle as hpte fault */ | |
563 | MMU_FTR_SECTION_ELSE | |
564 | b handle_page_fault | |
565 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
566 | ||
0ebc4cda | 567 | |
da2bc464 | 568 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
673b189a | 569 | SET_SCRATCH0(r13) |
1707dd16 | 570 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 571 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
572 | std r3,PACA_EXSLB+EX_R3(r13) |
573 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 574 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 575 | crclr 4*cr6+eq |
0ebc4cda | 576 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 577 | b slb_miss_realmode |
0ebc4cda BH |
578 | #else |
579 | mfctr r11 | |
ad0289e4 | 580 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
581 | mtctr r10 |
582 | bctr | |
583 | #endif | |
da2bc464 | 584 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
0ebc4cda | 585 | |
8d04631a NP |
586 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) |
587 | SET_SCRATCH0(r13) | |
588 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
589 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
590 | std r3,PACA_EXSLB+EX_R3(r13) | |
591 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
592 | mfspr r12,SPRN_SRR1 | |
593 | crclr 4*cr6+eq | |
594 | #ifndef CONFIG_RELOCATABLE | |
595 | b slb_miss_realmode | |
596 | #else | |
597 | mfctr r11 | |
598 | LOAD_HANDLER(r10, slb_miss_realmode) | |
599 | mtctr r10 | |
600 | bctr | |
601 | #endif | |
602 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) | |
603 | TRAMP_KVM(PACA_EXSLB, 0x480) | |
604 | ||
605 | ||
606 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ | |
607 | EXC_COMMON_BEGIN(slb_miss_realmode) | |
608 | /* | |
609 | * r13 points to the PACA, r9 contains the saved CR, | |
610 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
611 | * r3 has the faulting address | |
612 | * r9 - r13 are saved in paca->exslb. | |
613 | * r3 is saved in paca->slb_r3 | |
614 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss | |
615 | * We assume we aren't going to take any exceptions during this | |
616 | * procedure. | |
617 | */ | |
618 | mflr r10 | |
619 | #ifdef CONFIG_RELOCATABLE | |
620 | mtctr r11 | |
621 | #endif | |
622 | ||
623 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
624 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
625 | std r3,PACA_EXSLB+EX_DAR(r13) | |
626 | ||
627 | crset 4*cr0+eq | |
628 | #ifdef CONFIG_PPC_STD_MMU_64 | |
629 | BEGIN_MMU_FTR_SECTION | |
630 | bl slb_allocate_realmode | |
631 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) | |
632 | #endif | |
633 | ||
634 | ld r10,PACA_EXSLB+EX_LR(r13) | |
635 | ld r3,PACA_EXSLB+EX_R3(r13) | |
636 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
637 | mtlr r10 | |
638 | ||
639 | beq 8f /* if bad address, make full stack frame */ | |
640 | ||
641 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
642 | beq- 2f | |
643 | ||
644 | /* All done -- return from exception. */ | |
645 | ||
646 | .machine push | |
647 | .machine "power4" | |
648 | mtcrf 0x80,r9 | |
649 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
650 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
651 | .machine pop | |
652 | ||
653 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
654 | ld r9,PACA_EXSLB+EX_R9(r13) | |
655 | ld r10,PACA_EXSLB+EX_R10(r13) | |
656 | ld r11,PACA_EXSLB+EX_R11(r13) | |
657 | ld r12,PACA_EXSLB+EX_R12(r13) | |
658 | ld r13,PACA_EXSLB+EX_R13(r13) | |
659 | rfid | |
660 | b . /* prevent speculative execution */ | |
661 | ||
662 | 2: mfspr r11,SPRN_SRR0 | |
663 | LOAD_HANDLER(r10,unrecov_slb) | |
664 | mtspr SPRN_SRR0,r10 | |
665 | ld r10,PACAKMSR(r13) | |
666 | mtspr SPRN_SRR1,r10 | |
667 | rfid | |
668 | b . | |
669 | ||
670 | 8: mfspr r11,SPRN_SRR0 | |
671 | LOAD_HANDLER(r10,bad_addr_slb) | |
672 | mtspr SPRN_SRR0,r10 | |
673 | ld r10,PACAKMSR(r13) | |
674 | mtspr SPRN_SRR1,r10 | |
675 | rfid | |
676 | b . | |
677 | ||
678 | EXC_COMMON_BEGIN(unrecov_slb) | |
679 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
680 | RECONCILE_IRQ_STATE(r10, r11) | |
681 | bl save_nvgprs | |
682 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
683 | bl unrecoverable_exception | |
684 | b 1b | |
685 | ||
686 | EXC_COMMON_BEGIN(bad_addr_slb) | |
687 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
688 | RECONCILE_IRQ_STATE(r10, r11) | |
689 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
690 | std r3, _DAR(r1) | |
691 | beq cr6, 2f | |
692 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
693 | std r10, _TRAP(r1) | |
694 | 2: bl save_nvgprs | |
695 | addi r3, r1, STACK_FRAME_OVERHEAD | |
696 | bl slb_miss_bad_addr | |
697 | b ret_from_except | |
698 | ||
da2bc464 | 699 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
b3e6b5df | 700 | .globl hardware_interrupt_hv; |
b3e6b5df | 701 | hardware_interrupt_hv: |
a5d4f3ad | 702 | BEGIN_FTR_SECTION |
da2bc464 | 703 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 704 | EXC_HV, SOFTEN_TEST_HV) |
da2bc464 | 705 | do_kvm_H0x500: |
b01c8b54 | 706 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
de56a948 | 707 | FTR_SECTION_ELSE |
da2bc464 | 708 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 709 | EXC_STD, SOFTEN_TEST_PR) |
da2bc464 | 710 | do_kvm_0x500: |
de56a948 | 711 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 712 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
da2bc464 ME |
713 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
714 | ||
c138e588 NP |
715 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
716 | .globl hardware_interrupt_relon_hv; | |
717 | hardware_interrupt_relon_hv: | |
718 | BEGIN_FTR_SECTION | |
719 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) | |
720 | FTR_SECTION_ELSE | |
721 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) | |
722 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
723 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) | |
724 | ||
725 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) | |
726 | ||
727 | ||
da2bc464 | 728 | EXC_REAL(alignment, 0x600, 0x700) |
f9aa6714 | 729 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) |
da2bc464 | 730 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
731 | EXC_COMMON_BEGIN(alignment_common) |
732 | mfspr r10,SPRN_DAR | |
733 | std r10,PACA_EXGEN+EX_DAR(r13) | |
734 | mfspr r10,SPRN_DSISR | |
735 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
736 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
737 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
738 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
739 | std r3,_DAR(r1) | |
740 | std r4,_DSISR(r1) | |
741 | bl save_nvgprs | |
742 | RECONCILE_IRQ_STATE(r10, r11) | |
743 | addi r3,r1,STACK_FRAME_OVERHEAD | |
744 | bl alignment_exception | |
745 | b ret_from_except | |
746 | ||
da2bc464 ME |
747 | |
748 | EXC_REAL(program_check, 0x700, 0x800) | |
11e87346 | 749 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) |
da2bc464 | 750 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 NP |
751 | EXC_COMMON_BEGIN(program_check_common) |
752 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
753 | bl save_nvgprs | |
754 | RECONCILE_IRQ_STATE(r10, r11) | |
755 | addi r3,r1,STACK_FRAME_OVERHEAD | |
756 | bl program_check_exception | |
757 | b ret_from_except | |
758 | ||
b01c8b54 | 759 | |
da2bc464 | 760 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
c78d9b97 | 761 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) |
da2bc464 | 762 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
763 | EXC_COMMON_BEGIN(fp_unavailable_common) |
764 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
765 | bne 1f /* if from user, just load it up */ | |
766 | bl save_nvgprs | |
767 | RECONCILE_IRQ_STATE(r10, r11) | |
768 | addi r3,r1,STACK_FRAME_OVERHEAD | |
769 | bl kernel_fp_unavailable_exception | |
770 | BUG_OPCODE | |
771 | 1: | |
772 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
773 | BEGIN_FTR_SECTION | |
774 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
775 | * transaction), go do TM stuff | |
776 | */ | |
777 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
778 | bne- 2f | |
779 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
780 | #endif | |
781 | bl load_up_fpu | |
782 | b fast_exception_return | |
783 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
784 | 2: /* User process was in a transaction */ | |
785 | bl save_nvgprs | |
786 | RECONCILE_IRQ_STATE(r10, r11) | |
787 | addi r3,r1,STACK_FRAME_OVERHEAD | |
788 | bl fp_unavailable_tm | |
789 | b ret_from_except | |
790 | #endif | |
791 | ||
a5d4f3ad | 792 | |
da2bc464 | 793 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
39c0da57 NP |
794 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) |
795 | TRAMP_KVM(PACA_EXGEN, 0x900) | |
796 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
797 | ||
a485c709 | 798 | |
da2bc464 | 799 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
facc6d74 NP |
800 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) |
801 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) | |
802 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
803 | ||
a5d4f3ad | 804 | |
da2bc464 | 805 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
ca243163 | 806 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) |
da2bc464 | 807 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
808 | #ifdef CONFIG_PPC_DOORBELL |
809 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
810 | #else | |
811 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
812 | #endif | |
813 | ||
0ebc4cda | 814 | |
da2bc464 | 815 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
341215dc | 816 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) |
da2bc464 | 817 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
818 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
819 | ||
da2bc464 | 820 | |
d807ad37 NP |
821 | #define LOAD_SYSCALL_HANDLER(reg) \ |
822 | ld reg,PACAKBASE(r13); \ | |
823 | ori reg,reg,(ABS_ADDR(system_call_common))@l; | |
824 | ||
825 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ | |
826 | #define SYSCALL_PSERIES_1 \ | |
827 | BEGIN_FTR_SECTION \ | |
828 | cmpdi r0,0x1ebe ; \ | |
829 | beq- 1f ; \ | |
830 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
831 | mr r9,r13 ; \ | |
832 | GET_PACA(r13) ; \ | |
833 | mfspr r11,SPRN_SRR0 ; \ | |
834 | 0: | |
835 | ||
836 | #define SYSCALL_PSERIES_2_RFID \ | |
837 | mfspr r12,SPRN_SRR1 ; \ | |
838 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
839 | mtspr SPRN_SRR0,r10 ; \ | |
840 | ld r10,PACAKMSR(r13) ; \ | |
841 | mtspr SPRN_SRR1,r10 ; \ | |
842 | rfid ; \ | |
843 | b . ; /* prevent speculative execution */ | |
844 | ||
845 | #define SYSCALL_PSERIES_3 \ | |
846 | /* Fast LE/BE switch system call */ \ | |
847 | 1: mfspr r12,SPRN_SRR1 ; \ | |
848 | xori r12,r12,MSR_LE ; \ | |
849 | mtspr SPRN_SRR1,r12 ; \ | |
850 | rfid ; /* return to userspace */ \ | |
851 | b . ; /* prevent speculative execution */ | |
852 | ||
853 | #if defined(CONFIG_RELOCATABLE) | |
854 | /* | |
855 | * We can't branch directly so we do it via the CTR which | |
856 | * is volatile across system calls. | |
857 | */ | |
858 | #define SYSCALL_PSERIES_2_DIRECT \ | |
859 | LOAD_SYSCALL_HANDLER(r12) ; \ | |
860 | mtctr r12 ; \ | |
861 | mfspr r12,SPRN_SRR1 ; \ | |
862 | li r10,MSR_RI ; \ | |
863 | mtmsrd r10,1 ; \ | |
864 | bctr ; | |
865 | #else | |
866 | /* We can branch directly */ | |
867 | #define SYSCALL_PSERIES_2_DIRECT \ | |
868 | mfspr r12,SPRN_SRR1 ; \ | |
869 | li r10,MSR_RI ; \ | |
870 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
871 | b system_call_common ; | |
872 | #endif | |
873 | ||
da2bc464 | 874 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) |
8b91a255 SW |
875 | /* |
876 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
877 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
878 | * code to save that value into the guest state (it is the guest's PPR | |
879 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
880 | * already saved the PPR. | |
881 | */ | |
b01c8b54 PM |
882 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
883 | SET_SCRATCH0(r13) | |
884 | GET_PACA(r13) | |
885 | std r9,PACA_EXGEN+EX_R9(r13) | |
8b91a255 SW |
886 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
887 | HMT_MEDIUM; | |
b01c8b54 | 888 | std r10,PACA_EXGEN+EX_R10(r13) |
8b91a255 | 889 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
b01c8b54 | 890 | mfcr r9 |
da2bc464 | 891 | KVMTEST_PR(0xc00) |
b01c8b54 | 892 | GET_SCRATCH0(r13) |
8b91a255 SW |
893 | #else |
894 | HMT_MEDIUM; | |
b01c8b54 | 895 | #endif |
742415d6 MN |
896 | SYSCALL_PSERIES_1 |
897 | SYSCALL_PSERIES_2_RFID | |
898 | SYSCALL_PSERIES_3 | |
da2bc464 ME |
899 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
900 | ||
d807ad37 NP |
901 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) |
902 | HMT_MEDIUM | |
903 | SYSCALL_PSERIES_1 | |
904 | SYSCALL_PSERIES_2_DIRECT | |
905 | SYSCALL_PSERIES_3 | |
906 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) | |
907 | ||
da2bc464 ME |
908 | TRAMP_KVM(PACA_EXGEN, 0xc00) |
909 | ||
d807ad37 | 910 | |
da2bc464 | 911 | EXC_REAL(single_step, 0xd00, 0xe00) |
bc6675c6 | 912 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
da2bc464 | 913 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 914 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 915 | |
a33532af | 916 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
e0319829 | 917 | EXC_VIRT_NONE(0x4e00, 0x4e20) |
f5c32c1d NP |
918 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
919 | EXC_COMMON_BEGIN(h_data_storage_common) | |
920 | mfspr r10,SPRN_HDAR | |
921 | std r10,PACA_EXGEN+EX_DAR(r13) | |
922 | mfspr r10,SPRN_HDSISR | |
923 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
924 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
925 | bl save_nvgprs | |
926 | RECONCILE_IRQ_STATE(r10, r11) | |
927 | addi r3,r1,STACK_FRAME_OVERHEAD | |
928 | bl unknown_exception | |
929 | b ret_from_except | |
f5c32c1d | 930 | |
1707dd16 | 931 | |
a33532af | 932 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
e0319829 | 933 | EXC_VIRT_NONE(0x4e20, 0x4e40) |
82517cab NP |
934 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
935 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
936 | ||
1707dd16 | 937 | |
a33532af NP |
938 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
939 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60, 0xe40) | |
031b4026 NP |
940 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
941 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
942 | ||
1707dd16 | 943 | |
e0319829 NP |
944 | /* |
945 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
946 | * first, and then eventaully from there to the trampoline to get into virtual | |
947 | * mode. | |
948 | */ | |
da2bc464 | 949 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
62f9b03b | 950 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
e0319829 | 951 | EXC_VIRT_NONE(0x4e60, 0x4e80) |
62f9b03b NP |
952 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
953 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
954 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
955 | mr r10,r1 /* Save r1 */ | |
956 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
957 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
958 | std r9,_CCR(r1) /* save CR in stackframe */ | |
959 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
960 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
961 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
962 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
963 | std r10,0(r1) /* make stack chain pointer */ | |
964 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
965 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
966 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
967 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
968 | addi r3,r1,STACK_FRAME_OVERHEAD | |
969 | bl hmi_exception_realmode | |
970 | /* Windup the stack. */ | |
971 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
972 | ld r9,_MSR(r1) | |
973 | mtspr SPRN_HSRR1,r9 | |
974 | ld r3,_NIP(r1) | |
975 | mtspr SPRN_HSRR0,r3 | |
976 | ld r9,_CTR(r1) | |
977 | mtctr r9 | |
978 | ld r9,_XER(r1) | |
979 | mtxer r9 | |
980 | ld r9,_LINK(r1) | |
981 | mtlr r9 | |
982 | REST_GPR(0, r1) | |
983 | REST_8GPRS(2, r1) | |
984 | REST_GPR(10, r1) | |
985 | ld r11,_CCR(r1) | |
986 | mtcr r11 | |
987 | REST_GPR(11, r1) | |
988 | REST_2GPRS(12, r1) | |
989 | /* restore original r1. */ | |
990 | ld r1,GPR1(r1) | |
991 | ||
992 | /* | |
993 | * Go to virtual mode and pull the HMI event information from | |
994 | * firmware. | |
995 | */ | |
996 | .globl hmi_exception_after_realmode | |
997 | hmi_exception_after_realmode: | |
998 | SET_SCRATCH0(r13) | |
999 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
1000 | b tramp_real_hmi_exception | |
1001 | ||
1002 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) | |
1003 | ||
1707dd16 | 1004 | |
a33532af NP |
1005 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
1006 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0, 0xe80) | |
9bcb81bf NP |
1007 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1008 | #ifdef CONFIG_PPC_DOORBELL | |
1009 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1010 | #else | |
1011 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1012 | #endif | |
1013 | ||
0ebc4cda | 1014 | |
a33532af NP |
1015 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
1016 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0, 0xea0) | |
74408776 NP |
1017 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1018 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1019 | ||
9baaef0a | 1020 | |
da2bc464 | 1021 | EXC_REAL_NONE(0xec0, 0xf00) |
bda7fea2 NP |
1022 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
1023 | ||
0ebc4cda | 1024 | |
a33532af NP |
1025 | EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
1026 | EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20, 0xf00) | |
b1c7f150 NP |
1027 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1028 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1029 | ||
0ebc4cda | 1030 | |
a33532af NP |
1031 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
1032 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40, 0xf20) | |
d1a0ca9c NP |
1033 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1034 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1035 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1036 | #ifdef CONFIG_ALTIVEC | |
1037 | BEGIN_FTR_SECTION | |
1038 | beq 1f | |
1039 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1040 | BEGIN_FTR_SECTION_NESTED(69) | |
1041 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1042 | * transaction), go do TM stuff | |
1043 | */ | |
1044 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1045 | bne- 2f | |
1046 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1047 | #endif | |
1048 | bl load_up_altivec | |
1049 | b fast_exception_return | |
1050 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1051 | 2: /* User process was in a transaction */ | |
1052 | bl save_nvgprs | |
1053 | RECONCILE_IRQ_STATE(r10, r11) | |
1054 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1055 | bl altivec_unavailable_tm | |
1056 | b ret_from_except | |
1057 | #endif | |
1058 | 1: | |
1059 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1060 | #endif | |
1061 | bl save_nvgprs | |
1062 | RECONCILE_IRQ_STATE(r10, r11) | |
1063 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1064 | bl altivec_unavailable_exception | |
1065 | b ret_from_except | |
1066 | ||
0ebc4cda | 1067 | |
a33532af NP |
1068 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
1069 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60, 0xf40) | |
792cbddd NP |
1070 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1071 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1072 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1073 | #ifdef CONFIG_VSX | |
1074 | BEGIN_FTR_SECTION | |
1075 | beq 1f | |
1076 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1077 | BEGIN_FTR_SECTION_NESTED(69) | |
1078 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1079 | * transaction), go do TM stuff | |
1080 | */ | |
1081 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1082 | bne- 2f | |
1083 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1084 | #endif | |
1085 | b load_up_vsx | |
1086 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1087 | 2: /* User process was in a transaction */ | |
1088 | bl save_nvgprs | |
1089 | RECONCILE_IRQ_STATE(r10, r11) | |
1090 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1091 | bl vsx_unavailable_tm | |
1092 | b ret_from_except | |
1093 | #endif | |
1094 | 1: | |
1095 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1096 | #endif | |
1097 | bl save_nvgprs | |
1098 | RECONCILE_IRQ_STATE(r10, r11) | |
1099 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1100 | bl vsx_unavailable_exception | |
1101 | b ret_from_except | |
1102 | ||
da2bc464 | 1103 | |
a33532af NP |
1104 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) |
1105 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80, 0xf60) | |
1134713c NP |
1106 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1107 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1108 | ||
da2bc464 | 1109 | |
a33532af NP |
1110 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) |
1111 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0, 0xf80) | |
14b0072c NP |
1112 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1113 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1114 | ||
da2bc464 ME |
1115 | |
1116 | EXC_REAL_NONE(0xfa0, 0x1200) | |
e46b964c | 1117 | EXC_VIRT_NONE(0x4fa0, 0x5200) |
d0c0c9a1 | 1118 | |
0ebc4cda | 1119 | #ifdef CONFIG_CBE_RAS |
da2bc464 | 1120 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
ff1b3206 | 1121 | EXC_VIRT_NONE(0x5200, 0x5300) |
da2bc464 | 1122 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1123 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 ME |
1124 | #else /* CONFIG_CBE_RAS */ |
1125 | EXC_REAL_NONE(0x1200, 0x1300) | |
e0319829 | 1126 | EXC_VIRT_NONE(0x5200, 0x5300) |
da2bc464 | 1127 | #endif |
b01c8b54 | 1128 | |
ff1b3206 | 1129 | |
da2bc464 | 1130 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
4e96dbbf | 1131 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) |
da2bc464 | 1132 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1133 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1134 | ||
e0319829 NP |
1135 | EXC_REAL_NONE(0x1400, 0x1500) |
1136 | EXC_VIRT_NONE(0x5400, 0x5500) | |
da2bc464 ME |
1137 | |
1138 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) | |
b92a66a6 | 1139 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1140 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1141 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1142 | |
1143 | #ifdef CONFIG_PPC_DENORMALISATION | |
1144 | mfspr r10,SPRN_HSRR1 | |
1145 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
afcf0095 NP |
1146 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
1147 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
1148 | bne+ denorm_assist | |
1149 | #endif | |
1e9b4507 | 1150 | |
afcf0095 NP |
1151 | KVMTEST_PR(0x1500) |
1152 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
1153 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) | |
a74599a5 | 1154 | |
d7e89849 NP |
1155 | #ifdef CONFIG_PPC_DENORMALISATION |
1156 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) | |
1157 | b exc_real_0x1500_denorm_exception_hv | |
1158 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) | |
1159 | #else | |
1160 | EXC_VIRT_NONE(0x5500, 0x5600) | |
afcf0095 NP |
1161 | #endif |
1162 | ||
d7e89849 | 1163 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
b01c8b54 | 1164 | |
b92a66a6 | 1165 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1166 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1167 | BEGIN_FTR_SECTION |
1168 | /* | |
1169 | * To denormalise we need to move a copy of the register to itself. | |
1170 | * For POWER6 do that here for all FP regs. | |
1171 | */ | |
1172 | mfmsr r10 | |
1173 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1174 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1175 | mtmsrd r10 | |
1176 | sync | |
d7c67fb1 MN |
1177 | |
1178 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1179 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1180 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1181 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1182 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1183 | FMR32(0) | |
1184 | ||
b92a66a6 MN |
1185 | FTR_SECTION_ELSE |
1186 | /* | |
1187 | * To denormalise we need to move a copy of the register to itself. | |
1188 | * For POWER7 do that here for the first 32 VSX registers only. | |
1189 | */ | |
1190 | mfmsr r10 | |
1191 | oris r10,r10,MSR_VSX@h | |
1192 | mtmsrd r10 | |
1193 | sync | |
d7c67fb1 MN |
1194 | |
1195 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1196 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1197 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1198 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1199 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1200 | XVCPSGNDP32(0) | |
1201 | ||
b92a66a6 | 1202 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1203 | |
1204 | BEGIN_FTR_SECTION | |
1205 | b denorm_done | |
1206 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1207 | /* | |
1208 | * To denormalise we need to move a copy of the register to itself. | |
1209 | * For POWER8 we need to do that for all 64 VSX registers | |
1210 | */ | |
1211 | XVCPSGNDP32(32) | |
1212 | denorm_done: | |
b92a66a6 MN |
1213 | mtspr SPRN_HSRR0,r11 |
1214 | mtcrf 0x80,r9 | |
1215 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1216 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1217 | BEGIN_FTR_SECTION |
1218 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1219 | mtspr SPRN_CFAR,r10 | |
1220 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1221 | ld r10,PACA_EXGEN+EX_R10(r13) |
1222 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1223 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1224 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1225 | HRFID | |
1226 | b . | |
1227 | #endif | |
1228 | ||
d7e89849 NP |
1229 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
1230 | ||
1231 | ||
1232 | #ifdef CONFIG_CBE_RAS | |
1233 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) | |
69a79344 | 1234 | EXC_VIRT_NONE(0x5600, 0x5700) |
d7e89849 | 1235 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1236 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 NP |
1237 | #else /* CONFIG_CBE_RAS */ |
1238 | EXC_REAL_NONE(0x1600, 0x1700) | |
e0319829 | 1239 | EXC_VIRT_NONE(0x5600, 0x5700) |
d7e89849 NP |
1240 | #endif |
1241 | ||
69a79344 | 1242 | |
d7e89849 | 1243 | EXC_REAL(altivec_assist, 0x1700, 0x1800) |
b51c079e | 1244 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) |
d7e89849 | 1245 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1246 | #ifdef CONFIG_ALTIVEC |
1247 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1248 | #else | |
1249 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1250 | #endif | |
1251 | ||
d7e89849 NP |
1252 | |
1253 | #ifdef CONFIG_CBE_RAS | |
1254 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) | |
3965f8ab | 1255 | EXC_VIRT_NONE(0x5800, 0x5900) |
d7e89849 | 1256 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1257 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 NP |
1258 | #else /* CONFIG_CBE_RAS */ |
1259 | EXC_REAL_NONE(0x1800, 0x1900) | |
e0319829 | 1260 | EXC_VIRT_NONE(0x5800, 0x5900) |
d7e89849 NP |
1261 | #endif |
1262 | ||
1263 | ||
0ebc4cda | 1264 | /* |
fe9e1d54 IM |
1265 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1266 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1267 | * - If it was a doorbell we return immediately since doorbells are edge | |
1268 | * triggered and won't automatically refire. | |
0869b6fd MS |
1269 | * - If it was a HMI we return immediately since we handled it in realmode |
1270 | * and it won't refire. | |
fe9e1d54 IM |
1271 | * - else we hard disable and return. |
1272 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 1273 | */ |
7230c564 BH |
1274 | #define MASKED_INTERRUPT(_H) \ |
1275 | masked_##_H##interrupt: \ | |
1276 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1277 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1278 | or r11,r11,r10; \ | |
1279 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1280 | cmpwi r10,PACA_IRQ_DEC; \ |
1281 | bne 1f; \ | |
7230c564 BH |
1282 | lis r10,0x7fff; \ |
1283 | ori r10,r10,0xffff; \ | |
1284 | mtspr SPRN_DEC,r10; \ | |
1285 | b 2f; \ | |
fe9e1d54 | 1286 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
1287 | beq 2f; \ |
1288 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
1289 | beq 2f; \ |
1290 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
1291 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
1292 | rotldi r10,r10,16; \ | |
1293 | mtspr SPRN_##_H##SRR1,r10; \ | |
1294 | 2: mtcrf 0x80,r9; \ | |
1295 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
1296 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1297 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
1298 | GET_SCRATCH0(r13); \ | |
1299 | ##_H##rfid; \ | |
0ebc4cda | 1300 | b . |
57f26649 NP |
1301 | |
1302 | /* | |
1303 | * Real mode exceptions actually use this too, but alternate | |
1304 | * instruction code patches (which end up in the common .text area) | |
1305 | * cannot reach these if they are put there. | |
1306 | */ | |
1307 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1308 | MASKED_INTERRUPT() |
1309 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1310 | |
4f6c11db | 1311 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1312 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1313 | /* |
1314 | * Here all GPRs are unchanged from when the interrupt happened | |
1315 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1316 | */ | |
1317 | mfspr r13, SPRN_SRR0 | |
1318 | addi r13, r13, 4 | |
1319 | mtspr SPRN_SRR0, r13 | |
1320 | GET_SCRATCH0(r13) | |
1321 | rfid | |
1322 | b . | |
1323 | ||
da2bc464 | 1324 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1325 | /* |
1326 | * Here all GPRs are unchanged from when the interrupt happened | |
1327 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1328 | */ | |
1329 | mfspr r13, SPRN_HSRR0 | |
1330 | addi r13, r13, 4 | |
1331 | mtspr SPRN_HSRR0, r13 | |
1332 | GET_SCRATCH0(r13) | |
1333 | hrfid | |
1334 | b . | |
1335 | #endif | |
1336 | ||
0ebc4cda | 1337 | /* |
057b6d7e HB |
1338 | * Ensure that any handlers that get invoked from the exception prologs |
1339 | * above are below the first 64KB (0x10000) of the kernel image because | |
1340 | * the prologs assemble the addresses of these handlers using the | |
1341 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1342 | */ |
1343 | ||
1344 | /*** Common interrupt handlers ***/ | |
1345 | ||
0ebc4cda | 1346 | |
c1fb6816 MN |
1347 | /* |
1348 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1349 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1350 | * it. Addresses are the same as the original interrupt addresses, but | |
1351 | * offset by 0xc000000000004000. | |
1352 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1353 | * KVM: None of these traps are from the guest ; anything that escalated | |
1354 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1355 | */ | |
1356 | ||
1357 | /* | |
1358 | * This uses the standard macro, since the original 0x300 vector | |
1359 | * only has extra guff for STAB-based processors -- which never | |
1360 | * come here. | |
1361 | */ | |
da2bc464 | 1362 | |
57f26649 | 1363 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1364 | b __ppc64_runlatch_on |
fe1952fc | 1365 | |
57f26649 | 1366 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1367 | /* |
1368 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1369 | * handlers, so that they are copied to real address 0x100 when running | |
1370 | * a relocatable kernel. This ensures they can be reached from the short | |
1371 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1372 | * directly, without using LOAD_HANDLER(). | |
1373 | */ | |
1374 | .align 7 | |
1375 | .globl __end_interrupts | |
1376 | __end_interrupts: | |
57f26649 | 1377 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1378 | |
087aa036 | 1379 | #ifdef CONFIG_PPC_970_NAP |
da2bc464 | 1380 | TRAMP_REAL_BEGIN(power4_fixup_nap) |
087aa036 CG |
1381 | andc r9,r9,r10 |
1382 | std r9,TI_LOCAL_FLAGS(r11) | |
1383 | ld r10,_LINK(r1) /* make idle task do the */ | |
1384 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1385 | blr | |
1386 | #endif | |
1387 | ||
57f26649 NP |
1388 | CLOSE_FIXED_SECTION(real_vectors); |
1389 | CLOSE_FIXED_SECTION(real_trampolines); | |
1390 | CLOSE_FIXED_SECTION(virt_vectors); | |
1391 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1392 | ||
1393 | USE_TEXT_SECTION() | |
1394 | ||
0ebc4cda BH |
1395 | /* |
1396 | * Hash table stuff | |
1397 | */ | |
1398 | .align 7 | |
6a3bab90 | 1399 | do_hash_page: |
caca285e | 1400 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1401 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1402 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1403 | andis. r0,r4,DSISR_DABRMATCH@h |
1404 | bne- handle_dabr_fault | |
9778b696 | 1405 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1406 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1407 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1408 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1409 | |
1410 | /* | |
1411 | * r3 contains the faulting address | |
106713a1 | 1412 | * r4 msr |
0ebc4cda | 1413 | * r5 contains the trap number |
aefa5688 | 1414 | * r6 contains dsisr |
0ebc4cda | 1415 | * |
7230c564 | 1416 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1417 | */ |
106713a1 | 1418 | mr r4,r12 |
aefa5688 | 1419 | ld r6,_DSISR(r1) |
106713a1 AK |
1420 | bl __hash_page /* build HPTE if possible */ |
1421 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1422 | |
7230c564 | 1423 | /* Success */ |
0ebc4cda | 1424 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1425 | |
7230c564 BH |
1426 | /* Error */ |
1427 | blt- 13f | |
caca285e | 1428 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1429 | |
0ebc4cda BH |
1430 | /* Here we have a page fault that hash_page can't handle. */ |
1431 | handle_page_fault: | |
0ebc4cda BH |
1432 | 11: ld r4,_DAR(r1) |
1433 | ld r5,_DSISR(r1) | |
1434 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1435 | bl do_page_fault |
0ebc4cda | 1436 | cmpdi r3,0 |
a546498f | 1437 | beq+ 12f |
b1576fec | 1438 | bl save_nvgprs |
0ebc4cda BH |
1439 | mr r5,r3 |
1440 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1441 | lwz r4,_DAR(r1) | |
b1576fec AB |
1442 | bl bad_page_fault |
1443 | b ret_from_except | |
0ebc4cda | 1444 | |
a546498f BH |
1445 | /* We have a data breakpoint exception - handle it */ |
1446 | handle_dabr_fault: | |
b1576fec | 1447 | bl save_nvgprs |
a546498f BH |
1448 | ld r4,_DAR(r1) |
1449 | ld r5,_DSISR(r1) | |
1450 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1451 | bl do_break |
1452 | 12: b ret_from_except_lite | |
a546498f | 1453 | |
0ebc4cda | 1454 | |
caca285e | 1455 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1456 | /* We have a page fault that hash_page could handle but HV refused |
1457 | * the PTE insertion | |
1458 | */ | |
b1576fec | 1459 | 13: bl save_nvgprs |
0ebc4cda BH |
1460 | mr r5,r3 |
1461 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1462 | ld r4,_DAR(r1) | |
b1576fec AB |
1463 | bl low_hash_fault |
1464 | b ret_from_except | |
caca285e | 1465 | #endif |
0ebc4cda | 1466 | |
9c1e1052 PM |
1467 | /* |
1468 | * We come here as a result of a DSI at a point where we don't want | |
1469 | * to call hash_page, such as when we are accessing memory (possibly | |
1470 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1471 | * were soft-disabled. We want to invoke the exception handler for | |
1472 | * the access, or panic if there isn't a handler. | |
1473 | */ | |
b1576fec | 1474 | 77: bl save_nvgprs |
9c1e1052 PM |
1475 | mr r4,r3 |
1476 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1477 | li r5,SIGSEGV | |
b1576fec AB |
1478 | bl bad_page_fault |
1479 | b ret_from_except | |
4e2bf01b ME |
1480 | |
1481 | /* | |
1482 | * Here we have detected that the kernel stack pointer is bad. | |
1483 | * R9 contains the saved CR, r13 points to the paca, | |
1484 | * r10 contains the (bad) kernel stack pointer, | |
1485 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1486 | * We switch to using an emergency stack, save the registers there, | |
1487 | * and call kernel_bad_stack(), which panics. | |
1488 | */ | |
1489 | bad_stack: | |
1490 | ld r1,PACAEMERGSP(r13) | |
1491 | subi r1,r1,64+INT_FRAME_SIZE | |
1492 | std r9,_CCR(r1) | |
1493 | std r10,GPR1(r1) | |
1494 | std r11,_NIP(r1) | |
1495 | std r12,_MSR(r1) | |
1496 | mfspr r11,SPRN_DAR | |
1497 | mfspr r12,SPRN_DSISR | |
1498 | std r11,_DAR(r1) | |
1499 | std r12,_DSISR(r1) | |
1500 | mflr r10 | |
1501 | mfctr r11 | |
1502 | mfxer r12 | |
1503 | std r10,_LINK(r1) | |
1504 | std r11,_CTR(r1) | |
1505 | std r12,_XER(r1) | |
1506 | SAVE_GPR(0,r1) | |
1507 | SAVE_GPR(2,r1) | |
1508 | ld r10,EX_R3(r3) | |
1509 | std r10,GPR3(r1) | |
1510 | SAVE_GPR(4,r1) | |
1511 | SAVE_4GPRS(5,r1) | |
1512 | ld r9,EX_R9(r3) | |
1513 | ld r10,EX_R10(r3) | |
1514 | SAVE_2GPRS(9,r1) | |
1515 | ld r9,EX_R11(r3) | |
1516 | ld r10,EX_R12(r3) | |
1517 | ld r11,EX_R13(r3) | |
1518 | std r9,GPR11(r1) | |
1519 | std r10,GPR12(r1) | |
1520 | std r11,GPR13(r1) | |
1521 | BEGIN_FTR_SECTION | |
1522 | ld r10,EX_CFAR(r3) | |
1523 | std r10,ORIG_GPR3(r1) | |
1524 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1525 | SAVE_8GPRS(14,r1) | |
1526 | SAVE_10GPRS(22,r1) | |
1527 | lhz r12,PACA_TRAP_SAVE(r13) | |
1528 | std r12,_TRAP(r1) | |
1529 | addi r11,r1,INT_FRAME_SIZE | |
1530 | std r11,0(r1) | |
1531 | li r12,0 | |
1532 | std r12,0(r11) | |
1533 | ld r2,PACATOC(r13) | |
1534 | ld r11,exception_marker@toc(r2) | |
1535 | std r12,RESULT(r1) | |
1536 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1537 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1538 | bl kernel_bad_stack | |
1539 | b 1b | |
0f0c6ca1 NP |
1540 | |
1541 | /* | |
1542 | * Called from arch_local_irq_enable when an interrupt needs | |
1543 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1544 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1545 | * stackframe like if a real interrupt had happened. | |
1546 | * | |
1547 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1548 | * in the generated frame has EE set to 1 or the exception | |
1549 | * handler will not properly re-enable them. | |
1550 | */ | |
1551 | _GLOBAL(__replay_interrupt) | |
1552 | /* We are going to jump to the exception common code which | |
1553 | * will retrieve various register values from the PACA which | |
1554 | * we don't give a damn about, so we don't bother storing them. | |
1555 | */ | |
1556 | mfmsr r12 | |
1557 | mflr r11 | |
1558 | mfcr r9 | |
1559 | ori r12,r12,MSR_EE | |
1560 | cmpwi r3,0x900 | |
1561 | beq decrementer_common | |
1562 | cmpwi r3,0x500 | |
1563 | beq hardware_interrupt_common | |
1564 | BEGIN_FTR_SECTION | |
1565 | cmpwi r3,0xe80 | |
1566 | beq h_doorbell_common | |
1567 | cmpwi r3,0xea0 | |
1568 | beq h_virt_irq_common | |
1569 | cmpwi r3,0xe60 | |
1570 | beq hmi_exception_common | |
1571 | FTR_SECTION_ELSE | |
1572 | cmpwi r3,0xa00 | |
1573 | beq doorbell_super_common | |
1574 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1575 | blr |