]> git.proxmox.com Git - qemu.git/blame - target-arm/helper.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-arm: Extend feature flags to 64 bits
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
4a501606
PM		 7#ifndef CONFIG_USER_ONLY
8static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9 int access_type, int is_user,
10 uint32_t *phys_ptr, int *prot,
11 target_ulong *page_size);
12#endif
13
0ecb72a5 14static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 15{
16 int nregs;
17
18 /* VFP data registers are always little-endian. */
19 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[reg]);
22 return 8;
23 }
24 if (arm_feature(env, ARM_FEATURE_NEON)) {
25 /* Aliases for Q regs. */
26 nregs += 16;
27 if (reg < nregs) {
28 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
29 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
30 return 16;
31 }
32 }
33 switch (reg - nregs) {
34 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
35 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
36 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
37 }
38 return 0;
39}
40
0ecb72a5 41static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 42{
43 int nregs;
44
45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
46 if (reg < nregs) {
47 env->vfp.regs[reg] = ldfq_le_p(buf);
48 return 8;
49 }
50 if (arm_feature(env, ARM_FEATURE_NEON)) {
51 nregs += 16;
52 if (reg < nregs) {
53 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
54 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
55 return 16;
56 }
57 }
58 switch (reg - nregs) {
59 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
60 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 61 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 62 }
63 return 0;
64}
65
c983fe6c
PM		 66static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
67{
68 env->cp15.c3 = value;
69 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
70 return 0;
71}
72
08de207b
PM		 73static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
74{
75 if (env->cp15.c13_fcse != value) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
78 */
79 tlb_flush(env, 1);
80 env->cp15.c13_fcse = value;
81 }
82 return 0;
83}
84static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
85 uint64_t value)
86{
87 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
91 */
92 tlb_flush(env, 1);
93 }
94 env->cp15.c13_context = value;
95 return 0;
96}
97
d929823f
PM		 98static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
99 uint64_t value)
100{
101 /* Invalidate all (TLBIALL) */
102 tlb_flush(env, 1);
103 return 0;
104}
105
106static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
107 uint64_t value)
108{
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env, value & TARGET_PAGE_MASK);
111 return 0;
112}
113
114static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
115 uint64_t value)
116{
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env, value == 0);
119 return 0;
120}
121
122static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
123 uint64_t value)
124{
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env, value & TARGET_PAGE_MASK);
127 return 0;
128}
129
e9aa6c21
PM		 130static const ARMCPRegInfo cp_reginfo[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
134 */
135 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
136 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 137 /* MMU Domain access control / MPU write buffer control */
138 { .name = "DACR", .cp = 15,
139 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
140 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
141 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 142 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
143 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
144 .resetvalue = 0, .writefn = fcse_write },
145 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
146 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
147 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
150 */
151 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
152 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
155 */
156 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
157 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
158 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
159 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
160 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
161 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
162 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
163 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
166 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
167 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 168 REGINFO_SENTINEL
169};
170
7d57f408
PM		 171static const ARMCPRegInfo not_v6_cp_reginfo[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
173 * over-broad.
174 */
175 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
176 .access = PL1_W, .type = ARM_CP_WFI },
177 REGINFO_SENTINEL
178};
179
180static const ARMCPRegInfo not_v7_cp_reginfo[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
183 */
184 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
185 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
189 */
190 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
191 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
192 .resetvalue = 0 },
193 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
194 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
195 .resetvalue = 0 },
776d4e5c
PM		 196 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
197 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
198 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 199 REGINFO_SENTINEL
200};
201
2771db27
PM		 202static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
203{
204 if (env->cp15.c1_coproc != value) {
205 env->cp15.c1_coproc = value;
206 /* ??? Is this safe when called from within a TB? */
207 tb_flush(env);
208 }
209 return 0;
210}
211
7d57f408
PM		 212static const ARMCPRegInfo v6_cp_reginfo[] = {
213 /* prefetch by MVA in v6, NOP in v7 */
214 { .name = "MVA_prefetch",
215 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
216 .access = PL1_W, .type = ARM_CP_NOP },
217 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
218 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 219 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 220 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 221 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 222 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 223 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
224 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
225 .resetvalue = 0, },
226 /* Watchpoint Fault Address Register : should actually only be present
227 * for 1136, 1176, 11MPCore.
228 */
229 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
230 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 231 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
232 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
233 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 234 REGINFO_SENTINEL
235};
236
200ac0ef
PM		 237static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
238 uint64_t *value)
239{
240 /* Generic performance monitor register read function for where
241 * user access may be allowed by PMUSERENR.
242 */
243 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
244 return EXCP_UDEF;
245 }
246 *value = CPREG_FIELD32(env, ri);
247 return 0;
248}
249
250static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
251 uint64_t value)
252{
253 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
254 return EXCP_UDEF;
255 }
256 /* only the DP, X, D and E bits are writable */
257 env->cp15.c9_pmcr &= ~0x39;
258 env->cp15.c9_pmcr |= (value & 0x39);
259 return 0;
260}
261
262static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
263 uint64_t value)
264{
265 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
266 return EXCP_UDEF;
267 }
268 value &= (1 << 31);
269 env->cp15.c9_pmcnten |= value;
270 return 0;
271}
272
273static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
274 uint64_t value)
275{
276 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
277 return EXCP_UDEF;
278 }
279 value &= (1 << 31);
280 env->cp15.c9_pmcnten &= ~value;
281 return 0;
282}
283
284static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
285 uint64_t value)
286{
287 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
288 return EXCP_UDEF;
289 }
290 env->cp15.c9_pmovsr &= ~value;
291 return 0;
292}
293
294static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
295 uint64_t value)
296{
297 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
298 return EXCP_UDEF;
299 }
300 env->cp15.c9_pmxevtyper = value & 0xff;
301 return 0;
302}
303
304static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
305 uint64_t value)
306{
307 env->cp15.c9_pmuserenr = value & 1;
308 return 0;
309}
310
311static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
312 uint64_t value)
313{
314 /* We have no event counters so only the C bit can be changed */
315 value &= (1 << 31);
316 env->cp15.c9_pminten |= value;
317 return 0;
318}
319
320static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
321 uint64_t value)
322{
323 value &= (1 << 31);
324 env->cp15.c9_pminten &= ~value;
325 return 0;
326}
327
776d4e5c
PM		 328static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
329 uint64_t *value)
330{
331 ARMCPU *cpu = arm_env_get_cpu(env);
332 *value = cpu->ccsidr[env->cp15.c0_cssel];
333 return 0;
334}
335
336static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
337 uint64_t value)
338{
339 env->cp15.c0_cssel = value & 0xf;
340 return 0;
341}
342
e9aa6c21
PM		 343static const ARMCPRegInfo v7_cp_reginfo[] = {
344 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
345 * debug components
346 */
347 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
348 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 349 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 350 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 351 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
352 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
353 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 354 /* Performance monitors are implementation defined in v7,
355 * but with an ARM recommended set of registers, which we
356 * follow (although we don't actually implement any counters)
357 *
358 * Performance registers fall into three categories:
359 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
360 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
361 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
362 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
363 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
364 */
365 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
366 .access = PL0_RW, .resetvalue = 0,
367 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
368 .readfn = pmreg_read, .writefn = pmcntenset_write },
369 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
370 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
371 .readfn = pmreg_read, .writefn = pmcntenclr_write },
372 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
373 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
374 .readfn = pmreg_read, .writefn = pmovsr_write },
375 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
376 * respect PMUSERENR.
377 */
378 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
379 .access = PL0_W, .type = ARM_CP_NOP },
380 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
381 * We choose to RAZ/WI. XXX should respect PMUSERENR.
382 */
383 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
384 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
385 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
386 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
387 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
388 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
389 .access = PL0_RW,
390 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
391 .readfn = pmreg_read, .writefn = pmxevtyper_write },
392 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
393 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
394 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
395 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
396 .access = PL0_R | PL1_RW,
397 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
398 .resetvalue = 0,
399 .writefn = pmuserenr_write },
400 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
401 .access = PL1_RW,
402 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
403 .resetvalue = 0,
404 .writefn = pmintenset_write },
405 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
406 .access = PL1_RW,
407 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
408 .resetvalue = 0,
409 .writefn = pmintenclr_write },
2771db27
PM		 410 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
411 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
412 .resetvalue = 0, },
776d4e5c
PM		 413 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
414 .access = PL1_R, .readfn = ccsidr_read },
415 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
416 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
417 .writefn = csselr_write, .resetvalue = 0 },
418 /* Auxiliary ID register: this actually has an IMPDEF value but for now
419 * just RAZ for all cores:
420 */
421 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
422 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 423 REGINFO_SENTINEL
424};
425
c326b979
PM		 426static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
427{
428 value &= 1;
429 env->teecr = value;
430 return 0;
431}
432
433static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
434 uint64_t *value)
435{
436 /* This is a helper function because the user access rights
437 * depend on the value of the TEECR.
438 */
439 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
440 return EXCP_UDEF;
441 }
442 *value = env->teehbr;
443 return 0;
444}
445
446static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
447 uint64_t value)
448{
449 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
450 return EXCP_UDEF;
451 }
452 env->teehbr = value;
453 return 0;
454}
455
456static const ARMCPRegInfo t2ee_cp_reginfo[] = {
457 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
458 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
459 .resetvalue = 0,
460 .writefn = teecr_write },
461 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
462 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
463 .resetvalue = 0,
464 .readfn = teehbr_read, .writefn = teehbr_write },
465 REGINFO_SENTINEL
466};
467
4d31c596
PM		 468static const ARMCPRegInfo v6k_cp_reginfo[] = {
469 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
470 .access = PL0_RW,
471 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
472 .resetvalue = 0 },
473 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
474 .access = PL0_R|PL1_W,
475 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
476 .resetvalue = 0 },
477 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
478 .access = PL1_RW,
479 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
480 .resetvalue = 0 },
481 REGINFO_SENTINEL
482};
483
6cc7a3ae
PM		 484static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
485 /* Dummy implementation: RAZ/WI the whole crn=14 space */
486 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
487 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
488 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
489 REGINFO_SENTINEL
490};
491
4a501606
PM		 492static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
493{
494 if (arm_feature(env, ARM_FEATURE_V7)) {
495 env->cp15.c7_par = value & 0xfffff6ff;
496 } else {
497 env->cp15.c7_par = value & 0xfffff1ff;
498 }
499 return 0;
500}
501
502#ifndef CONFIG_USER_ONLY
503/* get_phys_addr() isn't present for user-mode-only targets */
504static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
505{
506 uint32_t phys_addr;
507 target_ulong page_size;
508 int prot;
509 int ret, is_user = ri->opc2 & 2;
510 int access_type = ri->opc2 & 1;
511
512 if (ri->opc2 & 4) {
513 /* Other states are only available with TrustZone */
514 return EXCP_UDEF;
515 }
516 ret = get_phys_addr(env, value, access_type, is_user,
517 &phys_addr, &prot, &page_size);
518 if (ret == 0) {
519 /* We do not set any attribute bits in the PAR */
520 if (page_size == (1 << 24)
521 && arm_feature(env, ARM_FEATURE_V7)) {
522 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
523 } else {
524 env->cp15.c7_par = phys_addr & 0xfffff000;
525 }
526 } else {
527 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
528 ((ret & (12 << 1)) >> 6) |
529 ((ret & 0xf) << 1) | 1;
530 }
531 return 0;
532}
533#endif
534
535static const ARMCPRegInfo vapa_cp_reginfo[] = {
536 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
537 .access = PL1_RW, .resetvalue = 0,
538 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
539 .writefn = par_write },
540#ifndef CONFIG_USER_ONLY
541 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
542 .access = PL1_W, .writefn = ats_write },
543#endif
544 REGINFO_SENTINEL
545};
546
18032bec
PM		 547/* Return basic MPU access permission bits. */
548static uint32_t simple_mpu_ap_bits(uint32_t val)
549{
550 uint32_t ret;
551 uint32_t mask;
552 int i;
553 ret = 0;
554 mask = 3;
555 for (i = 0; i < 16; i += 2) {
556 ret |= (val >> i) & mask;
557 mask <<= 2;
558 }
559 return ret;
560}
561
562/* Pad basic MPU access permission bits to extended format. */
563static uint32_t extended_mpu_ap_bits(uint32_t val)
564{
565 uint32_t ret;
566 uint32_t mask;
567 int i;
568 ret = 0;
569 mask = 3;
570 for (i = 0; i < 16; i += 2) {
571 ret |= (val & mask) << i;
572 mask <<= 2;
573 }
574 return ret;
575}
576
577static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
578 uint64_t value)
579{
580 env->cp15.c5_data = extended_mpu_ap_bits(value);
581 return 0;
582}
583
584static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
585 uint64_t *value)
586{
587 *value = simple_mpu_ap_bits(env->cp15.c5_data);
588 return 0;
589}
590
591static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
592 uint64_t value)
593{
594 env->cp15.c5_insn = extended_mpu_ap_bits(value);
595 return 0;
596}
597
598static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
599 uint64_t *value)
600{
601 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
602 return 0;
603}
604
06d76f31
PM		 605static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
606 uint64_t *value)
607{
608 if (ri->crm > 8) {
609 return EXCP_UDEF;
610 }
611 *value = env->cp15.c6_region[ri->crm];
612 return 0;
613}
614
615static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
616 uint64_t value)
617{
618 if (ri->crm > 8) {
619 return EXCP_UDEF;
620 }
621 env->cp15.c6_region[ri->crm] = value;
622 return 0;
623}
624
18032bec
PM		 625static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
626 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
627 .access = PL1_RW,
628 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
629 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
630 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
631 .access = PL1_RW,
632 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
633 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
634 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
635 .access = PL1_RW,
636 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
637 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
638 .access = PL1_RW,
639 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 640 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
641 .access = PL1_RW,
642 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
643 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
644 .access = PL1_RW,
645 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 646 /* Protection region base and size registers */
647 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
648 .opc2 = CP_ANY, .access = PL1_RW,
649 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 650 REGINFO_SENTINEL
651};
652
ecce5c3c
PM		 653static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
654 uint64_t value)
655{
656 value &= 7;
657 env->cp15.c2_control = value;
658 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
659 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
660 return 0;
661}
662
663static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
664{
665 env->cp15.c2_base_mask = 0xffffc000u;
666 env->cp15.c2_control = 0;
667 env->cp15.c2_mask = 0;
668}
669
18032bec
PM		 670static const ARMCPRegInfo vmsa_cp_reginfo[] = {
671 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
672 .access = PL1_RW,
673 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
674 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
675 .access = PL1_RW,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 677 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
678 .access = PL1_RW,
679 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
680 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
681 .access = PL1_RW,
81a60ada 682 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 683 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
684 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
685 .resetfn = vmsa_ttbcr_reset,
686 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 687 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
688 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
689 .resetvalue = 0, },
18032bec
PM		 690 REGINFO_SENTINEL
691};
692
1047b9d7
PM		 693static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695{
696 env->cp15.c15_ticonfig = value & 0xe7;
697 /* The OS_TYPE bit in this register changes the reported CPUID! */
698 env->cp15.c0_cpuid = (value & (1 << 5)) ?
699 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
700 return 0;
701}
702
703static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
704 uint64_t value)
705{
706 env->cp15.c15_threadid = value & 0xffff;
707 return 0;
708}
709
710static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
711 uint64_t value)
712{
713 /* Wait-for-interrupt (deprecated) */
714 cpu_interrupt(env, CPU_INTERRUPT_HALT);
715 return 0;
716}
717
c4804214
PM		 718static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
719 uint64_t value)
720{
721 /* On OMAP there are registers indicating the max/min index of dcache lines
722 * containing a dirty line; cache flush operations have to reset these.
723 */
724 env->cp15.c15_i_max = 0x000;
725 env->cp15.c15_i_min = 0xff0;
726 return 0;
727}
728
18032bec
PM		 729static const ARMCPRegInfo omap_cp_reginfo[] = {
730 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
731 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
732 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 733 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
734 .access = PL1_RW, .type = ARM_CP_NOP },
735 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
736 .access = PL1_RW,
737 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
738 .writefn = omap_ticonfig_write },
739 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
740 .access = PL1_RW,
741 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
742 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
743 .access = PL1_RW, .resetvalue = 0xff0,
744 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
745 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
746 .access = PL1_RW,
747 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
748 .writefn = omap_threadid_write },
749 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
750 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
751 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
752 /* TODO: Peripheral port remap register:
753 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
754 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
755 * when MMU is off.
756 */
c4804214
PM		 757 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
758 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
759 .writefn = omap_cachemaint_write },
34f90529
PM		 760 { .name = "C9", .cp = 15, .crn = 9,
761 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
762 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 763 REGINFO_SENTINEL
764};
765
766static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
767 uint64_t value)
768{
769 value &= 0x3fff;
770 if (env->cp15.c15_cpar != value) {
771 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
772 tb_flush(env);
773 env->cp15.c15_cpar = value;
774 }
775 return 0;
776}
777
778static const ARMCPRegInfo xscale_cp_reginfo[] = {
779 { .name = "XSCALE_CPAR",
780 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
781 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
782 .writefn = xscale_cpar_write, },
2771db27
PM		 783 { .name = "XSCALE_AUXCR",
784 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
785 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
786 .resetvalue = 0, },
1047b9d7
PM		 787 REGINFO_SENTINEL
788};
789
790static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
791 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
792 * implementation of this implementation-defined space.
793 * Ideally this should eventually disappear in favour of actually
794 * implementing the correct behaviour for all cores.
795 */
796 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
797 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
798 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 799 REGINFO_SENTINEL
800};
801
c4804214
PM		 802static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
803 /* Cache status: RAZ because we have no cache so it's always clean */
804 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
805 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
806 REGINFO_SENTINEL
807};
808
809static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
810 /* We never have a a block transfer operation in progress */
811 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
812 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
30b05bba
PM		 813 /* The cache ops themselves: these all NOP for QEMU */
814 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
815 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
816 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
817 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
818 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
819 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
820 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
821 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
822 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
823 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
824 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
825 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 826 REGINFO_SENTINEL
827};
828
829static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
830 /* The cache test-and-clean instructions always return (1 << 30)
831 * to indicate that there are no dirty cache lines.
832 */
833 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
834 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
835 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
836 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
837 REGINFO_SENTINEL
838};
839
34f90529
PM		 840static const ARMCPRegInfo strongarm_cp_reginfo[] = {
841 /* Ignore ReadBuffer accesses */
842 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
843 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
844 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
845 .resetvalue = 0 },
846 REGINFO_SENTINEL
847};
848
81bdde9d
PM		 849static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
850 uint64_t *value)
851{
852 uint32_t mpidr = env->cpu_index;
853 /* We don't support setting cluster ID ([8..11])
854 * so these bits always RAZ.
855 */
856 if (arm_feature(env, ARM_FEATURE_V7MP)) {
857 mpidr |= (1 << 31);
858 /* Cores which are uniprocessor (non-coherent)
859 * but still implement the MP extensions set
860 * bit 30. (For instance, A9UP.) However we do
861 * not currently model any of those cores.
862 */
863 }
864 *value = mpidr;
865 return 0;
866}
867
868static const ARMCPRegInfo mpidr_cp_reginfo[] = {
869 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
870 .access = PL1_R, .readfn = mpidr_read },
871 REGINFO_SENTINEL
872};
873
2771db27
PM		 874static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
875{
876 env->cp15.c1_sys = value;
877 /* ??? Lots of these bits are not implemented. */
878 /* This may enable/disable the MMU, so do a TLB flush. */
879 tlb_flush(env, 1);
880 return 0;
881}
882
2ceb98c0
PM		 883void register_cp_regs_for_features(ARMCPU *cpu)
884{
885 /* Register all the coprocessor registers based on feature bits */
886 CPUARMState *env = &cpu->env;
887 if (arm_feature(env, ARM_FEATURE_M)) {
888 /* M profile has no coprocessor registers */
889 return;
890 }
891
e9aa6c21 892 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 893 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 894 /* The ID registers all have impdef reset values */
895 ARMCPRegInfo v6_idregs[] = {
896 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
897 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
898 .resetvalue = cpu->id_pfr0 },
899 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
900 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
901 .resetvalue = cpu->id_pfr1 },
902 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
903 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
904 .resetvalue = cpu->id_dfr0 },
905 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
906 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
907 .resetvalue = cpu->id_afr0 },
908 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
909 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
910 .resetvalue = cpu->id_mmfr0 },
911 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
912 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
913 .resetvalue = cpu->id_mmfr1 },
914 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
915 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
916 .resetvalue = cpu->id_mmfr2 },
917 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
918 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
919 .resetvalue = cpu->id_mmfr3 },
920 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
921 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
922 .resetvalue = cpu->id_isar0 },
923 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
924 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
925 .resetvalue = cpu->id_isar1 },
926 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
927 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
928 .resetvalue = cpu->id_isar2 },
929 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
930 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
931 .resetvalue = cpu->id_isar3 },
932 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
933 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
934 .resetvalue = cpu->id_isar4 },
935 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
936 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
937 .resetvalue = cpu->id_isar5 },
938 /* 6..7 are as yet unallocated and must RAZ */
939 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
940 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
941 .resetvalue = 0 },
942 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
943 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
944 .resetvalue = 0 },
945 REGINFO_SENTINEL
946 };
947 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 948 define_arm_cp_regs(cpu, v6_cp_reginfo);
949 } else {
950 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
951 }
4d31c596
PM		 952 if (arm_feature(env, ARM_FEATURE_V6K)) {
953 define_arm_cp_regs(cpu, v6k_cp_reginfo);
954 }
e9aa6c21 955 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 956 /* v7 performance monitor control register: same implementor
957 * field as main ID register, and we implement no event counters.
958 */
959 ARMCPRegInfo pmcr = {
960 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
961 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
962 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
963 .readfn = pmreg_read, .writefn = pmcr_write
964 };
776d4e5c
PM		 965 ARMCPRegInfo clidr = {
966 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
967 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
968 };
200ac0ef 969 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 970 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 971 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 972 } else {
973 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 974 }
18032bec
PM		 975 if (arm_feature(env, ARM_FEATURE_MPU)) {
976 /* These are the MPU registers prior to PMSAv6. Any new
977 * PMSA core later than the ARM946 will require that we
978 * implement the PMSAv6 or PMSAv7 registers, which are
979 * completely different.
980 */
981 assert(!arm_feature(env, ARM_FEATURE_V6));
982 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
983 } else {
984 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
985 }
c326b979
PM		 986 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
987 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
988 }
6cc7a3ae
PM		 989 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
990 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
991 }
4a501606
PM		 992 if (arm_feature(env, ARM_FEATURE_VAPA)) {
993 define_arm_cp_regs(cpu, vapa_cp_reginfo);
994 }
c4804214
PM		 995 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
996 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
997 }
998 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
999 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1000 }
1001 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1002 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1003 }
18032bec
PM		 1004 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1005 define_arm_cp_regs(cpu, omap_cp_reginfo);
1006 }
34f90529
PM		 1007 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1008 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1009 }
1047b9d7
PM		 1010 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1011 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1012 }
1013 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1014 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1015 }
81bdde9d
PM		 1016 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1017 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1018 }
7884849c
PM		 1019 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1020 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1021 * be read-only (ie write causes UNDEF exception).
1022 */
1023 {
1024 ARMCPRegInfo id_cp_reginfo[] = {
1025 /* Note that the MIDR isn't a simple constant register because
1026 * of the TI925 behaviour where writes to another register can
1027 * cause the MIDR value to change.
1028 */
1029 { .name = "MIDR",
1030 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1031 .access = PL1_R, .resetvalue = cpu->midr,
1032 .writefn = arm_cp_write_ignore,
1033 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1034 { .name = "CTR",
1035 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1036 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1037 { .name = "TCMTR",
1038 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1039 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1040 { .name = "TLBTR",
1041 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1042 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1043 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1044 { .name = "DUMMY",
1045 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1046 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1047 { .name = "DUMMY",
1048 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1049 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1050 { .name = "DUMMY",
1051 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1052 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1053 { .name = "DUMMY",
1054 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1055 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1056 { .name = "DUMMY",
1057 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1058 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1059 REGINFO_SENTINEL
1060 };
1061 ARMCPRegInfo crn0_wi_reginfo = {
1062 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1063 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1064 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1065 };
1066 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1067 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1068 ARMCPRegInfo *r;
1069 /* Register the blanket "writes ignored" value first to cover the
1070 * whole space. Then define the specific ID registers, but update
1071 * their access field to allow write access, so that they ignore
1072 * writes rather than causing them to UNDEF.
1073 */
1074 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1075 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1076 r->access = PL1_RW;
1077 define_one_arm_cp_reg(cpu, r);
1078 }
1079 } else {
1080 /* Just register the standard ID registers (read-only, meaning
1081 * that writes will UNDEF).
1082 */
1083 define_arm_cp_regs(cpu, id_cp_reginfo);
1084 }
1085 }
1086
2771db27
PM		 1087 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1088 ARMCPRegInfo auxcr = {
1089 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1090 .access = PL1_RW, .type = ARM_CP_CONST,
1091 .resetvalue = cpu->reset_auxcr
1092 };
1093 define_one_arm_cp_reg(cpu, &auxcr);
1094 }
1095
1096 /* Generic registers whose values depend on the implementation */
1097 {
1098 ARMCPRegInfo sctlr = {
1099 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1100 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1101 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1102 };
1103 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1104 /* Normally we would always end the TB on an SCTLR write, but Linux
1105 * arch/arm/mach-pxa/sleep.S expects two instructions following
1106 * an MMU enable to execute from cache. Imitate this behaviour.
1107 */
1108 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1109 }
1110 define_one_arm_cp_reg(cpu, &sctlr);
1111 }
2ceb98c0
PM		 1112}
1113
778c3a06 1114ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1115{
dec9c2d4 1116 ARMCPU *cpu;
40f137e1 1117 CPUARMState *env;
b26eefb6 1118 static int inited = 0;
40f137e1 1119
777dc784 1120 if (!object_class_by_name(cpu_model)) {
aaed909a 1121 return NULL;
777dc784
PM		 1122 }
1123 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 1124 env = &cpu->env;
777dc784 1125 env->cpu_model_str = cpu_model;
581be094 1126 arm_cpu_realize(cpu);
777dc784 1127
f4fc247b 1128 if (tcg_enabled() && !inited) {
b26eefb6
PB		 1129 inited = 1;
1130 arm_translate_init();
1131 }
1132
df90dadb 1133 cpu_reset(CPU(cpu));
56aebc89
PB		 1134 if (arm_feature(env, ARM_FEATURE_NEON)) {
1135 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1136 51, "arm-neon.xml", 0);
1137 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1138 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1139 35, "arm-vfp3.xml", 0);
1140 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1141 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1142 19, "arm-vfp.xml", 0);
1143 }
0bf46a40 1144 qemu_init_vcpu(env);
778c3a06 1145 return cpu;
40f137e1
PB		 1146}
1147
777dc784
PM		 1148typedef struct ARMCPUListState {
1149 fprintf_function cpu_fprintf;
1150 FILE *file;
1151} ARMCPUListState;
3371d272 1152
777dc784
PM		 1153/* Sort alphabetically by type name, except for "any". */
1154static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1155{
777dc784
PM		 1156 ObjectClass *class_a = (ObjectClass *)a;
1157 ObjectClass *class_b = (ObjectClass *)b;
1158 const char *name_a, *name_b;
5adb4839 1159
777dc784
PM		 1160 name_a = object_class_get_name(class_a);
1161 name_b = object_class_get_name(class_b);
1162 if (strcmp(name_a, "any") == 0) {
1163 return 1;
1164 } else if (strcmp(name_b, "any") == 0) {
1165 return -1;
1166 } else {
1167 return strcmp(name_a, name_b);
5adb4839
PB		 1168 }
1169}
1170
777dc784 1171static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1172{
777dc784
PM		 1173 ObjectClass *oc = data;
1174 ARMCPUListState *s = user_data;
3371d272 1175
777dc784
PM		 1176 (*s->cpu_fprintf)(s->file, " %s\n",
1177 object_class_get_name(oc));
1178}
1179
1180void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1181{
1182 ARMCPUListState s = {
1183 .file = f,
1184 .cpu_fprintf = cpu_fprintf,
1185 };
1186 GSList *list;
1187
1188 list = object_class_get_list(TYPE_ARM_CPU, false);
1189 list = g_slist_sort(list, arm_cpu_list_compare);
1190 (*cpu_fprintf)(f, "Available CPUs:\n");
1191 g_slist_foreach(list, arm_cpu_list_entry, &s);
1192 g_slist_free(list);
40f137e1
PB		 1193}
1194
4b6a83fb
PM		 1195void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1196 const ARMCPRegInfo *r, void *opaque)
1197{
1198 /* Define implementations of coprocessor registers.
1199 * We store these in a hashtable because typically
1200 * there are less than 150 registers in a space which
1201 * is 16*16*16*8*8 = 262144 in size.
1202 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1203 * If a register is defined twice then the second definition is
1204 * used, so this can be used to define some generic registers and
1205 * then override them with implementation specific variations.
1206 * At least one of the original and the second definition should
1207 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1208 * against accidental use.
1209 */
1210 int crm, opc1, opc2;
1211 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1212 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1213 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1214 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1215 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1216 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1217 /* 64 bit registers have only CRm and Opc1 fields */
1218 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1219 /* Check that the register definition has enough info to handle
1220 * reads and writes if they are permitted.
1221 */
1222 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1223 if (r->access & PL3_R) {
1224 assert(r->fieldoffset || r->readfn);
1225 }
1226 if (r->access & PL3_W) {
1227 assert(r->fieldoffset || r->writefn);
1228 }
1229 }
1230 /* Bad type field probably means missing sentinel at end of reg list */
1231 assert(cptype_valid(r->type));
1232 for (crm = crmmin; crm <= crmmax; crm++) {
1233 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1234 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1235 uint32_t *key = g_new(uint32_t, 1);
1236 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1237 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1238 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1239 r2->opaque = opaque;
1240 /* Make sure reginfo passed to helpers for wildcarded regs
1241 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1242 */
1243 r2->crm = crm;
1244 r2->opc1 = opc1;
1245 r2->opc2 = opc2;
1246 /* Overriding of an existing definition must be explicitly
1247 * requested.
1248 */
1249 if (!(r->type & ARM_CP_OVERRIDE)) {
1250 ARMCPRegInfo *oldreg;
1251 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1252 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1253 fprintf(stderr, "Register redefined: cp=%d %d bit "
1254 "crn=%d crm=%d opc1=%d opc2=%d, "
1255 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1256 r2->crn, r2->crm, r2->opc1, r2->opc2,
1257 oldreg->name, r2->name);
1258 assert(0);
1259 }
1260 }
1261 g_hash_table_insert(cpu->cp_regs, key, r2);
1262 }
1263 }
1264 }
1265}
1266
1267void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1268 const ARMCPRegInfo *regs, void *opaque)
1269{
1270 /* Define a whole list of registers */
1271 const ARMCPRegInfo *r;
1272 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1273 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1274 }
1275}
1276
1277const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1278{
1279 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1280}
1281
1282int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1283 uint64_t value)
1284{
1285 /* Helper coprocessor write function for write-ignore registers */
1286 return 0;
1287}
1288
1289int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1290{
1291 /* Helper coprocessor write function for read-as-zero registers */
1292 *value = 0;
1293 return 0;
1294}
1295
0ecb72a5 1296static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1297{
1298 /* Return true if it is not valid for us to switch to
1299 * this CPU mode (ie all the UNPREDICTABLE cases in
1300 * the ARM ARM CPSRWriteByInstr pseudocode).
1301 */
1302 switch (mode) {
1303 case ARM_CPU_MODE_USR:
1304 case ARM_CPU_MODE_SYS:
1305 case ARM_CPU_MODE_SVC:
1306 case ARM_CPU_MODE_ABT:
1307 case ARM_CPU_MODE_UND:
1308 case ARM_CPU_MODE_IRQ:
1309 case ARM_CPU_MODE_FIQ:
1310 return 0;
1311 default:
1312 return 1;
1313 }
1314}
1315
2f4a40e5
AZ		 1316uint32_t cpsr_read(CPUARMState *env)
1317{
1318 int ZF;
6fbe23d5
PB		 1319 ZF = (env->ZF == 0);
1320 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1321 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1322 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1323 | ((env->condexec_bits & 0xfc) << 8)
1324 | (env->GE << 16);
1325}
1326
1327void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1328{
2f4a40e5 1329 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1330 env->ZF = (~val) & CPSR_Z;
1331 env->NF = val;
2f4a40e5
AZ		 1332 env->CF = (val >> 29) & 1;
1333 env->VF = (val << 3) & 0x80000000;
1334 }
1335 if (mask & CPSR_Q)
1336 env->QF = ((val & CPSR_Q) != 0);
1337 if (mask & CPSR_T)
1338 env->thumb = ((val & CPSR_T) != 0);
1339 if (mask & CPSR_IT_0_1) {
1340 env->condexec_bits &= ~3;
1341 env->condexec_bits |= (val >> 25) & 3;
1342 }
1343 if (mask & CPSR_IT_2_7) {
1344 env->condexec_bits &= 3;
1345 env->condexec_bits |= (val >> 8) & 0xfc;
1346 }
1347 if (mask & CPSR_GE) {
1348 env->GE = (val >> 16) & 0xf;
1349 }
1350
1351 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1352 if (bad_mode_switch(env, val & CPSR_M)) {
1353 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1354 * We choose to ignore the attempt and leave the CPSR M field
1355 * untouched.
1356 */
1357 mask &= ~CPSR_M;
1358 } else {
1359 switch_mode(env, val & CPSR_M);
1360 }
2f4a40e5
AZ		 1361 }
1362 mask &= ~CACHED_CPSR_BITS;
1363 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1364}
1365
b26eefb6
PB		 1366/* Sign/zero extend */
1367uint32_t HELPER(sxtb16)(uint32_t x)
1368{
1369 uint32_t res;
1370 res = (uint16_t)(int8_t)x;
1371 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1372 return res;
1373}
1374
1375uint32_t HELPER(uxtb16)(uint32_t x)
1376{
1377 uint32_t res;
1378 res = (uint16_t)(uint8_t)x;
1379 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1380 return res;
1381}
1382
f51bbbfe
PB		 1383uint32_t HELPER(clz)(uint32_t x)
1384{
7bbcb0af 1385 return clz32(x);
f51bbbfe
PB		 1386}
1387
3670669c
PB		 1388int32_t HELPER(sdiv)(int32_t num, int32_t den)
1389{
1390 if (den == 0)
1391 return 0;
686eeb93
AJ		 1392 if (num == INT_MIN && den == -1)
1393 return INT_MIN;
3670669c
PB		 1394 return num / den;
1395}
1396
1397uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1398{
1399 if (den == 0)
1400 return 0;
1401 return num / den;
1402}
1403
1404uint32_t HELPER(rbit)(uint32_t x)
1405{
1406 x = ((x & 0xff000000) >> 24)
1407 | ((x & 0x00ff0000) >> 8)
1408 | ((x & 0x0000ff00) << 8)
1409 | ((x & 0x000000ff) << 24);
1410 x = ((x & 0xf0f0f0f0) >> 4)
1411 | ((x & 0x0f0f0f0f) << 4);
1412 x = ((x & 0x88888888) >> 3)
1413 | ((x & 0x44444444) >> 1)
1414 | ((x & 0x22222222) << 1)
1415 | ((x & 0x11111111) << 3);
1416 return x;
1417}
1418
ad69471c
PB		 1419uint32_t HELPER(abs)(uint32_t x)
1420{
1421 return ((int32_t)x < 0) ? -x : x;
1422}
1423
5fafdf24 1424#if defined(CONFIG_USER_ONLY)
b5ff1b31 1425
0ecb72a5 1426void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 1427{
1428 env->exception_index = -1;
1429}
1430
0ecb72a5 1431int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1432 int mmu_idx)
b5ff1b31
FB		 1433{
1434 if (rw == 2) {
1435 env->exception_index = EXCP_PREFETCH_ABORT;
1436 env->cp15.c6_insn = address;
1437 } else {
1438 env->exception_index = EXCP_DATA_ABORT;
1439 env->cp15.c6_data = address;
1440 }
1441 return 1;
1442}
1443
9ee6e8bb 1444/* These should probably raise undefined insn exceptions. */
0ecb72a5 1445void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1446{
1447 cpu_abort(env, "v7m_mrs %d\n", reg);
1448}
1449
0ecb72a5 1450uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1451{
1452 cpu_abort(env, "v7m_mrs %d\n", reg);
1453 return 0;
1454}
1455
0ecb72a5 1456void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1457{
1458 if (mode != ARM_CPU_MODE_USR)
1459 cpu_abort(env, "Tried to switch out of user mode\n");
1460}
1461
0ecb72a5 1462void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1463{
1464 cpu_abort(env, "banked r13 write\n");
1465}
1466
0ecb72a5 1467uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1468{
1469 cpu_abort(env, "banked r13 read\n");
1470 return 0;
1471}
1472
b5ff1b31
FB		 1473#else
1474
1475/* Map CPU modes onto saved register banks. */
0ecb72a5 1476static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 1477{
1478 switch (mode) {
1479 case ARM_CPU_MODE_USR:
1480 case ARM_CPU_MODE_SYS:
1481 return 0;
1482 case ARM_CPU_MODE_SVC:
1483 return 1;
1484 case ARM_CPU_MODE_ABT:
1485 return 2;
1486 case ARM_CPU_MODE_UND:
1487 return 3;
1488 case ARM_CPU_MODE_IRQ:
1489 return 4;
1490 case ARM_CPU_MODE_FIQ:
1491 return 5;
1492 }
1b9e01c1 1493 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 1494 return -1;
1495}
1496
0ecb72a5 1497void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1498{
1499 int old_mode;
1500 int i;
1501
1502 old_mode = env->uncached_cpsr & CPSR_M;
1503 if (mode == old_mode)
1504 return;
1505
1506 if (old_mode == ARM_CPU_MODE_FIQ) {
1507 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1508 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1509 } else if (mode == ARM_CPU_MODE_FIQ) {
1510 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1511 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1512 }
1513
1b9e01c1 1514 i = bank_number(env, old_mode);
b5ff1b31
FB		 1515 env->banked_r13[i] = env->regs[13];
1516 env->banked_r14[i] = env->regs[14];
1517 env->banked_spsr[i] = env->spsr;
1518
1b9e01c1 1519 i = bank_number(env, mode);
b5ff1b31
FB		 1520 env->regs[13] = env->banked_r13[i];
1521 env->regs[14] = env->banked_r14[i];
1522 env->spsr = env->banked_spsr[i];
1523}
1524
9ee6e8bb
PB		 1525static void v7m_push(CPUARMState *env, uint32_t val)
1526{
1527 env->regs[13] -= 4;
1528 stl_phys(env->regs[13], val);
1529}
1530
1531static uint32_t v7m_pop(CPUARMState *env)
1532{
1533 uint32_t val;
1534 val = ldl_phys(env->regs[13]);
1535 env->regs[13] += 4;
1536 return val;
1537}
1538
1539/* Switch to V7M main or process stack pointer. */
1540static void switch_v7m_sp(CPUARMState *env, int process)
1541{
1542 uint32_t tmp;
1543 if (env->v7m.current_sp != process) {
1544 tmp = env->v7m.other_sp;
1545 env->v7m.other_sp = env->regs[13];
1546 env->regs[13] = tmp;
1547 env->v7m.current_sp = process;
1548 }
1549}
1550
1551static void do_v7m_exception_exit(CPUARMState *env)
1552{
1553 uint32_t type;
1554 uint32_t xpsr;
1555
1556 type = env->regs[15];
1557 if (env->v7m.exception != 0)
983fe826 1558 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1559
1560 /* Switch to the target stack. */
1561 switch_v7m_sp(env, (type & 4) != 0);
1562 /* Pop registers. */
1563 env->regs[0] = v7m_pop(env);
1564 env->regs[1] = v7m_pop(env);
1565 env->regs[2] = v7m_pop(env);
1566 env->regs[3] = v7m_pop(env);
1567 env->regs[12] = v7m_pop(env);
1568 env->regs[14] = v7m_pop(env);
1569 env->regs[15] = v7m_pop(env);
1570 xpsr = v7m_pop(env);
1571 xpsr_write(env, xpsr, 0xfffffdff);
1572 /* Undo stack alignment. */
1573 if (xpsr & 0x200)
1574 env->regs[13] |= 4;
1575 /* ??? The exception return type specifies Thread/Handler mode. However
1576 this is also implied by the xPSR value. Not sure what to do
1577 if there is a mismatch. */
1578 /* ??? Likewise for mismatches between the CONTROL register and the stack
1579 pointer. */
1580}
1581
2b3ea315 1582static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1583{
1584 uint32_t xpsr = xpsr_read(env);
1585 uint32_t lr;
1586 uint32_t addr;
1587
1588 lr = 0xfffffff1;
1589 if (env->v7m.current_sp)
1590 lr |= 4;
1591 if (env->v7m.exception == 0)
1592 lr |= 8;
1593
1594 /* For exceptions we just mark as pending on the NVIC, and let that
1595 handle it. */
1596 /* TODO: Need to escalate if the current priority is higher than the
1597 one we're raising. */
1598 switch (env->exception_index) {
1599 case EXCP_UDEF:
983fe826 1600 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1601 return;
1602 case EXCP_SWI:
1603 env->regs[15] += 2;
983fe826 1604 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1605 return;
1606 case EXCP_PREFETCH_ABORT:
1607 case EXCP_DATA_ABORT:
983fe826 1608 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1609 return;
1610 case EXCP_BKPT:
2ad207d4
PB		 1611 if (semihosting_enabled) {
1612 int nr;
d8fd2954 1613 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1614 if (nr == 0xab) {
1615 env->regs[15] += 2;
1616 env->regs[0] = do_arm_semihosting(env);
1617 return;
1618 }
1619 }
983fe826 1620 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1621 return;
1622 case EXCP_IRQ:
983fe826 1623 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1624 break;
1625 case EXCP_EXCEPTION_EXIT:
1626 do_v7m_exception_exit(env);
1627 return;
1628 default:
1629 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1630 return; /* Never happens. Keep compiler happy. */
1631 }
1632
1633 /* Align stack pointer. */
1634 /* ??? Should only do this if Configuration Control Register
1635 STACKALIGN bit is set. */
1636 if (env->regs[13] & 4) {
ab19b0ec 1637 env->regs[13] -= 4;
9ee6e8bb
PB		 1638 xpsr |= 0x200;
1639 }
6c95676b 1640 /* Switch to the handler mode. */
9ee6e8bb
PB		 1641 v7m_push(env, xpsr);
1642 v7m_push(env, env->regs[15]);
1643 v7m_push(env, env->regs[14]);
1644 v7m_push(env, env->regs[12]);
1645 v7m_push(env, env->regs[3]);
1646 v7m_push(env, env->regs[2]);
1647 v7m_push(env, env->regs[1]);
1648 v7m_push(env, env->regs[0]);
1649 switch_v7m_sp(env, 0);
c98d174c
PM		 1650 /* Clear IT bits */
1651 env->condexec_bits = 0;
9ee6e8bb
PB		 1652 env->regs[14] = lr;
1653 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1654 env->regs[15] = addr & 0xfffffffe;
1655 env->thumb = addr & 1;
1656}
1657
b5ff1b31
FB		 1658/* Handle a CPU exception. */
1659void do_interrupt(CPUARMState *env)
1660{
1661 uint32_t addr;
1662 uint32_t mask;
1663 int new_mode;
1664 uint32_t offset;
1665
9ee6e8bb
PB		 1666 if (IS_M(env)) {
1667 do_interrupt_v7m(env);
1668 return;
1669 }
b5ff1b31
FB		 1670 /* TODO: Vectored interrupt controller. */
1671 switch (env->exception_index) {
1672 case EXCP_UDEF:
1673 new_mode = ARM_CPU_MODE_UND;
1674 addr = 0x04;
1675 mask = CPSR_I;
1676 if (env->thumb)
1677 offset = 2;
1678 else
1679 offset = 4;
1680 break;
1681 case EXCP_SWI:
8e71621f
PB		 1682 if (semihosting_enabled) {
1683 /* Check for semihosting interrupt. */
1684 if (env->thumb) {
d8fd2954 1685 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 1686 } else {
d8fd2954
PB		 1687 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1688 & 0xffffff;
8e71621f
PB		 1689 }
1690 /* Only intercept calls from privileged modes, to provide some
1691 semblance of security. */
1692 if (((mask == 0x123456 && !env->thumb)
1693 || (mask == 0xab && env->thumb))
1694 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1695 env->regs[0] = do_arm_semihosting(env);
1696 return;
1697 }
1698 }
b5ff1b31
FB		 1699 new_mode = ARM_CPU_MODE_SVC;
1700 addr = 0x08;
1701 mask = CPSR_I;
601d70b9 1702 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1703 offset = 0;
1704 break;
06c949e6 1705 case EXCP_BKPT:
9ee6e8bb 1706 /* See if this is a semihosting syscall. */
2ad207d4 1707 if (env->thumb && semihosting_enabled) {
d8fd2954 1708 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1709 if (mask == 0xab
1710 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1711 env->regs[15] += 2;
1712 env->regs[0] = do_arm_semihosting(env);
1713 return;
1714 }
1715 }
81c05daf 1716 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1717 /* Fall through to prefetch abort. */
1718 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1719 new_mode = ARM_CPU_MODE_ABT;
1720 addr = 0x0c;
1721 mask = CPSR_A | CPSR_I;
1722 offset = 4;
1723 break;
1724 case EXCP_DATA_ABORT:
1725 new_mode = ARM_CPU_MODE_ABT;
1726 addr = 0x10;
1727 mask = CPSR_A | CPSR_I;
1728 offset = 8;
1729 break;
1730 case EXCP_IRQ:
1731 new_mode = ARM_CPU_MODE_IRQ;
1732 addr = 0x18;
1733 /* Disable IRQ and imprecise data aborts. */
1734 mask = CPSR_A | CPSR_I;
1735 offset = 4;
1736 break;
1737 case EXCP_FIQ:
1738 new_mode = ARM_CPU_MODE_FIQ;
1739 addr = 0x1c;
1740 /* Disable FIQ, IRQ and imprecise data aborts. */
1741 mask = CPSR_A | CPSR_I | CPSR_F;
1742 offset = 4;
1743 break;
1744 default:
1745 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1746 return; /* Never happens. Keep compiler happy. */
1747 }
1748 /* High vectors. */
1749 if (env->cp15.c1_sys & (1 << 13)) {
1750 addr += 0xffff0000;
1751 }
1752 switch_mode (env, new_mode);
1753 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1754 /* Clear IT bits. */
1755 env->condexec_bits = 0;
30a8cac1 1756 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1757 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1758 env->uncached_cpsr |= mask;
be5e7a76
DES		 1759 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1760 * and we should just guard the thumb mode on V4 */
1761 if (arm_feature(env, ARM_FEATURE_V4T)) {
1762 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1763 }
b5ff1b31
FB		 1764 env->regs[14] = env->regs[15] + offset;
1765 env->regs[15] = addr;
1766 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1767}
1768
1769/* Check section/page access permissions.
1770 Returns the page protection flags, or zero if the access is not
1771 permitted. */
0ecb72a5 1772static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1773 int access_type, int is_user)
b5ff1b31 1774{
9ee6e8bb
PB		 1775 int prot_ro;
1776
dd4ebc2e 1777 if (domain_prot == 3) {
b5ff1b31 1778 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1779 }
b5ff1b31 1780
9ee6e8bb
PB		 1781 if (access_type == 1)
1782 prot_ro = 0;
1783 else
1784 prot_ro = PAGE_READ;
1785
b5ff1b31
FB		 1786 switch (ap) {
1787 case 0:
78600320 1788 if (access_type == 1)
b5ff1b31
FB		 1789 return 0;
1790 switch ((env->cp15.c1_sys >> 8) & 3) {
1791 case 1:
1792 return is_user ? 0 : PAGE_READ;
1793 case 2:
1794 return PAGE_READ;
1795 default:
1796 return 0;
1797 }
1798 case 1:
1799 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1800 case 2:
1801 if (is_user)
9ee6e8bb 1802 return prot_ro;
b5ff1b31
FB		 1803 else
1804 return PAGE_READ | PAGE_WRITE;
1805 case 3:
1806 return PAGE_READ | PAGE_WRITE;
d4934d18 1807 case 4: /* Reserved. */
9ee6e8bb
PB		 1808 return 0;
1809 case 5:
1810 return is_user ? 0 : prot_ro;
1811 case 6:
1812 return prot_ro;
d4934d18 1813 case 7:
0ab06d83 1814 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1815 return 0;
1816 return prot_ro;
b5ff1b31
FB		 1817 default:
1818 abort();
1819 }
1820}
1821
0ecb72a5 1822static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1823{
1824 uint32_t table;
1825
1826 if (address & env->cp15.c2_mask)
1827 table = env->cp15.c2_base1 & 0xffffc000;
1828 else
1829 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1830
1831 table |= (address >> 18) & 0x3ffc;
1832 return table;
1833}
1834
0ecb72a5 1835static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1836 int is_user, uint32_t *phys_ptr, int *prot,
1837 target_ulong *page_size)
b5ff1b31
FB		 1838{
1839 int code;
1840 uint32_t table;
1841 uint32_t desc;
1842 int type;
1843 int ap;
1844 int domain;
dd4ebc2e 1845 int domain_prot;
b5ff1b31
FB		 1846 uint32_t phys_addr;
1847
9ee6e8bb
PB		 1848 /* Pagetable walk. */
1849 /* Lookup l1 descriptor. */
b2fa1797 1850 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1851 desc = ldl_phys(table);
1852 type = (desc & 3);
dd4ebc2e
JCD		 1853 domain = (desc >> 5) & 0x0f;
1854 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1855 if (type == 0) {
601d70b9 1856 /* Section translation fault. */
9ee6e8bb
PB		 1857 code = 5;
1858 goto do_fault;
1859 }
dd4ebc2e 1860 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1861 if (type == 2)
1862 code = 9; /* Section domain fault. */
1863 else
1864 code = 11; /* Page domain fault. */
1865 goto do_fault;
1866 }
1867 if (type == 2) {
1868 /* 1Mb section. */
1869 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1870 ap = (desc >> 10) & 3;
1871 code = 13;
d4c430a8 1872 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1873 } else {
1874 /* Lookup l2 entry. */
1875 if (type == 1) {
1876 /* Coarse pagetable. */
1877 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1878 } else {
1879 /* Fine pagetable. */
1880 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1881 }
1882 desc = ldl_phys(table);
1883 switch (desc & 3) {
1884 case 0: /* Page translation fault. */
1885 code = 7;
1886 goto do_fault;
1887 case 1: /* 64k page. */
1888 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1889 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1890 *page_size = 0x10000;
ce819861 1891 break;
9ee6e8bb
PB		 1892 case 2: /* 4k page. */
1893 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1894 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1895 *page_size = 0x1000;
ce819861 1896 break;
9ee6e8bb
PB		 1897 case 3: /* 1k page. */
1898 if (type == 1) {
1899 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1900 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1901 } else {
1902 /* Page translation fault. */
1903 code = 7;
1904 goto do_fault;
1905 }
1906 } else {
1907 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1908 }
1909 ap = (desc >> 4) & 3;
d4c430a8 1910 *page_size = 0x400;
ce819861
PB		 1911 break;
1912 default:
9ee6e8bb
PB		 1913 /* Never happens, but compiler isn't smart enough to tell. */
1914 abort();
ce819861 1915 }
9ee6e8bb
PB		 1916 code = 15;
1917 }
dd4ebc2e 1918 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1919 if (!*prot) {
1920 /* Access permission fault. */
1921 goto do_fault;
1922 }
3ad493fc 1923 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1924 *phys_ptr = phys_addr;
1925 return 0;
1926do_fault:
1927 return code | (domain << 4);
1928}
1929
0ecb72a5 1930static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1931 int is_user, uint32_t *phys_ptr, int *prot,
1932 target_ulong *page_size)
9ee6e8bb
PB		 1933{
1934 int code;
1935 uint32_t table;
1936 uint32_t desc;
1937 uint32_t xn;
de9b05b8 1938 uint32_t pxn = 0;
9ee6e8bb
PB		 1939 int type;
1940 int ap;
de9b05b8 1941 int domain = 0;
dd4ebc2e 1942 int domain_prot;
9ee6e8bb
PB		 1943 uint32_t phys_addr;
1944
1945 /* Pagetable walk. */
1946 /* Lookup l1 descriptor. */
b2fa1797 1947 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1948 desc = ldl_phys(table);
1949 type = (desc & 3);
de9b05b8
PM		 1950 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
1951 /* Section translation fault, or attempt to use the encoding
1952 * which is Reserved on implementations without PXN.
1953 */
9ee6e8bb 1954 code = 5;
9ee6e8bb 1955 goto do_fault;
de9b05b8
PM		 1956 }
1957 if ((type == 1) || !(desc & (1 << 18))) {
1958 /* Page or Section. */
dd4ebc2e 1959 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1960 }
dd4ebc2e
JCD		 1961 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1962 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 1963 if (type != 1) {
9ee6e8bb 1964 code = 9; /* Section domain fault. */
de9b05b8 1965 } else {
9ee6e8bb 1966 code = 11; /* Page domain fault. */
de9b05b8 1967 }
9ee6e8bb
PB		 1968 goto do_fault;
1969 }
de9b05b8 1970 if (type != 1) {
9ee6e8bb
PB		 1971 if (desc & (1 << 18)) {
1972 /* Supersection. */
1973 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1974 *page_size = 0x1000000;
b5ff1b31 1975 } else {
9ee6e8bb
PB		 1976 /* Section. */
1977 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1978 *page_size = 0x100000;
b5ff1b31 1979 }
9ee6e8bb
PB		 1980 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1981 xn = desc & (1 << 4);
de9b05b8 1982 pxn = desc & 1;
9ee6e8bb
PB		 1983 code = 13;
1984 } else {
de9b05b8
PM		 1985 if (arm_feature(env, ARM_FEATURE_PXN)) {
1986 pxn = (desc >> 2) & 1;
1987 }
9ee6e8bb
PB		 1988 /* Lookup l2 entry. */
1989 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1990 desc = ldl_phys(table);
1991 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1992 switch (desc & 3) {
1993 case 0: /* Page translation fault. */
1994 code = 7;
b5ff1b31 1995 goto do_fault;
9ee6e8bb
PB		 1996 case 1: /* 64k page. */
1997 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1998 xn = desc & (1 << 15);
d4c430a8 1999 *page_size = 0x10000;
9ee6e8bb
PB		 2000 break;
2001 case 2: case 3: /* 4k page. */
2002 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2003 xn = desc & 1;
d4c430a8 2004 *page_size = 0x1000;
9ee6e8bb
PB		 2005 break;
2006 default:
2007 /* Never happens, but compiler isn't smart enough to tell. */
2008 abort();
b5ff1b31 2009 }
9ee6e8bb
PB		 2010 code = 15;
2011 }
dd4ebc2e 2012 if (domain_prot == 3) {
c0034328
JR		 2013 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2014 } else {
de9b05b8
PM		 2015 if (pxn && !is_user) {
2016 xn = 1;
2017 }
c0034328
JR		 2018 if (xn && access_type == 2)
2019 goto do_fault;
9ee6e8bb 2020
c0034328
JR		 2021 /* The simplified model uses AP[0] as an access control bit. */
2022 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2023 /* Access flag fault. */
2024 code = (code == 15) ? 6 : 3;
2025 goto do_fault;
2026 }
dd4ebc2e 2027 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2028 if (!*prot) {
2029 /* Access permission fault. */
2030 goto do_fault;
2031 }
2032 if (!xn) {
2033 *prot |= PAGE_EXEC;
2034 }
3ad493fc 2035 }
9ee6e8bb 2036 *phys_ptr = phys_addr;
b5ff1b31
FB		 2037 return 0;
2038do_fault:
2039 return code | (domain << 4);
2040}
2041
0ecb72a5 2042static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 2043 int is_user, uint32_t *phys_ptr, int *prot)
2044{
2045 int n;
2046 uint32_t mask;
2047 uint32_t base;
2048
2049 *phys_ptr = address;
2050 for (n = 7; n >= 0; n--) {
2051 base = env->cp15.c6_region[n];
2052 if ((base & 1) == 0)
2053 continue;
2054 mask = 1 << ((base >> 1) & 0x1f);
2055 /* Keep this shift separate from the above to avoid an
2056 (undefined) << 32. */
2057 mask = (mask << 1) - 1;
2058 if (((base ^ address) & ~mask) == 0)
2059 break;
2060 }
2061 if (n < 0)
2062 return 2;
2063
2064 if (access_type == 2) {
2065 mask = env->cp15.c5_insn;
2066 } else {
2067 mask = env->cp15.c5_data;
2068 }
2069 mask = (mask >> (n * 4)) & 0xf;
2070 switch (mask) {
2071 case 0:
2072 return 1;
2073 case 1:
2074 if (is_user)
2075 return 1;
2076 *prot = PAGE_READ | PAGE_WRITE;
2077 break;
2078 case 2:
2079 *prot = PAGE_READ;
2080 if (!is_user)
2081 *prot |= PAGE_WRITE;
2082 break;
2083 case 3:
2084 *prot = PAGE_READ | PAGE_WRITE;
2085 break;
2086 case 5:
2087 if (is_user)
2088 return 1;
2089 *prot = PAGE_READ;
2090 break;
2091 case 6:
2092 *prot = PAGE_READ;
2093 break;
2094 default:
2095 /* Bad permission. */
2096 return 1;
2097 }
3ad493fc 2098 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2099 return 0;
2100}
2101
0ecb72a5 2102static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2103 int access_type, int is_user,
d4c430a8
PB		 2104 uint32_t *phys_ptr, int *prot,
2105 target_ulong *page_size)
9ee6e8bb
PB		 2106{
2107 /* Fast Context Switch Extension. */
2108 if (address < 0x02000000)
2109 address += env->cp15.c13_fcse;
2110
2111 if ((env->cp15.c1_sys & 1) == 0) {
2112 /* MMU/MPU disabled. */
2113 *phys_ptr = address;
3ad493fc 2114 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2115 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2116 return 0;
2117 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2118 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2119 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2120 prot);
2121 } else if (env->cp15.c1_sys & (1 << 23)) {
2122 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2123 prot, page_size);
9ee6e8bb
PB		 2124 } else {
2125 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2126 prot, page_size);
9ee6e8bb
PB		 2127 }
2128}
2129
0ecb72a5 2130int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2131 int access_type, int mmu_idx)
b5ff1b31
FB		 2132{
2133 uint32_t phys_addr;
d4c430a8 2134 target_ulong page_size;
b5ff1b31 2135 int prot;
6ebbf390 2136 int ret, is_user;
b5ff1b31 2137
6ebbf390 2138 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2139 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2140 &page_size);
b5ff1b31
FB		 2141 if (ret == 0) {
2142 /* Map a single [sub]page. */
2143 phys_addr &= ~(uint32_t)0x3ff;
2144 address &= ~(uint32_t)0x3ff;
3ad493fc 2145 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2146 return 0;
b5ff1b31
FB		 2147 }
2148
2149 if (access_type == 2) {
2150 env->cp15.c5_insn = ret;
2151 env->cp15.c6_insn = address;
2152 env->exception_index = EXCP_PREFETCH_ABORT;
2153 } else {
2154 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2155 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2156 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2157 env->cp15.c6_data = address;
2158 env->exception_index = EXCP_DATA_ABORT;
2159 }
2160 return 1;
2161}
2162
0ecb72a5 2163target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 2164{
2165 uint32_t phys_addr;
d4c430a8 2166 target_ulong page_size;
b5ff1b31
FB		 2167 int prot;
2168 int ret;
2169
d4c430a8 2170 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2171
2172 if (ret != 0)
2173 return -1;
2174
2175 return phys_addr;
2176}
2177
0ecb72a5 2178void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2179{
39ea3d4e
PM		 2180 if ((env->uncached_cpsr & CPSR_M) == mode) {
2181 env->regs[13] = val;
2182 } else {
1b9e01c1 2183 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2184 }
9ee6e8bb
PB		 2185}
2186
0ecb72a5 2187uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2188{
39ea3d4e
PM		 2189 if ((env->uncached_cpsr & CPSR_M) == mode) {
2190 return env->regs[13];
2191 } else {
1b9e01c1 2192 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2193 }
9ee6e8bb
PB		 2194}
2195
0ecb72a5 2196uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2197{
2198 switch (reg) {
2199 case 0: /* APSR */
2200 return xpsr_read(env) & 0xf8000000;
2201 case 1: /* IAPSR */
2202 return xpsr_read(env) & 0xf80001ff;
2203 case 2: /* EAPSR */
2204 return xpsr_read(env) & 0xff00fc00;
2205 case 3: /* xPSR */
2206 return xpsr_read(env) & 0xff00fdff;
2207 case 5: /* IPSR */
2208 return xpsr_read(env) & 0x000001ff;
2209 case 6: /* EPSR */
2210 return xpsr_read(env) & 0x0700fc00;
2211 case 7: /* IEPSR */
2212 return xpsr_read(env) & 0x0700edff;
2213 case 8: /* MSP */
2214 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2215 case 9: /* PSP */
2216 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2217 case 16: /* PRIMASK */
2218 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2219 case 17: /* BASEPRI */
2220 case 18: /* BASEPRI_MAX */
9ee6e8bb 2221 return env->v7m.basepri;
82845826
SH		 2222 case 19: /* FAULTMASK */
2223 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2224 case 20: /* CONTROL */
2225 return env->v7m.control;
2226 default:
2227 /* ??? For debugging only. */
2228 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2229 return 0;
2230 }
2231}
2232
0ecb72a5 2233void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2234{
2235 switch (reg) {
2236 case 0: /* APSR */
2237 xpsr_write(env, val, 0xf8000000);
2238 break;
2239 case 1: /* IAPSR */
2240 xpsr_write(env, val, 0xf8000000);
2241 break;
2242 case 2: /* EAPSR */
2243 xpsr_write(env, val, 0xfe00fc00);
2244 break;
2245 case 3: /* xPSR */
2246 xpsr_write(env, val, 0xfe00fc00);
2247 break;
2248 case 5: /* IPSR */
2249 /* IPSR bits are readonly. */
2250 break;
2251 case 6: /* EPSR */
2252 xpsr_write(env, val, 0x0600fc00);
2253 break;
2254 case 7: /* IEPSR */
2255 xpsr_write(env, val, 0x0600fc00);
2256 break;
2257 case 8: /* MSP */
2258 if (env->v7m.current_sp)
2259 env->v7m.other_sp = val;
2260 else
2261 env->regs[13] = val;
2262 break;
2263 case 9: /* PSP */
2264 if (env->v7m.current_sp)
2265 env->regs[13] = val;
2266 else
2267 env->v7m.other_sp = val;
2268 break;
2269 case 16: /* PRIMASK */
2270 if (val & 1)
2271 env->uncached_cpsr |= CPSR_I;
2272 else
2273 env->uncached_cpsr &= ~CPSR_I;
2274 break;
82845826 2275 case 17: /* BASEPRI */
9ee6e8bb
PB		 2276 env->v7m.basepri = val & 0xff;
2277 break;
82845826 2278 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2279 val &= 0xff;
2280 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2281 env->v7m.basepri = val;
2282 break;
82845826
SH		 2283 case 19: /* FAULTMASK */
2284 if (val & 1)
2285 env->uncached_cpsr |= CPSR_F;
2286 else
2287 env->uncached_cpsr &= ~CPSR_F;
2288 break;
9ee6e8bb
PB		 2289 case 20: /* CONTROL */
2290 env->v7m.control = val & 3;
2291 switch_v7m_sp(env, (val & 2) != 0);
2292 break;
2293 default:
2294 /* ??? For debugging only. */
2295 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2296 return;
2297 }
2298}
2299
b5ff1b31 2300#endif
6ddbc6e4
PB		 2301
2302/* Note that signed overflow is undefined in C. The following routines are
2303 careful to use unsigned types where modulo arithmetic is required.
2304 Failure to do so _will_ break on newer gcc. */
2305
2306/* Signed saturating arithmetic. */
2307
1654b2d6 2308/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2309static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2310{
2311 uint16_t res;
2312
2313 res = a + b;
2314 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2315 if (a & 0x8000)
2316 res = 0x8000;
2317 else
2318 res = 0x7fff;
2319 }
2320 return res;
2321}
2322
1654b2d6 2323/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2324static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2325{
2326 uint8_t res;
2327
2328 res = a + b;
2329 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2330 if (a & 0x80)
2331 res = 0x80;
2332 else
2333 res = 0x7f;
2334 }
2335 return res;
2336}
2337
1654b2d6 2338/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2339static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2340{
2341 uint16_t res;
2342
2343 res = a - b;
2344 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2345 if (a & 0x8000)
2346 res = 0x8000;
2347 else
2348 res = 0x7fff;
2349 }
2350 return res;
2351}
2352
1654b2d6 2353/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2354static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2355{
2356 uint8_t res;
2357
2358 res = a - b;
2359 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2360 if (a & 0x80)
2361 res = 0x80;
2362 else
2363 res = 0x7f;
2364 }
2365 return res;
2366}
2367
2368#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2369#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2370#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2371#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2372#define PFX q
2373
2374#include "op_addsub.h"
2375
2376/* Unsigned saturating arithmetic. */
460a09c1 2377static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2378{
2379 uint16_t res;
2380 res = a + b;
2381 if (res < a)
2382 res = 0xffff;
2383 return res;
2384}
2385
460a09c1 2386static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2387{
4c4fd3f8 2388 if (a > b)
6ddbc6e4
PB		 2389 return a - b;
2390 else
2391 return 0;
2392}
2393
2394static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2395{
2396 uint8_t res;
2397 res = a + b;
2398 if (res < a)
2399 res = 0xff;
2400 return res;
2401}
2402
2403static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2404{
4c4fd3f8 2405 if (a > b)
6ddbc6e4
PB		 2406 return a - b;
2407 else
2408 return 0;
2409}
2410
2411#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2412#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2413#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2414#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2415#define PFX uq
2416
2417#include "op_addsub.h"
2418
2419/* Signed modulo arithmetic. */
2420#define SARITH16(a, b, n, op) do { \
2421 int32_t sum; \
db6e2e65 2422 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2423 RESULT(sum, n, 16); \
2424 if (sum >= 0) \
2425 ge |= 3 << (n * 2); \
2426 } while(0)
2427
2428#define SARITH8(a, b, n, op) do { \
2429 int32_t sum; \
db6e2e65 2430 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2431 RESULT(sum, n, 8); \
2432 if (sum >= 0) \
2433 ge |= 1 << n; \
2434 } while(0)
2435
2436
2437#define ADD16(a, b, n) SARITH16(a, b, n, +)
2438#define SUB16(a, b, n) SARITH16(a, b, n, -)
2439#define ADD8(a, b, n) SARITH8(a, b, n, +)
2440#define SUB8(a, b, n) SARITH8(a, b, n, -)
2441#define PFX s
2442#define ARITH_GE
2443
2444#include "op_addsub.h"
2445
2446/* Unsigned modulo arithmetic. */
2447#define ADD16(a, b, n) do { \
2448 uint32_t sum; \
2449 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2450 RESULT(sum, n, 16); \
a87aa10b 2451 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2452 ge |= 3 << (n * 2); \
2453 } while(0)
2454
2455#define ADD8(a, b, n) do { \
2456 uint32_t sum; \
2457 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2458 RESULT(sum, n, 8); \
a87aa10b
AZ		 2459 if ((sum >> 8) == 1) \
2460 ge |= 1 << n; \
6ddbc6e4
PB		 2461 } while(0)
2462
2463#define SUB16(a, b, n) do { \
2464 uint32_t sum; \
2465 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2466 RESULT(sum, n, 16); \
2467 if ((sum >> 16) == 0) \
2468 ge |= 3 << (n * 2); \
2469 } while(0)
2470
2471#define SUB8(a, b, n) do { \
2472 uint32_t sum; \
2473 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2474 RESULT(sum, n, 8); \
2475 if ((sum >> 8) == 0) \
a87aa10b 2476 ge |= 1 << n; \
6ddbc6e4
PB		 2477 } while(0)
2478
2479#define PFX u
2480#define ARITH_GE
2481
2482#include "op_addsub.h"
2483
2484/* Halved signed arithmetic. */
2485#define ADD16(a, b, n) \
2486 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2487#define SUB16(a, b, n) \
2488 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2489#define ADD8(a, b, n) \
2490 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2491#define SUB8(a, b, n) \
2492 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2493#define PFX sh
2494
2495#include "op_addsub.h"
2496
2497/* Halved unsigned arithmetic. */
2498#define ADD16(a, b, n) \
2499 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2500#define SUB16(a, b, n) \
2501 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2502#define ADD8(a, b, n) \
2503 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2504#define SUB8(a, b, n) \
2505 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2506#define PFX uh
2507
2508#include "op_addsub.h"
2509
2510static inline uint8_t do_usad(uint8_t a, uint8_t b)
2511{
2512 if (a > b)
2513 return a - b;
2514 else
2515 return b - a;
2516}
2517
2518/* Unsigned sum of absolute byte differences. */
2519uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2520{
2521 uint32_t sum;
2522 sum = do_usad(a, b);
2523 sum += do_usad(a >> 8, b >> 8);
2524 sum += do_usad(a >> 16, b >>16);
2525 sum += do_usad(a >> 24, b >> 24);
2526 return sum;
2527}
2528
2529/* For ARMv6 SEL instruction. */
2530uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2531{
2532 uint32_t mask;
2533
2534 mask = 0;
2535 if (flags & 1)
2536 mask |= 0xff;
2537 if (flags & 2)
2538 mask |= 0xff00;
2539 if (flags & 4)
2540 mask |= 0xff0000;
2541 if (flags & 8)
2542 mask |= 0xff000000;
2543 return (a & mask) | (b & ~mask);
2544}
2545
5e3f878a
PB		 2546uint32_t HELPER(logicq_cc)(uint64_t val)
2547{
2548 return (val >> 32) | (val != 0);
2549}
4373f3ce
PB		 2550
2551/* VFP support. We follow the convention used for VFP instrunctions:
2552 Single precition routines have a "s" suffix, double precision a
2553 "d" suffix. */
2554
2555/* Convert host exception flags to vfp form. */
2556static inline int vfp_exceptbits_from_host(int host_bits)
2557{
2558 int target_bits = 0;
2559
2560 if (host_bits & float_flag_invalid)
2561 target_bits |= 1;
2562 if (host_bits & float_flag_divbyzero)
2563 target_bits |= 2;
2564 if (host_bits & float_flag_overflow)
2565 target_bits |= 4;
36802b6b 2566 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2567 target_bits |= 8;
2568 if (host_bits & float_flag_inexact)
2569 target_bits |= 0x10;
cecd8504
PM		 2570 if (host_bits & float_flag_input_denormal)
2571 target_bits |= 0x80;
4373f3ce
PB		 2572 return target_bits;
2573}
2574
0ecb72a5 2575uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2576{
2577 int i;
2578 uint32_t fpscr;
2579
2580 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2581 | (env->vfp.vec_len << 16)
2582 | (env->vfp.vec_stride << 20);
2583 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2584 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2585 fpscr |= vfp_exceptbits_from_host(i);
2586 return fpscr;
2587}
2588
0ecb72a5 2589uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2590{
2591 return HELPER(vfp_get_fpscr)(env);
2592}
2593
4373f3ce
PB		 2594/* Convert vfp exception flags to target form. */
2595static inline int vfp_exceptbits_to_host(int target_bits)
2596{
2597 int host_bits = 0;
2598
2599 if (target_bits & 1)
2600 host_bits |= float_flag_invalid;
2601 if (target_bits & 2)
2602 host_bits |= float_flag_divbyzero;
2603 if (target_bits & 4)
2604 host_bits |= float_flag_overflow;
2605 if (target_bits & 8)
2606 host_bits |= float_flag_underflow;
2607 if (target_bits & 0x10)
2608 host_bits |= float_flag_inexact;
cecd8504
PM		 2609 if (target_bits & 0x80)
2610 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2611 return host_bits;
2612}
2613
0ecb72a5 2614void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2615{
2616 int i;
2617 uint32_t changed;
2618
2619 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2620 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2621 env->vfp.vec_len = (val >> 16) & 7;
2622 env->vfp.vec_stride = (val >> 20) & 3;
2623
2624 changed ^= val;
2625 if (changed & (3 << 22)) {
2626 i = (val >> 22) & 3;
2627 switch (i) {
2628 case 0:
2629 i = float_round_nearest_even;
2630 break;
2631 case 1:
2632 i = float_round_up;
2633 break;
2634 case 2:
2635 i = float_round_down;
2636 break;
2637 case 3:
2638 i = float_round_to_zero;
2639 break;
2640 }
2641 set_float_rounding_mode(i, &env->vfp.fp_status);
2642 }
cecd8504 2643 if (changed & (1 << 24)) {
fe76d976 2644 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2645 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2646 }
5c7908ed
PB		 2647 if (changed & (1 << 25))
2648 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2649
b12c390b 2650 i = vfp_exceptbits_to_host(val);
4373f3ce 2651 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2652 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2653}
2654
0ecb72a5 2655void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2656{
2657 HELPER(vfp_set_fpscr)(env, val);
2658}
2659
4373f3ce
PB		 2660#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2661
2662#define VFP_BINOP(name) \
ae1857ec 2663float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2664{ \
ae1857ec
PM		 2665 float_status *fpst = fpstp; \
2666 return float32_ ## name(a, b, fpst); \
4373f3ce 2667} \
ae1857ec 2668float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2669{ \
ae1857ec
PM		 2670 float_status *fpst = fpstp; \
2671 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2672}
2673VFP_BINOP(add)
2674VFP_BINOP(sub)
2675VFP_BINOP(mul)
2676VFP_BINOP(div)
2677#undef VFP_BINOP
2678
2679float32 VFP_HELPER(neg, s)(float32 a)
2680{
2681 return float32_chs(a);
2682}
2683
2684float64 VFP_HELPER(neg, d)(float64 a)
2685{
66230e0d 2686 return float64_chs(a);
4373f3ce
PB		 2687}
2688
2689float32 VFP_HELPER(abs, s)(float32 a)
2690{
2691 return float32_abs(a);
2692}
2693
2694float64 VFP_HELPER(abs, d)(float64 a)
2695{
66230e0d 2696 return float64_abs(a);
4373f3ce
PB		 2697}
2698
0ecb72a5 2699float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2700{
2701 return float32_sqrt(a, &env->vfp.fp_status);
2702}
2703
0ecb72a5 2704float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2705{
2706 return float64_sqrt(a, &env->vfp.fp_status);
2707}
2708
2709/* XXX: check quiet/signaling case */
2710#define DO_VFP_cmp(p, type) \
0ecb72a5 2711void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2712{ \
2713 uint32_t flags; \
2714 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2715 case 0: flags = 0x6; break; \
2716 case -1: flags = 0x8; break; \
2717 case 1: flags = 0x2; break; \
2718 default: case 2: flags = 0x3; break; \
2719 } \
2720 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2721 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2722} \
0ecb72a5 2723void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2724{ \
2725 uint32_t flags; \
2726 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2727 case 0: flags = 0x6; break; \
2728 case -1: flags = 0x8; break; \
2729 case 1: flags = 0x2; break; \
2730 default: case 2: flags = 0x3; break; \
2731 } \
2732 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2733 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2734}
2735DO_VFP_cmp(s, float32)
2736DO_VFP_cmp(d, float64)
2737#undef DO_VFP_cmp
2738
5500b06c 2739/* Integer to float and float to integer conversions */
4373f3ce 2740
5500b06c
PM		 2741#define CONV_ITOF(name, fsz, sign) \
2742 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2743{ \
2744 float_status *fpst = fpstp; \
85836979 2745 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2746}
2747
5500b06c
PM		 2748#define CONV_FTOI(name, fsz, sign, round) \
2749uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2750{ \
2751 float_status *fpst = fpstp; \
2752 if (float##fsz##_is_any_nan(x)) { \
2753 float_raise(float_flag_invalid, fpst); \
2754 return 0; \
2755 } \
2756 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2757}
2758
5500b06c
PM		 2759#define FLOAT_CONVS(name, p, fsz, sign) \
2760CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2761CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2762CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2763
5500b06c
PM		 2764FLOAT_CONVS(si, s, 32, )
2765FLOAT_CONVS(si, d, 64, )
2766FLOAT_CONVS(ui, s, 32, u)
2767FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2768
5500b06c
PM		 2769#undef CONV_ITOF
2770#undef CONV_FTOI
2771#undef FLOAT_CONVS
4373f3ce
PB		 2772
2773/* floating point conversion */
0ecb72a5 2774float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2775{
2d627737
PM		 2776 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2777 /* ARM requires that S<->D conversion of any kind of NaN generates
2778 * a quiet NaN by forcing the most significant frac bit to 1.
2779 */
2780 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2781}
2782
0ecb72a5 2783float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2784{
2d627737
PM		 2785 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2786 /* ARM requires that S<->D conversion of any kind of NaN generates
2787 * a quiet NaN by forcing the most significant frac bit to 1.
2788 */
2789 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2790}
2791
2792/* VFP3 fixed point conversion. */
622465e1 2793#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2794float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2795 void *fpstp) \
4373f3ce 2796{ \
5500b06c 2797 float_status *fpst = fpstp; \
622465e1 2798 float##fsz tmp; \
5500b06c
PM		 2799 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2800 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2801} \
5500b06c
PM		 2802uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2803 void *fpstp) \
4373f3ce 2804{ \
5500b06c 2805 float_status *fpst = fpstp; \
622465e1
PM		 2806 float##fsz tmp; \
2807 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2808 float_raise(float_flag_invalid, fpst); \
622465e1 2809 return 0; \
09d9487f 2810 } \
5500b06c
PM		 2811 tmp = float##fsz##_scalbn(x, shift, fpst); \
2812 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2813}
2814
2815VFP_CONV_FIX(sh, d, 64, int16, )
2816VFP_CONV_FIX(sl, d, 64, int32, )
2817VFP_CONV_FIX(uh, d, 64, uint16, u)
2818VFP_CONV_FIX(ul, d, 64, uint32, u)
2819VFP_CONV_FIX(sh, s, 32, int16, )
2820VFP_CONV_FIX(sl, s, 32, int32, )
2821VFP_CONV_FIX(uh, s, 32, uint16, u)
2822VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2823#undef VFP_CONV_FIX
2824
60011498 2825/* Half precision conversions. */
0ecb72a5 2826static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2827{
60011498 2828 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2829 float32 r = float16_to_float32(make_float16(a), ieee, s);
2830 if (ieee) {
2831 return float32_maybe_silence_nan(r);
2832 }
2833 return r;
60011498
PB		 2834}
2835
0ecb72a5 2836static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2837{
60011498 2838 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2839 float16 r = float32_to_float16(a, ieee, s);
2840 if (ieee) {
2841 r = float16_maybe_silence_nan(r);
2842 }
2843 return float16_val(r);
60011498
PB		 2844}
2845
0ecb72a5 2846float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2847{
2848 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2849}
2850
0ecb72a5 2851uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2852{
2853 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2854}
2855
0ecb72a5 2856float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2857{
2858 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2859}
2860
0ecb72a5 2861uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2862{
2863 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2864}
2865
dda3ec49 2866#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2867#define float32_three make_float32(0x40400000)
2868#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2869
0ecb72a5 2870float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2871{
dda3ec49
PM		 2872 float_status *s = &env->vfp.standard_fp_status;
2873 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2874 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2875 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2876 float_raise(float_flag_input_denormal, s);
2877 }
dda3ec49
PM		 2878 return float32_two;
2879 }
2880 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2881}
2882
0ecb72a5 2883float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2884{
71826966 2885 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2886 float32 product;
2887 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2888 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2889 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2890 float_raise(float_flag_input_denormal, s);
2891 }
6aae3df1 2892 return float32_one_point_five;
9ea62f57 2893 }
6aae3df1
PM		 2894 product = float32_mul(a, b, s);
2895 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2896}
2897
8f8e3aa4
PB		 2898/* NEON helpers. */
2899
56bf4fe2
CL		 2900/* Constants 256 and 512 are used in some helpers; we avoid relying on
2901 * int->float conversions at run-time. */
2902#define float64_256 make_float64(0x4070000000000000LL)
2903#define float64_512 make_float64(0x4080000000000000LL)
2904
fe0e4872
CL		 2905/* The algorithm that must be used to calculate the estimate
2906 * is specified by the ARM ARM.
2907 */
0ecb72a5 2908static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2909{
1146a817
PM		 2910 /* These calculations mustn't set any fp exception flags,
2911 * so we use a local copy of the fp_status.
2912 */
2913 float_status dummy_status = env->vfp.standard_fp_status;
2914 float_status *s = &dummy_status;
fe0e4872
CL		 2915 /* q = (int)(a * 512.0) */
2916 float64 q = float64_mul(float64_512, a, s);
2917 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2918
2919 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2920 q = int64_to_float64(q_int, s);
2921 q = float64_add(q, float64_half, s);
2922 q = float64_div(q, float64_512, s);
2923 q = float64_div(float64_one, q, s);
2924
2925 /* s = (int)(256.0 * r + 0.5) */
2926 q = float64_mul(q, float64_256, s);
2927 q = float64_add(q, float64_half, s);
2928 q_int = float64_to_int64_round_to_zero(q, s);
2929
2930 /* return (double)s / 256.0 */
2931 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2932}
2933
0ecb72a5 2934float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2935{
fe0e4872
CL		 2936 float_status *s = &env->vfp.standard_fp_status;
2937 float64 f64;
2938 uint32_t val32 = float32_val(a);
2939
2940 int result_exp;
2941 int a_exp = (val32 & 0x7f800000) >> 23;
2942 int sign = val32 & 0x80000000;
2943
2944 if (float32_is_any_nan(a)) {
2945 if (float32_is_signaling_nan(a)) {
2946 float_raise(float_flag_invalid, s);
2947 }
2948 return float32_default_nan;
2949 } else if (float32_is_infinity(a)) {
2950 return float32_set_sign(float32_zero, float32_is_neg(a));
2951 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2952 if (!float32_is_zero(a)) {
2953 float_raise(float_flag_input_denormal, s);
2954 }
fe0e4872
CL		 2955 float_raise(float_flag_divbyzero, s);
2956 return float32_set_sign(float32_infinity, float32_is_neg(a));
2957 } else if (a_exp >= 253) {
2958 float_raise(float_flag_underflow, s);
2959 return float32_set_sign(float32_zero, float32_is_neg(a));
2960 }
2961
2962 f64 = make_float64((0x3feULL << 52)
2963 | ((int64_t)(val32 & 0x7fffff) << 29));
2964
2965 result_exp = 253 - a_exp;
2966
2967 f64 = recip_estimate(f64, env);
2968
2969 val32 = sign
2970 | ((result_exp & 0xff) << 23)
2971 | ((float64_val(f64) >> 29) & 0x7fffff);
2972 return make_float32(val32);
4373f3ce
PB		 2973}
2974
e07be5d2
CL		 2975/* The algorithm that must be used to calculate the estimate
2976 * is specified by the ARM ARM.
2977 */
0ecb72a5 2978static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 2979{
1146a817
PM		 2980 /* These calculations mustn't set any fp exception flags,
2981 * so we use a local copy of the fp_status.
2982 */
2983 float_status dummy_status = env->vfp.standard_fp_status;
2984 float_status *s = &dummy_status;
e07be5d2
CL		 2985 float64 q;
2986 int64_t q_int;
2987
2988 if (float64_lt(a, float64_half, s)) {
2989 /* range 0.25 <= a < 0.5 */
2990
2991 /* a in units of 1/512 rounded down */
2992 /* q0 = (int)(a * 512.0); */
2993 q = float64_mul(float64_512, a, s);
2994 q_int = float64_to_int64_round_to_zero(q, s);
2995
2996 /* reciprocal root r */
2997 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2998 q = int64_to_float64(q_int, s);
2999 q = float64_add(q, float64_half, s);
3000 q = float64_div(q, float64_512, s);
3001 q = float64_sqrt(q, s);
3002 q = float64_div(float64_one, q, s);
3003 } else {
3004 /* range 0.5 <= a < 1.0 */
3005
3006 /* a in units of 1/256 rounded down */
3007 /* q1 = (int)(a * 256.0); */
3008 q = float64_mul(float64_256, a, s);
3009 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3010
3011 /* reciprocal root r */
3012 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3013 q = int64_to_float64(q_int, s);
3014 q = float64_add(q, float64_half, s);
3015 q = float64_div(q, float64_256, s);
3016 q = float64_sqrt(q, s);
3017 q = float64_div(float64_one, q, s);
3018 }
3019 /* r in units of 1/256 rounded to nearest */
3020 /* s = (int)(256.0 * r + 0.5); */
3021
3022 q = float64_mul(q, float64_256,s );
3023 q = float64_add(q, float64_half, s);
3024 q_int = float64_to_int64_round_to_zero(q, s);
3025
3026 /* return (double)s / 256.0;*/
3027 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3028}
3029
0ecb72a5 3030float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3031{
e07be5d2
CL		 3032 float_status *s = &env->vfp.standard_fp_status;
3033 int result_exp;
3034 float64 f64;
3035 uint32_t val;
3036 uint64_t val64;
3037
3038 val = float32_val(a);
3039
3040 if (float32_is_any_nan(a)) {
3041 if (float32_is_signaling_nan(a)) {
3042 float_raise(float_flag_invalid, s);
3043 }
3044 return float32_default_nan;
3045 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3046 if (!float32_is_zero(a)) {
3047 float_raise(float_flag_input_denormal, s);
3048 }
e07be5d2
CL		 3049 float_raise(float_flag_divbyzero, s);
3050 return float32_set_sign(float32_infinity, float32_is_neg(a));
3051 } else if (float32_is_neg(a)) {
3052 float_raise(float_flag_invalid, s);
3053 return float32_default_nan;
3054 } else if (float32_is_infinity(a)) {
3055 return float32_zero;
3056 }
3057
3058 /* Normalize to a double-precision value between 0.25 and 1.0,
3059 * preserving the parity of the exponent. */
3060 if ((val & 0x800000) == 0) {
3061 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3062 | (0x3feULL << 52)
3063 | ((uint64_t)(val & 0x7fffff) << 29));
3064 } else {
3065 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3066 | (0x3fdULL << 52)
3067 | ((uint64_t)(val & 0x7fffff) << 29));
3068 }
3069
3070 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3071
3072 f64 = recip_sqrt_estimate(f64, env);
3073
3074 val64 = float64_val(f64);
3075
26cc6abf 3076 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3077 | ((val64 >> 29) & 0x7fffff);
3078 return make_float32(val);
4373f3ce
PB		 3079}
3080
0ecb72a5 3081uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3082{
fe0e4872
CL		 3083 float64 f64;
3084
3085 if ((a & 0x80000000) == 0) {
3086 return 0xffffffff;
3087 }
3088
3089 f64 = make_float64((0x3feULL << 52)
3090 | ((int64_t)(a & 0x7fffffff) << 21));
3091
3092 f64 = recip_estimate (f64, env);
3093
3094 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3095}
3096
0ecb72a5 3097uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3098{
e07be5d2
CL		 3099 float64 f64;
3100
3101 if ((a & 0xc0000000) == 0) {
3102 return 0xffffffff;
3103 }
3104
3105 if (a & 0x80000000) {
3106 f64 = make_float64((0x3feULL << 52)
3107 | ((uint64_t)(a & 0x7fffffff) << 21));
3108 } else { /* bits 31-30 == '01' */
3109 f64 = make_float64((0x3fdULL << 52)
3110 | ((uint64_t)(a & 0x3fffffff) << 22));
3111 }
3112
3113 f64 = recip_sqrt_estimate(f64, env);
3114
3115 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3116}
fe1479c3 3117
da97f52c
PM		 3118/* VFPv4 fused multiply-accumulate */
3119float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3120{
3121 float_status *fpst = fpstp;
3122 return float32_muladd(a, b, c, 0, fpst);
3123}
3124
3125float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3126{
3127 float_status *fpst = fpstp;
3128 return float64_muladd(a, b, c, 0, fpst);
3129}
Qemu copy for testing