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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
90ed18ca | 4 | Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r |
1e57a462 | 5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __ARM_LIB__\r | |
17 | #define __ARM_LIB__\r | |
18 | \r | |
19 | #include <Uefi/UefiBaseType.h>\r | |
20 | \r | |
25402f5d | 21 | #ifdef MDE_CPU_ARM\r |
70119d27 | 22 | #include <Chipset/ArmV7.h>\r |
25402f5d HL |
23 | #elif defined(MDE_CPU_AARCH64)\r |
24 | #include <Chipset/AArch64.h>\r | |
1e57a462 | 25 | #else\r |
25402f5d | 26 | #error "Unknown chipset."\r |
1e57a462 | 27 | #endif\r |
28 | \r | |
1e57a462 | 29 | /**\r |
30 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r | |
31 | *\r | |
32 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r | |
33 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r | |
34 | */\r | |
35 | typedef enum {\r | |
36 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r | |
37 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r | |
38 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r | |
39 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r | |
40 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r | |
41 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r | |
42 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r | |
43 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r | |
44 | } ARM_MEMORY_REGION_ATTRIBUTES;\r | |
45 | \r | |
46 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r | |
47 | \r | |
48 | typedef struct {\r | |
49 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r | |
50 | EFI_VIRTUAL_ADDRESS VirtualBase;\r | |
c357fd6a | 51 | UINT64 Length;\r |
1e57a462 | 52 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
53 | } ARM_MEMORY_REGION_DESCRIPTOR;\r | |
54 | \r | |
55 | typedef VOID (*CACHE_OPERATION)(VOID);\r | |
56 | typedef VOID (*LINE_OPERATION)(UINTN);\r | |
57 | \r | |
58 | //\r | |
59 | // ARM Processor Mode\r | |
60 | //\r | |
61 | typedef enum {\r | |
62 | ARM_PROCESSOR_MODE_USER = 0x10,\r | |
63 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r | |
64 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r | |
65 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r | |
66 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r | |
67 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r | |
68 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r | |
69 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r | |
70 | ARM_PROCESSOR_MODE_MASK = 0x1F\r | |
71 | } ARM_PROCESSOR_MODE;\r | |
72 | \r | |
73 | //\r | |
74 | // ARM Cpu IDs\r | |
75 | //\r | |
76 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r | |
77 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r | |
78 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r | |
79 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r | |
80 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r | |
81 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r | |
82 | \r | |
83 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r | |
84 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r | |
85 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r | |
86 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r | |
87 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r | |
88 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r | |
89 | \r | |
90 | //\r | |
91 | // ARM MP Core IDs\r | |
92 | //\r | |
90ed18ca OM |
93 | #define ARM_CORE_AFF0 0xFF\r |
94 | #define ARM_CORE_AFF1 (0xFF << 8)\r | |
95 | #define ARM_CORE_AFF2 (0xFF << 16)\r | |
96 | #define ARM_CORE_AFF3 (0xFFULL << 32)\r | |
97 | \r | |
98 | #define ARM_CORE_MASK ARM_CORE_AFF0\r | |
99 | #define ARM_CLUSTER_MASK ARM_CORE_AFF1\r | |
1e57a462 | 100 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r |
101 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r | |
e359565e | 102 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r |
1e57a462 | 103 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
104 | \r | |
1e57a462 | 105 | UINTN\r |
106 | EFIAPI\r | |
107 | ArmDataCacheLineLength (\r | |
108 | VOID\r | |
109 | );\r | |
3402aac7 | 110 | \r |
1e57a462 | 111 | UINTN\r |
112 | EFIAPI\r | |
113 | ArmInstructionCacheLineLength (\r | |
114 | VOID\r | |
115 | );\r | |
168d7245 | 116 | \r |
c653fc2a AB |
117 | UINTN\r |
118 | EFIAPI\r | |
119 | ArmCacheWritebackGranule (\r | |
120 | VOID\r | |
121 | );\r | |
122 | \r | |
168d7245 OM |
123 | UINTN\r |
124 | EFIAPI\r | |
125 | ArmIsArchTimerImplemented (\r | |
126 | VOID\r | |
127 | );\r | |
128 | \r | |
129 | UINTN\r | |
130 | EFIAPI\r | |
131 | ArmReadIdPfr0 (\r | |
132 | VOID\r | |
133 | );\r | |
134 | \r | |
135 | UINTN\r | |
136 | EFIAPI\r | |
137 | ArmReadIdPfr1 (\r | |
138 | VOID\r | |
139 | );\r | |
140 | \r | |
64751727 | 141 | UINTN\r |
1e57a462 | 142 | EFIAPI\r |
64751727 | 143 | ArmCacheInfo (\r |
1e57a462 | 144 | VOID\r |
145 | );\r | |
146 | \r | |
147 | BOOLEAN\r | |
148 | EFIAPI\r | |
149 | ArmIsMpCore (\r | |
150 | VOID\r | |
151 | );\r | |
152 | \r | |
153 | VOID\r | |
154 | EFIAPI\r | |
155 | ArmInvalidateDataCache (\r | |
156 | VOID\r | |
157 | );\r | |
158 | \r | |
159 | \r | |
160 | VOID\r | |
161 | EFIAPI\r | |
162 | ArmCleanInvalidateDataCache (\r | |
163 | VOID\r | |
164 | );\r | |
165 | \r | |
166 | VOID\r | |
167 | EFIAPI\r | |
168 | ArmCleanDataCache (\r | |
169 | VOID\r | |
170 | );\r | |
171 | \r | |
1e57a462 | 172 | VOID\r |
173 | EFIAPI\r | |
174 | ArmInvalidateInstructionCache (\r | |
175 | VOID\r | |
176 | );\r | |
177 | \r | |
178 | VOID\r | |
179 | EFIAPI\r | |
180 | ArmInvalidateDataCacheEntryByMVA (\r | |
181 | IN UINTN Address\r | |
182 | );\r | |
183 | \r | |
184 | VOID\r | |
185 | EFIAPI\r | |
b7de7e3c | 186 | ArmCleanDataCacheEntryToPoUByMVA(\r |
1e57a462 | 187 | IN UINTN Address\r |
188 | );\r | |
189 | \r | |
b7de7e3c EC |
190 | VOID\r |
191 | EFIAPI\r | |
192 | ArmCleanDataCacheEntryByMVA(\r | |
193 | IN UINTN Address\r | |
194 | );\r | |
195 | \r | |
1e57a462 | 196 | VOID\r |
197 | EFIAPI\r | |
198 | ArmCleanInvalidateDataCacheEntryByMVA (\r | |
199 | IN UINTN Address\r | |
200 | );\r | |
201 | \r | |
0ff0e414 OM |
202 | VOID\r |
203 | EFIAPI\r | |
204 | ArmInvalidateDataCacheEntryBySetWay (\r | |
205 | IN UINTN SetWayFormat\r | |
206 | );\r | |
207 | \r | |
208 | VOID\r | |
209 | EFIAPI\r | |
210 | ArmCleanDataCacheEntryBySetWay (\r | |
211 | IN UINTN SetWayFormat\r | |
212 | );\r | |
213 | \r | |
214 | VOID\r | |
215 | EFIAPI\r | |
216 | ArmCleanInvalidateDataCacheEntryBySetWay (\r | |
217 | IN UINTN SetWayFormat\r | |
218 | );\r | |
219 | \r | |
1e57a462 | 220 | VOID\r |
221 | EFIAPI\r | |
222 | ArmEnableDataCache (\r | |
223 | VOID\r | |
224 | );\r | |
225 | \r | |
226 | VOID\r | |
227 | EFIAPI\r | |
228 | ArmDisableDataCache (\r | |
229 | VOID\r | |
230 | );\r | |
231 | \r | |
232 | VOID\r | |
233 | EFIAPI\r | |
234 | ArmEnableInstructionCache (\r | |
235 | VOID\r | |
236 | );\r | |
237 | \r | |
238 | VOID\r | |
239 | EFIAPI\r | |
240 | ArmDisableInstructionCache (\r | |
241 | VOID\r | |
242 | );\r | |
3402aac7 | 243 | \r |
1e57a462 | 244 | VOID\r |
245 | EFIAPI\r | |
246 | ArmEnableMmu (\r | |
247 | VOID\r | |
248 | );\r | |
249 | \r | |
250 | VOID\r | |
251 | EFIAPI\r | |
252 | ArmDisableMmu (\r | |
253 | VOID\r | |
254 | );\r | |
255 | \r | |
0ff0e414 OM |
256 | VOID\r |
257 | EFIAPI\r | |
258 | ArmEnableCachesAndMmu (\r | |
259 | VOID\r | |
260 | );\r | |
261 | \r | |
1e57a462 | 262 | VOID\r |
263 | EFIAPI\r | |
264 | ArmDisableCachesAndMmu (\r | |
265 | VOID\r | |
266 | );\r | |
267 | \r | |
1e57a462 | 268 | VOID\r |
269 | EFIAPI\r | |
270 | ArmEnableInterrupts (\r | |
271 | VOID\r | |
272 | );\r | |
273 | \r | |
274 | UINTN\r | |
275 | EFIAPI\r | |
276 | ArmDisableInterrupts (\r | |
277 | VOID\r | |
278 | );\r | |
47585ed5 | 279 | \r |
1e57a462 | 280 | BOOLEAN\r |
281 | EFIAPI\r | |
282 | ArmGetInterruptState (\r | |
283 | VOID\r | |
284 | );\r | |
285 | \r | |
0ff0e414 OM |
286 | VOID\r |
287 | EFIAPI\r | |
288 | ArmEnableAsynchronousAbort (\r | |
289 | VOID\r | |
290 | );\r | |
291 | \r | |
47585ed5 | 292 | UINTN\r |
293 | EFIAPI\r | |
0ff0e414 | 294 | ArmDisableAsynchronousAbort (\r |
47585ed5 | 295 | VOID\r |
296 | );\r | |
297 | \r | |
298 | VOID\r | |
299 | EFIAPI\r | |
300 | ArmEnableIrq (\r | |
301 | VOID\r | |
302 | );\r | |
303 | \r | |
0ff0e414 OM |
304 | UINTN\r |
305 | EFIAPI\r | |
306 | ArmDisableIrq (\r | |
307 | VOID\r | |
308 | );\r | |
309 | \r | |
1e57a462 | 310 | VOID\r |
311 | EFIAPI\r | |
312 | ArmEnableFiq (\r | |
313 | VOID\r | |
314 | );\r | |
315 | \r | |
316 | UINTN\r | |
317 | EFIAPI\r | |
318 | ArmDisableFiq (\r | |
319 | VOID\r | |
320 | );\r | |
3402aac7 | 321 | \r |
1e57a462 | 322 | BOOLEAN\r |
323 | EFIAPI\r | |
324 | ArmGetFiqState (\r | |
325 | VOID\r | |
326 | );\r | |
327 | \r | |
8dd618d2 OM |
328 | /**\r |
329 | * Invalidate Data and Instruction TLBs\r | |
330 | */\r | |
1e57a462 | 331 | VOID\r |
332 | EFIAPI\r | |
333 | ArmInvalidateTlb (\r | |
334 | VOID\r | |
335 | );\r | |
3402aac7 | 336 | \r |
1e57a462 | 337 | VOID\r |
338 | EFIAPI\r | |
339 | ArmUpdateTranslationTableEntry (\r | |
340 | IN VOID *TranslationTableEntry,\r | |
341 | IN VOID *Mva\r | |
342 | );\r | |
3402aac7 | 343 | \r |
1e57a462 | 344 | VOID\r |
345 | EFIAPI\r | |
346 | ArmSetDomainAccessControl (\r | |
347 | IN UINT32 Domain\r | |
348 | );\r | |
349 | \r | |
350 | VOID\r | |
351 | EFIAPI\r | |
352 | ArmSetTTBR0 (\r | |
353 | IN VOID *TranslationTableBase\r | |
354 | );\r | |
355 | \r | |
356 | VOID *\r | |
357 | EFIAPI\r | |
358 | ArmGetTTBR0BaseAddress (\r | |
359 | VOID\r | |
360 | );\r | |
361 | \r | |
6f050ad6 | 362 | RETURN_STATUS\r |
1e57a462 | 363 | EFIAPI\r |
364 | ArmConfigureMmu (\r | |
365 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
6f050ad6 | 366 | OUT VOID **TranslationTableBase OPTIONAL,\r |
1e57a462 | 367 | OUT UINTN *TranslationTableSize OPTIONAL\r |
368 | );\r | |
3402aac7 | 369 | \r |
1e57a462 | 370 | BOOLEAN\r |
371 | EFIAPI\r | |
372 | ArmMmuEnabled (\r | |
373 | VOID\r | |
374 | );\r | |
3402aac7 | 375 | \r |
1e57a462 | 376 | VOID\r |
377 | EFIAPI\r | |
378 | ArmEnableBranchPrediction (\r | |
379 | VOID\r | |
380 | );\r | |
381 | \r | |
382 | VOID\r | |
383 | EFIAPI\r | |
384 | ArmDisableBranchPrediction (\r | |
385 | VOID\r | |
386 | );\r | |
387 | \r | |
388 | VOID\r | |
389 | EFIAPI\r | |
390 | ArmSetLowVectors (\r | |
391 | VOID\r | |
392 | );\r | |
393 | \r | |
394 | VOID\r | |
395 | EFIAPI\r | |
396 | ArmSetHighVectors (\r | |
397 | VOID\r | |
398 | );\r | |
399 | \r | |
400 | VOID\r | |
401 | EFIAPI\r | |
402 | ArmDataMemoryBarrier (\r | |
403 | VOID\r | |
404 | );\r | |
3402aac7 | 405 | \r |
1e57a462 | 406 | VOID\r |
407 | EFIAPI\r | |
cf93a378 | 408 | ArmDataSynchronizationBarrier (\r |
1e57a462 | 409 | VOID\r |
410 | );\r | |
3402aac7 | 411 | \r |
1e57a462 | 412 | VOID\r |
413 | EFIAPI\r | |
414 | ArmInstructionSynchronizationBarrier (\r | |
415 | VOID\r | |
416 | );\r | |
417 | \r | |
418 | VOID\r | |
419 | EFIAPI\r | |
420 | ArmWriteVBar (\r | |
4e57d6d7 | 421 | IN UINTN VectorBase\r |
1e57a462 | 422 | );\r |
423 | \r | |
4e57d6d7 | 424 | UINTN\r |
1e57a462 | 425 | EFIAPI\r |
426 | ArmReadVBar (\r | |
427 | VOID\r | |
428 | );\r | |
429 | \r | |
430 | VOID\r | |
431 | EFIAPI\r | |
432 | ArmWriteAuxCr (\r | |
433 | IN UINT32 Bit\r | |
434 | );\r | |
435 | \r | |
436 | UINT32\r | |
437 | EFIAPI\r | |
438 | ArmReadAuxCr (\r | |
439 | VOID\r | |
440 | );\r | |
441 | \r | |
442 | VOID\r | |
443 | EFIAPI\r | |
444 | ArmSetAuxCrBit (\r | |
445 | IN UINT32 Bits\r | |
446 | );\r | |
447 | \r | |
448 | VOID\r | |
449 | EFIAPI\r | |
450 | ArmUnsetAuxCrBit (\r | |
451 | IN UINT32 Bits\r | |
452 | );\r | |
453 | \r | |
454 | VOID\r | |
455 | EFIAPI\r | |
456 | ArmCallSEV (\r | |
457 | VOID\r | |
458 | );\r | |
459 | \r | |
460 | VOID\r | |
461 | EFIAPI\r | |
462 | ArmCallWFE (\r | |
463 | VOID\r | |
464 | );\r | |
465 | \r | |
466 | VOID\r | |
467 | EFIAPI\r | |
468 | ArmCallWFI (\r | |
25402f5d | 469 | \r |
1e57a462 | 470 | VOID\r |
471 | );\r | |
472 | \r | |
473 | UINTN\r | |
474 | EFIAPI\r | |
475 | ArmReadMpidr (\r | |
476 | VOID\r | |
477 | );\r | |
478 | \r | |
9401d6f4 OM |
479 | UINTN\r |
480 | EFIAPI\r | |
481 | ArmReadMidr (\r | |
482 | VOID\r | |
483 | );\r | |
484 | \r | |
1e57a462 | 485 | UINT32\r |
486 | EFIAPI\r | |
487 | ArmReadCpacr (\r | |
488 | VOID\r | |
489 | );\r | |
490 | \r | |
491 | VOID\r | |
492 | EFIAPI\r | |
493 | ArmWriteCpacr (\r | |
494 | IN UINT32 Access\r | |
495 | );\r | |
496 | \r | |
497 | VOID\r | |
498 | EFIAPI\r | |
499 | ArmEnableVFP (\r | |
500 | VOID\r | |
501 | );\r | |
502 | \r | |
46d4d75c OM |
503 | /**\r |
504 | Get the Secure Configuration Register value\r | |
505 | \r | |
506 | @return Value read from the Secure Configuration Register\r | |
507 | \r | |
508 | **/\r | |
1e57a462 | 509 | UINT32\r |
510 | EFIAPI\r | |
511 | ArmReadScr (\r | |
512 | VOID\r | |
513 | );\r | |
514 | \r | |
46d4d75c OM |
515 | /**\r |
516 | Set the Secure Configuration Register\r | |
517 | \r | |
518 | @param Value Value to write to the Secure Configuration Register\r | |
519 | \r | |
520 | **/\r | |
1e57a462 | 521 | VOID\r |
522 | EFIAPI\r | |
523 | ArmWriteScr (\r | |
46d4d75c | 524 | IN UINT32 Value\r |
1e57a462 | 525 | );\r |
526 | \r | |
527 | UINT32\r | |
528 | EFIAPI\r | |
529 | ArmReadMVBar (\r | |
530 | VOID\r | |
531 | );\r | |
532 | \r | |
533 | VOID\r | |
534 | EFIAPI\r | |
535 | ArmWriteMVBar (\r | |
536 | IN UINT32 VectorMonitorBase\r | |
537 | );\r | |
538 | \r | |
539 | UINT32\r | |
540 | EFIAPI\r | |
541 | ArmReadSctlr (\r | |
542 | VOID\r | |
543 | );\r | |
544 | \r | |
5ea2c2d3 | 545 | UINTN\r |
546 | EFIAPI\r | |
547 | ArmReadHVBar (\r | |
548 | VOID\r | |
549 | );\r | |
550 | \r | |
551 | VOID\r | |
552 | EFIAPI\r | |
553 | ArmWriteHVBar (\r | |
554 | IN UINTN HypModeVectorBase\r | |
555 | );\r | |
556 | \r | |
52d44f77 OM |
557 | \r |
558 | //\r | |
559 | // Helper functions for accessing CPU ACTLR\r | |
560 | //\r | |
561 | \r | |
562 | UINTN\r | |
563 | EFIAPI\r | |
564 | ArmReadCpuActlr (\r | |
565 | VOID\r | |
566 | );\r | |
567 | \r | |
568 | VOID\r | |
569 | EFIAPI\r | |
570 | ArmWriteCpuActlr (\r | |
571 | IN UINTN Val\r | |
572 | );\r | |
573 | \r | |
574 | VOID\r | |
575 | EFIAPI\r | |
576 | ArmSetCpuActlrBit (\r | |
577 | IN UINTN Bits\r | |
578 | );\r | |
579 | \r | |
580 | VOID\r | |
581 | EFIAPI\r | |
582 | ArmUnsetCpuActlrBit (\r | |
583 | IN UINTN Bits\r | |
584 | );\r | |
585 | \r | |
4d9a4f62 AB |
586 | RETURN_STATUS\r |
587 | ArmSetMemoryRegionNoExec (\r | |
588 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
589 | IN UINT64 Length\r | |
590 | );\r | |
591 | \r | |
592 | RETURN_STATUS\r | |
593 | ArmClearMemoryRegionNoExec (\r | |
594 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
595 | IN UINT64 Length\r | |
596 | );\r | |
597 | \r | |
598 | RETURN_STATUS\r | |
599 | ArmSetMemoryRegionReadOnly (\r | |
600 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
601 | IN UINT64 Length\r | |
602 | );\r | |
603 | \r | |
604 | RETURN_STATUS\r | |
605 | ArmClearMemoryRegionReadOnly (\r | |
606 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
607 | IN UINT64 Length\r | |
608 | );\r | |
609 | \r | |
1e57a462 | 610 | #endif // __ARM_LIB__\r |