]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
kvm: vmx: Implement set_apic_access_page_addr
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d77c26fc 475 } host_state;
9c8cba37 476 struct {
7ffd92c5 477 int vm86_active;
78ac8b47 478 ulong save_rflags;
f5f7b2fe
AK		 479 struct kvm_segment segs[8];
480 } rmode;
481 struct {
482 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 483 struct kvm_save_segment {
484 u16 selector;
485 unsigned long base;
486 u32 limit;
487 u32 ar;
f5f7b2fe 488 } seg[8];
2fb92db1 489 } segment_cache;
2384d2b3 490 int vpid;
04fa4d32 491 bool emulation_required;
3b86cd99
JK		 492
493 /* Support for vnmi-less CPUs */
494 int soft_vnmi_blocked;
495 ktime_t entry_time;
496 s64 vnmi_blocked_time;
a0861c02 497 u32 exit_reason;
4e47c7a6
SY		 498
499 bool rdtscp_enabled;
ec378aee 500
01e439be
YZ		 501 /* Posted interrupt descriptor */
502 struct pi_desc pi_desc;
503
ec378aee
NHE		 504 /* Support for a guest hypervisor (nested VMX) */
505 struct nested_vmx nested;
a7653ecd
RK		 506
507 /* Dynamic PLE window. */
508 int ple_window;
509 bool ple_window_dirty;
a2fa3e9f
GH		 510};
511
2fb92db1
AK		 512enum segment_cache_field {
513 SEG_FIELD_SEL = 0,
514 SEG_FIELD_BASE = 1,
515 SEG_FIELD_LIMIT = 2,
516 SEG_FIELD_AR = 3,
517
518 SEG_FIELD_NR = 4
519};
520
a2fa3e9f
GH		 521static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
522{
fb3f0f51 523 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 524}
525
22bd0358
NHE		 526#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
527#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
528#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
529 [number##_HIGH] = VMCS12_OFFSET(name)+4
530
4607c2d7 531
fe2b201b 532static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 533 /*
534 * We do NOT shadow fields that are modified when L0
535 * traps and emulates any vmx instruction (e.g. VMPTRLD,
536 * VMXON...) executed by L1.
537 * For example, VM_INSTRUCTION_ERROR is read
538 * by L1 if a vmx instruction fails (part of the error path).
539 * Note the code assumes this logic. If for some reason
540 * we start shadowing these fields then we need to
541 * force a shadow sync when L0 emulates vmx instructions
542 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
543 * by nested_vmx_failValid)
544 */
545 VM_EXIT_REASON,
546 VM_EXIT_INTR_INFO,
547 VM_EXIT_INSTRUCTION_LEN,
548 IDT_VECTORING_INFO_FIELD,
549 IDT_VECTORING_ERROR_CODE,
550 VM_EXIT_INTR_ERROR_CODE,
551 EXIT_QUALIFICATION,
552 GUEST_LINEAR_ADDRESS,
553 GUEST_PHYSICAL_ADDRESS
554};
fe2b201b 555static int max_shadow_read_only_fields =
4607c2d7
AG		 556 ARRAY_SIZE(shadow_read_only_fields);
557
fe2b201b 558static unsigned long shadow_read_write_fields[] = {
a7c0b07d 559 TPR_THRESHOLD,
4607c2d7
AG		 560 GUEST_RIP,
561 GUEST_RSP,
562 GUEST_CR0,
563 GUEST_CR3,
564 GUEST_CR4,
565 GUEST_INTERRUPTIBILITY_INFO,
566 GUEST_RFLAGS,
567 GUEST_CS_SELECTOR,
568 GUEST_CS_AR_BYTES,
569 GUEST_CS_LIMIT,
570 GUEST_CS_BASE,
571 GUEST_ES_BASE,
36be0b9d 572 GUEST_BNDCFGS,
4607c2d7
AG		 573 CR0_GUEST_HOST_MASK,
574 CR0_READ_SHADOW,
575 CR4_READ_SHADOW,
576 TSC_OFFSET,
577 EXCEPTION_BITMAP,
578 CPU_BASED_VM_EXEC_CONTROL,
579 VM_ENTRY_EXCEPTION_ERROR_CODE,
580 VM_ENTRY_INTR_INFO_FIELD,
581 VM_ENTRY_INSTRUCTION_LEN,
582 VM_ENTRY_EXCEPTION_ERROR_CODE,
583 HOST_FS_BASE,
584 HOST_GS_BASE,
585 HOST_FS_SELECTOR,
586 HOST_GS_SELECTOR
587};
fe2b201b 588static int max_shadow_read_write_fields =
4607c2d7
AG		 589 ARRAY_SIZE(shadow_read_write_fields);
590
772e0318 591static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 592 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
593 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
594 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
595 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
596 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
597 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
598 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
599 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
600 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
601 FIELD(HOST_ES_SELECTOR, host_es_selector),
602 FIELD(HOST_CS_SELECTOR, host_cs_selector),
603 FIELD(HOST_SS_SELECTOR, host_ss_selector),
604 FIELD(HOST_DS_SELECTOR, host_ds_selector),
605 FIELD(HOST_FS_SELECTOR, host_fs_selector),
606 FIELD(HOST_GS_SELECTOR, host_gs_selector),
607 FIELD(HOST_TR_SELECTOR, host_tr_selector),
608 FIELD64(IO_BITMAP_A, io_bitmap_a),
609 FIELD64(IO_BITMAP_B, io_bitmap_b),
610 FIELD64(MSR_BITMAP, msr_bitmap),
611 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
612 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
613 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
614 FIELD64(TSC_OFFSET, tsc_offset),
615 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
616 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
617 FIELD64(EPT_POINTER, ept_pointer),
618 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
619 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
620 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
621 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
622 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
623 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
624 FIELD64(GUEST_PDPTR0, guest_pdptr0),
625 FIELD64(GUEST_PDPTR1, guest_pdptr1),
626 FIELD64(GUEST_PDPTR2, guest_pdptr2),
627 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 628 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 629 FIELD64(HOST_IA32_PAT, host_ia32_pat),
630 FIELD64(HOST_IA32_EFER, host_ia32_efer),
631 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
632 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
633 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
634 FIELD(EXCEPTION_BITMAP, exception_bitmap),
635 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
636 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
637 FIELD(CR3_TARGET_COUNT, cr3_target_count),
638 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
639 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
640 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
641 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
642 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
643 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
644 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
645 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
646 FIELD(TPR_THRESHOLD, tpr_threshold),
647 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
648 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
649 FIELD(VM_EXIT_REASON, vm_exit_reason),
650 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
651 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
652 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
653 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
654 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
655 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
656 FIELD(GUEST_ES_LIMIT, guest_es_limit),
657 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
658 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
659 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
660 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
661 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
662 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
663 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
664 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
665 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
666 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
667 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
668 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
669 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
670 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
671 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
672 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
673 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
674 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
675 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
676 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
677 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 678 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 679 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
680 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
681 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
682 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
683 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
684 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
685 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
686 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
687 FIELD(EXIT_QUALIFICATION, exit_qualification),
688 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
689 FIELD(GUEST_CR0, guest_cr0),
690 FIELD(GUEST_CR3, guest_cr3),
691 FIELD(GUEST_CR4, guest_cr4),
692 FIELD(GUEST_ES_BASE, guest_es_base),
693 FIELD(GUEST_CS_BASE, guest_cs_base),
694 FIELD(GUEST_SS_BASE, guest_ss_base),
695 FIELD(GUEST_DS_BASE, guest_ds_base),
696 FIELD(GUEST_FS_BASE, guest_fs_base),
697 FIELD(GUEST_GS_BASE, guest_gs_base),
698 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
699 FIELD(GUEST_TR_BASE, guest_tr_base),
700 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
701 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
702 FIELD(GUEST_DR7, guest_dr7),
703 FIELD(GUEST_RSP, guest_rsp),
704 FIELD(GUEST_RIP, guest_rip),
705 FIELD(GUEST_RFLAGS, guest_rflags),
706 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
707 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
708 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
709 FIELD(HOST_CR0, host_cr0),
710 FIELD(HOST_CR3, host_cr3),
711 FIELD(HOST_CR4, host_cr4),
712 FIELD(HOST_FS_BASE, host_fs_base),
713 FIELD(HOST_GS_BASE, host_gs_base),
714 FIELD(HOST_TR_BASE, host_tr_base),
715 FIELD(HOST_GDTR_BASE, host_gdtr_base),
716 FIELD(HOST_IDTR_BASE, host_idtr_base),
717 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
718 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
719 FIELD(HOST_RSP, host_rsp),
720 FIELD(HOST_RIP, host_rip),
721};
722static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
726 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
727 return -1;
728 return vmcs_field_to_offset_table[field];
729}
730
a9d30f33
NHE		 731static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
732{
733 return to_vmx(vcpu)->nested.current_vmcs12;
734}
735
736static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
737{
738 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 739 if (is_error_page(page))
a9d30f33 740 return NULL;
32cad84f 741
a9d30f33
NHE		 742 return page;
743}
744
745static void nested_release_page(struct page *page)
746{
747 kvm_release_page_dirty(page);
748}
749
750static void nested_release_page_clean(struct page *page)
751{
752 kvm_release_page_clean(page);
753}
754
bfd0a56b 755static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 756static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 757static void kvm_cpu_vmxon(u64 addr);
758static void kvm_cpu_vmxoff(void);
93c4adc7 759static bool vmx_mpx_supported(void);
776e58ea 760static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 761static void vmx_set_segment(struct kvm_vcpu *vcpu,
762 struct kvm_segment *var, int seg);
763static void vmx_get_segment(struct kvm_vcpu *vcpu,
764 struct kvm_segment *var, int seg);
d99e4152
GN		 765static bool guest_state_valid(struct kvm_vcpu *vcpu);
766static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 767static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 768static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 769static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 770static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 771
6aa8b732
AK		 772static DEFINE_PER_CPU(struct vmcs *, vmxarea);
773static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 774/*
775 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
776 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
777 */
778static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 779static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 780
3e7c73e9
AK		 781static unsigned long *vmx_io_bitmap_a;
782static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 783static unsigned long *vmx_msr_bitmap_legacy;
784static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 785static unsigned long *vmx_msr_bitmap_legacy_x2apic;
786static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 787static unsigned long *vmx_vmread_bitmap;
788static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 789
110312c8 790static bool cpu_has_load_ia32_efer;
8bf00a52 791static bool cpu_has_load_perf_global_ctrl;
110312c8 792
2384d2b3
SY		 793static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
794static DEFINE_SPINLOCK(vmx_vpid_lock);
795
1c3d14fe 796static struct vmcs_config {
6aa8b732
AK		 797 int size;
798 int order;
799 u32 revision_id;
1c3d14fe
YS		 800 u32 pin_based_exec_ctrl;
801 u32 cpu_based_exec_ctrl;
f78e0e2e 802 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 803 u32 vmexit_ctrl;
804 u32 vmentry_ctrl;
805} vmcs_config;
6aa8b732 806
efff9e53 807static struct vmx_capability {
d56f546d
SY		 808 u32 ept;
809 u32 vpid;
810} vmx_capability;
811
6aa8b732
AK		 812#define VMX_SEGMENT_FIELD(seg) \
813 [VCPU_SREG_##seg] = { \
814 .selector = GUEST_##seg##_SELECTOR, \
815 .base = GUEST_##seg##_BASE, \
816 .limit = GUEST_##seg##_LIMIT, \
817 .ar_bytes = GUEST_##seg##_AR_BYTES, \
818 }
819
772e0318 820static const struct kvm_vmx_segment_field {
6aa8b732
AK		 821 unsigned selector;
822 unsigned base;
823 unsigned limit;
824 unsigned ar_bytes;
825} kvm_vmx_segment_fields[] = {
826 VMX_SEGMENT_FIELD(CS),
827 VMX_SEGMENT_FIELD(DS),
828 VMX_SEGMENT_FIELD(ES),
829 VMX_SEGMENT_FIELD(FS),
830 VMX_SEGMENT_FIELD(GS),
831 VMX_SEGMENT_FIELD(SS),
832 VMX_SEGMENT_FIELD(TR),
833 VMX_SEGMENT_FIELD(LDTR),
834};
835
26bb0981
AK		 836static u64 host_efer;
837
6de4f3ad
AK		 838static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
839
4d56c8a7 840/*
8c06585d 841 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 842 * away by decrementing the array size.
843 */
6aa8b732 844static const u32 vmx_msr_index[] = {
05b3e0c2 845#ifdef CONFIG_X86_64
44ea2b17 846 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 847#endif
8c06585d 848 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 849};
6aa8b732 850
31299944 851static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 852{
853 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
854 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 855 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 856}
857
31299944 858static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 859{
860 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
861 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 862 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 863}
864
31299944 865static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 866{
867 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
868 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 869 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 870}
871
31299944 872static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 873{
874 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
875 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
876}
877
31299944 878static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 879{
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
881 INTR_INFO_VALID_MASK)) ==
882 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
883}
884
31299944 885static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 886{
04547156 887 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 888}
889
31299944 890static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 891{
04547156 892 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 893}
894
31299944 895static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 896{
04547156 897 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 898}
899
31299944 900static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 901{
04547156
SY		 902 return vmcs_config.cpu_based_exec_ctrl &
903 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 904}
905
774ead3a 906static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 907{
04547156
SY		 908 return vmcs_config.cpu_based_2nd_exec_ctrl &
909 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
910}
911
8d14695f
YZ		 912static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
913{
914 return vmcs_config.cpu_based_2nd_exec_ctrl &
915 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
916}
917
83d4c286
YZ		 918static inline bool cpu_has_vmx_apic_register_virt(void)
919{
920 return vmcs_config.cpu_based_2nd_exec_ctrl &
921 SECONDARY_EXEC_APIC_REGISTER_VIRT;
922}
923
c7c9c56c
YZ		 924static inline bool cpu_has_vmx_virtual_intr_delivery(void)
925{
926 return vmcs_config.cpu_based_2nd_exec_ctrl &
927 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
928}
929
01e439be
YZ		 930static inline bool cpu_has_vmx_posted_intr(void)
931{
932 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
933}
934
935static inline bool cpu_has_vmx_apicv(void)
936{
937 return cpu_has_vmx_apic_register_virt() &&
938 cpu_has_vmx_virtual_intr_delivery() &&
939 cpu_has_vmx_posted_intr();
940}
941
04547156
SY		 942static inline bool cpu_has_vmx_flexpriority(void)
943{
944 return cpu_has_vmx_tpr_shadow() &&
945 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 946}
947
e799794e
MT		 948static inline bool cpu_has_vmx_ept_execute_only(void)
949{
31299944 950 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 951}
952
953static inline bool cpu_has_vmx_eptp_uncacheable(void)
954{
31299944 955 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 956}
957
958static inline bool cpu_has_vmx_eptp_writeback(void)
959{
31299944 960 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 961}
962
963static inline bool cpu_has_vmx_ept_2m_page(void)
964{
31299944 965 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 966}
967
878403b7
SY		 968static inline bool cpu_has_vmx_ept_1g_page(void)
969{
31299944 970 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 971}
972
4bc9b982
SY		 973static inline bool cpu_has_vmx_ept_4levels(void)
974{
975 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
976}
977
83c3a331
XH		 978static inline bool cpu_has_vmx_ept_ad_bits(void)
979{
980 return vmx_capability.ept & VMX_EPT_AD_BIT;
981}
982
31299944 983static inline bool cpu_has_vmx_invept_context(void)
d56f546d 984{
31299944 985 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 986}
987
31299944 988static inline bool cpu_has_vmx_invept_global(void)
d56f546d 989{
31299944 990 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 991}
992
518c8aee
GJ		 993static inline bool cpu_has_vmx_invvpid_single(void)
994{
995 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
996}
997
b9d762fa
GJ		 998static inline bool cpu_has_vmx_invvpid_global(void)
999{
1000 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1001}
1002
31299944 1003static inline bool cpu_has_vmx_ept(void)
d56f546d 1004{
04547156
SY		 1005 return vmcs_config.cpu_based_2nd_exec_ctrl &
1006 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1007}
1008
31299944 1009static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1010{
1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1013}
1014
31299944 1015static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1016{
1017 return vmcs_config.cpu_based_2nd_exec_ctrl &
1018 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1019}
1020
31299944 1021static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1022{
6d3e435e 1023 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1024}
1025
31299944 1026static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1027{
04547156
SY		 1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1033{
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_RDTSCP;
1036}
1037
ad756a16
MJ		 1038static inline bool cpu_has_vmx_invpcid(void)
1039{
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_ENABLE_INVPCID;
1042}
1043
31299944 1044static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1045{
1046 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1047}
1048
f5f48ee1
SY		 1049static inline bool cpu_has_vmx_wbinvd_exit(void)
1050{
1051 return vmcs_config.cpu_based_2nd_exec_ctrl &
1052 SECONDARY_EXEC_WBINVD_EXITING;
1053}
1054
abc4fc58
AG		 1055static inline bool cpu_has_vmx_shadow_vmcs(void)
1056{
1057 u64 vmx_msr;
1058 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1059 /* check if the cpu supports writing r/o exit information fields */
1060 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1061 return false;
1062
1063 return vmcs_config.cpu_based_2nd_exec_ctrl &
1064 SECONDARY_EXEC_SHADOW_VMCS;
1065}
1066
04547156
SY		 1067static inline bool report_flexpriority(void)
1068{
1069 return flexpriority_enabled;
1070}
1071
fe3ef05c
NHE		 1072static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1073{
1074 return vmcs12->cpu_based_vm_exec_control & bit;
1075}
1076
1077static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1078{
1079 return (vmcs12->cpu_based_vm_exec_control &
1080 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1081 (vmcs12->secondary_vm_exec_control & bit);
1082}
1083
f5c4368f 1084static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1085{
1086 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1087}
1088
f4124500
JK		 1089static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1090{
1091 return vmcs12->pin_based_vm_exec_control &
1092 PIN_BASED_VMX_PREEMPTION_TIMER;
1093}
1094
155a97a3
NHE		 1095static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1096{
1097 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1098}
1099
644d711a
NHE		 1100static inline bool is_exception(u32 intr_info)
1101{
1102 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1103 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1104}
1105
533558bc
JK		 1106static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1107 u32 exit_intr_info,
1108 unsigned long exit_qualification);
7c177938
NHE		 1109static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1110 struct vmcs12 *vmcs12,
1111 u32 reason, unsigned long qualification);
1112
8b9cf98c 1113static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1114{
1115 int i;
1116
a2fa3e9f 1117 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1118 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1119 return i;
1120 return -1;
1121}
1122
2384d2b3
SY		 1123static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1124{
1125 struct {
1126 u64 vpid : 16;
1127 u64 rsvd : 48;
1128 u64 gva;
1129 } operand = { vpid, 0, gva };
1130
4ecac3fd 1131 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1132 /* CF==1 or ZF==1 --> rc = -1 */
1133 "; ja 1f ; ud2 ; 1:"
1134 : : "a"(&operand), "c"(ext) : "cc", "memory");
1135}
1136
1439442c
SY		 1137static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1138{
1139 struct {
1140 u64 eptp, gpa;
1141 } operand = {eptp, gpa};
1142
4ecac3fd 1143 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1144 /* CF==1 or ZF==1 --> rc = -1 */
1145 "; ja 1f ; ud2 ; 1:\n"
1146 : : "a" (&operand), "c" (ext) : "cc", "memory");
1147}
1148
26bb0981 1149static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1150{
1151 int i;
1152
8b9cf98c 1153 i = __find_msr_index(vmx, msr);
a75beee6 1154 if (i >= 0)
a2fa3e9f 1155 return &vmx->guest_msrs[i];
8b6d44c7 1156 return NULL;
7725f0ba
AK		 1157}
1158
6aa8b732
AK		 1159static void vmcs_clear(struct vmcs *vmcs)
1160{
1161 u64 phys_addr = __pa(vmcs);
1162 u8 error;
1163
4ecac3fd 1164 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1165 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1166 : "cc", "memory");
1167 if (error)
1168 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1169 vmcs, phys_addr);
1170}
1171
d462b819
NHE		 1172static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1173{
1174 vmcs_clear(loaded_vmcs->vmcs);
1175 loaded_vmcs->cpu = -1;
1176 loaded_vmcs->launched = 0;
1177}
1178
7725b894
DX		 1179static void vmcs_load(struct vmcs *vmcs)
1180{
1181 u64 phys_addr = __pa(vmcs);
1182 u8 error;
1183
1184 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1185 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1186 : "cc", "memory");
1187 if (error)
2844d849 1188 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1189 vmcs, phys_addr);
1190}
1191
8f536b76
ZY		 1192#ifdef CONFIG_KEXEC
1193/*
1194 * This bitmap is used to indicate whether the vmclear
1195 * operation is enabled on all cpus. All disabled by
1196 * default.
1197 */
1198static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1199
1200static inline void crash_enable_local_vmclear(int cpu)
1201{
1202 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1203}
1204
1205static inline void crash_disable_local_vmclear(int cpu)
1206{
1207 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1208}
1209
1210static inline int crash_local_vmclear_enabled(int cpu)
1211{
1212 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1213}
1214
1215static void crash_vmclear_local_loaded_vmcss(void)
1216{
1217 int cpu = raw_smp_processor_id();
1218 struct loaded_vmcs *v;
1219
1220 if (!crash_local_vmclear_enabled(cpu))
1221 return;
1222
1223 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1224 loaded_vmcss_on_cpu_link)
1225 vmcs_clear(v->vmcs);
1226}
1227#else
1228static inline void crash_enable_local_vmclear(int cpu) { }
1229static inline void crash_disable_local_vmclear(int cpu) { }
1230#endif /* CONFIG_KEXEC */
1231
d462b819 1232static void __loaded_vmcs_clear(void *arg)
6aa8b732 1233{
d462b819 1234 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1235 int cpu = raw_smp_processor_id();
6aa8b732 1236
d462b819
NHE		 1237 if (loaded_vmcs->cpu != cpu)
1238 return; /* vcpu migration can race with cpu offline */
1239 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1240 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1241 crash_disable_local_vmclear(cpu);
d462b819 1242 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1243
1244 /*
1245 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1246 * is before setting loaded_vmcs->vcpu to -1 which is done in
1247 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1248 * then adds the vmcs into percpu list before it is deleted.
1249 */
1250 smp_wmb();
1251
d462b819 1252 loaded_vmcs_init(loaded_vmcs);
8f536b76 1253 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1254}
1255
d462b819 1256static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1257{
e6c7d321
XG		 1258 int cpu = loaded_vmcs->cpu;
1259
1260 if (cpu != -1)
1261 smp_call_function_single(cpu,
1262 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1263}
1264
1760dd49 1265static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1266{
1267 if (vmx->vpid == 0)
1268 return;
1269
518c8aee
GJ		 1270 if (cpu_has_vmx_invvpid_single())
1271 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1272}
1273
b9d762fa
GJ		 1274static inline void vpid_sync_vcpu_global(void)
1275{
1276 if (cpu_has_vmx_invvpid_global())
1277 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1278}
1279
1280static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1281{
1282 if (cpu_has_vmx_invvpid_single())
1760dd49 1283 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1284 else
1285 vpid_sync_vcpu_global();
1286}
1287
1439442c
SY		 1288static inline void ept_sync_global(void)
1289{
1290 if (cpu_has_vmx_invept_global())
1291 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1292}
1293
1294static inline void ept_sync_context(u64 eptp)
1295{
089d034e 1296 if (enable_ept) {
1439442c
SY		 1297 if (cpu_has_vmx_invept_context())
1298 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1299 else
1300 ept_sync_global();
1301 }
1302}
1303
96304217 1304static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1305{
5e520e62 1306 unsigned long value;
6aa8b732 1307
5e520e62
AK		 1308 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1309 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1310 return value;
1311}
1312
96304217 1313static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1314{
1315 return vmcs_readl(field);
1316}
1317
96304217 1318static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1319{
1320 return vmcs_readl(field);
1321}
1322
96304217 1323static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1324{
05b3e0c2 1325#ifdef CONFIG_X86_64
6aa8b732
AK		 1326 return vmcs_readl(field);
1327#else
1328 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1329#endif
1330}
1331
e52de1b8
AK		 1332static noinline void vmwrite_error(unsigned long field, unsigned long value)
1333{
1334 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1335 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1336 dump_stack();
1337}
1338
6aa8b732
AK		 1339static void vmcs_writel(unsigned long field, unsigned long value)
1340{
1341 u8 error;
1342
4ecac3fd 1343 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1344 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1345 if (unlikely(error))
1346 vmwrite_error(field, value);
6aa8b732
AK		 1347}
1348
1349static void vmcs_write16(unsigned long field, u16 value)
1350{
1351 vmcs_writel(field, value);
1352}
1353
1354static void vmcs_write32(unsigned long field, u32 value)
1355{
1356 vmcs_writel(field, value);
1357}
1358
1359static void vmcs_write64(unsigned long field, u64 value)
1360{
6aa8b732 1361 vmcs_writel(field, value);
7682f2d0 1362#ifndef CONFIG_X86_64
6aa8b732
AK		 1363 asm volatile ("");
1364 vmcs_writel(field+1, value >> 32);
1365#endif
1366}
1367
2ab455cc
AL		 1368static void vmcs_clear_bits(unsigned long field, u32 mask)
1369{
1370 vmcs_writel(field, vmcs_readl(field) & ~mask);
1371}
1372
1373static void vmcs_set_bits(unsigned long field, u32 mask)
1374{
1375 vmcs_writel(field, vmcs_readl(field) | mask);
1376}
1377
2961e876
GN		 1378static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1379{
1380 vmcs_write32(VM_ENTRY_CONTROLS, val);
1381 vmx->vm_entry_controls_shadow = val;
1382}
1383
1384static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1385{
1386 if (vmx->vm_entry_controls_shadow != val)
1387 vm_entry_controls_init(vmx, val);
1388}
1389
1390static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1391{
1392 return vmx->vm_entry_controls_shadow;
1393}
1394
1395
1396static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1397{
1398 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1399}
1400
1401static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1402{
1403 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1404}
1405
1406static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1407{
1408 vmcs_write32(VM_EXIT_CONTROLS, val);
1409 vmx->vm_exit_controls_shadow = val;
1410}
1411
1412static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1413{
1414 if (vmx->vm_exit_controls_shadow != val)
1415 vm_exit_controls_init(vmx, val);
1416}
1417
1418static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1419{
1420 return vmx->vm_exit_controls_shadow;
1421}
1422
1423
1424static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1425{
1426 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1427}
1428
1429static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1430{
1431 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1432}
1433
2fb92db1
AK		 1434static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1435{
1436 vmx->segment_cache.bitmask = 0;
1437}
1438
1439static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1440 unsigned field)
1441{
1442 bool ret;
1443 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1444
1445 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1446 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1447 vmx->segment_cache.bitmask = 0;
1448 }
1449 ret = vmx->segment_cache.bitmask & mask;
1450 vmx->segment_cache.bitmask |= mask;
1451 return ret;
1452}
1453
1454static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1455{
1456 u16 *p = &vmx->segment_cache.seg[seg].selector;
1457
1458 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1459 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1460 return *p;
1461}
1462
1463static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1464{
1465 ulong *p = &vmx->segment_cache.seg[seg].base;
1466
1467 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1468 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1469 return *p;
1470}
1471
1472static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1473{
1474 u32 *p = &vmx->segment_cache.seg[seg].limit;
1475
1476 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1477 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1478 return *p;
1479}
1480
1481static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1482{
1483 u32 *p = &vmx->segment_cache.seg[seg].ar;
1484
1485 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1486 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1487 return *p;
1488}
1489
abd3f2d6
AK		 1490static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1491{
1492 u32 eb;
1493
fd7373cc
JK		 1494 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1495 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1496 if ((vcpu->guest_debug &
1497 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1498 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1499 eb |= 1u << BP_VECTOR;
7ffd92c5 1500 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1501 eb = ~0;
089d034e 1502 if (enable_ept)
1439442c 1503 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1504 if (vcpu->fpu_active)
1505 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1506
1507 /* When we are running a nested L2 guest and L1 specified for it a
1508 * certain exception bitmap, we must trap the same exceptions and pass
1509 * them to L1. When running L2, we will only handle the exceptions
1510 * specified above if L1 did not want them.
1511 */
1512 if (is_guest_mode(vcpu))
1513 eb |= get_vmcs12(vcpu)->exception_bitmap;
1514
abd3f2d6
AK		 1515 vmcs_write32(EXCEPTION_BITMAP, eb);
1516}
1517
2961e876
GN		 1518static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1519 unsigned long entry, unsigned long exit)
8bf00a52 1520{
2961e876
GN		 1521 vm_entry_controls_clearbit(vmx, entry);
1522 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1523}
1524
61d2ef2c
AK		 1525static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1526{
1527 unsigned i;
1528 struct msr_autoload *m = &vmx->msr_autoload;
1529
8bf00a52
GN		 1530 switch (msr) {
1531 case MSR_EFER:
1532 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1533 clear_atomic_switch_msr_special(vmx,
1534 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1535 VM_EXIT_LOAD_IA32_EFER);
1536 return;
1537 }
1538 break;
1539 case MSR_CORE_PERF_GLOBAL_CTRL:
1540 if (cpu_has_load_perf_global_ctrl) {
2961e876 1541 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1542 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1543 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1544 return;
1545 }
1546 break;
110312c8
AK		 1547 }
1548
61d2ef2c
AK		 1549 for (i = 0; i < m->nr; ++i)
1550 if (m->guest[i].index == msr)
1551 break;
1552
1553 if (i == m->nr)
1554 return;
1555 --m->nr;
1556 m->guest[i] = m->guest[m->nr];
1557 m->host[i] = m->host[m->nr];
1558 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1559 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1560}
1561
2961e876
GN		 1562static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1563 unsigned long entry, unsigned long exit,
1564 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1565 u64 guest_val, u64 host_val)
8bf00a52
GN		 1566{
1567 vmcs_write64(guest_val_vmcs, guest_val);
1568 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1569 vm_entry_controls_setbit(vmx, entry);
1570 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1571}
1572
61d2ef2c
AK		 1573static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1574 u64 guest_val, u64 host_val)
1575{
1576 unsigned i;
1577 struct msr_autoload *m = &vmx->msr_autoload;
1578
8bf00a52
GN		 1579 switch (msr) {
1580 case MSR_EFER:
1581 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1582 add_atomic_switch_msr_special(vmx,
1583 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1584 VM_EXIT_LOAD_IA32_EFER,
1585 GUEST_IA32_EFER,
1586 HOST_IA32_EFER,
1587 guest_val, host_val);
1588 return;
1589 }
1590 break;
1591 case MSR_CORE_PERF_GLOBAL_CTRL:
1592 if (cpu_has_load_perf_global_ctrl) {
2961e876 1593 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1594 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1595 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1596 GUEST_IA32_PERF_GLOBAL_CTRL,
1597 HOST_IA32_PERF_GLOBAL_CTRL,
1598 guest_val, host_val);
1599 return;
1600 }
1601 break;
110312c8
AK		 1602 }
1603
61d2ef2c
AK		 1604 for (i = 0; i < m->nr; ++i)
1605 if (m->guest[i].index == msr)
1606 break;
1607
e7fc6f93 1608 if (i == NR_AUTOLOAD_MSRS) {
60266204 1609 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1610 "Can't add msr %x\n", msr);
1611 return;
1612 } else if (i == m->nr) {
61d2ef2c
AK		 1613 ++m->nr;
1614 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1615 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1616 }
1617
1618 m->guest[i].index = msr;
1619 m->guest[i].value = guest_val;
1620 m->host[i].index = msr;
1621 m->host[i].value = host_val;
1622}
1623
33ed6329
AK		 1624static void reload_tss(void)
1625{
33ed6329
AK		 1626 /*
1627 * VT restores TR but not its size. Useless.
1628 */
d359192f 1629 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1630 struct desc_struct *descs;
33ed6329 1631
d359192f 1632 descs = (void *)gdt->address;
33ed6329
AK		 1633 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1634 load_TR_desc();
33ed6329
AK		 1635}
1636
92c0d900 1637static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1638{
3a34a881 1639 u64 guest_efer;
51c6cf66
AK		 1640 u64 ignore_bits;
1641
f6801dff 1642 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1643
51c6cf66 1644 /*
0fa06071 1645 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1646 * outside long mode
1647 */
1648 ignore_bits = EFER_NX | EFER_SCE;
1649#ifdef CONFIG_X86_64
1650 ignore_bits |= EFER_LMA | EFER_LME;
1651 /* SCE is meaningful only in long mode on Intel */
1652 if (guest_efer & EFER_LMA)
1653 ignore_bits &= ~(u64)EFER_SCE;
1654#endif
51c6cf66
AK		 1655 guest_efer &= ~ignore_bits;
1656 guest_efer |= host_efer & ignore_bits;
26bb0981 1657 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1658 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1659
1660 clear_atomic_switch_msr(vmx, MSR_EFER);
1661 /* On ept, can't emulate nx, and must switch nx atomically */
1662 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1663 guest_efer = vmx->vcpu.arch.efer;
1664 if (!(guest_efer & EFER_LMA))
1665 guest_efer &= ~EFER_LME;
1666 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1667 return false;
1668 }
1669
26bb0981 1670 return true;
51c6cf66
AK		 1671}
1672
2d49ec72
GN		 1673static unsigned long segment_base(u16 selector)
1674{
d359192f 1675 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1676 struct desc_struct *d;
1677 unsigned long table_base;
1678 unsigned long v;
1679
1680 if (!(selector & ~3))
1681 return 0;
1682
d359192f 1683 table_base = gdt->address;
2d49ec72
GN		 1684
1685 if (selector & 4) { /* from ldt */
1686 u16 ldt_selector = kvm_read_ldt();
1687
1688 if (!(ldt_selector & ~3))
1689 return 0;
1690
1691 table_base = segment_base(ldt_selector);
1692 }
1693 d = (struct desc_struct *)(table_base + (selector & ~7));
1694 v = get_desc_base(d);
1695#ifdef CONFIG_X86_64
1696 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1697 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1698#endif
1699 return v;
1700}
1701
1702static inline unsigned long kvm_read_tr_base(void)
1703{
1704 u16 tr;
1705 asm("str %0" : "=g"(tr));
1706 return segment_base(tr);
1707}
1708
04d2cc77 1709static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1710{
04d2cc77 1711 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1712 int i;
04d2cc77 1713
a2fa3e9f 1714 if (vmx->host_state.loaded)
33ed6329
AK		 1715 return;
1716
a2fa3e9f 1717 vmx->host_state.loaded = 1;
33ed6329
AK		 1718 /*
1719 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1720 * allow segment selectors with cpl > 0 or ti == 1.
1721 */
d6e88aec 1722 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1723 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1724 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1725 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1726 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1727 vmx->host_state.fs_reload_needed = 0;
1728 } else {
33ed6329 1729 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1730 vmx->host_state.fs_reload_needed = 1;
33ed6329 1731 }
9581d442 1732 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1733 if (!(vmx->host_state.gs_sel & 7))
1734 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1735 else {
1736 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1737 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1738 }
1739
b2da15ac
AK		 1740#ifdef CONFIG_X86_64
1741 savesegment(ds, vmx->host_state.ds_sel);
1742 savesegment(es, vmx->host_state.es_sel);
1743#endif
1744
33ed6329
AK		 1745#ifdef CONFIG_X86_64
1746 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1747 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1748#else
a2fa3e9f
GH		 1749 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1750 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1751#endif
707c0874
AK		 1752
1753#ifdef CONFIG_X86_64
c8770e7b
AK		 1754 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1755 if (is_long_mode(&vmx->vcpu))
44ea2b17 1756 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1757#endif
da8999d3
LJ		 1758 if (boot_cpu_has(X86_FEATURE_MPX))
1759 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1760 for (i = 0; i < vmx->save_nmsrs; ++i)
1761 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1762 vmx->guest_msrs[i].data,
1763 vmx->guest_msrs[i].mask);
33ed6329
AK		 1764}
1765
a9b21b62 1766static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1767{
a2fa3e9f 1768 if (!vmx->host_state.loaded)
33ed6329
AK		 1769 return;
1770
e1beb1d3 1771 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1772 vmx->host_state.loaded = 0;
c8770e7b
AK		 1773#ifdef CONFIG_X86_64
1774 if (is_long_mode(&vmx->vcpu))
1775 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1776#endif
152d3f2f 1777 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1778 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1779#ifdef CONFIG_X86_64
9581d442 1780 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1781#else
1782 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1783#endif
33ed6329 1784 }
0a77fe4c
AK		 1785 if (vmx->host_state.fs_reload_needed)
1786 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1787#ifdef CONFIG_X86_64
1788 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1789 loadsegment(ds, vmx->host_state.ds_sel);
1790 loadsegment(es, vmx->host_state.es_sel);
1791 }
b2da15ac 1792#endif
152d3f2f 1793 reload_tss();
44ea2b17 1794#ifdef CONFIG_X86_64
c8770e7b 1795 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1796#endif
da8999d3
LJ		 1797 if (vmx->host_state.msr_host_bndcfgs)
1798 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1799 /*
1800 * If the FPU is not active (through the host task or
1801 * the guest vcpu), then restore the cr0.TS bit.
1802 */
1803 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1804 stts();
3444d7da 1805 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1806}
1807
a9b21b62
AK		 1808static void vmx_load_host_state(struct vcpu_vmx *vmx)
1809{
1810 preempt_disable();
1811 __vmx_load_host_state(vmx);
1812 preempt_enable();
1813}
1814
6aa8b732
AK		 1815/*
1816 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1817 * vcpu mutex is already taken.
1818 */
15ad7146 1819static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1820{
a2fa3e9f 1821 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1822 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1823
4610c9cc
DX		 1824 if (!vmm_exclusive)
1825 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1826 else if (vmx->loaded_vmcs->cpu != cpu)
1827 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1828
d462b819
NHE		 1829 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1830 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1831 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1832 }
1833
d462b819 1834 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1835 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1836 unsigned long sysenter_esp;
1837
a8eeb04a 1838 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1839 local_irq_disable();
8f536b76 1840 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1841
1842 /*
1843 * Read loaded_vmcs->cpu should be before fetching
1844 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1845 * See the comments in __loaded_vmcs_clear().
1846 */
1847 smp_rmb();
1848
d462b819
NHE		 1849 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1850 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1851 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1852 local_irq_enable();
1853
6aa8b732
AK		 1854 /*
1855 * Linux uses per-cpu TSS and GDT, so set these when switching
1856 * processors.
1857 */
d6e88aec 1858 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1859 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1860
1861 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1862 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1863 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1864 }
6aa8b732
AK		 1865}
1866
1867static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1868{
a9b21b62 1869 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1870 if (!vmm_exclusive) {
d462b819
NHE		 1871 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1872 vcpu->cpu = -1;
4610c9cc
DX		 1873 kvm_cpu_vmxoff();
1874 }
6aa8b732
AK		 1875}
1876
5fd86fcf
AK		 1877static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1878{
81231c69
AK		 1879 ulong cr0;
1880
5fd86fcf
AK		 1881 if (vcpu->fpu_active)
1882 return;
1883 vcpu->fpu_active = 1;
81231c69
AK		 1884 cr0 = vmcs_readl(GUEST_CR0);
1885 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1886 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1887 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1888 update_exception_bitmap(vcpu);
edcafe3c 1889 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1890 if (is_guest_mode(vcpu))
1891 vcpu->arch.cr0_guest_owned_bits &=
1892 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1893 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1894}
1895
edcafe3c
AK		 1896static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1897
fe3ef05c
NHE		 1898/*
1899 * Return the cr0 value that a nested guest would read. This is a combination
1900 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1901 * its hypervisor (cr0_read_shadow).
1902 */
1903static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1904{
1905 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1906 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1907}
1908static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1909{
1910 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1911 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1912}
1913
5fd86fcf
AK		 1914static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1915{
36cf24e0
NHE		 1916 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1917 * set this *before* calling this function.
1918 */
edcafe3c 1919 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1920 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1921 update_exception_bitmap(vcpu);
edcafe3c
AK		 1922 vcpu->arch.cr0_guest_owned_bits = 0;
1923 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1924 if (is_guest_mode(vcpu)) {
1925 /*
1926 * L1's specified read shadow might not contain the TS bit,
1927 * so now that we turned on shadowing of this bit, we need to
1928 * set this bit of the shadow. Like in nested_vmx_run we need
1929 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1930 * up-to-date here because we just decached cr0.TS (and we'll
1931 * only update vmcs12->guest_cr0 on nested exit).
1932 */
1933 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1934 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1935 (vcpu->arch.cr0 & X86_CR0_TS);
1936 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1937 } else
1938 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1939}
1940
6aa8b732
AK		 1941static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1942{
78ac8b47 1943 unsigned long rflags, save_rflags;
345dcaa8 1944
6de12732
AK		 1945 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1946 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1947 rflags = vmcs_readl(GUEST_RFLAGS);
1948 if (to_vmx(vcpu)->rmode.vm86_active) {
1949 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1950 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1951 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1952 }
1953 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1954 }
6de12732 1955 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1956}
1957
1958static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1959{
6de12732
AK		 1960 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1961 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1962 if (to_vmx(vcpu)->rmode.vm86_active) {
1963 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1964 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1965 }
6aa8b732
AK		 1966 vmcs_writel(GUEST_RFLAGS, rflags);
1967}
1968
37ccdcbe 1969static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1970{
1971 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1972 int ret = 0;
1973
1974 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1975 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1976 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1977 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1978
37ccdcbe 1979 return ret;
2809f5d2
GC		 1980}
1981
1982static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1983{
1984 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1985 u32 interruptibility = interruptibility_old;
1986
1987 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1988
48005f64 1989 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1990 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1991 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1992 interruptibility |= GUEST_INTR_STATE_STI;
1993
1994 if ((interruptibility != interruptibility_old))
1995 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1996}
1997
6aa8b732
AK		 1998static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1999{
2000 unsigned long rip;
6aa8b732 2001
5fdbf976 2002 rip = kvm_rip_read(vcpu);
6aa8b732 2003 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2004 kvm_rip_write(vcpu, rip);
6aa8b732 2005
2809f5d2
GC		 2006 /* skipping an emulated instruction also counts */
2007 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2008}
2009
0b6ac343
NHE		 2010/*
2011 * KVM wants to inject page-faults which it got to the guest. This function
2012 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2013 */
e011c663 2014static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2015{
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017
e011c663 2018 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2019 return 0;
2020
533558bc
JK		 2021 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2022 vmcs_read32(VM_EXIT_INTR_INFO),
2023 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2024 return 1;
2025}
2026
298101da 2027static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2028 bool has_error_code, u32 error_code,
2029 bool reinject)
298101da 2030{
77ab6db0 2031 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2032 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2033
e011c663
GN		 2034 if (!reinject && is_guest_mode(vcpu) &&
2035 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2036 return;
2037
8ab2d2e2 2038 if (has_error_code) {
77ab6db0 2039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2040 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2041 }
77ab6db0 2042
7ffd92c5 2043 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2044 int inc_eip = 0;
2045 if (kvm_exception_is_soft(nr))
2046 inc_eip = vcpu->arch.event_exit_inst_len;
2047 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2048 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2049 return;
2050 }
2051
66fd3f7f
GN		 2052 if (kvm_exception_is_soft(nr)) {
2053 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2054 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2055 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2056 } else
2057 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2058
2059 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2060}
2061
4e47c7a6
SY		 2062static bool vmx_rdtscp_supported(void)
2063{
2064 return cpu_has_vmx_rdtscp();
2065}
2066
ad756a16
MJ		 2067static bool vmx_invpcid_supported(void)
2068{
2069 return cpu_has_vmx_invpcid() && enable_ept;
2070}
2071
a75beee6
ED		 2072/*
2073 * Swap MSR entry in host/guest MSR entry array.
2074 */
8b9cf98c 2075static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2076{
26bb0981 2077 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2078
2079 tmp = vmx->guest_msrs[to];
2080 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2081 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2082}
2083
8d14695f
YZ		 2084static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2085{
2086 unsigned long *msr_bitmap;
2087
2088 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2089 if (is_long_mode(vcpu))
2090 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2091 else
2092 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2093 } else {
2094 if (is_long_mode(vcpu))
2095 msr_bitmap = vmx_msr_bitmap_longmode;
2096 else
2097 msr_bitmap = vmx_msr_bitmap_legacy;
2098 }
2099
2100 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2101}
2102
e38aea3e
AK		 2103/*
2104 * Set up the vmcs to automatically save and restore system
2105 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2106 * mode, as fiddling with msrs is very expensive.
2107 */
8b9cf98c 2108static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2109{
26bb0981 2110 int save_nmsrs, index;
e38aea3e 2111
a75beee6
ED		 2112 save_nmsrs = 0;
2113#ifdef CONFIG_X86_64
8b9cf98c 2114 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2115 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2116 if (index >= 0)
8b9cf98c
RR		 2117 move_msr_up(vmx, index, save_nmsrs++);
2118 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2119 if (index >= 0)
8b9cf98c
RR		 2120 move_msr_up(vmx, index, save_nmsrs++);
2121 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2122 if (index >= 0)
8b9cf98c 2123 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2124 index = __find_msr_index(vmx, MSR_TSC_AUX);
2125 if (index >= 0 && vmx->rdtscp_enabled)
2126 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2127 /*
8c06585d 2128 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2129 * if efer.sce is enabled.
2130 */
8c06585d 2131 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2132 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2133 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2134 }
2135#endif
92c0d900
AK		 2136 index = __find_msr_index(vmx, MSR_EFER);
2137 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2138 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2139
26bb0981 2140 vmx->save_nmsrs = save_nmsrs;
5897297b 2141
8d14695f
YZ		 2142 if (cpu_has_vmx_msr_bitmap())
2143 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2144}
2145
6aa8b732
AK		 2146/*
2147 * reads and returns guest's timestamp counter "register"
2148 * guest_tsc = host_tsc + tsc_offset -- 21.3
2149 */
2150static u64 guest_read_tsc(void)
2151{
2152 u64 host_tsc, tsc_offset;
2153
2154 rdtscll(host_tsc);
2155 tsc_offset = vmcs_read64(TSC_OFFSET);
2156 return host_tsc + tsc_offset;
2157}
2158
d5c1785d
NHE		 2159/*
2160 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2161 * counter, even if a nested guest (L2) is currently running.
2162 */
48d89b92 2163static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2164{
886b470c 2165 u64 tsc_offset;
d5c1785d 2166
d5c1785d
NHE		 2167 tsc_offset = is_guest_mode(vcpu) ?
2168 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2169 vmcs_read64(TSC_OFFSET);
2170 return host_tsc + tsc_offset;
2171}
2172
4051b188 2173/*
cc578287
ZA		 2174 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2175 * software catchup for faster rates on slower CPUs.
4051b188 2176 */
cc578287 2177static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2178{
cc578287
ZA		 2179 if (!scale)
2180 return;
2181
2182 if (user_tsc_khz > tsc_khz) {
2183 vcpu->arch.tsc_catchup = 1;
2184 vcpu->arch.tsc_always_catchup = 1;
2185 } else
2186 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2187}
2188
ba904635
WA		 2189static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2190{
2191 return vmcs_read64(TSC_OFFSET);
2192}
2193
6aa8b732 2194/*
99e3e30a 2195 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2196 */
99e3e30a 2197static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2198{
27fc51b2 2199 if (is_guest_mode(vcpu)) {
7991825b 2200 /*
27fc51b2
NHE		 2201 * We're here if L1 chose not to trap WRMSR to TSC. According
2202 * to the spec, this should set L1's TSC; The offset that L1
2203 * set for L2 remains unchanged, and still needs to be added
2204 * to the newly set TSC to get L2's TSC.
7991825b 2205 */
27fc51b2
NHE		 2206 struct vmcs12 *vmcs12;
2207 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2208 /* recalculate vmcs02.TSC_OFFSET: */
2209 vmcs12 = get_vmcs12(vcpu);
2210 vmcs_write64(TSC_OFFSET, offset +
2211 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2212 vmcs12->tsc_offset : 0));
2213 } else {
489223ed
YY		 2214 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2215 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2216 vmcs_write64(TSC_OFFSET, offset);
2217 }
6aa8b732
AK		 2218}
2219
f1e2b260 2220static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2221{
2222 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2223
e48672fa 2224 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2225 if (is_guest_mode(vcpu)) {
2226 /* Even when running L2, the adjustment needs to apply to L1 */
2227 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2228 } else
2229 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2230 offset + adjustment);
e48672fa
ZA		 2231}
2232
857e4099
JR		 2233static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2234{
2235 return target_tsc - native_read_tsc();
2236}
2237
801d3424
NHE		 2238static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2239{
2240 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2241 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2242}
2243
2244/*
2245 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2246 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2247 * all guests if the "nested" module option is off, and can also be disabled
2248 * for a single guest by disabling its VMX cpuid bit.
2249 */
2250static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2251{
2252 return nested && guest_cpuid_has_vmx(vcpu);
2253}
2254
b87a51ae
NHE		 2255/*
2256 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2257 * returned for the various VMX controls MSRs when nested VMX is enabled.
2258 * The same values should also be used to verify that vmcs12 control fields are
2259 * valid during nested entry from L1 to L2.
2260 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2261 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2262 * bit in the high half is on if the corresponding bit in the control field
2263 * may be on. See also vmx_control_verify().
2264 * TODO: allow these variables to be modified (downgraded) by module options
2265 * or other means.
2266 */
2267static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2268static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2269static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2270static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2271static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2272static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2273static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2274static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2275static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2276static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2277static __init void nested_vmx_setup_ctls_msrs(void)
2278{
2279 /*
2280 * Note that as a general rule, the high half of the MSRs (bits in
2281 * the control fields which may be 1) should be initialized by the
2282 * intersection of the underlying hardware's MSR (i.e., features which
2283 * can be supported) and the list of features we want to expose -
2284 * because they are known to be properly supported in our code.
2285 * Also, usually, the low half of the MSRs (bits which must be 1) can
2286 * be set to 0, meaning that L1 may turn off any of these bits. The
2287 * reason is that if one of these bits is necessary, it will appear
2288 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2289 * fields of vmcs01 and vmcs02, will turn these bits off - and
2290 * nested_vmx_exit_handled() will not pass related exits to L1.
2291 * These rules have exceptions below.
2292 */
2293
2294 /* pin-based controls */
eabeaacc
JK		 2295 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2296 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2297 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2298 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2299 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2300 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2301 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2302
3dbcd8da 2303 /* exit controls */
c0dfee58
ACL		 2304 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2305 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2306 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2307
c0dfee58 2308 nested_vmx_exit_ctls_high &=
b87a51ae 2309#ifdef CONFIG_X86_64
c0dfee58 2310 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2311#endif
f4124500
JK		 2312 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2313 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2314 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2315 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2316
36be0b9d
PB		 2317 if (vmx_mpx_supported())
2318 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2319
2996fca0
JK		 2320 /* We support free control of debug control saving. */
2321 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2322 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2323
b87a51ae
NHE		 2324 /* entry controls */
2325 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2326 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2327 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2328 nested_vmx_entry_ctls_high &=
57435349
JK		 2329#ifdef CONFIG_X86_64
2330 VM_ENTRY_IA32E_MODE |
2331#endif
2332 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2333 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2334 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2335 if (vmx_mpx_supported())
2336 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2337
2996fca0
JK		 2338 /* We support free control of debug control loading. */
2339 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2340 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2341
b87a51ae
NHE		 2342 /* cpu-based controls */
2343 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2344 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2345 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2346 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2347 CPU_BASED_VIRTUAL_INTR_PENDING |
2348 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2349 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2350 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2351 CPU_BASED_CR3_STORE_EXITING |
2352#ifdef CONFIG_X86_64
2353 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2354#endif
2355 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2356 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2357 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2358 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2359 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2360 /*
2361 * We can allow some features even when not supported by the
2362 * hardware. For example, L1 can specify an MSR bitmap - and we
2363 * can use it to avoid exits to L1 - even when L0 runs L2
2364 * without MSR bitmaps.
2365 */
560b7ee1
JK		 2366 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2367 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2368
3dcdf3ec
JK		 2369 /* We support free control of CR3 access interception. */
2370 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2371 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2372
b87a51ae
NHE		 2373 /* secondary cpu-based controls */
2374 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2375 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2376 nested_vmx_secondary_ctls_low = 0;
2377 nested_vmx_secondary_ctls_high &=
d6851fbe 2378 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2379 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2380 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2381
afa61f75
NHE		 2382 if (enable_ept) {
2383 /* nested EPT: emulate EPT also to L1 */
2384 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2385 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2386 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2387 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2388 nested_vmx_ept_caps &= vmx_capability.ept;
2389 /*
4b855078
BD		 2390 * For nested guests, we don't do anything specific
2391 * for single context invalidation. Hence, only advertise
2392 * support for global context invalidation.
afa61f75 2393 */
4b855078 2394 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2395 } else
2396 nested_vmx_ept_caps = 0;
2397
c18911a2
JK		 2398 /* miscellaneous data */
2399 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2400 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2401 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2402 VMX_MISC_ACTIVITY_HLT;
c18911a2 2403 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2404}
2405
2406static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2407{
2408 /*
2409 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2410 */
2411 return ((control & high) | low) == control;
2412}
2413
2414static inline u64 vmx_control_msr(u32 low, u32 high)
2415{
2416 return low | ((u64)high << 32);
2417}
2418
cae50139 2419/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2420static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2421{
b87a51ae 2422 switch (msr_index) {
b87a51ae
NHE		 2423 case MSR_IA32_VMX_BASIC:
2424 /*
2425 * This MSR reports some information about VMX support. We
2426 * should return information about the VMX we emulate for the
2427 * guest, and the VMCS structure we give it - not about the
2428 * VMX support of the underlying hardware.
2429 */
3dbcd8da 2430 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2431 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2432 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2433 break;
2434 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2435 case MSR_IA32_VMX_PINBASED_CTLS:
2436 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2437 nested_vmx_pinbased_ctls_high);
2438 break;
2439 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2440 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2441 nested_vmx_procbased_ctls_high);
2442 break;
b87a51ae
NHE		 2443 case MSR_IA32_VMX_PROCBASED_CTLS:
2444 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2445 nested_vmx_procbased_ctls_high);
2446 break;
2447 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2448 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2449 nested_vmx_exit_ctls_high);
2450 break;
b87a51ae
NHE		 2451 case MSR_IA32_VMX_EXIT_CTLS:
2452 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2453 nested_vmx_exit_ctls_high);
2454 break;
2455 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2456 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2457 nested_vmx_entry_ctls_high);
2458 break;
b87a51ae
NHE		 2459 case MSR_IA32_VMX_ENTRY_CTLS:
2460 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2461 nested_vmx_entry_ctls_high);
2462 break;
2463 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2464 *pdata = vmx_control_msr(nested_vmx_misc_low,
2465 nested_vmx_misc_high);
b87a51ae
NHE		 2466 break;
2467 /*
2468 * These MSRs specify bits which the guest must keep fixed (on or off)
2469 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2470 * We picked the standard core2 setting.
2471 */
2472#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2473#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2474 case MSR_IA32_VMX_CR0_FIXED0:
2475 *pdata = VMXON_CR0_ALWAYSON;
2476 break;
2477 case MSR_IA32_VMX_CR0_FIXED1:
2478 *pdata = -1ULL;
2479 break;
2480 case MSR_IA32_VMX_CR4_FIXED0:
2481 *pdata = VMXON_CR4_ALWAYSON;
2482 break;
2483 case MSR_IA32_VMX_CR4_FIXED1:
2484 *pdata = -1ULL;
2485 break;
2486 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2487 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2488 break;
2489 case MSR_IA32_VMX_PROCBASED_CTLS2:
2490 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2491 nested_vmx_secondary_ctls_high);
2492 break;
2493 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2494 /* Currently, no nested vpid support */
2495 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2496 break;
2497 default:
b87a51ae 2498 return 1;
b3897a49
NHE		 2499 }
2500
b87a51ae
NHE		 2501 return 0;
2502}
2503
6aa8b732
AK		 2504/*
2505 * Reads an msr value (of 'msr_index') into 'pdata'.
2506 * Returns 0 on success, non-0 otherwise.
2507 * Assumes vcpu_load() was already called.
2508 */
2509static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2510{
2511 u64 data;
26bb0981 2512 struct shared_msr_entry *msr;
6aa8b732
AK		 2513
2514 if (!pdata) {
2515 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2516 return -EINVAL;
2517 }
2518
2519 switch (msr_index) {
05b3e0c2 2520#ifdef CONFIG_X86_64
6aa8b732
AK		 2521 case MSR_FS_BASE:
2522 data = vmcs_readl(GUEST_FS_BASE);
2523 break;
2524 case MSR_GS_BASE:
2525 data = vmcs_readl(GUEST_GS_BASE);
2526 break;
44ea2b17
AK		 2527 case MSR_KERNEL_GS_BASE:
2528 vmx_load_host_state(to_vmx(vcpu));
2529 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2530 break;
26bb0981 2531#endif
6aa8b732 2532 case MSR_EFER:
3bab1f5d 2533 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2534 case MSR_IA32_TSC:
6aa8b732
AK		 2535 data = guest_read_tsc();
2536 break;
2537 case MSR_IA32_SYSENTER_CS:
2538 data = vmcs_read32(GUEST_SYSENTER_CS);
2539 break;
2540 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2541 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2542 break;
2543 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2544 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2545 break;
0dd376e7 2546 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2547 if (!vmx_mpx_supported())
2548 return 1;
0dd376e7
LJ		 2549 data = vmcs_read64(GUEST_BNDCFGS);
2550 break;
cae50139
JK		 2551 case MSR_IA32_FEATURE_CONTROL:
2552 if (!nested_vmx_allowed(vcpu))
2553 return 1;
2554 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2555 break;
2556 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2557 if (!nested_vmx_allowed(vcpu))
2558 return 1;
2559 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2560 case MSR_TSC_AUX:
2561 if (!to_vmx(vcpu)->rdtscp_enabled)
2562 return 1;
2563 /* Otherwise falls through */
6aa8b732 2564 default:
8b9cf98c 2565 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2566 if (msr) {
2567 data = msr->data;
2568 break;
6aa8b732 2569 }
3bab1f5d 2570 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2571 }
2572
2573 *pdata = data;
2574 return 0;
2575}
2576
cae50139
JK		 2577static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2578
6aa8b732
AK		 2579/*
2580 * Writes msr value into into the appropriate "register".
2581 * Returns 0 on success, non-0 otherwise.
2582 * Assumes vcpu_load() was already called.
2583 */
8fe8ab46 2584static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2585{
a2fa3e9f 2586 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2587 struct shared_msr_entry *msr;
2cc51560 2588 int ret = 0;
8fe8ab46
WA		 2589 u32 msr_index = msr_info->index;
2590 u64 data = msr_info->data;
2cc51560 2591
6aa8b732 2592 switch (msr_index) {
3bab1f5d 2593 case MSR_EFER:
8fe8ab46 2594 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2595 break;
16175a79 2596#ifdef CONFIG_X86_64
6aa8b732 2597 case MSR_FS_BASE:
2fb92db1 2598 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2599 vmcs_writel(GUEST_FS_BASE, data);
2600 break;
2601 case MSR_GS_BASE:
2fb92db1 2602 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2603 vmcs_writel(GUEST_GS_BASE, data);
2604 break;
44ea2b17
AK		 2605 case MSR_KERNEL_GS_BASE:
2606 vmx_load_host_state(vmx);
2607 vmx->msr_guest_kernel_gs_base = data;
2608 break;
6aa8b732
AK		 2609#endif
2610 case MSR_IA32_SYSENTER_CS:
2611 vmcs_write32(GUEST_SYSENTER_CS, data);
2612 break;
2613 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2614 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2615 break;
2616 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2617 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2618 break;
0dd376e7 2619 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2620 if (!vmx_mpx_supported())
2621 return 1;
0dd376e7
LJ		 2622 vmcs_write64(GUEST_BNDCFGS, data);
2623 break;
af24a4e4 2624 case MSR_IA32_TSC:
8fe8ab46 2625 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2626 break;
468d472f
SY		 2627 case MSR_IA32_CR_PAT:
2628 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2629 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2630 return 1;
468d472f
SY		 2631 vmcs_write64(GUEST_IA32_PAT, data);
2632 vcpu->arch.pat = data;
2633 break;
2634 }
8fe8ab46 2635 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2636 break;
ba904635
WA		 2637 case MSR_IA32_TSC_ADJUST:
2638 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2639 break;
cae50139
JK		 2640 case MSR_IA32_FEATURE_CONTROL:
2641 if (!nested_vmx_allowed(vcpu) ||
2642 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2643 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2644 return 1;
2645 vmx->nested.msr_ia32_feature_control = data;
2646 if (msr_info->host_initiated && data == 0)
2647 vmx_leave_nested(vcpu);
2648 break;
2649 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2650 return 1; /* they are read-only */
4e47c7a6
SY		 2651 case MSR_TSC_AUX:
2652 if (!vmx->rdtscp_enabled)
2653 return 1;
2654 /* Check reserved bit, higher 32 bits should be zero */
2655 if ((data >> 32) != 0)
2656 return 1;
2657 /* Otherwise falls through */
6aa8b732 2658 default:
8b9cf98c 2659 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2660 if (msr) {
2661 msr->data = data;
2225fd56
AK		 2662 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2663 preempt_disable();
9ee73970
AK		 2664 kvm_set_shared_msr(msr->index, msr->data,
2665 msr->mask);
2225fd56
AK		 2666 preempt_enable();
2667 }
3bab1f5d 2668 break;
6aa8b732 2669 }
8fe8ab46 2670 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2671 }
2672
2cc51560 2673 return ret;
6aa8b732
AK		 2674}
2675
5fdbf976 2676static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2677{
5fdbf976
MT		 2678 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2679 switch (reg) {
2680 case VCPU_REGS_RSP:
2681 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2682 break;
2683 case VCPU_REGS_RIP:
2684 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2685 break;
6de4f3ad
AK		 2686 case VCPU_EXREG_PDPTR:
2687 if (enable_ept)
2688 ept_save_pdptrs(vcpu);
2689 break;
5fdbf976
MT		 2690 default:
2691 break;
2692 }
6aa8b732
AK		 2693}
2694
6aa8b732
AK		 2695static __init int cpu_has_kvm_support(void)
2696{
6210e37b 2697 return cpu_has_vmx();
6aa8b732
AK		 2698}
2699
2700static __init int vmx_disabled_by_bios(void)
2701{
2702 u64 msr;
2703
2704 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2705 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2706 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2707 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2708 && tboot_enabled())
2709 return 1;
23f3e991 2710 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2711 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2712 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2713 && !tboot_enabled()) {
2714 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2715 "activate TXT before enabling KVM\n");
cafd6659 2716 return 1;
f9335afe 2717 }
23f3e991
JC		 2718 /* launched w/o TXT and VMX disabled */
2719 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2720 && !tboot_enabled())
2721 return 1;
cafd6659
SW		 2722 }
2723
2724 return 0;
6aa8b732
AK		 2725}
2726
7725b894
DX		 2727static void kvm_cpu_vmxon(u64 addr)
2728{
2729 asm volatile (ASM_VMX_VMXON_RAX
2730 : : "a"(&addr), "m"(addr)
2731 : "memory", "cc");
2732}
2733
13a34e06 2734static int hardware_enable(void)
6aa8b732
AK		 2735{
2736 int cpu = raw_smp_processor_id();
2737 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2738 u64 old, test_bits;
6aa8b732 2739
10474ae8
AG		 2740 if (read_cr4() & X86_CR4_VMXE)
2741 return -EBUSY;
2742
d462b819 2743 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2744
2745 /*
2746 * Now we can enable the vmclear operation in kdump
2747 * since the loaded_vmcss_on_cpu list on this cpu
2748 * has been initialized.
2749 *
2750 * Though the cpu is not in VMX operation now, there
2751 * is no problem to enable the vmclear operation
2752 * for the loaded_vmcss_on_cpu list is empty!
2753 */
2754 crash_enable_local_vmclear(cpu);
2755
6aa8b732 2756 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2757
2758 test_bits = FEATURE_CONTROL_LOCKED;
2759 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2760 if (tboot_enabled())
2761 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2762
2763 if ((old & test_bits) != test_bits) {
6aa8b732 2764 /* enable and lock */
cafd6659
SW		 2765 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2766 }
66aee91a 2767 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2768
4610c9cc
DX		 2769 if (vmm_exclusive) {
2770 kvm_cpu_vmxon(phys_addr);
2771 ept_sync_global();
2772 }
10474ae8 2773
357d1226 2774 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2775
10474ae8 2776 return 0;
6aa8b732
AK		 2777}
2778
d462b819 2779static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2780{
2781 int cpu = raw_smp_processor_id();
d462b819 2782 struct loaded_vmcs *v, *n;
543e4243 2783
d462b819
NHE		 2784 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2785 loaded_vmcss_on_cpu_link)
2786 __loaded_vmcs_clear(v);
543e4243
AK		 2787}
2788
710ff4a8
EH		 2789
2790/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2791 * tricks.
2792 */
2793static void kvm_cpu_vmxoff(void)
6aa8b732 2794{
4ecac3fd 2795 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2796}
2797
13a34e06 2798static void hardware_disable(void)
710ff4a8 2799{
4610c9cc 2800 if (vmm_exclusive) {
d462b819 2801 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2802 kvm_cpu_vmxoff();
2803 }
7725b894 2804 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2805}
2806
1c3d14fe 2807static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2808 u32 msr, u32 *result)
1c3d14fe
YS		 2809{
2810 u32 vmx_msr_low, vmx_msr_high;
2811 u32 ctl = ctl_min | ctl_opt;
2812
2813 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2814
2815 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2816 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2817
2818 /* Ensure minimum (required) set of control bits are supported. */
2819 if (ctl_min & ~ctl)
002c7f7c 2820 return -EIO;
1c3d14fe
YS		 2821
2822 *result = ctl;
2823 return 0;
2824}
2825
110312c8
AK		 2826static __init bool allow_1_setting(u32 msr, u32 ctl)
2827{
2828 u32 vmx_msr_low, vmx_msr_high;
2829
2830 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2831 return vmx_msr_high & ctl;
2832}
2833
002c7f7c 2834static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2835{
2836 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2837 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2838 u32 _pin_based_exec_control = 0;
2839 u32 _cpu_based_exec_control = 0;
f78e0e2e 2840 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2841 u32 _vmexit_control = 0;
2842 u32 _vmentry_control = 0;
2843
10166744 2844 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2845#ifdef CONFIG_X86_64
2846 CPU_BASED_CR8_LOAD_EXITING |
2847 CPU_BASED_CR8_STORE_EXITING |
2848#endif
d56f546d
SY		 2849 CPU_BASED_CR3_LOAD_EXITING |
2850 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2851 CPU_BASED_USE_IO_BITMAPS |
2852 CPU_BASED_MOV_DR_EXITING |
a7052897 2853 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2854 CPU_BASED_MWAIT_EXITING |
2855 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2856 CPU_BASED_INVLPG_EXITING |
2857 CPU_BASED_RDPMC_EXITING;
443381a8 2858
f78e0e2e 2859 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2860 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2861 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2862 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2863 &_cpu_based_exec_control) < 0)
002c7f7c 2864 return -EIO;
6e5d865c
YS		 2865#ifdef CONFIG_X86_64
2866 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2867 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2868 ~CPU_BASED_CR8_STORE_EXITING;
2869#endif
f78e0e2e 2870 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2871 min2 = 0;
2872 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2873 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2874 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2875 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2876 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2877 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2878 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2879 SECONDARY_EXEC_RDTSCP |
83d4c286 2880 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2881 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2882 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2883 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2884 if (adjust_vmx_controls(min2, opt2,
2885 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2886 &_cpu_based_2nd_exec_control) < 0)
2887 return -EIO;
2888 }
2889#ifndef CONFIG_X86_64
2890 if (!(_cpu_based_2nd_exec_control &
2891 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2892 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2893#endif
83d4c286
YZ		 2894
2895 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2896 _cpu_based_2nd_exec_control &= ~(
8d14695f 2897 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2898 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2899 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2900
d56f546d 2901 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2902 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2903 enabled */
5fff7d27
GN		 2904 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2905 CPU_BASED_CR3_STORE_EXITING |
2906 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2907 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2908 vmx_capability.ept, vmx_capability.vpid);
2909 }
1c3d14fe 2910
81908bf4 2911 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2912#ifdef CONFIG_X86_64
2913 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2914#endif
a547c6db 2915 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2916 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2917 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2918 &_vmexit_control) < 0)
002c7f7c 2919 return -EIO;
1c3d14fe 2920
01e439be
YZ		 2921 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2922 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2923 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2924 &_pin_based_exec_control) < 0)
2925 return -EIO;
2926
2927 if (!(_cpu_based_2nd_exec_control &
2928 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2929 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2930 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2931
c845f9c6 2932 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2933 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2934 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2935 &_vmentry_control) < 0)
002c7f7c 2936 return -EIO;
6aa8b732 2937
c68876fd 2938 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2939
2940 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2941 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2942 return -EIO;
1c3d14fe
YS		 2943
2944#ifdef CONFIG_X86_64
2945 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2946 if (vmx_msr_high & (1u<<16))
002c7f7c 2947 return -EIO;
1c3d14fe
YS		 2948#endif
2949
2950 /* Require Write-Back (WB) memory type for VMCS accesses. */
2951 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2952 return -EIO;
1c3d14fe 2953
002c7f7c
YS		 2954 vmcs_conf->size = vmx_msr_high & 0x1fff;
2955 vmcs_conf->order = get_order(vmcs_config.size);
2956 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2957
002c7f7c
YS		 2958 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2959 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2960 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2961 vmcs_conf->vmexit_ctrl = _vmexit_control;
2962 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2963
110312c8
AK		 2964 cpu_has_load_ia32_efer =
2965 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2966 VM_ENTRY_LOAD_IA32_EFER)
2967 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2968 VM_EXIT_LOAD_IA32_EFER);
2969
8bf00a52
GN		 2970 cpu_has_load_perf_global_ctrl =
2971 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2972 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2973 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2974 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2975
2976 /*
2977 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2978 * but due to arrata below it can't be used. Workaround is to use
2979 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2980 *
2981 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2982 *
2983 * AAK155 (model 26)
2984 * AAP115 (model 30)
2985 * AAT100 (model 37)
2986 * BC86,AAY89,BD102 (model 44)
2987 * BA97 (model 46)
2988 *
2989 */
2990 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2991 switch (boot_cpu_data.x86_model) {
2992 case 26:
2993 case 30:
2994 case 37:
2995 case 44:
2996 case 46:
2997 cpu_has_load_perf_global_ctrl = false;
2998 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2999 "does not work properly. Using workaround\n");
3000 break;
3001 default:
3002 break;
3003 }
3004 }
3005
1c3d14fe 3006 return 0;
c68876fd 3007}
6aa8b732
AK		 3008
3009static struct vmcs *alloc_vmcs_cpu(int cpu)
3010{
3011 int node = cpu_to_node(cpu);
3012 struct page *pages;
3013 struct vmcs *vmcs;
3014
6484eb3e 3015 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3016 if (!pages)
3017 return NULL;
3018 vmcs = page_address(pages);
1c3d14fe
YS		 3019 memset(vmcs, 0, vmcs_config.size);
3020 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3021 return vmcs;
3022}
3023
3024static struct vmcs *alloc_vmcs(void)
3025{
d3b2c338 3026 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3027}
3028
3029static void free_vmcs(struct vmcs *vmcs)
3030{
1c3d14fe 3031 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3032}
3033
d462b819
NHE		 3034/*
3035 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3036 */
3037static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3038{
3039 if (!loaded_vmcs->vmcs)
3040 return;
3041 loaded_vmcs_clear(loaded_vmcs);
3042 free_vmcs(loaded_vmcs->vmcs);
3043 loaded_vmcs->vmcs = NULL;
3044}
3045
39959588 3046static void free_kvm_area(void)
6aa8b732
AK		 3047{
3048 int cpu;
3049
3230bb47 3050 for_each_possible_cpu(cpu) {
6aa8b732 3051 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3052 per_cpu(vmxarea, cpu) = NULL;
3053 }
6aa8b732
AK		 3054}
3055
fe2b201b
BD		 3056static void init_vmcs_shadow_fields(void)
3057{
3058 int i, j;
3059
3060 /* No checks for read only fields yet */
3061
3062 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3063 switch (shadow_read_write_fields[i]) {
3064 case GUEST_BNDCFGS:
3065 if (!vmx_mpx_supported())
3066 continue;
3067 break;
3068 default:
3069 break;
3070 }
3071
3072 if (j < i)
3073 shadow_read_write_fields[j] =
3074 shadow_read_write_fields[i];
3075 j++;
3076 }
3077 max_shadow_read_write_fields = j;
3078
3079 /* shadowed fields guest access without vmexit */
3080 for (i = 0; i < max_shadow_read_write_fields; i++) {
3081 clear_bit(shadow_read_write_fields[i],
3082 vmx_vmwrite_bitmap);
3083 clear_bit(shadow_read_write_fields[i],
3084 vmx_vmread_bitmap);
3085 }
3086 for (i = 0; i < max_shadow_read_only_fields; i++)
3087 clear_bit(shadow_read_only_fields[i],
3088 vmx_vmread_bitmap);
3089}
3090
6aa8b732
AK		 3091static __init int alloc_kvm_area(void)
3092{
3093 int cpu;
3094
3230bb47 3095 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3096 struct vmcs *vmcs;
3097
3098 vmcs = alloc_vmcs_cpu(cpu);
3099 if (!vmcs) {
3100 free_kvm_area();
3101 return -ENOMEM;
3102 }
3103
3104 per_cpu(vmxarea, cpu) = vmcs;
3105 }
3106 return 0;
3107}
3108
3109static __init int hardware_setup(void)
3110{
002c7f7c
YS		 3111 if (setup_vmcs_config(&vmcs_config) < 0)
3112 return -EIO;
50a37eb4
JR		 3113
3114 if (boot_cpu_has(X86_FEATURE_NX))
3115 kvm_enable_efer_bits(EFER_NX);
3116
93ba03c2
SY		 3117 if (!cpu_has_vmx_vpid())
3118 enable_vpid = 0;
abc4fc58
AG		 3119 if (!cpu_has_vmx_shadow_vmcs())
3120 enable_shadow_vmcs = 0;
fe2b201b
BD		 3121 if (enable_shadow_vmcs)
3122 init_vmcs_shadow_fields();
93ba03c2 3123
4bc9b982
SY		 3124 if (!cpu_has_vmx_ept() ||
3125 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3126 enable_ept = 0;
3a624e29 3127 enable_unrestricted_guest = 0;
83c3a331 3128 enable_ept_ad_bits = 0;
3a624e29
NK		 3129 }
3130
83c3a331
XH		 3131 if (!cpu_has_vmx_ept_ad_bits())
3132 enable_ept_ad_bits = 0;
3133
3a624e29
NK		 3134 if (!cpu_has_vmx_unrestricted_guest())
3135 enable_unrestricted_guest = 0;
93ba03c2 3136
38b99173 3137 if (!cpu_has_vmx_flexpriority()) {
93ba03c2
SY		 3138 flexpriority_enabled = 0;
3139
38b99173
TC		 3140 /*
3141 * set_apic_access_page_addr() is used to reload apic access
3142 * page upon invalidation. No need to do anything if the
3143 * processor does not have the APIC_ACCESS_ADDR VMCS field.
3144 */
3145 kvm_x86_ops->set_apic_access_page_addr = NULL;
3146 }
3147
95ba8273
GN		 3148 if (!cpu_has_vmx_tpr_shadow())
3149 kvm_x86_ops->update_cr8_intercept = NULL;
3150
54dee993
MT		 3151 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3152 kvm_disable_largepages();
3153
4b8d54f9
ZE		 3154 if (!cpu_has_vmx_ple())
3155 ple_gap = 0;
3156
01e439be
YZ		 3157 if (!cpu_has_vmx_apicv())
3158 enable_apicv = 0;
c7c9c56c 3159
01e439be 3160 if (enable_apicv)
c7c9c56c 3161 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3162 else {
c7c9c56c 3163 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3164 kvm_x86_ops->deliver_posted_interrupt = NULL;
3165 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3166 }
83d4c286 3167
b87a51ae
NHE		 3168 if (nested)
3169 nested_vmx_setup_ctls_msrs();
3170
6aa8b732
AK		 3171 return alloc_kvm_area();
3172}
3173
3174static __exit void hardware_unsetup(void)
3175{
3176 free_kvm_area();
3177}
3178
14168786
GN		 3179static bool emulation_required(struct kvm_vcpu *vcpu)
3180{
3181 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3182}
3183
91b0aa2c 3184static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3185 struct kvm_segment *save)
6aa8b732 3186{
d99e4152
GN		 3187 if (!emulate_invalid_guest_state) {
3188 /*
3189 * CS and SS RPL should be equal during guest entry according
3190 * to VMX spec, but in reality it is not always so. Since vcpu
3191 * is in the middle of the transition from real mode to
3192 * protected mode it is safe to assume that RPL 0 is a good
3193 * default value.
3194 */
3195 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3196 save->selector &= ~SELECTOR_RPL_MASK;
3197 save->dpl = save->selector & SELECTOR_RPL_MASK;
3198 save->s = 1;
6aa8b732 3199 }
d99e4152 3200 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3201}
3202
3203static void enter_pmode(struct kvm_vcpu *vcpu)
3204{
3205 unsigned long flags;
a89a8fb9 3206 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3207
d99e4152
GN		 3208 /*
3209 * Update real mode segment cache. It may be not up-to-date if sement
3210 * register was written while vcpu was in a guest mode.
3211 */
3212 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3213 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3214 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3215 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3216 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3217 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3218
7ffd92c5 3219 vmx->rmode.vm86_active = 0;
6aa8b732 3220
2fb92db1
AK		 3221 vmx_segment_cache_clear(vmx);
3222
f5f7b2fe 3223 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3224
3225 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3226 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3227 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3228 vmcs_writel(GUEST_RFLAGS, flags);
3229
66aee91a
RR		 3230 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3231 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3232
3233 update_exception_bitmap(vcpu);
3234
91b0aa2c
GN		 3235 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3236 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3237 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3238 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3239 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3240 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3241}
3242
f5f7b2fe 3243static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3244{
772e0318 3245 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3246 struct kvm_segment var = *save;
3247
3248 var.dpl = 0x3;
3249 if (seg == VCPU_SREG_CS)
3250 var.type = 0x3;
3251
3252 if (!emulate_invalid_guest_state) {
3253 var.selector = var.base >> 4;
3254 var.base = var.base & 0xffff0;
3255 var.limit = 0xffff;
3256 var.g = 0;
3257 var.db = 0;
3258 var.present = 1;
3259 var.s = 1;
3260 var.l = 0;
3261 var.unusable = 0;
3262 var.type = 0x3;
3263 var.avl = 0;
3264 if (save->base & 0xf)
3265 printk_once(KERN_WARNING "kvm: segment base is not "
3266 "paragraph aligned when entering "
3267 "protected mode (seg=%d)", seg);
3268 }
6aa8b732 3269
d99e4152
GN		 3270 vmcs_write16(sf->selector, var.selector);
3271 vmcs_write32(sf->base, var.base);
3272 vmcs_write32(sf->limit, var.limit);
3273 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3274}
3275
3276static void enter_rmode(struct kvm_vcpu *vcpu)
3277{
3278 unsigned long flags;
a89a8fb9 3279 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3280
f5f7b2fe
AK		 3281 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3287 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3288
7ffd92c5 3289 vmx->rmode.vm86_active = 1;
6aa8b732 3290
776e58ea
GN		 3291 /*
3292 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3293 * vcpu. Warn the user that an update is overdue.
776e58ea 3294 */
4918c6ca 3295 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3296 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3297 "called before entering vcpu\n");
776e58ea 3298
2fb92db1
AK		 3299 vmx_segment_cache_clear(vmx);
3300
4918c6ca 3301 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3302 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3303 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3304
3305 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3306 vmx->rmode.save_rflags = flags;
6aa8b732 3307
053de044 3308 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3309
3310 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3311 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3312 update_exception_bitmap(vcpu);
3313
d99e4152
GN		 3314 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3315 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3316 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3317 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3318 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3319 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3320
8668a3c4 3321 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3322}
3323
401d10de
AS		 3324static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3325{
3326 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3327 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3328
3329 if (!msr)
3330 return;
401d10de 3331
44ea2b17
AK		 3332 /*
3333 * Force kernel_gs_base reloading before EFER changes, as control
3334 * of this msr depends on is_long_mode().
3335 */
3336 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3337 vcpu->arch.efer = efer;
401d10de 3338 if (efer & EFER_LMA) {
2961e876 3339 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3340 msr->data = efer;
3341 } else {
2961e876 3342 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3343
3344 msr->data = efer & ~EFER_LME;
3345 }
3346 setup_msrs(vmx);
3347}
3348
05b3e0c2 3349#ifdef CONFIG_X86_64
6aa8b732
AK		 3350
3351static void enter_lmode(struct kvm_vcpu *vcpu)
3352{
3353 u32 guest_tr_ar;
3354
2fb92db1
AK		 3355 vmx_segment_cache_clear(to_vmx(vcpu));
3356
6aa8b732
AK		 3357 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3358 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3359 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3360 __func__);
6aa8b732
AK		 3361 vmcs_write32(GUEST_TR_AR_BYTES,
3362 (guest_tr_ar & ~AR_TYPE_MASK)
3363 | AR_TYPE_BUSY_64_TSS);
3364 }
da38f438 3365 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3366}
3367
3368static void exit_lmode(struct kvm_vcpu *vcpu)
3369{
2961e876 3370 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3371 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3372}
3373
3374#endif
3375
2384d2b3
SY		 3376static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3377{
b9d762fa 3378 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3379 if (enable_ept) {
3380 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3381 return;
4e1096d2 3382 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3383 }
2384d2b3
SY		 3384}
3385
e8467fda
AK		 3386static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3387{
3388 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3389
3390 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3391 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3392}
3393
aff48baa
AK		 3394static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3395{
3396 if (enable_ept && is_paging(vcpu))
3397 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3398 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3399}
3400
25c4c276 3401static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3402{
fc78f519
AK		 3403 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3404
3405 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3406 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3407}
3408
1439442c
SY		 3409static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3410{
d0d538b9
GN		 3411 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3412
6de4f3ad
AK		 3413 if (!test_bit(VCPU_EXREG_PDPTR,
3414 (unsigned long *)&vcpu->arch.regs_dirty))
3415 return;
3416
1439442c 3417 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3418 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3419 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3420 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3421 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3422 }
3423}
3424
8f5d549f
AK		 3425static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3426{
d0d538b9
GN		 3427 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3428
8f5d549f 3429 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3430 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3431 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3432 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3433 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3434 }
6de4f3ad
AK		 3435
3436 __set_bit(VCPU_EXREG_PDPTR,
3437 (unsigned long *)&vcpu->arch.regs_avail);
3438 __set_bit(VCPU_EXREG_PDPTR,
3439 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3440}
3441
5e1746d6 3442static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3443
3444static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3445 unsigned long cr0,
3446 struct kvm_vcpu *vcpu)
3447{
5233dd51
MT		 3448 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3449 vmx_decache_cr3(vcpu);
1439442c
SY		 3450 if (!(cr0 & X86_CR0_PG)) {
3451 /* From paging/starting to nonpaging */
3452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3453 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3454 (CPU_BASED_CR3_LOAD_EXITING |
3455 CPU_BASED_CR3_STORE_EXITING));
3456 vcpu->arch.cr0 = cr0;
fc78f519 3457 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3458 } else if (!is_paging(vcpu)) {
3459 /* From nonpaging to paging */
3460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3461 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3462 ~(CPU_BASED_CR3_LOAD_EXITING |
3463 CPU_BASED_CR3_STORE_EXITING));
3464 vcpu->arch.cr0 = cr0;
fc78f519 3465 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3466 }
95eb84a7
SY		 3467
3468 if (!(cr0 & X86_CR0_WP))
3469 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3470}
3471
6aa8b732
AK		 3472static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3473{
7ffd92c5 3474 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3475 unsigned long hw_cr0;
3476
5037878e 3477 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3478 if (enable_unrestricted_guest)
5037878e 3479 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3480 else {
5037878e 3481 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3482
218e763f
GN		 3483 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3484 enter_pmode(vcpu);
6aa8b732 3485
218e763f
GN		 3486 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3487 enter_rmode(vcpu);
3488 }
6aa8b732 3489
05b3e0c2 3490#ifdef CONFIG_X86_64
f6801dff 3491 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3492 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3493 enter_lmode(vcpu);
707d92fa 3494 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3495 exit_lmode(vcpu);
3496 }
3497#endif
3498
089d034e 3499 if (enable_ept)
1439442c
SY		 3500 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3501
02daab21 3502 if (!vcpu->fpu_active)
81231c69 3503 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3504
6aa8b732 3505 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3506 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3507 vcpu->arch.cr0 = cr0;
14168786
GN		 3508
3509 /* depends on vcpu->arch.cr0 to be set to a new value */
3510 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3511}
3512
1439442c
SY		 3513static u64 construct_eptp(unsigned long root_hpa)
3514{
3515 u64 eptp;
3516
3517 /* TODO write the value reading from MSR */
3518 eptp = VMX_EPT_DEFAULT_MT |
3519 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3520 if (enable_ept_ad_bits)
3521 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3522 eptp |= (root_hpa & PAGE_MASK);
3523
3524 return eptp;
3525}
3526
6aa8b732
AK		 3527static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3528{
1439442c
SY		 3529 unsigned long guest_cr3;
3530 u64 eptp;
3531
3532 guest_cr3 = cr3;
089d034e 3533 if (enable_ept) {
1439442c
SY		 3534 eptp = construct_eptp(cr3);
3535 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3536 if (is_paging(vcpu) || is_guest_mode(vcpu))
3537 guest_cr3 = kvm_read_cr3(vcpu);
3538 else
3539 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3540 ept_load_pdptrs(vcpu);
1439442c
SY		 3541 }
3542
2384d2b3 3543 vmx_flush_tlb(vcpu);
1439442c 3544 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3545}
3546
5e1746d6 3547static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3548{
7ffd92c5 3549 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3550 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3551
5e1746d6
NHE		 3552 if (cr4 & X86_CR4_VMXE) {
3553 /*
3554 * To use VMXON (and later other VMX instructions), a guest
3555 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3556 * So basically the check on whether to allow nested VMX
3557 * is here.
3558 */
3559 if (!nested_vmx_allowed(vcpu))
3560 return 1;
1a0d74e6
JK		 3561 }
3562 if (to_vmx(vcpu)->nested.vmxon &&
3563 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3564 return 1;
3565
ad312c7c 3566 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3567 if (enable_ept) {
3568 if (!is_paging(vcpu)) {
3569 hw_cr4 &= ~X86_CR4_PAE;
3570 hw_cr4 |= X86_CR4_PSE;
c08800a5 3571 /*
e1e746b3
FW		 3572 * SMEP/SMAP is disabled if CPU is in non-paging mode
3573 * in hardware. However KVM always uses paging mode to
c08800a5 3574 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3575 * To emulate this behavior, SMEP/SMAP needs to be
3576 * manually disabled when guest switches to non-paging
3577 * mode.
c08800a5 3578 */
e1e746b3 3579 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3580 } else if (!(cr4 & X86_CR4_PAE)) {
3581 hw_cr4 &= ~X86_CR4_PAE;
3582 }
3583 }
1439442c
SY		 3584
3585 vmcs_writel(CR4_READ_SHADOW, cr4);
3586 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3587 return 0;
6aa8b732
AK		 3588}
3589
6aa8b732
AK		 3590static void vmx_get_segment(struct kvm_vcpu *vcpu,
3591 struct kvm_segment *var, int seg)
3592{
a9179499 3593 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3594 u32 ar;
3595
c6ad1153 3596 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3597 *var = vmx->rmode.segs[seg];
a9179499 3598 if (seg == VCPU_SREG_TR
2fb92db1 3599 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3600 return;
1390a28b
AK		 3601 var->base = vmx_read_guest_seg_base(vmx, seg);
3602 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3603 return;
a9179499 3604 }
2fb92db1
AK		 3605 var->base = vmx_read_guest_seg_base(vmx, seg);
3606 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3607 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3608 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3609 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3610 var->type = ar & 15;
3611 var->s = (ar >> 4) & 1;
3612 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3613 /*
3614 * Some userspaces do not preserve unusable property. Since usable
3615 * segment has to be present according to VMX spec we can use present
3616 * property to amend userspace bug by making unusable segment always
3617 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3618 * segment as unusable.
3619 */
3620 var->present = !var->unusable;
6aa8b732
AK		 3621 var->avl = (ar >> 12) & 1;
3622 var->l = (ar >> 13) & 1;
3623 var->db = (ar >> 14) & 1;
3624 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3625}
3626
a9179499
AK		 3627static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3628{
a9179499
AK		 3629 struct kvm_segment s;
3630
3631 if (to_vmx(vcpu)->rmode.vm86_active) {
3632 vmx_get_segment(vcpu, &s, seg);
3633 return s.base;
3634 }
2fb92db1 3635 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3636}
3637
b09408d0 3638static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3639{
b09408d0
MT		 3640 struct vcpu_vmx *vmx = to_vmx(vcpu);
3641
ae9fedc7 3642 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3643 return 0;
ae9fedc7
PB		 3644 else {
3645 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3646 return AR_DPL(ar);
69c73028 3647 }
69c73028
AK		 3648}
3649
653e3108 3650static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3651{
6aa8b732
AK		 3652 u32 ar;
3653
f0495f9b 3654 if (var->unusable || !var->present)
6aa8b732
AK		 3655 ar = 1 << 16;
3656 else {
3657 ar = var->type & 15;
3658 ar |= (var->s & 1) << 4;
3659 ar |= (var->dpl & 3) << 5;
3660 ar |= (var->present & 1) << 7;
3661 ar |= (var->avl & 1) << 12;
3662 ar |= (var->l & 1) << 13;
3663 ar |= (var->db & 1) << 14;
3664 ar |= (var->g & 1) << 15;
3665 }
653e3108
AK		 3666
3667 return ar;
3668}
3669
3670static void vmx_set_segment(struct kvm_vcpu *vcpu,
3671 struct kvm_segment *var, int seg)
3672{
7ffd92c5 3673 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3674 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3675
2fb92db1
AK		 3676 vmx_segment_cache_clear(vmx);
3677
1ecd50a9
GN		 3678 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3679 vmx->rmode.segs[seg] = *var;
3680 if (seg == VCPU_SREG_TR)
3681 vmcs_write16(sf->selector, var->selector);
3682 else if (var->s)
3683 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3684 goto out;
653e3108 3685 }
1ecd50a9 3686
653e3108
AK		 3687 vmcs_writel(sf->base, var->base);
3688 vmcs_write32(sf->limit, var->limit);
3689 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3690
3691 /*
3692 * Fix the "Accessed" bit in AR field of segment registers for older
3693 * qemu binaries.
3694 * IA32 arch specifies that at the time of processor reset the
3695 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3696 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3697 * state vmexit when "unrestricted guest" mode is turned on.
3698 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3699 * tree. Newer qemu binaries with that qemu fix would not need this
3700 * kvm hack.
3701 */
3702 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3703 var->type |= 0x1; /* Accessed */
3a624e29 3704
f924d66d 3705 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3706
3707out:
98eb2f8b 3708 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3709}
3710
6aa8b732
AK		 3711static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3712{
2fb92db1 3713 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3714
3715 *db = (ar >> 14) & 1;
3716 *l = (ar >> 13) & 1;
3717}
3718
89a27f4d 3719static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3720{
89a27f4d
GN		 3721 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3722 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3723}
3724
89a27f4d 3725static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3726{
89a27f4d
GN		 3727 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3728 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3729}
3730
89a27f4d 3731static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3732{
89a27f4d
GN		 3733 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3734 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3735}
3736
89a27f4d 3737static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3738{
89a27f4d
GN		 3739 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3740 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3741}
3742
648dfaa7
MG		 3743static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3744{
3745 struct kvm_segment var;
3746 u32 ar;
3747
3748 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3749 var.dpl = 0x3;
0647f4aa
GN		 3750 if (seg == VCPU_SREG_CS)
3751 var.type = 0x3;
648dfaa7
MG		 3752 ar = vmx_segment_access_rights(&var);
3753
3754 if (var.base != (var.selector << 4))
3755 return false;
89efbed0 3756 if (var.limit != 0xffff)
648dfaa7 3757 return false;
07f42f5f 3758 if (ar != 0xf3)
648dfaa7
MG		 3759 return false;
3760
3761 return true;
3762}
3763
3764static bool code_segment_valid(struct kvm_vcpu *vcpu)
3765{
3766 struct kvm_segment cs;
3767 unsigned int cs_rpl;
3768
3769 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3770 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3771
1872a3f4
AK		 3772 if (cs.unusable)
3773 return false;
648dfaa7
MG		 3774 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3775 return false;
3776 if (!cs.s)
3777 return false;
1872a3f4 3778 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3779 if (cs.dpl > cs_rpl)
3780 return false;
1872a3f4 3781 } else {
648dfaa7
MG		 3782 if (cs.dpl != cs_rpl)
3783 return false;
3784 }
3785 if (!cs.present)
3786 return false;
3787
3788 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3789 return true;
3790}
3791
3792static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3793{
3794 struct kvm_segment ss;
3795 unsigned int ss_rpl;
3796
3797 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3798 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3799
1872a3f4
AK		 3800 if (ss.unusable)
3801 return true;
3802 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3803 return false;
3804 if (!ss.s)
3805 return false;
3806 if (ss.dpl != ss_rpl) /* DPL != RPL */
3807 return false;
3808 if (!ss.present)
3809 return false;
3810
3811 return true;
3812}
3813
3814static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3815{
3816 struct kvm_segment var;
3817 unsigned int rpl;
3818
3819 vmx_get_segment(vcpu, &var, seg);
3820 rpl = var.selector & SELECTOR_RPL_MASK;
3821
1872a3f4
AK		 3822 if (var.unusable)
3823 return true;
648dfaa7
MG		 3824 if (!var.s)
3825 return false;
3826 if (!var.present)
3827 return false;
3828 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3829 if (var.dpl < rpl) /* DPL < RPL */
3830 return false;
3831 }
3832
3833 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3834 * rights flags
3835 */
3836 return true;
3837}
3838
3839static bool tr_valid(struct kvm_vcpu *vcpu)
3840{
3841 struct kvm_segment tr;
3842
3843 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3844
1872a3f4
AK		 3845 if (tr.unusable)
3846 return false;
648dfaa7
MG		 3847 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3848 return false;
1872a3f4 3849 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3850 return false;
3851 if (!tr.present)
3852 return false;
3853
3854 return true;
3855}
3856
3857static bool ldtr_valid(struct kvm_vcpu *vcpu)
3858{
3859 struct kvm_segment ldtr;
3860
3861 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3862
1872a3f4
AK		 3863 if (ldtr.unusable)
3864 return true;
648dfaa7
MG		 3865 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3866 return false;
3867 if (ldtr.type != 2)
3868 return false;
3869 if (!ldtr.present)
3870 return false;
3871
3872 return true;
3873}
3874
3875static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3876{
3877 struct kvm_segment cs, ss;
3878
3879 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3880 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3881
3882 return ((cs.selector & SELECTOR_RPL_MASK) ==
3883 (ss.selector & SELECTOR_RPL_MASK));
3884}
3885
3886/*
3887 * Check if guest state is valid. Returns true if valid, false if
3888 * not.
3889 * We assume that registers are always usable
3890 */
3891static bool guest_state_valid(struct kvm_vcpu *vcpu)
3892{
c5e97c80
GN		 3893 if (enable_unrestricted_guest)
3894 return true;
3895
648dfaa7 3896 /* real mode guest state checks */
f13882d8 3897 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3898 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3899 return false;
3900 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3901 return false;
3902 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3903 return false;
3904 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3905 return false;
3906 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3907 return false;
3908 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3909 return false;
3910 } else {
3911 /* protected mode guest state checks */
3912 if (!cs_ss_rpl_check(vcpu))
3913 return false;
3914 if (!code_segment_valid(vcpu))
3915 return false;
3916 if (!stack_segment_valid(vcpu))
3917 return false;
3918 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3919 return false;
3920 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3921 return false;
3922 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3923 return false;
3924 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3925 return false;
3926 if (!tr_valid(vcpu))
3927 return false;
3928 if (!ldtr_valid(vcpu))
3929 return false;
3930 }
3931 /* TODO:
3932 * - Add checks on RIP
3933 * - Add checks on RFLAGS
3934 */
3935
3936 return true;
3937}
3938
d77c26fc 3939static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3940{
40dcaa9f 3941 gfn_t fn;
195aefde 3942 u16 data = 0;
1f755a82 3943 int idx, r;
6aa8b732 3944
40dcaa9f 3945 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3946 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3947 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3948 if (r < 0)
10589a46 3949 goto out;
195aefde 3950 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3951 r = kvm_write_guest_page(kvm, fn++, &data,
3952 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3953 if (r < 0)
10589a46 3954 goto out;
195aefde
IE		 3955 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3956 if (r < 0)
10589a46 3957 goto out;
195aefde
IE		 3958 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3959 if (r < 0)
10589a46 3960 goto out;
195aefde 3961 data = ~0;
10589a46
MT		 3962 r = kvm_write_guest_page(kvm, fn, &data,
3963 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3964 sizeof(u8));
10589a46 3965out:
40dcaa9f 3966 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3967 return r;
6aa8b732
AK		 3968}
3969
b7ebfb05
SY		 3970static int init_rmode_identity_map(struct kvm *kvm)
3971{
f51770ed 3972 int i, idx, r = 0;
b7ebfb05
SY		 3973 pfn_t identity_map_pfn;
3974 u32 tmp;
3975
089d034e 3976 if (!enable_ept)
f51770ed 3977 return 0;
a255d479
TC		 3978
3979 /* Protect kvm->arch.ept_identity_pagetable_done. */
3980 mutex_lock(&kvm->slots_lock);
3981
f51770ed 3982 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3983 goto out2;
a255d479 3984
b927a3ce 3985 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3986
3987 r = alloc_identity_pagetable(kvm);
f51770ed 3988 if (r < 0)
a255d479
TC		 3989 goto out2;
3990
40dcaa9f 3991 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3992 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3993 if (r < 0)
3994 goto out;
3995 /* Set up identity-mapping pagetable for EPT in real mode */
3996 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3997 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3998 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3999 r = kvm_write_guest_page(kvm, identity_map_pfn,
4000 &tmp, i * sizeof(tmp), sizeof(tmp));
4001 if (r < 0)
4002 goto out;
4003 }
4004 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4005
b7ebfb05 4006out:
40dcaa9f 4007 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4008
4009out2:
4010 mutex_unlock(&kvm->slots_lock);
f51770ed 4011 return r;
b7ebfb05
SY		 4012}
4013
6aa8b732
AK		 4014static void seg_setup(int seg)
4015{
772e0318 4016 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4017 unsigned int ar;
6aa8b732
AK		 4018
4019 vmcs_write16(sf->selector, 0);
4020 vmcs_writel(sf->base, 0);
4021 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4022 ar = 0x93;
4023 if (seg == VCPU_SREG_CS)
4024 ar |= 0x08; /* code segment */
3a624e29
NK		 4025
4026 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4027}
4028
f78e0e2e
SY		 4029static int alloc_apic_access_page(struct kvm *kvm)
4030{
4484141a 4031 struct page *page;
f78e0e2e
SY		 4032 struct kvm_userspace_memory_region kvm_userspace_mem;
4033 int r = 0;
4034
79fac95e 4035 mutex_lock(&kvm->slots_lock);
bfc6d222 4036 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4037 goto out;
4038 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4039 kvm_userspace_mem.flags = 0;
73a6d941 4040 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4041 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4042 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4043 if (r)
4044 goto out;
72dc67a6 4045
73a6d941 4046 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4047 if (is_error_page(page)) {
4048 r = -EFAULT;
4049 goto out;
4050 }
4051
4052 kvm->arch.apic_access_page = page;
f78e0e2e 4053out:
79fac95e 4054 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4055 return r;
4056}
4057
b7ebfb05
SY		 4058static int alloc_identity_pagetable(struct kvm *kvm)
4059{
a255d479
TC		 4060 /* Called with kvm->slots_lock held. */
4061
b7ebfb05
SY		 4062 struct kvm_userspace_memory_region kvm_userspace_mem;
4063 int r = 0;
4064
a255d479
TC		 4065 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4066
b7ebfb05
SY		 4067 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4068 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4069 kvm_userspace_mem.guest_phys_addr =
4070 kvm->arch.ept_identity_map_addr;
b7ebfb05 4071 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4072 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4073
b7ebfb05
SY		 4074 return r;
4075}
4076
2384d2b3
SY		 4077static void allocate_vpid(struct vcpu_vmx *vmx)
4078{
4079 int vpid;
4080
4081 vmx->vpid = 0;
919818ab 4082 if (!enable_vpid)
2384d2b3
SY		 4083 return;
4084 spin_lock(&vmx_vpid_lock);
4085 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4086 if (vpid < VMX_NR_VPIDS) {
4087 vmx->vpid = vpid;
4088 __set_bit(vpid, vmx_vpid_bitmap);
4089 }
4090 spin_unlock(&vmx_vpid_lock);
4091}
4092
cdbecfc3
LJ		 4093static void free_vpid(struct vcpu_vmx *vmx)
4094{
4095 if (!enable_vpid)
4096 return;
4097 spin_lock(&vmx_vpid_lock);
4098 if (vmx->vpid != 0)
4099 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4100 spin_unlock(&vmx_vpid_lock);
4101}
4102
8d14695f
YZ		 4103#define MSR_TYPE_R 1
4104#define MSR_TYPE_W 2
4105static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4106 u32 msr, int type)
25c5f225 4107{
3e7c73e9 4108 int f = sizeof(unsigned long);
25c5f225
SY		 4109
4110 if (!cpu_has_vmx_msr_bitmap())
4111 return;
4112
4113 /*
4114 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4115 * have the write-low and read-high bitmap offsets the wrong way round.
4116 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4117 */
25c5f225 4118 if (msr <= 0x1fff) {
8d14695f
YZ		 4119 if (type & MSR_TYPE_R)
4120 /* read-low */
4121 __clear_bit(msr, msr_bitmap + 0x000 / f);
4122
4123 if (type & MSR_TYPE_W)
4124 /* write-low */
4125 __clear_bit(msr, msr_bitmap + 0x800 / f);
4126
25c5f225
SY		 4127 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4128 msr &= 0x1fff;
8d14695f
YZ		 4129 if (type & MSR_TYPE_R)
4130 /* read-high */
4131 __clear_bit(msr, msr_bitmap + 0x400 / f);
4132
4133 if (type & MSR_TYPE_W)
4134 /* write-high */
4135 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4136
4137 }
4138}
4139
4140static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4141 u32 msr, int type)
4142{
4143 int f = sizeof(unsigned long);
4144
4145 if (!cpu_has_vmx_msr_bitmap())
4146 return;
4147
4148 /*
4149 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4150 * have the write-low and read-high bitmap offsets the wrong way round.
4151 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4152 */
4153 if (msr <= 0x1fff) {
4154 if (type & MSR_TYPE_R)
4155 /* read-low */
4156 __set_bit(msr, msr_bitmap + 0x000 / f);
4157
4158 if (type & MSR_TYPE_W)
4159 /* write-low */
4160 __set_bit(msr, msr_bitmap + 0x800 / f);
4161
4162 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4163 msr &= 0x1fff;
4164 if (type & MSR_TYPE_R)
4165 /* read-high */
4166 __set_bit(msr, msr_bitmap + 0x400 / f);
4167
4168 if (type & MSR_TYPE_W)
4169 /* write-high */
4170 __set_bit(msr, msr_bitmap + 0xc00 / f);
4171
25c5f225 4172 }
25c5f225
SY		 4173}
4174
5897297b
AK		 4175static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4176{
4177 if (!longmode_only)
8d14695f
YZ		 4178 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4179 msr, MSR_TYPE_R | MSR_TYPE_W);
4180 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4181 msr, MSR_TYPE_R | MSR_TYPE_W);
4182}
4183
4184static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4185{
4186 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4187 msr, MSR_TYPE_R);
4188 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4189 msr, MSR_TYPE_R);
4190}
4191
4192static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4193{
4194 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4195 msr, MSR_TYPE_R);
4196 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4197 msr, MSR_TYPE_R);
4198}
4199
4200static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4201{
4202 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4203 msr, MSR_TYPE_W);
4204 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4205 msr, MSR_TYPE_W);
5897297b
AK		 4206}
4207
01e439be
YZ		 4208static int vmx_vm_has_apicv(struct kvm *kvm)
4209{
4210 return enable_apicv && irqchip_in_kernel(kvm);
4211}
4212
a20ed54d
YZ		 4213/*
4214 * Send interrupt to vcpu via posted interrupt way.
4215 * 1. If target vcpu is running(non-root mode), send posted interrupt
4216 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4217 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4218 * interrupt from PIR in next vmentry.
4219 */
4220static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4221{
4222 struct vcpu_vmx *vmx = to_vmx(vcpu);
4223 int r;
4224
4225 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4226 return;
4227
4228 r = pi_test_and_set_on(&vmx->pi_desc);
4229 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4230#ifdef CONFIG_SMP
a20ed54d
YZ		 4231 if (!r && (vcpu->mode == IN_GUEST_MODE))
4232 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4233 POSTED_INTR_VECTOR);
4234 else
6ffbbbba 4235#endif
a20ed54d
YZ		 4236 kvm_vcpu_kick(vcpu);
4237}
4238
4239static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4240{
4241 struct vcpu_vmx *vmx = to_vmx(vcpu);
4242
4243 if (!pi_test_and_clear_on(&vmx->pi_desc))
4244 return;
4245
4246 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4247}
4248
4249static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4250{
4251 return;
4252}
4253
a3a8ff8e
NHE		 4254/*
4255 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4256 * will not change in the lifetime of the guest.
4257 * Note that host-state that does change is set elsewhere. E.g., host-state
4258 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4259 */
a547c6db 4260static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4261{
4262 u32 low32, high32;
4263 unsigned long tmpl;
4264 struct desc_ptr dt;
4265
b1a74bf8 4266 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4267 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4268 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4269
4270 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4271#ifdef CONFIG_X86_64
4272 /*
4273 * Load null selectors, so we can avoid reloading them in
4274 * __vmx_load_host_state(), in case userspace uses the null selectors
4275 * too (the expected case).
4276 */
4277 vmcs_write16(HOST_DS_SELECTOR, 0);
4278 vmcs_write16(HOST_ES_SELECTOR, 0);
4279#else
a3a8ff8e
NHE		 4280 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4281 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4282#endif
a3a8ff8e
NHE		 4283 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4284 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4285
4286 native_store_idt(&dt);
4287 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4288 vmx->host_idt_base = dt.address;
a3a8ff8e 4289
83287ea4 4290 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4291
4292 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4293 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4294 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4295 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4296
4297 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4298 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4299 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4300 }
4301}
4302
bf8179a0
NHE		 4303static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4304{
4305 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4306 if (enable_ept)
4307 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4308 if (is_guest_mode(&vmx->vcpu))
4309 vmx->vcpu.arch.cr4_guest_owned_bits &=
4310 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4311 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4312}
4313
01e439be
YZ		 4314static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4315{
4316 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4317
4318 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4319 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4320 return pin_based_exec_ctrl;
4321}
4322
bf8179a0
NHE		 4323static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4324{
4325 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4326
4327 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4328 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4329
bf8179a0
NHE		 4330 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4331 exec_control &= ~CPU_BASED_TPR_SHADOW;
4332#ifdef CONFIG_X86_64
4333 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4334 CPU_BASED_CR8_LOAD_EXITING;
4335#endif
4336 }
4337 if (!enable_ept)
4338 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4339 CPU_BASED_CR3_LOAD_EXITING |
4340 CPU_BASED_INVLPG_EXITING;
4341 return exec_control;
4342}
4343
4344static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4345{
4346 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4347 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4348 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4349 if (vmx->vpid == 0)
4350 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4351 if (!enable_ept) {
4352 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4353 enable_unrestricted_guest = 0;
ad756a16
MJ		 4354 /* Enable INVPCID for non-ept guests may cause performance regression. */
4355 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4356 }
4357 if (!enable_unrestricted_guest)
4358 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4359 if (!ple_gap)
4360 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4361 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4362 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4363 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4364 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4365 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4366 (handle_vmptrld).
4367 We can NOT enable shadow_vmcs here because we don't have yet
4368 a current VMCS12
4369 */
4370 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4371 return exec_control;
4372}
4373
ce88decf
XG		 4374static void ept_set_mmio_spte_mask(void)
4375{
4376 /*
4377 * EPT Misconfigurations can be generated if the value of bits 2:0
4378 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4379 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4380 * spte.
4381 */
885032b9 4382 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4383}
4384
6aa8b732
AK		 4385/*
4386 * Sets up the vmcs for emulated real mode.
4387 */
8b9cf98c 4388static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4389{
2e4ce7f5 4390#ifdef CONFIG_X86_64
6aa8b732 4391 unsigned long a;
2e4ce7f5 4392#endif
6aa8b732 4393 int i;
6aa8b732 4394
6aa8b732 4395 /* I/O */
3e7c73e9
AK		 4396 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4397 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4398
4607c2d7
AG		 4399 if (enable_shadow_vmcs) {
4400 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4401 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4402 }
25c5f225 4403 if (cpu_has_vmx_msr_bitmap())
5897297b 4404 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4405
6aa8b732
AK		 4406 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4407
6aa8b732 4408 /* Control */
01e439be 4409 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4410
bf8179a0 4411 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4412
83ff3b9d 4413 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4414 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4415 vmx_secondary_exec_control(vmx));
83ff3b9d 4416 }
f78e0e2e 4417
01e439be 4418 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4419 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4420 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4421 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4422 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4423
4424 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4425
4426 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4427 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4428 }
4429
4b8d54f9
ZE		 4430 if (ple_gap) {
4431 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4432 vmx->ple_window = ple_window;
4433 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4434 }
4435
c3707958
XG		 4436 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4437 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4438 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4439
9581d442
AK		 4440 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4441 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4442 vmx_set_constant_host_state(vmx);
05b3e0c2 4443#ifdef CONFIG_X86_64
6aa8b732
AK		 4444 rdmsrl(MSR_FS_BASE, a);
4445 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4446 rdmsrl(MSR_GS_BASE, a);
4447 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4448#else
4449 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4450 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4451#endif
4452
2cc51560
ED		 4453 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4454 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4455 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4456 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4457 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4458
468d472f 4459 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4460 u32 msr_low, msr_high;
4461 u64 host_pat;
468d472f
SY		 4462 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4463 host_pat = msr_low | ((u64) msr_high << 32);
4464 /* Write the default value follow host pat */
4465 vmcs_write64(GUEST_IA32_PAT, host_pat);
4466 /* Keep arch.pat sync with GUEST_IA32_PAT */
4467 vmx->vcpu.arch.pat = host_pat;
4468 }
4469
03916db9 4470 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4471 u32 index = vmx_msr_index[i];
4472 u32 data_low, data_high;
a2fa3e9f 4473 int j = vmx->nmsrs;
6aa8b732
AK		 4474
4475 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4476 continue;
432bd6cb
AK		 4477 if (wrmsr_safe(index, data_low, data_high) < 0)
4478 continue;
26bb0981
AK		 4479 vmx->guest_msrs[j].index = i;
4480 vmx->guest_msrs[j].data = 0;
d5696725 4481 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4482 ++vmx->nmsrs;
6aa8b732 4483 }
6aa8b732 4484
2961e876
GN		 4485
4486 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4487
4488 /* 22.2.1, 20.8.1 */
2961e876 4489 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4490
e00c8cf2 4491 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4492 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4493
4494 return 0;
4495}
4496
57f252f2 4497static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4498{
4499 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4500 struct msr_data apic_base_msr;
e00c8cf2 4501
7ffd92c5 4502 vmx->rmode.vm86_active = 0;
e00c8cf2 4503
3b86cd99
JK		 4504 vmx->soft_vnmi_blocked = 0;
4505
ad312c7c 4506 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4507 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4508 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4509 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4510 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4511 apic_base_msr.host_initiated = true;
4512 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4513
2fb92db1
AK		 4514 vmx_segment_cache_clear(vmx);
4515
5706be0d 4516 seg_setup(VCPU_SREG_CS);
66450a21 4517 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4518 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4519
4520 seg_setup(VCPU_SREG_DS);
4521 seg_setup(VCPU_SREG_ES);
4522 seg_setup(VCPU_SREG_FS);
4523 seg_setup(VCPU_SREG_GS);
4524 seg_setup(VCPU_SREG_SS);
4525
4526 vmcs_write16(GUEST_TR_SELECTOR, 0);
4527 vmcs_writel(GUEST_TR_BASE, 0);
4528 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4529 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4530
4531 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4532 vmcs_writel(GUEST_LDTR_BASE, 0);
4533 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4534 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4535
4536 vmcs_write32(GUEST_SYSENTER_CS, 0);
4537 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4538 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4539
4540 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4541 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4542
e00c8cf2
AK		 4543 vmcs_writel(GUEST_GDTR_BASE, 0);
4544 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4545
4546 vmcs_writel(GUEST_IDTR_BASE, 0);
4547 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4548
443381a8 4549 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4550 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4551 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4552
e00c8cf2
AK		 4553 /* Special registers */
4554 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4555
4556 setup_msrs(vmx);
4557
6aa8b732
AK		 4558 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4559
f78e0e2e
SY		 4560 if (cpu_has_vmx_tpr_shadow()) {
4561 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4562 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4563 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4564 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4565 vmcs_write32(TPR_THRESHOLD, 0);
4566 }
4567
38b99173 4568 kvm_vcpu_reload_apic_access_page(vcpu);
6aa8b732 4569
01e439be
YZ		 4570 if (vmx_vm_has_apicv(vcpu->kvm))
4571 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4572
2384d2b3
SY		 4573 if (vmx->vpid != 0)
4574 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4575
fa40052c 4576 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4577 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4578 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4579 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4580 vmx_fpu_activate(&vmx->vcpu);
4581 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4582
b9d762fa 4583 vpid_sync_context(vmx);
6aa8b732
AK		 4584}
4585
b6f1250e
NHE		 4586/*
4587 * In nested virtualization, check if L1 asked to exit on external interrupts.
4588 * For most existing hypervisors, this will always return true.
4589 */
4590static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4591{
4592 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4593 PIN_BASED_EXT_INTR_MASK;
4594}
4595
77b0f5d6
BD		 4596/*
4597 * In nested virtualization, check if L1 has set
4598 * VM_EXIT_ACK_INTR_ON_EXIT
4599 */
4600static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4601{
4602 return get_vmcs12(vcpu)->vm_exit_controls &
4603 VM_EXIT_ACK_INTR_ON_EXIT;
4604}
4605
ea8ceb83
JK		 4606static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4607{
4608 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4609 PIN_BASED_NMI_EXITING;
4610}
4611
c9a7953f 4612static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4613{
4614 u32 cpu_based_vm_exec_control;
730dca42 4615
3b86cd99
JK		 4616 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4617 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4618 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4619}
4620
c9a7953f 4621static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4622{
4623 u32 cpu_based_vm_exec_control;
4624
c9a7953f
JK		 4625 if (!cpu_has_virtual_nmis() ||
4626 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4627 enable_irq_window(vcpu);
4628 return;
4629 }
3b86cd99
JK		 4630
4631 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4632 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4633 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4634}
4635
66fd3f7f 4636static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4637{
9c8cba37 4638 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4639 uint32_t intr;
4640 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4641
229456fc 4642 trace_kvm_inj_virq(irq);
2714d1d3 4643
fa89a817 4644 ++vcpu->stat.irq_injections;
7ffd92c5 4645 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4646 int inc_eip = 0;
4647 if (vcpu->arch.interrupt.soft)
4648 inc_eip = vcpu->arch.event_exit_inst_len;
4649 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4650 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4651 return;
4652 }
66fd3f7f
GN		 4653 intr = irq | INTR_INFO_VALID_MASK;
4654 if (vcpu->arch.interrupt.soft) {
4655 intr |= INTR_TYPE_SOFT_INTR;
4656 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4657 vmx->vcpu.arch.event_exit_inst_len);
4658 } else
4659 intr |= INTR_TYPE_EXT_INTR;
4660 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4661}
4662
f08864b4
SY		 4663static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4664{
66a5a347
JK		 4665 struct vcpu_vmx *vmx = to_vmx(vcpu);
4666
0b6ac343
NHE		 4667 if (is_guest_mode(vcpu))
4668 return;
4669
3b86cd99
JK		 4670 if (!cpu_has_virtual_nmis()) {
4671 /*
4672 * Tracking the NMI-blocked state in software is built upon
4673 * finding the next open IRQ window. This, in turn, depends on
4674 * well-behaving guests: They have to keep IRQs disabled at
4675 * least as long as the NMI handler runs. Otherwise we may
4676 * cause NMI nesting, maybe breaking the guest. But as this is
4677 * highly unlikely, we can live with the residual risk.
4678 */
4679 vmx->soft_vnmi_blocked = 1;
4680 vmx->vnmi_blocked_time = 0;
4681 }
4682
487b391d 4683 ++vcpu->stat.nmi_injections;
9d58b931 4684 vmx->nmi_known_unmasked = false;
7ffd92c5 4685 if (vmx->rmode.vm86_active) {
71f9833b 4686 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4687 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4688 return;
4689 }
f08864b4
SY		 4690 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4691 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4692}
4693
3cfc3092
JK		 4694static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4695{
4696 if (!cpu_has_virtual_nmis())
4697 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4698 if (to_vmx(vcpu)->nmi_known_unmasked)
4699 return false;
c332c83a 4700 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4701}
4702
4703static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4704{
4705 struct vcpu_vmx *vmx = to_vmx(vcpu);
4706
4707 if (!cpu_has_virtual_nmis()) {
4708 if (vmx->soft_vnmi_blocked != masked) {
4709 vmx->soft_vnmi_blocked = masked;
4710 vmx->vnmi_blocked_time = 0;
4711 }
4712 } else {
9d58b931 4713 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4714 if (masked)
4715 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4716 GUEST_INTR_STATE_NMI);
4717 else
4718 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4719 GUEST_INTR_STATE_NMI);
4720 }
4721}
4722
2505dc9f
JK		 4723static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4724{
b6b8a145
JK		 4725 if (to_vmx(vcpu)->nested.nested_run_pending)
4726 return 0;
ea8ceb83 4727
2505dc9f
JK		 4728 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4729 return 0;
4730
4731 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4732 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4733 | GUEST_INTR_STATE_NMI));
4734}
4735
78646121
GN		 4736static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4737{
b6b8a145
JK		 4738 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4739 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4740 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4741 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4742}
4743
cbc94022
IE		 4744static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4745{
4746 int ret;
4747 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4748 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4749 .guest_phys_addr = addr,
4750 .memory_size = PAGE_SIZE * 3,
4751 .flags = 0,
4752 };
4753
47ae31e2 4754 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4755 if (ret)
4756 return ret;
bfc6d222 4757 kvm->arch.tss_addr = addr;
1f755a82 4758 return init_rmode_tss(kvm);
cbc94022
IE		 4759}
4760
0ca1b4f4 4761static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4762{
77ab6db0 4763 switch (vec) {
77ab6db0 4764 case BP_VECTOR:
c573cd22
JK		 4765 /*
4766 * Update instruction length as we may reinject the exception
4767 * from user space while in guest debugging mode.
4768 */
4769 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4770 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4771 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4772 return false;
4773 /* fall through */
4774 case DB_VECTOR:
4775 if (vcpu->guest_debug &
4776 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4777 return false;
d0bfb940
JK		 4778 /* fall through */
4779 case DE_VECTOR:
77ab6db0
JK		 4780 case OF_VECTOR:
4781 case BR_VECTOR:
4782 case UD_VECTOR:
4783 case DF_VECTOR:
4784 case SS_VECTOR:
4785 case GP_VECTOR:
4786 case MF_VECTOR:
0ca1b4f4
GN		 4787 return true;
4788 break;
77ab6db0 4789 }
0ca1b4f4
GN		 4790 return false;
4791}
4792
4793static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4794 int vec, u32 err_code)
4795{
4796 /*
4797 * Instruction with address size override prefix opcode 0x67
4798 * Cause the #SS fault with 0 error code in VM86 mode.
4799 */
4800 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4801 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4802 if (vcpu->arch.halt_request) {
4803 vcpu->arch.halt_request = 0;
4804 return kvm_emulate_halt(vcpu);
4805 }
4806 return 1;
4807 }
4808 return 0;
4809 }
4810
4811 /*
4812 * Forward all other exceptions that are valid in real mode.
4813 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4814 * the required debugging infrastructure rework.
4815 */
4816 kvm_queue_exception(vcpu, vec);
4817 return 1;
6aa8b732
AK		 4818}
4819
a0861c02
AK		 4820/*
4821 * Trigger machine check on the host. We assume all the MSRs are already set up
4822 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4823 * We pass a fake environment to the machine check handler because we want
4824 * the guest to be always treated like user space, no matter what context
4825 * it used internally.
4826 */
4827static void kvm_machine_check(void)
4828{
4829#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4830 struct pt_regs regs = {
4831 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4832 .flags = X86_EFLAGS_IF,
4833 };
4834
4835 do_machine_check(&regs, 0);
4836#endif
4837}
4838
851ba692 4839static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4840{
4841 /* already handled by vcpu_run */
4842 return 1;
4843}
4844
851ba692 4845static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4846{
1155f76a 4847 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4848 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4849 u32 intr_info, ex_no, error_code;
42dbaa5a 4850 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4851 u32 vect_info;
4852 enum emulation_result er;
4853
1155f76a 4854 vect_info = vmx->idt_vectoring_info;
88786475 4855 intr_info = vmx->exit_intr_info;
6aa8b732 4856
a0861c02 4857 if (is_machine_check(intr_info))
851ba692 4858 return handle_machine_check(vcpu);
a0861c02 4859
e4a41889 4860 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4861 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4862
4863 if (is_no_device(intr_info)) {
5fd86fcf 4864 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4865 return 1;
4866 }
4867
7aa81cc0 4868 if (is_invalid_opcode(intr_info)) {
51d8b661 4869 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4870 if (er != EMULATE_DONE)
7ee5d940 4871 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4872 return 1;
4873 }
4874
6aa8b732 4875 error_code = 0;
2e11384c 4876 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4877 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4878
4879 /*
4880 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4881 * MMIO, it is better to report an internal error.
4882 * See the comments in vmx_handle_exit.
4883 */
4884 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4885 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4886 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4887 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4888 vcpu->run->internal.ndata = 2;
4889 vcpu->run->internal.data[0] = vect_info;
4890 vcpu->run->internal.data[1] = intr_info;
4891 return 0;
4892 }
4893
6aa8b732 4894 if (is_page_fault(intr_info)) {
1439442c 4895 /* EPT won't cause page fault directly */
cf3ace79 4896 BUG_ON(enable_ept);
6aa8b732 4897 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4898 trace_kvm_page_fault(cr2, error_code);
4899
3298b75c 4900 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4901 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4902 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4903 }
4904
d0bfb940 4905 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4906
4907 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4908 return handle_rmode_exception(vcpu, ex_no, error_code);
4909
42dbaa5a
JK		 4910 switch (ex_no) {
4911 case DB_VECTOR:
4912 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4913 if (!(vcpu->guest_debug &
4914 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4915 vcpu->arch.dr6 &= ~15;
6f43ed01 4916 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4917 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4918 skip_emulated_instruction(vcpu);
4919
42dbaa5a
JK		 4920 kvm_queue_exception(vcpu, DB_VECTOR);
4921 return 1;
4922 }
4923 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4924 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4925 /* fall through */
4926 case BP_VECTOR:
c573cd22
JK		 4927 /*
4928 * Update instruction length as we may reinject #BP from
4929 * user space while in guest debugging mode. Reading it for
4930 * #DB as well causes no harm, it is not used in that case.
4931 */
4932 vmx->vcpu.arch.event_exit_inst_len =
4933 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4934 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4935 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4936 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4937 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4938 break;
4939 default:
d0bfb940
JK		 4940 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4941 kvm_run->ex.exception = ex_no;
4942 kvm_run->ex.error_code = error_code;
42dbaa5a 4943 break;
6aa8b732 4944 }
6aa8b732
AK		 4945 return 0;
4946}
4947
851ba692 4948static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4949{
1165f5fe 4950 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4951 return 1;
4952}
4953
851ba692 4954static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4955{
851ba692 4956 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4957 return 0;
4958}
6aa8b732 4959
851ba692 4960static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4961{
bfdaab09 4962 unsigned long exit_qualification;
34c33d16 4963 int size, in, string;
039576c0 4964 unsigned port;
6aa8b732 4965
bfdaab09 4966 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4967 string = (exit_qualification & 16) != 0;
cf8f70bf 4968 in = (exit_qualification & 8) != 0;
e70669ab 4969
cf8f70bf 4970 ++vcpu->stat.io_exits;
e70669ab 4971
cf8f70bf 4972 if (string || in)
51d8b661 4973 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4974
cf8f70bf
GN		 4975 port = exit_qualification >> 16;
4976 size = (exit_qualification & 7) + 1;
e93f36bc 4977 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4978
4979 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4980}
4981
102d8325
IM		 4982static void
4983vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4984{
4985 /*
4986 * Patch in the VMCALL instruction:
4987 */
4988 hypercall[0] = 0x0f;
4989 hypercall[1] = 0x01;
4990 hypercall[2] = 0xc1;
102d8325
IM		 4991}
4992
92fbc7b1
JK		 4993static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4994{
4995 unsigned long always_on = VMXON_CR0_ALWAYSON;
4996
4997 if (nested_vmx_secondary_ctls_high &
4998 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4999 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5000 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5001 return (val & always_on) == always_on;
5002}
5003
0fa06071 5004/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5005static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5006{
eeadf9e7 5007 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5008 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5009 unsigned long orig_val = val;
5010
eeadf9e7
NHE		 5011 /*
5012 * We get here when L2 changed cr0 in a way that did not change
5013 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5014 * but did change L0 shadowed bits. So we first calculate the
5015 * effective cr0 value that L1 would like to write into the
5016 * hardware. It consists of the L2-owned bits from the new
5017 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5018 */
1a0d74e6
JK		 5019 val = (val & ~vmcs12->cr0_guest_host_mask) |
5020 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5021
92fbc7b1 5022 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5023 return 1;
1a0d74e6
JK		 5024
5025 if (kvm_set_cr0(vcpu, val))
5026 return 1;
5027 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5028 return 0;
1a0d74e6
JK		 5029 } else {
5030 if (to_vmx(vcpu)->nested.vmxon &&
5031 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5032 return 1;
eeadf9e7 5033 return kvm_set_cr0(vcpu, val);
1a0d74e6 5034 }
eeadf9e7
NHE		 5035}
5036
5037static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5038{
5039 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5040 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5041 unsigned long orig_val = val;
5042
5043 /* analogously to handle_set_cr0 */
5044 val = (val & ~vmcs12->cr4_guest_host_mask) |
5045 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5046 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5047 return 1;
1a0d74e6 5048 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5049 return 0;
5050 } else
5051 return kvm_set_cr4(vcpu, val);
5052}
5053
5054/* called to set cr0 as approriate for clts instruction exit. */
5055static void handle_clts(struct kvm_vcpu *vcpu)
5056{
5057 if (is_guest_mode(vcpu)) {
5058 /*
5059 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5060 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5061 * just pretend it's off (also in arch.cr0 for fpu_activate).
5062 */
5063 vmcs_writel(CR0_READ_SHADOW,
5064 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5065 vcpu->arch.cr0 &= ~X86_CR0_TS;
5066 } else
5067 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5068}
5069
851ba692 5070static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5071{
229456fc 5072 unsigned long exit_qualification, val;
6aa8b732
AK		 5073 int cr;
5074 int reg;
49a9b07e 5075 int err;
6aa8b732 5076
bfdaab09 5077 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5078 cr = exit_qualification & 15;
5079 reg = (exit_qualification >> 8) & 15;
5080 switch ((exit_qualification >> 4) & 3) {
5081 case 0: /* mov to cr */
1e32c079 5082 val = kvm_register_readl(vcpu, reg);
229456fc 5083 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5084 switch (cr) {
5085 case 0:
eeadf9e7 5086 err = handle_set_cr0(vcpu, val);
db8fcefa 5087 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5088 return 1;
5089 case 3:
2390218b 5090 err = kvm_set_cr3(vcpu, val);
db8fcefa 5091 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5092 return 1;
5093 case 4:
eeadf9e7 5094 err = handle_set_cr4(vcpu, val);
db8fcefa 5095 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5096 return 1;
0a5fff19
GN		 5097 case 8: {
5098 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5099 u8 cr8 = (u8)val;
eea1cff9 5100 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5101 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5102 if (irqchip_in_kernel(vcpu->kvm))
5103 return 1;
5104 if (cr8_prev <= cr8)
5105 return 1;
851ba692 5106 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5107 return 0;
5108 }
4b8073e4 5109 }
6aa8b732 5110 break;
25c4c276 5111 case 2: /* clts */
eeadf9e7 5112 handle_clts(vcpu);
4d4ec087 5113 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5114 skip_emulated_instruction(vcpu);
6b52d186 5115 vmx_fpu_activate(vcpu);
25c4c276 5116 return 1;
6aa8b732
AK		 5117 case 1: /*mov from cr*/
5118 switch (cr) {
5119 case 3:
9f8fe504
AK		 5120 val = kvm_read_cr3(vcpu);
5121 kvm_register_write(vcpu, reg, val);
5122 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5123 skip_emulated_instruction(vcpu);
5124 return 1;
5125 case 8:
229456fc
MT		 5126 val = kvm_get_cr8(vcpu);
5127 kvm_register_write(vcpu, reg, val);
5128 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5129 skip_emulated_instruction(vcpu);
5130 return 1;
5131 }
5132 break;
5133 case 3: /* lmsw */
a1f83a74 5134 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5135 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5136 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5137
5138 skip_emulated_instruction(vcpu);
5139 return 1;
5140 default:
5141 break;
5142 }
851ba692 5143 vcpu->run->exit_reason = 0;
a737f256 5144 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5145 (int)(exit_qualification >> 4) & 3, cr);
5146 return 0;
5147}
5148
851ba692 5149static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5150{
bfdaab09 5151 unsigned long exit_qualification;
6aa8b732
AK		 5152 int dr, reg;
5153
f2483415 5154 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5155 if (!kvm_require_cpl(vcpu, 0))
5156 return 1;
42dbaa5a
JK		 5157 dr = vmcs_readl(GUEST_DR7);
5158 if (dr & DR7_GD) {
5159 /*
5160 * As the vm-exit takes precedence over the debug trap, we
5161 * need to emulate the latter, either for the host or the
5162 * guest debugging itself.
5163 */
5164 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5165 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5166 vcpu->run->debug.arch.dr7 = dr;
5167 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5168 vmcs_readl(GUEST_CS_BASE) +
5169 vmcs_readl(GUEST_RIP);
851ba692
AK		 5170 vcpu->run->debug.arch.exception = DB_VECTOR;
5171 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5172 return 0;
5173 } else {
5174 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5175 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5176 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5177 kvm_queue_exception(vcpu, DB_VECTOR);
5178 return 1;
5179 }
5180 }
5181
81908bf4
PB		 5182 if (vcpu->guest_debug == 0) {
5183 u32 cpu_based_vm_exec_control;
5184
5185 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5186 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5187 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5188
5189 /*
5190 * No more DR vmexits; force a reload of the debug registers
5191 * and reenter on this instruction. The next vmexit will
5192 * retrieve the full state of the debug registers.
5193 */
5194 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5195 return 1;
5196 }
5197
bfdaab09 5198 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5199 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5200 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5201 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5202 unsigned long val;
4c4d563b
JK		 5203
5204 if (kvm_get_dr(vcpu, dr, &val))
5205 return 1;
5206 kvm_register_write(vcpu, reg, val);
020df079 5207 } else
5777392e 5208 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5209 return 1;
5210
6aa8b732
AK		 5211 skip_emulated_instruction(vcpu);
5212 return 1;
5213}
5214
73aaf249
JK		 5215static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5216{
5217 return vcpu->arch.dr6;
5218}
5219
5220static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5221{
5222}
5223
81908bf4
PB		 5224static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5225{
5226 u32 cpu_based_vm_exec_control;
5227
5228 get_debugreg(vcpu->arch.db[0], 0);
5229 get_debugreg(vcpu->arch.db[1], 1);
5230 get_debugreg(vcpu->arch.db[2], 2);
5231 get_debugreg(vcpu->arch.db[3], 3);
5232 get_debugreg(vcpu->arch.dr6, 6);
5233 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5234
5235 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5236
5237 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5238 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5239 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5240}
5241
020df079
GN		 5242static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5243{
5244 vmcs_writel(GUEST_DR7, val);
5245}
5246
851ba692 5247static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5248{
06465c5a
AK		 5249 kvm_emulate_cpuid(vcpu);
5250 return 1;
6aa8b732
AK		 5251}
5252
851ba692 5253static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5254{
ad312c7c 5255 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5256 u64 data;
5257
5258 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5259 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5260 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5261 return 1;
5262 }
5263
229456fc 5264 trace_kvm_msr_read(ecx, data);
2714d1d3 5265
6aa8b732 5266 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5267 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5268 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5269 skip_emulated_instruction(vcpu);
5270 return 1;
5271}
5272
851ba692 5273static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5274{
8fe8ab46 5275 struct msr_data msr;
ad312c7c
ZX		 5276 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5277 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5278 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5279
8fe8ab46
WA		 5280 msr.data = data;
5281 msr.index = ecx;
5282 msr.host_initiated = false;
5283 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5284 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5285 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5286 return 1;
5287 }
5288
59200273 5289 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5290 skip_emulated_instruction(vcpu);
5291 return 1;
5292}
5293
851ba692 5294static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5295{
3842d135 5296 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5297 return 1;
5298}
5299
851ba692 5300static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5301{
85f455f7
ED		 5302 u32 cpu_based_vm_exec_control;
5303
5304 /* clear pending irq */
5305 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5306 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5308
3842d135
AK		 5309 kvm_make_request(KVM_REQ_EVENT, vcpu);
5310
a26bf12a 5311 ++vcpu->stat.irq_window_exits;
2714d1d3 5312
c1150d8c
DL		 5313 /*
5314 * If the user space waits to inject interrupts, exit as soon as
5315 * possible
5316 */
8061823a 5317 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5318 vcpu->run->request_interrupt_window &&
8061823a 5319 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5320 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5321 return 0;
5322 }
6aa8b732
AK		 5323 return 1;
5324}
5325
851ba692 5326static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5327{
5328 skip_emulated_instruction(vcpu);
d3bef15f 5329 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5330}
5331
851ba692 5332static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5333{
510043da 5334 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5335 kvm_emulate_hypercall(vcpu);
5336 return 1;
c21415e8
IM		 5337}
5338
ec25d5e6
GN		 5339static int handle_invd(struct kvm_vcpu *vcpu)
5340{
51d8b661 5341 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5342}
5343
851ba692 5344static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5345{
f9c617f6 5346 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5347
5348 kvm_mmu_invlpg(vcpu, exit_qualification);
5349 skip_emulated_instruction(vcpu);
5350 return 1;
5351}
5352
fee84b07
AK		 5353static int handle_rdpmc(struct kvm_vcpu *vcpu)
5354{
5355 int err;
5356
5357 err = kvm_rdpmc(vcpu);
5358 kvm_complete_insn_gp(vcpu, err);
5359
5360 return 1;
5361}
5362
851ba692 5363static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5364{
5365 skip_emulated_instruction(vcpu);
f5f48ee1 5366 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5367 return 1;
5368}
5369
2acf923e
DC		 5370static int handle_xsetbv(struct kvm_vcpu *vcpu)
5371{
5372 u64 new_bv = kvm_read_edx_eax(vcpu);
5373 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5374
5375 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5376 skip_emulated_instruction(vcpu);
5377 return 1;
5378}
5379
851ba692 5380static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5381{
58fbbf26
KT		 5382 if (likely(fasteoi)) {
5383 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5384 int access_type, offset;
5385
5386 access_type = exit_qualification & APIC_ACCESS_TYPE;
5387 offset = exit_qualification & APIC_ACCESS_OFFSET;
5388 /*
5389 * Sane guest uses MOV to write EOI, with written value
5390 * not cared. So make a short-circuit here by avoiding
5391 * heavy instruction emulation.
5392 */
5393 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5394 (offset == APIC_EOI)) {
5395 kvm_lapic_set_eoi(vcpu);
5396 skip_emulated_instruction(vcpu);
5397 return 1;
5398 }
5399 }
51d8b661 5400 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5401}
5402
c7c9c56c
YZ		 5403static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5404{
5405 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5406 int vector = exit_qualification & 0xff;
5407
5408 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5409 kvm_apic_set_eoi_accelerated(vcpu, vector);
5410 return 1;
5411}
5412
83d4c286
YZ		 5413static int handle_apic_write(struct kvm_vcpu *vcpu)
5414{
5415 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5416 u32 offset = exit_qualification & 0xfff;
5417
5418 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5419 kvm_apic_write_nodecode(vcpu, offset);
5420 return 1;
5421}
5422
851ba692 5423static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5424{
60637aac 5425 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5426 unsigned long exit_qualification;
e269fb21
JK		 5427 bool has_error_code = false;
5428 u32 error_code = 0;
37817f29 5429 u16 tss_selector;
7f3d35fd 5430 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5431
5432 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5433 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5434 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5435
5436 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5437
5438 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5439 if (reason == TASK_SWITCH_GATE && idt_v) {
5440 switch (type) {
5441 case INTR_TYPE_NMI_INTR:
5442 vcpu->arch.nmi_injected = false;
654f06fc 5443 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5444 break;
5445 case INTR_TYPE_EXT_INTR:
66fd3f7f 5446 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5447 kvm_clear_interrupt_queue(vcpu);
5448 break;
5449 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5450 if (vmx->idt_vectoring_info &
5451 VECTORING_INFO_DELIVER_CODE_MASK) {
5452 has_error_code = true;
5453 error_code =
5454 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5455 }
5456 /* fall through */
64a7ec06
GN		 5457 case INTR_TYPE_SOFT_EXCEPTION:
5458 kvm_clear_exception_queue(vcpu);
5459 break;
5460 default:
5461 break;
5462 }
60637aac 5463 }
37817f29
IE		 5464 tss_selector = exit_qualification;
5465
64a7ec06
GN		 5466 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5467 type != INTR_TYPE_EXT_INTR &&
5468 type != INTR_TYPE_NMI_INTR))
5469 skip_emulated_instruction(vcpu);
5470
7f3d35fd
KW		 5471 if (kvm_task_switch(vcpu, tss_selector,
5472 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5473 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5474 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5475 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5476 vcpu->run->internal.ndata = 0;
42dbaa5a 5477 return 0;
acb54517 5478 }
42dbaa5a
JK		 5479
5480 /* clear all local breakpoint enable flags */
1f854112 5481 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5482
5483 /*
5484 * TODO: What about debug traps on tss switch?
5485 * Are we supposed to inject them and update dr6?
5486 */
5487
5488 return 1;
37817f29
IE		 5489}
5490
851ba692 5491static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5492{
f9c617f6 5493 unsigned long exit_qualification;
1439442c 5494 gpa_t gpa;
4f5982a5 5495 u32 error_code;
1439442c 5496 int gla_validity;
1439442c 5497
f9c617f6 5498 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5499
1439442c
SY		 5500 gla_validity = (exit_qualification >> 7) & 0x3;
5501 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5502 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5503 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5504 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5505 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5506 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5507 (long unsigned int)exit_qualification);
851ba692
AK		 5508 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5509 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5510 return 0;
1439442c
SY		 5511 }
5512
0be9c7a8
GN		 5513 /*
5514 * EPT violation happened while executing iret from NMI,
5515 * "blocked by NMI" bit has to be set before next VM entry.
5516 * There are errata that may cause this bit to not be set:
5517 * AAK134, BY25.
5518 */
bcd1c294
GN		 5519 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5520 cpu_has_virtual_nmis() &&
5521 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5522 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5523
1439442c 5524 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5525 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5526
5527 /* It is a write fault? */
5528 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5529 /* It is a fetch fault? */
5530 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5531 /* ept page table is present? */
5532 error_code |= (exit_qualification >> 3) & 0x1;
5533
25d92081
YZ		 5534 vcpu->arch.exit_qualification = exit_qualification;
5535
4f5982a5 5536 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5537}
5538
68f89400
MT		 5539static u64 ept_rsvd_mask(u64 spte, int level)
5540{
5541 int i;
5542 u64 mask = 0;
5543
5544 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5545 mask |= (1ULL << i);
5546
a32e8459 5547 if (level == 4)
68f89400
MT		 5548 /* bits 7:3 reserved */
5549 mask |= 0xf8;
a32e8459
WL		 5550 else if (spte & (1ULL << 7))
5551 /*
5552 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5553 * level == 1 if the hypervisor is using the ignored bit 7.
5554 */
5555 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5556 else if (level > 1)
5557 /* bits 6:3 reserved */
5558 mask |= 0x78;
68f89400
MT		 5559
5560 return mask;
5561}
5562
5563static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5564 int level)
5565{
5566 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5567
5568 /* 010b (write-only) */
5569 WARN_ON((spte & 0x7) == 0x2);
5570
5571 /* 110b (write/execute) */
5572 WARN_ON((spte & 0x7) == 0x6);
5573
5574 /* 100b (execute-only) and value not supported by logical processor */
5575 if (!cpu_has_vmx_ept_execute_only())
5576 WARN_ON((spte & 0x7) == 0x4);
5577
5578 /* not 000b */
5579 if ((spte & 0x7)) {
5580 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5581
5582 if (rsvd_bits != 0) {
5583 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5584 __func__, rsvd_bits);
5585 WARN_ON(1);
5586 }
5587
a32e8459
WL		 5588 /* bits 5:3 are _not_ reserved for large page or leaf page */
5589 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5590 u64 ept_mem_type = (spte & 0x38) >> 3;
5591
5592 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5593 ept_mem_type == 7) {
5594 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5595 __func__, ept_mem_type);
5596 WARN_ON(1);
5597 }
5598 }
5599 }
5600}
5601
851ba692 5602static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5603{
5604 u64 sptes[4];
ce88decf 5605 int nr_sptes, i, ret;
68f89400
MT		 5606 gpa_t gpa;
5607
5608 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5609 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5610 skip_emulated_instruction(vcpu);
5611 return 1;
5612 }
68f89400 5613
ce88decf 5614 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5615 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5616 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5617 EMULATE_DONE;
f8f55942
XG		 5618
5619 if (unlikely(ret == RET_MMIO_PF_INVALID))
5620 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5621
b37fbea6 5622 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5623 return 1;
5624
5625 /* It is the real ept misconfig */
68f89400
MT		 5626 printk(KERN_ERR "EPT: Misconfiguration.\n");
5627 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5628
5629 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5630
5631 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5632 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5633
851ba692
AK		 5634 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5635 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5636
5637 return 0;
5638}
5639
851ba692 5640static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5641{
5642 u32 cpu_based_vm_exec_control;
5643
5644 /* clear pending NMI */
5645 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5646 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5648 ++vcpu->stat.nmi_window_exits;
3842d135 5649 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5650
5651 return 1;
5652}
5653
80ced186 5654static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5655{
8b3079a5
AK		 5656 struct vcpu_vmx *vmx = to_vmx(vcpu);
5657 enum emulation_result err = EMULATE_DONE;
80ced186 5658 int ret = 1;
49e9d557
AK		 5659 u32 cpu_exec_ctrl;
5660 bool intr_window_requested;
b8405c18 5661 unsigned count = 130;
49e9d557
AK		 5662
5663 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5664 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5665
98eb2f8b 5666 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5667 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5668 return handle_interrupt_window(&vmx->vcpu);
5669
de87dcdd
AK		 5670 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5671 return 1;
5672
991eebf9 5673 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5674
ac0a48c3 5675 if (err == EMULATE_USER_EXIT) {
94452b9e 5676 ++vcpu->stat.mmio_exits;
80ced186
MG		 5677 ret = 0;
5678 goto out;
5679 }
1d5a4d9b 5680
de5f70e0
AK		 5681 if (err != EMULATE_DONE) {
5682 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5683 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5684 vcpu->run->internal.ndata = 0;
6d77dbfc 5685 return 0;
de5f70e0 5686 }
ea953ef0 5687
8d76c49e
GN		 5688 if (vcpu->arch.halt_request) {
5689 vcpu->arch.halt_request = 0;
5690 ret = kvm_emulate_halt(vcpu);
5691 goto out;
5692 }
5693
ea953ef0 5694 if (signal_pending(current))
80ced186 5695 goto out;
ea953ef0
MG		 5696 if (need_resched())
5697 schedule();
5698 }
5699
80ced186
MG		 5700out:
5701 return ret;
ea953ef0
MG		 5702}
5703
b4a2d31d
RK		 5704static int __grow_ple_window(int val)
5705{
5706 if (ple_window_grow < 1)
5707 return ple_window;
5708
5709 val = min(val, ple_window_actual_max);
5710
5711 if (ple_window_grow < ple_window)
5712 val *= ple_window_grow;
5713 else
5714 val += ple_window_grow;
5715
5716 return val;
5717}
5718
5719static int __shrink_ple_window(int val, int modifier, int minimum)
5720{
5721 if (modifier < 1)
5722 return ple_window;
5723
5724 if (modifier < ple_window)
5725 val /= modifier;
5726 else
5727 val -= modifier;
5728
5729 return max(val, minimum);
5730}
5731
5732static void grow_ple_window(struct kvm_vcpu *vcpu)
5733{
5734 struct vcpu_vmx *vmx = to_vmx(vcpu);
5735 int old = vmx->ple_window;
5736
5737 vmx->ple_window = __grow_ple_window(old);
5738
5739 if (vmx->ple_window != old)
5740 vmx->ple_window_dirty = true;
7b46268d
RK		 5741
5742 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5743}
5744
5745static void shrink_ple_window(struct kvm_vcpu *vcpu)
5746{
5747 struct vcpu_vmx *vmx = to_vmx(vcpu);
5748 int old = vmx->ple_window;
5749
5750 vmx->ple_window = __shrink_ple_window(old,
5751 ple_window_shrink, ple_window);
5752
5753 if (vmx->ple_window != old)
5754 vmx->ple_window_dirty = true;
7b46268d
RK		 5755
5756 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5757}
5758
5759/*
5760 * ple_window_actual_max is computed to be one grow_ple_window() below
5761 * ple_window_max. (See __grow_ple_window for the reason.)
5762 * This prevents overflows, because ple_window_max is int.
5763 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5764 * this process.
5765 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5766 */
5767static void update_ple_window_actual_max(void)
5768{
5769 ple_window_actual_max =
5770 __shrink_ple_window(max(ple_window_max, ple_window),
5771 ple_window_grow, INT_MIN);
5772}
5773
4b8d54f9
ZE		 5774/*
5775 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5776 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5777 */
9fb41ba8 5778static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5779{
b4a2d31d
RK		 5780 if (ple_gap)
5781 grow_ple_window(vcpu);
5782
4b8d54f9
ZE		 5783 skip_emulated_instruction(vcpu);
5784 kvm_vcpu_on_spin(vcpu);
5785
5786 return 1;
5787}
5788
87c00572 5789static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5790{
87c00572 5791 skip_emulated_instruction(vcpu);
59708670
SY		 5792 return 1;
5793}
5794
87c00572
GS		 5795static int handle_mwait(struct kvm_vcpu *vcpu)
5796{
5797 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5798 return handle_nop(vcpu);
5799}
5800
5801static int handle_monitor(struct kvm_vcpu *vcpu)
5802{
5803 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5804 return handle_nop(vcpu);
5805}
5806
ff2f6fe9
NHE		 5807/*
5808 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5809 * We could reuse a single VMCS for all the L2 guests, but we also want the
5810 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5811 * allows keeping them loaded on the processor, and in the future will allow
5812 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5813 * every entry if they never change.
5814 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5815 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5816 *
5817 * The following functions allocate and free a vmcs02 in this pool.
5818 */
5819
5820/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5821static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5822{
5823 struct vmcs02_list *item;
5824 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5825 if (item->vmptr == vmx->nested.current_vmptr) {
5826 list_move(&item->list, &vmx->nested.vmcs02_pool);
5827 return &item->vmcs02;
5828 }
5829
5830 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5831 /* Recycle the least recently used VMCS. */
5832 item = list_entry(vmx->nested.vmcs02_pool.prev,
5833 struct vmcs02_list, list);
5834 item->vmptr = vmx->nested.current_vmptr;
5835 list_move(&item->list, &vmx->nested.vmcs02_pool);
5836 return &item->vmcs02;
5837 }
5838
5839 /* Create a new VMCS */
0fa24ce3 5840 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5841 if (!item)
5842 return NULL;
5843 item->vmcs02.vmcs = alloc_vmcs();
5844 if (!item->vmcs02.vmcs) {
5845 kfree(item);
5846 return NULL;
5847 }
5848 loaded_vmcs_init(&item->vmcs02);
5849 item->vmptr = vmx->nested.current_vmptr;
5850 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5851 vmx->nested.vmcs02_num++;
5852 return &item->vmcs02;
5853}
5854
5855/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5856static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5857{
5858 struct vmcs02_list *item;
5859 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5860 if (item->vmptr == vmptr) {
5861 free_loaded_vmcs(&item->vmcs02);
5862 list_del(&item->list);
5863 kfree(item);
5864 vmx->nested.vmcs02_num--;
5865 return;
5866 }
5867}
5868
5869/*
5870 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5871 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5872 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5873 */
5874static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5875{
5876 struct vmcs02_list *item, *n;
4fa7734c
PB		 5877
5878 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5879 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5880 /*
5881 * Something will leak if the above WARN triggers. Better than
5882 * a use-after-free.
5883 */
5884 if (vmx->loaded_vmcs == &item->vmcs02)
5885 continue;
5886
5887 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5888 list_del(&item->list);
5889 kfree(item);
4fa7734c 5890 vmx->nested.vmcs02_num--;
ff2f6fe9 5891 }
ff2f6fe9
NHE		 5892}
5893
0658fbaa
ACL		 5894/*
5895 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5896 * set the success or error code of an emulated VMX instruction, as specified
5897 * by Vol 2B, VMX Instruction Reference, "Conventions".
5898 */
5899static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5900{
5901 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5902 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5903 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5904}
5905
5906static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5907{
5908 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5909 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5910 X86_EFLAGS_SF | X86_EFLAGS_OF))
5911 | X86_EFLAGS_CF);
5912}
5913
145c28dd 5914static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5915 u32 vm_instruction_error)
5916{
5917 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5918 /*
5919 * failValid writes the error number to the current VMCS, which
5920 * can't be done there isn't a current VMCS.
5921 */
5922 nested_vmx_failInvalid(vcpu);
5923 return;
5924 }
5925 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5926 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5927 X86_EFLAGS_SF | X86_EFLAGS_OF))
5928 | X86_EFLAGS_ZF);
5929 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5930 /*
5931 * We don't need to force a shadow sync because
5932 * VM_INSTRUCTION_ERROR is not shadowed
5933 */
5934}
145c28dd 5935
f4124500
JK		 5936static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5937{
5938 struct vcpu_vmx *vmx =
5939 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5940
5941 vmx->nested.preemption_timer_expired = true;
5942 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5943 kvm_vcpu_kick(&vmx->vcpu);
5944
5945 return HRTIMER_NORESTART;
5946}
5947
19677e32
BD		 5948/*
5949 * Decode the memory-address operand of a vmx instruction, as recorded on an
5950 * exit caused by such an instruction (run by a guest hypervisor).
5951 * On success, returns 0. When the operand is invalid, returns 1 and throws
5952 * #UD or #GP.
5953 */
5954static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5955 unsigned long exit_qualification,
5956 u32 vmx_instruction_info, gva_t *ret)
5957{
5958 /*
5959 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5960 * Execution", on an exit, vmx_instruction_info holds most of the
5961 * addressing components of the operand. Only the displacement part
5962 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5963 * For how an actual address is calculated from all these components,
5964 * refer to Vol. 1, "Operand Addressing".
5965 */
5966 int scaling = vmx_instruction_info & 3;
5967 int addr_size = (vmx_instruction_info >> 7) & 7;
5968 bool is_reg = vmx_instruction_info & (1u << 10);
5969 int seg_reg = (vmx_instruction_info >> 15) & 7;
5970 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5971 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5972 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5973 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5974
5975 if (is_reg) {
5976 kvm_queue_exception(vcpu, UD_VECTOR);
5977 return 1;
5978 }
5979
5980 /* Addr = segment_base + offset */
5981 /* offset = base + [index * scale] + displacement */
5982 *ret = vmx_get_segment_base(vcpu, seg_reg);
5983 if (base_is_valid)
5984 *ret += kvm_register_read(vcpu, base_reg);
5985 if (index_is_valid)
5986 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5987 *ret += exit_qualification; /* holds the displacement */
5988
5989 if (addr_size == 1) /* 32 bit */
5990 *ret &= 0xffffffff;
5991
5992 /*
5993 * TODO: throw #GP (and return 1) in various cases that the VM*
5994 * instructions require it - e.g., offset beyond segment limit,
5995 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5996 * address, and so on. Currently these are not checked.
5997 */
5998 return 0;
5999}
6000
3573e22c
BD		 6001/*
6002 * This function performs the various checks including
6003 * - if it's 4KB aligned
6004 * - No bits beyond the physical address width are set
6005 * - Returns 0 on success or else 1
4291b588 6006 * (Intel SDM Section 30.3)
3573e22c 6007 */
4291b588
BD		 6008static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6009 gpa_t *vmpointer)
3573e22c
BD		 6010{
6011 gva_t gva;
6012 gpa_t vmptr;
6013 struct x86_exception e;
6014 struct page *page;
6015 struct vcpu_vmx *vmx = to_vmx(vcpu);
6016 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6017
6018 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6019 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6020 return 1;
6021
6022 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6023 sizeof(vmptr), &e)) {
6024 kvm_inject_page_fault(vcpu, &e);
6025 return 1;
6026 }
6027
6028 switch (exit_reason) {
6029 case EXIT_REASON_VMON:
6030 /*
6031 * SDM 3: 24.11.5
6032 * The first 4 bytes of VMXON region contain the supported
6033 * VMCS revision identifier
6034 *
6035 * Note - IA32_VMX_BASIC[48] will never be 1
6036 * for the nested case;
6037 * which replaces physical address width with 32
6038 *
6039 */
bc39c4db 6040 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6041 nested_vmx_failInvalid(vcpu);
6042 skip_emulated_instruction(vcpu);
6043 return 1;
6044 }
6045
6046 page = nested_get_page(vcpu, vmptr);
6047 if (page == NULL ||
6048 *(u32 *)kmap(page) != VMCS12_REVISION) {
6049 nested_vmx_failInvalid(vcpu);
6050 kunmap(page);
6051 skip_emulated_instruction(vcpu);
6052 return 1;
6053 }
6054 kunmap(page);
6055 vmx->nested.vmxon_ptr = vmptr;
6056 break;
4291b588 6057 case EXIT_REASON_VMCLEAR:
bc39c4db 6058 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6059 nested_vmx_failValid(vcpu,
6060 VMXERR_VMCLEAR_INVALID_ADDRESS);
6061 skip_emulated_instruction(vcpu);
6062 return 1;
6063 }
6064
6065 if (vmptr == vmx->nested.vmxon_ptr) {
6066 nested_vmx_failValid(vcpu,
6067 VMXERR_VMCLEAR_VMXON_POINTER);
6068 skip_emulated_instruction(vcpu);
6069 return 1;
6070 }
6071 break;
6072 case EXIT_REASON_VMPTRLD:
bc39c4db 6073 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6074 nested_vmx_failValid(vcpu,
6075 VMXERR_VMPTRLD_INVALID_ADDRESS);
6076 skip_emulated_instruction(vcpu);
6077 return 1;
6078 }
3573e22c 6079
4291b588
BD		 6080 if (vmptr == vmx->nested.vmxon_ptr) {
6081 nested_vmx_failValid(vcpu,
6082 VMXERR_VMCLEAR_VMXON_POINTER);
6083 skip_emulated_instruction(vcpu);
6084 return 1;
6085 }
6086 break;
3573e22c
BD		 6087 default:
6088 return 1; /* shouldn't happen */
6089 }
6090
4291b588
BD		 6091 if (vmpointer)
6092 *vmpointer = vmptr;
3573e22c
BD		 6093 return 0;
6094}
6095
ec378aee
NHE		 6096/*
6097 * Emulate the VMXON instruction.
6098 * Currently, we just remember that VMX is active, and do not save or even
6099 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6100 * do not currently need to store anything in that guest-allocated memory
6101 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6102 * argument is different from the VMXON pointer (which the spec says they do).
6103 */
6104static int handle_vmon(struct kvm_vcpu *vcpu)
6105{
6106 struct kvm_segment cs;
6107 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6108 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6109 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6110 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6111
6112 /* The Intel VMX Instruction Reference lists a bunch of bits that
6113 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6114 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6115 * Otherwise, we should fail with #UD. We test these now:
6116 */
6117 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6118 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6119 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6120 kvm_queue_exception(vcpu, UD_VECTOR);
6121 return 1;
6122 }
6123
6124 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6125 if (is_long_mode(vcpu) && !cs.l) {
6126 kvm_queue_exception(vcpu, UD_VECTOR);
6127 return 1;
6128 }
6129
6130 if (vmx_get_cpl(vcpu)) {
6131 kvm_inject_gp(vcpu, 0);
6132 return 1;
6133 }
3573e22c 6134
4291b588 6135 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6136 return 1;
6137
145c28dd
AG		 6138 if (vmx->nested.vmxon) {
6139 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6140 skip_emulated_instruction(vcpu);
6141 return 1;
6142 }
b3897a49
NHE		 6143
6144 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6145 != VMXON_NEEDED_FEATURES) {
6146 kvm_inject_gp(vcpu, 0);
6147 return 1;
6148 }
6149
8de48833
AG		 6150 if (enable_shadow_vmcs) {
6151 shadow_vmcs = alloc_vmcs();
6152 if (!shadow_vmcs)
6153 return -ENOMEM;
6154 /* mark vmcs as shadow */
6155 shadow_vmcs->revision_id |= (1u << 31);
6156 /* init shadow vmcs */
6157 vmcs_clear(shadow_vmcs);
6158 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6159 }
ec378aee 6160
ff2f6fe9
NHE		 6161 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6162 vmx->nested.vmcs02_num = 0;
6163
f4124500
JK		 6164 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6165 HRTIMER_MODE_REL);
6166 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6167
ec378aee
NHE		 6168 vmx->nested.vmxon = true;
6169
6170 skip_emulated_instruction(vcpu);
a25eb114 6171 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6172 return 1;
6173}
6174
6175/*
6176 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6177 * for running VMX instructions (except VMXON, whose prerequisites are
6178 * slightly different). It also specifies what exception to inject otherwise.
6179 */
6180static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6181{
6182 struct kvm_segment cs;
6183 struct vcpu_vmx *vmx = to_vmx(vcpu);
6184
6185 if (!vmx->nested.vmxon) {
6186 kvm_queue_exception(vcpu, UD_VECTOR);
6187 return 0;
6188 }
6189
6190 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6191 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6192 (is_long_mode(vcpu) && !cs.l)) {
6193 kvm_queue_exception(vcpu, UD_VECTOR);
6194 return 0;
6195 }
6196
6197 if (vmx_get_cpl(vcpu)) {
6198 kvm_inject_gp(vcpu, 0);
6199 return 0;
6200 }
6201
6202 return 1;
6203}
6204
e7953d7f
AG		 6205static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6206{
8a1b9dd0 6207 u32 exec_control;
9a2a05b9
PB		 6208 if (vmx->nested.current_vmptr == -1ull)
6209 return;
6210
6211 /* current_vmptr and current_vmcs12 are always set/reset together */
6212 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6213 return;
6214
012f83cb 6215 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6216 /* copy to memory all shadowed fields in case
6217 they were modified */
6218 copy_shadow_to_vmcs12(vmx);
6219 vmx->nested.sync_shadow_vmcs = false;
6220 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6221 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6222 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6223 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6224 }
e7953d7f
AG		 6225 kunmap(vmx->nested.current_vmcs12_page);
6226 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6227 vmx->nested.current_vmptr = -1ull;
6228 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6229}
6230
ec378aee
NHE		 6231/*
6232 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6233 * just stops using VMX.
6234 */
6235static void free_nested(struct vcpu_vmx *vmx)
6236{
6237 if (!vmx->nested.vmxon)
6238 return;
9a2a05b9 6239
ec378aee 6240 vmx->nested.vmxon = false;
9a2a05b9 6241 nested_release_vmcs12(vmx);
e7953d7f
AG		 6242 if (enable_shadow_vmcs)
6243 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6244 /* Unpin physical memory we referred to in current vmcs02 */
6245 if (vmx->nested.apic_access_page) {
6246 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6247 vmx->nested.apic_access_page = NULL;
fe3ef05c 6248 }
a7c0b07d
WL		 6249 if (vmx->nested.virtual_apic_page) {
6250 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6251 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6252 }
ff2f6fe9
NHE		 6253
6254 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6255}
6256
6257/* Emulate the VMXOFF instruction */
6258static int handle_vmoff(struct kvm_vcpu *vcpu)
6259{
6260 if (!nested_vmx_check_permission(vcpu))
6261 return 1;
6262 free_nested(to_vmx(vcpu));
6263 skip_emulated_instruction(vcpu);
a25eb114 6264 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6265 return 1;
6266}
6267
27d6c865
NHE		 6268/* Emulate the VMCLEAR instruction */
6269static int handle_vmclear(struct kvm_vcpu *vcpu)
6270{
6271 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6272 gpa_t vmptr;
6273 struct vmcs12 *vmcs12;
6274 struct page *page;
27d6c865
NHE		 6275
6276 if (!nested_vmx_check_permission(vcpu))
6277 return 1;
6278
4291b588 6279 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6280 return 1;
27d6c865 6281
9a2a05b9 6282 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6283 nested_release_vmcs12(vmx);
27d6c865
NHE		 6284
6285 page = nested_get_page(vcpu, vmptr);
6286 if (page == NULL) {
6287 /*
6288 * For accurate processor emulation, VMCLEAR beyond available
6289 * physical memory should do nothing at all. However, it is
6290 * possible that a nested vmx bug, not a guest hypervisor bug,
6291 * resulted in this case, so let's shut down before doing any
6292 * more damage:
6293 */
6294 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6295 return 1;
6296 }
6297 vmcs12 = kmap(page);
6298 vmcs12->launch_state = 0;
6299 kunmap(page);
6300 nested_release_page(page);
6301
6302 nested_free_vmcs02(vmx, vmptr);
6303
6304 skip_emulated_instruction(vcpu);
6305 nested_vmx_succeed(vcpu);
6306 return 1;
6307}
6308
cd232ad0
NHE		 6309static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6310
6311/* Emulate the VMLAUNCH instruction */
6312static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6313{
6314 return nested_vmx_run(vcpu, true);
6315}
6316
6317/* Emulate the VMRESUME instruction */
6318static int handle_vmresume(struct kvm_vcpu *vcpu)
6319{
6320
6321 return nested_vmx_run(vcpu, false);
6322}
6323
49f705c5
NHE		 6324enum vmcs_field_type {
6325 VMCS_FIELD_TYPE_U16 = 0,
6326 VMCS_FIELD_TYPE_U64 = 1,
6327 VMCS_FIELD_TYPE_U32 = 2,
6328 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6329};
6330
6331static inline int vmcs_field_type(unsigned long field)
6332{
6333 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6334 return VMCS_FIELD_TYPE_U32;
6335 return (field >> 13) & 0x3 ;
6336}
6337
6338static inline int vmcs_field_readonly(unsigned long field)
6339{
6340 return (((field >> 10) & 0x3) == 1);
6341}
6342
6343/*
6344 * Read a vmcs12 field. Since these can have varying lengths and we return
6345 * one type, we chose the biggest type (u64) and zero-extend the return value
6346 * to that size. Note that the caller, handle_vmread, might need to use only
6347 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6348 * 64-bit fields are to be returned).
6349 */
6350static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6351 unsigned long field, u64 *ret)
6352{
6353 short offset = vmcs_field_to_offset(field);
6354 char *p;
6355
6356 if (offset < 0)
6357 return 0;
6358
6359 p = ((char *)(get_vmcs12(vcpu))) + offset;
6360
6361 switch (vmcs_field_type(field)) {
6362 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6363 *ret = *((natural_width *)p);
6364 return 1;
6365 case VMCS_FIELD_TYPE_U16:
6366 *ret = *((u16 *)p);
6367 return 1;
6368 case VMCS_FIELD_TYPE_U32:
6369 *ret = *((u32 *)p);
6370 return 1;
6371 case VMCS_FIELD_TYPE_U64:
6372 *ret = *((u64 *)p);
6373 return 1;
6374 default:
6375 return 0; /* can never happen. */
6376 }
6377}
6378
20b97fea
AG		 6379
6380static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6381 unsigned long field, u64 field_value){
6382 short offset = vmcs_field_to_offset(field);
6383 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6384 if (offset < 0)
6385 return false;
6386
6387 switch (vmcs_field_type(field)) {
6388 case VMCS_FIELD_TYPE_U16:
6389 *(u16 *)p = field_value;
6390 return true;
6391 case VMCS_FIELD_TYPE_U32:
6392 *(u32 *)p = field_value;
6393 return true;
6394 case VMCS_FIELD_TYPE_U64:
6395 *(u64 *)p = field_value;
6396 return true;
6397 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6398 *(natural_width *)p = field_value;
6399 return true;
6400 default:
6401 return false; /* can never happen. */
6402 }
6403
6404}
6405
16f5b903
AG		 6406static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6407{
6408 int i;
6409 unsigned long field;
6410 u64 field_value;
6411 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6412 const unsigned long *fields = shadow_read_write_fields;
6413 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6414
6415 vmcs_load(shadow_vmcs);
6416
6417 for (i = 0; i < num_fields; i++) {
6418 field = fields[i];
6419 switch (vmcs_field_type(field)) {
6420 case VMCS_FIELD_TYPE_U16:
6421 field_value = vmcs_read16(field);
6422 break;
6423 case VMCS_FIELD_TYPE_U32:
6424 field_value = vmcs_read32(field);
6425 break;
6426 case VMCS_FIELD_TYPE_U64:
6427 field_value = vmcs_read64(field);
6428 break;
6429 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6430 field_value = vmcs_readl(field);
6431 break;
6432 }
6433 vmcs12_write_any(&vmx->vcpu, field, field_value);
6434 }
6435
6436 vmcs_clear(shadow_vmcs);
6437 vmcs_load(vmx->loaded_vmcs->vmcs);
6438}
6439
c3114420
AG		 6440static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6441{
c2bae893
MK		 6442 const unsigned long *fields[] = {
6443 shadow_read_write_fields,
6444 shadow_read_only_fields
c3114420 6445 };
c2bae893 6446 const int max_fields[] = {
c3114420
AG		 6447 max_shadow_read_write_fields,
6448 max_shadow_read_only_fields
6449 };
6450 int i, q;
6451 unsigned long field;
6452 u64 field_value = 0;
6453 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6454
6455 vmcs_load(shadow_vmcs);
6456
c2bae893 6457 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6458 for (i = 0; i < max_fields[q]; i++) {
6459 field = fields[q][i];
6460 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6461
6462 switch (vmcs_field_type(field)) {
6463 case VMCS_FIELD_TYPE_U16:
6464 vmcs_write16(field, (u16)field_value);
6465 break;
6466 case VMCS_FIELD_TYPE_U32:
6467 vmcs_write32(field, (u32)field_value);
6468 break;
6469 case VMCS_FIELD_TYPE_U64:
6470 vmcs_write64(field, (u64)field_value);
6471 break;
6472 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6473 vmcs_writel(field, (long)field_value);
6474 break;
6475 }
6476 }
6477 }
6478
6479 vmcs_clear(shadow_vmcs);
6480 vmcs_load(vmx->loaded_vmcs->vmcs);
6481}
6482
49f705c5
NHE		 6483/*
6484 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6485 * used before) all generate the same failure when it is missing.
6486 */
6487static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6488{
6489 struct vcpu_vmx *vmx = to_vmx(vcpu);
6490 if (vmx->nested.current_vmptr == -1ull) {
6491 nested_vmx_failInvalid(vcpu);
6492 skip_emulated_instruction(vcpu);
6493 return 0;
6494 }
6495 return 1;
6496}
6497
6498static int handle_vmread(struct kvm_vcpu *vcpu)
6499{
6500 unsigned long field;
6501 u64 field_value;
6502 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6503 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6504 gva_t gva = 0;
6505
6506 if (!nested_vmx_check_permission(vcpu) ||
6507 !nested_vmx_check_vmcs12(vcpu))
6508 return 1;
6509
6510 /* Decode instruction info and find the field to read */
27e6fb5d 6511 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6512 /* Read the field, zero-extended to a u64 field_value */
6513 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6514 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6515 skip_emulated_instruction(vcpu);
6516 return 1;
6517 }
6518 /*
6519 * Now copy part of this value to register or memory, as requested.
6520 * Note that the number of bits actually copied is 32 or 64 depending
6521 * on the guest's mode (32 or 64 bit), not on the given field's length.
6522 */
6523 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6524 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6525 field_value);
6526 } else {
6527 if (get_vmx_mem_address(vcpu, exit_qualification,
6528 vmx_instruction_info, &gva))
6529 return 1;
6530 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6531 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6532 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6533 }
6534
6535 nested_vmx_succeed(vcpu);
6536 skip_emulated_instruction(vcpu);
6537 return 1;
6538}
6539
6540
6541static int handle_vmwrite(struct kvm_vcpu *vcpu)
6542{
6543 unsigned long field;
6544 gva_t gva;
6545 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6546 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6547 /* The value to write might be 32 or 64 bits, depending on L1's long
6548 * mode, and eventually we need to write that into a field of several
6549 * possible lengths. The code below first zero-extends the value to 64
6550 * bit (field_value), and then copies only the approriate number of
6551 * bits into the vmcs12 field.
6552 */
6553 u64 field_value = 0;
6554 struct x86_exception e;
6555
6556 if (!nested_vmx_check_permission(vcpu) ||
6557 !nested_vmx_check_vmcs12(vcpu))
6558 return 1;
6559
6560 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6561 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6562 (((vmx_instruction_info) >> 3) & 0xf));
6563 else {
6564 if (get_vmx_mem_address(vcpu, exit_qualification,
6565 vmx_instruction_info, &gva))
6566 return 1;
6567 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6568 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6569 kvm_inject_page_fault(vcpu, &e);
6570 return 1;
6571 }
6572 }
6573
6574
27e6fb5d 6575 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6576 if (vmcs_field_readonly(field)) {
6577 nested_vmx_failValid(vcpu,
6578 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6579 skip_emulated_instruction(vcpu);
6580 return 1;
6581 }
6582
20b97fea 6583 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6584 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6585 skip_emulated_instruction(vcpu);
6586 return 1;
6587 }
6588
6589 nested_vmx_succeed(vcpu);
6590 skip_emulated_instruction(vcpu);
6591 return 1;
6592}
6593
63846663
NHE		 6594/* Emulate the VMPTRLD instruction */
6595static int handle_vmptrld(struct kvm_vcpu *vcpu)
6596{
6597 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6598 gpa_t vmptr;
8a1b9dd0 6599 u32 exec_control;
63846663
NHE		 6600
6601 if (!nested_vmx_check_permission(vcpu))
6602 return 1;
6603
4291b588 6604 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6605 return 1;
63846663
NHE		 6606
6607 if (vmx->nested.current_vmptr != vmptr) {
6608 struct vmcs12 *new_vmcs12;
6609 struct page *page;
6610 page = nested_get_page(vcpu, vmptr);
6611 if (page == NULL) {
6612 nested_vmx_failInvalid(vcpu);
6613 skip_emulated_instruction(vcpu);
6614 return 1;
6615 }
6616 new_vmcs12 = kmap(page);
6617 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6618 kunmap(page);
6619 nested_release_page_clean(page);
6620 nested_vmx_failValid(vcpu,
6621 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6622 skip_emulated_instruction(vcpu);
6623 return 1;
6624 }
63846663 6625
9a2a05b9 6626 nested_release_vmcs12(vmx);
63846663
NHE		 6627 vmx->nested.current_vmptr = vmptr;
6628 vmx->nested.current_vmcs12 = new_vmcs12;
6629 vmx->nested.current_vmcs12_page = page;
012f83cb 6630 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6631 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6632 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6633 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6634 vmcs_write64(VMCS_LINK_POINTER,
6635 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6636 vmx->nested.sync_shadow_vmcs = true;
6637 }
63846663
NHE		 6638 }
6639
6640 nested_vmx_succeed(vcpu);
6641 skip_emulated_instruction(vcpu);
6642 return 1;
6643}
6644
6a4d7550
NHE		 6645/* Emulate the VMPTRST instruction */
6646static int handle_vmptrst(struct kvm_vcpu *vcpu)
6647{
6648 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6649 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6650 gva_t vmcs_gva;
6651 struct x86_exception e;
6652
6653 if (!nested_vmx_check_permission(vcpu))
6654 return 1;
6655
6656 if (get_vmx_mem_address(vcpu, exit_qualification,
6657 vmx_instruction_info, &vmcs_gva))
6658 return 1;
6659 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6660 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6661 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6662 sizeof(u64), &e)) {
6663 kvm_inject_page_fault(vcpu, &e);
6664 return 1;
6665 }
6666 nested_vmx_succeed(vcpu);
6667 skip_emulated_instruction(vcpu);
6668 return 1;
6669}
6670
bfd0a56b
NHE		 6671/* Emulate the INVEPT instruction */
6672static int handle_invept(struct kvm_vcpu *vcpu)
6673{
6674 u32 vmx_instruction_info, types;
6675 unsigned long type;
6676 gva_t gva;
6677 struct x86_exception e;
6678 struct {
6679 u64 eptp, gpa;
6680 } operand;
bfd0a56b
NHE		 6681
6682 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6683 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6684 kvm_queue_exception(vcpu, UD_VECTOR);
6685 return 1;
6686 }
6687
6688 if (!nested_vmx_check_permission(vcpu))
6689 return 1;
6690
6691 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6692 kvm_queue_exception(vcpu, UD_VECTOR);
6693 return 1;
6694 }
6695
6696 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6697 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6698
6699 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6700
6701 if (!(types & (1UL << type))) {
6702 nested_vmx_failValid(vcpu,
6703 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6704 return 1;
6705 }
6706
6707 /* According to the Intel VMX instruction reference, the memory
6708 * operand is read even if it isn't needed (e.g., for type==global)
6709 */
6710 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6711 vmx_instruction_info, &gva))
6712 return 1;
6713 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6714 sizeof(operand), &e)) {
6715 kvm_inject_page_fault(vcpu, &e);
6716 return 1;
6717 }
6718
6719 switch (type) {
bfd0a56b
NHE		 6720 case VMX_EPT_EXTENT_GLOBAL:
6721 kvm_mmu_sync_roots(vcpu);
77c3913b 6722 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6723 nested_vmx_succeed(vcpu);
6724 break;
6725 default:
4b855078 6726 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6727 BUG_ON(1);
6728 break;
6729 }
6730
6731 skip_emulated_instruction(vcpu);
6732 return 1;
6733}
6734
6aa8b732
AK		 6735/*
6736 * The exit handlers return 1 if the exit was handled fully and guest execution
6737 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6738 * to be done to userspace and return 0.
6739 */
772e0318 6740static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6741 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6742 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6743 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6744 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6745 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6746 [EXIT_REASON_CR_ACCESS] = handle_cr,
6747 [EXIT_REASON_DR_ACCESS] = handle_dr,
6748 [EXIT_REASON_CPUID] = handle_cpuid,
6749 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6750 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6751 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6752 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6753 [EXIT_REASON_INVD] = handle_invd,
a7052897 6754 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6755 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6756 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6757 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6758 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6759 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6760 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6761 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6762 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6763 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6764 [EXIT_REASON_VMOFF] = handle_vmoff,
6765 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6766 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6767 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6768 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6769 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6770 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6771 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6772 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6773 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6774 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6775 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6776 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6777 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6778 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6779 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6780};
6781
6782static const int kvm_vmx_max_exit_handlers =
50a3485c 6783 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6784
908a7bdd
JK		 6785static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6786 struct vmcs12 *vmcs12)
6787{
6788 unsigned long exit_qualification;
6789 gpa_t bitmap, last_bitmap;
6790 unsigned int port;
6791 int size;
6792 u8 b;
6793
908a7bdd 6794 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6795 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6796
6797 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6798
6799 port = exit_qualification >> 16;
6800 size = (exit_qualification & 7) + 1;
6801
6802 last_bitmap = (gpa_t)-1;
6803 b = -1;
6804
6805 while (size > 0) {
6806 if (port < 0x8000)
6807 bitmap = vmcs12->io_bitmap_a;
6808 else if (port < 0x10000)
6809 bitmap = vmcs12->io_bitmap_b;
6810 else
6811 return 1;
6812 bitmap += (port & 0x7fff) / 8;
6813
6814 if (last_bitmap != bitmap)
6815 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6816 return 1;
6817 if (b & (1 << (port & 7)))
6818 return 1;
6819
6820 port++;
6821 size--;
6822 last_bitmap = bitmap;
6823 }
6824
6825 return 0;
6826}
6827
644d711a
NHE		 6828/*
6829 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6830 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6831 * disinterest in the current event (read or write a specific MSR) by using an
6832 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6833 */
6834static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6835 struct vmcs12 *vmcs12, u32 exit_reason)
6836{
6837 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6838 gpa_t bitmap;
6839
cbd29cb6 6840 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6841 return 1;
6842
6843 /*
6844 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6845 * for the four combinations of read/write and low/high MSR numbers.
6846 * First we need to figure out which of the four to use:
6847 */
6848 bitmap = vmcs12->msr_bitmap;
6849 if (exit_reason == EXIT_REASON_MSR_WRITE)
6850 bitmap += 2048;
6851 if (msr_index >= 0xc0000000) {
6852 msr_index -= 0xc0000000;
6853 bitmap += 1024;
6854 }
6855
6856 /* Then read the msr_index'th bit from this bitmap: */
6857 if (msr_index < 1024*8) {
6858 unsigned char b;
bd31a7f5
JK		 6859 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6860 return 1;
644d711a
NHE		 6861 return 1 & (b >> (msr_index & 7));
6862 } else
6863 return 1; /* let L1 handle the wrong parameter */
6864}
6865
6866/*
6867 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6868 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6869 * intercept (via guest_host_mask etc.) the current event.
6870 */
6871static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6872 struct vmcs12 *vmcs12)
6873{
6874 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6875 int cr = exit_qualification & 15;
6876 int reg = (exit_qualification >> 8) & 15;
1e32c079 6877 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6878
6879 switch ((exit_qualification >> 4) & 3) {
6880 case 0: /* mov to cr */
6881 switch (cr) {
6882 case 0:
6883 if (vmcs12->cr0_guest_host_mask &
6884 (val ^ vmcs12->cr0_read_shadow))
6885 return 1;
6886 break;
6887 case 3:
6888 if ((vmcs12->cr3_target_count >= 1 &&
6889 vmcs12->cr3_target_value0 == val) ||
6890 (vmcs12->cr3_target_count >= 2 &&
6891 vmcs12->cr3_target_value1 == val) ||
6892 (vmcs12->cr3_target_count >= 3 &&
6893 vmcs12->cr3_target_value2 == val) ||
6894 (vmcs12->cr3_target_count >= 4 &&
6895 vmcs12->cr3_target_value3 == val))
6896 return 0;
6897 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6898 return 1;
6899 break;
6900 case 4:
6901 if (vmcs12->cr4_guest_host_mask &
6902 (vmcs12->cr4_read_shadow ^ val))
6903 return 1;
6904 break;
6905 case 8:
6906 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6907 return 1;
6908 break;
6909 }
6910 break;
6911 case 2: /* clts */
6912 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6913 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6914 return 1;
6915 break;
6916 case 1: /* mov from cr */
6917 switch (cr) {
6918 case 3:
6919 if (vmcs12->cpu_based_vm_exec_control &
6920 CPU_BASED_CR3_STORE_EXITING)
6921 return 1;
6922 break;
6923 case 8:
6924 if (vmcs12->cpu_based_vm_exec_control &
6925 CPU_BASED_CR8_STORE_EXITING)
6926 return 1;
6927 break;
6928 }
6929 break;
6930 case 3: /* lmsw */
6931 /*
6932 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6933 * cr0. Other attempted changes are ignored, with no exit.
6934 */
6935 if (vmcs12->cr0_guest_host_mask & 0xe &
6936 (val ^ vmcs12->cr0_read_shadow))
6937 return 1;
6938 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6939 !(vmcs12->cr0_read_shadow & 0x1) &&
6940 (val & 0x1))
6941 return 1;
6942 break;
6943 }
6944 return 0;
6945}
6946
6947/*
6948 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6949 * should handle it ourselves in L0 (and then continue L2). Only call this
6950 * when in is_guest_mode (L2).
6951 */
6952static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6953{
644d711a
NHE		 6954 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6955 struct vcpu_vmx *vmx = to_vmx(vcpu);
6956 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6957 u32 exit_reason = vmx->exit_reason;
644d711a 6958
542060ea
JK		 6959 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6960 vmcs_readl(EXIT_QUALIFICATION),
6961 vmx->idt_vectoring_info,
6962 intr_info,
6963 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6964 KVM_ISA_VMX);
6965
644d711a
NHE		 6966 if (vmx->nested.nested_run_pending)
6967 return 0;
6968
6969 if (unlikely(vmx->fail)) {
bd80158a
JK		 6970 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6971 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6972 return 1;
6973 }
6974
6975 switch (exit_reason) {
6976 case EXIT_REASON_EXCEPTION_NMI:
6977 if (!is_exception(intr_info))
6978 return 0;
6979 else if (is_page_fault(intr_info))
6980 return enable_ept;
e504c909 6981 else if (is_no_device(intr_info) &&
ccf9844e 6982 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6983 return 0;
644d711a
NHE		 6984 return vmcs12->exception_bitmap &
6985 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6986 case EXIT_REASON_EXTERNAL_INTERRUPT:
6987 return 0;
6988 case EXIT_REASON_TRIPLE_FAULT:
6989 return 1;
6990 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6991 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6992 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6993 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6994 case EXIT_REASON_TASK_SWITCH:
6995 return 1;
6996 case EXIT_REASON_CPUID:
bc613494
MT		 6997 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
6998 return 0;
644d711a
NHE		 6999 return 1;
7000 case EXIT_REASON_HLT:
7001 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7002 case EXIT_REASON_INVD:
7003 return 1;
7004 case EXIT_REASON_INVLPG:
7005 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7006 case EXIT_REASON_RDPMC:
7007 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7008 case EXIT_REASON_RDTSC:
7009 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7010 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7011 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7012 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7013 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7014 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 7015 case EXIT_REASON_INVEPT:
644d711a
NHE		 7016 /*
7017 * VMX instructions trap unconditionally. This allows L1 to
7018 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7019 */
7020 return 1;
7021 case EXIT_REASON_CR_ACCESS:
7022 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7023 case EXIT_REASON_DR_ACCESS:
7024 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7025 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7026 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7027 case EXIT_REASON_MSR_READ:
7028 case EXIT_REASON_MSR_WRITE:
7029 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7030 case EXIT_REASON_INVALID_STATE:
7031 return 1;
7032 case EXIT_REASON_MWAIT_INSTRUCTION:
7033 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7034 case EXIT_REASON_MONITOR_INSTRUCTION:
7035 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7036 case EXIT_REASON_PAUSE_INSTRUCTION:
7037 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7038 nested_cpu_has2(vmcs12,
7039 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7040 case EXIT_REASON_MCE_DURING_VMENTRY:
7041 return 0;
7042 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7043 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7044 case EXIT_REASON_APIC_ACCESS:
7045 return nested_cpu_has2(vmcs12,
7046 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7047 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7048 /*
7049 * L0 always deals with the EPT violation. If nested EPT is
7050 * used, and the nested mmu code discovers that the address is
7051 * missing in the guest EPT table (EPT12), the EPT violation
7052 * will be injected with nested_ept_inject_page_fault()
7053 */
7054 return 0;
644d711a 7055 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7056 /*
7057 * L2 never uses directly L1's EPT, but rather L0's own EPT
7058 * table (shadow on EPT) or a merged EPT table that L0 built
7059 * (EPT on EPT). So any problems with the structure of the
7060 * table is L0's fault.
7061 */
644d711a
NHE		 7062 return 0;
7063 case EXIT_REASON_WBINVD:
7064 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7065 case EXIT_REASON_XSETBV:
7066 return 1;
7067 default:
7068 return 1;
7069 }
7070}
7071
586f9607
AK		 7072static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7073{
7074 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7075 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7076}
7077
6aa8b732
AK		 7078/*
7079 * The guest has exited. See if we can fix it or if we need userspace
7080 * assistance.
7081 */
851ba692 7082static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7083{
29bd8a78 7084 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7085 u32 exit_reason = vmx->exit_reason;
1155f76a 7086 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7087
80ced186 7088 /* If guest state is invalid, start emulating */
14168786 7089 if (vmx->emulation_required)
80ced186 7090 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7091
644d711a 7092 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7093 nested_vmx_vmexit(vcpu, exit_reason,
7094 vmcs_read32(VM_EXIT_INTR_INFO),
7095 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7096 return 1;
7097 }
7098
5120702e
MG		 7099 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7100 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7101 vcpu->run->fail_entry.hardware_entry_failure_reason
7102 = exit_reason;
7103 return 0;
7104 }
7105
29bd8a78 7106 if (unlikely(vmx->fail)) {
851ba692
AK		 7107 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7108 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7109 = vmcs_read32(VM_INSTRUCTION_ERROR);
7110 return 0;
7111 }
6aa8b732 7112
b9bf6882
XG		 7113 /*
7114 * Note:
7115 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7116 * delivery event since it indicates guest is accessing MMIO.
7117 * The vm-exit can be triggered again after return to guest that
7118 * will cause infinite loop.
7119 */
d77c26fc 7120 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7121 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7122 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7123 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7124 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7125 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7126 vcpu->run->internal.ndata = 2;
7127 vcpu->run->internal.data[0] = vectoring_info;
7128 vcpu->run->internal.data[1] = exit_reason;
7129 return 0;
7130 }
3b86cd99 7131
644d711a
NHE		 7132 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7133 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7134 get_vmcs12(vcpu))))) {
c4282df9 7135 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7136 vmx->soft_vnmi_blocked = 0;
3b86cd99 7137 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7138 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7139 /*
7140 * This CPU don't support us in finding the end of an
7141 * NMI-blocked window if the guest runs with IRQs
7142 * disabled. So we pull the trigger after 1 s of
7143 * futile waiting, but inform the user about this.
7144 */
7145 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7146 "state on VCPU %d after 1 s timeout\n",
7147 __func__, vcpu->vcpu_id);
7148 vmx->soft_vnmi_blocked = 0;
3b86cd99 7149 }
3b86cd99
JK		 7150 }
7151
6aa8b732
AK		 7152 if (exit_reason < kvm_vmx_max_exit_handlers
7153 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7154 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7155 else {
851ba692
AK		 7156 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7157 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7158 }
7159 return 0;
7160}
7161
95ba8273 7162static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7163{
a7c0b07d
WL		 7164 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7165
7166 if (is_guest_mode(vcpu) &&
7167 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7168 return;
7169
95ba8273 7170 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7171 vmcs_write32(TPR_THRESHOLD, 0);
7172 return;
7173 }
7174
95ba8273 7175 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7176}
7177
8d14695f
YZ		 7178static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7179{
7180 u32 sec_exec_control;
7181
7182 /*
7183 * There is not point to enable virtualize x2apic without enable
7184 * apicv
7185 */
c7c9c56c
YZ		 7186 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7187 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7188 return;
7189
7190 if (!vm_need_tpr_shadow(vcpu->kvm))
7191 return;
7192
7193 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7194
7195 if (set) {
7196 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7197 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7198 } else {
7199 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7200 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7201 }
7202 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7203
7204 vmx_set_msr_bitmap(vcpu);
7205}
7206
38b99173
TC		 7207static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7208{
7209 struct vcpu_vmx *vmx = to_vmx(vcpu);
7210
7211 /*
7212 * Currently we do not handle the nested case where L2 has an
7213 * APIC access page of its own; that page is still pinned.
7214 * Hence, we skip the case where the VCPU is in guest mode _and_
7215 * L1 prepared an APIC access page for L2.
7216 *
7217 * For the case where L1 and L2 share the same APIC access page
7218 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7219 * in the vmcs12), this function will only update either the vmcs01
7220 * or the vmcs02. If the former, the vmcs02 will be updated by
7221 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7222 * the next L2->L1 exit.
7223 */
7224 if (!is_guest_mode(vcpu) ||
7225 !nested_cpu_has2(vmx->nested.current_vmcs12,
7226 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7227 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7228}
7229
c7c9c56c
YZ		 7230static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7231{
7232 u16 status;
7233 u8 old;
7234
7235 if (!vmx_vm_has_apicv(kvm))
7236 return;
7237
7238 if (isr == -1)
7239 isr = 0;
7240
7241 status = vmcs_read16(GUEST_INTR_STATUS);
7242 old = status >> 8;
7243 if (isr != old) {
7244 status &= 0xff;
7245 status |= isr << 8;
7246 vmcs_write16(GUEST_INTR_STATUS, status);
7247 }
7248}
7249
7250static void vmx_set_rvi(int vector)
7251{
7252 u16 status;
7253 u8 old;
7254
7255 status = vmcs_read16(GUEST_INTR_STATUS);
7256 old = (u8)status & 0xff;
7257 if ((u8)vector != old) {
7258 status &= ~0xff;
7259 status |= (u8)vector;
7260 vmcs_write16(GUEST_INTR_STATUS, status);
7261 }
7262}
7263
7264static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7265{
7266 if (max_irr == -1)
7267 return;
7268
963fee16
WL		 7269 /*
7270 * If a vmexit is needed, vmx_check_nested_events handles it.
7271 */
7272 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7273 return;
7274
7275 if (!is_guest_mode(vcpu)) {
7276 vmx_set_rvi(max_irr);
7277 return;
7278 }
7279
7280 /*
7281 * Fall back to pre-APICv interrupt injection since L2
7282 * is run without virtual interrupt delivery.
7283 */
7284 if (!kvm_event_needs_reinjection(vcpu) &&
7285 vmx_interrupt_allowed(vcpu)) {
7286 kvm_queue_interrupt(vcpu, max_irr, false);
7287 vmx_inject_irq(vcpu);
7288 }
c7c9c56c
YZ		 7289}
7290
7291static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7292{
3d81bc7e
YZ		 7293 if (!vmx_vm_has_apicv(vcpu->kvm))
7294 return;
7295
c7c9c56c
YZ		 7296 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7297 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7298 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7299 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7300}
7301
51aa01d1 7302static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7303{
00eba012
AK		 7304 u32 exit_intr_info;
7305
7306 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7307 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7308 return;
7309
c5ca8e57 7310 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7311 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7312
7313 /* Handle machine checks before interrupts are enabled */
00eba012 7314 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7315 kvm_machine_check();
7316
20f65983 7317 /* We need to handle NMIs before interrupts are enabled */
00eba012 7318 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7319 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7320 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7321 asm("int $2");
ff9d07a0
ZY		 7322 kvm_after_handle_nmi(&vmx->vcpu);
7323 }
51aa01d1 7324}
20f65983 7325
a547c6db
YZ		 7326static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7327{
7328 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7329
7330 /*
7331 * If external interrupt exists, IF bit is set in rflags/eflags on the
7332 * interrupt stack frame, and interrupt will be enabled on a return
7333 * from interrupt handler.
7334 */
7335 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7336 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7337 unsigned int vector;
7338 unsigned long entry;
7339 gate_desc *desc;
7340 struct vcpu_vmx *vmx = to_vmx(vcpu);
7341#ifdef CONFIG_X86_64
7342 unsigned long tmp;
7343#endif
7344
7345 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7346 desc = (gate_desc *)vmx->host_idt_base + vector;
7347 entry = gate_offset(*desc);
7348 asm volatile(
7349#ifdef CONFIG_X86_64
7350 "mov %%" _ASM_SP ", %[sp]\n\t"
7351 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7352 "push $%c[ss]\n\t"
7353 "push %[sp]\n\t"
7354#endif
7355 "pushf\n\t"
7356 "orl $0x200, (%%" _ASM_SP ")\n\t"
7357 __ASM_SIZE(push) " $%c[cs]\n\t"
7358 "call *%[entry]\n\t"
7359 :
7360#ifdef CONFIG_X86_64
7361 [sp]"=&r"(tmp)
7362#endif
7363 :
7364 [entry]"r"(entry),
7365 [ss]"i"(__KERNEL_DS),
7366 [cs]"i"(__KERNEL_CS)
7367 );
7368 } else
7369 local_irq_enable();
7370}
7371
da8999d3
LJ		 7372static bool vmx_mpx_supported(void)
7373{
7374 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7375 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7376}
7377
51aa01d1
AK		 7378static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7379{
c5ca8e57 7380 u32 exit_intr_info;
51aa01d1
AK		 7381 bool unblock_nmi;
7382 u8 vector;
7383 bool idtv_info_valid;
7384
7385 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7386
cf393f75 7387 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7388 if (vmx->nmi_known_unmasked)
7389 return;
c5ca8e57
AK		 7390 /*
7391 * Can't use vmx->exit_intr_info since we're not sure what
7392 * the exit reason is.
7393 */
7394 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7395 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7396 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7397 /*
7b4a25cb 7398 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7399 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7400 * a guest IRET fault.
7b4a25cb
GN		 7401 * SDM 3: 23.2.2 (September 2008)
7402 * Bit 12 is undefined in any of the following cases:
7403 * If the VM exit sets the valid bit in the IDT-vectoring
7404 * information field.
7405 * If the VM exit is due to a double fault.
cf393f75 7406 */
7b4a25cb
GN		 7407 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7408 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7409 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7410 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7411 else
7412 vmx->nmi_known_unmasked =
7413 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7414 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7415 } else if (unlikely(vmx->soft_vnmi_blocked))
7416 vmx->vnmi_blocked_time +=
7417 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7418}
7419
3ab66e8a 7420static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7421 u32 idt_vectoring_info,
7422 int instr_len_field,
7423 int error_code_field)
51aa01d1 7424{
51aa01d1
AK		 7425 u8 vector;
7426 int type;
7427 bool idtv_info_valid;
7428
7429 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7430
3ab66e8a
JK		 7431 vcpu->arch.nmi_injected = false;
7432 kvm_clear_exception_queue(vcpu);
7433 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7434
7435 if (!idtv_info_valid)
7436 return;
7437
3ab66e8a 7438 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7439
668f612f
AK		 7440 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7441 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7442
64a7ec06 7443 switch (type) {
37b96e98 7444 case INTR_TYPE_NMI_INTR:
3ab66e8a 7445 vcpu->arch.nmi_injected = true;
668f612f 7446 /*
7b4a25cb 7447 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7448 * Clear bit "block by NMI" before VM entry if a NMI
7449 * delivery faulted.
668f612f 7450 */
3ab66e8a 7451 vmx_set_nmi_mask(vcpu, false);
37b96e98 7452 break;
37b96e98 7453 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7454 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7455 /* fall through */
7456 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7457 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7458 u32 err = vmcs_read32(error_code_field);
851eb667 7459 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7460 } else
851eb667 7461 kvm_requeue_exception(vcpu, vector);
37b96e98 7462 break;
66fd3f7f 7463 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7464 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7465 /* fall through */
37b96e98 7466 case INTR_TYPE_EXT_INTR:
3ab66e8a 7467 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7468 break;
7469 default:
7470 break;
f7d9238f 7471 }
cf393f75
AK		 7472}
7473
83422e17
AK		 7474static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7475{
3ab66e8a 7476 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7477 VM_EXIT_INSTRUCTION_LEN,
7478 IDT_VECTORING_ERROR_CODE);
7479}
7480
b463a6f7
AK		 7481static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7482{
3ab66e8a 7483 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7484 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7485 VM_ENTRY_INSTRUCTION_LEN,
7486 VM_ENTRY_EXCEPTION_ERROR_CODE);
7487
7488 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7489}
7490
d7cd9796
GN		 7491static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7492{
7493 int i, nr_msrs;
7494 struct perf_guest_switch_msr *msrs;
7495
7496 msrs = perf_guest_get_msrs(&nr_msrs);
7497
7498 if (!msrs)
7499 return;
7500
7501 for (i = 0; i < nr_msrs; i++)
7502 if (msrs[i].host == msrs[i].guest)
7503 clear_atomic_switch_msr(vmx, msrs[i].msr);
7504 else
7505 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7506 msrs[i].host);
7507}
7508
a3b5ba49 7509static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7510{
a2fa3e9f 7511 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7512 unsigned long debugctlmsr;
104f226b
AK		 7513
7514 /* Record the guest's net vcpu time for enforced NMI injections. */
7515 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7516 vmx->entry_time = ktime_get();
7517
7518 /* Don't enter VMX if guest state is invalid, let the exit handler
7519 start emulation until we arrive back to a valid state */
14168786 7520 if (vmx->emulation_required)
104f226b
AK		 7521 return;
7522
a7653ecd
RK		 7523 if (vmx->ple_window_dirty) {
7524 vmx->ple_window_dirty = false;
7525 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7526 }
7527
012f83cb
AG		 7528 if (vmx->nested.sync_shadow_vmcs) {
7529 copy_vmcs12_to_shadow(vmx);
7530 vmx->nested.sync_shadow_vmcs = false;
7531 }
7532
104f226b
AK		 7533 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7534 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7535 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7536 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7537
7538 /* When single-stepping over STI and MOV SS, we must clear the
7539 * corresponding interruptibility bits in the guest state. Otherwise
7540 * vmentry fails as it then expects bit 14 (BS) in pending debug
7541 * exceptions being set, but that's not correct for the guest debugging
7542 * case. */
7543 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7544 vmx_set_interrupt_shadow(vcpu, 0);
7545
d7cd9796 7546 atomic_switch_perf_msrs(vmx);
2a7921b7 7547 debugctlmsr = get_debugctlmsr();
d7cd9796 7548
d462b819 7549 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7550 asm(
6aa8b732 7551 /* Store host registers */
b188c81f
AK		 7552 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7553 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7554 "push %%" _ASM_CX " \n\t"
7555 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7556 "je 1f \n\t"
b188c81f 7557 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7558 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7559 "1: \n\t"
d3edefc0 7560 /* Reload cr2 if changed */
b188c81f
AK		 7561 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7562 "mov %%cr2, %%" _ASM_DX " \n\t"
7563 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7564 "je 2f \n\t"
b188c81f 7565 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7566 "2: \n\t"
6aa8b732 7567 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7568 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7569 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7570 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7571 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7572 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7573 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7574 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7575 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7576#ifdef CONFIG_X86_64
e08aa78a
AK		 7577 "mov %c[r8](%0), %%r8 \n\t"
7578 "mov %c[r9](%0), %%r9 \n\t"
7579 "mov %c[r10](%0), %%r10 \n\t"
7580 "mov %c[r11](%0), %%r11 \n\t"
7581 "mov %c[r12](%0), %%r12 \n\t"
7582 "mov %c[r13](%0), %%r13 \n\t"
7583 "mov %c[r14](%0), %%r14 \n\t"
7584 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7585#endif
b188c81f 7586 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7587
6aa8b732 7588 /* Enter guest mode */
83287ea4 7589 "jne 1f \n\t"
4ecac3fd 7590 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7591 "jmp 2f \n\t"
7592 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7593 "2: "
6aa8b732 7594 /* Save guest registers, load host registers, keep flags */
b188c81f 7595 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7596 "pop %0 \n\t"
b188c81f
AK		 7597 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7598 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7599 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7600 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7601 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7602 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7603 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7604#ifdef CONFIG_X86_64
e08aa78a
AK		 7605 "mov %%r8, %c[r8](%0) \n\t"
7606 "mov %%r9, %c[r9](%0) \n\t"
7607 "mov %%r10, %c[r10](%0) \n\t"
7608 "mov %%r11, %c[r11](%0) \n\t"
7609 "mov %%r12, %c[r12](%0) \n\t"
7610 "mov %%r13, %c[r13](%0) \n\t"
7611 "mov %%r14, %c[r14](%0) \n\t"
7612 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7613#endif
b188c81f
AK		 7614 "mov %%cr2, %%" _ASM_AX " \n\t"
7615 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7616
b188c81f 7617 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7618 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7619 ".pushsection .rodata \n\t"
7620 ".global vmx_return \n\t"
7621 "vmx_return: " _ASM_PTR " 2b \n\t"
7622 ".popsection"
e08aa78a 7623 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7624 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7625 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7626 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7627 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7628 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7629 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7630 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7631 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7632 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7633 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7634#ifdef CONFIG_X86_64
ad312c7c
ZX		 7635 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7636 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7637 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7638 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7639 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7640 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7641 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7642 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7643#endif
40712fae
AK		 7644 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7645 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7646 : "cc", "memory"
7647#ifdef CONFIG_X86_64
b188c81f 7648 , "rax", "rbx", "rdi", "rsi"
c2036300 7649 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7650#else
7651 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7652#endif
7653 );
6aa8b732 7654
2a7921b7
GN		 7655 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7656 if (debugctlmsr)
7657 update_debugctlmsr(debugctlmsr);
7658
aa67f609
AK		 7659#ifndef CONFIG_X86_64
7660 /*
7661 * The sysexit path does not restore ds/es, so we must set them to
7662 * a reasonable value ourselves.
7663 *
7664 * We can't defer this to vmx_load_host_state() since that function
7665 * may be executed in interrupt context, which saves and restore segments
7666 * around it, nullifying its effect.
7667 */
7668 loadsegment(ds, __USER_DS);
7669 loadsegment(es, __USER_DS);
7670#endif
7671
6de4f3ad 7672 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7673 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7674 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7675 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7676 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7677 vcpu->arch.regs_dirty = 0;
7678
1155f76a
AK		 7679 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7680
d462b819 7681 vmx->loaded_vmcs->launched = 1;
1b6269db 7682
51aa01d1 7683 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7684 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7685
e0b890d3
GN		 7686 /*
7687 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7688 * we did not inject a still-pending event to L1 now because of
7689 * nested_run_pending, we need to re-enable this bit.
7690 */
7691 if (vmx->nested.nested_run_pending)
7692 kvm_make_request(KVM_REQ_EVENT, vcpu);
7693
7694 vmx->nested.nested_run_pending = 0;
7695
51aa01d1
AK		 7696 vmx_complete_atomic_exit(vmx);
7697 vmx_recover_nmi_blocking(vmx);
cf393f75 7698 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7699}
7700
4fa7734c
PB		 7701static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7702{
7703 struct vcpu_vmx *vmx = to_vmx(vcpu);
7704 int cpu;
7705
7706 if (vmx->loaded_vmcs == &vmx->vmcs01)
7707 return;
7708
7709 cpu = get_cpu();
7710 vmx->loaded_vmcs = &vmx->vmcs01;
7711 vmx_vcpu_put(vcpu);
7712 vmx_vcpu_load(vcpu, cpu);
7713 vcpu->cpu = cpu;
7714 put_cpu();
7715}
7716
6aa8b732
AK		 7717static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7718{
fb3f0f51
RR		 7719 struct vcpu_vmx *vmx = to_vmx(vcpu);
7720
cdbecfc3 7721 free_vpid(vmx);
4fa7734c
PB		 7722 leave_guest_mode(vcpu);
7723 vmx_load_vmcs01(vcpu);
26a865f4 7724 free_nested(vmx);
4fa7734c 7725 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7726 kfree(vmx->guest_msrs);
7727 kvm_vcpu_uninit(vcpu);
a4770347 7728 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7729}
7730
fb3f0f51 7731static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7732{
fb3f0f51 7733 int err;
c16f862d 7734 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7735 int cpu;
6aa8b732 7736
a2fa3e9f 7737 if (!vmx)
fb3f0f51
RR		 7738 return ERR_PTR(-ENOMEM);
7739
2384d2b3
SY		 7740 allocate_vpid(vmx);
7741
fb3f0f51
RR		 7742 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7743 if (err)
7744 goto free_vcpu;
965b58a5 7745
a2fa3e9f 7746 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7747 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7748 > PAGE_SIZE);
0123be42 7749
be6d05cf 7750 err = -ENOMEM;
fb3f0f51 7751 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7752 goto uninit_vcpu;
7753 }
965b58a5 7754
d462b819
NHE		 7755 vmx->loaded_vmcs = &vmx->vmcs01;
7756 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7757 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7758 goto free_msrs;
d462b819
NHE		 7759 if (!vmm_exclusive)
7760 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7761 loaded_vmcs_init(vmx->loaded_vmcs);
7762 if (!vmm_exclusive)
7763 kvm_cpu_vmxoff();
a2fa3e9f 7764
15ad7146
AK		 7765 cpu = get_cpu();
7766 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7767 vmx->vcpu.cpu = cpu;
8b9cf98c 7768 err = vmx_vcpu_setup(vmx);
fb3f0f51 7769 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7770 put_cpu();
fb3f0f51
RR		 7771 if (err)
7772 goto free_vmcs;
a63cb560 7773 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7774 err = alloc_apic_access_page(kvm);
7775 if (err)
5e4a0b3c 7776 goto free_vmcs;
a63cb560 7777 }
fb3f0f51 7778
b927a3ce
SY		 7779 if (enable_ept) {
7780 if (!kvm->arch.ept_identity_map_addr)
7781 kvm->arch.ept_identity_map_addr =
7782 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7783 err = init_rmode_identity_map(kvm);
7784 if (err)
93ea5388 7785 goto free_vmcs;
b927a3ce 7786 }
b7ebfb05 7787
a9d30f33
NHE		 7788 vmx->nested.current_vmptr = -1ull;
7789 vmx->nested.current_vmcs12 = NULL;
7790
fb3f0f51
RR		 7791 return &vmx->vcpu;
7792
7793free_vmcs:
5f3fbc34 7794 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7795free_msrs:
fb3f0f51
RR		 7796 kfree(vmx->guest_msrs);
7797uninit_vcpu:
7798 kvm_vcpu_uninit(&vmx->vcpu);
7799free_vcpu:
cdbecfc3 7800 free_vpid(vmx);
a4770347 7801 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7802 return ERR_PTR(err);
6aa8b732
AK		 7803}
7804
002c7f7c
YS		 7805static void __init vmx_check_processor_compat(void *rtn)
7806{
7807 struct vmcs_config vmcs_conf;
7808
7809 *(int *)rtn = 0;
7810 if (setup_vmcs_config(&vmcs_conf) < 0)
7811 *(int *)rtn = -EIO;
7812 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7813 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7814 smp_processor_id());
7815 *(int *)rtn = -EIO;
7816 }
7817}
7818
67253af5
SY		 7819static int get_ept_level(void)
7820{
7821 return VMX_EPT_DEFAULT_GAW + 1;
7822}
7823
4b12f0de 7824static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7825{
4b12f0de
SY		 7826 u64 ret;
7827
522c68c4
SY		 7828 /* For VT-d and EPT combination
7829 * 1. MMIO: always map as UC
7830 * 2. EPT with VT-d:
7831 * a. VT-d without snooping control feature: can't guarantee the
7832 * result, try to trust guest.
7833 * b. VT-d with snooping control feature: snooping control feature of
7834 * VT-d engine can guarantee the cache correctness. Just set it
7835 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7836 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7837 * consistent with host MTRR
7838 */
4b12f0de
SY		 7839 if (is_mmio)
7840 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7841 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7842 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7843 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7844 else
522c68c4 7845 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7846 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7847
7848 return ret;
64d4d521
SY		 7849}
7850
17cc3935 7851static int vmx_get_lpage_level(void)
344f414f 7852{
878403b7
SY		 7853 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7854 return PT_DIRECTORY_LEVEL;
7855 else
7856 /* For shadow and EPT supported 1GB page */
7857 return PT_PDPE_LEVEL;
344f414f
JR		 7858}
7859
0e851880
SY		 7860static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7861{
4e47c7a6
SY		 7862 struct kvm_cpuid_entry2 *best;
7863 struct vcpu_vmx *vmx = to_vmx(vcpu);
7864 u32 exec_control;
7865
7866 vmx->rdtscp_enabled = false;
7867 if (vmx_rdtscp_supported()) {
7868 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7869 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7870 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7871 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7872 vmx->rdtscp_enabled = true;
7873 else {
7874 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7875 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7876 exec_control);
7877 }
7878 }
7879 }
ad756a16 7880
ad756a16
MJ		 7881 /* Exposing INVPCID only when PCID is exposed */
7882 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7883 if (vmx_invpcid_supported() &&
4f977045 7884 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7885 guest_cpuid_has_pcid(vcpu)) {
29282fde 7886 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7887 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7888 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7889 exec_control);
7890 } else {
29282fde
TI		 7891 if (cpu_has_secondary_exec_ctrls()) {
7892 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7893 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7894 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7895 exec_control);
7896 }
ad756a16 7897 if (best)
4f977045 7898 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7899 }
0e851880
SY		 7900}
7901
d4330ef2
JR		 7902static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7903{
7b8050f5
NHE		 7904 if (func == 1 && nested)
7905 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7906}
7907
25d92081
YZ		 7908static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7909 struct x86_exception *fault)
7910{
533558bc
JK		 7911 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7912 u32 exit_reason;
25d92081
YZ		 7913
7914 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7915 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7916 else
533558bc
JK		 7917 exit_reason = EXIT_REASON_EPT_VIOLATION;
7918 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7919 vmcs12->guest_physical_address = fault->address;
7920}
7921
155a97a3
NHE		 7922/* Callbacks for nested_ept_init_mmu_context: */
7923
7924static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7925{
7926 /* return the page table to be shadowed - in our case, EPT12 */
7927 return get_vmcs12(vcpu)->ept_pointer;
7928}
7929
8a3c1a33 7930static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7931{
8a3c1a33 7932 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7933 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7934
7935 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7936 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7937 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7938
7939 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7940}
7941
7942static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7943{
7944 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7945}
7946
feaf0c7d
GN		 7947static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7948 struct x86_exception *fault)
7949{
7950 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7951
7952 WARN_ON(!is_guest_mode(vcpu));
7953
7954 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7955 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7956 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7957 vmcs_read32(VM_EXIT_INTR_INFO),
7958 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7959 else
7960 kvm_inject_page_fault(vcpu, fault);
7961}
7962
a2bcba50
WL		 7963static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7964 struct vmcs12 *vmcs12)
7965{
7966 struct vcpu_vmx *vmx = to_vmx(vcpu);
7967
7968 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 7969 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 7970 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 7971 return false;
7972
7973 /*
7974 * Translate L1 physical address to host physical
7975 * address for vmcs02. Keep the page pinned, so this
7976 * physical address remains valid. We keep a reference
7977 * to it so we can release it later.
7978 */
7979 if (vmx->nested.apic_access_page) /* shouldn't happen */
7980 nested_release_page(vmx->nested.apic_access_page);
7981 vmx->nested.apic_access_page =
7982 nested_get_page(vcpu, vmcs12->apic_access_addr);
7983 }
a7c0b07d
WL		 7984
7985 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
7986 /* TODO: Also verify bits beyond physical address width are 0 */
7987 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
7988 return false;
7989
7990 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
7991 nested_release_page(vmx->nested.virtual_apic_page);
7992 vmx->nested.virtual_apic_page =
7993 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
7994
7995 /*
7996 * Failing the vm entry is _not_ what the processor does
7997 * but it's basically the only possibility we have.
7998 * We could still enter the guest if CR8 load exits are
7999 * enabled, CR8 store exits are enabled, and virtualize APIC
8000 * access is disabled; in this case the processor would never
8001 * use the TPR shadow and we could simply clear the bit from
8002 * the execution control. But such a configuration is useless,
8003 * so let's keep the code simple.
8004 */
8005 if (!vmx->nested.virtual_apic_page)
8006 return false;
8007 }
8008
a2bcba50
WL		 8009 return true;
8010}
8011
f4124500
JK		 8012static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8013{
8014 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8015 struct vcpu_vmx *vmx = to_vmx(vcpu);
8016
8017 if (vcpu->arch.virtual_tsc_khz == 0)
8018 return;
8019
8020 /* Make sure short timeouts reliably trigger an immediate vmexit.
8021 * hrtimer_start does not guarantee this. */
8022 if (preemption_timeout <= 1) {
8023 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8024 return;
8025 }
8026
8027 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8028 preemption_timeout *= 1000000;
8029 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8030 hrtimer_start(&vmx->nested.preemption_timer,
8031 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8032}
8033
fe3ef05c
NHE		 8034/*
8035 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8036 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8037 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8038 * guest in a way that will both be appropriate to L1's requests, and our
8039 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8040 * function also has additional necessary side-effects, like setting various
8041 * vcpu->arch fields.
8042 */
8043static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8044{
8045 struct vcpu_vmx *vmx = to_vmx(vcpu);
8046 u32 exec_control;
8047
8048 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8049 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8050 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8051 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8052 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8053 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8054 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8055 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8056 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8057 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8058 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8059 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8060 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8061 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8062 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8063 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8064 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8065 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8066 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8067 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8068 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8069 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8070 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8071 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8072 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8073 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8074 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8075 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8076 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8077 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8078 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8079 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8080 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8081 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8082 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8083 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8084
2996fca0
JK		 8085 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8086 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8087 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8088 } else {
8089 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8090 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8091 }
fe3ef05c
NHE		 8092 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8093 vmcs12->vm_entry_intr_info_field);
8094 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8095 vmcs12->vm_entry_exception_error_code);
8096 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8097 vmcs12->vm_entry_instruction_len);
8098 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8099 vmcs12->guest_interruptibility_info);
fe3ef05c 8100 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8101 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8102 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8103 vmcs12->guest_pending_dbg_exceptions);
8104 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8105 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8106
8107 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8108
f4124500
JK		 8109 exec_control = vmcs12->pin_based_vm_exec_control;
8110 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8111 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8112 PIN_BASED_POSTED_INTR);
f4124500 8113 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8114
f4124500
JK		 8115 vmx->nested.preemption_timer_expired = false;
8116 if (nested_cpu_has_preemption_timer(vmcs12))
8117 vmx_start_preemption_timer(vcpu);
0238ea91 8118
fe3ef05c
NHE		 8119 /*
8120 * Whether page-faults are trapped is determined by a combination of
8121 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8122 * If enable_ept, L0 doesn't care about page faults and we should
8123 * set all of these to L1's desires. However, if !enable_ept, L0 does
8124 * care about (at least some) page faults, and because it is not easy
8125 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8126 * to exit on each and every L2 page fault. This is done by setting
8127 * MASK=MATCH=0 and (see below) EB.PF=1.
8128 * Note that below we don't need special code to set EB.PF beyond the
8129 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8130 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8131 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8132 *
8133 * A problem with this approach (when !enable_ept) is that L1 may be
8134 * injected with more page faults than it asked for. This could have
8135 * caused problems, but in practice existing hypervisors don't care.
8136 * To fix this, we will need to emulate the PFEC checking (on the L1
8137 * page tables), using walk_addr(), when injecting PFs to L1.
8138 */
8139 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8140 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8141 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8142 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8143
8144 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8145 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8146 if (!vmx->rdtscp_enabled)
8147 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8148 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8149 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8150 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8151 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8152 if (nested_cpu_has(vmcs12,
8153 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8154 exec_control |= vmcs12->secondary_vm_exec_control;
8155
8156 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8157 /*
8158 * If translation failed, no matter: This feature asks
8159 * to exit when accessing the given address, and if it
8160 * can never be accessed, this feature won't do
8161 * anything anyway.
8162 */
8163 if (!vmx->nested.apic_access_page)
8164 exec_control &=
8165 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8166 else
8167 vmcs_write64(APIC_ACCESS_ADDR,
8168 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8169 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8170 exec_control |=
8171 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8172 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8173 }
8174
8175 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8176 }
8177
8178
8179 /*
8180 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8181 * Some constant fields are set here by vmx_set_constant_host_state().
8182 * Other fields are different per CPU, and will be set later when
8183 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8184 */
a547c6db 8185 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8186
8187 /*
8188 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8189 * entry, but only if the current (host) sp changed from the value
8190 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8191 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8192 * here we just force the write to happen on entry.
8193 */
8194 vmx->host_rsp = 0;
8195
8196 exec_control = vmx_exec_control(vmx); /* L0's desires */
8197 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8198 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8199 exec_control &= ~CPU_BASED_TPR_SHADOW;
8200 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8201
8202 if (exec_control & CPU_BASED_TPR_SHADOW) {
8203 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8204 page_to_phys(vmx->nested.virtual_apic_page));
8205 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8206 }
8207
fe3ef05c
NHE		 8208 /*
8209 * Merging of IO and MSR bitmaps not currently supported.
8210 * Rather, exit every time.
8211 */
8212 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8213 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8214 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8215
8216 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8217
8218 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8219 * bitwise-or of what L1 wants to trap for L2, and what we want to
8220 * trap. Note that CR0.TS also needs updating - we do this later.
8221 */
8222 update_exception_bitmap(vcpu);
8223 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8224 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8225
8049d651
NHE		 8226 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8227 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8228 * bits are further modified by vmx_set_efer() below.
8229 */
f4124500 8230 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8231
8232 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8233 * emulated by vmx_set_efer(), below.
8234 */
2961e876 8235 vm_entry_controls_init(vmx,
8049d651
NHE		 8236 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8237 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8238 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8239
44811c02 8240 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8241 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8242 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8243 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8244 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8245
8246
8247 set_cr4_guest_host_mask(vmx);
8248
36be0b9d
PB		 8249 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8250 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8251
27fc51b2
NHE		 8252 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8253 vmcs_write64(TSC_OFFSET,
8254 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8255 else
8256 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8257
8258 if (enable_vpid) {
8259 /*
8260 * Trivially support vpid by letting L2s share their parent
8261 * L1's vpid. TODO: move to a more elaborate solution, giving
8262 * each L2 its own vpid and exposing the vpid feature to L1.
8263 */
8264 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8265 vmx_flush_tlb(vcpu);
8266 }
8267
155a97a3
NHE		 8268 if (nested_cpu_has_ept(vmcs12)) {
8269 kvm_mmu_unload(vcpu);
8270 nested_ept_init_mmu_context(vcpu);
8271 }
8272
fe3ef05c
NHE		 8273 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8274 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8275 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8276 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8277 else
8278 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8279 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8280 vmx_set_efer(vcpu, vcpu->arch.efer);
8281
8282 /*
8283 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8284 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8285 * The CR0_READ_SHADOW is what L2 should have expected to read given
8286 * the specifications by L1; It's not enough to take
8287 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8288 * have more bits than L1 expected.
8289 */
8290 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8291 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8292
8293 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8294 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8295
8296 /* shadow page tables on either EPT or shadow page tables */
8297 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8298 kvm_mmu_reset_context(vcpu);
8299
feaf0c7d
GN		 8300 if (!enable_ept)
8301 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8302
3633cfc3
NHE		 8303 /*
8304 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8305 */
8306 if (enable_ept) {
8307 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8308 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8309 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8310 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8311 }
8312
fe3ef05c
NHE		 8313 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8314 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8315}
8316
cd232ad0
NHE		 8317/*
8318 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8319 * for running an L2 nested guest.
8320 */
8321static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8322{
8323 struct vmcs12 *vmcs12;
8324 struct vcpu_vmx *vmx = to_vmx(vcpu);
8325 int cpu;
8326 struct loaded_vmcs *vmcs02;
384bb783 8327 bool ia32e;
cd232ad0
NHE		 8328
8329 if (!nested_vmx_check_permission(vcpu) ||
8330 !nested_vmx_check_vmcs12(vcpu))
8331 return 1;
8332
8333 skip_emulated_instruction(vcpu);
8334 vmcs12 = get_vmcs12(vcpu);
8335
012f83cb
AG		 8336 if (enable_shadow_vmcs)
8337 copy_shadow_to_vmcs12(vmx);
8338
7c177938
NHE		 8339 /*
8340 * The nested entry process starts with enforcing various prerequisites
8341 * on vmcs12 as required by the Intel SDM, and act appropriately when
8342 * they fail: As the SDM explains, some conditions should cause the
8343 * instruction to fail, while others will cause the instruction to seem
8344 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8345 * To speed up the normal (success) code path, we should avoid checking
8346 * for misconfigurations which will anyway be caught by the processor
8347 * when using the merged vmcs02.
8348 */
8349 if (vmcs12->launch_state == launch) {
8350 nested_vmx_failValid(vcpu,
8351 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8352 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8353 return 1;
8354 }
8355
6dfacadd
JK		 8356 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8357 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8358 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8359 return 1;
8360 }
8361
7c177938 8362 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8363 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8364 /*TODO: Also verify bits beyond physical address width are 0*/
8365 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8366 return 1;
8367 }
8368
a2bcba50 8369 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8370 /*TODO: Also verify bits beyond physical address width are 0*/
8371 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8372 return 1;
8373 }
8374
8375 if (vmcs12->vm_entry_msr_load_count > 0 ||
8376 vmcs12->vm_exit_msr_load_count > 0 ||
8377 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8378 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8379 __func__);
7c177938
NHE		 8380 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8381 return 1;
8382 }
8383
8384 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8385 nested_vmx_true_procbased_ctls_low,
8386 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8387 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8388 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8389 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8390 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8391 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8392 nested_vmx_true_exit_ctls_low,
8393 nested_vmx_exit_ctls_high) ||
7c177938 8394 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8395 nested_vmx_true_entry_ctls_low,
8396 nested_vmx_entry_ctls_high))
7c177938
NHE		 8397 {
8398 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8399 return 1;
8400 }
8401
8402 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8403 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8404 nested_vmx_failValid(vcpu,
8405 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8406 return 1;
8407 }
8408
92fbc7b1 8409 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8410 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8411 nested_vmx_entry_failure(vcpu, vmcs12,
8412 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8413 return 1;
8414 }
8415 if (vmcs12->vmcs_link_pointer != -1ull) {
8416 nested_vmx_entry_failure(vcpu, vmcs12,
8417 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8418 return 1;
8419 }
8420
384bb783 8421 /*
cb0c8cda 8422 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8423 * are performed on the field for the IA32_EFER MSR:
8424 * - Bits reserved in the IA32_EFER MSR must be 0.
8425 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8426 * the IA-32e mode guest VM-exit control. It must also be identical
8427 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8428 * CR0.PG) is 1.
8429 */
8430 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8431 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8432 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8433 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8434 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8435 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8436 nested_vmx_entry_failure(vcpu, vmcs12,
8437 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8438 return 1;
8439 }
8440 }
8441
8442 /*
8443 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8444 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8445 * the values of the LMA and LME bits in the field must each be that of
8446 * the host address-space size VM-exit control.
8447 */
8448 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8449 ia32e = (vmcs12->vm_exit_controls &
8450 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8451 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8452 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8453 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8454 nested_vmx_entry_failure(vcpu, vmcs12,
8455 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8456 return 1;
8457 }
8458 }
8459
7c177938
NHE		 8460 /*
8461 * We're finally done with prerequisite checking, and can start with
8462 * the nested entry.
8463 */
8464
cd232ad0
NHE		 8465 vmcs02 = nested_get_current_vmcs02(vmx);
8466 if (!vmcs02)
8467 return -ENOMEM;
8468
8469 enter_guest_mode(vcpu);
8470
8471 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8472
2996fca0
JK		 8473 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8474 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8475
cd232ad0
NHE		 8476 cpu = get_cpu();
8477 vmx->loaded_vmcs = vmcs02;
8478 vmx_vcpu_put(vcpu);
8479 vmx_vcpu_load(vcpu, cpu);
8480 vcpu->cpu = cpu;
8481 put_cpu();
8482
36c3cc42
JK		 8483 vmx_segment_cache_clear(vmx);
8484
cd232ad0
NHE		 8485 vmcs12->launch_state = 1;
8486
8487 prepare_vmcs02(vcpu, vmcs12);
8488
6dfacadd
JK		 8489 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8490 return kvm_emulate_halt(vcpu);
8491
7af40ad3
JK		 8492 vmx->nested.nested_run_pending = 1;
8493
cd232ad0
NHE		 8494 /*
8495 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8496 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8497 * returned as far as L1 is concerned. It will only return (and set
8498 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8499 */
8500 return 1;
8501}
8502
4704d0be
NHE		 8503/*
8504 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8505 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8506 * This function returns the new value we should put in vmcs12.guest_cr0.
8507 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8508 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8509 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8510 * didn't trap the bit, because if L1 did, so would L0).
8511 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8512 * been modified by L2, and L1 knows it. So just leave the old value of
8513 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8514 * isn't relevant, because if L0 traps this bit it can set it to anything.
8515 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8516 * changed these bits, and therefore they need to be updated, but L0
8517 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8518 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8519 */
8520static inline unsigned long
8521vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8522{
8523 return
8524 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8525 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8526 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8527 vcpu->arch.cr0_guest_owned_bits));
8528}
8529
8530static inline unsigned long
8531vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8532{
8533 return
8534 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8535 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8536 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8537 vcpu->arch.cr4_guest_owned_bits));
8538}
8539
5f3d5799
JK		 8540static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8541 struct vmcs12 *vmcs12)
8542{
8543 u32 idt_vectoring;
8544 unsigned int nr;
8545
851eb667 8546 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8547 nr = vcpu->arch.exception.nr;
8548 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8549
8550 if (kvm_exception_is_soft(nr)) {
8551 vmcs12->vm_exit_instruction_len =
8552 vcpu->arch.event_exit_inst_len;
8553 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8554 } else
8555 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8556
8557 if (vcpu->arch.exception.has_error_code) {
8558 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8559 vmcs12->idt_vectoring_error_code =
8560 vcpu->arch.exception.error_code;
8561 }
8562
8563 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8564 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8565 vmcs12->idt_vectoring_info_field =
8566 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8567 } else if (vcpu->arch.interrupt.pending) {
8568 nr = vcpu->arch.interrupt.nr;
8569 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8570
8571 if (vcpu->arch.interrupt.soft) {
8572 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8573 vmcs12->vm_entry_instruction_len =
8574 vcpu->arch.event_exit_inst_len;
8575 } else
8576 idt_vectoring |= INTR_TYPE_EXT_INTR;
8577
8578 vmcs12->idt_vectoring_info_field = idt_vectoring;
8579 }
8580}
8581
b6b8a145
JK		 8582static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8583{
8584 struct vcpu_vmx *vmx = to_vmx(vcpu);
8585
f4124500
JK		 8586 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8587 vmx->nested.preemption_timer_expired) {
8588 if (vmx->nested.nested_run_pending)
8589 return -EBUSY;
8590 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8591 return 0;
8592 }
8593
b6b8a145 8594 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8595 if (vmx->nested.nested_run_pending ||
8596 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8597 return -EBUSY;
8598 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8599 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8600 INTR_INFO_VALID_MASK, 0);
8601 /*
8602 * The NMI-triggered VM exit counts as injection:
8603 * clear this one and block further NMIs.
8604 */
8605 vcpu->arch.nmi_pending = 0;
8606 vmx_set_nmi_mask(vcpu, true);
8607 return 0;
8608 }
8609
8610 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8611 nested_exit_on_intr(vcpu)) {
8612 if (vmx->nested.nested_run_pending)
8613 return -EBUSY;
8614 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8615 }
8616
8617 return 0;
8618}
8619
f4124500
JK		 8620static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8621{
8622 ktime_t remaining =
8623 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8624 u64 value;
8625
8626 if (ktime_to_ns(remaining) <= 0)
8627 return 0;
8628
8629 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8630 do_div(value, 1000000);
8631 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8632}
8633
4704d0be
NHE		 8634/*
8635 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8636 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8637 * and this function updates it to reflect the changes to the guest state while
8638 * L2 was running (and perhaps made some exits which were handled directly by L0
8639 * without going back to L1), and to reflect the exit reason.
8640 * Note that we do not have to copy here all VMCS fields, just those that
8641 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8642 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8643 * which already writes to vmcs12 directly.
8644 */
533558bc
JK		 8645static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8646 u32 exit_reason, u32 exit_intr_info,
8647 unsigned long exit_qualification)
4704d0be
NHE		 8648{
8649 /* update guest state fields: */
8650 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8651 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8652
4704d0be
NHE		 8653 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8654 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8655 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8656
8657 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8658 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8659 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8660 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8661 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8662 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8663 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8664 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8665 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8666 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8667 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8668 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8669 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8670 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8671 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8672 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8673 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8674 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8675 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8676 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8677 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8678 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8679 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8680 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8681 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8682 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8683 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8684 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8685 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8686 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8687 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8688 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8689 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8690 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8691 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8692 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8693
4704d0be
NHE		 8694 vmcs12->guest_interruptibility_info =
8695 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8696 vmcs12->guest_pending_dbg_exceptions =
8697 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8698 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8699 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8700 else
8701 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8702
f4124500
JK		 8703 if (nested_cpu_has_preemption_timer(vmcs12)) {
8704 if (vmcs12->vm_exit_controls &
8705 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8706 vmcs12->vmx_preemption_timer_value =
8707 vmx_get_preemption_timer_value(vcpu);
8708 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8709 }
7854cbca 8710
3633cfc3
NHE		 8711 /*
8712 * In some cases (usually, nested EPT), L2 is allowed to change its
8713 * own CR3 without exiting. If it has changed it, we must keep it.
8714 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8715 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8716 *
8717 * Additionally, restore L2's PDPTR to vmcs12.
8718 */
8719 if (enable_ept) {
8720 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8721 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8722 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8723 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8724 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8725 }
8726
c18911a2
JK		 8727 vmcs12->vm_entry_controls =
8728 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8729 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8730
2996fca0
JK		 8731 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8732 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8733 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8734 }
8735
4704d0be
NHE		 8736 /* TODO: These cannot have changed unless we have MSR bitmaps and
8737 * the relevant bit asks not to trap the change */
b8c07d55 8738 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8739 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8740 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8741 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8742 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8743 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8744 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8745 if (vmx_mpx_supported())
8746 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8747
8748 /* update exit information fields: */
8749
533558bc
JK		 8750 vmcs12->vm_exit_reason = exit_reason;
8751 vmcs12->exit_qualification = exit_qualification;
4704d0be 8752
533558bc 8753 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8754 if ((vmcs12->vm_exit_intr_info &
8755 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8756 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8757 vmcs12->vm_exit_intr_error_code =
8758 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8759 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8760 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8761 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8762
5f3d5799
JK		 8763 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8764 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8765 * instead of reading the real value. */
4704d0be 8766 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8767
8768 /*
8769 * Transfer the event that L0 or L1 may wanted to inject into
8770 * L2 to IDT_VECTORING_INFO_FIELD.
8771 */
8772 vmcs12_save_pending_event(vcpu, vmcs12);
8773 }
8774
8775 /*
8776 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8777 * preserved above and would only end up incorrectly in L1.
8778 */
8779 vcpu->arch.nmi_injected = false;
8780 kvm_clear_exception_queue(vcpu);
8781 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8782}
8783
8784/*
8785 * A part of what we need to when the nested L2 guest exits and we want to
8786 * run its L1 parent, is to reset L1's guest state to the host state specified
8787 * in vmcs12.
8788 * This function is to be called not only on normal nested exit, but also on
8789 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8790 * Failures During or After Loading Guest State").
8791 * This function should be called when the active VMCS is L1's (vmcs01).
8792 */
733568f9
JK		 8793static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8794 struct vmcs12 *vmcs12)
4704d0be 8795{
21feb4eb
ACL		 8796 struct kvm_segment seg;
8797
4704d0be
NHE		 8798 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8799 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8800 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8801 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8802 else
8803 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8804 vmx_set_efer(vcpu, vcpu->arch.efer);
8805
8806 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8807 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8808 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8809 /*
8810 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8811 * actually changed, because it depends on the current state of
8812 * fpu_active (which may have changed).
8813 * Note that vmx_set_cr0 refers to efer set above.
8814 */
9e3e4dbf 8815 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8816 /*
8817 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8818 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8819 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8820 */
8821 update_exception_bitmap(vcpu);
8822 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8823 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8824
8825 /*
8826 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8827 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8828 */
8829 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8830 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8831
29bf08f1 8832 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8833
4704d0be
NHE		 8834 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8835 kvm_mmu_reset_context(vcpu);
8836
feaf0c7d
GN		 8837 if (!enable_ept)
8838 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8839
4704d0be
NHE		 8840 if (enable_vpid) {
8841 /*
8842 * Trivially support vpid by letting L2s share their parent
8843 * L1's vpid. TODO: move to a more elaborate solution, giving
8844 * each L2 its own vpid and exposing the vpid feature to L1.
8845 */
8846 vmx_flush_tlb(vcpu);
8847 }
8848
8849
8850 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8851 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8852 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8853 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8854 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8855
36be0b9d
PB		 8856 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8857 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8858 vmcs_write64(GUEST_BNDCFGS, 0);
8859
44811c02 8860 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8861 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8862 vcpu->arch.pat = vmcs12->host_ia32_pat;
8863 }
4704d0be
NHE		 8864 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8865 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8866 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8867
21feb4eb
ACL		 8868 /* Set L1 segment info according to Intel SDM
8869 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8870 seg = (struct kvm_segment) {
8871 .base = 0,
8872 .limit = 0xFFFFFFFF,
8873 .selector = vmcs12->host_cs_selector,
8874 .type = 11,
8875 .present = 1,
8876 .s = 1,
8877 .g = 1
8878 };
8879 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8880 seg.l = 1;
8881 else
8882 seg.db = 1;
8883 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8884 seg = (struct kvm_segment) {
8885 .base = 0,
8886 .limit = 0xFFFFFFFF,
8887 .type = 3,
8888 .present = 1,
8889 .s = 1,
8890 .db = 1,
8891 .g = 1
8892 };
8893 seg.selector = vmcs12->host_ds_selector;
8894 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8895 seg.selector = vmcs12->host_es_selector;
8896 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8897 seg.selector = vmcs12->host_ss_selector;
8898 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8899 seg.selector = vmcs12->host_fs_selector;
8900 seg.base = vmcs12->host_fs_base;
8901 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8902 seg.selector = vmcs12->host_gs_selector;
8903 seg.base = vmcs12->host_gs_base;
8904 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8905 seg = (struct kvm_segment) {
205befd9 8906 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8907 .limit = 0x67,
8908 .selector = vmcs12->host_tr_selector,
8909 .type = 11,
8910 .present = 1
8911 };
8912 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8913
503cd0c5
JK		 8914 kvm_set_dr(vcpu, 7, 0x400);
8915 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8916}
8917
8918/*
8919 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8920 * and modify vmcs12 to make it see what it would expect to see there if
8921 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8922 */
533558bc
JK		 8923static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8924 u32 exit_intr_info,
8925 unsigned long exit_qualification)
4704d0be
NHE		 8926{
8927 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8928 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8929
5f3d5799
JK		 8930 /* trying to cancel vmlaunch/vmresume is a bug */
8931 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8932
4704d0be 8933 leave_guest_mode(vcpu);
533558bc
JK		 8934 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8935 exit_qualification);
4704d0be 8936
f3380ca5
WL		 8937 vmx_load_vmcs01(vcpu);
8938
77b0f5d6
BD		 8939 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8940 && nested_exit_intr_ack_set(vcpu)) {
8941 int irq = kvm_cpu_get_interrupt(vcpu);
8942 WARN_ON(irq < 0);
8943 vmcs12->vm_exit_intr_info = irq |
8944 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8945 }
8946
542060ea
JK		 8947 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8948 vmcs12->exit_qualification,
8949 vmcs12->idt_vectoring_info_field,
8950 vmcs12->vm_exit_intr_info,
8951 vmcs12->vm_exit_intr_error_code,
8952 KVM_ISA_VMX);
4704d0be 8953
2961e876
GN		 8954 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8955 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8956 vmx_segment_cache_clear(vmx);
8957
4704d0be
NHE		 8958 /* if no vmcs02 cache requested, remove the one we used */
8959 if (VMCS02_POOL_SIZE == 0)
8960 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8961
8962 load_vmcs12_host_state(vcpu, vmcs12);
8963
27fc51b2 8964 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8965 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8966
8967 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8968 vmx->host_rsp = 0;
8969
8970 /* Unpin physical memory we referred to in vmcs02 */
8971 if (vmx->nested.apic_access_page) {
8972 nested_release_page(vmx->nested.apic_access_page);
48d89b92 8973 vmx->nested.apic_access_page = NULL;
4704d0be 8974 }
a7c0b07d
WL		 8975 if (vmx->nested.virtual_apic_page) {
8976 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 8977 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 8978 }
4704d0be 8979
38b99173
TC		 8980 /*
8981 * We are now running in L2, mmu_notifier will force to reload the
8982 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
8983 */
8984 kvm_vcpu_reload_apic_access_page(vcpu);
8985
4704d0be
NHE		 8986 /*
8987 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8988 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8989 * success or failure flag accordingly.
8990 */
8991 if (unlikely(vmx->fail)) {
8992 vmx->fail = 0;
8993 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8994 } else
8995 nested_vmx_succeed(vcpu);
012f83cb
AG		 8996 if (enable_shadow_vmcs)
8997 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8998
8999 /* in case we halted in L2 */
9000 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9001}
9002
42124925
JK		 9003/*
9004 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9005 */
9006static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9007{
9008 if (is_guest_mode(vcpu))
533558bc 9009 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9010 free_nested(to_vmx(vcpu));
9011}
9012
7c177938
NHE		 9013/*
9014 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9015 * 23.7 "VM-entry failures during or after loading guest state" (this also
9016 * lists the acceptable exit-reason and exit-qualification parameters).
9017 * It should only be called before L2 actually succeeded to run, and when
9018 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9019 */
9020static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9021 struct vmcs12 *vmcs12,
9022 u32 reason, unsigned long qualification)
9023{
9024 load_vmcs12_host_state(vcpu, vmcs12);
9025 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9026 vmcs12->exit_qualification = qualification;
9027 nested_vmx_succeed(vcpu);
012f83cb
AG		 9028 if (enable_shadow_vmcs)
9029 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9030}
9031
8a76d7f2
JR		 9032static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9033 struct x86_instruction_info *info,
9034 enum x86_intercept_stage stage)
9035{
9036 return X86EMUL_CONTINUE;
9037}
9038
48d89b92 9039static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9040{
b4a2d31d
RK		 9041 if (ple_gap)
9042 shrink_ple_window(vcpu);
ae97a3b8
RK		 9043}
9044
cbdd1bea 9045static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9046 .cpu_has_kvm_support = cpu_has_kvm_support,
9047 .disabled_by_bios = vmx_disabled_by_bios,
9048 .hardware_setup = hardware_setup,
9049 .hardware_unsetup = hardware_unsetup,
002c7f7c 9050 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9051 .hardware_enable = hardware_enable,
9052 .hardware_disable = hardware_disable,
04547156 9053 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9054
9055 .vcpu_create = vmx_create_vcpu,
9056 .vcpu_free = vmx_free_vcpu,
04d2cc77 9057 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9058
04d2cc77 9059 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9060 .vcpu_load = vmx_vcpu_load,
9061 .vcpu_put = vmx_vcpu_put,
9062
c8639010 9063 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9064 .get_msr = vmx_get_msr,
9065 .set_msr = vmx_set_msr,
9066 .get_segment_base = vmx_get_segment_base,
9067 .get_segment = vmx_get_segment,
9068 .set_segment = vmx_set_segment,
2e4d2653 9069 .get_cpl = vmx_get_cpl,
6aa8b732 9070 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9071 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9072 .decache_cr3 = vmx_decache_cr3,
25c4c276 9073 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9074 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9075 .set_cr3 = vmx_set_cr3,
9076 .set_cr4 = vmx_set_cr4,
6aa8b732 9077 .set_efer = vmx_set_efer,
6aa8b732
AK		 9078 .get_idt = vmx_get_idt,
9079 .set_idt = vmx_set_idt,
9080 .get_gdt = vmx_get_gdt,
9081 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9082 .get_dr6 = vmx_get_dr6,
9083 .set_dr6 = vmx_set_dr6,
020df079 9084 .set_dr7 = vmx_set_dr7,
81908bf4 9085 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9086 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9087 .get_rflags = vmx_get_rflags,
9088 .set_rflags = vmx_set_rflags,
02daab21 9089 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9090
9091 .tlb_flush = vmx_flush_tlb,
6aa8b732 9092
6aa8b732 9093 .run = vmx_vcpu_run,
6062d012 9094 .handle_exit = vmx_handle_exit,
6aa8b732 9095 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9096 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9097 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9098 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9099 .set_irq = vmx_inject_irq,
95ba8273 9100 .set_nmi = vmx_inject_nmi,
298101da 9101 .queue_exception = vmx_queue_exception,
b463a6f7 9102 .cancel_injection = vmx_cancel_injection,
78646121 9103 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9104 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9105 .get_nmi_mask = vmx_get_nmi_mask,
9106 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9107 .enable_nmi_window = enable_nmi_window,
9108 .enable_irq_window = enable_irq_window,
9109 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9110 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9111 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9112 .vm_has_apicv = vmx_vm_has_apicv,
9113 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9114 .hwapic_irr_update = vmx_hwapic_irr_update,
9115 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9116 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9117 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9118
cbc94022 9119 .set_tss_addr = vmx_set_tss_addr,
67253af5 9120 .get_tdp_level = get_ept_level,
4b12f0de 9121 .get_mt_mask = vmx_get_mt_mask,
229456fc 9122
586f9607 9123 .get_exit_info = vmx_get_exit_info,
586f9607 9124
17cc3935 9125 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9126
9127 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9128
9129 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9130 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9131
9132 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9133
9134 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9135
4051b188 9136 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9137 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9138 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9139 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9140 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9141 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9142
9143 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9144
9145 .check_intercept = vmx_check_intercept,
a547c6db 9146 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9147 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9148
9149 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9150
9151 .sched_in = vmx_sched_in,
6aa8b732
AK		 9152};
9153
9154static int __init vmx_init(void)
9155{
8d14695f 9156 int r, i, msr;
26bb0981
AK		 9157
9158 rdmsrl_safe(MSR_EFER, &host_efer);
9159
03916db9 9160 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 9161 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 9162
3e7c73e9 9163 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 9164 if (!vmx_io_bitmap_a)
9165 return -ENOMEM;
9166
2106a548
GC		 9167 r = -ENOMEM;
9168
3e7c73e9 9169 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9170 if (!vmx_io_bitmap_b)
fdef3ad1 9171 goto out;
fdef3ad1 9172
5897297b 9173 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9174 if (!vmx_msr_bitmap_legacy)
25c5f225 9175 goto out1;
2106a548 9176
8d14695f
YZ		 9177 vmx_msr_bitmap_legacy_x2apic =
9178 (unsigned long *)__get_free_page(GFP_KERNEL);
9179 if (!vmx_msr_bitmap_legacy_x2apic)
9180 goto out2;
25c5f225 9181
5897297b 9182 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9183 if (!vmx_msr_bitmap_longmode)
8d14695f 9184 goto out3;
2106a548 9185
8d14695f
YZ		 9186 vmx_msr_bitmap_longmode_x2apic =
9187 (unsigned long *)__get_free_page(GFP_KERNEL);
9188 if (!vmx_msr_bitmap_longmode_x2apic)
9189 goto out4;
4607c2d7
AG		 9190 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9191 if (!vmx_vmread_bitmap)
9192 goto out5;
9193
9194 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9195 if (!vmx_vmwrite_bitmap)
9196 goto out6;
9197
9198 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9199 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9200
fdef3ad1
HQ		 9201 /*
9202 * Allow direct access to the PC debug port (it is often used for I/O
9203 * delays, but the vmexits simply slow things down).
9204 */
3e7c73e9
AK		 9205 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9206 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9207
3e7c73e9 9208 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9209
5897297b
AK		 9210 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9211 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9212
2384d2b3
SY		 9213 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9214
0ee75bea
AK		 9215 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9216 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9217 if (r)
4607c2d7 9218 goto out7;
25c5f225 9219
8f536b76
ZY		 9220#ifdef CONFIG_KEXEC
9221 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9222 crash_vmclear_local_loaded_vmcss);
9223#endif
9224
5897297b
AK		 9225 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9226 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9227 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9228 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9229 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9230 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9231 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9232
8d14695f
YZ		 9233 memcpy(vmx_msr_bitmap_legacy_x2apic,
9234 vmx_msr_bitmap_legacy, PAGE_SIZE);
9235 memcpy(vmx_msr_bitmap_longmode_x2apic,
9236 vmx_msr_bitmap_longmode, PAGE_SIZE);
9237
01e439be 9238 if (enable_apicv) {
8d14695f
YZ		 9239 for (msr = 0x800; msr <= 0x8ff; msr++)
9240 vmx_disable_intercept_msr_read_x2apic(msr);
9241
9242 /* According SDM, in x2apic mode, the whole id reg is used.
9243 * But in KVM, it only use the highest eight bits. Need to
9244 * intercept it */
9245 vmx_enable_intercept_msr_read_x2apic(0x802);
9246 /* TMCCT */
9247 vmx_enable_intercept_msr_read_x2apic(0x839);
9248 /* TPR */
9249 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9250 /* EOI */
9251 vmx_disable_intercept_msr_write_x2apic(0x80b);
9252 /* SELF-IPI */
9253 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9254 }
fdef3ad1 9255
089d034e 9256 if (enable_ept) {
3f6d8c8a
XH		 9257 kvm_mmu_set_mask_ptes(0ull,
9258 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9259 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9260 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9261 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9262 kvm_enable_tdp();
9263 } else
9264 kvm_disable_tdp();
1439442c 9265
b4a2d31d
RK		 9266 update_ple_window_actual_max();
9267
fdef3ad1
HQ		 9268 return 0;
9269
4607c2d7
AG		 9270out7:
9271 free_page((unsigned long)vmx_vmwrite_bitmap);
9272out6:
9273 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9274out5:
9275 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9276out4:
5897297b 9277 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9278out3:
9279 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9280out2:
5897297b 9281 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9282out1:
3e7c73e9 9283 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9284out:
3e7c73e9 9285 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9286 return r;
6aa8b732
AK		 9287}
9288
9289static void __exit vmx_exit(void)
9290{
8d14695f
YZ		 9291 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9292 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9293 free_page((unsigned long)vmx_msr_bitmap_legacy);
9294 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9295 free_page((unsigned long)vmx_io_bitmap_b);
9296 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9297 free_page((unsigned long)vmx_vmwrite_bitmap);
9298 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9299
8f536b76 9300#ifdef CONFIG_KEXEC
3b63a43f 9301 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9302 synchronize_rcu();
9303#endif
9304
cb498ea2 9305 kvm_exit();
6aa8b732
AK		 9306}
9307
9308module_init(vmx_init)
9309module_exit(vmx_exit)
ubuntu-bionic-kernel mirror