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KVM: x86: Check non-canonical addresses upon WRMSR
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d974baa3 475 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 476 } host_state;
9c8cba37 477 struct {
7ffd92c5 478 int vm86_active;
78ac8b47 479 ulong save_rflags;
f5f7b2fe
AK		 480 struct kvm_segment segs[8];
481 } rmode;
482 struct {
483 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 484 struct kvm_save_segment {
485 u16 selector;
486 unsigned long base;
487 u32 limit;
488 u32 ar;
f5f7b2fe 489 } seg[8];
2fb92db1 490 } segment_cache;
2384d2b3 491 int vpid;
04fa4d32 492 bool emulation_required;
3b86cd99
JK		 493
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked;
496 ktime_t entry_time;
497 s64 vnmi_blocked_time;
a0861c02 498 u32 exit_reason;
4e47c7a6
SY		 499
500 bool rdtscp_enabled;
ec378aee 501
01e439be
YZ		 502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc;
504
ec378aee
NHE		 505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested;
a7653ecd
RK		 507
508 /* Dynamic PLE window. */
509 int ple_window;
510 bool ple_window_dirty;
a2fa3e9f
GH		 511};
512
2fb92db1
AK		 513enum segment_cache_field {
514 SEG_FIELD_SEL = 0,
515 SEG_FIELD_BASE = 1,
516 SEG_FIELD_LIMIT = 2,
517 SEG_FIELD_AR = 3,
518
519 SEG_FIELD_NR = 4
520};
521
a2fa3e9f
GH		 522static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
523{
fb3f0f51 524 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 525}
526
22bd0358
NHE		 527#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
531
4607c2d7 532
fe2b201b 533static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 534 /*
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
545 */
546 VM_EXIT_REASON,
547 VM_EXIT_INTR_INFO,
548 VM_EXIT_INSTRUCTION_LEN,
549 IDT_VECTORING_INFO_FIELD,
550 IDT_VECTORING_ERROR_CODE,
551 VM_EXIT_INTR_ERROR_CODE,
552 EXIT_QUALIFICATION,
553 GUEST_LINEAR_ADDRESS,
554 GUEST_PHYSICAL_ADDRESS
555};
fe2b201b 556static int max_shadow_read_only_fields =
4607c2d7
AG		 557 ARRAY_SIZE(shadow_read_only_fields);
558
fe2b201b 559static unsigned long shadow_read_write_fields[] = {
a7c0b07d 560 TPR_THRESHOLD,
4607c2d7
AG		 561 GUEST_RIP,
562 GUEST_RSP,
563 GUEST_CR0,
564 GUEST_CR3,
565 GUEST_CR4,
566 GUEST_INTERRUPTIBILITY_INFO,
567 GUEST_RFLAGS,
568 GUEST_CS_SELECTOR,
569 GUEST_CS_AR_BYTES,
570 GUEST_CS_LIMIT,
571 GUEST_CS_BASE,
572 GUEST_ES_BASE,
36be0b9d 573 GUEST_BNDCFGS,
4607c2d7
AG		 574 CR0_GUEST_HOST_MASK,
575 CR0_READ_SHADOW,
576 CR4_READ_SHADOW,
577 TSC_OFFSET,
578 EXCEPTION_BITMAP,
579 CPU_BASED_VM_EXEC_CONTROL,
580 VM_ENTRY_EXCEPTION_ERROR_CODE,
581 VM_ENTRY_INTR_INFO_FIELD,
582 VM_ENTRY_INSTRUCTION_LEN,
583 VM_ENTRY_EXCEPTION_ERROR_CODE,
584 HOST_FS_BASE,
585 HOST_GS_BASE,
586 HOST_FS_SELECTOR,
587 HOST_GS_SELECTOR
588};
fe2b201b 589static int max_shadow_read_write_fields =
4607c2d7
AG		 590 ARRAY_SIZE(shadow_read_write_fields);
591
772e0318 592static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 593 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
594 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
595 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
596 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
597 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
598 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
599 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
600 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
601 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
602 FIELD(HOST_ES_SELECTOR, host_es_selector),
603 FIELD(HOST_CS_SELECTOR, host_cs_selector),
604 FIELD(HOST_SS_SELECTOR, host_ss_selector),
605 FIELD(HOST_DS_SELECTOR, host_ds_selector),
606 FIELD(HOST_FS_SELECTOR, host_fs_selector),
607 FIELD(HOST_GS_SELECTOR, host_gs_selector),
608 FIELD(HOST_TR_SELECTOR, host_tr_selector),
609 FIELD64(IO_BITMAP_A, io_bitmap_a),
610 FIELD64(IO_BITMAP_B, io_bitmap_b),
611 FIELD64(MSR_BITMAP, msr_bitmap),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
615 FIELD64(TSC_OFFSET, tsc_offset),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
617 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
618 FIELD64(EPT_POINTER, ept_pointer),
619 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
620 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
621 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
622 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
623 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
625 FIELD64(GUEST_PDPTR0, guest_pdptr0),
626 FIELD64(GUEST_PDPTR1, guest_pdptr1),
627 FIELD64(GUEST_PDPTR2, guest_pdptr2),
628 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 629 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 630 FIELD64(HOST_IA32_PAT, host_ia32_pat),
631 FIELD64(HOST_IA32_EFER, host_ia32_efer),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
635 FIELD(EXCEPTION_BITMAP, exception_bitmap),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
638 FIELD(CR3_TARGET_COUNT, cr3_target_count),
639 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
640 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
642 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
647 FIELD(TPR_THRESHOLD, tpr_threshold),
648 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
649 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
650 FIELD(VM_EXIT_REASON, vm_exit_reason),
651 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
652 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
653 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
654 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
655 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
656 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
657 FIELD(GUEST_ES_LIMIT, guest_es_limit),
658 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
659 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
660 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
661 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
662 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
663 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
664 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
665 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
666 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
667 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
668 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
669 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
670 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
671 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
672 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
673 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
674 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
676 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
677 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
678 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 679 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 680 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
681 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
682 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
683 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
684 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
685 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
686 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
687 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
688 FIELD(EXIT_QUALIFICATION, exit_qualification),
689 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
690 FIELD(GUEST_CR0, guest_cr0),
691 FIELD(GUEST_CR3, guest_cr3),
692 FIELD(GUEST_CR4, guest_cr4),
693 FIELD(GUEST_ES_BASE, guest_es_base),
694 FIELD(GUEST_CS_BASE, guest_cs_base),
695 FIELD(GUEST_SS_BASE, guest_ss_base),
696 FIELD(GUEST_DS_BASE, guest_ds_base),
697 FIELD(GUEST_FS_BASE, guest_fs_base),
698 FIELD(GUEST_GS_BASE, guest_gs_base),
699 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
700 FIELD(GUEST_TR_BASE, guest_tr_base),
701 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
702 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
703 FIELD(GUEST_DR7, guest_dr7),
704 FIELD(GUEST_RSP, guest_rsp),
705 FIELD(GUEST_RIP, guest_rip),
706 FIELD(GUEST_RFLAGS, guest_rflags),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
708 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
709 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
710 FIELD(HOST_CR0, host_cr0),
711 FIELD(HOST_CR3, host_cr3),
712 FIELD(HOST_CR4, host_cr4),
713 FIELD(HOST_FS_BASE, host_fs_base),
714 FIELD(HOST_GS_BASE, host_gs_base),
715 FIELD(HOST_TR_BASE, host_tr_base),
716 FIELD(HOST_GDTR_BASE, host_gdtr_base),
717 FIELD(HOST_IDTR_BASE, host_idtr_base),
718 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
719 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
720 FIELD(HOST_RSP, host_rsp),
721 FIELD(HOST_RIP, host_rip),
722};
723static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
724
725static inline short vmcs_field_to_offset(unsigned long field)
726{
727 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
728 return -1;
729 return vmcs_field_to_offset_table[field];
730}
731
a9d30f33
NHE		 732static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
733{
734 return to_vmx(vcpu)->nested.current_vmcs12;
735}
736
737static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
738{
739 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 740 if (is_error_page(page))
a9d30f33 741 return NULL;
32cad84f 742
a9d30f33
NHE		 743 return page;
744}
745
746static void nested_release_page(struct page *page)
747{
748 kvm_release_page_dirty(page);
749}
750
751static void nested_release_page_clean(struct page *page)
752{
753 kvm_release_page_clean(page);
754}
755
bfd0a56b 756static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 757static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 758static void kvm_cpu_vmxon(u64 addr);
759static void kvm_cpu_vmxoff(void);
93c4adc7 760static bool vmx_mpx_supported(void);
776e58ea 761static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 762static void vmx_set_segment(struct kvm_vcpu *vcpu,
763 struct kvm_segment *var, int seg);
764static void vmx_get_segment(struct kvm_vcpu *vcpu,
765 struct kvm_segment *var, int seg);
d99e4152
GN		 766static bool guest_state_valid(struct kvm_vcpu *vcpu);
767static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 768static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 769static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 770static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 771static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 772
6aa8b732
AK		 773static DEFINE_PER_CPU(struct vmcs *, vmxarea);
774static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 775/*
776 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
777 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
778 */
779static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 780static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 781
3e7c73e9
AK		 782static unsigned long *vmx_io_bitmap_a;
783static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 784static unsigned long *vmx_msr_bitmap_legacy;
785static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 786static unsigned long *vmx_msr_bitmap_legacy_x2apic;
787static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 788static unsigned long *vmx_vmread_bitmap;
789static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 790
110312c8 791static bool cpu_has_load_ia32_efer;
8bf00a52 792static bool cpu_has_load_perf_global_ctrl;
110312c8 793
2384d2b3
SY		 794static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
795static DEFINE_SPINLOCK(vmx_vpid_lock);
796
1c3d14fe 797static struct vmcs_config {
6aa8b732
AK		 798 int size;
799 int order;
800 u32 revision_id;
1c3d14fe
YS		 801 u32 pin_based_exec_ctrl;
802 u32 cpu_based_exec_ctrl;
f78e0e2e 803 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 804 u32 vmexit_ctrl;
805 u32 vmentry_ctrl;
806} vmcs_config;
6aa8b732 807
efff9e53 808static struct vmx_capability {
d56f546d
SY		 809 u32 ept;
810 u32 vpid;
811} vmx_capability;
812
6aa8b732
AK		 813#define VMX_SEGMENT_FIELD(seg) \
814 [VCPU_SREG_##seg] = { \
815 .selector = GUEST_##seg##_SELECTOR, \
816 .base = GUEST_##seg##_BASE, \
817 .limit = GUEST_##seg##_LIMIT, \
818 .ar_bytes = GUEST_##seg##_AR_BYTES, \
819 }
820
772e0318 821static const struct kvm_vmx_segment_field {
6aa8b732
AK		 822 unsigned selector;
823 unsigned base;
824 unsigned limit;
825 unsigned ar_bytes;
826} kvm_vmx_segment_fields[] = {
827 VMX_SEGMENT_FIELD(CS),
828 VMX_SEGMENT_FIELD(DS),
829 VMX_SEGMENT_FIELD(ES),
830 VMX_SEGMENT_FIELD(FS),
831 VMX_SEGMENT_FIELD(GS),
832 VMX_SEGMENT_FIELD(SS),
833 VMX_SEGMENT_FIELD(TR),
834 VMX_SEGMENT_FIELD(LDTR),
835};
836
26bb0981
AK		 837static u64 host_efer;
838
6de4f3ad
AK		 839static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
840
4d56c8a7 841/*
8c06585d 842 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 843 * away by decrementing the array size.
844 */
6aa8b732 845static const u32 vmx_msr_index[] = {
05b3e0c2 846#ifdef CONFIG_X86_64
44ea2b17 847 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 848#endif
8c06585d 849 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 850};
6aa8b732 851
31299944 852static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 853{
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 856 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 857}
858
31299944 859static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 860{
861 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
862 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 863 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 864}
865
31299944 866static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 867{
868 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
869 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 870 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 871}
872
31299944 873static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 874{
875 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
876 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
877}
878
31299944 879static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 880{
881 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
882 INTR_INFO_VALID_MASK)) ==
883 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
884}
885
31299944 886static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 887{
04547156 888 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 889}
890
31299944 891static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 892{
04547156 893 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 894}
895
31299944 896static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 897{
04547156 898 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 899}
900
31299944 901static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 902{
04547156
SY		 903 return vmcs_config.cpu_based_exec_ctrl &
904 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 905}
906
774ead3a 907static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 908{
04547156
SY		 909 return vmcs_config.cpu_based_2nd_exec_ctrl &
910 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
911}
912
8d14695f
YZ		 913static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
914{
915 return vmcs_config.cpu_based_2nd_exec_ctrl &
916 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
917}
918
83d4c286
YZ		 919static inline bool cpu_has_vmx_apic_register_virt(void)
920{
921 return vmcs_config.cpu_based_2nd_exec_ctrl &
922 SECONDARY_EXEC_APIC_REGISTER_VIRT;
923}
924
c7c9c56c
YZ		 925static inline bool cpu_has_vmx_virtual_intr_delivery(void)
926{
927 return vmcs_config.cpu_based_2nd_exec_ctrl &
928 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
929}
930
01e439be
YZ		 931static inline bool cpu_has_vmx_posted_intr(void)
932{
933 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
934}
935
936static inline bool cpu_has_vmx_apicv(void)
937{
938 return cpu_has_vmx_apic_register_virt() &&
939 cpu_has_vmx_virtual_intr_delivery() &&
940 cpu_has_vmx_posted_intr();
941}
942
04547156
SY		 943static inline bool cpu_has_vmx_flexpriority(void)
944{
945 return cpu_has_vmx_tpr_shadow() &&
946 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 947}
948
e799794e
MT		 949static inline bool cpu_has_vmx_ept_execute_only(void)
950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 952}
953
954static inline bool cpu_has_vmx_eptp_uncacheable(void)
955{
31299944 956 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 957}
958
959static inline bool cpu_has_vmx_eptp_writeback(void)
960{
31299944 961 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 962}
963
964static inline bool cpu_has_vmx_ept_2m_page(void)
965{
31299944 966 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 967}
968
878403b7
SY		 969static inline bool cpu_has_vmx_ept_1g_page(void)
970{
31299944 971 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 972}
973
4bc9b982
SY		 974static inline bool cpu_has_vmx_ept_4levels(void)
975{
976 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
977}
978
83c3a331
XH		 979static inline bool cpu_has_vmx_ept_ad_bits(void)
980{
981 return vmx_capability.ept & VMX_EPT_AD_BIT;
982}
983
31299944 984static inline bool cpu_has_vmx_invept_context(void)
d56f546d 985{
31299944 986 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 987}
988
31299944 989static inline bool cpu_has_vmx_invept_global(void)
d56f546d 990{
31299944 991 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 992}
993
518c8aee
GJ		 994static inline bool cpu_has_vmx_invvpid_single(void)
995{
996 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
997}
998
b9d762fa
GJ		 999static inline bool cpu_has_vmx_invvpid_global(void)
1000{
1001 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1002}
1003
31299944 1004static inline bool cpu_has_vmx_ept(void)
d56f546d 1005{
04547156
SY		 1006 return vmcs_config.cpu_based_2nd_exec_ctrl &
1007 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1008}
1009
31299944 1010static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1014}
1015
31299944 1016static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1017{
1018 return vmcs_config.cpu_based_2nd_exec_ctrl &
1019 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1020}
1021
31299944 1022static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1023{
6d3e435e 1024 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1025}
1026
31299944 1027static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1028{
04547156
SY		 1029 return vmcs_config.cpu_based_2nd_exec_ctrl &
1030 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1031}
1032
31299944 1033static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1034{
1035 return vmcs_config.cpu_based_2nd_exec_ctrl &
1036 SECONDARY_EXEC_RDTSCP;
1037}
1038
ad756a16
MJ		 1039static inline bool cpu_has_vmx_invpcid(void)
1040{
1041 return vmcs_config.cpu_based_2nd_exec_ctrl &
1042 SECONDARY_EXEC_ENABLE_INVPCID;
1043}
1044
31299944 1045static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1046{
1047 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
f5f48ee1
SY		 1050static inline bool cpu_has_vmx_wbinvd_exit(void)
1051{
1052 return vmcs_config.cpu_based_2nd_exec_ctrl &
1053 SECONDARY_EXEC_WBINVD_EXITING;
1054}
1055
abc4fc58
AG		 1056static inline bool cpu_has_vmx_shadow_vmcs(void)
1057{
1058 u64 vmx_msr;
1059 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1060 /* check if the cpu supports writing r/o exit information fields */
1061 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1062 return false;
1063
1064 return vmcs_config.cpu_based_2nd_exec_ctrl &
1065 SECONDARY_EXEC_SHADOW_VMCS;
1066}
1067
04547156
SY		 1068static inline bool report_flexpriority(void)
1069{
1070 return flexpriority_enabled;
1071}
1072
fe3ef05c
NHE		 1073static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1074{
1075 return vmcs12->cpu_based_vm_exec_control & bit;
1076}
1077
1078static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1079{
1080 return (vmcs12->cpu_based_vm_exec_control &
1081 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1082 (vmcs12->secondary_vm_exec_control & bit);
1083}
1084
f5c4368f 1085static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1086{
1087 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1088}
1089
f4124500
JK		 1090static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1091{
1092 return vmcs12->pin_based_vm_exec_control &
1093 PIN_BASED_VMX_PREEMPTION_TIMER;
1094}
1095
155a97a3
NHE		 1096static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1097{
1098 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1099}
1100
644d711a
NHE		 1101static inline bool is_exception(u32 intr_info)
1102{
1103 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1104 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1105}
1106
533558bc
JK		 1107static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1108 u32 exit_intr_info,
1109 unsigned long exit_qualification);
7c177938
NHE		 1110static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1111 struct vmcs12 *vmcs12,
1112 u32 reason, unsigned long qualification);
1113
8b9cf98c 1114static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1115{
1116 int i;
1117
a2fa3e9f 1118 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1119 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1120 return i;
1121 return -1;
1122}
1123
2384d2b3
SY		 1124static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1125{
1126 struct {
1127 u64 vpid : 16;
1128 u64 rsvd : 48;
1129 u64 gva;
1130 } operand = { vpid, 0, gva };
1131
4ecac3fd 1132 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1133 /* CF==1 or ZF==1 --> rc = -1 */
1134 "; ja 1f ; ud2 ; 1:"
1135 : : "a"(&operand), "c"(ext) : "cc", "memory");
1136}
1137
1439442c
SY		 1138static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1139{
1140 struct {
1141 u64 eptp, gpa;
1142 } operand = {eptp, gpa};
1143
4ecac3fd 1144 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1145 /* CF==1 or ZF==1 --> rc = -1 */
1146 "; ja 1f ; ud2 ; 1:\n"
1147 : : "a" (&operand), "c" (ext) : "cc", "memory");
1148}
1149
26bb0981 1150static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1151{
1152 int i;
1153
8b9cf98c 1154 i = __find_msr_index(vmx, msr);
a75beee6 1155 if (i >= 0)
a2fa3e9f 1156 return &vmx->guest_msrs[i];
8b6d44c7 1157 return NULL;
7725f0ba
AK		 1158}
1159
6aa8b732
AK		 1160static void vmcs_clear(struct vmcs *vmcs)
1161{
1162 u64 phys_addr = __pa(vmcs);
1163 u8 error;
1164
4ecac3fd 1165 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1166 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1167 : "cc", "memory");
1168 if (error)
1169 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1170 vmcs, phys_addr);
1171}
1172
d462b819
NHE		 1173static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1174{
1175 vmcs_clear(loaded_vmcs->vmcs);
1176 loaded_vmcs->cpu = -1;
1177 loaded_vmcs->launched = 0;
1178}
1179
7725b894
DX		 1180static void vmcs_load(struct vmcs *vmcs)
1181{
1182 u64 phys_addr = __pa(vmcs);
1183 u8 error;
1184
1185 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1186 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1187 : "cc", "memory");
1188 if (error)
2844d849 1189 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1190 vmcs, phys_addr);
1191}
1192
8f536b76
ZY		 1193#ifdef CONFIG_KEXEC
1194/*
1195 * This bitmap is used to indicate whether the vmclear
1196 * operation is enabled on all cpus. All disabled by
1197 * default.
1198 */
1199static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1200
1201static inline void crash_enable_local_vmclear(int cpu)
1202{
1203 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1204}
1205
1206static inline void crash_disable_local_vmclear(int cpu)
1207{
1208 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1209}
1210
1211static inline int crash_local_vmclear_enabled(int cpu)
1212{
1213 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1214}
1215
1216static void crash_vmclear_local_loaded_vmcss(void)
1217{
1218 int cpu = raw_smp_processor_id();
1219 struct loaded_vmcs *v;
1220
1221 if (!crash_local_vmclear_enabled(cpu))
1222 return;
1223
1224 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1225 loaded_vmcss_on_cpu_link)
1226 vmcs_clear(v->vmcs);
1227}
1228#else
1229static inline void crash_enable_local_vmclear(int cpu) { }
1230static inline void crash_disable_local_vmclear(int cpu) { }
1231#endif /* CONFIG_KEXEC */
1232
d462b819 1233static void __loaded_vmcs_clear(void *arg)
6aa8b732 1234{
d462b819 1235 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1236 int cpu = raw_smp_processor_id();
6aa8b732 1237
d462b819
NHE		 1238 if (loaded_vmcs->cpu != cpu)
1239 return; /* vcpu migration can race with cpu offline */
1240 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1241 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1242 crash_disable_local_vmclear(cpu);
d462b819 1243 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1244
1245 /*
1246 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1247 * is before setting loaded_vmcs->vcpu to -1 which is done in
1248 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1249 * then adds the vmcs into percpu list before it is deleted.
1250 */
1251 smp_wmb();
1252
d462b819 1253 loaded_vmcs_init(loaded_vmcs);
8f536b76 1254 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1255}
1256
d462b819 1257static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1258{
e6c7d321
XG		 1259 int cpu = loaded_vmcs->cpu;
1260
1261 if (cpu != -1)
1262 smp_call_function_single(cpu,
1263 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1264}
1265
1760dd49 1266static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1267{
1268 if (vmx->vpid == 0)
1269 return;
1270
518c8aee
GJ		 1271 if (cpu_has_vmx_invvpid_single())
1272 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1273}
1274
b9d762fa
GJ		 1275static inline void vpid_sync_vcpu_global(void)
1276{
1277 if (cpu_has_vmx_invvpid_global())
1278 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1279}
1280
1281static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1282{
1283 if (cpu_has_vmx_invvpid_single())
1760dd49 1284 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1285 else
1286 vpid_sync_vcpu_global();
1287}
1288
1439442c
SY		 1289static inline void ept_sync_global(void)
1290{
1291 if (cpu_has_vmx_invept_global())
1292 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1293}
1294
1295static inline void ept_sync_context(u64 eptp)
1296{
089d034e 1297 if (enable_ept) {
1439442c
SY		 1298 if (cpu_has_vmx_invept_context())
1299 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1300 else
1301 ept_sync_global();
1302 }
1303}
1304
96304217 1305static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1306{
5e520e62 1307 unsigned long value;
6aa8b732 1308
5e520e62
AK		 1309 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1310 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1311 return value;
1312}
1313
96304217 1314static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1315{
1316 return vmcs_readl(field);
1317}
1318
96304217 1319static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1320{
1321 return vmcs_readl(field);
1322}
1323
96304217 1324static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1325{
05b3e0c2 1326#ifdef CONFIG_X86_64
6aa8b732
AK		 1327 return vmcs_readl(field);
1328#else
1329 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1330#endif
1331}
1332
e52de1b8
AK		 1333static noinline void vmwrite_error(unsigned long field, unsigned long value)
1334{
1335 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1336 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1337 dump_stack();
1338}
1339
6aa8b732
AK		 1340static void vmcs_writel(unsigned long field, unsigned long value)
1341{
1342 u8 error;
1343
4ecac3fd 1344 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1345 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1346 if (unlikely(error))
1347 vmwrite_error(field, value);
6aa8b732
AK		 1348}
1349
1350static void vmcs_write16(unsigned long field, u16 value)
1351{
1352 vmcs_writel(field, value);
1353}
1354
1355static void vmcs_write32(unsigned long field, u32 value)
1356{
1357 vmcs_writel(field, value);
1358}
1359
1360static void vmcs_write64(unsigned long field, u64 value)
1361{
6aa8b732 1362 vmcs_writel(field, value);
7682f2d0 1363#ifndef CONFIG_X86_64
6aa8b732
AK		 1364 asm volatile ("");
1365 vmcs_writel(field+1, value >> 32);
1366#endif
1367}
1368
2ab455cc
AL		 1369static void vmcs_clear_bits(unsigned long field, u32 mask)
1370{
1371 vmcs_writel(field, vmcs_readl(field) & ~mask);
1372}
1373
1374static void vmcs_set_bits(unsigned long field, u32 mask)
1375{
1376 vmcs_writel(field, vmcs_readl(field) | mask);
1377}
1378
2961e876
GN		 1379static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1380{
1381 vmcs_write32(VM_ENTRY_CONTROLS, val);
1382 vmx->vm_entry_controls_shadow = val;
1383}
1384
1385static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1386{
1387 if (vmx->vm_entry_controls_shadow != val)
1388 vm_entry_controls_init(vmx, val);
1389}
1390
1391static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1392{
1393 return vmx->vm_entry_controls_shadow;
1394}
1395
1396
1397static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1398{
1399 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1400}
1401
1402static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1403{
1404 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1405}
1406
1407static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1408{
1409 vmcs_write32(VM_EXIT_CONTROLS, val);
1410 vmx->vm_exit_controls_shadow = val;
1411}
1412
1413static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1414{
1415 if (vmx->vm_exit_controls_shadow != val)
1416 vm_exit_controls_init(vmx, val);
1417}
1418
1419static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1420{
1421 return vmx->vm_exit_controls_shadow;
1422}
1423
1424
1425static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1426{
1427 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1428}
1429
1430static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1431{
1432 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1433}
1434
2fb92db1
AK		 1435static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1436{
1437 vmx->segment_cache.bitmask = 0;
1438}
1439
1440static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1441 unsigned field)
1442{
1443 bool ret;
1444 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1445
1446 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1447 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1448 vmx->segment_cache.bitmask = 0;
1449 }
1450 ret = vmx->segment_cache.bitmask & mask;
1451 vmx->segment_cache.bitmask |= mask;
1452 return ret;
1453}
1454
1455static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1456{
1457 u16 *p = &vmx->segment_cache.seg[seg].selector;
1458
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1460 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1461 return *p;
1462}
1463
1464static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1465{
1466 ulong *p = &vmx->segment_cache.seg[seg].base;
1467
1468 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1469 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1470 return *p;
1471}
1472
1473static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1474{
1475 u32 *p = &vmx->segment_cache.seg[seg].limit;
1476
1477 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1478 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1479 return *p;
1480}
1481
1482static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1483{
1484 u32 *p = &vmx->segment_cache.seg[seg].ar;
1485
1486 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1487 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1488 return *p;
1489}
1490
abd3f2d6
AK		 1491static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1492{
1493 u32 eb;
1494
fd7373cc
JK		 1495 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1496 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1497 if ((vcpu->guest_debug &
1498 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1499 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1500 eb |= 1u << BP_VECTOR;
7ffd92c5 1501 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1502 eb = ~0;
089d034e 1503 if (enable_ept)
1439442c 1504 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1505 if (vcpu->fpu_active)
1506 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1507
1508 /* When we are running a nested L2 guest and L1 specified for it a
1509 * certain exception bitmap, we must trap the same exceptions and pass
1510 * them to L1. When running L2, we will only handle the exceptions
1511 * specified above if L1 did not want them.
1512 */
1513 if (is_guest_mode(vcpu))
1514 eb |= get_vmcs12(vcpu)->exception_bitmap;
1515
abd3f2d6
AK		 1516 vmcs_write32(EXCEPTION_BITMAP, eb);
1517}
1518
2961e876
GN		 1519static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1520 unsigned long entry, unsigned long exit)
8bf00a52 1521{
2961e876
GN		 1522 vm_entry_controls_clearbit(vmx, entry);
1523 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1524}
1525
61d2ef2c
AK		 1526static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1527{
1528 unsigned i;
1529 struct msr_autoload *m = &vmx->msr_autoload;
1530
8bf00a52
GN		 1531 switch (msr) {
1532 case MSR_EFER:
1533 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1534 clear_atomic_switch_msr_special(vmx,
1535 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1536 VM_EXIT_LOAD_IA32_EFER);
1537 return;
1538 }
1539 break;
1540 case MSR_CORE_PERF_GLOBAL_CTRL:
1541 if (cpu_has_load_perf_global_ctrl) {
2961e876 1542 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1544 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1545 return;
1546 }
1547 break;
110312c8
AK		 1548 }
1549
61d2ef2c
AK		 1550 for (i = 0; i < m->nr; ++i)
1551 if (m->guest[i].index == msr)
1552 break;
1553
1554 if (i == m->nr)
1555 return;
1556 --m->nr;
1557 m->guest[i] = m->guest[m->nr];
1558 m->host[i] = m->host[m->nr];
1559 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1560 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1561}
1562
2961e876
GN		 1563static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1564 unsigned long entry, unsigned long exit,
1565 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1566 u64 guest_val, u64 host_val)
8bf00a52
GN		 1567{
1568 vmcs_write64(guest_val_vmcs, guest_val);
1569 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1570 vm_entry_controls_setbit(vmx, entry);
1571 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1572}
1573
61d2ef2c
AK		 1574static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1575 u64 guest_val, u64 host_val)
1576{
1577 unsigned i;
1578 struct msr_autoload *m = &vmx->msr_autoload;
1579
8bf00a52
GN		 1580 switch (msr) {
1581 case MSR_EFER:
1582 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1583 add_atomic_switch_msr_special(vmx,
1584 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1585 VM_EXIT_LOAD_IA32_EFER,
1586 GUEST_IA32_EFER,
1587 HOST_IA32_EFER,
1588 guest_val, host_val);
1589 return;
1590 }
1591 break;
1592 case MSR_CORE_PERF_GLOBAL_CTRL:
1593 if (cpu_has_load_perf_global_ctrl) {
2961e876 1594 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1595 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1596 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1597 GUEST_IA32_PERF_GLOBAL_CTRL,
1598 HOST_IA32_PERF_GLOBAL_CTRL,
1599 guest_val, host_val);
1600 return;
1601 }
1602 break;
110312c8
AK		 1603 }
1604
61d2ef2c
AK		 1605 for (i = 0; i < m->nr; ++i)
1606 if (m->guest[i].index == msr)
1607 break;
1608
e7fc6f93 1609 if (i == NR_AUTOLOAD_MSRS) {
60266204 1610 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1611 "Can't add msr %x\n", msr);
1612 return;
1613 } else if (i == m->nr) {
61d2ef2c
AK		 1614 ++m->nr;
1615 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1616 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1617 }
1618
1619 m->guest[i].index = msr;
1620 m->guest[i].value = guest_val;
1621 m->host[i].index = msr;
1622 m->host[i].value = host_val;
1623}
1624
33ed6329
AK		 1625static void reload_tss(void)
1626{
33ed6329
AK		 1627 /*
1628 * VT restores TR but not its size. Useless.
1629 */
89cbc767 1630 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1631 struct desc_struct *descs;
33ed6329 1632
d359192f 1633 descs = (void *)gdt->address;
33ed6329
AK		 1634 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1635 load_TR_desc();
33ed6329
AK		 1636}
1637
92c0d900 1638static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1639{
3a34a881 1640 u64 guest_efer;
51c6cf66
AK		 1641 u64 ignore_bits;
1642
f6801dff 1643 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1644
51c6cf66 1645 /*
0fa06071 1646 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1647 * outside long mode
1648 */
1649 ignore_bits = EFER_NX | EFER_SCE;
1650#ifdef CONFIG_X86_64
1651 ignore_bits |= EFER_LMA | EFER_LME;
1652 /* SCE is meaningful only in long mode on Intel */
1653 if (guest_efer & EFER_LMA)
1654 ignore_bits &= ~(u64)EFER_SCE;
1655#endif
51c6cf66
AK		 1656 guest_efer &= ~ignore_bits;
1657 guest_efer |= host_efer & ignore_bits;
26bb0981 1658 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1659 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1660
1661 clear_atomic_switch_msr(vmx, MSR_EFER);
1662 /* On ept, can't emulate nx, and must switch nx atomically */
1663 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1664 guest_efer = vmx->vcpu.arch.efer;
1665 if (!(guest_efer & EFER_LMA))
1666 guest_efer &= ~EFER_LME;
1667 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1668 return false;
1669 }
1670
26bb0981 1671 return true;
51c6cf66
AK		 1672}
1673
2d49ec72
GN		 1674static unsigned long segment_base(u16 selector)
1675{
89cbc767 1676 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1677 struct desc_struct *d;
1678 unsigned long table_base;
1679 unsigned long v;
1680
1681 if (!(selector & ~3))
1682 return 0;
1683
d359192f 1684 table_base = gdt->address;
2d49ec72
GN		 1685
1686 if (selector & 4) { /* from ldt */
1687 u16 ldt_selector = kvm_read_ldt();
1688
1689 if (!(ldt_selector & ~3))
1690 return 0;
1691
1692 table_base = segment_base(ldt_selector);
1693 }
1694 d = (struct desc_struct *)(table_base + (selector & ~7));
1695 v = get_desc_base(d);
1696#ifdef CONFIG_X86_64
1697 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1698 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1699#endif
1700 return v;
1701}
1702
1703static inline unsigned long kvm_read_tr_base(void)
1704{
1705 u16 tr;
1706 asm("str %0" : "=g"(tr));
1707 return segment_base(tr);
1708}
1709
04d2cc77 1710static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1711{
04d2cc77 1712 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1713 int i;
04d2cc77 1714
a2fa3e9f 1715 if (vmx->host_state.loaded)
33ed6329
AK		 1716 return;
1717
a2fa3e9f 1718 vmx->host_state.loaded = 1;
33ed6329
AK		 1719 /*
1720 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1721 * allow segment selectors with cpl > 0 or ti == 1.
1722 */
d6e88aec 1723 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1724 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1725 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1726 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1727 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1728 vmx->host_state.fs_reload_needed = 0;
1729 } else {
33ed6329 1730 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1731 vmx->host_state.fs_reload_needed = 1;
33ed6329 1732 }
9581d442 1733 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1734 if (!(vmx->host_state.gs_sel & 7))
1735 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1736 else {
1737 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1738 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1739 }
1740
b2da15ac
AK		 1741#ifdef CONFIG_X86_64
1742 savesegment(ds, vmx->host_state.ds_sel);
1743 savesegment(es, vmx->host_state.es_sel);
1744#endif
1745
33ed6329
AK		 1746#ifdef CONFIG_X86_64
1747 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1748 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1749#else
a2fa3e9f
GH		 1750 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1751 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1752#endif
707c0874
AK		 1753
1754#ifdef CONFIG_X86_64
c8770e7b
AK		 1755 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1756 if (is_long_mode(&vmx->vcpu))
44ea2b17 1757 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1758#endif
da8999d3
LJ		 1759 if (boot_cpu_has(X86_FEATURE_MPX))
1760 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1761 for (i = 0; i < vmx->save_nmsrs; ++i)
1762 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1763 vmx->guest_msrs[i].data,
1764 vmx->guest_msrs[i].mask);
33ed6329
AK		 1765}
1766
a9b21b62 1767static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1768{
a2fa3e9f 1769 if (!vmx->host_state.loaded)
33ed6329
AK		 1770 return;
1771
e1beb1d3 1772 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1773 vmx->host_state.loaded = 0;
c8770e7b
AK		 1774#ifdef CONFIG_X86_64
1775 if (is_long_mode(&vmx->vcpu))
1776 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1777#endif
152d3f2f 1778 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1779 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1780#ifdef CONFIG_X86_64
9581d442 1781 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1782#else
1783 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1784#endif
33ed6329 1785 }
0a77fe4c
AK		 1786 if (vmx->host_state.fs_reload_needed)
1787 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1788#ifdef CONFIG_X86_64
1789 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1790 loadsegment(ds, vmx->host_state.ds_sel);
1791 loadsegment(es, vmx->host_state.es_sel);
1792 }
b2da15ac 1793#endif
152d3f2f 1794 reload_tss();
44ea2b17 1795#ifdef CONFIG_X86_64
c8770e7b 1796 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1797#endif
da8999d3
LJ		 1798 if (vmx->host_state.msr_host_bndcfgs)
1799 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1800 /*
1801 * If the FPU is not active (through the host task or
1802 * the guest vcpu), then restore the cr0.TS bit.
1803 */
1804 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1805 stts();
89cbc767 1806 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1807}
1808
a9b21b62
AK		 1809static void vmx_load_host_state(struct vcpu_vmx *vmx)
1810{
1811 preempt_disable();
1812 __vmx_load_host_state(vmx);
1813 preempt_enable();
1814}
1815
6aa8b732
AK		 1816/*
1817 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1818 * vcpu mutex is already taken.
1819 */
15ad7146 1820static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1821{
a2fa3e9f 1822 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1823 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1824
4610c9cc
DX		 1825 if (!vmm_exclusive)
1826 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1827 else if (vmx->loaded_vmcs->cpu != cpu)
1828 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1829
d462b819
NHE		 1830 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1831 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1832 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1833 }
1834
d462b819 1835 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1836 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1837 unsigned long sysenter_esp;
1838
a8eeb04a 1839 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1840 local_irq_disable();
8f536b76 1841 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1842
1843 /*
1844 * Read loaded_vmcs->cpu should be before fetching
1845 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1846 * See the comments in __loaded_vmcs_clear().
1847 */
1848 smp_rmb();
1849
d462b819
NHE		 1850 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1851 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1852 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1853 local_irq_enable();
1854
6aa8b732
AK		 1855 /*
1856 * Linux uses per-cpu TSS and GDT, so set these when switching
1857 * processors.
1858 */
d6e88aec 1859 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1860 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1861
1862 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1863 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1864 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1865 }
6aa8b732
AK		 1866}
1867
1868static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1869{
a9b21b62 1870 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1871 if (!vmm_exclusive) {
d462b819
NHE		 1872 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1873 vcpu->cpu = -1;
4610c9cc
DX		 1874 kvm_cpu_vmxoff();
1875 }
6aa8b732
AK		 1876}
1877
5fd86fcf
AK		 1878static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1879{
81231c69
AK		 1880 ulong cr0;
1881
5fd86fcf
AK		 1882 if (vcpu->fpu_active)
1883 return;
1884 vcpu->fpu_active = 1;
81231c69
AK		 1885 cr0 = vmcs_readl(GUEST_CR0);
1886 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1887 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1888 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1889 update_exception_bitmap(vcpu);
edcafe3c 1890 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1891 if (is_guest_mode(vcpu))
1892 vcpu->arch.cr0_guest_owned_bits &=
1893 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1894 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1895}
1896
edcafe3c
AK		 1897static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1898
fe3ef05c
NHE		 1899/*
1900 * Return the cr0 value that a nested guest would read. This is a combination
1901 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1902 * its hypervisor (cr0_read_shadow).
1903 */
1904static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1905{
1906 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1907 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1908}
1909static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1910{
1911 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1912 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1913}
1914
5fd86fcf
AK		 1915static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1916{
36cf24e0
NHE		 1917 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1918 * set this *before* calling this function.
1919 */
edcafe3c 1920 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1921 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1922 update_exception_bitmap(vcpu);
edcafe3c
AK		 1923 vcpu->arch.cr0_guest_owned_bits = 0;
1924 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1925 if (is_guest_mode(vcpu)) {
1926 /*
1927 * L1's specified read shadow might not contain the TS bit,
1928 * so now that we turned on shadowing of this bit, we need to
1929 * set this bit of the shadow. Like in nested_vmx_run we need
1930 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1931 * up-to-date here because we just decached cr0.TS (and we'll
1932 * only update vmcs12->guest_cr0 on nested exit).
1933 */
1934 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1935 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1936 (vcpu->arch.cr0 & X86_CR0_TS);
1937 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1938 } else
1939 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1940}
1941
6aa8b732
AK		 1942static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1943{
78ac8b47 1944 unsigned long rflags, save_rflags;
345dcaa8 1945
6de12732
AK		 1946 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1947 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1948 rflags = vmcs_readl(GUEST_RFLAGS);
1949 if (to_vmx(vcpu)->rmode.vm86_active) {
1950 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1951 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1952 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1953 }
1954 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1955 }
6de12732 1956 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1957}
1958
1959static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1960{
6de12732
AK		 1961 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1962 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1963 if (to_vmx(vcpu)->rmode.vm86_active) {
1964 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1965 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1966 }
6aa8b732
AK		 1967 vmcs_writel(GUEST_RFLAGS, rflags);
1968}
1969
37ccdcbe 1970static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1971{
1972 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1973 int ret = 0;
1974
1975 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1976 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1977 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1978 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1979
37ccdcbe 1980 return ret;
2809f5d2
GC		 1981}
1982
1983static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1984{
1985 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1986 u32 interruptibility = interruptibility_old;
1987
1988 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1989
48005f64 1990 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1991 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1992 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1993 interruptibility |= GUEST_INTR_STATE_STI;
1994
1995 if ((interruptibility != interruptibility_old))
1996 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1997}
1998
6aa8b732
AK		 1999static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2000{
2001 unsigned long rip;
6aa8b732 2002
5fdbf976 2003 rip = kvm_rip_read(vcpu);
6aa8b732 2004 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2005 kvm_rip_write(vcpu, rip);
6aa8b732 2006
2809f5d2
GC		 2007 /* skipping an emulated instruction also counts */
2008 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2009}
2010
0b6ac343
NHE		 2011/*
2012 * KVM wants to inject page-faults which it got to the guest. This function
2013 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2014 */
e011c663 2015static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2016{
2017 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2018
e011c663 2019 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2020 return 0;
2021
533558bc
JK		 2022 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2023 vmcs_read32(VM_EXIT_INTR_INFO),
2024 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2025 return 1;
2026}
2027
298101da 2028static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2029 bool has_error_code, u32 error_code,
2030 bool reinject)
298101da 2031{
77ab6db0 2032 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2033 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2034
e011c663
GN		 2035 if (!reinject && is_guest_mode(vcpu) &&
2036 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2037 return;
2038
8ab2d2e2 2039 if (has_error_code) {
77ab6db0 2040 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2041 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2042 }
77ab6db0 2043
7ffd92c5 2044 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2045 int inc_eip = 0;
2046 if (kvm_exception_is_soft(nr))
2047 inc_eip = vcpu->arch.event_exit_inst_len;
2048 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2049 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2050 return;
2051 }
2052
66fd3f7f
GN		 2053 if (kvm_exception_is_soft(nr)) {
2054 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2055 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2056 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2057 } else
2058 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2059
2060 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2061}
2062
4e47c7a6
SY		 2063static bool vmx_rdtscp_supported(void)
2064{
2065 return cpu_has_vmx_rdtscp();
2066}
2067
ad756a16
MJ		 2068static bool vmx_invpcid_supported(void)
2069{
2070 return cpu_has_vmx_invpcid() && enable_ept;
2071}
2072
a75beee6
ED		 2073/*
2074 * Swap MSR entry in host/guest MSR entry array.
2075 */
8b9cf98c 2076static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2077{
26bb0981 2078 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2079
2080 tmp = vmx->guest_msrs[to];
2081 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2082 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2083}
2084
8d14695f
YZ		 2085static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2086{
2087 unsigned long *msr_bitmap;
2088
2089 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2090 if (is_long_mode(vcpu))
2091 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2092 else
2093 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2094 } else {
2095 if (is_long_mode(vcpu))
2096 msr_bitmap = vmx_msr_bitmap_longmode;
2097 else
2098 msr_bitmap = vmx_msr_bitmap_legacy;
2099 }
2100
2101 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2102}
2103
e38aea3e
AK		 2104/*
2105 * Set up the vmcs to automatically save and restore system
2106 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2107 * mode, as fiddling with msrs is very expensive.
2108 */
8b9cf98c 2109static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2110{
26bb0981 2111 int save_nmsrs, index;
e38aea3e 2112
a75beee6
ED		 2113 save_nmsrs = 0;
2114#ifdef CONFIG_X86_64
8b9cf98c 2115 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2116 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2117 if (index >= 0)
8b9cf98c
RR		 2118 move_msr_up(vmx, index, save_nmsrs++);
2119 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2120 if (index >= 0)
8b9cf98c
RR		 2121 move_msr_up(vmx, index, save_nmsrs++);
2122 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2123 if (index >= 0)
8b9cf98c 2124 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2125 index = __find_msr_index(vmx, MSR_TSC_AUX);
2126 if (index >= 0 && vmx->rdtscp_enabled)
2127 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2128 /*
8c06585d 2129 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2130 * if efer.sce is enabled.
2131 */
8c06585d 2132 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2133 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2134 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2135 }
2136#endif
92c0d900
AK		 2137 index = __find_msr_index(vmx, MSR_EFER);
2138 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2139 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2140
26bb0981 2141 vmx->save_nmsrs = save_nmsrs;
5897297b 2142
8d14695f
YZ		 2143 if (cpu_has_vmx_msr_bitmap())
2144 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2145}
2146
6aa8b732
AK		 2147/*
2148 * reads and returns guest's timestamp counter "register"
2149 * guest_tsc = host_tsc + tsc_offset -- 21.3
2150 */
2151static u64 guest_read_tsc(void)
2152{
2153 u64 host_tsc, tsc_offset;
2154
2155 rdtscll(host_tsc);
2156 tsc_offset = vmcs_read64(TSC_OFFSET);
2157 return host_tsc + tsc_offset;
2158}
2159
d5c1785d
NHE		 2160/*
2161 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2162 * counter, even if a nested guest (L2) is currently running.
2163 */
48d89b92 2164static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2165{
886b470c 2166 u64 tsc_offset;
d5c1785d 2167
d5c1785d
NHE		 2168 tsc_offset = is_guest_mode(vcpu) ?
2169 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2170 vmcs_read64(TSC_OFFSET);
2171 return host_tsc + tsc_offset;
2172}
2173
4051b188 2174/*
cc578287
ZA		 2175 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2176 * software catchup for faster rates on slower CPUs.
4051b188 2177 */
cc578287 2178static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2179{
cc578287
ZA		 2180 if (!scale)
2181 return;
2182
2183 if (user_tsc_khz > tsc_khz) {
2184 vcpu->arch.tsc_catchup = 1;
2185 vcpu->arch.tsc_always_catchup = 1;
2186 } else
2187 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2188}
2189
ba904635
WA		 2190static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2191{
2192 return vmcs_read64(TSC_OFFSET);
2193}
2194
6aa8b732 2195/*
99e3e30a 2196 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2197 */
99e3e30a 2198static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2199{
27fc51b2 2200 if (is_guest_mode(vcpu)) {
7991825b 2201 /*
27fc51b2
NHE		 2202 * We're here if L1 chose not to trap WRMSR to TSC. According
2203 * to the spec, this should set L1's TSC; The offset that L1
2204 * set for L2 remains unchanged, and still needs to be added
2205 * to the newly set TSC to get L2's TSC.
7991825b 2206 */
27fc51b2
NHE		 2207 struct vmcs12 *vmcs12;
2208 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2209 /* recalculate vmcs02.TSC_OFFSET: */
2210 vmcs12 = get_vmcs12(vcpu);
2211 vmcs_write64(TSC_OFFSET, offset +
2212 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2213 vmcs12->tsc_offset : 0));
2214 } else {
489223ed
YY		 2215 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2216 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2217 vmcs_write64(TSC_OFFSET, offset);
2218 }
6aa8b732
AK		 2219}
2220
f1e2b260 2221static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2222{
2223 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2224
e48672fa 2225 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2226 if (is_guest_mode(vcpu)) {
2227 /* Even when running L2, the adjustment needs to apply to L1 */
2228 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2229 } else
2230 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2231 offset + adjustment);
e48672fa
ZA		 2232}
2233
857e4099
JR		 2234static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2235{
2236 return target_tsc - native_read_tsc();
2237}
2238
801d3424
NHE		 2239static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2240{
2241 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2242 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2243}
2244
2245/*
2246 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2247 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2248 * all guests if the "nested" module option is off, and can also be disabled
2249 * for a single guest by disabling its VMX cpuid bit.
2250 */
2251static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2252{
2253 return nested && guest_cpuid_has_vmx(vcpu);
2254}
2255
b87a51ae
NHE		 2256/*
2257 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2258 * returned for the various VMX controls MSRs when nested VMX is enabled.
2259 * The same values should also be used to verify that vmcs12 control fields are
2260 * valid during nested entry from L1 to L2.
2261 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2262 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2263 * bit in the high half is on if the corresponding bit in the control field
2264 * may be on. See also vmx_control_verify().
2265 * TODO: allow these variables to be modified (downgraded) by module options
2266 * or other means.
2267 */
2268static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2269static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2270static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2271static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2272static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2273static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2274static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2275static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2276static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2277static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2278static __init void nested_vmx_setup_ctls_msrs(void)
2279{
2280 /*
2281 * Note that as a general rule, the high half of the MSRs (bits in
2282 * the control fields which may be 1) should be initialized by the
2283 * intersection of the underlying hardware's MSR (i.e., features which
2284 * can be supported) and the list of features we want to expose -
2285 * because they are known to be properly supported in our code.
2286 * Also, usually, the low half of the MSRs (bits which must be 1) can
2287 * be set to 0, meaning that L1 may turn off any of these bits. The
2288 * reason is that if one of these bits is necessary, it will appear
2289 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2290 * fields of vmcs01 and vmcs02, will turn these bits off - and
2291 * nested_vmx_exit_handled() will not pass related exits to L1.
2292 * These rules have exceptions below.
2293 */
2294
2295 /* pin-based controls */
eabeaacc
JK		 2296 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2297 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2298 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2299 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2300 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2301 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2302 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2303
3dbcd8da 2304 /* exit controls */
c0dfee58
ACL		 2305 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2306 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2307 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2308
c0dfee58 2309 nested_vmx_exit_ctls_high &=
b87a51ae 2310#ifdef CONFIG_X86_64
c0dfee58 2311 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2312#endif
f4124500
JK		 2313 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2314 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2315 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2316 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2317
36be0b9d
PB		 2318 if (vmx_mpx_supported())
2319 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2320
2996fca0
JK		 2321 /* We support free control of debug control saving. */
2322 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2323 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2324
b87a51ae
NHE		 2325 /* entry controls */
2326 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2327 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2328 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2329 nested_vmx_entry_ctls_high &=
57435349
JK		 2330#ifdef CONFIG_X86_64
2331 VM_ENTRY_IA32E_MODE |
2332#endif
2333 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2334 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2335 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2336 if (vmx_mpx_supported())
2337 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2338
2996fca0
JK		 2339 /* We support free control of debug control loading. */
2340 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2341 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2342
b87a51ae
NHE		 2343 /* cpu-based controls */
2344 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2345 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2346 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2347 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2348 CPU_BASED_VIRTUAL_INTR_PENDING |
2349 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2350 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2351 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2352 CPU_BASED_CR3_STORE_EXITING |
2353#ifdef CONFIG_X86_64
2354 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2355#endif
2356 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2357 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2358 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2359 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2360 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2361 /*
2362 * We can allow some features even when not supported by the
2363 * hardware. For example, L1 can specify an MSR bitmap - and we
2364 * can use it to avoid exits to L1 - even when L0 runs L2
2365 * without MSR bitmaps.
2366 */
560b7ee1
JK		 2367 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2368 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2369
3dcdf3ec
JK		 2370 /* We support free control of CR3 access interception. */
2371 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2372 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2373
b87a51ae
NHE		 2374 /* secondary cpu-based controls */
2375 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2376 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2377 nested_vmx_secondary_ctls_low = 0;
2378 nested_vmx_secondary_ctls_high &=
d6851fbe 2379 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2380 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2381 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2382
afa61f75
NHE		 2383 if (enable_ept) {
2384 /* nested EPT: emulate EPT also to L1 */
2385 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2386 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2387 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2388 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2389 nested_vmx_ept_caps &= vmx_capability.ept;
2390 /*
4b855078
BD		 2391 * For nested guests, we don't do anything specific
2392 * for single context invalidation. Hence, only advertise
2393 * support for global context invalidation.
afa61f75 2394 */
4b855078 2395 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2396 } else
2397 nested_vmx_ept_caps = 0;
2398
c18911a2
JK		 2399 /* miscellaneous data */
2400 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2401 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2402 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2403 VMX_MISC_ACTIVITY_HLT;
c18911a2 2404 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2405}
2406
2407static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2408{
2409 /*
2410 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2411 */
2412 return ((control & high) | low) == control;
2413}
2414
2415static inline u64 vmx_control_msr(u32 low, u32 high)
2416{
2417 return low | ((u64)high << 32);
2418}
2419
cae50139 2420/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2421static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2422{
b87a51ae 2423 switch (msr_index) {
b87a51ae
NHE		 2424 case MSR_IA32_VMX_BASIC:
2425 /*
2426 * This MSR reports some information about VMX support. We
2427 * should return information about the VMX we emulate for the
2428 * guest, and the VMCS structure we give it - not about the
2429 * VMX support of the underlying hardware.
2430 */
3dbcd8da 2431 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2432 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2433 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2434 break;
2435 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2436 case MSR_IA32_VMX_PINBASED_CTLS:
2437 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2438 nested_vmx_pinbased_ctls_high);
2439 break;
2440 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2441 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2442 nested_vmx_procbased_ctls_high);
2443 break;
b87a51ae
NHE		 2444 case MSR_IA32_VMX_PROCBASED_CTLS:
2445 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2446 nested_vmx_procbased_ctls_high);
2447 break;
2448 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2449 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2450 nested_vmx_exit_ctls_high);
2451 break;
b87a51ae
NHE		 2452 case MSR_IA32_VMX_EXIT_CTLS:
2453 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2454 nested_vmx_exit_ctls_high);
2455 break;
2456 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2457 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2458 nested_vmx_entry_ctls_high);
2459 break;
b87a51ae
NHE		 2460 case MSR_IA32_VMX_ENTRY_CTLS:
2461 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2462 nested_vmx_entry_ctls_high);
2463 break;
2464 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2465 *pdata = vmx_control_msr(nested_vmx_misc_low,
2466 nested_vmx_misc_high);
b87a51ae
NHE		 2467 break;
2468 /*
2469 * These MSRs specify bits which the guest must keep fixed (on or off)
2470 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2471 * We picked the standard core2 setting.
2472 */
2473#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2474#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2475 case MSR_IA32_VMX_CR0_FIXED0:
2476 *pdata = VMXON_CR0_ALWAYSON;
2477 break;
2478 case MSR_IA32_VMX_CR0_FIXED1:
2479 *pdata = -1ULL;
2480 break;
2481 case MSR_IA32_VMX_CR4_FIXED0:
2482 *pdata = VMXON_CR4_ALWAYSON;
2483 break;
2484 case MSR_IA32_VMX_CR4_FIXED1:
2485 *pdata = -1ULL;
2486 break;
2487 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2488 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2489 break;
2490 case MSR_IA32_VMX_PROCBASED_CTLS2:
2491 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2492 nested_vmx_secondary_ctls_high);
2493 break;
2494 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2495 /* Currently, no nested vpid support */
2496 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2497 break;
2498 default:
b87a51ae 2499 return 1;
b3897a49
NHE		 2500 }
2501
b87a51ae
NHE		 2502 return 0;
2503}
2504
6aa8b732
AK		 2505/*
2506 * Reads an msr value (of 'msr_index') into 'pdata'.
2507 * Returns 0 on success, non-0 otherwise.
2508 * Assumes vcpu_load() was already called.
2509 */
2510static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2511{
2512 u64 data;
26bb0981 2513 struct shared_msr_entry *msr;
6aa8b732
AK		 2514
2515 if (!pdata) {
2516 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2517 return -EINVAL;
2518 }
2519
2520 switch (msr_index) {
05b3e0c2 2521#ifdef CONFIG_X86_64
6aa8b732
AK		 2522 case MSR_FS_BASE:
2523 data = vmcs_readl(GUEST_FS_BASE);
2524 break;
2525 case MSR_GS_BASE:
2526 data = vmcs_readl(GUEST_GS_BASE);
2527 break;
44ea2b17
AK		 2528 case MSR_KERNEL_GS_BASE:
2529 vmx_load_host_state(to_vmx(vcpu));
2530 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2531 break;
26bb0981 2532#endif
6aa8b732 2533 case MSR_EFER:
3bab1f5d 2534 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2535 case MSR_IA32_TSC:
6aa8b732
AK		 2536 data = guest_read_tsc();
2537 break;
2538 case MSR_IA32_SYSENTER_CS:
2539 data = vmcs_read32(GUEST_SYSENTER_CS);
2540 break;
2541 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2542 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2543 break;
2544 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2545 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2546 break;
0dd376e7 2547 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2548 if (!vmx_mpx_supported())
2549 return 1;
0dd376e7
LJ		 2550 data = vmcs_read64(GUEST_BNDCFGS);
2551 break;
cae50139
JK		 2552 case MSR_IA32_FEATURE_CONTROL:
2553 if (!nested_vmx_allowed(vcpu))
2554 return 1;
2555 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2556 break;
2557 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2558 if (!nested_vmx_allowed(vcpu))
2559 return 1;
2560 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2561 case MSR_TSC_AUX:
2562 if (!to_vmx(vcpu)->rdtscp_enabled)
2563 return 1;
2564 /* Otherwise falls through */
6aa8b732 2565 default:
8b9cf98c 2566 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2567 if (msr) {
2568 data = msr->data;
2569 break;
6aa8b732 2570 }
3bab1f5d 2571 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2572 }
2573
2574 *pdata = data;
2575 return 0;
2576}
2577
cae50139
JK		 2578static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2579
6aa8b732
AK		 2580/*
2581 * Writes msr value into into the appropriate "register".
2582 * Returns 0 on success, non-0 otherwise.
2583 * Assumes vcpu_load() was already called.
2584 */
8fe8ab46 2585static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2586{
a2fa3e9f 2587 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2588 struct shared_msr_entry *msr;
2cc51560 2589 int ret = 0;
8fe8ab46
WA		 2590 u32 msr_index = msr_info->index;
2591 u64 data = msr_info->data;
2cc51560 2592
6aa8b732 2593 switch (msr_index) {
3bab1f5d 2594 case MSR_EFER:
8fe8ab46 2595 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2596 break;
16175a79 2597#ifdef CONFIG_X86_64
6aa8b732 2598 case MSR_FS_BASE:
2fb92db1 2599 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2600 vmcs_writel(GUEST_FS_BASE, data);
2601 break;
2602 case MSR_GS_BASE:
2fb92db1 2603 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2604 vmcs_writel(GUEST_GS_BASE, data);
2605 break;
44ea2b17
AK		 2606 case MSR_KERNEL_GS_BASE:
2607 vmx_load_host_state(vmx);
2608 vmx->msr_guest_kernel_gs_base = data;
2609 break;
6aa8b732
AK		 2610#endif
2611 case MSR_IA32_SYSENTER_CS:
2612 vmcs_write32(GUEST_SYSENTER_CS, data);
2613 break;
2614 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2615 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2616 break;
2617 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2618 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2619 break;
0dd376e7 2620 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2621 if (!vmx_mpx_supported())
2622 return 1;
0dd376e7
LJ		 2623 vmcs_write64(GUEST_BNDCFGS, data);
2624 break;
af24a4e4 2625 case MSR_IA32_TSC:
8fe8ab46 2626 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2627 break;
468d472f
SY		 2628 case MSR_IA32_CR_PAT:
2629 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2630 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2631 return 1;
468d472f
SY		 2632 vmcs_write64(GUEST_IA32_PAT, data);
2633 vcpu->arch.pat = data;
2634 break;
2635 }
8fe8ab46 2636 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2637 break;
ba904635
WA		 2638 case MSR_IA32_TSC_ADJUST:
2639 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2640 break;
cae50139
JK		 2641 case MSR_IA32_FEATURE_CONTROL:
2642 if (!nested_vmx_allowed(vcpu) ||
2643 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2644 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2645 return 1;
2646 vmx->nested.msr_ia32_feature_control = data;
2647 if (msr_info->host_initiated && data == 0)
2648 vmx_leave_nested(vcpu);
2649 break;
2650 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2651 return 1; /* they are read-only */
4e47c7a6
SY		 2652 case MSR_TSC_AUX:
2653 if (!vmx->rdtscp_enabled)
2654 return 1;
2655 /* Check reserved bit, higher 32 bits should be zero */
2656 if ((data >> 32) != 0)
2657 return 1;
2658 /* Otherwise falls through */
6aa8b732 2659 default:
8b9cf98c 2660 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2661 if (msr) {
2662 msr->data = data;
2225fd56
AK		 2663 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2664 preempt_disable();
9ee73970
AK		 2665 kvm_set_shared_msr(msr->index, msr->data,
2666 msr->mask);
2225fd56
AK		 2667 preempt_enable();
2668 }
3bab1f5d 2669 break;
6aa8b732 2670 }
8fe8ab46 2671 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2672 }
2673
2cc51560 2674 return ret;
6aa8b732
AK		 2675}
2676
5fdbf976 2677static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2678{
5fdbf976
MT		 2679 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2680 switch (reg) {
2681 case VCPU_REGS_RSP:
2682 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2683 break;
2684 case VCPU_REGS_RIP:
2685 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2686 break;
6de4f3ad
AK		 2687 case VCPU_EXREG_PDPTR:
2688 if (enable_ept)
2689 ept_save_pdptrs(vcpu);
2690 break;
5fdbf976
MT		 2691 default:
2692 break;
2693 }
6aa8b732
AK		 2694}
2695
6aa8b732
AK		 2696static __init int cpu_has_kvm_support(void)
2697{
6210e37b 2698 return cpu_has_vmx();
6aa8b732
AK		 2699}
2700
2701static __init int vmx_disabled_by_bios(void)
2702{
2703 u64 msr;
2704
2705 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2706 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2707 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2708 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2709 && tboot_enabled())
2710 return 1;
23f3e991 2711 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2712 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2713 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2714 && !tboot_enabled()) {
2715 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2716 "activate TXT before enabling KVM\n");
cafd6659 2717 return 1;
f9335afe 2718 }
23f3e991
JC		 2719 /* launched w/o TXT and VMX disabled */
2720 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2721 && !tboot_enabled())
2722 return 1;
cafd6659
SW		 2723 }
2724
2725 return 0;
6aa8b732
AK		 2726}
2727
7725b894
DX		 2728static void kvm_cpu_vmxon(u64 addr)
2729{
2730 asm volatile (ASM_VMX_VMXON_RAX
2731 : : "a"(&addr), "m"(addr)
2732 : "memory", "cc");
2733}
2734
13a34e06 2735static int hardware_enable(void)
6aa8b732
AK		 2736{
2737 int cpu = raw_smp_processor_id();
2738 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2739 u64 old, test_bits;
6aa8b732 2740
10474ae8
AG		 2741 if (read_cr4() & X86_CR4_VMXE)
2742 return -EBUSY;
2743
d462b819 2744 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2745
2746 /*
2747 * Now we can enable the vmclear operation in kdump
2748 * since the loaded_vmcss_on_cpu list on this cpu
2749 * has been initialized.
2750 *
2751 * Though the cpu is not in VMX operation now, there
2752 * is no problem to enable the vmclear operation
2753 * for the loaded_vmcss_on_cpu list is empty!
2754 */
2755 crash_enable_local_vmclear(cpu);
2756
6aa8b732 2757 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2758
2759 test_bits = FEATURE_CONTROL_LOCKED;
2760 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2761 if (tboot_enabled())
2762 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2763
2764 if ((old & test_bits) != test_bits) {
6aa8b732 2765 /* enable and lock */
cafd6659
SW		 2766 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2767 }
66aee91a 2768 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2769
4610c9cc
DX		 2770 if (vmm_exclusive) {
2771 kvm_cpu_vmxon(phys_addr);
2772 ept_sync_global();
2773 }
10474ae8 2774
89cbc767 2775 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2776
10474ae8 2777 return 0;
6aa8b732
AK		 2778}
2779
d462b819 2780static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2781{
2782 int cpu = raw_smp_processor_id();
d462b819 2783 struct loaded_vmcs *v, *n;
543e4243 2784
d462b819
NHE		 2785 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2786 loaded_vmcss_on_cpu_link)
2787 __loaded_vmcs_clear(v);
543e4243
AK		 2788}
2789
710ff4a8
EH		 2790
2791/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2792 * tricks.
2793 */
2794static void kvm_cpu_vmxoff(void)
6aa8b732 2795{
4ecac3fd 2796 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2797}
2798
13a34e06 2799static void hardware_disable(void)
710ff4a8 2800{
4610c9cc 2801 if (vmm_exclusive) {
d462b819 2802 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2803 kvm_cpu_vmxoff();
2804 }
7725b894 2805 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2806}
2807
1c3d14fe 2808static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2809 u32 msr, u32 *result)
1c3d14fe
YS		 2810{
2811 u32 vmx_msr_low, vmx_msr_high;
2812 u32 ctl = ctl_min | ctl_opt;
2813
2814 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2815
2816 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2817 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2818
2819 /* Ensure minimum (required) set of control bits are supported. */
2820 if (ctl_min & ~ctl)
002c7f7c 2821 return -EIO;
1c3d14fe
YS		 2822
2823 *result = ctl;
2824 return 0;
2825}
2826
110312c8
AK		 2827static __init bool allow_1_setting(u32 msr, u32 ctl)
2828{
2829 u32 vmx_msr_low, vmx_msr_high;
2830
2831 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2832 return vmx_msr_high & ctl;
2833}
2834
002c7f7c 2835static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2836{
2837 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2838 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2839 u32 _pin_based_exec_control = 0;
2840 u32 _cpu_based_exec_control = 0;
f78e0e2e 2841 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2842 u32 _vmexit_control = 0;
2843 u32 _vmentry_control = 0;
2844
10166744 2845 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2846#ifdef CONFIG_X86_64
2847 CPU_BASED_CR8_LOAD_EXITING |
2848 CPU_BASED_CR8_STORE_EXITING |
2849#endif
d56f546d
SY		 2850 CPU_BASED_CR3_LOAD_EXITING |
2851 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2852 CPU_BASED_USE_IO_BITMAPS |
2853 CPU_BASED_MOV_DR_EXITING |
a7052897 2854 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2855 CPU_BASED_MWAIT_EXITING |
2856 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2857 CPU_BASED_INVLPG_EXITING |
2858 CPU_BASED_RDPMC_EXITING;
443381a8 2859
f78e0e2e 2860 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2861 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2863 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2864 &_cpu_based_exec_control) < 0)
002c7f7c 2865 return -EIO;
6e5d865c
YS		 2866#ifdef CONFIG_X86_64
2867 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2868 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2869 ~CPU_BASED_CR8_STORE_EXITING;
2870#endif
f78e0e2e 2871 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2872 min2 = 0;
2873 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2875 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2876 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2877 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2878 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2879 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2880 SECONDARY_EXEC_RDTSCP |
83d4c286 2881 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2882 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2883 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2884 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2885 if (adjust_vmx_controls(min2, opt2,
2886 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2887 &_cpu_based_2nd_exec_control) < 0)
2888 return -EIO;
2889 }
2890#ifndef CONFIG_X86_64
2891 if (!(_cpu_based_2nd_exec_control &
2892 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2893 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2894#endif
83d4c286
YZ		 2895
2896 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2897 _cpu_based_2nd_exec_control &= ~(
8d14695f 2898 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2899 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2900 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2901
d56f546d 2902 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2903 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2904 enabled */
5fff7d27
GN		 2905 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2906 CPU_BASED_CR3_STORE_EXITING |
2907 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2908 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2909 vmx_capability.ept, vmx_capability.vpid);
2910 }
1c3d14fe 2911
81908bf4 2912 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2913#ifdef CONFIG_X86_64
2914 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2915#endif
a547c6db 2916 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2917 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2918 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2919 &_vmexit_control) < 0)
002c7f7c 2920 return -EIO;
1c3d14fe 2921
01e439be
YZ		 2922 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2923 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2924 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2925 &_pin_based_exec_control) < 0)
2926 return -EIO;
2927
2928 if (!(_cpu_based_2nd_exec_control &
2929 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2930 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2931 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2932
c845f9c6 2933 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2934 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2935 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2936 &_vmentry_control) < 0)
002c7f7c 2937 return -EIO;
6aa8b732 2938
c68876fd 2939 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2940
2941 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2942 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2943 return -EIO;
1c3d14fe
YS		 2944
2945#ifdef CONFIG_X86_64
2946 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2947 if (vmx_msr_high & (1u<<16))
002c7f7c 2948 return -EIO;
1c3d14fe
YS		 2949#endif
2950
2951 /* Require Write-Back (WB) memory type for VMCS accesses. */
2952 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2953 return -EIO;
1c3d14fe 2954
002c7f7c
YS		 2955 vmcs_conf->size = vmx_msr_high & 0x1fff;
2956 vmcs_conf->order = get_order(vmcs_config.size);
2957 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2958
002c7f7c
YS		 2959 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2960 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2961 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2962 vmcs_conf->vmexit_ctrl = _vmexit_control;
2963 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2964
110312c8
AK		 2965 cpu_has_load_ia32_efer =
2966 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2967 VM_ENTRY_LOAD_IA32_EFER)
2968 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2969 VM_EXIT_LOAD_IA32_EFER);
2970
8bf00a52
GN		 2971 cpu_has_load_perf_global_ctrl =
2972 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2973 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2974 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2975 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2976
2977 /*
2978 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2979 * but due to arrata below it can't be used. Workaround is to use
2980 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2981 *
2982 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2983 *
2984 * AAK155 (model 26)
2985 * AAP115 (model 30)
2986 * AAT100 (model 37)
2987 * BC86,AAY89,BD102 (model 44)
2988 * BA97 (model 46)
2989 *
2990 */
2991 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2992 switch (boot_cpu_data.x86_model) {
2993 case 26:
2994 case 30:
2995 case 37:
2996 case 44:
2997 case 46:
2998 cpu_has_load_perf_global_ctrl = false;
2999 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3000 "does not work properly. Using workaround\n");
3001 break;
3002 default:
3003 break;
3004 }
3005 }
3006
1c3d14fe 3007 return 0;
c68876fd 3008}
6aa8b732
AK		 3009
3010static struct vmcs *alloc_vmcs_cpu(int cpu)
3011{
3012 int node = cpu_to_node(cpu);
3013 struct page *pages;
3014 struct vmcs *vmcs;
3015
6484eb3e 3016 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3017 if (!pages)
3018 return NULL;
3019 vmcs = page_address(pages);
1c3d14fe
YS		 3020 memset(vmcs, 0, vmcs_config.size);
3021 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3022 return vmcs;
3023}
3024
3025static struct vmcs *alloc_vmcs(void)
3026{
d3b2c338 3027 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3028}
3029
3030static void free_vmcs(struct vmcs *vmcs)
3031{
1c3d14fe 3032 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3033}
3034
d462b819
NHE		 3035/*
3036 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3037 */
3038static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3039{
3040 if (!loaded_vmcs->vmcs)
3041 return;
3042 loaded_vmcs_clear(loaded_vmcs);
3043 free_vmcs(loaded_vmcs->vmcs);
3044 loaded_vmcs->vmcs = NULL;
3045}
3046
39959588 3047static void free_kvm_area(void)
6aa8b732
AK		 3048{
3049 int cpu;
3050
3230bb47 3051 for_each_possible_cpu(cpu) {
6aa8b732 3052 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3053 per_cpu(vmxarea, cpu) = NULL;
3054 }
6aa8b732
AK		 3055}
3056
fe2b201b
BD		 3057static void init_vmcs_shadow_fields(void)
3058{
3059 int i, j;
3060
3061 /* No checks for read only fields yet */
3062
3063 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3064 switch (shadow_read_write_fields[i]) {
3065 case GUEST_BNDCFGS:
3066 if (!vmx_mpx_supported())
3067 continue;
3068 break;
3069 default:
3070 break;
3071 }
3072
3073 if (j < i)
3074 shadow_read_write_fields[j] =
3075 shadow_read_write_fields[i];
3076 j++;
3077 }
3078 max_shadow_read_write_fields = j;
3079
3080 /* shadowed fields guest access without vmexit */
3081 for (i = 0; i < max_shadow_read_write_fields; i++) {
3082 clear_bit(shadow_read_write_fields[i],
3083 vmx_vmwrite_bitmap);
3084 clear_bit(shadow_read_write_fields[i],
3085 vmx_vmread_bitmap);
3086 }
3087 for (i = 0; i < max_shadow_read_only_fields; i++)
3088 clear_bit(shadow_read_only_fields[i],
3089 vmx_vmread_bitmap);
3090}
3091
6aa8b732
AK		 3092static __init int alloc_kvm_area(void)
3093{
3094 int cpu;
3095
3230bb47 3096 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3097 struct vmcs *vmcs;
3098
3099 vmcs = alloc_vmcs_cpu(cpu);
3100 if (!vmcs) {
3101 free_kvm_area();
3102 return -ENOMEM;
3103 }
3104
3105 per_cpu(vmxarea, cpu) = vmcs;
3106 }
3107 return 0;
3108}
3109
3110static __init int hardware_setup(void)
3111{
002c7f7c
YS		 3112 if (setup_vmcs_config(&vmcs_config) < 0)
3113 return -EIO;
50a37eb4
JR		 3114
3115 if (boot_cpu_has(X86_FEATURE_NX))
3116 kvm_enable_efer_bits(EFER_NX);
3117
93ba03c2
SY		 3118 if (!cpu_has_vmx_vpid())
3119 enable_vpid = 0;
abc4fc58
AG		 3120 if (!cpu_has_vmx_shadow_vmcs())
3121 enable_shadow_vmcs = 0;
fe2b201b
BD		 3122 if (enable_shadow_vmcs)
3123 init_vmcs_shadow_fields();
93ba03c2 3124
4bc9b982
SY		 3125 if (!cpu_has_vmx_ept() ||
3126 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3127 enable_ept = 0;
3a624e29 3128 enable_unrestricted_guest = 0;
83c3a331 3129 enable_ept_ad_bits = 0;
3a624e29
NK		 3130 }
3131
83c3a331
XH		 3132 if (!cpu_has_vmx_ept_ad_bits())
3133 enable_ept_ad_bits = 0;
3134
3a624e29
NK		 3135 if (!cpu_has_vmx_unrestricted_guest())
3136 enable_unrestricted_guest = 0;
93ba03c2 3137
38b99173 3138 if (!cpu_has_vmx_flexpriority()) {
93ba03c2
SY		 3139 flexpriority_enabled = 0;
3140
38b99173
TC		 3141 /*
3142 * set_apic_access_page_addr() is used to reload apic access
3143 * page upon invalidation. No need to do anything if the
3144 * processor does not have the APIC_ACCESS_ADDR VMCS field.
3145 */
3146 kvm_x86_ops->set_apic_access_page_addr = NULL;
3147 }
3148
95ba8273
GN		 3149 if (!cpu_has_vmx_tpr_shadow())
3150 kvm_x86_ops->update_cr8_intercept = NULL;
3151
54dee993
MT		 3152 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3153 kvm_disable_largepages();
3154
4b8d54f9
ZE		 3155 if (!cpu_has_vmx_ple())
3156 ple_gap = 0;
3157
01e439be
YZ		 3158 if (!cpu_has_vmx_apicv())
3159 enable_apicv = 0;
c7c9c56c 3160
01e439be 3161 if (enable_apicv)
c7c9c56c 3162 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3163 else {
c7c9c56c 3164 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3165 kvm_x86_ops->deliver_posted_interrupt = NULL;
3166 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3167 }
83d4c286 3168
b87a51ae
NHE		 3169 if (nested)
3170 nested_vmx_setup_ctls_msrs();
3171
6aa8b732
AK		 3172 return alloc_kvm_area();
3173}
3174
3175static __exit void hardware_unsetup(void)
3176{
3177 free_kvm_area();
3178}
3179
14168786
GN		 3180static bool emulation_required(struct kvm_vcpu *vcpu)
3181{
3182 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3183}
3184
91b0aa2c 3185static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3186 struct kvm_segment *save)
6aa8b732 3187{
d99e4152
GN		 3188 if (!emulate_invalid_guest_state) {
3189 /*
3190 * CS and SS RPL should be equal during guest entry according
3191 * to VMX spec, but in reality it is not always so. Since vcpu
3192 * is in the middle of the transition from real mode to
3193 * protected mode it is safe to assume that RPL 0 is a good
3194 * default value.
3195 */
3196 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3197 save->selector &= ~SELECTOR_RPL_MASK;
3198 save->dpl = save->selector & SELECTOR_RPL_MASK;
3199 save->s = 1;
6aa8b732 3200 }
d99e4152 3201 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3202}
3203
3204static void enter_pmode(struct kvm_vcpu *vcpu)
3205{
3206 unsigned long flags;
a89a8fb9 3207 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3208
d99e4152
GN		 3209 /*
3210 * Update real mode segment cache. It may be not up-to-date if sement
3211 * register was written while vcpu was in a guest mode.
3212 */
3213 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3214 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3215 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3216 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3217 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3218 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3219
7ffd92c5 3220 vmx->rmode.vm86_active = 0;
6aa8b732 3221
2fb92db1
AK		 3222 vmx_segment_cache_clear(vmx);
3223
f5f7b2fe 3224 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3225
3226 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3227 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3228 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3229 vmcs_writel(GUEST_RFLAGS, flags);
3230
66aee91a
RR		 3231 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3232 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3233
3234 update_exception_bitmap(vcpu);
3235
91b0aa2c
GN		 3236 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3237 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3238 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3239 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3240 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3241 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3242}
3243
f5f7b2fe 3244static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3245{
772e0318 3246 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3247 struct kvm_segment var = *save;
3248
3249 var.dpl = 0x3;
3250 if (seg == VCPU_SREG_CS)
3251 var.type = 0x3;
3252
3253 if (!emulate_invalid_guest_state) {
3254 var.selector = var.base >> 4;
3255 var.base = var.base & 0xffff0;
3256 var.limit = 0xffff;
3257 var.g = 0;
3258 var.db = 0;
3259 var.present = 1;
3260 var.s = 1;
3261 var.l = 0;
3262 var.unusable = 0;
3263 var.type = 0x3;
3264 var.avl = 0;
3265 if (save->base & 0xf)
3266 printk_once(KERN_WARNING "kvm: segment base is not "
3267 "paragraph aligned when entering "
3268 "protected mode (seg=%d)", seg);
3269 }
6aa8b732 3270
d99e4152
GN		 3271 vmcs_write16(sf->selector, var.selector);
3272 vmcs_write32(sf->base, var.base);
3273 vmcs_write32(sf->limit, var.limit);
3274 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3275}
3276
3277static void enter_rmode(struct kvm_vcpu *vcpu)
3278{
3279 unsigned long flags;
a89a8fb9 3280 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3281
f5f7b2fe
AK		 3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3287 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3289
7ffd92c5 3290 vmx->rmode.vm86_active = 1;
6aa8b732 3291
776e58ea
GN		 3292 /*
3293 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3294 * vcpu. Warn the user that an update is overdue.
776e58ea 3295 */
4918c6ca 3296 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3297 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3298 "called before entering vcpu\n");
776e58ea 3299
2fb92db1
AK		 3300 vmx_segment_cache_clear(vmx);
3301
4918c6ca 3302 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3303 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3304 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3305
3306 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3307 vmx->rmode.save_rflags = flags;
6aa8b732 3308
053de044 3309 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3310
3311 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3312 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3313 update_exception_bitmap(vcpu);
3314
d99e4152
GN		 3315 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3316 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3317 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3318 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3319 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3320 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3321
8668a3c4 3322 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3323}
3324
401d10de
AS		 3325static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3326{
3327 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3328 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3329
3330 if (!msr)
3331 return;
401d10de 3332
44ea2b17
AK		 3333 /*
3334 * Force kernel_gs_base reloading before EFER changes, as control
3335 * of this msr depends on is_long_mode().
3336 */
3337 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3338 vcpu->arch.efer = efer;
401d10de 3339 if (efer & EFER_LMA) {
2961e876 3340 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3341 msr->data = efer;
3342 } else {
2961e876 3343 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3344
3345 msr->data = efer & ~EFER_LME;
3346 }
3347 setup_msrs(vmx);
3348}
3349
05b3e0c2 3350#ifdef CONFIG_X86_64
6aa8b732
AK		 3351
3352static void enter_lmode(struct kvm_vcpu *vcpu)
3353{
3354 u32 guest_tr_ar;
3355
2fb92db1
AK		 3356 vmx_segment_cache_clear(to_vmx(vcpu));
3357
6aa8b732
AK		 3358 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3359 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3360 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3361 __func__);
6aa8b732
AK		 3362 vmcs_write32(GUEST_TR_AR_BYTES,
3363 (guest_tr_ar & ~AR_TYPE_MASK)
3364 | AR_TYPE_BUSY_64_TSS);
3365 }
da38f438 3366 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3367}
3368
3369static void exit_lmode(struct kvm_vcpu *vcpu)
3370{
2961e876 3371 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3372 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3373}
3374
3375#endif
3376
2384d2b3
SY		 3377static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3378{
b9d762fa 3379 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3380 if (enable_ept) {
3381 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3382 return;
4e1096d2 3383 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3384 }
2384d2b3
SY		 3385}
3386
e8467fda
AK		 3387static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3388{
3389 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3390
3391 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3392 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3393}
3394
aff48baa
AK		 3395static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3396{
3397 if (enable_ept && is_paging(vcpu))
3398 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3399 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3400}
3401
25c4c276 3402static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3403{
fc78f519
AK		 3404 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3405
3406 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3407 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3408}
3409
1439442c
SY		 3410static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3411{
d0d538b9
GN		 3412 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3413
6de4f3ad
AK		 3414 if (!test_bit(VCPU_EXREG_PDPTR,
3415 (unsigned long *)&vcpu->arch.regs_dirty))
3416 return;
3417
1439442c 3418 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3419 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3420 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3421 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3422 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3423 }
3424}
3425
8f5d549f
AK		 3426static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3427{
d0d538b9
GN		 3428 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3429
8f5d549f 3430 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3431 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3432 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3433 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3434 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3435 }
6de4f3ad
AK		 3436
3437 __set_bit(VCPU_EXREG_PDPTR,
3438 (unsigned long *)&vcpu->arch.regs_avail);
3439 __set_bit(VCPU_EXREG_PDPTR,
3440 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3441}
3442
5e1746d6 3443static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3444
3445static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3446 unsigned long cr0,
3447 struct kvm_vcpu *vcpu)
3448{
5233dd51
MT		 3449 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3450 vmx_decache_cr3(vcpu);
1439442c
SY		 3451 if (!(cr0 & X86_CR0_PG)) {
3452 /* From paging/starting to nonpaging */
3453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3454 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3455 (CPU_BASED_CR3_LOAD_EXITING |
3456 CPU_BASED_CR3_STORE_EXITING));
3457 vcpu->arch.cr0 = cr0;
fc78f519 3458 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3459 } else if (!is_paging(vcpu)) {
3460 /* From nonpaging to paging */
3461 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3462 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3463 ~(CPU_BASED_CR3_LOAD_EXITING |
3464 CPU_BASED_CR3_STORE_EXITING));
3465 vcpu->arch.cr0 = cr0;
fc78f519 3466 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3467 }
95eb84a7
SY		 3468
3469 if (!(cr0 & X86_CR0_WP))
3470 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3471}
3472
6aa8b732
AK		 3473static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3474{
7ffd92c5 3475 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3476 unsigned long hw_cr0;
3477
5037878e 3478 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3479 if (enable_unrestricted_guest)
5037878e 3480 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3481 else {
5037878e 3482 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3483
218e763f
GN		 3484 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3485 enter_pmode(vcpu);
6aa8b732 3486
218e763f
GN		 3487 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3488 enter_rmode(vcpu);
3489 }
6aa8b732 3490
05b3e0c2 3491#ifdef CONFIG_X86_64
f6801dff 3492 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3493 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3494 enter_lmode(vcpu);
707d92fa 3495 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3496 exit_lmode(vcpu);
3497 }
3498#endif
3499
089d034e 3500 if (enable_ept)
1439442c
SY		 3501 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3502
02daab21 3503 if (!vcpu->fpu_active)
81231c69 3504 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3505
6aa8b732 3506 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3507 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3508 vcpu->arch.cr0 = cr0;
14168786
GN		 3509
3510 /* depends on vcpu->arch.cr0 to be set to a new value */
3511 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3512}
3513
1439442c
SY		 3514static u64 construct_eptp(unsigned long root_hpa)
3515{
3516 u64 eptp;
3517
3518 /* TODO write the value reading from MSR */
3519 eptp = VMX_EPT_DEFAULT_MT |
3520 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3521 if (enable_ept_ad_bits)
3522 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3523 eptp |= (root_hpa & PAGE_MASK);
3524
3525 return eptp;
3526}
3527
6aa8b732
AK		 3528static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3529{
1439442c
SY		 3530 unsigned long guest_cr3;
3531 u64 eptp;
3532
3533 guest_cr3 = cr3;
089d034e 3534 if (enable_ept) {
1439442c
SY		 3535 eptp = construct_eptp(cr3);
3536 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3537 if (is_paging(vcpu) || is_guest_mode(vcpu))
3538 guest_cr3 = kvm_read_cr3(vcpu);
3539 else
3540 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3541 ept_load_pdptrs(vcpu);
1439442c
SY		 3542 }
3543
2384d2b3 3544 vmx_flush_tlb(vcpu);
1439442c 3545 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3546}
3547
5e1746d6 3548static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3549{
7ffd92c5 3550 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3551 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3552
5e1746d6
NHE		 3553 if (cr4 & X86_CR4_VMXE) {
3554 /*
3555 * To use VMXON (and later other VMX instructions), a guest
3556 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3557 * So basically the check on whether to allow nested VMX
3558 * is here.
3559 */
3560 if (!nested_vmx_allowed(vcpu))
3561 return 1;
1a0d74e6
JK		 3562 }
3563 if (to_vmx(vcpu)->nested.vmxon &&
3564 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3565 return 1;
3566
ad312c7c 3567 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3568 if (enable_ept) {
3569 if (!is_paging(vcpu)) {
3570 hw_cr4 &= ~X86_CR4_PAE;
3571 hw_cr4 |= X86_CR4_PSE;
c08800a5 3572 /*
e1e746b3
FW		 3573 * SMEP/SMAP is disabled if CPU is in non-paging mode
3574 * in hardware. However KVM always uses paging mode to
c08800a5 3575 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3576 * To emulate this behavior, SMEP/SMAP needs to be
3577 * manually disabled when guest switches to non-paging
3578 * mode.
c08800a5 3579 */
e1e746b3 3580 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3581 } else if (!(cr4 & X86_CR4_PAE)) {
3582 hw_cr4 &= ~X86_CR4_PAE;
3583 }
3584 }
1439442c
SY		 3585
3586 vmcs_writel(CR4_READ_SHADOW, cr4);
3587 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3588 return 0;
6aa8b732
AK		 3589}
3590
6aa8b732
AK		 3591static void vmx_get_segment(struct kvm_vcpu *vcpu,
3592 struct kvm_segment *var, int seg)
3593{
a9179499 3594 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3595 u32 ar;
3596
c6ad1153 3597 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3598 *var = vmx->rmode.segs[seg];
a9179499 3599 if (seg == VCPU_SREG_TR
2fb92db1 3600 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3601 return;
1390a28b
AK		 3602 var->base = vmx_read_guest_seg_base(vmx, seg);
3603 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3604 return;
a9179499 3605 }
2fb92db1
AK		 3606 var->base = vmx_read_guest_seg_base(vmx, seg);
3607 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3608 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3609 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3610 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3611 var->type = ar & 15;
3612 var->s = (ar >> 4) & 1;
3613 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3614 /*
3615 * Some userspaces do not preserve unusable property. Since usable
3616 * segment has to be present according to VMX spec we can use present
3617 * property to amend userspace bug by making unusable segment always
3618 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3619 * segment as unusable.
3620 */
3621 var->present = !var->unusable;
6aa8b732
AK		 3622 var->avl = (ar >> 12) & 1;
3623 var->l = (ar >> 13) & 1;
3624 var->db = (ar >> 14) & 1;
3625 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3626}
3627
a9179499
AK		 3628static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3629{
a9179499
AK		 3630 struct kvm_segment s;
3631
3632 if (to_vmx(vcpu)->rmode.vm86_active) {
3633 vmx_get_segment(vcpu, &s, seg);
3634 return s.base;
3635 }
2fb92db1 3636 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3637}
3638
b09408d0 3639static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3640{
b09408d0
MT		 3641 struct vcpu_vmx *vmx = to_vmx(vcpu);
3642
ae9fedc7 3643 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3644 return 0;
ae9fedc7
PB		 3645 else {
3646 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3647 return AR_DPL(ar);
69c73028 3648 }
69c73028
AK		 3649}
3650
653e3108 3651static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3652{
6aa8b732
AK		 3653 u32 ar;
3654
f0495f9b 3655 if (var->unusable || !var->present)
6aa8b732
AK		 3656 ar = 1 << 16;
3657 else {
3658 ar = var->type & 15;
3659 ar |= (var->s & 1) << 4;
3660 ar |= (var->dpl & 3) << 5;
3661 ar |= (var->present & 1) << 7;
3662 ar |= (var->avl & 1) << 12;
3663 ar |= (var->l & 1) << 13;
3664 ar |= (var->db & 1) << 14;
3665 ar |= (var->g & 1) << 15;
3666 }
653e3108
AK		 3667
3668 return ar;
3669}
3670
3671static void vmx_set_segment(struct kvm_vcpu *vcpu,
3672 struct kvm_segment *var, int seg)
3673{
7ffd92c5 3674 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3675 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3676
2fb92db1
AK		 3677 vmx_segment_cache_clear(vmx);
3678
1ecd50a9
GN		 3679 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3680 vmx->rmode.segs[seg] = *var;
3681 if (seg == VCPU_SREG_TR)
3682 vmcs_write16(sf->selector, var->selector);
3683 else if (var->s)
3684 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3685 goto out;
653e3108 3686 }
1ecd50a9 3687
653e3108
AK		 3688 vmcs_writel(sf->base, var->base);
3689 vmcs_write32(sf->limit, var->limit);
3690 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3691
3692 /*
3693 * Fix the "Accessed" bit in AR field of segment registers for older
3694 * qemu binaries.
3695 * IA32 arch specifies that at the time of processor reset the
3696 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3697 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3698 * state vmexit when "unrestricted guest" mode is turned on.
3699 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3700 * tree. Newer qemu binaries with that qemu fix would not need this
3701 * kvm hack.
3702 */
3703 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3704 var->type |= 0x1; /* Accessed */
3a624e29 3705
f924d66d 3706 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3707
3708out:
98eb2f8b 3709 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3710}
3711
6aa8b732
AK		 3712static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3713{
2fb92db1 3714 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3715
3716 *db = (ar >> 14) & 1;
3717 *l = (ar >> 13) & 1;
3718}
3719
89a27f4d 3720static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3721{
89a27f4d
GN		 3722 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3723 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3724}
3725
89a27f4d 3726static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3727{
89a27f4d
GN		 3728 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3729 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3730}
3731
89a27f4d 3732static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3733{
89a27f4d
GN		 3734 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3735 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3736}
3737
89a27f4d 3738static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3739{
89a27f4d
GN		 3740 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3741 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3742}
3743
648dfaa7
MG		 3744static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3745{
3746 struct kvm_segment var;
3747 u32 ar;
3748
3749 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3750 var.dpl = 0x3;
0647f4aa
GN		 3751 if (seg == VCPU_SREG_CS)
3752 var.type = 0x3;
648dfaa7
MG		 3753 ar = vmx_segment_access_rights(&var);
3754
3755 if (var.base != (var.selector << 4))
3756 return false;
89efbed0 3757 if (var.limit != 0xffff)
648dfaa7 3758 return false;
07f42f5f 3759 if (ar != 0xf3)
648dfaa7
MG		 3760 return false;
3761
3762 return true;
3763}
3764
3765static bool code_segment_valid(struct kvm_vcpu *vcpu)
3766{
3767 struct kvm_segment cs;
3768 unsigned int cs_rpl;
3769
3770 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3771 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3772
1872a3f4
AK		 3773 if (cs.unusable)
3774 return false;
648dfaa7
MG		 3775 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3776 return false;
3777 if (!cs.s)
3778 return false;
1872a3f4 3779 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3780 if (cs.dpl > cs_rpl)
3781 return false;
1872a3f4 3782 } else {
648dfaa7
MG		 3783 if (cs.dpl != cs_rpl)
3784 return false;
3785 }
3786 if (!cs.present)
3787 return false;
3788
3789 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3790 return true;
3791}
3792
3793static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3794{
3795 struct kvm_segment ss;
3796 unsigned int ss_rpl;
3797
3798 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3799 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3800
1872a3f4
AK		 3801 if (ss.unusable)
3802 return true;
3803 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3804 return false;
3805 if (!ss.s)
3806 return false;
3807 if (ss.dpl != ss_rpl) /* DPL != RPL */
3808 return false;
3809 if (!ss.present)
3810 return false;
3811
3812 return true;
3813}
3814
3815static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3816{
3817 struct kvm_segment var;
3818 unsigned int rpl;
3819
3820 vmx_get_segment(vcpu, &var, seg);
3821 rpl = var.selector & SELECTOR_RPL_MASK;
3822
1872a3f4
AK		 3823 if (var.unusable)
3824 return true;
648dfaa7
MG		 3825 if (!var.s)
3826 return false;
3827 if (!var.present)
3828 return false;
3829 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3830 if (var.dpl < rpl) /* DPL < RPL */
3831 return false;
3832 }
3833
3834 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3835 * rights flags
3836 */
3837 return true;
3838}
3839
3840static bool tr_valid(struct kvm_vcpu *vcpu)
3841{
3842 struct kvm_segment tr;
3843
3844 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3845
1872a3f4
AK		 3846 if (tr.unusable)
3847 return false;
648dfaa7
MG		 3848 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3849 return false;
1872a3f4 3850 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3851 return false;
3852 if (!tr.present)
3853 return false;
3854
3855 return true;
3856}
3857
3858static bool ldtr_valid(struct kvm_vcpu *vcpu)
3859{
3860 struct kvm_segment ldtr;
3861
3862 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3863
1872a3f4
AK		 3864 if (ldtr.unusable)
3865 return true;
648dfaa7
MG		 3866 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3867 return false;
3868 if (ldtr.type != 2)
3869 return false;
3870 if (!ldtr.present)
3871 return false;
3872
3873 return true;
3874}
3875
3876static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3877{
3878 struct kvm_segment cs, ss;
3879
3880 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3881 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3882
3883 return ((cs.selector & SELECTOR_RPL_MASK) ==
3884 (ss.selector & SELECTOR_RPL_MASK));
3885}
3886
3887/*
3888 * Check if guest state is valid. Returns true if valid, false if
3889 * not.
3890 * We assume that registers are always usable
3891 */
3892static bool guest_state_valid(struct kvm_vcpu *vcpu)
3893{
c5e97c80
GN		 3894 if (enable_unrestricted_guest)
3895 return true;
3896
648dfaa7 3897 /* real mode guest state checks */
f13882d8 3898 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3899 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3900 return false;
3901 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3902 return false;
3903 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3904 return false;
3905 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3906 return false;
3907 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3908 return false;
3909 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3910 return false;
3911 } else {
3912 /* protected mode guest state checks */
3913 if (!cs_ss_rpl_check(vcpu))
3914 return false;
3915 if (!code_segment_valid(vcpu))
3916 return false;
3917 if (!stack_segment_valid(vcpu))
3918 return false;
3919 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3920 return false;
3921 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3922 return false;
3923 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3924 return false;
3925 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3926 return false;
3927 if (!tr_valid(vcpu))
3928 return false;
3929 if (!ldtr_valid(vcpu))
3930 return false;
3931 }
3932 /* TODO:
3933 * - Add checks on RIP
3934 * - Add checks on RFLAGS
3935 */
3936
3937 return true;
3938}
3939
d77c26fc 3940static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3941{
40dcaa9f 3942 gfn_t fn;
195aefde 3943 u16 data = 0;
1f755a82 3944 int idx, r;
6aa8b732 3945
40dcaa9f 3946 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3947 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3948 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3949 if (r < 0)
10589a46 3950 goto out;
195aefde 3951 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3952 r = kvm_write_guest_page(kvm, fn++, &data,
3953 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3954 if (r < 0)
10589a46 3955 goto out;
195aefde
IE		 3956 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3957 if (r < 0)
10589a46 3958 goto out;
195aefde
IE		 3959 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3960 if (r < 0)
10589a46 3961 goto out;
195aefde 3962 data = ~0;
10589a46
MT		 3963 r = kvm_write_guest_page(kvm, fn, &data,
3964 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3965 sizeof(u8));
10589a46 3966out:
40dcaa9f 3967 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3968 return r;
6aa8b732
AK		 3969}
3970
b7ebfb05
SY		 3971static int init_rmode_identity_map(struct kvm *kvm)
3972{
f51770ed 3973 int i, idx, r = 0;
b7ebfb05
SY		 3974 pfn_t identity_map_pfn;
3975 u32 tmp;
3976
089d034e 3977 if (!enable_ept)
f51770ed 3978 return 0;
a255d479
TC		 3979
3980 /* Protect kvm->arch.ept_identity_pagetable_done. */
3981 mutex_lock(&kvm->slots_lock);
3982
f51770ed 3983 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3984 goto out2;
a255d479 3985
b927a3ce 3986 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3987
3988 r = alloc_identity_pagetable(kvm);
f51770ed 3989 if (r < 0)
a255d479
TC		 3990 goto out2;
3991
40dcaa9f 3992 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3993 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3994 if (r < 0)
3995 goto out;
3996 /* Set up identity-mapping pagetable for EPT in real mode */
3997 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3998 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3999 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4000 r = kvm_write_guest_page(kvm, identity_map_pfn,
4001 &tmp, i * sizeof(tmp), sizeof(tmp));
4002 if (r < 0)
4003 goto out;
4004 }
4005 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4006
b7ebfb05 4007out:
40dcaa9f 4008 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4009
4010out2:
4011 mutex_unlock(&kvm->slots_lock);
f51770ed 4012 return r;
b7ebfb05
SY		 4013}
4014
6aa8b732
AK		 4015static void seg_setup(int seg)
4016{
772e0318 4017 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4018 unsigned int ar;
6aa8b732
AK		 4019
4020 vmcs_write16(sf->selector, 0);
4021 vmcs_writel(sf->base, 0);
4022 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4023 ar = 0x93;
4024 if (seg == VCPU_SREG_CS)
4025 ar |= 0x08; /* code segment */
3a624e29
NK		 4026
4027 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4028}
4029
f78e0e2e
SY		 4030static int alloc_apic_access_page(struct kvm *kvm)
4031{
4484141a 4032 struct page *page;
f78e0e2e
SY		 4033 struct kvm_userspace_memory_region kvm_userspace_mem;
4034 int r = 0;
4035
79fac95e 4036 mutex_lock(&kvm->slots_lock);
c24ae0dc 4037 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4038 goto out;
4039 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4040 kvm_userspace_mem.flags = 0;
73a6d941 4041 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4042 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4043 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4044 if (r)
4045 goto out;
72dc67a6 4046
73a6d941 4047 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4048 if (is_error_page(page)) {
4049 r = -EFAULT;
4050 goto out;
4051 }
4052
c24ae0dc
TC		 4053 /*
4054 * Do not pin the page in memory, so that memory hot-unplug
4055 * is able to migrate it.
4056 */
4057 put_page(page);
4058 kvm->arch.apic_access_page_done = true;
f78e0e2e 4059out:
79fac95e 4060 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4061 return r;
4062}
4063
b7ebfb05
SY		 4064static int alloc_identity_pagetable(struct kvm *kvm)
4065{
a255d479
TC		 4066 /* Called with kvm->slots_lock held. */
4067
b7ebfb05
SY		 4068 struct kvm_userspace_memory_region kvm_userspace_mem;
4069 int r = 0;
4070
a255d479
TC		 4071 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4072
b7ebfb05
SY		 4073 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4074 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4075 kvm_userspace_mem.guest_phys_addr =
4076 kvm->arch.ept_identity_map_addr;
b7ebfb05 4077 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4078 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4079
b7ebfb05
SY		 4080 return r;
4081}
4082
2384d2b3
SY		 4083static void allocate_vpid(struct vcpu_vmx *vmx)
4084{
4085 int vpid;
4086
4087 vmx->vpid = 0;
919818ab 4088 if (!enable_vpid)
2384d2b3
SY		 4089 return;
4090 spin_lock(&vmx_vpid_lock);
4091 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4092 if (vpid < VMX_NR_VPIDS) {
4093 vmx->vpid = vpid;
4094 __set_bit(vpid, vmx_vpid_bitmap);
4095 }
4096 spin_unlock(&vmx_vpid_lock);
4097}
4098
cdbecfc3
LJ		 4099static void free_vpid(struct vcpu_vmx *vmx)
4100{
4101 if (!enable_vpid)
4102 return;
4103 spin_lock(&vmx_vpid_lock);
4104 if (vmx->vpid != 0)
4105 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4106 spin_unlock(&vmx_vpid_lock);
4107}
4108
8d14695f
YZ		 4109#define MSR_TYPE_R 1
4110#define MSR_TYPE_W 2
4111static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4112 u32 msr, int type)
25c5f225 4113{
3e7c73e9 4114 int f = sizeof(unsigned long);
25c5f225
SY		 4115
4116 if (!cpu_has_vmx_msr_bitmap())
4117 return;
4118
4119 /*
4120 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4121 * have the write-low and read-high bitmap offsets the wrong way round.
4122 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4123 */
25c5f225 4124 if (msr <= 0x1fff) {
8d14695f
YZ		 4125 if (type & MSR_TYPE_R)
4126 /* read-low */
4127 __clear_bit(msr, msr_bitmap + 0x000 / f);
4128
4129 if (type & MSR_TYPE_W)
4130 /* write-low */
4131 __clear_bit(msr, msr_bitmap + 0x800 / f);
4132
25c5f225
SY		 4133 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4134 msr &= 0x1fff;
8d14695f
YZ		 4135 if (type & MSR_TYPE_R)
4136 /* read-high */
4137 __clear_bit(msr, msr_bitmap + 0x400 / f);
4138
4139 if (type & MSR_TYPE_W)
4140 /* write-high */
4141 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4142
4143 }
4144}
4145
4146static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4147 u32 msr, int type)
4148{
4149 int f = sizeof(unsigned long);
4150
4151 if (!cpu_has_vmx_msr_bitmap())
4152 return;
4153
4154 /*
4155 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4156 * have the write-low and read-high bitmap offsets the wrong way round.
4157 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4158 */
4159 if (msr <= 0x1fff) {
4160 if (type & MSR_TYPE_R)
4161 /* read-low */
4162 __set_bit(msr, msr_bitmap + 0x000 / f);
4163
4164 if (type & MSR_TYPE_W)
4165 /* write-low */
4166 __set_bit(msr, msr_bitmap + 0x800 / f);
4167
4168 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4169 msr &= 0x1fff;
4170 if (type & MSR_TYPE_R)
4171 /* read-high */
4172 __set_bit(msr, msr_bitmap + 0x400 / f);
4173
4174 if (type & MSR_TYPE_W)
4175 /* write-high */
4176 __set_bit(msr, msr_bitmap + 0xc00 / f);
4177
25c5f225 4178 }
25c5f225
SY		 4179}
4180
5897297b
AK		 4181static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4182{
4183 if (!longmode_only)
8d14695f
YZ		 4184 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4185 msr, MSR_TYPE_R | MSR_TYPE_W);
4186 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4187 msr, MSR_TYPE_R | MSR_TYPE_W);
4188}
4189
4190static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4191{
4192 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4193 msr, MSR_TYPE_R);
4194 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4195 msr, MSR_TYPE_R);
4196}
4197
4198static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4199{
4200 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4201 msr, MSR_TYPE_R);
4202 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4203 msr, MSR_TYPE_R);
4204}
4205
4206static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4207{
4208 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4209 msr, MSR_TYPE_W);
4210 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4211 msr, MSR_TYPE_W);
5897297b
AK		 4212}
4213
01e439be
YZ		 4214static int vmx_vm_has_apicv(struct kvm *kvm)
4215{
4216 return enable_apicv && irqchip_in_kernel(kvm);
4217}
4218
a20ed54d
YZ		 4219/*
4220 * Send interrupt to vcpu via posted interrupt way.
4221 * 1. If target vcpu is running(non-root mode), send posted interrupt
4222 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4223 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4224 * interrupt from PIR in next vmentry.
4225 */
4226static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4227{
4228 struct vcpu_vmx *vmx = to_vmx(vcpu);
4229 int r;
4230
4231 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4232 return;
4233
4234 r = pi_test_and_set_on(&vmx->pi_desc);
4235 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4236#ifdef CONFIG_SMP
a20ed54d
YZ		 4237 if (!r && (vcpu->mode == IN_GUEST_MODE))
4238 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4239 POSTED_INTR_VECTOR);
4240 else
6ffbbbba 4241#endif
a20ed54d
YZ		 4242 kvm_vcpu_kick(vcpu);
4243}
4244
4245static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4246{
4247 struct vcpu_vmx *vmx = to_vmx(vcpu);
4248
4249 if (!pi_test_and_clear_on(&vmx->pi_desc))
4250 return;
4251
4252 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4253}
4254
4255static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4256{
4257 return;
4258}
4259
a3a8ff8e
NHE		 4260/*
4261 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4262 * will not change in the lifetime of the guest.
4263 * Note that host-state that does change is set elsewhere. E.g., host-state
4264 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4265 */
a547c6db 4266static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4267{
4268 u32 low32, high32;
4269 unsigned long tmpl;
4270 struct desc_ptr dt;
d974baa3 4271 unsigned long cr4;
a3a8ff8e 4272
b1a74bf8 4273 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4274 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4275
d974baa3
AL		 4276 /* Save the most likely value for this task's CR4 in the VMCS. */
4277 cr4 = read_cr4();
4278 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4279 vmx->host_state.vmcs_host_cr4 = cr4;
4280
a3a8ff8e 4281 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4282#ifdef CONFIG_X86_64
4283 /*
4284 * Load null selectors, so we can avoid reloading them in
4285 * __vmx_load_host_state(), in case userspace uses the null selectors
4286 * too (the expected case).
4287 */
4288 vmcs_write16(HOST_DS_SELECTOR, 0);
4289 vmcs_write16(HOST_ES_SELECTOR, 0);
4290#else
a3a8ff8e
NHE		 4291 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4292 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4293#endif
a3a8ff8e
NHE		 4294 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4295 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4296
4297 native_store_idt(&dt);
4298 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4299 vmx->host_idt_base = dt.address;
a3a8ff8e 4300
83287ea4 4301 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4302
4303 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4304 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4305 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4306 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4307
4308 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4309 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4310 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4311 }
4312}
4313
bf8179a0
NHE		 4314static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4315{
4316 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4317 if (enable_ept)
4318 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4319 if (is_guest_mode(&vmx->vcpu))
4320 vmx->vcpu.arch.cr4_guest_owned_bits &=
4321 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4322 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4323}
4324
01e439be
YZ		 4325static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4326{
4327 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4328
4329 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4330 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4331 return pin_based_exec_ctrl;
4332}
4333
bf8179a0
NHE		 4334static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4335{
4336 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4337
4338 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4339 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4340
bf8179a0
NHE		 4341 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4342 exec_control &= ~CPU_BASED_TPR_SHADOW;
4343#ifdef CONFIG_X86_64
4344 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4345 CPU_BASED_CR8_LOAD_EXITING;
4346#endif
4347 }
4348 if (!enable_ept)
4349 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4350 CPU_BASED_CR3_LOAD_EXITING |
4351 CPU_BASED_INVLPG_EXITING;
4352 return exec_control;
4353}
4354
4355static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4356{
4357 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4358 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4359 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4360 if (vmx->vpid == 0)
4361 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4362 if (!enable_ept) {
4363 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4364 enable_unrestricted_guest = 0;
ad756a16
MJ		 4365 /* Enable INVPCID for non-ept guests may cause performance regression. */
4366 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4367 }
4368 if (!enable_unrestricted_guest)
4369 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4370 if (!ple_gap)
4371 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4372 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4373 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4374 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4375 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4376 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4377 (handle_vmptrld).
4378 We can NOT enable shadow_vmcs here because we don't have yet
4379 a current VMCS12
4380 */
4381 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4382 return exec_control;
4383}
4384
ce88decf
XG		 4385static void ept_set_mmio_spte_mask(void)
4386{
4387 /*
4388 * EPT Misconfigurations can be generated if the value of bits 2:0
4389 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4390 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4391 * spte.
4392 */
885032b9 4393 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4394}
4395
6aa8b732
AK		 4396/*
4397 * Sets up the vmcs for emulated real mode.
4398 */
8b9cf98c 4399static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4400{
2e4ce7f5 4401#ifdef CONFIG_X86_64
6aa8b732 4402 unsigned long a;
2e4ce7f5 4403#endif
6aa8b732 4404 int i;
6aa8b732 4405
6aa8b732 4406 /* I/O */
3e7c73e9
AK		 4407 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4408 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4409
4607c2d7
AG		 4410 if (enable_shadow_vmcs) {
4411 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4412 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4413 }
25c5f225 4414 if (cpu_has_vmx_msr_bitmap())
5897297b 4415 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4416
6aa8b732
AK		 4417 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4418
6aa8b732 4419 /* Control */
01e439be 4420 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4421
bf8179a0 4422 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4423
83ff3b9d 4424 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4425 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4426 vmx_secondary_exec_control(vmx));
83ff3b9d 4427 }
f78e0e2e 4428
01e439be 4429 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4430 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4431 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4432 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4433 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4434
4435 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4436
4437 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4438 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4439 }
4440
4b8d54f9
ZE		 4441 if (ple_gap) {
4442 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4443 vmx->ple_window = ple_window;
4444 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4445 }
4446
c3707958
XG		 4447 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4448 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4449 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4450
9581d442
AK		 4451 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4452 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4453 vmx_set_constant_host_state(vmx);
05b3e0c2 4454#ifdef CONFIG_X86_64
6aa8b732
AK		 4455 rdmsrl(MSR_FS_BASE, a);
4456 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4457 rdmsrl(MSR_GS_BASE, a);
4458 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4459#else
4460 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4461 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4462#endif
4463
2cc51560
ED		 4464 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4465 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4466 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4467 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4468 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4469
468d472f 4470 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4471 u32 msr_low, msr_high;
4472 u64 host_pat;
468d472f
SY		 4473 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4474 host_pat = msr_low | ((u64) msr_high << 32);
4475 /* Write the default value follow host pat */
4476 vmcs_write64(GUEST_IA32_PAT, host_pat);
4477 /* Keep arch.pat sync with GUEST_IA32_PAT */
4478 vmx->vcpu.arch.pat = host_pat;
4479 }
4480
03916db9 4481 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4482 u32 index = vmx_msr_index[i];
4483 u32 data_low, data_high;
a2fa3e9f 4484 int j = vmx->nmsrs;
6aa8b732
AK		 4485
4486 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4487 continue;
432bd6cb
AK		 4488 if (wrmsr_safe(index, data_low, data_high) < 0)
4489 continue;
26bb0981
AK		 4490 vmx->guest_msrs[j].index = i;
4491 vmx->guest_msrs[j].data = 0;
d5696725 4492 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4493 ++vmx->nmsrs;
6aa8b732 4494 }
6aa8b732 4495
2961e876
GN		 4496
4497 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4498
4499 /* 22.2.1, 20.8.1 */
2961e876 4500 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4501
e00c8cf2 4502 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4503 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4504
4505 return 0;
4506}
4507
57f252f2 4508static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4509{
4510 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4511 struct msr_data apic_base_msr;
e00c8cf2 4512
7ffd92c5 4513 vmx->rmode.vm86_active = 0;
e00c8cf2 4514
3b86cd99
JK		 4515 vmx->soft_vnmi_blocked = 0;
4516
ad312c7c 4517 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4518 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4519 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4520 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4521 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4522 apic_base_msr.host_initiated = true;
4523 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4524
2fb92db1
AK		 4525 vmx_segment_cache_clear(vmx);
4526
5706be0d 4527 seg_setup(VCPU_SREG_CS);
66450a21 4528 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4529 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4530
4531 seg_setup(VCPU_SREG_DS);
4532 seg_setup(VCPU_SREG_ES);
4533 seg_setup(VCPU_SREG_FS);
4534 seg_setup(VCPU_SREG_GS);
4535 seg_setup(VCPU_SREG_SS);
4536
4537 vmcs_write16(GUEST_TR_SELECTOR, 0);
4538 vmcs_writel(GUEST_TR_BASE, 0);
4539 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4540 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4541
4542 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4543 vmcs_writel(GUEST_LDTR_BASE, 0);
4544 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4545 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4546
4547 vmcs_write32(GUEST_SYSENTER_CS, 0);
4548 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4549 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4550
4551 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4552 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4553
e00c8cf2
AK		 4554 vmcs_writel(GUEST_GDTR_BASE, 0);
4555 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4556
4557 vmcs_writel(GUEST_IDTR_BASE, 0);
4558 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4559
443381a8 4560 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4561 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4562 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4563
e00c8cf2
AK		 4564 /* Special registers */
4565 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4566
4567 setup_msrs(vmx);
4568
6aa8b732
AK		 4569 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4570
f78e0e2e
SY		 4571 if (cpu_has_vmx_tpr_shadow()) {
4572 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4573 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4574 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4575 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4576 vmcs_write32(TPR_THRESHOLD, 0);
4577 }
4578
38b99173 4579 kvm_vcpu_reload_apic_access_page(vcpu);
6aa8b732 4580
01e439be
YZ		 4581 if (vmx_vm_has_apicv(vcpu->kvm))
4582 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4583
2384d2b3
SY		 4584 if (vmx->vpid != 0)
4585 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4586
fa40052c 4587 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4588 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4589 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4590 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4591 vmx_fpu_activate(&vmx->vcpu);
4592 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4593
b9d762fa 4594 vpid_sync_context(vmx);
6aa8b732
AK		 4595}
4596
b6f1250e
NHE		 4597/*
4598 * In nested virtualization, check if L1 asked to exit on external interrupts.
4599 * For most existing hypervisors, this will always return true.
4600 */
4601static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4602{
4603 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4604 PIN_BASED_EXT_INTR_MASK;
4605}
4606
77b0f5d6
BD		 4607/*
4608 * In nested virtualization, check if L1 has set
4609 * VM_EXIT_ACK_INTR_ON_EXIT
4610 */
4611static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4612{
4613 return get_vmcs12(vcpu)->vm_exit_controls &
4614 VM_EXIT_ACK_INTR_ON_EXIT;
4615}
4616
ea8ceb83
JK		 4617static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4618{
4619 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4620 PIN_BASED_NMI_EXITING;
4621}
4622
c9a7953f 4623static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4624{
4625 u32 cpu_based_vm_exec_control;
730dca42 4626
3b86cd99
JK		 4627 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4628 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4630}
4631
c9a7953f 4632static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4633{
4634 u32 cpu_based_vm_exec_control;
4635
c9a7953f
JK		 4636 if (!cpu_has_virtual_nmis() ||
4637 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4638 enable_irq_window(vcpu);
4639 return;
4640 }
3b86cd99
JK		 4641
4642 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4643 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4645}
4646
66fd3f7f 4647static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4648{
9c8cba37 4649 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4650 uint32_t intr;
4651 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4652
229456fc 4653 trace_kvm_inj_virq(irq);
2714d1d3 4654
fa89a817 4655 ++vcpu->stat.irq_injections;
7ffd92c5 4656 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4657 int inc_eip = 0;
4658 if (vcpu->arch.interrupt.soft)
4659 inc_eip = vcpu->arch.event_exit_inst_len;
4660 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4661 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4662 return;
4663 }
66fd3f7f
GN		 4664 intr = irq | INTR_INFO_VALID_MASK;
4665 if (vcpu->arch.interrupt.soft) {
4666 intr |= INTR_TYPE_SOFT_INTR;
4667 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4668 vmx->vcpu.arch.event_exit_inst_len);
4669 } else
4670 intr |= INTR_TYPE_EXT_INTR;
4671 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4672}
4673
f08864b4
SY		 4674static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4675{
66a5a347
JK		 4676 struct vcpu_vmx *vmx = to_vmx(vcpu);
4677
0b6ac343
NHE		 4678 if (is_guest_mode(vcpu))
4679 return;
4680
3b86cd99
JK		 4681 if (!cpu_has_virtual_nmis()) {
4682 /*
4683 * Tracking the NMI-blocked state in software is built upon
4684 * finding the next open IRQ window. This, in turn, depends on
4685 * well-behaving guests: They have to keep IRQs disabled at
4686 * least as long as the NMI handler runs. Otherwise we may
4687 * cause NMI nesting, maybe breaking the guest. But as this is
4688 * highly unlikely, we can live with the residual risk.
4689 */
4690 vmx->soft_vnmi_blocked = 1;
4691 vmx->vnmi_blocked_time = 0;
4692 }
4693
487b391d 4694 ++vcpu->stat.nmi_injections;
9d58b931 4695 vmx->nmi_known_unmasked = false;
7ffd92c5 4696 if (vmx->rmode.vm86_active) {
71f9833b 4697 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4698 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4699 return;
4700 }
f08864b4
SY		 4701 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4702 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4703}
4704
3cfc3092
JK		 4705static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4706{
4707 if (!cpu_has_virtual_nmis())
4708 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4709 if (to_vmx(vcpu)->nmi_known_unmasked)
4710 return false;
c332c83a 4711 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4712}
4713
4714static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4715{
4716 struct vcpu_vmx *vmx = to_vmx(vcpu);
4717
4718 if (!cpu_has_virtual_nmis()) {
4719 if (vmx->soft_vnmi_blocked != masked) {
4720 vmx->soft_vnmi_blocked = masked;
4721 vmx->vnmi_blocked_time = 0;
4722 }
4723 } else {
9d58b931 4724 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4725 if (masked)
4726 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4727 GUEST_INTR_STATE_NMI);
4728 else
4729 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4730 GUEST_INTR_STATE_NMI);
4731 }
4732}
4733
2505dc9f
JK		 4734static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4735{
b6b8a145
JK		 4736 if (to_vmx(vcpu)->nested.nested_run_pending)
4737 return 0;
ea8ceb83 4738
2505dc9f
JK		 4739 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4740 return 0;
4741
4742 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4743 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4744 | GUEST_INTR_STATE_NMI));
4745}
4746
78646121
GN		 4747static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4748{
b6b8a145
JK		 4749 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4750 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4751 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4752 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4753}
4754
cbc94022
IE		 4755static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4756{
4757 int ret;
4758 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4759 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4760 .guest_phys_addr = addr,
4761 .memory_size = PAGE_SIZE * 3,
4762 .flags = 0,
4763 };
4764
47ae31e2 4765 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4766 if (ret)
4767 return ret;
bfc6d222 4768 kvm->arch.tss_addr = addr;
1f755a82 4769 return init_rmode_tss(kvm);
cbc94022
IE		 4770}
4771
0ca1b4f4 4772static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4773{
77ab6db0 4774 switch (vec) {
77ab6db0 4775 case BP_VECTOR:
c573cd22
JK		 4776 /*
4777 * Update instruction length as we may reinject the exception
4778 * from user space while in guest debugging mode.
4779 */
4780 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4781 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4782 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4783 return false;
4784 /* fall through */
4785 case DB_VECTOR:
4786 if (vcpu->guest_debug &
4787 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4788 return false;
d0bfb940
JK		 4789 /* fall through */
4790 case DE_VECTOR:
77ab6db0
JK		 4791 case OF_VECTOR:
4792 case BR_VECTOR:
4793 case UD_VECTOR:
4794 case DF_VECTOR:
4795 case SS_VECTOR:
4796 case GP_VECTOR:
4797 case MF_VECTOR:
0ca1b4f4
GN		 4798 return true;
4799 break;
77ab6db0 4800 }
0ca1b4f4
GN		 4801 return false;
4802}
4803
4804static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4805 int vec, u32 err_code)
4806{
4807 /*
4808 * Instruction with address size override prefix opcode 0x67
4809 * Cause the #SS fault with 0 error code in VM86 mode.
4810 */
4811 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4812 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4813 if (vcpu->arch.halt_request) {
4814 vcpu->arch.halt_request = 0;
4815 return kvm_emulate_halt(vcpu);
4816 }
4817 return 1;
4818 }
4819 return 0;
4820 }
4821
4822 /*
4823 * Forward all other exceptions that are valid in real mode.
4824 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4825 * the required debugging infrastructure rework.
4826 */
4827 kvm_queue_exception(vcpu, vec);
4828 return 1;
6aa8b732
AK		 4829}
4830
a0861c02
AK		 4831/*
4832 * Trigger machine check on the host. We assume all the MSRs are already set up
4833 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4834 * We pass a fake environment to the machine check handler because we want
4835 * the guest to be always treated like user space, no matter what context
4836 * it used internally.
4837 */
4838static void kvm_machine_check(void)
4839{
4840#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4841 struct pt_regs regs = {
4842 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4843 .flags = X86_EFLAGS_IF,
4844 };
4845
4846 do_machine_check(&regs, 0);
4847#endif
4848}
4849
851ba692 4850static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4851{
4852 /* already handled by vcpu_run */
4853 return 1;
4854}
4855
851ba692 4856static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4857{
1155f76a 4858 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4859 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4860 u32 intr_info, ex_no, error_code;
42dbaa5a 4861 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4862 u32 vect_info;
4863 enum emulation_result er;
4864
1155f76a 4865 vect_info = vmx->idt_vectoring_info;
88786475 4866 intr_info = vmx->exit_intr_info;
6aa8b732 4867
a0861c02 4868 if (is_machine_check(intr_info))
851ba692 4869 return handle_machine_check(vcpu);
a0861c02 4870
e4a41889 4871 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4872 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4873
4874 if (is_no_device(intr_info)) {
5fd86fcf 4875 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4876 return 1;
4877 }
4878
7aa81cc0 4879 if (is_invalid_opcode(intr_info)) {
51d8b661 4880 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4881 if (er != EMULATE_DONE)
7ee5d940 4882 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4883 return 1;
4884 }
4885
6aa8b732 4886 error_code = 0;
2e11384c 4887 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4888 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4889
4890 /*
4891 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4892 * MMIO, it is better to report an internal error.
4893 * See the comments in vmx_handle_exit.
4894 */
4895 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4896 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4897 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4898 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4899 vcpu->run->internal.ndata = 2;
4900 vcpu->run->internal.data[0] = vect_info;
4901 vcpu->run->internal.data[1] = intr_info;
4902 return 0;
4903 }
4904
6aa8b732 4905 if (is_page_fault(intr_info)) {
1439442c 4906 /* EPT won't cause page fault directly */
cf3ace79 4907 BUG_ON(enable_ept);
6aa8b732 4908 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4909 trace_kvm_page_fault(cr2, error_code);
4910
3298b75c 4911 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4912 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4913 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4914 }
4915
d0bfb940 4916 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4917
4918 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4919 return handle_rmode_exception(vcpu, ex_no, error_code);
4920
42dbaa5a
JK		 4921 switch (ex_no) {
4922 case DB_VECTOR:
4923 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4924 if (!(vcpu->guest_debug &
4925 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4926 vcpu->arch.dr6 &= ~15;
6f43ed01 4927 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4928 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4929 skip_emulated_instruction(vcpu);
4930
42dbaa5a
JK		 4931 kvm_queue_exception(vcpu, DB_VECTOR);
4932 return 1;
4933 }
4934 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4935 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4936 /* fall through */
4937 case BP_VECTOR:
c573cd22
JK		 4938 /*
4939 * Update instruction length as we may reinject #BP from
4940 * user space while in guest debugging mode. Reading it for
4941 * #DB as well causes no harm, it is not used in that case.
4942 */
4943 vmx->vcpu.arch.event_exit_inst_len =
4944 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4945 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4946 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4947 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4948 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4949 break;
4950 default:
d0bfb940
JK		 4951 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4952 kvm_run->ex.exception = ex_no;
4953 kvm_run->ex.error_code = error_code;
42dbaa5a 4954 break;
6aa8b732 4955 }
6aa8b732
AK		 4956 return 0;
4957}
4958
851ba692 4959static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4960{
1165f5fe 4961 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4962 return 1;
4963}
4964
851ba692 4965static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4966{
851ba692 4967 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4968 return 0;
4969}
6aa8b732 4970
851ba692 4971static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4972{
bfdaab09 4973 unsigned long exit_qualification;
34c33d16 4974 int size, in, string;
039576c0 4975 unsigned port;
6aa8b732 4976
bfdaab09 4977 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4978 string = (exit_qualification & 16) != 0;
cf8f70bf 4979 in = (exit_qualification & 8) != 0;
e70669ab 4980
cf8f70bf 4981 ++vcpu->stat.io_exits;
e70669ab 4982
cf8f70bf 4983 if (string || in)
51d8b661 4984 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4985
cf8f70bf
GN		 4986 port = exit_qualification >> 16;
4987 size = (exit_qualification & 7) + 1;
e93f36bc 4988 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4989
4990 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4991}
4992
102d8325
IM		 4993static void
4994vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4995{
4996 /*
4997 * Patch in the VMCALL instruction:
4998 */
4999 hypercall[0] = 0x0f;
5000 hypercall[1] = 0x01;
5001 hypercall[2] = 0xc1;
102d8325
IM		 5002}
5003
92fbc7b1
JK		 5004static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
5005{
5006 unsigned long always_on = VMXON_CR0_ALWAYSON;
5007
5008 if (nested_vmx_secondary_ctls_high &
5009 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5010 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5011 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5012 return (val & always_on) == always_on;
5013}
5014
0fa06071 5015/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5016static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5017{
eeadf9e7 5018 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5019 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5020 unsigned long orig_val = val;
5021
eeadf9e7
NHE		 5022 /*
5023 * We get here when L2 changed cr0 in a way that did not change
5024 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5025 * but did change L0 shadowed bits. So we first calculate the
5026 * effective cr0 value that L1 would like to write into the
5027 * hardware. It consists of the L2-owned bits from the new
5028 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5029 */
1a0d74e6
JK		 5030 val = (val & ~vmcs12->cr0_guest_host_mask) |
5031 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5032
92fbc7b1 5033 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5034 return 1;
1a0d74e6
JK		 5035
5036 if (kvm_set_cr0(vcpu, val))
5037 return 1;
5038 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5039 return 0;
1a0d74e6
JK		 5040 } else {
5041 if (to_vmx(vcpu)->nested.vmxon &&
5042 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5043 return 1;
eeadf9e7 5044 return kvm_set_cr0(vcpu, val);
1a0d74e6 5045 }
eeadf9e7
NHE		 5046}
5047
5048static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5049{
5050 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5051 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5052 unsigned long orig_val = val;
5053
5054 /* analogously to handle_set_cr0 */
5055 val = (val & ~vmcs12->cr4_guest_host_mask) |
5056 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5057 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5058 return 1;
1a0d74e6 5059 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5060 return 0;
5061 } else
5062 return kvm_set_cr4(vcpu, val);
5063}
5064
5065/* called to set cr0 as approriate for clts instruction exit. */
5066static void handle_clts(struct kvm_vcpu *vcpu)
5067{
5068 if (is_guest_mode(vcpu)) {
5069 /*
5070 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5071 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5072 * just pretend it's off (also in arch.cr0 for fpu_activate).
5073 */
5074 vmcs_writel(CR0_READ_SHADOW,
5075 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5076 vcpu->arch.cr0 &= ~X86_CR0_TS;
5077 } else
5078 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5079}
5080
851ba692 5081static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5082{
229456fc 5083 unsigned long exit_qualification, val;
6aa8b732
AK		 5084 int cr;
5085 int reg;
49a9b07e 5086 int err;
6aa8b732 5087
bfdaab09 5088 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5089 cr = exit_qualification & 15;
5090 reg = (exit_qualification >> 8) & 15;
5091 switch ((exit_qualification >> 4) & 3) {
5092 case 0: /* mov to cr */
1e32c079 5093 val = kvm_register_readl(vcpu, reg);
229456fc 5094 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5095 switch (cr) {
5096 case 0:
eeadf9e7 5097 err = handle_set_cr0(vcpu, val);
db8fcefa 5098 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5099 return 1;
5100 case 3:
2390218b 5101 err = kvm_set_cr3(vcpu, val);
db8fcefa 5102 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5103 return 1;
5104 case 4:
eeadf9e7 5105 err = handle_set_cr4(vcpu, val);
db8fcefa 5106 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5107 return 1;
0a5fff19
GN		 5108 case 8: {
5109 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5110 u8 cr8 = (u8)val;
eea1cff9 5111 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5112 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5113 if (irqchip_in_kernel(vcpu->kvm))
5114 return 1;
5115 if (cr8_prev <= cr8)
5116 return 1;
851ba692 5117 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5118 return 0;
5119 }
4b8073e4 5120 }
6aa8b732 5121 break;
25c4c276 5122 case 2: /* clts */
eeadf9e7 5123 handle_clts(vcpu);
4d4ec087 5124 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5125 skip_emulated_instruction(vcpu);
6b52d186 5126 vmx_fpu_activate(vcpu);
25c4c276 5127 return 1;
6aa8b732
AK		 5128 case 1: /*mov from cr*/
5129 switch (cr) {
5130 case 3:
9f8fe504
AK		 5131 val = kvm_read_cr3(vcpu);
5132 kvm_register_write(vcpu, reg, val);
5133 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5134 skip_emulated_instruction(vcpu);
5135 return 1;
5136 case 8:
229456fc
MT		 5137 val = kvm_get_cr8(vcpu);
5138 kvm_register_write(vcpu, reg, val);
5139 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5140 skip_emulated_instruction(vcpu);
5141 return 1;
5142 }
5143 break;
5144 case 3: /* lmsw */
a1f83a74 5145 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5146 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5147 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5148
5149 skip_emulated_instruction(vcpu);
5150 return 1;
5151 default:
5152 break;
5153 }
851ba692 5154 vcpu->run->exit_reason = 0;
a737f256 5155 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5156 (int)(exit_qualification >> 4) & 3, cr);
5157 return 0;
5158}
5159
851ba692 5160static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5161{
bfdaab09 5162 unsigned long exit_qualification;
6aa8b732
AK		 5163 int dr, reg;
5164
f2483415 5165 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5166 if (!kvm_require_cpl(vcpu, 0))
5167 return 1;
42dbaa5a
JK		 5168 dr = vmcs_readl(GUEST_DR7);
5169 if (dr & DR7_GD) {
5170 /*
5171 * As the vm-exit takes precedence over the debug trap, we
5172 * need to emulate the latter, either for the host or the
5173 * guest debugging itself.
5174 */
5175 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5176 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5177 vcpu->run->debug.arch.dr7 = dr;
5178 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5179 vmcs_readl(GUEST_CS_BASE) +
5180 vmcs_readl(GUEST_RIP);
851ba692
AK		 5181 vcpu->run->debug.arch.exception = DB_VECTOR;
5182 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5183 return 0;
5184 } else {
5185 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5186 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5187 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5188 kvm_queue_exception(vcpu, DB_VECTOR);
5189 return 1;
5190 }
5191 }
5192
81908bf4
PB		 5193 if (vcpu->guest_debug == 0) {
5194 u32 cpu_based_vm_exec_control;
5195
5196 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5197 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5198 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5199
5200 /*
5201 * No more DR vmexits; force a reload of the debug registers
5202 * and reenter on this instruction. The next vmexit will
5203 * retrieve the full state of the debug registers.
5204 */
5205 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5206 return 1;
5207 }
5208
bfdaab09 5209 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5210 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5211 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5212 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5213 unsigned long val;
4c4d563b
JK		 5214
5215 if (kvm_get_dr(vcpu, dr, &val))
5216 return 1;
5217 kvm_register_write(vcpu, reg, val);
020df079 5218 } else
5777392e 5219 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5220 return 1;
5221
6aa8b732
AK		 5222 skip_emulated_instruction(vcpu);
5223 return 1;
5224}
5225
73aaf249
JK		 5226static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5227{
5228 return vcpu->arch.dr6;
5229}
5230
5231static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5232{
5233}
5234
81908bf4
PB		 5235static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5236{
5237 u32 cpu_based_vm_exec_control;
5238
5239 get_debugreg(vcpu->arch.db[0], 0);
5240 get_debugreg(vcpu->arch.db[1], 1);
5241 get_debugreg(vcpu->arch.db[2], 2);
5242 get_debugreg(vcpu->arch.db[3], 3);
5243 get_debugreg(vcpu->arch.dr6, 6);
5244 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5245
5246 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5247
5248 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5249 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5250 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5251}
5252
020df079
GN		 5253static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5254{
5255 vmcs_writel(GUEST_DR7, val);
5256}
5257
851ba692 5258static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5259{
06465c5a
AK		 5260 kvm_emulate_cpuid(vcpu);
5261 return 1;
6aa8b732
AK		 5262}
5263
851ba692 5264static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5265{
ad312c7c 5266 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5267 u64 data;
5268
5269 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5270 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5271 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5272 return 1;
5273 }
5274
229456fc 5275 trace_kvm_msr_read(ecx, data);
2714d1d3 5276
6aa8b732 5277 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5278 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5279 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5280 skip_emulated_instruction(vcpu);
5281 return 1;
5282}
5283
851ba692 5284static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5285{
8fe8ab46 5286 struct msr_data msr;
ad312c7c
ZX		 5287 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5288 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5289 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5290
8fe8ab46
WA		 5291 msr.data = data;
5292 msr.index = ecx;
5293 msr.host_initiated = false;
854e8bb1 5294 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5295 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5296 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5297 return 1;
5298 }
5299
59200273 5300 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5301 skip_emulated_instruction(vcpu);
5302 return 1;
5303}
5304
851ba692 5305static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5306{
3842d135 5307 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5308 return 1;
5309}
5310
851ba692 5311static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5312{
85f455f7
ED		 5313 u32 cpu_based_vm_exec_control;
5314
5315 /* clear pending irq */
5316 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5317 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5318 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5319
3842d135
AK		 5320 kvm_make_request(KVM_REQ_EVENT, vcpu);
5321
a26bf12a 5322 ++vcpu->stat.irq_window_exits;
2714d1d3 5323
c1150d8c
DL		 5324 /*
5325 * If the user space waits to inject interrupts, exit as soon as
5326 * possible
5327 */
8061823a 5328 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5329 vcpu->run->request_interrupt_window &&
8061823a 5330 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5331 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5332 return 0;
5333 }
6aa8b732
AK		 5334 return 1;
5335}
5336
851ba692 5337static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5338{
5339 skip_emulated_instruction(vcpu);
d3bef15f 5340 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5341}
5342
851ba692 5343static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5344{
510043da 5345 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5346 kvm_emulate_hypercall(vcpu);
5347 return 1;
c21415e8
IM		 5348}
5349
ec25d5e6
GN		 5350static int handle_invd(struct kvm_vcpu *vcpu)
5351{
51d8b661 5352 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5353}
5354
851ba692 5355static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5356{
f9c617f6 5357 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5358
5359 kvm_mmu_invlpg(vcpu, exit_qualification);
5360 skip_emulated_instruction(vcpu);
5361 return 1;
5362}
5363
fee84b07
AK		 5364static int handle_rdpmc(struct kvm_vcpu *vcpu)
5365{
5366 int err;
5367
5368 err = kvm_rdpmc(vcpu);
5369 kvm_complete_insn_gp(vcpu, err);
5370
5371 return 1;
5372}
5373
851ba692 5374static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5375{
5376 skip_emulated_instruction(vcpu);
f5f48ee1 5377 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5378 return 1;
5379}
5380
2acf923e
DC		 5381static int handle_xsetbv(struct kvm_vcpu *vcpu)
5382{
5383 u64 new_bv = kvm_read_edx_eax(vcpu);
5384 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5385
5386 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5387 skip_emulated_instruction(vcpu);
5388 return 1;
5389}
5390
851ba692 5391static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5392{
58fbbf26
KT		 5393 if (likely(fasteoi)) {
5394 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5395 int access_type, offset;
5396
5397 access_type = exit_qualification & APIC_ACCESS_TYPE;
5398 offset = exit_qualification & APIC_ACCESS_OFFSET;
5399 /*
5400 * Sane guest uses MOV to write EOI, with written value
5401 * not cared. So make a short-circuit here by avoiding
5402 * heavy instruction emulation.
5403 */
5404 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5405 (offset == APIC_EOI)) {
5406 kvm_lapic_set_eoi(vcpu);
5407 skip_emulated_instruction(vcpu);
5408 return 1;
5409 }
5410 }
51d8b661 5411 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5412}
5413
c7c9c56c
YZ		 5414static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5415{
5416 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5417 int vector = exit_qualification & 0xff;
5418
5419 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5420 kvm_apic_set_eoi_accelerated(vcpu, vector);
5421 return 1;
5422}
5423
83d4c286
YZ		 5424static int handle_apic_write(struct kvm_vcpu *vcpu)
5425{
5426 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5427 u32 offset = exit_qualification & 0xfff;
5428
5429 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5430 kvm_apic_write_nodecode(vcpu, offset);
5431 return 1;
5432}
5433
851ba692 5434static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5435{
60637aac 5436 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5437 unsigned long exit_qualification;
e269fb21
JK		 5438 bool has_error_code = false;
5439 u32 error_code = 0;
37817f29 5440 u16 tss_selector;
7f3d35fd 5441 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5442
5443 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5444 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5445 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5446
5447 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5448
5449 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5450 if (reason == TASK_SWITCH_GATE && idt_v) {
5451 switch (type) {
5452 case INTR_TYPE_NMI_INTR:
5453 vcpu->arch.nmi_injected = false;
654f06fc 5454 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5455 break;
5456 case INTR_TYPE_EXT_INTR:
66fd3f7f 5457 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5458 kvm_clear_interrupt_queue(vcpu);
5459 break;
5460 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5461 if (vmx->idt_vectoring_info &
5462 VECTORING_INFO_DELIVER_CODE_MASK) {
5463 has_error_code = true;
5464 error_code =
5465 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5466 }
5467 /* fall through */
64a7ec06
GN		 5468 case INTR_TYPE_SOFT_EXCEPTION:
5469 kvm_clear_exception_queue(vcpu);
5470 break;
5471 default:
5472 break;
5473 }
60637aac 5474 }
37817f29
IE		 5475 tss_selector = exit_qualification;
5476
64a7ec06
GN		 5477 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5478 type != INTR_TYPE_EXT_INTR &&
5479 type != INTR_TYPE_NMI_INTR))
5480 skip_emulated_instruction(vcpu);
5481
7f3d35fd
KW		 5482 if (kvm_task_switch(vcpu, tss_selector,
5483 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5484 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5485 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5486 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5487 vcpu->run->internal.ndata = 0;
42dbaa5a 5488 return 0;
acb54517 5489 }
42dbaa5a
JK		 5490
5491 /* clear all local breakpoint enable flags */
1f854112 5492 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5493
5494 /*
5495 * TODO: What about debug traps on tss switch?
5496 * Are we supposed to inject them and update dr6?
5497 */
5498
5499 return 1;
37817f29
IE		 5500}
5501
851ba692 5502static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5503{
f9c617f6 5504 unsigned long exit_qualification;
1439442c 5505 gpa_t gpa;
4f5982a5 5506 u32 error_code;
1439442c 5507 int gla_validity;
1439442c 5508
f9c617f6 5509 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5510
1439442c
SY		 5511 gla_validity = (exit_qualification >> 7) & 0x3;
5512 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5513 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5514 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5515 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5516 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5517 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5518 (long unsigned int)exit_qualification);
851ba692
AK		 5519 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5520 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5521 return 0;
1439442c
SY		 5522 }
5523
0be9c7a8
GN		 5524 /*
5525 * EPT violation happened while executing iret from NMI,
5526 * "blocked by NMI" bit has to be set before next VM entry.
5527 * There are errata that may cause this bit to not be set:
5528 * AAK134, BY25.
5529 */
bcd1c294
GN		 5530 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5531 cpu_has_virtual_nmis() &&
5532 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5533 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5534
1439442c 5535 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5536 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5537
5538 /* It is a write fault? */
5539 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5540 /* It is a fetch fault? */
5541 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5542 /* ept page table is present? */
5543 error_code |= (exit_qualification >> 3) & 0x1;
5544
25d92081
YZ		 5545 vcpu->arch.exit_qualification = exit_qualification;
5546
4f5982a5 5547 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5548}
5549
68f89400
MT		 5550static u64 ept_rsvd_mask(u64 spte, int level)
5551{
5552 int i;
5553 u64 mask = 0;
5554
5555 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5556 mask |= (1ULL << i);
5557
a32e8459 5558 if (level == 4)
68f89400
MT		 5559 /* bits 7:3 reserved */
5560 mask |= 0xf8;
a32e8459
WL		 5561 else if (spte & (1ULL << 7))
5562 /*
5563 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5564 * level == 1 if the hypervisor is using the ignored bit 7.
5565 */
5566 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5567 else if (level > 1)
5568 /* bits 6:3 reserved */
5569 mask |= 0x78;
68f89400
MT		 5570
5571 return mask;
5572}
5573
5574static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5575 int level)
5576{
5577 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5578
5579 /* 010b (write-only) */
5580 WARN_ON((spte & 0x7) == 0x2);
5581
5582 /* 110b (write/execute) */
5583 WARN_ON((spte & 0x7) == 0x6);
5584
5585 /* 100b (execute-only) and value not supported by logical processor */
5586 if (!cpu_has_vmx_ept_execute_only())
5587 WARN_ON((spte & 0x7) == 0x4);
5588
5589 /* not 000b */
5590 if ((spte & 0x7)) {
5591 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5592
5593 if (rsvd_bits != 0) {
5594 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5595 __func__, rsvd_bits);
5596 WARN_ON(1);
5597 }
5598
a32e8459
WL		 5599 /* bits 5:3 are _not_ reserved for large page or leaf page */
5600 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5601 u64 ept_mem_type = (spte & 0x38) >> 3;
5602
5603 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5604 ept_mem_type == 7) {
5605 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5606 __func__, ept_mem_type);
5607 WARN_ON(1);
5608 }
5609 }
5610 }
5611}
5612
851ba692 5613static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5614{
5615 u64 sptes[4];
ce88decf 5616 int nr_sptes, i, ret;
68f89400
MT		 5617 gpa_t gpa;
5618
5619 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5620 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5621 skip_emulated_instruction(vcpu);
5622 return 1;
5623 }
68f89400 5624
ce88decf 5625 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5626 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5627 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5628 EMULATE_DONE;
f8f55942
XG		 5629
5630 if (unlikely(ret == RET_MMIO_PF_INVALID))
5631 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5632
b37fbea6 5633 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5634 return 1;
5635
5636 /* It is the real ept misconfig */
68f89400
MT		 5637 printk(KERN_ERR "EPT: Misconfiguration.\n");
5638 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5639
5640 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5641
5642 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5643 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5644
851ba692
AK		 5645 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5646 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5647
5648 return 0;
5649}
5650
851ba692 5651static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5652{
5653 u32 cpu_based_vm_exec_control;
5654
5655 /* clear pending NMI */
5656 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5657 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5658 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5659 ++vcpu->stat.nmi_window_exits;
3842d135 5660 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5661
5662 return 1;
5663}
5664
80ced186 5665static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5666{
8b3079a5
AK		 5667 struct vcpu_vmx *vmx = to_vmx(vcpu);
5668 enum emulation_result err = EMULATE_DONE;
80ced186 5669 int ret = 1;
49e9d557
AK		 5670 u32 cpu_exec_ctrl;
5671 bool intr_window_requested;
b8405c18 5672 unsigned count = 130;
49e9d557
AK		 5673
5674 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5675 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5676
98eb2f8b 5677 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5678 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5679 return handle_interrupt_window(&vmx->vcpu);
5680
de87dcdd
AK		 5681 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5682 return 1;
5683
991eebf9 5684 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5685
ac0a48c3 5686 if (err == EMULATE_USER_EXIT) {
94452b9e 5687 ++vcpu->stat.mmio_exits;
80ced186
MG		 5688 ret = 0;
5689 goto out;
5690 }
1d5a4d9b 5691
de5f70e0
AK		 5692 if (err != EMULATE_DONE) {
5693 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5694 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5695 vcpu->run->internal.ndata = 0;
6d77dbfc 5696 return 0;
de5f70e0 5697 }
ea953ef0 5698
8d76c49e
GN		 5699 if (vcpu->arch.halt_request) {
5700 vcpu->arch.halt_request = 0;
5701 ret = kvm_emulate_halt(vcpu);
5702 goto out;
5703 }
5704
ea953ef0 5705 if (signal_pending(current))
80ced186 5706 goto out;
ea953ef0
MG		 5707 if (need_resched())
5708 schedule();
5709 }
5710
80ced186
MG		 5711out:
5712 return ret;
ea953ef0
MG		 5713}
5714
b4a2d31d
RK		 5715static int __grow_ple_window(int val)
5716{
5717 if (ple_window_grow < 1)
5718 return ple_window;
5719
5720 val = min(val, ple_window_actual_max);
5721
5722 if (ple_window_grow < ple_window)
5723 val *= ple_window_grow;
5724 else
5725 val += ple_window_grow;
5726
5727 return val;
5728}
5729
5730static int __shrink_ple_window(int val, int modifier, int minimum)
5731{
5732 if (modifier < 1)
5733 return ple_window;
5734
5735 if (modifier < ple_window)
5736 val /= modifier;
5737 else
5738 val -= modifier;
5739
5740 return max(val, minimum);
5741}
5742
5743static void grow_ple_window(struct kvm_vcpu *vcpu)
5744{
5745 struct vcpu_vmx *vmx = to_vmx(vcpu);
5746 int old = vmx->ple_window;
5747
5748 vmx->ple_window = __grow_ple_window(old);
5749
5750 if (vmx->ple_window != old)
5751 vmx->ple_window_dirty = true;
7b46268d
RK		 5752
5753 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5754}
5755
5756static void shrink_ple_window(struct kvm_vcpu *vcpu)
5757{
5758 struct vcpu_vmx *vmx = to_vmx(vcpu);
5759 int old = vmx->ple_window;
5760
5761 vmx->ple_window = __shrink_ple_window(old,
5762 ple_window_shrink, ple_window);
5763
5764 if (vmx->ple_window != old)
5765 vmx->ple_window_dirty = true;
7b46268d
RK		 5766
5767 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5768}
5769
5770/*
5771 * ple_window_actual_max is computed to be one grow_ple_window() below
5772 * ple_window_max. (See __grow_ple_window for the reason.)
5773 * This prevents overflows, because ple_window_max is int.
5774 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5775 * this process.
5776 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5777 */
5778static void update_ple_window_actual_max(void)
5779{
5780 ple_window_actual_max =
5781 __shrink_ple_window(max(ple_window_max, ple_window),
5782 ple_window_grow, INT_MIN);
5783}
5784
4b8d54f9
ZE		 5785/*
5786 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5787 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5788 */
9fb41ba8 5789static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5790{
b4a2d31d
RK		 5791 if (ple_gap)
5792 grow_ple_window(vcpu);
5793
4b8d54f9
ZE		 5794 skip_emulated_instruction(vcpu);
5795 kvm_vcpu_on_spin(vcpu);
5796
5797 return 1;
5798}
5799
87c00572 5800static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5801{
87c00572 5802 skip_emulated_instruction(vcpu);
59708670
SY		 5803 return 1;
5804}
5805
87c00572
GS		 5806static int handle_mwait(struct kvm_vcpu *vcpu)
5807{
5808 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5809 return handle_nop(vcpu);
5810}
5811
5812static int handle_monitor(struct kvm_vcpu *vcpu)
5813{
5814 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5815 return handle_nop(vcpu);
5816}
5817
ff2f6fe9
NHE		 5818/*
5819 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5820 * We could reuse a single VMCS for all the L2 guests, but we also want the
5821 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5822 * allows keeping them loaded on the processor, and in the future will allow
5823 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5824 * every entry if they never change.
5825 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5826 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5827 *
5828 * The following functions allocate and free a vmcs02 in this pool.
5829 */
5830
5831/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5832static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5833{
5834 struct vmcs02_list *item;
5835 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5836 if (item->vmptr == vmx->nested.current_vmptr) {
5837 list_move(&item->list, &vmx->nested.vmcs02_pool);
5838 return &item->vmcs02;
5839 }
5840
5841 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5842 /* Recycle the least recently used VMCS. */
5843 item = list_entry(vmx->nested.vmcs02_pool.prev,
5844 struct vmcs02_list, list);
5845 item->vmptr = vmx->nested.current_vmptr;
5846 list_move(&item->list, &vmx->nested.vmcs02_pool);
5847 return &item->vmcs02;
5848 }
5849
5850 /* Create a new VMCS */
0fa24ce3 5851 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5852 if (!item)
5853 return NULL;
5854 item->vmcs02.vmcs = alloc_vmcs();
5855 if (!item->vmcs02.vmcs) {
5856 kfree(item);
5857 return NULL;
5858 }
5859 loaded_vmcs_init(&item->vmcs02);
5860 item->vmptr = vmx->nested.current_vmptr;
5861 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5862 vmx->nested.vmcs02_num++;
5863 return &item->vmcs02;
5864}
5865
5866/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5867static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5868{
5869 struct vmcs02_list *item;
5870 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5871 if (item->vmptr == vmptr) {
5872 free_loaded_vmcs(&item->vmcs02);
5873 list_del(&item->list);
5874 kfree(item);
5875 vmx->nested.vmcs02_num--;
5876 return;
5877 }
5878}
5879
5880/*
5881 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5882 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5883 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5884 */
5885static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5886{
5887 struct vmcs02_list *item, *n;
4fa7734c
PB		 5888
5889 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5890 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5891 /*
5892 * Something will leak if the above WARN triggers. Better than
5893 * a use-after-free.
5894 */
5895 if (vmx->loaded_vmcs == &item->vmcs02)
5896 continue;
5897
5898 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5899 list_del(&item->list);
5900 kfree(item);
4fa7734c 5901 vmx->nested.vmcs02_num--;
ff2f6fe9 5902 }
ff2f6fe9
NHE		 5903}
5904
0658fbaa
ACL		 5905/*
5906 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5907 * set the success or error code of an emulated VMX instruction, as specified
5908 * by Vol 2B, VMX Instruction Reference, "Conventions".
5909 */
5910static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5911{
5912 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5913 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5914 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5915}
5916
5917static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5918{
5919 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5920 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5921 X86_EFLAGS_SF | X86_EFLAGS_OF))
5922 | X86_EFLAGS_CF);
5923}
5924
145c28dd 5925static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5926 u32 vm_instruction_error)
5927{
5928 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5929 /*
5930 * failValid writes the error number to the current VMCS, which
5931 * can't be done there isn't a current VMCS.
5932 */
5933 nested_vmx_failInvalid(vcpu);
5934 return;
5935 }
5936 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5937 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5938 X86_EFLAGS_SF | X86_EFLAGS_OF))
5939 | X86_EFLAGS_ZF);
5940 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5941 /*
5942 * We don't need to force a shadow sync because
5943 * VM_INSTRUCTION_ERROR is not shadowed
5944 */
5945}
145c28dd 5946
f4124500
JK		 5947static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5948{
5949 struct vcpu_vmx *vmx =
5950 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5951
5952 vmx->nested.preemption_timer_expired = true;
5953 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5954 kvm_vcpu_kick(&vmx->vcpu);
5955
5956 return HRTIMER_NORESTART;
5957}
5958
19677e32
BD		 5959/*
5960 * Decode the memory-address operand of a vmx instruction, as recorded on an
5961 * exit caused by such an instruction (run by a guest hypervisor).
5962 * On success, returns 0. When the operand is invalid, returns 1 and throws
5963 * #UD or #GP.
5964 */
5965static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5966 unsigned long exit_qualification,
5967 u32 vmx_instruction_info, gva_t *ret)
5968{
5969 /*
5970 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5971 * Execution", on an exit, vmx_instruction_info holds most of the
5972 * addressing components of the operand. Only the displacement part
5973 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5974 * For how an actual address is calculated from all these components,
5975 * refer to Vol. 1, "Operand Addressing".
5976 */
5977 int scaling = vmx_instruction_info & 3;
5978 int addr_size = (vmx_instruction_info >> 7) & 7;
5979 bool is_reg = vmx_instruction_info & (1u << 10);
5980 int seg_reg = (vmx_instruction_info >> 15) & 7;
5981 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5982 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5983 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5984 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5985
5986 if (is_reg) {
5987 kvm_queue_exception(vcpu, UD_VECTOR);
5988 return 1;
5989 }
5990
5991 /* Addr = segment_base + offset */
5992 /* offset = base + [index * scale] + displacement */
5993 *ret = vmx_get_segment_base(vcpu, seg_reg);
5994 if (base_is_valid)
5995 *ret += kvm_register_read(vcpu, base_reg);
5996 if (index_is_valid)
5997 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5998 *ret += exit_qualification; /* holds the displacement */
5999
6000 if (addr_size == 1) /* 32 bit */
6001 *ret &= 0xffffffff;
6002
6003 /*
6004 * TODO: throw #GP (and return 1) in various cases that the VM*
6005 * instructions require it - e.g., offset beyond segment limit,
6006 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6007 * address, and so on. Currently these are not checked.
6008 */
6009 return 0;
6010}
6011
3573e22c
BD		 6012/*
6013 * This function performs the various checks including
6014 * - if it's 4KB aligned
6015 * - No bits beyond the physical address width are set
6016 * - Returns 0 on success or else 1
4291b588 6017 * (Intel SDM Section 30.3)
3573e22c 6018 */
4291b588
BD		 6019static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6020 gpa_t *vmpointer)
3573e22c
BD		 6021{
6022 gva_t gva;
6023 gpa_t vmptr;
6024 struct x86_exception e;
6025 struct page *page;
6026 struct vcpu_vmx *vmx = to_vmx(vcpu);
6027 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6028
6029 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6030 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6031 return 1;
6032
6033 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6034 sizeof(vmptr), &e)) {
6035 kvm_inject_page_fault(vcpu, &e);
6036 return 1;
6037 }
6038
6039 switch (exit_reason) {
6040 case EXIT_REASON_VMON:
6041 /*
6042 * SDM 3: 24.11.5
6043 * The first 4 bytes of VMXON region contain the supported
6044 * VMCS revision identifier
6045 *
6046 * Note - IA32_VMX_BASIC[48] will never be 1
6047 * for the nested case;
6048 * which replaces physical address width with 32
6049 *
6050 */
bc39c4db 6051 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6052 nested_vmx_failInvalid(vcpu);
6053 skip_emulated_instruction(vcpu);
6054 return 1;
6055 }
6056
6057 page = nested_get_page(vcpu, vmptr);
6058 if (page == NULL ||
6059 *(u32 *)kmap(page) != VMCS12_REVISION) {
6060 nested_vmx_failInvalid(vcpu);
6061 kunmap(page);
6062 skip_emulated_instruction(vcpu);
6063 return 1;
6064 }
6065 kunmap(page);
6066 vmx->nested.vmxon_ptr = vmptr;
6067 break;
4291b588 6068 case EXIT_REASON_VMCLEAR:
bc39c4db 6069 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6070 nested_vmx_failValid(vcpu,
6071 VMXERR_VMCLEAR_INVALID_ADDRESS);
6072 skip_emulated_instruction(vcpu);
6073 return 1;
6074 }
6075
6076 if (vmptr == vmx->nested.vmxon_ptr) {
6077 nested_vmx_failValid(vcpu,
6078 VMXERR_VMCLEAR_VMXON_POINTER);
6079 skip_emulated_instruction(vcpu);
6080 return 1;
6081 }
6082 break;
6083 case EXIT_REASON_VMPTRLD:
bc39c4db 6084 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6085 nested_vmx_failValid(vcpu,
6086 VMXERR_VMPTRLD_INVALID_ADDRESS);
6087 skip_emulated_instruction(vcpu);
6088 return 1;
6089 }
3573e22c 6090
4291b588
BD		 6091 if (vmptr == vmx->nested.vmxon_ptr) {
6092 nested_vmx_failValid(vcpu,
6093 VMXERR_VMCLEAR_VMXON_POINTER);
6094 skip_emulated_instruction(vcpu);
6095 return 1;
6096 }
6097 break;
3573e22c
BD		 6098 default:
6099 return 1; /* shouldn't happen */
6100 }
6101
4291b588
BD		 6102 if (vmpointer)
6103 *vmpointer = vmptr;
3573e22c
BD		 6104 return 0;
6105}
6106
ec378aee
NHE		 6107/*
6108 * Emulate the VMXON instruction.
6109 * Currently, we just remember that VMX is active, and do not save or even
6110 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6111 * do not currently need to store anything in that guest-allocated memory
6112 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6113 * argument is different from the VMXON pointer (which the spec says they do).
6114 */
6115static int handle_vmon(struct kvm_vcpu *vcpu)
6116{
6117 struct kvm_segment cs;
6118 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6119 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6120 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6121 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6122
6123 /* The Intel VMX Instruction Reference lists a bunch of bits that
6124 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6125 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6126 * Otherwise, we should fail with #UD. We test these now:
6127 */
6128 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6129 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6130 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6131 kvm_queue_exception(vcpu, UD_VECTOR);
6132 return 1;
6133 }
6134
6135 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6136 if (is_long_mode(vcpu) && !cs.l) {
6137 kvm_queue_exception(vcpu, UD_VECTOR);
6138 return 1;
6139 }
6140
6141 if (vmx_get_cpl(vcpu)) {
6142 kvm_inject_gp(vcpu, 0);
6143 return 1;
6144 }
3573e22c 6145
4291b588 6146 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6147 return 1;
6148
145c28dd
AG		 6149 if (vmx->nested.vmxon) {
6150 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6151 skip_emulated_instruction(vcpu);
6152 return 1;
6153 }
b3897a49
NHE		 6154
6155 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6156 != VMXON_NEEDED_FEATURES) {
6157 kvm_inject_gp(vcpu, 0);
6158 return 1;
6159 }
6160
8de48833
AG		 6161 if (enable_shadow_vmcs) {
6162 shadow_vmcs = alloc_vmcs();
6163 if (!shadow_vmcs)
6164 return -ENOMEM;
6165 /* mark vmcs as shadow */
6166 shadow_vmcs->revision_id |= (1u << 31);
6167 /* init shadow vmcs */
6168 vmcs_clear(shadow_vmcs);
6169 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6170 }
ec378aee 6171
ff2f6fe9
NHE		 6172 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6173 vmx->nested.vmcs02_num = 0;
6174
f4124500
JK		 6175 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6176 HRTIMER_MODE_REL);
6177 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6178
ec378aee
NHE		 6179 vmx->nested.vmxon = true;
6180
6181 skip_emulated_instruction(vcpu);
a25eb114 6182 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6183 return 1;
6184}
6185
6186/*
6187 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6188 * for running VMX instructions (except VMXON, whose prerequisites are
6189 * slightly different). It also specifies what exception to inject otherwise.
6190 */
6191static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6192{
6193 struct kvm_segment cs;
6194 struct vcpu_vmx *vmx = to_vmx(vcpu);
6195
6196 if (!vmx->nested.vmxon) {
6197 kvm_queue_exception(vcpu, UD_VECTOR);
6198 return 0;
6199 }
6200
6201 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6202 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6203 (is_long_mode(vcpu) && !cs.l)) {
6204 kvm_queue_exception(vcpu, UD_VECTOR);
6205 return 0;
6206 }
6207
6208 if (vmx_get_cpl(vcpu)) {
6209 kvm_inject_gp(vcpu, 0);
6210 return 0;
6211 }
6212
6213 return 1;
6214}
6215
e7953d7f
AG		 6216static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6217{
8a1b9dd0 6218 u32 exec_control;
9a2a05b9
PB		 6219 if (vmx->nested.current_vmptr == -1ull)
6220 return;
6221
6222 /* current_vmptr and current_vmcs12 are always set/reset together */
6223 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6224 return;
6225
012f83cb 6226 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6227 /* copy to memory all shadowed fields in case
6228 they were modified */
6229 copy_shadow_to_vmcs12(vmx);
6230 vmx->nested.sync_shadow_vmcs = false;
6231 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6232 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6233 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6234 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6235 }
e7953d7f
AG		 6236 kunmap(vmx->nested.current_vmcs12_page);
6237 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6238 vmx->nested.current_vmptr = -1ull;
6239 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6240}
6241
ec378aee
NHE		 6242/*
6243 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6244 * just stops using VMX.
6245 */
6246static void free_nested(struct vcpu_vmx *vmx)
6247{
6248 if (!vmx->nested.vmxon)
6249 return;
9a2a05b9 6250
ec378aee 6251 vmx->nested.vmxon = false;
9a2a05b9 6252 nested_release_vmcs12(vmx);
e7953d7f
AG		 6253 if (enable_shadow_vmcs)
6254 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6255 /* Unpin physical memory we referred to in current vmcs02 */
6256 if (vmx->nested.apic_access_page) {
6257 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6258 vmx->nested.apic_access_page = NULL;
fe3ef05c 6259 }
a7c0b07d
WL		 6260 if (vmx->nested.virtual_apic_page) {
6261 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6262 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6263 }
ff2f6fe9
NHE		 6264
6265 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6266}
6267
6268/* Emulate the VMXOFF instruction */
6269static int handle_vmoff(struct kvm_vcpu *vcpu)
6270{
6271 if (!nested_vmx_check_permission(vcpu))
6272 return 1;
6273 free_nested(to_vmx(vcpu));
6274 skip_emulated_instruction(vcpu);
a25eb114 6275 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6276 return 1;
6277}
6278
27d6c865
NHE		 6279/* Emulate the VMCLEAR instruction */
6280static int handle_vmclear(struct kvm_vcpu *vcpu)
6281{
6282 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6283 gpa_t vmptr;
6284 struct vmcs12 *vmcs12;
6285 struct page *page;
27d6c865
NHE		 6286
6287 if (!nested_vmx_check_permission(vcpu))
6288 return 1;
6289
4291b588 6290 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6291 return 1;
27d6c865 6292
9a2a05b9 6293 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6294 nested_release_vmcs12(vmx);
27d6c865
NHE		 6295
6296 page = nested_get_page(vcpu, vmptr);
6297 if (page == NULL) {
6298 /*
6299 * For accurate processor emulation, VMCLEAR beyond available
6300 * physical memory should do nothing at all. However, it is
6301 * possible that a nested vmx bug, not a guest hypervisor bug,
6302 * resulted in this case, so let's shut down before doing any
6303 * more damage:
6304 */
6305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6306 return 1;
6307 }
6308 vmcs12 = kmap(page);
6309 vmcs12->launch_state = 0;
6310 kunmap(page);
6311 nested_release_page(page);
6312
6313 nested_free_vmcs02(vmx, vmptr);
6314
6315 skip_emulated_instruction(vcpu);
6316 nested_vmx_succeed(vcpu);
6317 return 1;
6318}
6319
cd232ad0
NHE		 6320static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6321
6322/* Emulate the VMLAUNCH instruction */
6323static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6324{
6325 return nested_vmx_run(vcpu, true);
6326}
6327
6328/* Emulate the VMRESUME instruction */
6329static int handle_vmresume(struct kvm_vcpu *vcpu)
6330{
6331
6332 return nested_vmx_run(vcpu, false);
6333}
6334
49f705c5
NHE		 6335enum vmcs_field_type {
6336 VMCS_FIELD_TYPE_U16 = 0,
6337 VMCS_FIELD_TYPE_U64 = 1,
6338 VMCS_FIELD_TYPE_U32 = 2,
6339 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6340};
6341
6342static inline int vmcs_field_type(unsigned long field)
6343{
6344 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6345 return VMCS_FIELD_TYPE_U32;
6346 return (field >> 13) & 0x3 ;
6347}
6348
6349static inline int vmcs_field_readonly(unsigned long field)
6350{
6351 return (((field >> 10) & 0x3) == 1);
6352}
6353
6354/*
6355 * Read a vmcs12 field. Since these can have varying lengths and we return
6356 * one type, we chose the biggest type (u64) and zero-extend the return value
6357 * to that size. Note that the caller, handle_vmread, might need to use only
6358 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6359 * 64-bit fields are to be returned).
6360 */
6361static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6362 unsigned long field, u64 *ret)
6363{
6364 short offset = vmcs_field_to_offset(field);
6365 char *p;
6366
6367 if (offset < 0)
6368 return 0;
6369
6370 p = ((char *)(get_vmcs12(vcpu))) + offset;
6371
6372 switch (vmcs_field_type(field)) {
6373 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6374 *ret = *((natural_width *)p);
6375 return 1;
6376 case VMCS_FIELD_TYPE_U16:
6377 *ret = *((u16 *)p);
6378 return 1;
6379 case VMCS_FIELD_TYPE_U32:
6380 *ret = *((u32 *)p);
6381 return 1;
6382 case VMCS_FIELD_TYPE_U64:
6383 *ret = *((u64 *)p);
6384 return 1;
6385 default:
6386 return 0; /* can never happen. */
6387 }
6388}
6389
20b97fea
AG		 6390
6391static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6392 unsigned long field, u64 field_value){
6393 short offset = vmcs_field_to_offset(field);
6394 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6395 if (offset < 0)
6396 return false;
6397
6398 switch (vmcs_field_type(field)) {
6399 case VMCS_FIELD_TYPE_U16:
6400 *(u16 *)p = field_value;
6401 return true;
6402 case VMCS_FIELD_TYPE_U32:
6403 *(u32 *)p = field_value;
6404 return true;
6405 case VMCS_FIELD_TYPE_U64:
6406 *(u64 *)p = field_value;
6407 return true;
6408 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6409 *(natural_width *)p = field_value;
6410 return true;
6411 default:
6412 return false; /* can never happen. */
6413 }
6414
6415}
6416
16f5b903
AG		 6417static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6418{
6419 int i;
6420 unsigned long field;
6421 u64 field_value;
6422 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6423 const unsigned long *fields = shadow_read_write_fields;
6424 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6425
6426 vmcs_load(shadow_vmcs);
6427
6428 for (i = 0; i < num_fields; i++) {
6429 field = fields[i];
6430 switch (vmcs_field_type(field)) {
6431 case VMCS_FIELD_TYPE_U16:
6432 field_value = vmcs_read16(field);
6433 break;
6434 case VMCS_FIELD_TYPE_U32:
6435 field_value = vmcs_read32(field);
6436 break;
6437 case VMCS_FIELD_TYPE_U64:
6438 field_value = vmcs_read64(field);
6439 break;
6440 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6441 field_value = vmcs_readl(field);
6442 break;
6443 }
6444 vmcs12_write_any(&vmx->vcpu, field, field_value);
6445 }
6446
6447 vmcs_clear(shadow_vmcs);
6448 vmcs_load(vmx->loaded_vmcs->vmcs);
6449}
6450
c3114420
AG		 6451static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6452{
c2bae893
MK		 6453 const unsigned long *fields[] = {
6454 shadow_read_write_fields,
6455 shadow_read_only_fields
c3114420 6456 };
c2bae893 6457 const int max_fields[] = {
c3114420
AG		 6458 max_shadow_read_write_fields,
6459 max_shadow_read_only_fields
6460 };
6461 int i, q;
6462 unsigned long field;
6463 u64 field_value = 0;
6464 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6465
6466 vmcs_load(shadow_vmcs);
6467
c2bae893 6468 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6469 for (i = 0; i < max_fields[q]; i++) {
6470 field = fields[q][i];
6471 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6472
6473 switch (vmcs_field_type(field)) {
6474 case VMCS_FIELD_TYPE_U16:
6475 vmcs_write16(field, (u16)field_value);
6476 break;
6477 case VMCS_FIELD_TYPE_U32:
6478 vmcs_write32(field, (u32)field_value);
6479 break;
6480 case VMCS_FIELD_TYPE_U64:
6481 vmcs_write64(field, (u64)field_value);
6482 break;
6483 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6484 vmcs_writel(field, (long)field_value);
6485 break;
6486 }
6487 }
6488 }
6489
6490 vmcs_clear(shadow_vmcs);
6491 vmcs_load(vmx->loaded_vmcs->vmcs);
6492}
6493
49f705c5
NHE		 6494/*
6495 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6496 * used before) all generate the same failure when it is missing.
6497 */
6498static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6499{
6500 struct vcpu_vmx *vmx = to_vmx(vcpu);
6501 if (vmx->nested.current_vmptr == -1ull) {
6502 nested_vmx_failInvalid(vcpu);
6503 skip_emulated_instruction(vcpu);
6504 return 0;
6505 }
6506 return 1;
6507}
6508
6509static int handle_vmread(struct kvm_vcpu *vcpu)
6510{
6511 unsigned long field;
6512 u64 field_value;
6513 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6514 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6515 gva_t gva = 0;
6516
6517 if (!nested_vmx_check_permission(vcpu) ||
6518 !nested_vmx_check_vmcs12(vcpu))
6519 return 1;
6520
6521 /* Decode instruction info and find the field to read */
27e6fb5d 6522 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6523 /* Read the field, zero-extended to a u64 field_value */
6524 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6525 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6526 skip_emulated_instruction(vcpu);
6527 return 1;
6528 }
6529 /*
6530 * Now copy part of this value to register or memory, as requested.
6531 * Note that the number of bits actually copied is 32 or 64 depending
6532 * on the guest's mode (32 or 64 bit), not on the given field's length.
6533 */
6534 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6535 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6536 field_value);
6537 } else {
6538 if (get_vmx_mem_address(vcpu, exit_qualification,
6539 vmx_instruction_info, &gva))
6540 return 1;
6541 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6542 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6543 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6544 }
6545
6546 nested_vmx_succeed(vcpu);
6547 skip_emulated_instruction(vcpu);
6548 return 1;
6549}
6550
6551
6552static int handle_vmwrite(struct kvm_vcpu *vcpu)
6553{
6554 unsigned long field;
6555 gva_t gva;
6556 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6557 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6558 /* The value to write might be 32 or 64 bits, depending on L1's long
6559 * mode, and eventually we need to write that into a field of several
6560 * possible lengths. The code below first zero-extends the value to 64
6561 * bit (field_value), and then copies only the approriate number of
6562 * bits into the vmcs12 field.
6563 */
6564 u64 field_value = 0;
6565 struct x86_exception e;
6566
6567 if (!nested_vmx_check_permission(vcpu) ||
6568 !nested_vmx_check_vmcs12(vcpu))
6569 return 1;
6570
6571 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6572 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6573 (((vmx_instruction_info) >> 3) & 0xf));
6574 else {
6575 if (get_vmx_mem_address(vcpu, exit_qualification,
6576 vmx_instruction_info, &gva))
6577 return 1;
6578 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6579 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6580 kvm_inject_page_fault(vcpu, &e);
6581 return 1;
6582 }
6583 }
6584
6585
27e6fb5d 6586 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6587 if (vmcs_field_readonly(field)) {
6588 nested_vmx_failValid(vcpu,
6589 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6590 skip_emulated_instruction(vcpu);
6591 return 1;
6592 }
6593
20b97fea 6594 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6595 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6596 skip_emulated_instruction(vcpu);
6597 return 1;
6598 }
6599
6600 nested_vmx_succeed(vcpu);
6601 skip_emulated_instruction(vcpu);
6602 return 1;
6603}
6604
63846663
NHE		 6605/* Emulate the VMPTRLD instruction */
6606static int handle_vmptrld(struct kvm_vcpu *vcpu)
6607{
6608 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6609 gpa_t vmptr;
8a1b9dd0 6610 u32 exec_control;
63846663
NHE		 6611
6612 if (!nested_vmx_check_permission(vcpu))
6613 return 1;
6614
4291b588 6615 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6616 return 1;
63846663
NHE		 6617
6618 if (vmx->nested.current_vmptr != vmptr) {
6619 struct vmcs12 *new_vmcs12;
6620 struct page *page;
6621 page = nested_get_page(vcpu, vmptr);
6622 if (page == NULL) {
6623 nested_vmx_failInvalid(vcpu);
6624 skip_emulated_instruction(vcpu);
6625 return 1;
6626 }
6627 new_vmcs12 = kmap(page);
6628 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6629 kunmap(page);
6630 nested_release_page_clean(page);
6631 nested_vmx_failValid(vcpu,
6632 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6633 skip_emulated_instruction(vcpu);
6634 return 1;
6635 }
63846663 6636
9a2a05b9 6637 nested_release_vmcs12(vmx);
63846663
NHE		 6638 vmx->nested.current_vmptr = vmptr;
6639 vmx->nested.current_vmcs12 = new_vmcs12;
6640 vmx->nested.current_vmcs12_page = page;
012f83cb 6641 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6642 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6643 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6644 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6645 vmcs_write64(VMCS_LINK_POINTER,
6646 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6647 vmx->nested.sync_shadow_vmcs = true;
6648 }
63846663
NHE		 6649 }
6650
6651 nested_vmx_succeed(vcpu);
6652 skip_emulated_instruction(vcpu);
6653 return 1;
6654}
6655
6a4d7550
NHE		 6656/* Emulate the VMPTRST instruction */
6657static int handle_vmptrst(struct kvm_vcpu *vcpu)
6658{
6659 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6660 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6661 gva_t vmcs_gva;
6662 struct x86_exception e;
6663
6664 if (!nested_vmx_check_permission(vcpu))
6665 return 1;
6666
6667 if (get_vmx_mem_address(vcpu, exit_qualification,
6668 vmx_instruction_info, &vmcs_gva))
6669 return 1;
6670 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6671 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6672 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6673 sizeof(u64), &e)) {
6674 kvm_inject_page_fault(vcpu, &e);
6675 return 1;
6676 }
6677 nested_vmx_succeed(vcpu);
6678 skip_emulated_instruction(vcpu);
6679 return 1;
6680}
6681
bfd0a56b
NHE		 6682/* Emulate the INVEPT instruction */
6683static int handle_invept(struct kvm_vcpu *vcpu)
6684{
6685 u32 vmx_instruction_info, types;
6686 unsigned long type;
6687 gva_t gva;
6688 struct x86_exception e;
6689 struct {
6690 u64 eptp, gpa;
6691 } operand;
bfd0a56b
NHE		 6692
6693 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6694 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6695 kvm_queue_exception(vcpu, UD_VECTOR);
6696 return 1;
6697 }
6698
6699 if (!nested_vmx_check_permission(vcpu))
6700 return 1;
6701
6702 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6703 kvm_queue_exception(vcpu, UD_VECTOR);
6704 return 1;
6705 }
6706
6707 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6708 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6709
6710 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6711
6712 if (!(types & (1UL << type))) {
6713 nested_vmx_failValid(vcpu,
6714 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6715 return 1;
6716 }
6717
6718 /* According to the Intel VMX instruction reference, the memory
6719 * operand is read even if it isn't needed (e.g., for type==global)
6720 */
6721 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6722 vmx_instruction_info, &gva))
6723 return 1;
6724 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6725 sizeof(operand), &e)) {
6726 kvm_inject_page_fault(vcpu, &e);
6727 return 1;
6728 }
6729
6730 switch (type) {
bfd0a56b
NHE		 6731 case VMX_EPT_EXTENT_GLOBAL:
6732 kvm_mmu_sync_roots(vcpu);
77c3913b 6733 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6734 nested_vmx_succeed(vcpu);
6735 break;
6736 default:
4b855078 6737 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6738 BUG_ON(1);
6739 break;
6740 }
6741
6742 skip_emulated_instruction(vcpu);
6743 return 1;
6744}
6745
6aa8b732
AK		 6746/*
6747 * The exit handlers return 1 if the exit was handled fully and guest execution
6748 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6749 * to be done to userspace and return 0.
6750 */
772e0318 6751static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6752 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6753 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6754 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6755 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6756 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6757 [EXIT_REASON_CR_ACCESS] = handle_cr,
6758 [EXIT_REASON_DR_ACCESS] = handle_dr,
6759 [EXIT_REASON_CPUID] = handle_cpuid,
6760 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6761 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6762 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6763 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6764 [EXIT_REASON_INVD] = handle_invd,
a7052897 6765 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6766 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6767 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6768 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6769 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6770 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6771 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6772 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6773 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6774 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6775 [EXIT_REASON_VMOFF] = handle_vmoff,
6776 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6777 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6778 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6779 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6780 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6781 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6782 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6783 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6784 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6785 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6786 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6787 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6788 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6789 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6790 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6791};
6792
6793static const int kvm_vmx_max_exit_handlers =
50a3485c 6794 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6795
908a7bdd
JK		 6796static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6797 struct vmcs12 *vmcs12)
6798{
6799 unsigned long exit_qualification;
6800 gpa_t bitmap, last_bitmap;
6801 unsigned int port;
6802 int size;
6803 u8 b;
6804
908a7bdd 6805 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6806 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6807
6808 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6809
6810 port = exit_qualification >> 16;
6811 size = (exit_qualification & 7) + 1;
6812
6813 last_bitmap = (gpa_t)-1;
6814 b = -1;
6815
6816 while (size > 0) {
6817 if (port < 0x8000)
6818 bitmap = vmcs12->io_bitmap_a;
6819 else if (port < 0x10000)
6820 bitmap = vmcs12->io_bitmap_b;
6821 else
6822 return 1;
6823 bitmap += (port & 0x7fff) / 8;
6824
6825 if (last_bitmap != bitmap)
6826 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6827 return 1;
6828 if (b & (1 << (port & 7)))
6829 return 1;
6830
6831 port++;
6832 size--;
6833 last_bitmap = bitmap;
6834 }
6835
6836 return 0;
6837}
6838
644d711a
NHE		 6839/*
6840 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6841 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6842 * disinterest in the current event (read or write a specific MSR) by using an
6843 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6844 */
6845static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6846 struct vmcs12 *vmcs12, u32 exit_reason)
6847{
6848 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6849 gpa_t bitmap;
6850
cbd29cb6 6851 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6852 return 1;
6853
6854 /*
6855 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6856 * for the four combinations of read/write and low/high MSR numbers.
6857 * First we need to figure out which of the four to use:
6858 */
6859 bitmap = vmcs12->msr_bitmap;
6860 if (exit_reason == EXIT_REASON_MSR_WRITE)
6861 bitmap += 2048;
6862 if (msr_index >= 0xc0000000) {
6863 msr_index -= 0xc0000000;
6864 bitmap += 1024;
6865 }
6866
6867 /* Then read the msr_index'th bit from this bitmap: */
6868 if (msr_index < 1024*8) {
6869 unsigned char b;
bd31a7f5
JK		 6870 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6871 return 1;
644d711a
NHE		 6872 return 1 & (b >> (msr_index & 7));
6873 } else
6874 return 1; /* let L1 handle the wrong parameter */
6875}
6876
6877/*
6878 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6879 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6880 * intercept (via guest_host_mask etc.) the current event.
6881 */
6882static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6883 struct vmcs12 *vmcs12)
6884{
6885 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6886 int cr = exit_qualification & 15;
6887 int reg = (exit_qualification >> 8) & 15;
1e32c079 6888 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6889
6890 switch ((exit_qualification >> 4) & 3) {
6891 case 0: /* mov to cr */
6892 switch (cr) {
6893 case 0:
6894 if (vmcs12->cr0_guest_host_mask &
6895 (val ^ vmcs12->cr0_read_shadow))
6896 return 1;
6897 break;
6898 case 3:
6899 if ((vmcs12->cr3_target_count >= 1 &&
6900 vmcs12->cr3_target_value0 == val) ||
6901 (vmcs12->cr3_target_count >= 2 &&
6902 vmcs12->cr3_target_value1 == val) ||
6903 (vmcs12->cr3_target_count >= 3 &&
6904 vmcs12->cr3_target_value2 == val) ||
6905 (vmcs12->cr3_target_count >= 4 &&
6906 vmcs12->cr3_target_value3 == val))
6907 return 0;
6908 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6909 return 1;
6910 break;
6911 case 4:
6912 if (vmcs12->cr4_guest_host_mask &
6913 (vmcs12->cr4_read_shadow ^ val))
6914 return 1;
6915 break;
6916 case 8:
6917 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6918 return 1;
6919 break;
6920 }
6921 break;
6922 case 2: /* clts */
6923 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6924 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6925 return 1;
6926 break;
6927 case 1: /* mov from cr */
6928 switch (cr) {
6929 case 3:
6930 if (vmcs12->cpu_based_vm_exec_control &
6931 CPU_BASED_CR3_STORE_EXITING)
6932 return 1;
6933 break;
6934 case 8:
6935 if (vmcs12->cpu_based_vm_exec_control &
6936 CPU_BASED_CR8_STORE_EXITING)
6937 return 1;
6938 break;
6939 }
6940 break;
6941 case 3: /* lmsw */
6942 /*
6943 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6944 * cr0. Other attempted changes are ignored, with no exit.
6945 */
6946 if (vmcs12->cr0_guest_host_mask & 0xe &
6947 (val ^ vmcs12->cr0_read_shadow))
6948 return 1;
6949 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6950 !(vmcs12->cr0_read_shadow & 0x1) &&
6951 (val & 0x1))
6952 return 1;
6953 break;
6954 }
6955 return 0;
6956}
6957
6958/*
6959 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6960 * should handle it ourselves in L0 (and then continue L2). Only call this
6961 * when in is_guest_mode (L2).
6962 */
6963static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6964{
644d711a
NHE		 6965 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6966 struct vcpu_vmx *vmx = to_vmx(vcpu);
6967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6968 u32 exit_reason = vmx->exit_reason;
644d711a 6969
542060ea
JK		 6970 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6971 vmcs_readl(EXIT_QUALIFICATION),
6972 vmx->idt_vectoring_info,
6973 intr_info,
6974 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6975 KVM_ISA_VMX);
6976
644d711a
NHE		 6977 if (vmx->nested.nested_run_pending)
6978 return 0;
6979
6980 if (unlikely(vmx->fail)) {
bd80158a
JK		 6981 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6982 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6983 return 1;
6984 }
6985
6986 switch (exit_reason) {
6987 case EXIT_REASON_EXCEPTION_NMI:
6988 if (!is_exception(intr_info))
6989 return 0;
6990 else if (is_page_fault(intr_info))
6991 return enable_ept;
e504c909 6992 else if (is_no_device(intr_info) &&
ccf9844e 6993 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6994 return 0;
644d711a
NHE		 6995 return vmcs12->exception_bitmap &
6996 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6997 case EXIT_REASON_EXTERNAL_INTERRUPT:
6998 return 0;
6999 case EXIT_REASON_TRIPLE_FAULT:
7000 return 1;
7001 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7002 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7003 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7004 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7005 case EXIT_REASON_TASK_SWITCH:
7006 return 1;
7007 case EXIT_REASON_CPUID:
bc613494
MT		 7008 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7009 return 0;
644d711a
NHE		 7010 return 1;
7011 case EXIT_REASON_HLT:
7012 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7013 case EXIT_REASON_INVD:
7014 return 1;
7015 case EXIT_REASON_INVLPG:
7016 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7017 case EXIT_REASON_RDPMC:
7018 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7019 case EXIT_REASON_RDTSC:
7020 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7021 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7022 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7023 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7024 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7025 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 7026 case EXIT_REASON_INVEPT:
644d711a
NHE		 7027 /*
7028 * VMX instructions trap unconditionally. This allows L1 to
7029 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7030 */
7031 return 1;
7032 case EXIT_REASON_CR_ACCESS:
7033 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7034 case EXIT_REASON_DR_ACCESS:
7035 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7036 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7037 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7038 case EXIT_REASON_MSR_READ:
7039 case EXIT_REASON_MSR_WRITE:
7040 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7041 case EXIT_REASON_INVALID_STATE:
7042 return 1;
7043 case EXIT_REASON_MWAIT_INSTRUCTION:
7044 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7045 case EXIT_REASON_MONITOR_INSTRUCTION:
7046 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7047 case EXIT_REASON_PAUSE_INSTRUCTION:
7048 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7049 nested_cpu_has2(vmcs12,
7050 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7051 case EXIT_REASON_MCE_DURING_VMENTRY:
7052 return 0;
7053 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7054 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7055 case EXIT_REASON_APIC_ACCESS:
7056 return nested_cpu_has2(vmcs12,
7057 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7058 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7059 /*
7060 * L0 always deals with the EPT violation. If nested EPT is
7061 * used, and the nested mmu code discovers that the address is
7062 * missing in the guest EPT table (EPT12), the EPT violation
7063 * will be injected with nested_ept_inject_page_fault()
7064 */
7065 return 0;
644d711a 7066 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7067 /*
7068 * L2 never uses directly L1's EPT, but rather L0's own EPT
7069 * table (shadow on EPT) or a merged EPT table that L0 built
7070 * (EPT on EPT). So any problems with the structure of the
7071 * table is L0's fault.
7072 */
644d711a
NHE		 7073 return 0;
7074 case EXIT_REASON_WBINVD:
7075 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7076 case EXIT_REASON_XSETBV:
7077 return 1;
7078 default:
7079 return 1;
7080 }
7081}
7082
586f9607
AK		 7083static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7084{
7085 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7086 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7087}
7088
6aa8b732
AK		 7089/*
7090 * The guest has exited. See if we can fix it or if we need userspace
7091 * assistance.
7092 */
851ba692 7093static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7094{
29bd8a78 7095 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7096 u32 exit_reason = vmx->exit_reason;
1155f76a 7097 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7098
80ced186 7099 /* If guest state is invalid, start emulating */
14168786 7100 if (vmx->emulation_required)
80ced186 7101 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7102
644d711a 7103 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7104 nested_vmx_vmexit(vcpu, exit_reason,
7105 vmcs_read32(VM_EXIT_INTR_INFO),
7106 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7107 return 1;
7108 }
7109
5120702e
MG		 7110 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7111 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7112 vcpu->run->fail_entry.hardware_entry_failure_reason
7113 = exit_reason;
7114 return 0;
7115 }
7116
29bd8a78 7117 if (unlikely(vmx->fail)) {
851ba692
AK		 7118 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7119 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7120 = vmcs_read32(VM_INSTRUCTION_ERROR);
7121 return 0;
7122 }
6aa8b732 7123
b9bf6882
XG		 7124 /*
7125 * Note:
7126 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7127 * delivery event since it indicates guest is accessing MMIO.
7128 * The vm-exit can be triggered again after return to guest that
7129 * will cause infinite loop.
7130 */
d77c26fc 7131 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7132 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7133 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7134 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7135 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7136 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7137 vcpu->run->internal.ndata = 2;
7138 vcpu->run->internal.data[0] = vectoring_info;
7139 vcpu->run->internal.data[1] = exit_reason;
7140 return 0;
7141 }
3b86cd99 7142
644d711a
NHE		 7143 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7144 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7145 get_vmcs12(vcpu))))) {
c4282df9 7146 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7147 vmx->soft_vnmi_blocked = 0;
3b86cd99 7148 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7149 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7150 /*
7151 * This CPU don't support us in finding the end of an
7152 * NMI-blocked window if the guest runs with IRQs
7153 * disabled. So we pull the trigger after 1 s of
7154 * futile waiting, but inform the user about this.
7155 */
7156 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7157 "state on VCPU %d after 1 s timeout\n",
7158 __func__, vcpu->vcpu_id);
7159 vmx->soft_vnmi_blocked = 0;
3b86cd99 7160 }
3b86cd99
JK		 7161 }
7162
6aa8b732
AK		 7163 if (exit_reason < kvm_vmx_max_exit_handlers
7164 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7165 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7166 else {
851ba692
AK		 7167 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7168 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7169 }
7170 return 0;
7171}
7172
95ba8273 7173static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7174{
a7c0b07d
WL		 7175 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7176
7177 if (is_guest_mode(vcpu) &&
7178 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7179 return;
7180
95ba8273 7181 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7182 vmcs_write32(TPR_THRESHOLD, 0);
7183 return;
7184 }
7185
95ba8273 7186 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7187}
7188
8d14695f
YZ		 7189static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7190{
7191 u32 sec_exec_control;
7192
7193 /*
7194 * There is not point to enable virtualize x2apic without enable
7195 * apicv
7196 */
c7c9c56c
YZ		 7197 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7198 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7199 return;
7200
7201 if (!vm_need_tpr_shadow(vcpu->kvm))
7202 return;
7203
7204 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7205
7206 if (set) {
7207 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7208 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7209 } else {
7210 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7211 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7212 }
7213 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7214
7215 vmx_set_msr_bitmap(vcpu);
7216}
7217
38b99173
TC		 7218static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7219{
7220 struct vcpu_vmx *vmx = to_vmx(vcpu);
7221
7222 /*
7223 * Currently we do not handle the nested case where L2 has an
7224 * APIC access page of its own; that page is still pinned.
7225 * Hence, we skip the case where the VCPU is in guest mode _and_
7226 * L1 prepared an APIC access page for L2.
7227 *
7228 * For the case where L1 and L2 share the same APIC access page
7229 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7230 * in the vmcs12), this function will only update either the vmcs01
7231 * or the vmcs02. If the former, the vmcs02 will be updated by
7232 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7233 * the next L2->L1 exit.
7234 */
7235 if (!is_guest_mode(vcpu) ||
7236 !nested_cpu_has2(vmx->nested.current_vmcs12,
7237 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7238 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7239}
7240
c7c9c56c
YZ		 7241static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7242{
7243 u16 status;
7244 u8 old;
7245
7246 if (!vmx_vm_has_apicv(kvm))
7247 return;
7248
7249 if (isr == -1)
7250 isr = 0;
7251
7252 status = vmcs_read16(GUEST_INTR_STATUS);
7253 old = status >> 8;
7254 if (isr != old) {
7255 status &= 0xff;
7256 status |= isr << 8;
7257 vmcs_write16(GUEST_INTR_STATUS, status);
7258 }
7259}
7260
7261static void vmx_set_rvi(int vector)
7262{
7263 u16 status;
7264 u8 old;
7265
7266 status = vmcs_read16(GUEST_INTR_STATUS);
7267 old = (u8)status & 0xff;
7268 if ((u8)vector != old) {
7269 status &= ~0xff;
7270 status |= (u8)vector;
7271 vmcs_write16(GUEST_INTR_STATUS, status);
7272 }
7273}
7274
7275static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7276{
7277 if (max_irr == -1)
7278 return;
7279
963fee16
WL		 7280 /*
7281 * If a vmexit is needed, vmx_check_nested_events handles it.
7282 */
7283 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7284 return;
7285
7286 if (!is_guest_mode(vcpu)) {
7287 vmx_set_rvi(max_irr);
7288 return;
7289 }
7290
7291 /*
7292 * Fall back to pre-APICv interrupt injection since L2
7293 * is run without virtual interrupt delivery.
7294 */
7295 if (!kvm_event_needs_reinjection(vcpu) &&
7296 vmx_interrupt_allowed(vcpu)) {
7297 kvm_queue_interrupt(vcpu, max_irr, false);
7298 vmx_inject_irq(vcpu);
7299 }
c7c9c56c
YZ		 7300}
7301
7302static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7303{
3d81bc7e
YZ		 7304 if (!vmx_vm_has_apicv(vcpu->kvm))
7305 return;
7306
c7c9c56c
YZ		 7307 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7308 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7309 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7310 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7311}
7312
51aa01d1 7313static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7314{
00eba012
AK		 7315 u32 exit_intr_info;
7316
7317 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7318 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7319 return;
7320
c5ca8e57 7321 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7322 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7323
7324 /* Handle machine checks before interrupts are enabled */
00eba012 7325 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7326 kvm_machine_check();
7327
20f65983 7328 /* We need to handle NMIs before interrupts are enabled */
00eba012 7329 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7330 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7331 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7332 asm("int $2");
ff9d07a0
ZY		 7333 kvm_after_handle_nmi(&vmx->vcpu);
7334 }
51aa01d1 7335}
20f65983 7336
a547c6db
YZ		 7337static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7338{
7339 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7340
7341 /*
7342 * If external interrupt exists, IF bit is set in rflags/eflags on the
7343 * interrupt stack frame, and interrupt will be enabled on a return
7344 * from interrupt handler.
7345 */
7346 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7347 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7348 unsigned int vector;
7349 unsigned long entry;
7350 gate_desc *desc;
7351 struct vcpu_vmx *vmx = to_vmx(vcpu);
7352#ifdef CONFIG_X86_64
7353 unsigned long tmp;
7354#endif
7355
7356 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7357 desc = (gate_desc *)vmx->host_idt_base + vector;
7358 entry = gate_offset(*desc);
7359 asm volatile(
7360#ifdef CONFIG_X86_64
7361 "mov %%" _ASM_SP ", %[sp]\n\t"
7362 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7363 "push $%c[ss]\n\t"
7364 "push %[sp]\n\t"
7365#endif
7366 "pushf\n\t"
7367 "orl $0x200, (%%" _ASM_SP ")\n\t"
7368 __ASM_SIZE(push) " $%c[cs]\n\t"
7369 "call *%[entry]\n\t"
7370 :
7371#ifdef CONFIG_X86_64
7372 [sp]"=&r"(tmp)
7373#endif
7374 :
7375 [entry]"r"(entry),
7376 [ss]"i"(__KERNEL_DS),
7377 [cs]"i"(__KERNEL_CS)
7378 );
7379 } else
7380 local_irq_enable();
7381}
7382
da8999d3
LJ		 7383static bool vmx_mpx_supported(void)
7384{
7385 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7386 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7387}
7388
51aa01d1
AK		 7389static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7390{
c5ca8e57 7391 u32 exit_intr_info;
51aa01d1
AK		 7392 bool unblock_nmi;
7393 u8 vector;
7394 bool idtv_info_valid;
7395
7396 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7397
cf393f75 7398 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7399 if (vmx->nmi_known_unmasked)
7400 return;
c5ca8e57
AK		 7401 /*
7402 * Can't use vmx->exit_intr_info since we're not sure what
7403 * the exit reason is.
7404 */
7405 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7406 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7407 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7408 /*
7b4a25cb 7409 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7410 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7411 * a guest IRET fault.
7b4a25cb
GN		 7412 * SDM 3: 23.2.2 (September 2008)
7413 * Bit 12 is undefined in any of the following cases:
7414 * If the VM exit sets the valid bit in the IDT-vectoring
7415 * information field.
7416 * If the VM exit is due to a double fault.
cf393f75 7417 */
7b4a25cb
GN		 7418 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7419 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7420 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7421 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7422 else
7423 vmx->nmi_known_unmasked =
7424 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7425 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7426 } else if (unlikely(vmx->soft_vnmi_blocked))
7427 vmx->vnmi_blocked_time +=
7428 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7429}
7430
3ab66e8a 7431static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7432 u32 idt_vectoring_info,
7433 int instr_len_field,
7434 int error_code_field)
51aa01d1 7435{
51aa01d1
AK		 7436 u8 vector;
7437 int type;
7438 bool idtv_info_valid;
7439
7440 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7441
3ab66e8a
JK		 7442 vcpu->arch.nmi_injected = false;
7443 kvm_clear_exception_queue(vcpu);
7444 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7445
7446 if (!idtv_info_valid)
7447 return;
7448
3ab66e8a 7449 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7450
668f612f
AK		 7451 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7452 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7453
64a7ec06 7454 switch (type) {
37b96e98 7455 case INTR_TYPE_NMI_INTR:
3ab66e8a 7456 vcpu->arch.nmi_injected = true;
668f612f 7457 /*
7b4a25cb 7458 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7459 * Clear bit "block by NMI" before VM entry if a NMI
7460 * delivery faulted.
668f612f 7461 */
3ab66e8a 7462 vmx_set_nmi_mask(vcpu, false);
37b96e98 7463 break;
37b96e98 7464 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7465 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7466 /* fall through */
7467 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7468 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7469 u32 err = vmcs_read32(error_code_field);
851eb667 7470 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7471 } else
851eb667 7472 kvm_requeue_exception(vcpu, vector);
37b96e98 7473 break;
66fd3f7f 7474 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7475 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7476 /* fall through */
37b96e98 7477 case INTR_TYPE_EXT_INTR:
3ab66e8a 7478 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7479 break;
7480 default:
7481 break;
f7d9238f 7482 }
cf393f75
AK		 7483}
7484
83422e17
AK		 7485static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7486{
3ab66e8a 7487 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7488 VM_EXIT_INSTRUCTION_LEN,
7489 IDT_VECTORING_ERROR_CODE);
7490}
7491
b463a6f7
AK		 7492static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7493{
3ab66e8a 7494 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7495 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7496 VM_ENTRY_INSTRUCTION_LEN,
7497 VM_ENTRY_EXCEPTION_ERROR_CODE);
7498
7499 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7500}
7501
d7cd9796
GN		 7502static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7503{
7504 int i, nr_msrs;
7505 struct perf_guest_switch_msr *msrs;
7506
7507 msrs = perf_guest_get_msrs(&nr_msrs);
7508
7509 if (!msrs)
7510 return;
7511
7512 for (i = 0; i < nr_msrs; i++)
7513 if (msrs[i].host == msrs[i].guest)
7514 clear_atomic_switch_msr(vmx, msrs[i].msr);
7515 else
7516 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7517 msrs[i].host);
7518}
7519
a3b5ba49 7520static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7521{
a2fa3e9f 7522 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7523 unsigned long debugctlmsr, cr4;
104f226b
AK		 7524
7525 /* Record the guest's net vcpu time for enforced NMI injections. */
7526 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7527 vmx->entry_time = ktime_get();
7528
7529 /* Don't enter VMX if guest state is invalid, let the exit handler
7530 start emulation until we arrive back to a valid state */
14168786 7531 if (vmx->emulation_required)
104f226b
AK		 7532 return;
7533
a7653ecd
RK		 7534 if (vmx->ple_window_dirty) {
7535 vmx->ple_window_dirty = false;
7536 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7537 }
7538
012f83cb
AG		 7539 if (vmx->nested.sync_shadow_vmcs) {
7540 copy_vmcs12_to_shadow(vmx);
7541 vmx->nested.sync_shadow_vmcs = false;
7542 }
7543
104f226b
AK		 7544 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7545 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7546 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7547 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7548
d974baa3
AL		 7549 cr4 = read_cr4();
7550 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7551 vmcs_writel(HOST_CR4, cr4);
7552 vmx->host_state.vmcs_host_cr4 = cr4;
7553 }
7554
104f226b
AK		 7555 /* When single-stepping over STI and MOV SS, we must clear the
7556 * corresponding interruptibility bits in the guest state. Otherwise
7557 * vmentry fails as it then expects bit 14 (BS) in pending debug
7558 * exceptions being set, but that's not correct for the guest debugging
7559 * case. */
7560 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7561 vmx_set_interrupt_shadow(vcpu, 0);
7562
d7cd9796 7563 atomic_switch_perf_msrs(vmx);
2a7921b7 7564 debugctlmsr = get_debugctlmsr();
d7cd9796 7565
d462b819 7566 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7567 asm(
6aa8b732 7568 /* Store host registers */
b188c81f
AK		 7569 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7570 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7571 "push %%" _ASM_CX " \n\t"
7572 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7573 "je 1f \n\t"
b188c81f 7574 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7575 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7576 "1: \n\t"
d3edefc0 7577 /* Reload cr2 if changed */
b188c81f
AK		 7578 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7579 "mov %%cr2, %%" _ASM_DX " \n\t"
7580 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7581 "je 2f \n\t"
b188c81f 7582 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7583 "2: \n\t"
6aa8b732 7584 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7585 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7586 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7587 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7588 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7589 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7590 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7591 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7592 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7593#ifdef CONFIG_X86_64
e08aa78a
AK		 7594 "mov %c[r8](%0), %%r8 \n\t"
7595 "mov %c[r9](%0), %%r9 \n\t"
7596 "mov %c[r10](%0), %%r10 \n\t"
7597 "mov %c[r11](%0), %%r11 \n\t"
7598 "mov %c[r12](%0), %%r12 \n\t"
7599 "mov %c[r13](%0), %%r13 \n\t"
7600 "mov %c[r14](%0), %%r14 \n\t"
7601 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7602#endif
b188c81f 7603 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7604
6aa8b732 7605 /* Enter guest mode */
83287ea4 7606 "jne 1f \n\t"
4ecac3fd 7607 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7608 "jmp 2f \n\t"
7609 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7610 "2: "
6aa8b732 7611 /* Save guest registers, load host registers, keep flags */
b188c81f 7612 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7613 "pop %0 \n\t"
b188c81f
AK		 7614 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7615 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7616 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7617 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7618 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7619 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7620 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7621#ifdef CONFIG_X86_64
e08aa78a
AK		 7622 "mov %%r8, %c[r8](%0) \n\t"
7623 "mov %%r9, %c[r9](%0) \n\t"
7624 "mov %%r10, %c[r10](%0) \n\t"
7625 "mov %%r11, %c[r11](%0) \n\t"
7626 "mov %%r12, %c[r12](%0) \n\t"
7627 "mov %%r13, %c[r13](%0) \n\t"
7628 "mov %%r14, %c[r14](%0) \n\t"
7629 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7630#endif
b188c81f
AK		 7631 "mov %%cr2, %%" _ASM_AX " \n\t"
7632 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7633
b188c81f 7634 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7635 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7636 ".pushsection .rodata \n\t"
7637 ".global vmx_return \n\t"
7638 "vmx_return: " _ASM_PTR " 2b \n\t"
7639 ".popsection"
e08aa78a 7640 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7641 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7642 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7643 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7644 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7645 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7646 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7647 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7648 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7649 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7650 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7651#ifdef CONFIG_X86_64
ad312c7c
ZX		 7652 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7653 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7654 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7655 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7656 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7657 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7658 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7659 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7660#endif
40712fae
AK		 7661 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7662 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7663 : "cc", "memory"
7664#ifdef CONFIG_X86_64
b188c81f 7665 , "rax", "rbx", "rdi", "rsi"
c2036300 7666 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7667#else
7668 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7669#endif
7670 );
6aa8b732 7671
2a7921b7
GN		 7672 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7673 if (debugctlmsr)
7674 update_debugctlmsr(debugctlmsr);
7675
aa67f609
AK		 7676#ifndef CONFIG_X86_64
7677 /*
7678 * The sysexit path does not restore ds/es, so we must set them to
7679 * a reasonable value ourselves.
7680 *
7681 * We can't defer this to vmx_load_host_state() since that function
7682 * may be executed in interrupt context, which saves and restore segments
7683 * around it, nullifying its effect.
7684 */
7685 loadsegment(ds, __USER_DS);
7686 loadsegment(es, __USER_DS);
7687#endif
7688
6de4f3ad 7689 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7690 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7691 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7692 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7693 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7694 vcpu->arch.regs_dirty = 0;
7695
1155f76a
AK		 7696 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7697
d462b819 7698 vmx->loaded_vmcs->launched = 1;
1b6269db 7699
51aa01d1 7700 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7701 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7702
e0b890d3
GN		 7703 /*
7704 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7705 * we did not inject a still-pending event to L1 now because of
7706 * nested_run_pending, we need to re-enable this bit.
7707 */
7708 if (vmx->nested.nested_run_pending)
7709 kvm_make_request(KVM_REQ_EVENT, vcpu);
7710
7711 vmx->nested.nested_run_pending = 0;
7712
51aa01d1
AK		 7713 vmx_complete_atomic_exit(vmx);
7714 vmx_recover_nmi_blocking(vmx);
cf393f75 7715 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7716}
7717
4fa7734c
PB		 7718static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7719{
7720 struct vcpu_vmx *vmx = to_vmx(vcpu);
7721 int cpu;
7722
7723 if (vmx->loaded_vmcs == &vmx->vmcs01)
7724 return;
7725
7726 cpu = get_cpu();
7727 vmx->loaded_vmcs = &vmx->vmcs01;
7728 vmx_vcpu_put(vcpu);
7729 vmx_vcpu_load(vcpu, cpu);
7730 vcpu->cpu = cpu;
7731 put_cpu();
7732}
7733
6aa8b732
AK		 7734static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7735{
fb3f0f51
RR		 7736 struct vcpu_vmx *vmx = to_vmx(vcpu);
7737
cdbecfc3 7738 free_vpid(vmx);
4fa7734c
PB		 7739 leave_guest_mode(vcpu);
7740 vmx_load_vmcs01(vcpu);
26a865f4 7741 free_nested(vmx);
4fa7734c 7742 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7743 kfree(vmx->guest_msrs);
7744 kvm_vcpu_uninit(vcpu);
a4770347 7745 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7746}
7747
fb3f0f51 7748static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7749{
fb3f0f51 7750 int err;
c16f862d 7751 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7752 int cpu;
6aa8b732 7753
a2fa3e9f 7754 if (!vmx)
fb3f0f51
RR		 7755 return ERR_PTR(-ENOMEM);
7756
2384d2b3
SY		 7757 allocate_vpid(vmx);
7758
fb3f0f51
RR		 7759 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7760 if (err)
7761 goto free_vcpu;
965b58a5 7762
a2fa3e9f 7763 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7764 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7765 > PAGE_SIZE);
0123be42 7766
be6d05cf 7767 err = -ENOMEM;
fb3f0f51 7768 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7769 goto uninit_vcpu;
7770 }
965b58a5 7771
d462b819
NHE		 7772 vmx->loaded_vmcs = &vmx->vmcs01;
7773 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7774 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7775 goto free_msrs;
d462b819
NHE		 7776 if (!vmm_exclusive)
7777 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7778 loaded_vmcs_init(vmx->loaded_vmcs);
7779 if (!vmm_exclusive)
7780 kvm_cpu_vmxoff();
a2fa3e9f 7781
15ad7146
AK		 7782 cpu = get_cpu();
7783 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7784 vmx->vcpu.cpu = cpu;
8b9cf98c 7785 err = vmx_vcpu_setup(vmx);
fb3f0f51 7786 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7787 put_cpu();
fb3f0f51
RR		 7788 if (err)
7789 goto free_vmcs;
a63cb560 7790 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7791 err = alloc_apic_access_page(kvm);
7792 if (err)
5e4a0b3c 7793 goto free_vmcs;
a63cb560 7794 }
fb3f0f51 7795
b927a3ce
SY		 7796 if (enable_ept) {
7797 if (!kvm->arch.ept_identity_map_addr)
7798 kvm->arch.ept_identity_map_addr =
7799 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7800 err = init_rmode_identity_map(kvm);
7801 if (err)
93ea5388 7802 goto free_vmcs;
b927a3ce 7803 }
b7ebfb05 7804
a9d30f33
NHE		 7805 vmx->nested.current_vmptr = -1ull;
7806 vmx->nested.current_vmcs12 = NULL;
7807
fb3f0f51
RR		 7808 return &vmx->vcpu;
7809
7810free_vmcs:
5f3fbc34 7811 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7812free_msrs:
fb3f0f51
RR		 7813 kfree(vmx->guest_msrs);
7814uninit_vcpu:
7815 kvm_vcpu_uninit(&vmx->vcpu);
7816free_vcpu:
cdbecfc3 7817 free_vpid(vmx);
a4770347 7818 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7819 return ERR_PTR(err);
6aa8b732
AK		 7820}
7821
002c7f7c
YS		 7822static void __init vmx_check_processor_compat(void *rtn)
7823{
7824 struct vmcs_config vmcs_conf;
7825
7826 *(int *)rtn = 0;
7827 if (setup_vmcs_config(&vmcs_conf) < 0)
7828 *(int *)rtn = -EIO;
7829 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7830 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7831 smp_processor_id());
7832 *(int *)rtn = -EIO;
7833 }
7834}
7835
67253af5
SY		 7836static int get_ept_level(void)
7837{
7838 return VMX_EPT_DEFAULT_GAW + 1;
7839}
7840
4b12f0de 7841static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7842{
4b12f0de
SY		 7843 u64 ret;
7844
522c68c4
SY		 7845 /* For VT-d and EPT combination
7846 * 1. MMIO: always map as UC
7847 * 2. EPT with VT-d:
7848 * a. VT-d without snooping control feature: can't guarantee the
7849 * result, try to trust guest.
7850 * b. VT-d with snooping control feature: snooping control feature of
7851 * VT-d engine can guarantee the cache correctness. Just set it
7852 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7853 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7854 * consistent with host MTRR
7855 */
4b12f0de
SY		 7856 if (is_mmio)
7857 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7858 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7859 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7860 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7861 else
522c68c4 7862 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7863 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7864
7865 return ret;
64d4d521
SY		 7866}
7867
17cc3935 7868static int vmx_get_lpage_level(void)
344f414f 7869{
878403b7
SY		 7870 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7871 return PT_DIRECTORY_LEVEL;
7872 else
7873 /* For shadow and EPT supported 1GB page */
7874 return PT_PDPE_LEVEL;
344f414f
JR		 7875}
7876
0e851880
SY		 7877static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7878{
4e47c7a6
SY		 7879 struct kvm_cpuid_entry2 *best;
7880 struct vcpu_vmx *vmx = to_vmx(vcpu);
7881 u32 exec_control;
7882
7883 vmx->rdtscp_enabled = false;
7884 if (vmx_rdtscp_supported()) {
7885 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7886 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7887 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7888 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7889 vmx->rdtscp_enabled = true;
7890 else {
7891 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7892 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7893 exec_control);
7894 }
7895 }
7896 }
ad756a16 7897
ad756a16
MJ		 7898 /* Exposing INVPCID only when PCID is exposed */
7899 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7900 if (vmx_invpcid_supported() &&
4f977045 7901 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7902 guest_cpuid_has_pcid(vcpu)) {
29282fde 7903 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7904 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7905 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7906 exec_control);
7907 } else {
29282fde
TI		 7908 if (cpu_has_secondary_exec_ctrls()) {
7909 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7910 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7911 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7912 exec_control);
7913 }
ad756a16 7914 if (best)
4f977045 7915 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7916 }
0e851880
SY		 7917}
7918
d4330ef2
JR		 7919static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7920{
7b8050f5
NHE		 7921 if (func == 1 && nested)
7922 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7923}
7924
25d92081
YZ		 7925static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7926 struct x86_exception *fault)
7927{
533558bc
JK		 7928 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7929 u32 exit_reason;
25d92081
YZ		 7930
7931 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7932 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7933 else
533558bc
JK		 7934 exit_reason = EXIT_REASON_EPT_VIOLATION;
7935 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7936 vmcs12->guest_physical_address = fault->address;
7937}
7938
155a97a3
NHE		 7939/* Callbacks for nested_ept_init_mmu_context: */
7940
7941static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7942{
7943 /* return the page table to be shadowed - in our case, EPT12 */
7944 return get_vmcs12(vcpu)->ept_pointer;
7945}
7946
8a3c1a33 7947static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7948{
8a3c1a33 7949 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7950 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7951
7952 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7953 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7954 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7955
7956 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7957}
7958
7959static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7960{
7961 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7962}
7963
feaf0c7d
GN		 7964static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7965 struct x86_exception *fault)
7966{
7967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7968
7969 WARN_ON(!is_guest_mode(vcpu));
7970
7971 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7972 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7973 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7974 vmcs_read32(VM_EXIT_INTR_INFO),
7975 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7976 else
7977 kvm_inject_page_fault(vcpu, fault);
7978}
7979
a2bcba50
WL		 7980static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7981 struct vmcs12 *vmcs12)
7982{
7983 struct vcpu_vmx *vmx = to_vmx(vcpu);
7984
7985 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 7986 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 7987 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 7988 return false;
7989
7990 /*
7991 * Translate L1 physical address to host physical
7992 * address for vmcs02. Keep the page pinned, so this
7993 * physical address remains valid. We keep a reference
7994 * to it so we can release it later.
7995 */
7996 if (vmx->nested.apic_access_page) /* shouldn't happen */
7997 nested_release_page(vmx->nested.apic_access_page);
7998 vmx->nested.apic_access_page =
7999 nested_get_page(vcpu, vmcs12->apic_access_addr);
8000 }
a7c0b07d
WL		 8001
8002 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8003 /* TODO: Also verify bits beyond physical address width are 0 */
8004 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8005 return false;
8006
8007 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8008 nested_release_page(vmx->nested.virtual_apic_page);
8009 vmx->nested.virtual_apic_page =
8010 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8011
8012 /*
8013 * Failing the vm entry is _not_ what the processor does
8014 * but it's basically the only possibility we have.
8015 * We could still enter the guest if CR8 load exits are
8016 * enabled, CR8 store exits are enabled, and virtualize APIC
8017 * access is disabled; in this case the processor would never
8018 * use the TPR shadow and we could simply clear the bit from
8019 * the execution control. But such a configuration is useless,
8020 * so let's keep the code simple.
8021 */
8022 if (!vmx->nested.virtual_apic_page)
8023 return false;
8024 }
8025
a2bcba50
WL		 8026 return true;
8027}
8028
f4124500
JK		 8029static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8030{
8031 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8032 struct vcpu_vmx *vmx = to_vmx(vcpu);
8033
8034 if (vcpu->arch.virtual_tsc_khz == 0)
8035 return;
8036
8037 /* Make sure short timeouts reliably trigger an immediate vmexit.
8038 * hrtimer_start does not guarantee this. */
8039 if (preemption_timeout <= 1) {
8040 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8041 return;
8042 }
8043
8044 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8045 preemption_timeout *= 1000000;
8046 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8047 hrtimer_start(&vmx->nested.preemption_timer,
8048 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8049}
8050
fe3ef05c
NHE		 8051/*
8052 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8053 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8054 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8055 * guest in a way that will both be appropriate to L1's requests, and our
8056 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8057 * function also has additional necessary side-effects, like setting various
8058 * vcpu->arch fields.
8059 */
8060static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8061{
8062 struct vcpu_vmx *vmx = to_vmx(vcpu);
8063 u32 exec_control;
8064
8065 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8066 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8067 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8068 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8069 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8070 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8071 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8072 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8073 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8074 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8075 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8076 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8077 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8078 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8079 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8080 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8081 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8082 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8083 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8084 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8085 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8086 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8087 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8088 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8089 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8090 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8091 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8092 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8093 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8094 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8095 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8096 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8097 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8098 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8099 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8100 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8101
2996fca0
JK		 8102 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8103 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8104 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8105 } else {
8106 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8107 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8108 }
fe3ef05c
NHE		 8109 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8110 vmcs12->vm_entry_intr_info_field);
8111 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8112 vmcs12->vm_entry_exception_error_code);
8113 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8114 vmcs12->vm_entry_instruction_len);
8115 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8116 vmcs12->guest_interruptibility_info);
fe3ef05c 8117 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8118 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8119 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8120 vmcs12->guest_pending_dbg_exceptions);
8121 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8122 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8123
8124 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8125
f4124500
JK		 8126 exec_control = vmcs12->pin_based_vm_exec_control;
8127 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8128 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8129 PIN_BASED_POSTED_INTR);
f4124500 8130 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8131
f4124500
JK		 8132 vmx->nested.preemption_timer_expired = false;
8133 if (nested_cpu_has_preemption_timer(vmcs12))
8134 vmx_start_preemption_timer(vcpu);
0238ea91 8135
fe3ef05c
NHE		 8136 /*
8137 * Whether page-faults are trapped is determined by a combination of
8138 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8139 * If enable_ept, L0 doesn't care about page faults and we should
8140 * set all of these to L1's desires. However, if !enable_ept, L0 does
8141 * care about (at least some) page faults, and because it is not easy
8142 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8143 * to exit on each and every L2 page fault. This is done by setting
8144 * MASK=MATCH=0 and (see below) EB.PF=1.
8145 * Note that below we don't need special code to set EB.PF beyond the
8146 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8147 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8148 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8149 *
8150 * A problem with this approach (when !enable_ept) is that L1 may be
8151 * injected with more page faults than it asked for. This could have
8152 * caused problems, but in practice existing hypervisors don't care.
8153 * To fix this, we will need to emulate the PFEC checking (on the L1
8154 * page tables), using walk_addr(), when injecting PFs to L1.
8155 */
8156 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8157 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8158 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8159 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8160
8161 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8162 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8163 if (!vmx->rdtscp_enabled)
8164 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8165 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8166 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8167 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8168 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8169 if (nested_cpu_has(vmcs12,
8170 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8171 exec_control |= vmcs12->secondary_vm_exec_control;
8172
8173 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8174 /*
8175 * If translation failed, no matter: This feature asks
8176 * to exit when accessing the given address, and if it
8177 * can never be accessed, this feature won't do
8178 * anything anyway.
8179 */
8180 if (!vmx->nested.apic_access_page)
8181 exec_control &=
8182 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8183 else
8184 vmcs_write64(APIC_ACCESS_ADDR,
8185 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8186 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8187 exec_control |=
8188 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8189 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8190 }
8191
8192 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8193 }
8194
8195
8196 /*
8197 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8198 * Some constant fields are set here by vmx_set_constant_host_state().
8199 * Other fields are different per CPU, and will be set later when
8200 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8201 */
a547c6db 8202 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8203
8204 /*
8205 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8206 * entry, but only if the current (host) sp changed from the value
8207 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8208 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8209 * here we just force the write to happen on entry.
8210 */
8211 vmx->host_rsp = 0;
8212
8213 exec_control = vmx_exec_control(vmx); /* L0's desires */
8214 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8215 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8216 exec_control &= ~CPU_BASED_TPR_SHADOW;
8217 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8218
8219 if (exec_control & CPU_BASED_TPR_SHADOW) {
8220 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8221 page_to_phys(vmx->nested.virtual_apic_page));
8222 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8223 }
8224
fe3ef05c
NHE		 8225 /*
8226 * Merging of IO and MSR bitmaps not currently supported.
8227 * Rather, exit every time.
8228 */
8229 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8230 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8231 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8232
8233 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8234
8235 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8236 * bitwise-or of what L1 wants to trap for L2, and what we want to
8237 * trap. Note that CR0.TS also needs updating - we do this later.
8238 */
8239 update_exception_bitmap(vcpu);
8240 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8241 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8242
8049d651
NHE		 8243 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8244 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8245 * bits are further modified by vmx_set_efer() below.
8246 */
f4124500 8247 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8248
8249 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8250 * emulated by vmx_set_efer(), below.
8251 */
2961e876 8252 vm_entry_controls_init(vmx,
8049d651
NHE		 8253 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8254 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8255 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8256
44811c02 8257 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8258 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8259 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8260 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8261 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8262
8263
8264 set_cr4_guest_host_mask(vmx);
8265
36be0b9d
PB		 8266 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8267 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8268
27fc51b2
NHE		 8269 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8270 vmcs_write64(TSC_OFFSET,
8271 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8272 else
8273 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8274
8275 if (enable_vpid) {
8276 /*
8277 * Trivially support vpid by letting L2s share their parent
8278 * L1's vpid. TODO: move to a more elaborate solution, giving
8279 * each L2 its own vpid and exposing the vpid feature to L1.
8280 */
8281 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8282 vmx_flush_tlb(vcpu);
8283 }
8284
155a97a3
NHE		 8285 if (nested_cpu_has_ept(vmcs12)) {
8286 kvm_mmu_unload(vcpu);
8287 nested_ept_init_mmu_context(vcpu);
8288 }
8289
fe3ef05c
NHE		 8290 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8291 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8292 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8293 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8294 else
8295 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8296 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8297 vmx_set_efer(vcpu, vcpu->arch.efer);
8298
8299 /*
8300 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8301 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8302 * The CR0_READ_SHADOW is what L2 should have expected to read given
8303 * the specifications by L1; It's not enough to take
8304 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8305 * have more bits than L1 expected.
8306 */
8307 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8308 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8309
8310 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8311 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8312
8313 /* shadow page tables on either EPT or shadow page tables */
8314 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8315 kvm_mmu_reset_context(vcpu);
8316
feaf0c7d
GN		 8317 if (!enable_ept)
8318 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8319
3633cfc3
NHE		 8320 /*
8321 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8322 */
8323 if (enable_ept) {
8324 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8325 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8326 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8327 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8328 }
8329
fe3ef05c
NHE		 8330 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8331 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8332}
8333
cd232ad0
NHE		 8334/*
8335 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8336 * for running an L2 nested guest.
8337 */
8338static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8339{
8340 struct vmcs12 *vmcs12;
8341 struct vcpu_vmx *vmx = to_vmx(vcpu);
8342 int cpu;
8343 struct loaded_vmcs *vmcs02;
384bb783 8344 bool ia32e;
cd232ad0
NHE		 8345
8346 if (!nested_vmx_check_permission(vcpu) ||
8347 !nested_vmx_check_vmcs12(vcpu))
8348 return 1;
8349
8350 skip_emulated_instruction(vcpu);
8351 vmcs12 = get_vmcs12(vcpu);
8352
012f83cb
AG		 8353 if (enable_shadow_vmcs)
8354 copy_shadow_to_vmcs12(vmx);
8355
7c177938
NHE		 8356 /*
8357 * The nested entry process starts with enforcing various prerequisites
8358 * on vmcs12 as required by the Intel SDM, and act appropriately when
8359 * they fail: As the SDM explains, some conditions should cause the
8360 * instruction to fail, while others will cause the instruction to seem
8361 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8362 * To speed up the normal (success) code path, we should avoid checking
8363 * for misconfigurations which will anyway be caught by the processor
8364 * when using the merged vmcs02.
8365 */
8366 if (vmcs12->launch_state == launch) {
8367 nested_vmx_failValid(vcpu,
8368 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8369 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8370 return 1;
8371 }
8372
6dfacadd
JK		 8373 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8374 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8375 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8376 return 1;
8377 }
8378
7c177938 8379 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8380 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8381 /*TODO: Also verify bits beyond physical address width are 0*/
8382 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8383 return 1;
8384 }
8385
a2bcba50 8386 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8387 /*TODO: Also verify bits beyond physical address width are 0*/
8388 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8389 return 1;
8390 }
8391
8392 if (vmcs12->vm_entry_msr_load_count > 0 ||
8393 vmcs12->vm_exit_msr_load_count > 0 ||
8394 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8395 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8396 __func__);
7c177938
NHE		 8397 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8398 return 1;
8399 }
8400
8401 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8402 nested_vmx_true_procbased_ctls_low,
8403 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8404 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8405 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8406 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8407 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8408 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8409 nested_vmx_true_exit_ctls_low,
8410 nested_vmx_exit_ctls_high) ||
7c177938 8411 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8412 nested_vmx_true_entry_ctls_low,
8413 nested_vmx_entry_ctls_high))
7c177938
NHE		 8414 {
8415 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8416 return 1;
8417 }
8418
8419 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8420 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8421 nested_vmx_failValid(vcpu,
8422 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8423 return 1;
8424 }
8425
92fbc7b1 8426 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8427 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8428 nested_vmx_entry_failure(vcpu, vmcs12,
8429 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8430 return 1;
8431 }
8432 if (vmcs12->vmcs_link_pointer != -1ull) {
8433 nested_vmx_entry_failure(vcpu, vmcs12,
8434 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8435 return 1;
8436 }
8437
384bb783 8438 /*
cb0c8cda 8439 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8440 * are performed on the field for the IA32_EFER MSR:
8441 * - Bits reserved in the IA32_EFER MSR must be 0.
8442 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8443 * the IA-32e mode guest VM-exit control. It must also be identical
8444 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8445 * CR0.PG) is 1.
8446 */
8447 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8448 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8449 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8450 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8451 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8452 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8453 nested_vmx_entry_failure(vcpu, vmcs12,
8454 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8455 return 1;
8456 }
8457 }
8458
8459 /*
8460 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8461 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8462 * the values of the LMA and LME bits in the field must each be that of
8463 * the host address-space size VM-exit control.
8464 */
8465 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8466 ia32e = (vmcs12->vm_exit_controls &
8467 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8468 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8469 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8470 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8471 nested_vmx_entry_failure(vcpu, vmcs12,
8472 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8473 return 1;
8474 }
8475 }
8476
7c177938
NHE		 8477 /*
8478 * We're finally done with prerequisite checking, and can start with
8479 * the nested entry.
8480 */
8481
cd232ad0
NHE		 8482 vmcs02 = nested_get_current_vmcs02(vmx);
8483 if (!vmcs02)
8484 return -ENOMEM;
8485
8486 enter_guest_mode(vcpu);
8487
8488 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8489
2996fca0
JK		 8490 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8491 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8492
cd232ad0
NHE		 8493 cpu = get_cpu();
8494 vmx->loaded_vmcs = vmcs02;
8495 vmx_vcpu_put(vcpu);
8496 vmx_vcpu_load(vcpu, cpu);
8497 vcpu->cpu = cpu;
8498 put_cpu();
8499
36c3cc42
JK		 8500 vmx_segment_cache_clear(vmx);
8501
cd232ad0
NHE		 8502 vmcs12->launch_state = 1;
8503
8504 prepare_vmcs02(vcpu, vmcs12);
8505
6dfacadd
JK		 8506 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8507 return kvm_emulate_halt(vcpu);
8508
7af40ad3
JK		 8509 vmx->nested.nested_run_pending = 1;
8510
cd232ad0
NHE		 8511 /*
8512 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8513 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8514 * returned as far as L1 is concerned. It will only return (and set
8515 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8516 */
8517 return 1;
8518}
8519
4704d0be
NHE		 8520/*
8521 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8522 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8523 * This function returns the new value we should put in vmcs12.guest_cr0.
8524 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8525 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8526 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8527 * didn't trap the bit, because if L1 did, so would L0).
8528 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8529 * been modified by L2, and L1 knows it. So just leave the old value of
8530 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8531 * isn't relevant, because if L0 traps this bit it can set it to anything.
8532 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8533 * changed these bits, and therefore they need to be updated, but L0
8534 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8535 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8536 */
8537static inline unsigned long
8538vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8539{
8540 return
8541 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8542 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8543 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8544 vcpu->arch.cr0_guest_owned_bits));
8545}
8546
8547static inline unsigned long
8548vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8549{
8550 return
8551 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8552 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8553 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8554 vcpu->arch.cr4_guest_owned_bits));
8555}
8556
5f3d5799
JK		 8557static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8558 struct vmcs12 *vmcs12)
8559{
8560 u32 idt_vectoring;
8561 unsigned int nr;
8562
851eb667 8563 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8564 nr = vcpu->arch.exception.nr;
8565 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8566
8567 if (kvm_exception_is_soft(nr)) {
8568 vmcs12->vm_exit_instruction_len =
8569 vcpu->arch.event_exit_inst_len;
8570 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8571 } else
8572 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8573
8574 if (vcpu->arch.exception.has_error_code) {
8575 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8576 vmcs12->idt_vectoring_error_code =
8577 vcpu->arch.exception.error_code;
8578 }
8579
8580 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8581 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8582 vmcs12->idt_vectoring_info_field =
8583 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8584 } else if (vcpu->arch.interrupt.pending) {
8585 nr = vcpu->arch.interrupt.nr;
8586 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8587
8588 if (vcpu->arch.interrupt.soft) {
8589 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8590 vmcs12->vm_entry_instruction_len =
8591 vcpu->arch.event_exit_inst_len;
8592 } else
8593 idt_vectoring |= INTR_TYPE_EXT_INTR;
8594
8595 vmcs12->idt_vectoring_info_field = idt_vectoring;
8596 }
8597}
8598
b6b8a145
JK		 8599static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8600{
8601 struct vcpu_vmx *vmx = to_vmx(vcpu);
8602
f4124500
JK		 8603 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8604 vmx->nested.preemption_timer_expired) {
8605 if (vmx->nested.nested_run_pending)
8606 return -EBUSY;
8607 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8608 return 0;
8609 }
8610
b6b8a145 8611 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8612 if (vmx->nested.nested_run_pending ||
8613 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8614 return -EBUSY;
8615 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8616 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8617 INTR_INFO_VALID_MASK, 0);
8618 /*
8619 * The NMI-triggered VM exit counts as injection:
8620 * clear this one and block further NMIs.
8621 */
8622 vcpu->arch.nmi_pending = 0;
8623 vmx_set_nmi_mask(vcpu, true);
8624 return 0;
8625 }
8626
8627 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8628 nested_exit_on_intr(vcpu)) {
8629 if (vmx->nested.nested_run_pending)
8630 return -EBUSY;
8631 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8632 }
8633
8634 return 0;
8635}
8636
f4124500
JK		 8637static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8638{
8639 ktime_t remaining =
8640 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8641 u64 value;
8642
8643 if (ktime_to_ns(remaining) <= 0)
8644 return 0;
8645
8646 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8647 do_div(value, 1000000);
8648 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8649}
8650
4704d0be
NHE		 8651/*
8652 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8653 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8654 * and this function updates it to reflect the changes to the guest state while
8655 * L2 was running (and perhaps made some exits which were handled directly by L0
8656 * without going back to L1), and to reflect the exit reason.
8657 * Note that we do not have to copy here all VMCS fields, just those that
8658 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8659 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8660 * which already writes to vmcs12 directly.
8661 */
533558bc
JK		 8662static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8663 u32 exit_reason, u32 exit_intr_info,
8664 unsigned long exit_qualification)
4704d0be
NHE		 8665{
8666 /* update guest state fields: */
8667 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8668 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8669
4704d0be
NHE		 8670 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8671 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8672 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8673
8674 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8675 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8676 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8677 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8678 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8679 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8680 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8681 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8682 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8683 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8684 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8685 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8686 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8687 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8688 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8689 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8690 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8691 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8692 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8693 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8694 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8695 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8696 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8697 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8698 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8699 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8700 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8701 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8702 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8703 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8704 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8705 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8706 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8707 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8708 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8709 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8710
4704d0be
NHE		 8711 vmcs12->guest_interruptibility_info =
8712 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8713 vmcs12->guest_pending_dbg_exceptions =
8714 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8715 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8716 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8717 else
8718 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8719
f4124500
JK		 8720 if (nested_cpu_has_preemption_timer(vmcs12)) {
8721 if (vmcs12->vm_exit_controls &
8722 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8723 vmcs12->vmx_preemption_timer_value =
8724 vmx_get_preemption_timer_value(vcpu);
8725 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8726 }
7854cbca 8727
3633cfc3
NHE		 8728 /*
8729 * In some cases (usually, nested EPT), L2 is allowed to change its
8730 * own CR3 without exiting. If it has changed it, we must keep it.
8731 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8732 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8733 *
8734 * Additionally, restore L2's PDPTR to vmcs12.
8735 */
8736 if (enable_ept) {
8737 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8738 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8739 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8740 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8741 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8742 }
8743
c18911a2
JK		 8744 vmcs12->vm_entry_controls =
8745 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8746 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8747
2996fca0
JK		 8748 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8749 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8750 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8751 }
8752
4704d0be
NHE		 8753 /* TODO: These cannot have changed unless we have MSR bitmaps and
8754 * the relevant bit asks not to trap the change */
b8c07d55 8755 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8756 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8757 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8758 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8759 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8760 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8761 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8762 if (vmx_mpx_supported())
8763 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8764
8765 /* update exit information fields: */
8766
533558bc
JK		 8767 vmcs12->vm_exit_reason = exit_reason;
8768 vmcs12->exit_qualification = exit_qualification;
4704d0be 8769
533558bc 8770 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8771 if ((vmcs12->vm_exit_intr_info &
8772 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8773 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8774 vmcs12->vm_exit_intr_error_code =
8775 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8776 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8777 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8778 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8779
5f3d5799
JK		 8780 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8781 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8782 * instead of reading the real value. */
4704d0be 8783 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8784
8785 /*
8786 * Transfer the event that L0 or L1 may wanted to inject into
8787 * L2 to IDT_VECTORING_INFO_FIELD.
8788 */
8789 vmcs12_save_pending_event(vcpu, vmcs12);
8790 }
8791
8792 /*
8793 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8794 * preserved above and would only end up incorrectly in L1.
8795 */
8796 vcpu->arch.nmi_injected = false;
8797 kvm_clear_exception_queue(vcpu);
8798 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8799}
8800
8801/*
8802 * A part of what we need to when the nested L2 guest exits and we want to
8803 * run its L1 parent, is to reset L1's guest state to the host state specified
8804 * in vmcs12.
8805 * This function is to be called not only on normal nested exit, but also on
8806 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8807 * Failures During or After Loading Guest State").
8808 * This function should be called when the active VMCS is L1's (vmcs01).
8809 */
733568f9
JK		 8810static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8811 struct vmcs12 *vmcs12)
4704d0be 8812{
21feb4eb
ACL		 8813 struct kvm_segment seg;
8814
4704d0be
NHE		 8815 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8816 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8817 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8818 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8819 else
8820 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8821 vmx_set_efer(vcpu, vcpu->arch.efer);
8822
8823 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8824 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8825 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8826 /*
8827 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8828 * actually changed, because it depends on the current state of
8829 * fpu_active (which may have changed).
8830 * Note that vmx_set_cr0 refers to efer set above.
8831 */
9e3e4dbf 8832 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8833 /*
8834 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8835 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8836 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8837 */
8838 update_exception_bitmap(vcpu);
8839 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8840 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8841
8842 /*
8843 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8844 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8845 */
8846 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8847 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8848
29bf08f1 8849 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8850
4704d0be
NHE		 8851 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8852 kvm_mmu_reset_context(vcpu);
8853
feaf0c7d
GN		 8854 if (!enable_ept)
8855 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8856
4704d0be
NHE		 8857 if (enable_vpid) {
8858 /*
8859 * Trivially support vpid by letting L2s share their parent
8860 * L1's vpid. TODO: move to a more elaborate solution, giving
8861 * each L2 its own vpid and exposing the vpid feature to L1.
8862 */
8863 vmx_flush_tlb(vcpu);
8864 }
8865
8866
8867 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8868 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8869 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8870 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8871 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8872
36be0b9d
PB		 8873 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8874 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8875 vmcs_write64(GUEST_BNDCFGS, 0);
8876
44811c02 8877 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8878 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8879 vcpu->arch.pat = vmcs12->host_ia32_pat;
8880 }
4704d0be
NHE		 8881 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8882 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8883 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8884
21feb4eb
ACL		 8885 /* Set L1 segment info according to Intel SDM
8886 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8887 seg = (struct kvm_segment) {
8888 .base = 0,
8889 .limit = 0xFFFFFFFF,
8890 .selector = vmcs12->host_cs_selector,
8891 .type = 11,
8892 .present = 1,
8893 .s = 1,
8894 .g = 1
8895 };
8896 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8897 seg.l = 1;
8898 else
8899 seg.db = 1;
8900 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8901 seg = (struct kvm_segment) {
8902 .base = 0,
8903 .limit = 0xFFFFFFFF,
8904 .type = 3,
8905 .present = 1,
8906 .s = 1,
8907 .db = 1,
8908 .g = 1
8909 };
8910 seg.selector = vmcs12->host_ds_selector;
8911 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8912 seg.selector = vmcs12->host_es_selector;
8913 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8914 seg.selector = vmcs12->host_ss_selector;
8915 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8916 seg.selector = vmcs12->host_fs_selector;
8917 seg.base = vmcs12->host_fs_base;
8918 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8919 seg.selector = vmcs12->host_gs_selector;
8920 seg.base = vmcs12->host_gs_base;
8921 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8922 seg = (struct kvm_segment) {
205befd9 8923 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8924 .limit = 0x67,
8925 .selector = vmcs12->host_tr_selector,
8926 .type = 11,
8927 .present = 1
8928 };
8929 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8930
503cd0c5
JK		 8931 kvm_set_dr(vcpu, 7, 0x400);
8932 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8933}
8934
8935/*
8936 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8937 * and modify vmcs12 to make it see what it would expect to see there if
8938 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8939 */
533558bc
JK		 8940static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8941 u32 exit_intr_info,
8942 unsigned long exit_qualification)
4704d0be
NHE		 8943{
8944 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8945 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8946
5f3d5799
JK		 8947 /* trying to cancel vmlaunch/vmresume is a bug */
8948 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8949
4704d0be 8950 leave_guest_mode(vcpu);
533558bc
JK		 8951 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8952 exit_qualification);
4704d0be 8953
f3380ca5
WL		 8954 vmx_load_vmcs01(vcpu);
8955
77b0f5d6
BD		 8956 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8957 && nested_exit_intr_ack_set(vcpu)) {
8958 int irq = kvm_cpu_get_interrupt(vcpu);
8959 WARN_ON(irq < 0);
8960 vmcs12->vm_exit_intr_info = irq |
8961 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8962 }
8963
542060ea
JK		 8964 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8965 vmcs12->exit_qualification,
8966 vmcs12->idt_vectoring_info_field,
8967 vmcs12->vm_exit_intr_info,
8968 vmcs12->vm_exit_intr_error_code,
8969 KVM_ISA_VMX);
4704d0be 8970
2961e876
GN		 8971 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8972 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8973 vmx_segment_cache_clear(vmx);
8974
4704d0be
NHE		 8975 /* if no vmcs02 cache requested, remove the one we used */
8976 if (VMCS02_POOL_SIZE == 0)
8977 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8978
8979 load_vmcs12_host_state(vcpu, vmcs12);
8980
27fc51b2 8981 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8982 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8983
8984 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8985 vmx->host_rsp = 0;
8986
8987 /* Unpin physical memory we referred to in vmcs02 */
8988 if (vmx->nested.apic_access_page) {
8989 nested_release_page(vmx->nested.apic_access_page);
48d89b92 8990 vmx->nested.apic_access_page = NULL;
4704d0be 8991 }
a7c0b07d
WL		 8992 if (vmx->nested.virtual_apic_page) {
8993 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 8994 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 8995 }
4704d0be 8996
38b99173
TC		 8997 /*
8998 * We are now running in L2, mmu_notifier will force to reload the
8999 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9000 */
9001 kvm_vcpu_reload_apic_access_page(vcpu);
9002
4704d0be
NHE		 9003 /*
9004 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9005 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9006 * success or failure flag accordingly.
9007 */
9008 if (unlikely(vmx->fail)) {
9009 vmx->fail = 0;
9010 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9011 } else
9012 nested_vmx_succeed(vcpu);
012f83cb
AG		 9013 if (enable_shadow_vmcs)
9014 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9015
9016 /* in case we halted in L2 */
9017 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9018}
9019
42124925
JK		 9020/*
9021 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9022 */
9023static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9024{
9025 if (is_guest_mode(vcpu))
533558bc 9026 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9027 free_nested(to_vmx(vcpu));
9028}
9029
7c177938
NHE		 9030/*
9031 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9032 * 23.7 "VM-entry failures during or after loading guest state" (this also
9033 * lists the acceptable exit-reason and exit-qualification parameters).
9034 * It should only be called before L2 actually succeeded to run, and when
9035 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9036 */
9037static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9038 struct vmcs12 *vmcs12,
9039 u32 reason, unsigned long qualification)
9040{
9041 load_vmcs12_host_state(vcpu, vmcs12);
9042 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9043 vmcs12->exit_qualification = qualification;
9044 nested_vmx_succeed(vcpu);
012f83cb
AG		 9045 if (enable_shadow_vmcs)
9046 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9047}
9048
8a76d7f2
JR		 9049static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9050 struct x86_instruction_info *info,
9051 enum x86_intercept_stage stage)
9052{
9053 return X86EMUL_CONTINUE;
9054}
9055
48d89b92 9056static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9057{
b4a2d31d
RK		 9058 if (ple_gap)
9059 shrink_ple_window(vcpu);
ae97a3b8
RK		 9060}
9061
cbdd1bea 9062static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9063 .cpu_has_kvm_support = cpu_has_kvm_support,
9064 .disabled_by_bios = vmx_disabled_by_bios,
9065 .hardware_setup = hardware_setup,
9066 .hardware_unsetup = hardware_unsetup,
002c7f7c 9067 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9068 .hardware_enable = hardware_enable,
9069 .hardware_disable = hardware_disable,
04547156 9070 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9071
9072 .vcpu_create = vmx_create_vcpu,
9073 .vcpu_free = vmx_free_vcpu,
04d2cc77 9074 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9075
04d2cc77 9076 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9077 .vcpu_load = vmx_vcpu_load,
9078 .vcpu_put = vmx_vcpu_put,
9079
c8639010 9080 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9081 .get_msr = vmx_get_msr,
9082 .set_msr = vmx_set_msr,
9083 .get_segment_base = vmx_get_segment_base,
9084 .get_segment = vmx_get_segment,
9085 .set_segment = vmx_set_segment,
2e4d2653 9086 .get_cpl = vmx_get_cpl,
6aa8b732 9087 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9088 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9089 .decache_cr3 = vmx_decache_cr3,
25c4c276 9090 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9091 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9092 .set_cr3 = vmx_set_cr3,
9093 .set_cr4 = vmx_set_cr4,
6aa8b732 9094 .set_efer = vmx_set_efer,
6aa8b732
AK		 9095 .get_idt = vmx_get_idt,
9096 .set_idt = vmx_set_idt,
9097 .get_gdt = vmx_get_gdt,
9098 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9099 .get_dr6 = vmx_get_dr6,
9100 .set_dr6 = vmx_set_dr6,
020df079 9101 .set_dr7 = vmx_set_dr7,
81908bf4 9102 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9103 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9104 .get_rflags = vmx_get_rflags,
9105 .set_rflags = vmx_set_rflags,
02daab21 9106 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9107
9108 .tlb_flush = vmx_flush_tlb,
6aa8b732 9109
6aa8b732 9110 .run = vmx_vcpu_run,
6062d012 9111 .handle_exit = vmx_handle_exit,
6aa8b732 9112 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9113 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9114 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9115 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9116 .set_irq = vmx_inject_irq,
95ba8273 9117 .set_nmi = vmx_inject_nmi,
298101da 9118 .queue_exception = vmx_queue_exception,
b463a6f7 9119 .cancel_injection = vmx_cancel_injection,
78646121 9120 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9121 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9122 .get_nmi_mask = vmx_get_nmi_mask,
9123 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9124 .enable_nmi_window = enable_nmi_window,
9125 .enable_irq_window = enable_irq_window,
9126 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9127 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9128 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9129 .vm_has_apicv = vmx_vm_has_apicv,
9130 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9131 .hwapic_irr_update = vmx_hwapic_irr_update,
9132 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9133 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9134 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9135
cbc94022 9136 .set_tss_addr = vmx_set_tss_addr,
67253af5 9137 .get_tdp_level = get_ept_level,
4b12f0de 9138 .get_mt_mask = vmx_get_mt_mask,
229456fc 9139
586f9607 9140 .get_exit_info = vmx_get_exit_info,
586f9607 9141
17cc3935 9142 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9143
9144 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9145
9146 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9147 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9148
9149 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9150
9151 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9152
4051b188 9153 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9154 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9155 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9156 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9157 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9158 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9159
9160 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9161
9162 .check_intercept = vmx_check_intercept,
a547c6db 9163 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9164 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9165
9166 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9167
9168 .sched_in = vmx_sched_in,
6aa8b732
AK		 9169};
9170
9171static int __init vmx_init(void)
9172{
8d14695f 9173 int r, i, msr;
26bb0981
AK		 9174
9175 rdmsrl_safe(MSR_EFER, &host_efer);
9176
03916db9 9177 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 9178 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 9179
3e7c73e9 9180 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 9181 if (!vmx_io_bitmap_a)
9182 return -ENOMEM;
9183
2106a548
GC		 9184 r = -ENOMEM;
9185
3e7c73e9 9186 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9187 if (!vmx_io_bitmap_b)
fdef3ad1 9188 goto out;
fdef3ad1 9189
5897297b 9190 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9191 if (!vmx_msr_bitmap_legacy)
25c5f225 9192 goto out1;
2106a548 9193
8d14695f
YZ		 9194 vmx_msr_bitmap_legacy_x2apic =
9195 (unsigned long *)__get_free_page(GFP_KERNEL);
9196 if (!vmx_msr_bitmap_legacy_x2apic)
9197 goto out2;
25c5f225 9198
5897297b 9199 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9200 if (!vmx_msr_bitmap_longmode)
8d14695f 9201 goto out3;
2106a548 9202
8d14695f
YZ		 9203 vmx_msr_bitmap_longmode_x2apic =
9204 (unsigned long *)__get_free_page(GFP_KERNEL);
9205 if (!vmx_msr_bitmap_longmode_x2apic)
9206 goto out4;
4607c2d7
AG		 9207 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9208 if (!vmx_vmread_bitmap)
9209 goto out5;
9210
9211 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9212 if (!vmx_vmwrite_bitmap)
9213 goto out6;
9214
9215 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9216 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9217
fdef3ad1
HQ		 9218 /*
9219 * Allow direct access to the PC debug port (it is often used for I/O
9220 * delays, but the vmexits simply slow things down).
9221 */
3e7c73e9
AK		 9222 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9223 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9224
3e7c73e9 9225 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9226
5897297b
AK		 9227 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9228 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9229
2384d2b3
SY		 9230 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9231
0ee75bea
AK		 9232 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9233 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9234 if (r)
4607c2d7 9235 goto out7;
25c5f225 9236
8f536b76
ZY		 9237#ifdef CONFIG_KEXEC
9238 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9239 crash_vmclear_local_loaded_vmcss);
9240#endif
9241
5897297b
AK		 9242 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9243 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9244 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9245 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9246 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9247 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9248 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9249
8d14695f
YZ		 9250 memcpy(vmx_msr_bitmap_legacy_x2apic,
9251 vmx_msr_bitmap_legacy, PAGE_SIZE);
9252 memcpy(vmx_msr_bitmap_longmode_x2apic,
9253 vmx_msr_bitmap_longmode, PAGE_SIZE);
9254
01e439be 9255 if (enable_apicv) {
8d14695f
YZ		 9256 for (msr = 0x800; msr <= 0x8ff; msr++)
9257 vmx_disable_intercept_msr_read_x2apic(msr);
9258
9259 /* According SDM, in x2apic mode, the whole id reg is used.
9260 * But in KVM, it only use the highest eight bits. Need to
9261 * intercept it */
9262 vmx_enable_intercept_msr_read_x2apic(0x802);
9263 /* TMCCT */
9264 vmx_enable_intercept_msr_read_x2apic(0x839);
9265 /* TPR */
9266 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9267 /* EOI */
9268 vmx_disable_intercept_msr_write_x2apic(0x80b);
9269 /* SELF-IPI */
9270 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9271 }
fdef3ad1 9272
089d034e 9273 if (enable_ept) {
3f6d8c8a
XH		 9274 kvm_mmu_set_mask_ptes(0ull,
9275 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9276 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9277 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9278 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9279 kvm_enable_tdp();
9280 } else
9281 kvm_disable_tdp();
1439442c 9282
b4a2d31d
RK		 9283 update_ple_window_actual_max();
9284
fdef3ad1
HQ		 9285 return 0;
9286
4607c2d7
AG		 9287out7:
9288 free_page((unsigned long)vmx_vmwrite_bitmap);
9289out6:
9290 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9291out5:
9292 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9293out4:
5897297b 9294 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9295out3:
9296 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9297out2:
5897297b 9298 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9299out1:
3e7c73e9 9300 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9301out:
3e7c73e9 9302 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9303 return r;
6aa8b732
AK		 9304}
9305
9306static void __exit vmx_exit(void)
9307{
8d14695f
YZ		 9308 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9309 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9310 free_page((unsigned long)vmx_msr_bitmap_legacy);
9311 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9312 free_page((unsigned long)vmx_io_bitmap_b);
9313 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9314 free_page((unsigned long)vmx_vmwrite_bitmap);
9315 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9316
8f536b76 9317#ifdef CONFIG_KEXEC
3b63a43f 9318 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9319 synchronize_rcu();
9320#endif
9321
cb498ea2 9322 kvm_exit();
6aa8b732
AK		 9323}
9324
9325module_init(vmx_init)
9326module_exit(vmx_exit)
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