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KVM: x86: Warn if guest virtual address space is not 48-bits
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d77c26fc 475 } host_state;
9c8cba37 476 struct {
7ffd92c5 477 int vm86_active;
78ac8b47 478 ulong save_rflags;
f5f7b2fe
AK		 479 struct kvm_segment segs[8];
480 } rmode;
481 struct {
482 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 483 struct kvm_save_segment {
484 u16 selector;
485 unsigned long base;
486 u32 limit;
487 u32 ar;
f5f7b2fe 488 } seg[8];
2fb92db1 489 } segment_cache;
2384d2b3 490 int vpid;
04fa4d32 491 bool emulation_required;
3b86cd99
JK		 492
493 /* Support for vnmi-less CPUs */
494 int soft_vnmi_blocked;
495 ktime_t entry_time;
496 s64 vnmi_blocked_time;
a0861c02 497 u32 exit_reason;
4e47c7a6
SY		 498
499 bool rdtscp_enabled;
ec378aee 500
01e439be
YZ		 501 /* Posted interrupt descriptor */
502 struct pi_desc pi_desc;
503
ec378aee
NHE		 504 /* Support for a guest hypervisor (nested VMX) */
505 struct nested_vmx nested;
a7653ecd
RK		 506
507 /* Dynamic PLE window. */
508 int ple_window;
509 bool ple_window_dirty;
a2fa3e9f
GH		 510};
511
2fb92db1
AK		 512enum segment_cache_field {
513 SEG_FIELD_SEL = 0,
514 SEG_FIELD_BASE = 1,
515 SEG_FIELD_LIMIT = 2,
516 SEG_FIELD_AR = 3,
517
518 SEG_FIELD_NR = 4
519};
520
a2fa3e9f
GH		 521static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
522{
fb3f0f51 523 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 524}
525
22bd0358
NHE		 526#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
527#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
528#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
529 [number##_HIGH] = VMCS12_OFFSET(name)+4
530
4607c2d7 531
fe2b201b 532static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 533 /*
534 * We do NOT shadow fields that are modified when L0
535 * traps and emulates any vmx instruction (e.g. VMPTRLD,
536 * VMXON...) executed by L1.
537 * For example, VM_INSTRUCTION_ERROR is read
538 * by L1 if a vmx instruction fails (part of the error path).
539 * Note the code assumes this logic. If for some reason
540 * we start shadowing these fields then we need to
541 * force a shadow sync when L0 emulates vmx instructions
542 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
543 * by nested_vmx_failValid)
544 */
545 VM_EXIT_REASON,
546 VM_EXIT_INTR_INFO,
547 VM_EXIT_INSTRUCTION_LEN,
548 IDT_VECTORING_INFO_FIELD,
549 IDT_VECTORING_ERROR_CODE,
550 VM_EXIT_INTR_ERROR_CODE,
551 EXIT_QUALIFICATION,
552 GUEST_LINEAR_ADDRESS,
553 GUEST_PHYSICAL_ADDRESS
554};
fe2b201b 555static int max_shadow_read_only_fields =
4607c2d7
AG		 556 ARRAY_SIZE(shadow_read_only_fields);
557
fe2b201b 558static unsigned long shadow_read_write_fields[] = {
a7c0b07d 559 TPR_THRESHOLD,
4607c2d7
AG		 560 GUEST_RIP,
561 GUEST_RSP,
562 GUEST_CR0,
563 GUEST_CR3,
564 GUEST_CR4,
565 GUEST_INTERRUPTIBILITY_INFO,
566 GUEST_RFLAGS,
567 GUEST_CS_SELECTOR,
568 GUEST_CS_AR_BYTES,
569 GUEST_CS_LIMIT,
570 GUEST_CS_BASE,
571 GUEST_ES_BASE,
36be0b9d 572 GUEST_BNDCFGS,
4607c2d7
AG		 573 CR0_GUEST_HOST_MASK,
574 CR0_READ_SHADOW,
575 CR4_READ_SHADOW,
576 TSC_OFFSET,
577 EXCEPTION_BITMAP,
578 CPU_BASED_VM_EXEC_CONTROL,
579 VM_ENTRY_EXCEPTION_ERROR_CODE,
580 VM_ENTRY_INTR_INFO_FIELD,
581 VM_ENTRY_INSTRUCTION_LEN,
582 VM_ENTRY_EXCEPTION_ERROR_CODE,
583 HOST_FS_BASE,
584 HOST_GS_BASE,
585 HOST_FS_SELECTOR,
586 HOST_GS_SELECTOR
587};
fe2b201b 588static int max_shadow_read_write_fields =
4607c2d7
AG		 589 ARRAY_SIZE(shadow_read_write_fields);
590
772e0318 591static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 592 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
593 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
594 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
595 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
596 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
597 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
598 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
599 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
600 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
601 FIELD(HOST_ES_SELECTOR, host_es_selector),
602 FIELD(HOST_CS_SELECTOR, host_cs_selector),
603 FIELD(HOST_SS_SELECTOR, host_ss_selector),
604 FIELD(HOST_DS_SELECTOR, host_ds_selector),
605 FIELD(HOST_FS_SELECTOR, host_fs_selector),
606 FIELD(HOST_GS_SELECTOR, host_gs_selector),
607 FIELD(HOST_TR_SELECTOR, host_tr_selector),
608 FIELD64(IO_BITMAP_A, io_bitmap_a),
609 FIELD64(IO_BITMAP_B, io_bitmap_b),
610 FIELD64(MSR_BITMAP, msr_bitmap),
611 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
612 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
613 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
614 FIELD64(TSC_OFFSET, tsc_offset),
615 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
616 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
617 FIELD64(EPT_POINTER, ept_pointer),
618 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
619 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
620 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
621 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
622 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
623 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
624 FIELD64(GUEST_PDPTR0, guest_pdptr0),
625 FIELD64(GUEST_PDPTR1, guest_pdptr1),
626 FIELD64(GUEST_PDPTR2, guest_pdptr2),
627 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 628 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 629 FIELD64(HOST_IA32_PAT, host_ia32_pat),
630 FIELD64(HOST_IA32_EFER, host_ia32_efer),
631 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
632 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
633 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
634 FIELD(EXCEPTION_BITMAP, exception_bitmap),
635 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
636 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
637 FIELD(CR3_TARGET_COUNT, cr3_target_count),
638 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
639 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
640 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
641 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
642 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
643 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
644 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
645 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
646 FIELD(TPR_THRESHOLD, tpr_threshold),
647 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
648 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
649 FIELD(VM_EXIT_REASON, vm_exit_reason),
650 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
651 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
652 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
653 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
654 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
655 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
656 FIELD(GUEST_ES_LIMIT, guest_es_limit),
657 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
658 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
659 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
660 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
661 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
662 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
663 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
664 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
665 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
666 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
667 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
668 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
669 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
670 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
671 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
672 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
673 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
674 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
675 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
676 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
677 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 678 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 679 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
680 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
681 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
682 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
683 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
684 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
685 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
686 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
687 FIELD(EXIT_QUALIFICATION, exit_qualification),
688 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
689 FIELD(GUEST_CR0, guest_cr0),
690 FIELD(GUEST_CR3, guest_cr3),
691 FIELD(GUEST_CR4, guest_cr4),
692 FIELD(GUEST_ES_BASE, guest_es_base),
693 FIELD(GUEST_CS_BASE, guest_cs_base),
694 FIELD(GUEST_SS_BASE, guest_ss_base),
695 FIELD(GUEST_DS_BASE, guest_ds_base),
696 FIELD(GUEST_FS_BASE, guest_fs_base),
697 FIELD(GUEST_GS_BASE, guest_gs_base),
698 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
699 FIELD(GUEST_TR_BASE, guest_tr_base),
700 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
701 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
702 FIELD(GUEST_DR7, guest_dr7),
703 FIELD(GUEST_RSP, guest_rsp),
704 FIELD(GUEST_RIP, guest_rip),
705 FIELD(GUEST_RFLAGS, guest_rflags),
706 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
707 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
708 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
709 FIELD(HOST_CR0, host_cr0),
710 FIELD(HOST_CR3, host_cr3),
711 FIELD(HOST_CR4, host_cr4),
712 FIELD(HOST_FS_BASE, host_fs_base),
713 FIELD(HOST_GS_BASE, host_gs_base),
714 FIELD(HOST_TR_BASE, host_tr_base),
715 FIELD(HOST_GDTR_BASE, host_gdtr_base),
716 FIELD(HOST_IDTR_BASE, host_idtr_base),
717 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
718 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
719 FIELD(HOST_RSP, host_rsp),
720 FIELD(HOST_RIP, host_rip),
721};
722static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
726 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
727 return -1;
728 return vmcs_field_to_offset_table[field];
729}
730
a9d30f33
NHE		 731static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
732{
733 return to_vmx(vcpu)->nested.current_vmcs12;
734}
735
736static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
737{
738 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 739 if (is_error_page(page))
a9d30f33 740 return NULL;
32cad84f 741
a9d30f33
NHE		 742 return page;
743}
744
745static void nested_release_page(struct page *page)
746{
747 kvm_release_page_dirty(page);
748}
749
750static void nested_release_page_clean(struct page *page)
751{
752 kvm_release_page_clean(page);
753}
754
bfd0a56b 755static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 756static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 757static void kvm_cpu_vmxon(u64 addr);
758static void kvm_cpu_vmxoff(void);
93c4adc7 759static bool vmx_mpx_supported(void);
776e58ea 760static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 761static void vmx_set_segment(struct kvm_vcpu *vcpu,
762 struct kvm_segment *var, int seg);
763static void vmx_get_segment(struct kvm_vcpu *vcpu,
764 struct kvm_segment *var, int seg);
d99e4152
GN		 765static bool guest_state_valid(struct kvm_vcpu *vcpu);
766static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 767static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 768static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 769static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 770static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 771
6aa8b732
AK		 772static DEFINE_PER_CPU(struct vmcs *, vmxarea);
773static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 774/*
775 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
776 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
777 */
778static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 779static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 780
3e7c73e9
AK		 781static unsigned long *vmx_io_bitmap_a;
782static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 783static unsigned long *vmx_msr_bitmap_legacy;
784static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 785static unsigned long *vmx_msr_bitmap_legacy_x2apic;
786static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 787static unsigned long *vmx_vmread_bitmap;
788static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 789
110312c8 790static bool cpu_has_load_ia32_efer;
8bf00a52 791static bool cpu_has_load_perf_global_ctrl;
110312c8 792
2384d2b3
SY		 793static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
794static DEFINE_SPINLOCK(vmx_vpid_lock);
795
1c3d14fe 796static struct vmcs_config {
6aa8b732
AK		 797 int size;
798 int order;
799 u32 revision_id;
1c3d14fe
YS		 800 u32 pin_based_exec_ctrl;
801 u32 cpu_based_exec_ctrl;
f78e0e2e 802 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 803 u32 vmexit_ctrl;
804 u32 vmentry_ctrl;
805} vmcs_config;
6aa8b732 806
efff9e53 807static struct vmx_capability {
d56f546d
SY		 808 u32 ept;
809 u32 vpid;
810} vmx_capability;
811
6aa8b732
AK		 812#define VMX_SEGMENT_FIELD(seg) \
813 [VCPU_SREG_##seg] = { \
814 .selector = GUEST_##seg##_SELECTOR, \
815 .base = GUEST_##seg##_BASE, \
816 .limit = GUEST_##seg##_LIMIT, \
817 .ar_bytes = GUEST_##seg##_AR_BYTES, \
818 }
819
772e0318 820static const struct kvm_vmx_segment_field {
6aa8b732
AK		 821 unsigned selector;
822 unsigned base;
823 unsigned limit;
824 unsigned ar_bytes;
825} kvm_vmx_segment_fields[] = {
826 VMX_SEGMENT_FIELD(CS),
827 VMX_SEGMENT_FIELD(DS),
828 VMX_SEGMENT_FIELD(ES),
829 VMX_SEGMENT_FIELD(FS),
830 VMX_SEGMENT_FIELD(GS),
831 VMX_SEGMENT_FIELD(SS),
832 VMX_SEGMENT_FIELD(TR),
833 VMX_SEGMENT_FIELD(LDTR),
834};
835
26bb0981
AK		 836static u64 host_efer;
837
6de4f3ad
AK		 838static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
839
4d56c8a7 840/*
8c06585d 841 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 842 * away by decrementing the array size.
843 */
6aa8b732 844static const u32 vmx_msr_index[] = {
05b3e0c2 845#ifdef CONFIG_X86_64
44ea2b17 846 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 847#endif
8c06585d 848 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 849};
6aa8b732 850
31299944 851static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 852{
853 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
854 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 855 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 856}
857
31299944 858static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 859{
860 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
861 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 862 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 863}
864
31299944 865static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 866{
867 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
868 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 869 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 870}
871
31299944 872static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 873{
874 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
875 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
876}
877
31299944 878static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 879{
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
881 INTR_INFO_VALID_MASK)) ==
882 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
883}
884
31299944 885static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 886{
04547156 887 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 888}
889
31299944 890static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 891{
04547156 892 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 893}
894
31299944 895static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 896{
04547156 897 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 898}
899
31299944 900static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 901{
04547156
SY		 902 return vmcs_config.cpu_based_exec_ctrl &
903 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 904}
905
774ead3a 906static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 907{
04547156
SY		 908 return vmcs_config.cpu_based_2nd_exec_ctrl &
909 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
910}
911
8d14695f
YZ		 912static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
913{
914 return vmcs_config.cpu_based_2nd_exec_ctrl &
915 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
916}
917
83d4c286
YZ		 918static inline bool cpu_has_vmx_apic_register_virt(void)
919{
920 return vmcs_config.cpu_based_2nd_exec_ctrl &
921 SECONDARY_EXEC_APIC_REGISTER_VIRT;
922}
923
c7c9c56c
YZ		 924static inline bool cpu_has_vmx_virtual_intr_delivery(void)
925{
926 return vmcs_config.cpu_based_2nd_exec_ctrl &
927 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
928}
929
01e439be
YZ		 930static inline bool cpu_has_vmx_posted_intr(void)
931{
932 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
933}
934
935static inline bool cpu_has_vmx_apicv(void)
936{
937 return cpu_has_vmx_apic_register_virt() &&
938 cpu_has_vmx_virtual_intr_delivery() &&
939 cpu_has_vmx_posted_intr();
940}
941
04547156
SY		 942static inline bool cpu_has_vmx_flexpriority(void)
943{
944 return cpu_has_vmx_tpr_shadow() &&
945 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 946}
947
e799794e
MT		 948static inline bool cpu_has_vmx_ept_execute_only(void)
949{
31299944 950 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 951}
952
953static inline bool cpu_has_vmx_eptp_uncacheable(void)
954{
31299944 955 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 956}
957
958static inline bool cpu_has_vmx_eptp_writeback(void)
959{
31299944 960 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 961}
962
963static inline bool cpu_has_vmx_ept_2m_page(void)
964{
31299944 965 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 966}
967
878403b7
SY		 968static inline bool cpu_has_vmx_ept_1g_page(void)
969{
31299944 970 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 971}
972
4bc9b982
SY		 973static inline bool cpu_has_vmx_ept_4levels(void)
974{
975 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
976}
977
83c3a331
XH		 978static inline bool cpu_has_vmx_ept_ad_bits(void)
979{
980 return vmx_capability.ept & VMX_EPT_AD_BIT;
981}
982
31299944 983static inline bool cpu_has_vmx_invept_context(void)
d56f546d 984{
31299944 985 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 986}
987
31299944 988static inline bool cpu_has_vmx_invept_global(void)
d56f546d 989{
31299944 990 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 991}
992
518c8aee
GJ		 993static inline bool cpu_has_vmx_invvpid_single(void)
994{
995 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
996}
997
b9d762fa
GJ		 998static inline bool cpu_has_vmx_invvpid_global(void)
999{
1000 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1001}
1002
31299944 1003static inline bool cpu_has_vmx_ept(void)
d56f546d 1004{
04547156
SY		 1005 return vmcs_config.cpu_based_2nd_exec_ctrl &
1006 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1007}
1008
31299944 1009static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1010{
1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1013}
1014
31299944 1015static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1016{
1017 return vmcs_config.cpu_based_2nd_exec_ctrl &
1018 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1019}
1020
31299944 1021static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1022{
6d3e435e 1023 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1024}
1025
31299944 1026static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1027{
04547156
SY		 1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1033{
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_RDTSCP;
1036}
1037
ad756a16
MJ		 1038static inline bool cpu_has_vmx_invpcid(void)
1039{
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_ENABLE_INVPCID;
1042}
1043
31299944 1044static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1045{
1046 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1047}
1048
f5f48ee1
SY		 1049static inline bool cpu_has_vmx_wbinvd_exit(void)
1050{
1051 return vmcs_config.cpu_based_2nd_exec_ctrl &
1052 SECONDARY_EXEC_WBINVD_EXITING;
1053}
1054
abc4fc58
AG		 1055static inline bool cpu_has_vmx_shadow_vmcs(void)
1056{
1057 u64 vmx_msr;
1058 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1059 /* check if the cpu supports writing r/o exit information fields */
1060 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1061 return false;
1062
1063 return vmcs_config.cpu_based_2nd_exec_ctrl &
1064 SECONDARY_EXEC_SHADOW_VMCS;
1065}
1066
04547156
SY		 1067static inline bool report_flexpriority(void)
1068{
1069 return flexpriority_enabled;
1070}
1071
fe3ef05c
NHE		 1072static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1073{
1074 return vmcs12->cpu_based_vm_exec_control & bit;
1075}
1076
1077static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1078{
1079 return (vmcs12->cpu_based_vm_exec_control &
1080 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1081 (vmcs12->secondary_vm_exec_control & bit);
1082}
1083
f5c4368f 1084static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1085{
1086 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1087}
1088
f4124500
JK		 1089static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1090{
1091 return vmcs12->pin_based_vm_exec_control &
1092 PIN_BASED_VMX_PREEMPTION_TIMER;
1093}
1094
155a97a3
NHE		 1095static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1096{
1097 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1098}
1099
644d711a
NHE		 1100static inline bool is_exception(u32 intr_info)
1101{
1102 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1103 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1104}
1105
533558bc
JK		 1106static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1107 u32 exit_intr_info,
1108 unsigned long exit_qualification);
7c177938
NHE		 1109static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1110 struct vmcs12 *vmcs12,
1111 u32 reason, unsigned long qualification);
1112
8b9cf98c 1113static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1114{
1115 int i;
1116
a2fa3e9f 1117 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1118 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1119 return i;
1120 return -1;
1121}
1122
2384d2b3
SY		 1123static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1124{
1125 struct {
1126 u64 vpid : 16;
1127 u64 rsvd : 48;
1128 u64 gva;
1129 } operand = { vpid, 0, gva };
1130
4ecac3fd 1131 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1132 /* CF==1 or ZF==1 --> rc = -1 */
1133 "; ja 1f ; ud2 ; 1:"
1134 : : "a"(&operand), "c"(ext) : "cc", "memory");
1135}
1136
1439442c
SY		 1137static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1138{
1139 struct {
1140 u64 eptp, gpa;
1141 } operand = {eptp, gpa};
1142
4ecac3fd 1143 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1144 /* CF==1 or ZF==1 --> rc = -1 */
1145 "; ja 1f ; ud2 ; 1:\n"
1146 : : "a" (&operand), "c" (ext) : "cc", "memory");
1147}
1148
26bb0981 1149static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1150{
1151 int i;
1152
8b9cf98c 1153 i = __find_msr_index(vmx, msr);
a75beee6 1154 if (i >= 0)
a2fa3e9f 1155 return &vmx->guest_msrs[i];
8b6d44c7 1156 return NULL;
7725f0ba
AK		 1157}
1158
6aa8b732
AK		 1159static void vmcs_clear(struct vmcs *vmcs)
1160{
1161 u64 phys_addr = __pa(vmcs);
1162 u8 error;
1163
4ecac3fd 1164 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1165 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1166 : "cc", "memory");
1167 if (error)
1168 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1169 vmcs, phys_addr);
1170}
1171
d462b819
NHE		 1172static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1173{
1174 vmcs_clear(loaded_vmcs->vmcs);
1175 loaded_vmcs->cpu = -1;
1176 loaded_vmcs->launched = 0;
1177}
1178
7725b894
DX		 1179static void vmcs_load(struct vmcs *vmcs)
1180{
1181 u64 phys_addr = __pa(vmcs);
1182 u8 error;
1183
1184 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1185 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1186 : "cc", "memory");
1187 if (error)
2844d849 1188 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1189 vmcs, phys_addr);
1190}
1191
8f536b76
ZY		 1192#ifdef CONFIG_KEXEC
1193/*
1194 * This bitmap is used to indicate whether the vmclear
1195 * operation is enabled on all cpus. All disabled by
1196 * default.
1197 */
1198static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1199
1200static inline void crash_enable_local_vmclear(int cpu)
1201{
1202 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1203}
1204
1205static inline void crash_disable_local_vmclear(int cpu)
1206{
1207 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1208}
1209
1210static inline int crash_local_vmclear_enabled(int cpu)
1211{
1212 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1213}
1214
1215static void crash_vmclear_local_loaded_vmcss(void)
1216{
1217 int cpu = raw_smp_processor_id();
1218 struct loaded_vmcs *v;
1219
1220 if (!crash_local_vmclear_enabled(cpu))
1221 return;
1222
1223 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1224 loaded_vmcss_on_cpu_link)
1225 vmcs_clear(v->vmcs);
1226}
1227#else
1228static inline void crash_enable_local_vmclear(int cpu) { }
1229static inline void crash_disable_local_vmclear(int cpu) { }
1230#endif /* CONFIG_KEXEC */
1231
d462b819 1232static void __loaded_vmcs_clear(void *arg)
6aa8b732 1233{
d462b819 1234 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1235 int cpu = raw_smp_processor_id();
6aa8b732 1236
d462b819
NHE		 1237 if (loaded_vmcs->cpu != cpu)
1238 return; /* vcpu migration can race with cpu offline */
1239 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1240 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1241 crash_disable_local_vmclear(cpu);
d462b819 1242 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1243
1244 /*
1245 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1246 * is before setting loaded_vmcs->vcpu to -1 which is done in
1247 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1248 * then adds the vmcs into percpu list before it is deleted.
1249 */
1250 smp_wmb();
1251
d462b819 1252 loaded_vmcs_init(loaded_vmcs);
8f536b76 1253 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1254}
1255
d462b819 1256static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1257{
e6c7d321
XG		 1258 int cpu = loaded_vmcs->cpu;
1259
1260 if (cpu != -1)
1261 smp_call_function_single(cpu,
1262 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1263}
1264
1760dd49 1265static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1266{
1267 if (vmx->vpid == 0)
1268 return;
1269
518c8aee
GJ		 1270 if (cpu_has_vmx_invvpid_single())
1271 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1272}
1273
b9d762fa
GJ		 1274static inline void vpid_sync_vcpu_global(void)
1275{
1276 if (cpu_has_vmx_invvpid_global())
1277 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1278}
1279
1280static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1281{
1282 if (cpu_has_vmx_invvpid_single())
1760dd49 1283 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1284 else
1285 vpid_sync_vcpu_global();
1286}
1287
1439442c
SY		 1288static inline void ept_sync_global(void)
1289{
1290 if (cpu_has_vmx_invept_global())
1291 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1292}
1293
1294static inline void ept_sync_context(u64 eptp)
1295{
089d034e 1296 if (enable_ept) {
1439442c
SY		 1297 if (cpu_has_vmx_invept_context())
1298 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1299 else
1300 ept_sync_global();
1301 }
1302}
1303
96304217 1304static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1305{
5e520e62 1306 unsigned long value;
6aa8b732 1307
5e520e62
AK		 1308 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1309 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1310 return value;
1311}
1312
96304217 1313static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1314{
1315 return vmcs_readl(field);
1316}
1317
96304217 1318static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1319{
1320 return vmcs_readl(field);
1321}
1322
96304217 1323static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1324{
05b3e0c2 1325#ifdef CONFIG_X86_64
6aa8b732
AK		 1326 return vmcs_readl(field);
1327#else
1328 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1329#endif
1330}
1331
e52de1b8
AK		 1332static noinline void vmwrite_error(unsigned long field, unsigned long value)
1333{
1334 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1335 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1336 dump_stack();
1337}
1338
6aa8b732
AK		 1339static void vmcs_writel(unsigned long field, unsigned long value)
1340{
1341 u8 error;
1342
4ecac3fd 1343 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1344 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1345 if (unlikely(error))
1346 vmwrite_error(field, value);
6aa8b732
AK		 1347}
1348
1349static void vmcs_write16(unsigned long field, u16 value)
1350{
1351 vmcs_writel(field, value);
1352}
1353
1354static void vmcs_write32(unsigned long field, u32 value)
1355{
1356 vmcs_writel(field, value);
1357}
1358
1359static void vmcs_write64(unsigned long field, u64 value)
1360{
6aa8b732 1361 vmcs_writel(field, value);
7682f2d0 1362#ifndef CONFIG_X86_64
6aa8b732
AK		 1363 asm volatile ("");
1364 vmcs_writel(field+1, value >> 32);
1365#endif
1366}
1367
2ab455cc
AL		 1368static void vmcs_clear_bits(unsigned long field, u32 mask)
1369{
1370 vmcs_writel(field, vmcs_readl(field) & ~mask);
1371}
1372
1373static void vmcs_set_bits(unsigned long field, u32 mask)
1374{
1375 vmcs_writel(field, vmcs_readl(field) | mask);
1376}
1377
2961e876
GN		 1378static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1379{
1380 vmcs_write32(VM_ENTRY_CONTROLS, val);
1381 vmx->vm_entry_controls_shadow = val;
1382}
1383
1384static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1385{
1386 if (vmx->vm_entry_controls_shadow != val)
1387 vm_entry_controls_init(vmx, val);
1388}
1389
1390static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1391{
1392 return vmx->vm_entry_controls_shadow;
1393}
1394
1395
1396static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1397{
1398 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1399}
1400
1401static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1402{
1403 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1404}
1405
1406static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1407{
1408 vmcs_write32(VM_EXIT_CONTROLS, val);
1409 vmx->vm_exit_controls_shadow = val;
1410}
1411
1412static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1413{
1414 if (vmx->vm_exit_controls_shadow != val)
1415 vm_exit_controls_init(vmx, val);
1416}
1417
1418static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1419{
1420 return vmx->vm_exit_controls_shadow;
1421}
1422
1423
1424static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1425{
1426 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1427}
1428
1429static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1430{
1431 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1432}
1433
2fb92db1
AK		 1434static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1435{
1436 vmx->segment_cache.bitmask = 0;
1437}
1438
1439static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1440 unsigned field)
1441{
1442 bool ret;
1443 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1444
1445 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1446 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1447 vmx->segment_cache.bitmask = 0;
1448 }
1449 ret = vmx->segment_cache.bitmask & mask;
1450 vmx->segment_cache.bitmask |= mask;
1451 return ret;
1452}
1453
1454static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1455{
1456 u16 *p = &vmx->segment_cache.seg[seg].selector;
1457
1458 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1459 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1460 return *p;
1461}
1462
1463static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1464{
1465 ulong *p = &vmx->segment_cache.seg[seg].base;
1466
1467 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1468 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1469 return *p;
1470}
1471
1472static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1473{
1474 u32 *p = &vmx->segment_cache.seg[seg].limit;
1475
1476 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1477 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1478 return *p;
1479}
1480
1481static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1482{
1483 u32 *p = &vmx->segment_cache.seg[seg].ar;
1484
1485 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1486 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1487 return *p;
1488}
1489
abd3f2d6
AK		 1490static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1491{
1492 u32 eb;
1493
fd7373cc
JK		 1494 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1495 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1496 if ((vcpu->guest_debug &
1497 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1498 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1499 eb |= 1u << BP_VECTOR;
7ffd92c5 1500 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1501 eb = ~0;
089d034e 1502 if (enable_ept)
1439442c 1503 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1504 if (vcpu->fpu_active)
1505 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1506
1507 /* When we are running a nested L2 guest and L1 specified for it a
1508 * certain exception bitmap, we must trap the same exceptions and pass
1509 * them to L1. When running L2, we will only handle the exceptions
1510 * specified above if L1 did not want them.
1511 */
1512 if (is_guest_mode(vcpu))
1513 eb |= get_vmcs12(vcpu)->exception_bitmap;
1514
abd3f2d6
AK		 1515 vmcs_write32(EXCEPTION_BITMAP, eb);
1516}
1517
2961e876
GN		 1518static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1519 unsigned long entry, unsigned long exit)
8bf00a52 1520{
2961e876
GN		 1521 vm_entry_controls_clearbit(vmx, entry);
1522 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1523}
1524
61d2ef2c
AK		 1525static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1526{
1527 unsigned i;
1528 struct msr_autoload *m = &vmx->msr_autoload;
1529
8bf00a52
GN		 1530 switch (msr) {
1531 case MSR_EFER:
1532 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1533 clear_atomic_switch_msr_special(vmx,
1534 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1535 VM_EXIT_LOAD_IA32_EFER);
1536 return;
1537 }
1538 break;
1539 case MSR_CORE_PERF_GLOBAL_CTRL:
1540 if (cpu_has_load_perf_global_ctrl) {
2961e876 1541 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1542 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1543 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1544 return;
1545 }
1546 break;
110312c8
AK		 1547 }
1548
61d2ef2c
AK		 1549 for (i = 0; i < m->nr; ++i)
1550 if (m->guest[i].index == msr)
1551 break;
1552
1553 if (i == m->nr)
1554 return;
1555 --m->nr;
1556 m->guest[i] = m->guest[m->nr];
1557 m->host[i] = m->host[m->nr];
1558 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1559 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1560}
1561
2961e876
GN		 1562static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1563 unsigned long entry, unsigned long exit,
1564 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1565 u64 guest_val, u64 host_val)
8bf00a52
GN		 1566{
1567 vmcs_write64(guest_val_vmcs, guest_val);
1568 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1569 vm_entry_controls_setbit(vmx, entry);
1570 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1571}
1572
61d2ef2c
AK		 1573static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1574 u64 guest_val, u64 host_val)
1575{
1576 unsigned i;
1577 struct msr_autoload *m = &vmx->msr_autoload;
1578
8bf00a52
GN		 1579 switch (msr) {
1580 case MSR_EFER:
1581 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1582 add_atomic_switch_msr_special(vmx,
1583 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1584 VM_EXIT_LOAD_IA32_EFER,
1585 GUEST_IA32_EFER,
1586 HOST_IA32_EFER,
1587 guest_val, host_val);
1588 return;
1589 }
1590 break;
1591 case MSR_CORE_PERF_GLOBAL_CTRL:
1592 if (cpu_has_load_perf_global_ctrl) {
2961e876 1593 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1594 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1595 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1596 GUEST_IA32_PERF_GLOBAL_CTRL,
1597 HOST_IA32_PERF_GLOBAL_CTRL,
1598 guest_val, host_val);
1599 return;
1600 }
1601 break;
110312c8
AK		 1602 }
1603
61d2ef2c
AK		 1604 for (i = 0; i < m->nr; ++i)
1605 if (m->guest[i].index == msr)
1606 break;
1607
e7fc6f93 1608 if (i == NR_AUTOLOAD_MSRS) {
60266204 1609 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1610 "Can't add msr %x\n", msr);
1611 return;
1612 } else if (i == m->nr) {
61d2ef2c
AK		 1613 ++m->nr;
1614 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1615 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1616 }
1617
1618 m->guest[i].index = msr;
1619 m->guest[i].value = guest_val;
1620 m->host[i].index = msr;
1621 m->host[i].value = host_val;
1622}
1623
33ed6329
AK		 1624static void reload_tss(void)
1625{
33ed6329
AK		 1626 /*
1627 * VT restores TR but not its size. Useless.
1628 */
d359192f 1629 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1630 struct desc_struct *descs;
33ed6329 1631
d359192f 1632 descs = (void *)gdt->address;
33ed6329
AK		 1633 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1634 load_TR_desc();
33ed6329
AK		 1635}
1636
92c0d900 1637static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1638{
3a34a881 1639 u64 guest_efer;
51c6cf66
AK		 1640 u64 ignore_bits;
1641
f6801dff 1642 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1643
51c6cf66 1644 /*
0fa06071 1645 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1646 * outside long mode
1647 */
1648 ignore_bits = EFER_NX | EFER_SCE;
1649#ifdef CONFIG_X86_64
1650 ignore_bits |= EFER_LMA | EFER_LME;
1651 /* SCE is meaningful only in long mode on Intel */
1652 if (guest_efer & EFER_LMA)
1653 ignore_bits &= ~(u64)EFER_SCE;
1654#endif
51c6cf66
AK		 1655 guest_efer &= ~ignore_bits;
1656 guest_efer |= host_efer & ignore_bits;
26bb0981 1657 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1658 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1659
1660 clear_atomic_switch_msr(vmx, MSR_EFER);
1661 /* On ept, can't emulate nx, and must switch nx atomically */
1662 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1663 guest_efer = vmx->vcpu.arch.efer;
1664 if (!(guest_efer & EFER_LMA))
1665 guest_efer &= ~EFER_LME;
1666 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1667 return false;
1668 }
1669
26bb0981 1670 return true;
51c6cf66
AK		 1671}
1672
2d49ec72
GN		 1673static unsigned long segment_base(u16 selector)
1674{
d359192f 1675 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1676 struct desc_struct *d;
1677 unsigned long table_base;
1678 unsigned long v;
1679
1680 if (!(selector & ~3))
1681 return 0;
1682
d359192f 1683 table_base = gdt->address;
2d49ec72
GN		 1684
1685 if (selector & 4) { /* from ldt */
1686 u16 ldt_selector = kvm_read_ldt();
1687
1688 if (!(ldt_selector & ~3))
1689 return 0;
1690
1691 table_base = segment_base(ldt_selector);
1692 }
1693 d = (struct desc_struct *)(table_base + (selector & ~7));
1694 v = get_desc_base(d);
1695#ifdef CONFIG_X86_64
1696 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1697 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1698#endif
1699 return v;
1700}
1701
1702static inline unsigned long kvm_read_tr_base(void)
1703{
1704 u16 tr;
1705 asm("str %0" : "=g"(tr));
1706 return segment_base(tr);
1707}
1708
04d2cc77 1709static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1710{
04d2cc77 1711 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1712 int i;
04d2cc77 1713
a2fa3e9f 1714 if (vmx->host_state.loaded)
33ed6329
AK		 1715 return;
1716
a2fa3e9f 1717 vmx->host_state.loaded = 1;
33ed6329
AK		 1718 /*
1719 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1720 * allow segment selectors with cpl > 0 or ti == 1.
1721 */
d6e88aec 1722 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1723 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1724 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1725 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1726 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1727 vmx->host_state.fs_reload_needed = 0;
1728 } else {
33ed6329 1729 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1730 vmx->host_state.fs_reload_needed = 1;
33ed6329 1731 }
9581d442 1732 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1733 if (!(vmx->host_state.gs_sel & 7))
1734 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1735 else {
1736 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1737 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1738 }
1739
b2da15ac
AK		 1740#ifdef CONFIG_X86_64
1741 savesegment(ds, vmx->host_state.ds_sel);
1742 savesegment(es, vmx->host_state.es_sel);
1743#endif
1744
33ed6329
AK		 1745#ifdef CONFIG_X86_64
1746 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1747 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1748#else
a2fa3e9f
GH		 1749 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1750 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1751#endif
707c0874
AK		 1752
1753#ifdef CONFIG_X86_64
c8770e7b
AK		 1754 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1755 if (is_long_mode(&vmx->vcpu))
44ea2b17 1756 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1757#endif
da8999d3
LJ		 1758 if (boot_cpu_has(X86_FEATURE_MPX))
1759 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1760 for (i = 0; i < vmx->save_nmsrs; ++i)
1761 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1762 vmx->guest_msrs[i].data,
1763 vmx->guest_msrs[i].mask);
33ed6329
AK		 1764}
1765
a9b21b62 1766static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1767{
a2fa3e9f 1768 if (!vmx->host_state.loaded)
33ed6329
AK		 1769 return;
1770
e1beb1d3 1771 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1772 vmx->host_state.loaded = 0;
c8770e7b
AK		 1773#ifdef CONFIG_X86_64
1774 if (is_long_mode(&vmx->vcpu))
1775 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1776#endif
152d3f2f 1777 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1778 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1779#ifdef CONFIG_X86_64
9581d442 1780 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1781#else
1782 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1783#endif
33ed6329 1784 }
0a77fe4c
AK		 1785 if (vmx->host_state.fs_reload_needed)
1786 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1787#ifdef CONFIG_X86_64
1788 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1789 loadsegment(ds, vmx->host_state.ds_sel);
1790 loadsegment(es, vmx->host_state.es_sel);
1791 }
b2da15ac 1792#endif
152d3f2f 1793 reload_tss();
44ea2b17 1794#ifdef CONFIG_X86_64
c8770e7b 1795 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1796#endif
da8999d3
LJ		 1797 if (vmx->host_state.msr_host_bndcfgs)
1798 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1799 /*
1800 * If the FPU is not active (through the host task or
1801 * the guest vcpu), then restore the cr0.TS bit.
1802 */
1803 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1804 stts();
3444d7da 1805 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1806}
1807
a9b21b62
AK		 1808static void vmx_load_host_state(struct vcpu_vmx *vmx)
1809{
1810 preempt_disable();
1811 __vmx_load_host_state(vmx);
1812 preempt_enable();
1813}
1814
6aa8b732
AK		 1815/*
1816 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1817 * vcpu mutex is already taken.
1818 */
15ad7146 1819static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1820{
a2fa3e9f 1821 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1822 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1823
4610c9cc
DX		 1824 if (!vmm_exclusive)
1825 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1826 else if (vmx->loaded_vmcs->cpu != cpu)
1827 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1828
d462b819
NHE		 1829 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1830 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1831 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1832 }
1833
d462b819 1834 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1835 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1836 unsigned long sysenter_esp;
1837
a8eeb04a 1838 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1839 local_irq_disable();
8f536b76 1840 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1841
1842 /*
1843 * Read loaded_vmcs->cpu should be before fetching
1844 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1845 * See the comments in __loaded_vmcs_clear().
1846 */
1847 smp_rmb();
1848
d462b819
NHE		 1849 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1850 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1851 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1852 local_irq_enable();
1853
6aa8b732
AK		 1854 /*
1855 * Linux uses per-cpu TSS and GDT, so set these when switching
1856 * processors.
1857 */
d6e88aec 1858 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1859 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1860
1861 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1862 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1863 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1864 }
6aa8b732
AK		 1865}
1866
1867static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1868{
a9b21b62 1869 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1870 if (!vmm_exclusive) {
d462b819
NHE		 1871 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1872 vcpu->cpu = -1;
4610c9cc
DX		 1873 kvm_cpu_vmxoff();
1874 }
6aa8b732
AK		 1875}
1876
5fd86fcf
AK		 1877static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1878{
81231c69
AK		 1879 ulong cr0;
1880
5fd86fcf
AK		 1881 if (vcpu->fpu_active)
1882 return;
1883 vcpu->fpu_active = 1;
81231c69
AK		 1884 cr0 = vmcs_readl(GUEST_CR0);
1885 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1886 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1887 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1888 update_exception_bitmap(vcpu);
edcafe3c 1889 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1890 if (is_guest_mode(vcpu))
1891 vcpu->arch.cr0_guest_owned_bits &=
1892 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1893 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1894}
1895
edcafe3c
AK		 1896static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1897
fe3ef05c
NHE		 1898/*
1899 * Return the cr0 value that a nested guest would read. This is a combination
1900 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1901 * its hypervisor (cr0_read_shadow).
1902 */
1903static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1904{
1905 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1906 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1907}
1908static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1909{
1910 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1911 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1912}
1913
5fd86fcf
AK		 1914static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1915{
36cf24e0
NHE		 1916 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1917 * set this *before* calling this function.
1918 */
edcafe3c 1919 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1920 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1921 update_exception_bitmap(vcpu);
edcafe3c
AK		 1922 vcpu->arch.cr0_guest_owned_bits = 0;
1923 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1924 if (is_guest_mode(vcpu)) {
1925 /*
1926 * L1's specified read shadow might not contain the TS bit,
1927 * so now that we turned on shadowing of this bit, we need to
1928 * set this bit of the shadow. Like in nested_vmx_run we need
1929 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1930 * up-to-date here because we just decached cr0.TS (and we'll
1931 * only update vmcs12->guest_cr0 on nested exit).
1932 */
1933 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1934 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1935 (vcpu->arch.cr0 & X86_CR0_TS);
1936 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1937 } else
1938 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1939}
1940
6aa8b732
AK		 1941static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1942{
78ac8b47 1943 unsigned long rflags, save_rflags;
345dcaa8 1944
6de12732
AK		 1945 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1946 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1947 rflags = vmcs_readl(GUEST_RFLAGS);
1948 if (to_vmx(vcpu)->rmode.vm86_active) {
1949 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1950 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1951 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1952 }
1953 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1954 }
6de12732 1955 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1956}
1957
1958static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1959{
6de12732
AK		 1960 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1961 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1962 if (to_vmx(vcpu)->rmode.vm86_active) {
1963 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1964 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1965 }
6aa8b732
AK		 1966 vmcs_writel(GUEST_RFLAGS, rflags);
1967}
1968
37ccdcbe 1969static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1970{
1971 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1972 int ret = 0;
1973
1974 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1975 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1976 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1977 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1978
37ccdcbe 1979 return ret;
2809f5d2
GC		 1980}
1981
1982static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1983{
1984 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1985 u32 interruptibility = interruptibility_old;
1986
1987 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1988
48005f64 1989 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1990 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1991 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1992 interruptibility |= GUEST_INTR_STATE_STI;
1993
1994 if ((interruptibility != interruptibility_old))
1995 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1996}
1997
6aa8b732
AK		 1998static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1999{
2000 unsigned long rip;
6aa8b732 2001
5fdbf976 2002 rip = kvm_rip_read(vcpu);
6aa8b732 2003 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2004 kvm_rip_write(vcpu, rip);
6aa8b732 2005
2809f5d2
GC		 2006 /* skipping an emulated instruction also counts */
2007 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2008}
2009
0b6ac343
NHE		 2010/*
2011 * KVM wants to inject page-faults which it got to the guest. This function
2012 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2013 */
e011c663 2014static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2015{
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017
e011c663 2018 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2019 return 0;
2020
533558bc
JK		 2021 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2022 vmcs_read32(VM_EXIT_INTR_INFO),
2023 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2024 return 1;
2025}
2026
298101da 2027static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2028 bool has_error_code, u32 error_code,
2029 bool reinject)
298101da 2030{
77ab6db0 2031 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2032 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2033
e011c663
GN		 2034 if (!reinject && is_guest_mode(vcpu) &&
2035 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2036 return;
2037
8ab2d2e2 2038 if (has_error_code) {
77ab6db0 2039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2040 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2041 }
77ab6db0 2042
7ffd92c5 2043 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2044 int inc_eip = 0;
2045 if (kvm_exception_is_soft(nr))
2046 inc_eip = vcpu->arch.event_exit_inst_len;
2047 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2048 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2049 return;
2050 }
2051
66fd3f7f
GN		 2052 if (kvm_exception_is_soft(nr)) {
2053 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2054 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2055 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2056 } else
2057 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2058
2059 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2060}
2061
4e47c7a6
SY		 2062static bool vmx_rdtscp_supported(void)
2063{
2064 return cpu_has_vmx_rdtscp();
2065}
2066
ad756a16
MJ		 2067static bool vmx_invpcid_supported(void)
2068{
2069 return cpu_has_vmx_invpcid() && enable_ept;
2070}
2071
a75beee6
ED		 2072/*
2073 * Swap MSR entry in host/guest MSR entry array.
2074 */
8b9cf98c 2075static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2076{
26bb0981 2077 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2078
2079 tmp = vmx->guest_msrs[to];
2080 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2081 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2082}
2083
8d14695f
YZ		 2084static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2085{
2086 unsigned long *msr_bitmap;
2087
2088 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2089 if (is_long_mode(vcpu))
2090 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2091 else
2092 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2093 } else {
2094 if (is_long_mode(vcpu))
2095 msr_bitmap = vmx_msr_bitmap_longmode;
2096 else
2097 msr_bitmap = vmx_msr_bitmap_legacy;
2098 }
2099
2100 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2101}
2102
e38aea3e
AK		 2103/*
2104 * Set up the vmcs to automatically save and restore system
2105 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2106 * mode, as fiddling with msrs is very expensive.
2107 */
8b9cf98c 2108static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2109{
26bb0981 2110 int save_nmsrs, index;
e38aea3e 2111
a75beee6
ED		 2112 save_nmsrs = 0;
2113#ifdef CONFIG_X86_64
8b9cf98c 2114 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2115 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2116 if (index >= 0)
8b9cf98c
RR		 2117 move_msr_up(vmx, index, save_nmsrs++);
2118 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2119 if (index >= 0)
8b9cf98c
RR		 2120 move_msr_up(vmx, index, save_nmsrs++);
2121 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2122 if (index >= 0)
8b9cf98c 2123 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2124 index = __find_msr_index(vmx, MSR_TSC_AUX);
2125 if (index >= 0 && vmx->rdtscp_enabled)
2126 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2127 /*
8c06585d 2128 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2129 * if efer.sce is enabled.
2130 */
8c06585d 2131 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2132 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2133 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2134 }
2135#endif
92c0d900
AK		 2136 index = __find_msr_index(vmx, MSR_EFER);
2137 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2138 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2139
26bb0981 2140 vmx->save_nmsrs = save_nmsrs;
5897297b 2141
8d14695f
YZ		 2142 if (cpu_has_vmx_msr_bitmap())
2143 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2144}
2145
6aa8b732
AK		 2146/*
2147 * reads and returns guest's timestamp counter "register"
2148 * guest_tsc = host_tsc + tsc_offset -- 21.3
2149 */
2150static u64 guest_read_tsc(void)
2151{
2152 u64 host_tsc, tsc_offset;
2153
2154 rdtscll(host_tsc);
2155 tsc_offset = vmcs_read64(TSC_OFFSET);
2156 return host_tsc + tsc_offset;
2157}
2158
d5c1785d
NHE		 2159/*
2160 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2161 * counter, even if a nested guest (L2) is currently running.
2162 */
48d89b92 2163static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2164{
886b470c 2165 u64 tsc_offset;
d5c1785d 2166
d5c1785d
NHE		 2167 tsc_offset = is_guest_mode(vcpu) ?
2168 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2169 vmcs_read64(TSC_OFFSET);
2170 return host_tsc + tsc_offset;
2171}
2172
4051b188 2173/*
cc578287
ZA		 2174 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2175 * software catchup for faster rates on slower CPUs.
4051b188 2176 */
cc578287 2177static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2178{
cc578287
ZA		 2179 if (!scale)
2180 return;
2181
2182 if (user_tsc_khz > tsc_khz) {
2183 vcpu->arch.tsc_catchup = 1;
2184 vcpu->arch.tsc_always_catchup = 1;
2185 } else
2186 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2187}
2188
ba904635
WA		 2189static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2190{
2191 return vmcs_read64(TSC_OFFSET);
2192}
2193
6aa8b732 2194/*
99e3e30a 2195 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2196 */
99e3e30a 2197static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2198{
27fc51b2 2199 if (is_guest_mode(vcpu)) {
7991825b 2200 /*
27fc51b2
NHE		 2201 * We're here if L1 chose not to trap WRMSR to TSC. According
2202 * to the spec, this should set L1's TSC; The offset that L1
2203 * set for L2 remains unchanged, and still needs to be added
2204 * to the newly set TSC to get L2's TSC.
7991825b 2205 */
27fc51b2
NHE		 2206 struct vmcs12 *vmcs12;
2207 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2208 /* recalculate vmcs02.TSC_OFFSET: */
2209 vmcs12 = get_vmcs12(vcpu);
2210 vmcs_write64(TSC_OFFSET, offset +
2211 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2212 vmcs12->tsc_offset : 0));
2213 } else {
489223ed
YY		 2214 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2215 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2216 vmcs_write64(TSC_OFFSET, offset);
2217 }
6aa8b732
AK		 2218}
2219
f1e2b260 2220static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2221{
2222 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2223
e48672fa 2224 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2225 if (is_guest_mode(vcpu)) {
2226 /* Even when running L2, the adjustment needs to apply to L1 */
2227 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2228 } else
2229 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2230 offset + adjustment);
e48672fa
ZA		 2231}
2232
857e4099
JR		 2233static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2234{
2235 return target_tsc - native_read_tsc();
2236}
2237
801d3424
NHE		 2238static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2239{
2240 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2241 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2242}
2243
2244/*
2245 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2246 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2247 * all guests if the "nested" module option is off, and can also be disabled
2248 * for a single guest by disabling its VMX cpuid bit.
2249 */
2250static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2251{
2252 return nested && guest_cpuid_has_vmx(vcpu);
2253}
2254
b87a51ae
NHE		 2255/*
2256 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2257 * returned for the various VMX controls MSRs when nested VMX is enabled.
2258 * The same values should also be used to verify that vmcs12 control fields are
2259 * valid during nested entry from L1 to L2.
2260 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2261 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2262 * bit in the high half is on if the corresponding bit in the control field
2263 * may be on. See also vmx_control_verify().
2264 * TODO: allow these variables to be modified (downgraded) by module options
2265 * or other means.
2266 */
2267static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2268static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2269static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2270static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2271static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2272static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2273static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2274static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2275static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2276static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2277static __init void nested_vmx_setup_ctls_msrs(void)
2278{
2279 /*
2280 * Note that as a general rule, the high half of the MSRs (bits in
2281 * the control fields which may be 1) should be initialized by the
2282 * intersection of the underlying hardware's MSR (i.e., features which
2283 * can be supported) and the list of features we want to expose -
2284 * because they are known to be properly supported in our code.
2285 * Also, usually, the low half of the MSRs (bits which must be 1) can
2286 * be set to 0, meaning that L1 may turn off any of these bits. The
2287 * reason is that if one of these bits is necessary, it will appear
2288 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2289 * fields of vmcs01 and vmcs02, will turn these bits off - and
2290 * nested_vmx_exit_handled() will not pass related exits to L1.
2291 * These rules have exceptions below.
2292 */
2293
2294 /* pin-based controls */
eabeaacc
JK		 2295 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2296 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2297 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2298 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2299 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2300 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2301 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2302
3dbcd8da 2303 /* exit controls */
c0dfee58
ACL		 2304 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2305 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2306 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2307
c0dfee58 2308 nested_vmx_exit_ctls_high &=
b87a51ae 2309#ifdef CONFIG_X86_64
c0dfee58 2310 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2311#endif
f4124500
JK		 2312 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2313 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2314 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2315 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2316
36be0b9d
PB		 2317 if (vmx_mpx_supported())
2318 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2319
2996fca0
JK		 2320 /* We support free control of debug control saving. */
2321 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2322 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2323
b87a51ae
NHE		 2324 /* entry controls */
2325 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2326 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2327 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2328 nested_vmx_entry_ctls_high &=
57435349
JK		 2329#ifdef CONFIG_X86_64
2330 VM_ENTRY_IA32E_MODE |
2331#endif
2332 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2333 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2334 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2335 if (vmx_mpx_supported())
2336 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2337
2996fca0
JK		 2338 /* We support free control of debug control loading. */
2339 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2340 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2341
b87a51ae
NHE		 2342 /* cpu-based controls */
2343 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2344 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2345 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2346 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2347 CPU_BASED_VIRTUAL_INTR_PENDING |
2348 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2349 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2350 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2351 CPU_BASED_CR3_STORE_EXITING |
2352#ifdef CONFIG_X86_64
2353 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2354#endif
2355 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2356 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2357 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2358 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2359 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2360 /*
2361 * We can allow some features even when not supported by the
2362 * hardware. For example, L1 can specify an MSR bitmap - and we
2363 * can use it to avoid exits to L1 - even when L0 runs L2
2364 * without MSR bitmaps.
2365 */
560b7ee1
JK		 2366 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2367 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2368
3dcdf3ec
JK		 2369 /* We support free control of CR3 access interception. */
2370 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2371 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2372
b87a51ae
NHE		 2373 /* secondary cpu-based controls */
2374 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2375 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2376 nested_vmx_secondary_ctls_low = 0;
2377 nested_vmx_secondary_ctls_high &=
d6851fbe 2378 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2379 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2380 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2381
afa61f75
NHE		 2382 if (enable_ept) {
2383 /* nested EPT: emulate EPT also to L1 */
2384 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2385 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2386 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2387 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2388 nested_vmx_ept_caps &= vmx_capability.ept;
2389 /*
4b855078
BD		 2390 * For nested guests, we don't do anything specific
2391 * for single context invalidation. Hence, only advertise
2392 * support for global context invalidation.
afa61f75 2393 */
4b855078 2394 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2395 } else
2396 nested_vmx_ept_caps = 0;
2397
c18911a2
JK		 2398 /* miscellaneous data */
2399 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2400 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2401 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2402 VMX_MISC_ACTIVITY_HLT;
c18911a2 2403 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2404}
2405
2406static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2407{
2408 /*
2409 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2410 */
2411 return ((control & high) | low) == control;
2412}
2413
2414static inline u64 vmx_control_msr(u32 low, u32 high)
2415{
2416 return low | ((u64)high << 32);
2417}
2418
cae50139 2419/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2420static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2421{
b87a51ae 2422 switch (msr_index) {
b87a51ae
NHE		 2423 case MSR_IA32_VMX_BASIC:
2424 /*
2425 * This MSR reports some information about VMX support. We
2426 * should return information about the VMX we emulate for the
2427 * guest, and the VMCS structure we give it - not about the
2428 * VMX support of the underlying hardware.
2429 */
3dbcd8da 2430 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2431 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2432 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2433 break;
2434 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2435 case MSR_IA32_VMX_PINBASED_CTLS:
2436 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2437 nested_vmx_pinbased_ctls_high);
2438 break;
2439 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2440 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2441 nested_vmx_procbased_ctls_high);
2442 break;
b87a51ae
NHE		 2443 case MSR_IA32_VMX_PROCBASED_CTLS:
2444 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2445 nested_vmx_procbased_ctls_high);
2446 break;
2447 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2448 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2449 nested_vmx_exit_ctls_high);
2450 break;
b87a51ae
NHE		 2451 case MSR_IA32_VMX_EXIT_CTLS:
2452 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2453 nested_vmx_exit_ctls_high);
2454 break;
2455 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2456 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2457 nested_vmx_entry_ctls_high);
2458 break;
b87a51ae
NHE		 2459 case MSR_IA32_VMX_ENTRY_CTLS:
2460 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2461 nested_vmx_entry_ctls_high);
2462 break;
2463 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2464 *pdata = vmx_control_msr(nested_vmx_misc_low,
2465 nested_vmx_misc_high);
b87a51ae
NHE		 2466 break;
2467 /*
2468 * These MSRs specify bits which the guest must keep fixed (on or off)
2469 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2470 * We picked the standard core2 setting.
2471 */
2472#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2473#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2474 case MSR_IA32_VMX_CR0_FIXED0:
2475 *pdata = VMXON_CR0_ALWAYSON;
2476 break;
2477 case MSR_IA32_VMX_CR0_FIXED1:
2478 *pdata = -1ULL;
2479 break;
2480 case MSR_IA32_VMX_CR4_FIXED0:
2481 *pdata = VMXON_CR4_ALWAYSON;
2482 break;
2483 case MSR_IA32_VMX_CR4_FIXED1:
2484 *pdata = -1ULL;
2485 break;
2486 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2487 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2488 break;
2489 case MSR_IA32_VMX_PROCBASED_CTLS2:
2490 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2491 nested_vmx_secondary_ctls_high);
2492 break;
2493 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2494 /* Currently, no nested vpid support */
2495 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2496 break;
2497 default:
b87a51ae 2498 return 1;
b3897a49
NHE		 2499 }
2500
b87a51ae
NHE		 2501 return 0;
2502}
2503
6aa8b732
AK		 2504/*
2505 * Reads an msr value (of 'msr_index') into 'pdata'.
2506 * Returns 0 on success, non-0 otherwise.
2507 * Assumes vcpu_load() was already called.
2508 */
2509static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2510{
2511 u64 data;
26bb0981 2512 struct shared_msr_entry *msr;
6aa8b732
AK		 2513
2514 if (!pdata) {
2515 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2516 return -EINVAL;
2517 }
2518
2519 switch (msr_index) {
05b3e0c2 2520#ifdef CONFIG_X86_64
6aa8b732
AK		 2521 case MSR_FS_BASE:
2522 data = vmcs_readl(GUEST_FS_BASE);
2523 break;
2524 case MSR_GS_BASE:
2525 data = vmcs_readl(GUEST_GS_BASE);
2526 break;
44ea2b17
AK		 2527 case MSR_KERNEL_GS_BASE:
2528 vmx_load_host_state(to_vmx(vcpu));
2529 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2530 break;
26bb0981 2531#endif
6aa8b732 2532 case MSR_EFER:
3bab1f5d 2533 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2534 case MSR_IA32_TSC:
6aa8b732
AK		 2535 data = guest_read_tsc();
2536 break;
2537 case MSR_IA32_SYSENTER_CS:
2538 data = vmcs_read32(GUEST_SYSENTER_CS);
2539 break;
2540 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2541 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2542 break;
2543 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2544 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2545 break;
0dd376e7 2546 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2547 if (!vmx_mpx_supported())
2548 return 1;
0dd376e7
LJ		 2549 data = vmcs_read64(GUEST_BNDCFGS);
2550 break;
cae50139
JK		 2551 case MSR_IA32_FEATURE_CONTROL:
2552 if (!nested_vmx_allowed(vcpu))
2553 return 1;
2554 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2555 break;
2556 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2557 if (!nested_vmx_allowed(vcpu))
2558 return 1;
2559 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2560 case MSR_TSC_AUX:
2561 if (!to_vmx(vcpu)->rdtscp_enabled)
2562 return 1;
2563 /* Otherwise falls through */
6aa8b732 2564 default:
8b9cf98c 2565 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2566 if (msr) {
2567 data = msr->data;
2568 break;
6aa8b732 2569 }
3bab1f5d 2570 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2571 }
2572
2573 *pdata = data;
2574 return 0;
2575}
2576
cae50139
JK		 2577static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2578
6aa8b732
AK		 2579/*
2580 * Writes msr value into into the appropriate "register".
2581 * Returns 0 on success, non-0 otherwise.
2582 * Assumes vcpu_load() was already called.
2583 */
8fe8ab46 2584static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2585{
a2fa3e9f 2586 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2587 struct shared_msr_entry *msr;
2cc51560 2588 int ret = 0;
8fe8ab46
WA		 2589 u32 msr_index = msr_info->index;
2590 u64 data = msr_info->data;
2cc51560 2591
6aa8b732 2592 switch (msr_index) {
3bab1f5d 2593 case MSR_EFER:
8fe8ab46 2594 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2595 break;
16175a79 2596#ifdef CONFIG_X86_64
6aa8b732 2597 case MSR_FS_BASE:
2fb92db1 2598 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2599 vmcs_writel(GUEST_FS_BASE, data);
2600 break;
2601 case MSR_GS_BASE:
2fb92db1 2602 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2603 vmcs_writel(GUEST_GS_BASE, data);
2604 break;
44ea2b17
AK		 2605 case MSR_KERNEL_GS_BASE:
2606 vmx_load_host_state(vmx);
2607 vmx->msr_guest_kernel_gs_base = data;
2608 break;
6aa8b732
AK		 2609#endif
2610 case MSR_IA32_SYSENTER_CS:
2611 vmcs_write32(GUEST_SYSENTER_CS, data);
2612 break;
2613 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2614 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2615 break;
2616 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2617 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2618 break;
0dd376e7 2619 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2620 if (!vmx_mpx_supported())
2621 return 1;
0dd376e7
LJ		 2622 vmcs_write64(GUEST_BNDCFGS, data);
2623 break;
af24a4e4 2624 case MSR_IA32_TSC:
8fe8ab46 2625 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2626 break;
468d472f
SY		 2627 case MSR_IA32_CR_PAT:
2628 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2629 vmcs_write64(GUEST_IA32_PAT, data);
2630 vcpu->arch.pat = data;
2631 break;
2632 }
8fe8ab46 2633 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2634 break;
ba904635
WA		 2635 case MSR_IA32_TSC_ADJUST:
2636 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2637 break;
cae50139
JK		 2638 case MSR_IA32_FEATURE_CONTROL:
2639 if (!nested_vmx_allowed(vcpu) ||
2640 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2641 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2642 return 1;
2643 vmx->nested.msr_ia32_feature_control = data;
2644 if (msr_info->host_initiated && data == 0)
2645 vmx_leave_nested(vcpu);
2646 break;
2647 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2648 return 1; /* they are read-only */
4e47c7a6
SY		 2649 case MSR_TSC_AUX:
2650 if (!vmx->rdtscp_enabled)
2651 return 1;
2652 /* Check reserved bit, higher 32 bits should be zero */
2653 if ((data >> 32) != 0)
2654 return 1;
2655 /* Otherwise falls through */
6aa8b732 2656 default:
8b9cf98c 2657 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2658 if (msr) {
2659 msr->data = data;
2225fd56
AK		 2660 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2661 preempt_disable();
9ee73970
AK		 2662 kvm_set_shared_msr(msr->index, msr->data,
2663 msr->mask);
2225fd56
AK		 2664 preempt_enable();
2665 }
3bab1f5d 2666 break;
6aa8b732 2667 }
8fe8ab46 2668 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2669 }
2670
2cc51560 2671 return ret;
6aa8b732
AK		 2672}
2673
5fdbf976 2674static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2675{
5fdbf976
MT		 2676 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2677 switch (reg) {
2678 case VCPU_REGS_RSP:
2679 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2680 break;
2681 case VCPU_REGS_RIP:
2682 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2683 break;
6de4f3ad
AK		 2684 case VCPU_EXREG_PDPTR:
2685 if (enable_ept)
2686 ept_save_pdptrs(vcpu);
2687 break;
5fdbf976
MT		 2688 default:
2689 break;
2690 }
6aa8b732
AK		 2691}
2692
6aa8b732
AK		 2693static __init int cpu_has_kvm_support(void)
2694{
6210e37b 2695 return cpu_has_vmx();
6aa8b732
AK		 2696}
2697
2698static __init int vmx_disabled_by_bios(void)
2699{
2700 u64 msr;
2701
2702 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2703 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2704 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2705 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2706 && tboot_enabled())
2707 return 1;
23f3e991 2708 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2709 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2710 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2711 && !tboot_enabled()) {
2712 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2713 "activate TXT before enabling KVM\n");
cafd6659 2714 return 1;
f9335afe 2715 }
23f3e991
JC		 2716 /* launched w/o TXT and VMX disabled */
2717 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2718 && !tboot_enabled())
2719 return 1;
cafd6659
SW		 2720 }
2721
2722 return 0;
6aa8b732
AK		 2723}
2724
7725b894
DX		 2725static void kvm_cpu_vmxon(u64 addr)
2726{
2727 asm volatile (ASM_VMX_VMXON_RAX
2728 : : "a"(&addr), "m"(addr)
2729 : "memory", "cc");
2730}
2731
13a34e06 2732static int hardware_enable(void)
6aa8b732
AK		 2733{
2734 int cpu = raw_smp_processor_id();
2735 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2736 u64 old, test_bits;
6aa8b732 2737
10474ae8
AG		 2738 if (read_cr4() & X86_CR4_VMXE)
2739 return -EBUSY;
2740
d462b819 2741 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2742
2743 /*
2744 * Now we can enable the vmclear operation in kdump
2745 * since the loaded_vmcss_on_cpu list on this cpu
2746 * has been initialized.
2747 *
2748 * Though the cpu is not in VMX operation now, there
2749 * is no problem to enable the vmclear operation
2750 * for the loaded_vmcss_on_cpu list is empty!
2751 */
2752 crash_enable_local_vmclear(cpu);
2753
6aa8b732 2754 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2755
2756 test_bits = FEATURE_CONTROL_LOCKED;
2757 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2758 if (tboot_enabled())
2759 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2760
2761 if ((old & test_bits) != test_bits) {
6aa8b732 2762 /* enable and lock */
cafd6659
SW		 2763 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2764 }
66aee91a 2765 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2766
4610c9cc
DX		 2767 if (vmm_exclusive) {
2768 kvm_cpu_vmxon(phys_addr);
2769 ept_sync_global();
2770 }
10474ae8 2771
357d1226 2772 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2773
10474ae8 2774 return 0;
6aa8b732
AK		 2775}
2776
d462b819 2777static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2778{
2779 int cpu = raw_smp_processor_id();
d462b819 2780 struct loaded_vmcs *v, *n;
543e4243 2781
d462b819
NHE		 2782 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2783 loaded_vmcss_on_cpu_link)
2784 __loaded_vmcs_clear(v);
543e4243
AK		 2785}
2786
710ff4a8
EH		 2787
2788/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2789 * tricks.
2790 */
2791static void kvm_cpu_vmxoff(void)
6aa8b732 2792{
4ecac3fd 2793 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2794}
2795
13a34e06 2796static void hardware_disable(void)
710ff4a8 2797{
4610c9cc 2798 if (vmm_exclusive) {
d462b819 2799 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2800 kvm_cpu_vmxoff();
2801 }
7725b894 2802 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2803}
2804
1c3d14fe 2805static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2806 u32 msr, u32 *result)
1c3d14fe
YS		 2807{
2808 u32 vmx_msr_low, vmx_msr_high;
2809 u32 ctl = ctl_min | ctl_opt;
2810
2811 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2812
2813 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2814 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2815
2816 /* Ensure minimum (required) set of control bits are supported. */
2817 if (ctl_min & ~ctl)
002c7f7c 2818 return -EIO;
1c3d14fe
YS		 2819
2820 *result = ctl;
2821 return 0;
2822}
2823
110312c8
AK		 2824static __init bool allow_1_setting(u32 msr, u32 ctl)
2825{
2826 u32 vmx_msr_low, vmx_msr_high;
2827
2828 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2829 return vmx_msr_high & ctl;
2830}
2831
002c7f7c 2832static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2833{
2834 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2835 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2836 u32 _pin_based_exec_control = 0;
2837 u32 _cpu_based_exec_control = 0;
f78e0e2e 2838 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2839 u32 _vmexit_control = 0;
2840 u32 _vmentry_control = 0;
2841
10166744 2842 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2843#ifdef CONFIG_X86_64
2844 CPU_BASED_CR8_LOAD_EXITING |
2845 CPU_BASED_CR8_STORE_EXITING |
2846#endif
d56f546d
SY		 2847 CPU_BASED_CR3_LOAD_EXITING |
2848 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2849 CPU_BASED_USE_IO_BITMAPS |
2850 CPU_BASED_MOV_DR_EXITING |
a7052897 2851 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2852 CPU_BASED_MWAIT_EXITING |
2853 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2854 CPU_BASED_INVLPG_EXITING |
2855 CPU_BASED_RDPMC_EXITING;
443381a8 2856
f78e0e2e 2857 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2858 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2859 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2860 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2861 &_cpu_based_exec_control) < 0)
002c7f7c 2862 return -EIO;
6e5d865c
YS		 2863#ifdef CONFIG_X86_64
2864 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2865 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2866 ~CPU_BASED_CR8_STORE_EXITING;
2867#endif
f78e0e2e 2868 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2869 min2 = 0;
2870 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2871 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2872 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2873 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2874 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2875 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2876 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2877 SECONDARY_EXEC_RDTSCP |
83d4c286 2878 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2879 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2880 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2881 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2882 if (adjust_vmx_controls(min2, opt2,
2883 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2884 &_cpu_based_2nd_exec_control) < 0)
2885 return -EIO;
2886 }
2887#ifndef CONFIG_X86_64
2888 if (!(_cpu_based_2nd_exec_control &
2889 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2890 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2891#endif
83d4c286
YZ		 2892
2893 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2894 _cpu_based_2nd_exec_control &= ~(
8d14695f 2895 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2896 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2897 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2898
d56f546d 2899 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2900 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2901 enabled */
5fff7d27
GN		 2902 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2903 CPU_BASED_CR3_STORE_EXITING |
2904 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2905 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2906 vmx_capability.ept, vmx_capability.vpid);
2907 }
1c3d14fe 2908
81908bf4 2909 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2910#ifdef CONFIG_X86_64
2911 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2912#endif
a547c6db 2913 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2914 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2915 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2916 &_vmexit_control) < 0)
002c7f7c 2917 return -EIO;
1c3d14fe 2918
01e439be
YZ		 2919 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2920 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2921 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2922 &_pin_based_exec_control) < 0)
2923 return -EIO;
2924
2925 if (!(_cpu_based_2nd_exec_control &
2926 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2927 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2928 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2929
c845f9c6 2930 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2931 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2932 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2933 &_vmentry_control) < 0)
002c7f7c 2934 return -EIO;
6aa8b732 2935
c68876fd 2936 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2937
2938 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2939 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2940 return -EIO;
1c3d14fe
YS		 2941
2942#ifdef CONFIG_X86_64
2943 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2944 if (vmx_msr_high & (1u<<16))
002c7f7c 2945 return -EIO;
1c3d14fe
YS		 2946#endif
2947
2948 /* Require Write-Back (WB) memory type for VMCS accesses. */
2949 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2950 return -EIO;
1c3d14fe 2951
002c7f7c
YS		 2952 vmcs_conf->size = vmx_msr_high & 0x1fff;
2953 vmcs_conf->order = get_order(vmcs_config.size);
2954 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2955
002c7f7c
YS		 2956 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2957 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2958 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2959 vmcs_conf->vmexit_ctrl = _vmexit_control;
2960 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2961
110312c8
AK		 2962 cpu_has_load_ia32_efer =
2963 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2964 VM_ENTRY_LOAD_IA32_EFER)
2965 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2966 VM_EXIT_LOAD_IA32_EFER);
2967
8bf00a52
GN		 2968 cpu_has_load_perf_global_ctrl =
2969 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2970 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2971 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2972 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2973
2974 /*
2975 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2976 * but due to arrata below it can't be used. Workaround is to use
2977 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2978 *
2979 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2980 *
2981 * AAK155 (model 26)
2982 * AAP115 (model 30)
2983 * AAT100 (model 37)
2984 * BC86,AAY89,BD102 (model 44)
2985 * BA97 (model 46)
2986 *
2987 */
2988 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2989 switch (boot_cpu_data.x86_model) {
2990 case 26:
2991 case 30:
2992 case 37:
2993 case 44:
2994 case 46:
2995 cpu_has_load_perf_global_ctrl = false;
2996 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2997 "does not work properly. Using workaround\n");
2998 break;
2999 default:
3000 break;
3001 }
3002 }
3003
1c3d14fe 3004 return 0;
c68876fd 3005}
6aa8b732
AK		 3006
3007static struct vmcs *alloc_vmcs_cpu(int cpu)
3008{
3009 int node = cpu_to_node(cpu);
3010 struct page *pages;
3011 struct vmcs *vmcs;
3012
6484eb3e 3013 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3014 if (!pages)
3015 return NULL;
3016 vmcs = page_address(pages);
1c3d14fe
YS		 3017 memset(vmcs, 0, vmcs_config.size);
3018 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3019 return vmcs;
3020}
3021
3022static struct vmcs *alloc_vmcs(void)
3023{
d3b2c338 3024 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3025}
3026
3027static void free_vmcs(struct vmcs *vmcs)
3028{
1c3d14fe 3029 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3030}
3031
d462b819
NHE		 3032/*
3033 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3034 */
3035static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3036{
3037 if (!loaded_vmcs->vmcs)
3038 return;
3039 loaded_vmcs_clear(loaded_vmcs);
3040 free_vmcs(loaded_vmcs->vmcs);
3041 loaded_vmcs->vmcs = NULL;
3042}
3043
39959588 3044static void free_kvm_area(void)
6aa8b732
AK		 3045{
3046 int cpu;
3047
3230bb47 3048 for_each_possible_cpu(cpu) {
6aa8b732 3049 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3050 per_cpu(vmxarea, cpu) = NULL;
3051 }
6aa8b732
AK		 3052}
3053
fe2b201b
BD		 3054static void init_vmcs_shadow_fields(void)
3055{
3056 int i, j;
3057
3058 /* No checks for read only fields yet */
3059
3060 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3061 switch (shadow_read_write_fields[i]) {
3062 case GUEST_BNDCFGS:
3063 if (!vmx_mpx_supported())
3064 continue;
3065 break;
3066 default:
3067 break;
3068 }
3069
3070 if (j < i)
3071 shadow_read_write_fields[j] =
3072 shadow_read_write_fields[i];
3073 j++;
3074 }
3075 max_shadow_read_write_fields = j;
3076
3077 /* shadowed fields guest access without vmexit */
3078 for (i = 0; i < max_shadow_read_write_fields; i++) {
3079 clear_bit(shadow_read_write_fields[i],
3080 vmx_vmwrite_bitmap);
3081 clear_bit(shadow_read_write_fields[i],
3082 vmx_vmread_bitmap);
3083 }
3084 for (i = 0; i < max_shadow_read_only_fields; i++)
3085 clear_bit(shadow_read_only_fields[i],
3086 vmx_vmread_bitmap);
3087}
3088
6aa8b732
AK		 3089static __init int alloc_kvm_area(void)
3090{
3091 int cpu;
3092
3230bb47 3093 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3094 struct vmcs *vmcs;
3095
3096 vmcs = alloc_vmcs_cpu(cpu);
3097 if (!vmcs) {
3098 free_kvm_area();
3099 return -ENOMEM;
3100 }
3101
3102 per_cpu(vmxarea, cpu) = vmcs;
3103 }
3104 return 0;
3105}
3106
3107static __init int hardware_setup(void)
3108{
002c7f7c
YS		 3109 if (setup_vmcs_config(&vmcs_config) < 0)
3110 return -EIO;
50a37eb4
JR		 3111
3112 if (boot_cpu_has(X86_FEATURE_NX))
3113 kvm_enable_efer_bits(EFER_NX);
3114
93ba03c2
SY		 3115 if (!cpu_has_vmx_vpid())
3116 enable_vpid = 0;
abc4fc58
AG		 3117 if (!cpu_has_vmx_shadow_vmcs())
3118 enable_shadow_vmcs = 0;
fe2b201b
BD		 3119 if (enable_shadow_vmcs)
3120 init_vmcs_shadow_fields();
93ba03c2 3121
4bc9b982
SY		 3122 if (!cpu_has_vmx_ept() ||
3123 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3124 enable_ept = 0;
3a624e29 3125 enable_unrestricted_guest = 0;
83c3a331 3126 enable_ept_ad_bits = 0;
3a624e29
NK		 3127 }
3128
83c3a331
XH		 3129 if (!cpu_has_vmx_ept_ad_bits())
3130 enable_ept_ad_bits = 0;
3131
3a624e29
NK		 3132 if (!cpu_has_vmx_unrestricted_guest())
3133 enable_unrestricted_guest = 0;
93ba03c2
SY		 3134
3135 if (!cpu_has_vmx_flexpriority())
3136 flexpriority_enabled = 0;
3137
95ba8273
GN		 3138 if (!cpu_has_vmx_tpr_shadow())
3139 kvm_x86_ops->update_cr8_intercept = NULL;
3140
54dee993
MT		 3141 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3142 kvm_disable_largepages();
3143
4b8d54f9
ZE		 3144 if (!cpu_has_vmx_ple())
3145 ple_gap = 0;
3146
01e439be
YZ		 3147 if (!cpu_has_vmx_apicv())
3148 enable_apicv = 0;
c7c9c56c 3149
01e439be 3150 if (enable_apicv)
c7c9c56c 3151 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3152 else {
c7c9c56c 3153 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3154 kvm_x86_ops->deliver_posted_interrupt = NULL;
3155 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3156 }
83d4c286 3157
b87a51ae
NHE		 3158 if (nested)
3159 nested_vmx_setup_ctls_msrs();
3160
6aa8b732
AK		 3161 return alloc_kvm_area();
3162}
3163
3164static __exit void hardware_unsetup(void)
3165{
3166 free_kvm_area();
3167}
3168
14168786
GN		 3169static bool emulation_required(struct kvm_vcpu *vcpu)
3170{
3171 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3172}
3173
91b0aa2c 3174static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3175 struct kvm_segment *save)
6aa8b732 3176{
d99e4152
GN		 3177 if (!emulate_invalid_guest_state) {
3178 /*
3179 * CS and SS RPL should be equal during guest entry according
3180 * to VMX spec, but in reality it is not always so. Since vcpu
3181 * is in the middle of the transition from real mode to
3182 * protected mode it is safe to assume that RPL 0 is a good
3183 * default value.
3184 */
3185 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3186 save->selector &= ~SELECTOR_RPL_MASK;
3187 save->dpl = save->selector & SELECTOR_RPL_MASK;
3188 save->s = 1;
6aa8b732 3189 }
d99e4152 3190 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3191}
3192
3193static void enter_pmode(struct kvm_vcpu *vcpu)
3194{
3195 unsigned long flags;
a89a8fb9 3196 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3197
d99e4152
GN		 3198 /*
3199 * Update real mode segment cache. It may be not up-to-date if sement
3200 * register was written while vcpu was in a guest mode.
3201 */
3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3203 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3204 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3205 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3206 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3207 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3208
7ffd92c5 3209 vmx->rmode.vm86_active = 0;
6aa8b732 3210
2fb92db1
AK		 3211 vmx_segment_cache_clear(vmx);
3212
f5f7b2fe 3213 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3214
3215 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3216 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3217 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3218 vmcs_writel(GUEST_RFLAGS, flags);
3219
66aee91a
RR		 3220 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3221 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3222
3223 update_exception_bitmap(vcpu);
3224
91b0aa2c
GN		 3225 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3226 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3227 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3228 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3229 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3230 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3231}
3232
f5f7b2fe 3233static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3234{
772e0318 3235 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3236 struct kvm_segment var = *save;
3237
3238 var.dpl = 0x3;
3239 if (seg == VCPU_SREG_CS)
3240 var.type = 0x3;
3241
3242 if (!emulate_invalid_guest_state) {
3243 var.selector = var.base >> 4;
3244 var.base = var.base & 0xffff0;
3245 var.limit = 0xffff;
3246 var.g = 0;
3247 var.db = 0;
3248 var.present = 1;
3249 var.s = 1;
3250 var.l = 0;
3251 var.unusable = 0;
3252 var.type = 0x3;
3253 var.avl = 0;
3254 if (save->base & 0xf)
3255 printk_once(KERN_WARNING "kvm: segment base is not "
3256 "paragraph aligned when entering "
3257 "protected mode (seg=%d)", seg);
3258 }
6aa8b732 3259
d99e4152
GN		 3260 vmcs_write16(sf->selector, var.selector);
3261 vmcs_write32(sf->base, var.base);
3262 vmcs_write32(sf->limit, var.limit);
3263 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3264}
3265
3266static void enter_rmode(struct kvm_vcpu *vcpu)
3267{
3268 unsigned long flags;
a89a8fb9 3269 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3270
f5f7b2fe
AK		 3271 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3272 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3273 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3274 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3275 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3276 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3277 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3278
7ffd92c5 3279 vmx->rmode.vm86_active = 1;
6aa8b732 3280
776e58ea
GN		 3281 /*
3282 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3283 * vcpu. Warn the user that an update is overdue.
776e58ea 3284 */
4918c6ca 3285 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3286 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3287 "called before entering vcpu\n");
776e58ea 3288
2fb92db1
AK		 3289 vmx_segment_cache_clear(vmx);
3290
4918c6ca 3291 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3292 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3293 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3294
3295 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3296 vmx->rmode.save_rflags = flags;
6aa8b732 3297
053de044 3298 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3299
3300 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3301 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3302 update_exception_bitmap(vcpu);
3303
d99e4152
GN		 3304 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3305 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3306 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3307 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3308 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3309 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3310
8668a3c4 3311 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3312}
3313
401d10de
AS		 3314static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3315{
3316 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3317 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3318
3319 if (!msr)
3320 return;
401d10de 3321
44ea2b17
AK		 3322 /*
3323 * Force kernel_gs_base reloading before EFER changes, as control
3324 * of this msr depends on is_long_mode().
3325 */
3326 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3327 vcpu->arch.efer = efer;
401d10de 3328 if (efer & EFER_LMA) {
2961e876 3329 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3330 msr->data = efer;
3331 } else {
2961e876 3332 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3333
3334 msr->data = efer & ~EFER_LME;
3335 }
3336 setup_msrs(vmx);
3337}
3338
05b3e0c2 3339#ifdef CONFIG_X86_64
6aa8b732
AK		 3340
3341static void enter_lmode(struct kvm_vcpu *vcpu)
3342{
3343 u32 guest_tr_ar;
3344
2fb92db1
AK		 3345 vmx_segment_cache_clear(to_vmx(vcpu));
3346
6aa8b732
AK		 3347 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3348 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3349 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3350 __func__);
6aa8b732
AK		 3351 vmcs_write32(GUEST_TR_AR_BYTES,
3352 (guest_tr_ar & ~AR_TYPE_MASK)
3353 | AR_TYPE_BUSY_64_TSS);
3354 }
da38f438 3355 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3356}
3357
3358static void exit_lmode(struct kvm_vcpu *vcpu)
3359{
2961e876 3360 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3361 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3362}
3363
3364#endif
3365
2384d2b3
SY		 3366static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3367{
b9d762fa 3368 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3369 if (enable_ept) {
3370 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3371 return;
4e1096d2 3372 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3373 }
2384d2b3
SY		 3374}
3375
e8467fda
AK		 3376static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3377{
3378 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3379
3380 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3381 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3382}
3383
aff48baa
AK		 3384static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3385{
3386 if (enable_ept && is_paging(vcpu))
3387 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3388 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3389}
3390
25c4c276 3391static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3392{
fc78f519
AK		 3393 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3394
3395 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3396 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3397}
3398
1439442c
SY		 3399static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3400{
d0d538b9
GN		 3401 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3402
6de4f3ad
AK		 3403 if (!test_bit(VCPU_EXREG_PDPTR,
3404 (unsigned long *)&vcpu->arch.regs_dirty))
3405 return;
3406
1439442c 3407 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3408 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3409 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3410 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3411 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3412 }
3413}
3414
8f5d549f
AK		 3415static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3416{
d0d538b9
GN		 3417 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3418
8f5d549f 3419 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3420 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3421 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3422 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3423 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3424 }
6de4f3ad
AK		 3425
3426 __set_bit(VCPU_EXREG_PDPTR,
3427 (unsigned long *)&vcpu->arch.regs_avail);
3428 __set_bit(VCPU_EXREG_PDPTR,
3429 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3430}
3431
5e1746d6 3432static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3433
3434static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3435 unsigned long cr0,
3436 struct kvm_vcpu *vcpu)
3437{
5233dd51
MT		 3438 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3439 vmx_decache_cr3(vcpu);
1439442c
SY		 3440 if (!(cr0 & X86_CR0_PG)) {
3441 /* From paging/starting to nonpaging */
3442 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3443 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3444 (CPU_BASED_CR3_LOAD_EXITING |
3445 CPU_BASED_CR3_STORE_EXITING));
3446 vcpu->arch.cr0 = cr0;
fc78f519 3447 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3448 } else if (!is_paging(vcpu)) {
3449 /* From nonpaging to paging */
3450 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3451 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3452 ~(CPU_BASED_CR3_LOAD_EXITING |
3453 CPU_BASED_CR3_STORE_EXITING));
3454 vcpu->arch.cr0 = cr0;
fc78f519 3455 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3456 }
95eb84a7
SY		 3457
3458 if (!(cr0 & X86_CR0_WP))
3459 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3460}
3461
6aa8b732
AK		 3462static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3463{
7ffd92c5 3464 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3465 unsigned long hw_cr0;
3466
5037878e 3467 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3468 if (enable_unrestricted_guest)
5037878e 3469 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3470 else {
5037878e 3471 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3472
218e763f
GN		 3473 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3474 enter_pmode(vcpu);
6aa8b732 3475
218e763f
GN		 3476 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3477 enter_rmode(vcpu);
3478 }
6aa8b732 3479
05b3e0c2 3480#ifdef CONFIG_X86_64
f6801dff 3481 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3482 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3483 enter_lmode(vcpu);
707d92fa 3484 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3485 exit_lmode(vcpu);
3486 }
3487#endif
3488
089d034e 3489 if (enable_ept)
1439442c
SY		 3490 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3491
02daab21 3492 if (!vcpu->fpu_active)
81231c69 3493 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3494
6aa8b732 3495 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3496 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3497 vcpu->arch.cr0 = cr0;
14168786
GN		 3498
3499 /* depends on vcpu->arch.cr0 to be set to a new value */
3500 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3501}
3502
1439442c
SY		 3503static u64 construct_eptp(unsigned long root_hpa)
3504{
3505 u64 eptp;
3506
3507 /* TODO write the value reading from MSR */
3508 eptp = VMX_EPT_DEFAULT_MT |
3509 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3510 if (enable_ept_ad_bits)
3511 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3512 eptp |= (root_hpa & PAGE_MASK);
3513
3514 return eptp;
3515}
3516
6aa8b732
AK		 3517static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3518{
1439442c
SY		 3519 unsigned long guest_cr3;
3520 u64 eptp;
3521
3522 guest_cr3 = cr3;
089d034e 3523 if (enable_ept) {
1439442c
SY		 3524 eptp = construct_eptp(cr3);
3525 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3526 if (is_paging(vcpu) || is_guest_mode(vcpu))
3527 guest_cr3 = kvm_read_cr3(vcpu);
3528 else
3529 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3530 ept_load_pdptrs(vcpu);
1439442c
SY		 3531 }
3532
2384d2b3 3533 vmx_flush_tlb(vcpu);
1439442c 3534 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3535}
3536
5e1746d6 3537static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3538{
7ffd92c5 3539 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3540 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3541
5e1746d6
NHE		 3542 if (cr4 & X86_CR4_VMXE) {
3543 /*
3544 * To use VMXON (and later other VMX instructions), a guest
3545 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3546 * So basically the check on whether to allow nested VMX
3547 * is here.
3548 */
3549 if (!nested_vmx_allowed(vcpu))
3550 return 1;
1a0d74e6
JK		 3551 }
3552 if (to_vmx(vcpu)->nested.vmxon &&
3553 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3554 return 1;
3555
ad312c7c 3556 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3557 if (enable_ept) {
3558 if (!is_paging(vcpu)) {
3559 hw_cr4 &= ~X86_CR4_PAE;
3560 hw_cr4 |= X86_CR4_PSE;
c08800a5 3561 /*
e1e746b3
FW		 3562 * SMEP/SMAP is disabled if CPU is in non-paging mode
3563 * in hardware. However KVM always uses paging mode to
c08800a5 3564 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3565 * To emulate this behavior, SMEP/SMAP needs to be
3566 * manually disabled when guest switches to non-paging
3567 * mode.
c08800a5 3568 */
e1e746b3 3569 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3570 } else if (!(cr4 & X86_CR4_PAE)) {
3571 hw_cr4 &= ~X86_CR4_PAE;
3572 }
3573 }
1439442c
SY		 3574
3575 vmcs_writel(CR4_READ_SHADOW, cr4);
3576 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3577 return 0;
6aa8b732
AK		 3578}
3579
6aa8b732
AK		 3580static void vmx_get_segment(struct kvm_vcpu *vcpu,
3581 struct kvm_segment *var, int seg)
3582{
a9179499 3583 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3584 u32 ar;
3585
c6ad1153 3586 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3587 *var = vmx->rmode.segs[seg];
a9179499 3588 if (seg == VCPU_SREG_TR
2fb92db1 3589 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3590 return;
1390a28b
AK		 3591 var->base = vmx_read_guest_seg_base(vmx, seg);
3592 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3593 return;
a9179499 3594 }
2fb92db1
AK		 3595 var->base = vmx_read_guest_seg_base(vmx, seg);
3596 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3597 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3598 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3599 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3600 var->type = ar & 15;
3601 var->s = (ar >> 4) & 1;
3602 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3603 /*
3604 * Some userspaces do not preserve unusable property. Since usable
3605 * segment has to be present according to VMX spec we can use present
3606 * property to amend userspace bug by making unusable segment always
3607 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3608 * segment as unusable.
3609 */
3610 var->present = !var->unusable;
6aa8b732
AK		 3611 var->avl = (ar >> 12) & 1;
3612 var->l = (ar >> 13) & 1;
3613 var->db = (ar >> 14) & 1;
3614 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3615}
3616
a9179499
AK		 3617static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3618{
a9179499
AK		 3619 struct kvm_segment s;
3620
3621 if (to_vmx(vcpu)->rmode.vm86_active) {
3622 vmx_get_segment(vcpu, &s, seg);
3623 return s.base;
3624 }
2fb92db1 3625 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3626}
3627
b09408d0 3628static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3629{
b09408d0
MT		 3630 struct vcpu_vmx *vmx = to_vmx(vcpu);
3631
ae9fedc7 3632 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3633 return 0;
ae9fedc7
PB		 3634 else {
3635 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3636 return AR_DPL(ar);
69c73028 3637 }
69c73028
AK		 3638}
3639
653e3108 3640static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3641{
6aa8b732
AK		 3642 u32 ar;
3643
f0495f9b 3644 if (var->unusable || !var->present)
6aa8b732
AK		 3645 ar = 1 << 16;
3646 else {
3647 ar = var->type & 15;
3648 ar |= (var->s & 1) << 4;
3649 ar |= (var->dpl & 3) << 5;
3650 ar |= (var->present & 1) << 7;
3651 ar |= (var->avl & 1) << 12;
3652 ar |= (var->l & 1) << 13;
3653 ar |= (var->db & 1) << 14;
3654 ar |= (var->g & 1) << 15;
3655 }
653e3108
AK		 3656
3657 return ar;
3658}
3659
3660static void vmx_set_segment(struct kvm_vcpu *vcpu,
3661 struct kvm_segment *var, int seg)
3662{
7ffd92c5 3663 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3664 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3665
2fb92db1
AK		 3666 vmx_segment_cache_clear(vmx);
3667
1ecd50a9
GN		 3668 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3669 vmx->rmode.segs[seg] = *var;
3670 if (seg == VCPU_SREG_TR)
3671 vmcs_write16(sf->selector, var->selector);
3672 else if (var->s)
3673 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3674 goto out;
653e3108 3675 }
1ecd50a9 3676
653e3108
AK		 3677 vmcs_writel(sf->base, var->base);
3678 vmcs_write32(sf->limit, var->limit);
3679 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3680
3681 /*
3682 * Fix the "Accessed" bit in AR field of segment registers for older
3683 * qemu binaries.
3684 * IA32 arch specifies that at the time of processor reset the
3685 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3686 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3687 * state vmexit when "unrestricted guest" mode is turned on.
3688 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3689 * tree. Newer qemu binaries with that qemu fix would not need this
3690 * kvm hack.
3691 */
3692 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3693 var->type |= 0x1; /* Accessed */
3a624e29 3694
f924d66d 3695 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3696
3697out:
98eb2f8b 3698 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3699}
3700
6aa8b732
AK		 3701static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3702{
2fb92db1 3703 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3704
3705 *db = (ar >> 14) & 1;
3706 *l = (ar >> 13) & 1;
3707}
3708
89a27f4d 3709static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3710{
89a27f4d
GN		 3711 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3712 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3713}
3714
89a27f4d 3715static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3716{
89a27f4d
GN		 3717 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3718 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3719}
3720
89a27f4d 3721static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3722{
89a27f4d
GN		 3723 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3724 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3725}
3726
89a27f4d 3727static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3728{
89a27f4d
GN		 3729 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3730 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3731}
3732
648dfaa7
MG		 3733static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3734{
3735 struct kvm_segment var;
3736 u32 ar;
3737
3738 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3739 var.dpl = 0x3;
0647f4aa
GN		 3740 if (seg == VCPU_SREG_CS)
3741 var.type = 0x3;
648dfaa7
MG		 3742 ar = vmx_segment_access_rights(&var);
3743
3744 if (var.base != (var.selector << 4))
3745 return false;
89efbed0 3746 if (var.limit != 0xffff)
648dfaa7 3747 return false;
07f42f5f 3748 if (ar != 0xf3)
648dfaa7
MG		 3749 return false;
3750
3751 return true;
3752}
3753
3754static bool code_segment_valid(struct kvm_vcpu *vcpu)
3755{
3756 struct kvm_segment cs;
3757 unsigned int cs_rpl;
3758
3759 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3760 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3761
1872a3f4
AK		 3762 if (cs.unusable)
3763 return false;
648dfaa7
MG		 3764 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3765 return false;
3766 if (!cs.s)
3767 return false;
1872a3f4 3768 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3769 if (cs.dpl > cs_rpl)
3770 return false;
1872a3f4 3771 } else {
648dfaa7
MG		 3772 if (cs.dpl != cs_rpl)
3773 return false;
3774 }
3775 if (!cs.present)
3776 return false;
3777
3778 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3779 return true;
3780}
3781
3782static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3783{
3784 struct kvm_segment ss;
3785 unsigned int ss_rpl;
3786
3787 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3788 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3789
1872a3f4
AK		 3790 if (ss.unusable)
3791 return true;
3792 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3793 return false;
3794 if (!ss.s)
3795 return false;
3796 if (ss.dpl != ss_rpl) /* DPL != RPL */
3797 return false;
3798 if (!ss.present)
3799 return false;
3800
3801 return true;
3802}
3803
3804static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3805{
3806 struct kvm_segment var;
3807 unsigned int rpl;
3808
3809 vmx_get_segment(vcpu, &var, seg);
3810 rpl = var.selector & SELECTOR_RPL_MASK;
3811
1872a3f4
AK		 3812 if (var.unusable)
3813 return true;
648dfaa7
MG		 3814 if (!var.s)
3815 return false;
3816 if (!var.present)
3817 return false;
3818 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3819 if (var.dpl < rpl) /* DPL < RPL */
3820 return false;
3821 }
3822
3823 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3824 * rights flags
3825 */
3826 return true;
3827}
3828
3829static bool tr_valid(struct kvm_vcpu *vcpu)
3830{
3831 struct kvm_segment tr;
3832
3833 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3834
1872a3f4
AK		 3835 if (tr.unusable)
3836 return false;
648dfaa7
MG		 3837 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3838 return false;
1872a3f4 3839 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3840 return false;
3841 if (!tr.present)
3842 return false;
3843
3844 return true;
3845}
3846
3847static bool ldtr_valid(struct kvm_vcpu *vcpu)
3848{
3849 struct kvm_segment ldtr;
3850
3851 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3852
1872a3f4
AK		 3853 if (ldtr.unusable)
3854 return true;
648dfaa7
MG		 3855 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3856 return false;
3857 if (ldtr.type != 2)
3858 return false;
3859 if (!ldtr.present)
3860 return false;
3861
3862 return true;
3863}
3864
3865static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3866{
3867 struct kvm_segment cs, ss;
3868
3869 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3870 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3871
3872 return ((cs.selector & SELECTOR_RPL_MASK) ==
3873 (ss.selector & SELECTOR_RPL_MASK));
3874}
3875
3876/*
3877 * Check if guest state is valid. Returns true if valid, false if
3878 * not.
3879 * We assume that registers are always usable
3880 */
3881static bool guest_state_valid(struct kvm_vcpu *vcpu)
3882{
c5e97c80
GN		 3883 if (enable_unrestricted_guest)
3884 return true;
3885
648dfaa7 3886 /* real mode guest state checks */
f13882d8 3887 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3888 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3889 return false;
3890 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3891 return false;
3892 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3893 return false;
3894 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3895 return false;
3896 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3897 return false;
3898 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3899 return false;
3900 } else {
3901 /* protected mode guest state checks */
3902 if (!cs_ss_rpl_check(vcpu))
3903 return false;
3904 if (!code_segment_valid(vcpu))
3905 return false;
3906 if (!stack_segment_valid(vcpu))
3907 return false;
3908 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3909 return false;
3910 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3911 return false;
3912 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3913 return false;
3914 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3915 return false;
3916 if (!tr_valid(vcpu))
3917 return false;
3918 if (!ldtr_valid(vcpu))
3919 return false;
3920 }
3921 /* TODO:
3922 * - Add checks on RIP
3923 * - Add checks on RFLAGS
3924 */
3925
3926 return true;
3927}
3928
d77c26fc 3929static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3930{
40dcaa9f 3931 gfn_t fn;
195aefde 3932 u16 data = 0;
40dcaa9f 3933 int r, idx, ret = 0;
6aa8b732 3934
40dcaa9f 3935 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3936 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3937 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3938 if (r < 0)
10589a46 3939 goto out;
195aefde 3940 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3941 r = kvm_write_guest_page(kvm, fn++, &data,
3942 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3943 if (r < 0)
10589a46 3944 goto out;
195aefde
IE		 3945 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3946 if (r < 0)
10589a46 3947 goto out;
195aefde
IE		 3948 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3949 if (r < 0)
10589a46 3950 goto out;
195aefde 3951 data = ~0;
10589a46
MT		 3952 r = kvm_write_guest_page(kvm, fn, &data,
3953 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3954 sizeof(u8));
195aefde 3955 if (r < 0)
10589a46
MT		 3956 goto out;
3957
3958 ret = 1;
3959out:
40dcaa9f 3960 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3961 return ret;
6aa8b732
AK		 3962}
3963
b7ebfb05
SY		 3964static int init_rmode_identity_map(struct kvm *kvm)
3965{
f51770ed 3966 int i, idx, r = 0;
b7ebfb05
SY		 3967 pfn_t identity_map_pfn;
3968 u32 tmp;
3969
089d034e 3970 if (!enable_ept)
f51770ed 3971 return 0;
a255d479
TC		 3972
3973 /* Protect kvm->arch.ept_identity_pagetable_done. */
3974 mutex_lock(&kvm->slots_lock);
3975
f51770ed 3976 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3977 goto out2;
a255d479 3978
b927a3ce 3979 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3980
3981 r = alloc_identity_pagetable(kvm);
f51770ed 3982 if (r < 0)
a255d479
TC		 3983 goto out2;
3984
40dcaa9f 3985 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3986 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3987 if (r < 0)
3988 goto out;
3989 /* Set up identity-mapping pagetable for EPT in real mode */
3990 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3991 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3992 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3993 r = kvm_write_guest_page(kvm, identity_map_pfn,
3994 &tmp, i * sizeof(tmp), sizeof(tmp));
3995 if (r < 0)
3996 goto out;
3997 }
3998 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3999
b7ebfb05 4000out:
40dcaa9f 4001 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4002
4003out2:
4004 mutex_unlock(&kvm->slots_lock);
f51770ed 4005 return r;
b7ebfb05
SY		 4006}
4007
6aa8b732
AK		 4008static void seg_setup(int seg)
4009{
772e0318 4010 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4011 unsigned int ar;
6aa8b732
AK		 4012
4013 vmcs_write16(sf->selector, 0);
4014 vmcs_writel(sf->base, 0);
4015 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4016 ar = 0x93;
4017 if (seg == VCPU_SREG_CS)
4018 ar |= 0x08; /* code segment */
3a624e29
NK		 4019
4020 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4021}
4022
f78e0e2e
SY		 4023static int alloc_apic_access_page(struct kvm *kvm)
4024{
4484141a 4025 struct page *page;
f78e0e2e
SY		 4026 struct kvm_userspace_memory_region kvm_userspace_mem;
4027 int r = 0;
4028
79fac95e 4029 mutex_lock(&kvm->slots_lock);
bfc6d222 4030 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4031 goto out;
4032 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4033 kvm_userspace_mem.flags = 0;
73a6d941 4034 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4035 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4036 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4037 if (r)
4038 goto out;
72dc67a6 4039
73a6d941 4040 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4041 if (is_error_page(page)) {
4042 r = -EFAULT;
4043 goto out;
4044 }
4045
4046 kvm->arch.apic_access_page = page;
f78e0e2e 4047out:
79fac95e 4048 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4049 return r;
4050}
4051
b7ebfb05
SY		 4052static int alloc_identity_pagetable(struct kvm *kvm)
4053{
a255d479
TC		 4054 /* Called with kvm->slots_lock held. */
4055
b7ebfb05
SY		 4056 struct kvm_userspace_memory_region kvm_userspace_mem;
4057 int r = 0;
4058
a255d479
TC		 4059 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4060
b7ebfb05
SY		 4061 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4062 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4063 kvm_userspace_mem.guest_phys_addr =
4064 kvm->arch.ept_identity_map_addr;
b7ebfb05 4065 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4066 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4067
b7ebfb05
SY		 4068 return r;
4069}
4070
2384d2b3
SY		 4071static void allocate_vpid(struct vcpu_vmx *vmx)
4072{
4073 int vpid;
4074
4075 vmx->vpid = 0;
919818ab 4076 if (!enable_vpid)
2384d2b3
SY		 4077 return;
4078 spin_lock(&vmx_vpid_lock);
4079 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4080 if (vpid < VMX_NR_VPIDS) {
4081 vmx->vpid = vpid;
4082 __set_bit(vpid, vmx_vpid_bitmap);
4083 }
4084 spin_unlock(&vmx_vpid_lock);
4085}
4086
cdbecfc3
LJ		 4087static void free_vpid(struct vcpu_vmx *vmx)
4088{
4089 if (!enable_vpid)
4090 return;
4091 spin_lock(&vmx_vpid_lock);
4092 if (vmx->vpid != 0)
4093 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4094 spin_unlock(&vmx_vpid_lock);
4095}
4096
8d14695f
YZ		 4097#define MSR_TYPE_R 1
4098#define MSR_TYPE_W 2
4099static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4100 u32 msr, int type)
25c5f225 4101{
3e7c73e9 4102 int f = sizeof(unsigned long);
25c5f225
SY		 4103
4104 if (!cpu_has_vmx_msr_bitmap())
4105 return;
4106
4107 /*
4108 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4109 * have the write-low and read-high bitmap offsets the wrong way round.
4110 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4111 */
25c5f225 4112 if (msr <= 0x1fff) {
8d14695f
YZ		 4113 if (type & MSR_TYPE_R)
4114 /* read-low */
4115 __clear_bit(msr, msr_bitmap + 0x000 / f);
4116
4117 if (type & MSR_TYPE_W)
4118 /* write-low */
4119 __clear_bit(msr, msr_bitmap + 0x800 / f);
4120
25c5f225
SY		 4121 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4122 msr &= 0x1fff;
8d14695f
YZ		 4123 if (type & MSR_TYPE_R)
4124 /* read-high */
4125 __clear_bit(msr, msr_bitmap + 0x400 / f);
4126
4127 if (type & MSR_TYPE_W)
4128 /* write-high */
4129 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4130
4131 }
4132}
4133
4134static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4135 u32 msr, int type)
4136{
4137 int f = sizeof(unsigned long);
4138
4139 if (!cpu_has_vmx_msr_bitmap())
4140 return;
4141
4142 /*
4143 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4144 * have the write-low and read-high bitmap offsets the wrong way round.
4145 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4146 */
4147 if (msr <= 0x1fff) {
4148 if (type & MSR_TYPE_R)
4149 /* read-low */
4150 __set_bit(msr, msr_bitmap + 0x000 / f);
4151
4152 if (type & MSR_TYPE_W)
4153 /* write-low */
4154 __set_bit(msr, msr_bitmap + 0x800 / f);
4155
4156 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4157 msr &= 0x1fff;
4158 if (type & MSR_TYPE_R)
4159 /* read-high */
4160 __set_bit(msr, msr_bitmap + 0x400 / f);
4161
4162 if (type & MSR_TYPE_W)
4163 /* write-high */
4164 __set_bit(msr, msr_bitmap + 0xc00 / f);
4165
25c5f225 4166 }
25c5f225
SY		 4167}
4168
5897297b
AK		 4169static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4170{
4171 if (!longmode_only)
8d14695f
YZ		 4172 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4173 msr, MSR_TYPE_R | MSR_TYPE_W);
4174 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4175 msr, MSR_TYPE_R | MSR_TYPE_W);
4176}
4177
4178static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4179{
4180 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4181 msr, MSR_TYPE_R);
4182 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4183 msr, MSR_TYPE_R);
4184}
4185
4186static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4187{
4188 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4189 msr, MSR_TYPE_R);
4190 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4191 msr, MSR_TYPE_R);
4192}
4193
4194static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4195{
4196 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4197 msr, MSR_TYPE_W);
4198 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4199 msr, MSR_TYPE_W);
5897297b
AK		 4200}
4201
01e439be
YZ		 4202static int vmx_vm_has_apicv(struct kvm *kvm)
4203{
4204 return enable_apicv && irqchip_in_kernel(kvm);
4205}
4206
a20ed54d
YZ		 4207/*
4208 * Send interrupt to vcpu via posted interrupt way.
4209 * 1. If target vcpu is running(non-root mode), send posted interrupt
4210 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4211 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4212 * interrupt from PIR in next vmentry.
4213 */
4214static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4215{
4216 struct vcpu_vmx *vmx = to_vmx(vcpu);
4217 int r;
4218
4219 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4220 return;
4221
4222 r = pi_test_and_set_on(&vmx->pi_desc);
4223 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4224#ifdef CONFIG_SMP
a20ed54d
YZ		 4225 if (!r && (vcpu->mode == IN_GUEST_MODE))
4226 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4227 POSTED_INTR_VECTOR);
4228 else
6ffbbbba 4229#endif
a20ed54d
YZ		 4230 kvm_vcpu_kick(vcpu);
4231}
4232
4233static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4234{
4235 struct vcpu_vmx *vmx = to_vmx(vcpu);
4236
4237 if (!pi_test_and_clear_on(&vmx->pi_desc))
4238 return;
4239
4240 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4241}
4242
4243static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4244{
4245 return;
4246}
4247
a3a8ff8e
NHE		 4248/*
4249 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4250 * will not change in the lifetime of the guest.
4251 * Note that host-state that does change is set elsewhere. E.g., host-state
4252 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4253 */
a547c6db 4254static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4255{
4256 u32 low32, high32;
4257 unsigned long tmpl;
4258 struct desc_ptr dt;
4259
b1a74bf8 4260 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4261 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4262 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4263
4264 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4265#ifdef CONFIG_X86_64
4266 /*
4267 * Load null selectors, so we can avoid reloading them in
4268 * __vmx_load_host_state(), in case userspace uses the null selectors
4269 * too (the expected case).
4270 */
4271 vmcs_write16(HOST_DS_SELECTOR, 0);
4272 vmcs_write16(HOST_ES_SELECTOR, 0);
4273#else
a3a8ff8e
NHE		 4274 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4275 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4276#endif
a3a8ff8e
NHE		 4277 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4278 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4279
4280 native_store_idt(&dt);
4281 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4282 vmx->host_idt_base = dt.address;
a3a8ff8e 4283
83287ea4 4284 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4285
4286 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4287 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4288 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4289 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4290
4291 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4292 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4293 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4294 }
4295}
4296
bf8179a0
NHE		 4297static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4298{
4299 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4300 if (enable_ept)
4301 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4302 if (is_guest_mode(&vmx->vcpu))
4303 vmx->vcpu.arch.cr4_guest_owned_bits &=
4304 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4305 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4306}
4307
01e439be
YZ		 4308static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4309{
4310 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4311
4312 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4313 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4314 return pin_based_exec_ctrl;
4315}
4316
bf8179a0
NHE		 4317static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4318{
4319 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4320
4321 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4322 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4323
bf8179a0
NHE		 4324 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4325 exec_control &= ~CPU_BASED_TPR_SHADOW;
4326#ifdef CONFIG_X86_64
4327 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4328 CPU_BASED_CR8_LOAD_EXITING;
4329#endif
4330 }
4331 if (!enable_ept)
4332 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4333 CPU_BASED_CR3_LOAD_EXITING |
4334 CPU_BASED_INVLPG_EXITING;
4335 return exec_control;
4336}
4337
4338static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4339{
4340 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4341 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4342 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4343 if (vmx->vpid == 0)
4344 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4345 if (!enable_ept) {
4346 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4347 enable_unrestricted_guest = 0;
ad756a16
MJ		 4348 /* Enable INVPCID for non-ept guests may cause performance regression. */
4349 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4350 }
4351 if (!enable_unrestricted_guest)
4352 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4353 if (!ple_gap)
4354 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4355 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4356 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4357 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4358 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4359 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4360 (handle_vmptrld).
4361 We can NOT enable shadow_vmcs here because we don't have yet
4362 a current VMCS12
4363 */
4364 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4365 return exec_control;
4366}
4367
ce88decf
XG		 4368static void ept_set_mmio_spte_mask(void)
4369{
4370 /*
4371 * EPT Misconfigurations can be generated if the value of bits 2:0
4372 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4373 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4374 * spte.
4375 */
885032b9 4376 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4377}
4378
6aa8b732
AK		 4379/*
4380 * Sets up the vmcs for emulated real mode.
4381 */
8b9cf98c 4382static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4383{
2e4ce7f5 4384#ifdef CONFIG_X86_64
6aa8b732 4385 unsigned long a;
2e4ce7f5 4386#endif
6aa8b732 4387 int i;
6aa8b732 4388
6aa8b732 4389 /* I/O */
3e7c73e9
AK		 4390 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4391 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4392
4607c2d7
AG		 4393 if (enable_shadow_vmcs) {
4394 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4395 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4396 }
25c5f225 4397 if (cpu_has_vmx_msr_bitmap())
5897297b 4398 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4399
6aa8b732
AK		 4400 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4401
6aa8b732 4402 /* Control */
01e439be 4403 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4404
bf8179a0 4405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4406
83ff3b9d 4407 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4408 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4409 vmx_secondary_exec_control(vmx));
83ff3b9d 4410 }
f78e0e2e 4411
01e439be 4412 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4413 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4414 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4415 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4416 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4417
4418 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4419
4420 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4421 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4422 }
4423
4b8d54f9
ZE		 4424 if (ple_gap) {
4425 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4426 vmx->ple_window = ple_window;
4427 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4428 }
4429
c3707958
XG		 4430 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4431 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4432 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4433
9581d442
AK		 4434 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4435 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4436 vmx_set_constant_host_state(vmx);
05b3e0c2 4437#ifdef CONFIG_X86_64
6aa8b732
AK		 4438 rdmsrl(MSR_FS_BASE, a);
4439 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4440 rdmsrl(MSR_GS_BASE, a);
4441 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4442#else
4443 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4444 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4445#endif
4446
2cc51560
ED		 4447 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4448 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4449 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4450 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4451 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4452
468d472f 4453 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4454 u32 msr_low, msr_high;
4455 u64 host_pat;
468d472f
SY		 4456 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4457 host_pat = msr_low | ((u64) msr_high << 32);
4458 /* Write the default value follow host pat */
4459 vmcs_write64(GUEST_IA32_PAT, host_pat);
4460 /* Keep arch.pat sync with GUEST_IA32_PAT */
4461 vmx->vcpu.arch.pat = host_pat;
4462 }
4463
03916db9 4464 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4465 u32 index = vmx_msr_index[i];
4466 u32 data_low, data_high;
a2fa3e9f 4467 int j = vmx->nmsrs;
6aa8b732
AK		 4468
4469 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4470 continue;
432bd6cb
AK		 4471 if (wrmsr_safe(index, data_low, data_high) < 0)
4472 continue;
26bb0981
AK		 4473 vmx->guest_msrs[j].index = i;
4474 vmx->guest_msrs[j].data = 0;
d5696725 4475 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4476 ++vmx->nmsrs;
6aa8b732 4477 }
6aa8b732 4478
2961e876
GN		 4479
4480 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4481
4482 /* 22.2.1, 20.8.1 */
2961e876 4483 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4484
e00c8cf2 4485 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4486 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4487
4488 return 0;
4489}
4490
57f252f2 4491static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4492{
4493 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4494 struct msr_data apic_base_msr;
e00c8cf2 4495
7ffd92c5 4496 vmx->rmode.vm86_active = 0;
e00c8cf2 4497
3b86cd99
JK		 4498 vmx->soft_vnmi_blocked = 0;
4499
ad312c7c 4500 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4501 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4502 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4503 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4504 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4505 apic_base_msr.host_initiated = true;
4506 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4507
2fb92db1
AK		 4508 vmx_segment_cache_clear(vmx);
4509
5706be0d 4510 seg_setup(VCPU_SREG_CS);
66450a21 4511 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4512 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4513
4514 seg_setup(VCPU_SREG_DS);
4515 seg_setup(VCPU_SREG_ES);
4516 seg_setup(VCPU_SREG_FS);
4517 seg_setup(VCPU_SREG_GS);
4518 seg_setup(VCPU_SREG_SS);
4519
4520 vmcs_write16(GUEST_TR_SELECTOR, 0);
4521 vmcs_writel(GUEST_TR_BASE, 0);
4522 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4523 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4524
4525 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4526 vmcs_writel(GUEST_LDTR_BASE, 0);
4527 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4528 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4529
4530 vmcs_write32(GUEST_SYSENTER_CS, 0);
4531 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4532 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4533
4534 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4535 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4536
e00c8cf2
AK		 4537 vmcs_writel(GUEST_GDTR_BASE, 0);
4538 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4539
4540 vmcs_writel(GUEST_IDTR_BASE, 0);
4541 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4542
443381a8 4543 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4544 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4545 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4546
e00c8cf2
AK		 4547 /* Special registers */
4548 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4549
4550 setup_msrs(vmx);
4551
6aa8b732
AK		 4552 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4553
f78e0e2e
SY		 4554 if (cpu_has_vmx_tpr_shadow()) {
4555 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4556 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4557 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4558 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4559 vmcs_write32(TPR_THRESHOLD, 0);
4560 }
4561
4562 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4563 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4564 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4565
01e439be
YZ		 4566 if (vmx_vm_has_apicv(vcpu->kvm))
4567 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4568
2384d2b3
SY		 4569 if (vmx->vpid != 0)
4570 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4571
fa40052c 4572 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4573 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4574 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4575 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4576 vmx_fpu_activate(&vmx->vcpu);
4577 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4578
b9d762fa 4579 vpid_sync_context(vmx);
6aa8b732
AK		 4580}
4581
b6f1250e
NHE		 4582/*
4583 * In nested virtualization, check if L1 asked to exit on external interrupts.
4584 * For most existing hypervisors, this will always return true.
4585 */
4586static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4587{
4588 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4589 PIN_BASED_EXT_INTR_MASK;
4590}
4591
77b0f5d6
BD		 4592/*
4593 * In nested virtualization, check if L1 has set
4594 * VM_EXIT_ACK_INTR_ON_EXIT
4595 */
4596static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4597{
4598 return get_vmcs12(vcpu)->vm_exit_controls &
4599 VM_EXIT_ACK_INTR_ON_EXIT;
4600}
4601
ea8ceb83
JK		 4602static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4603{
4604 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4605 PIN_BASED_NMI_EXITING;
4606}
4607
c9a7953f 4608static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4609{
4610 u32 cpu_based_vm_exec_control;
730dca42 4611
3b86cd99
JK		 4612 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4613 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4614 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4615}
4616
c9a7953f 4617static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4618{
4619 u32 cpu_based_vm_exec_control;
4620
c9a7953f
JK		 4621 if (!cpu_has_virtual_nmis() ||
4622 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4623 enable_irq_window(vcpu);
4624 return;
4625 }
3b86cd99
JK		 4626
4627 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4628 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4630}
4631
66fd3f7f 4632static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4633{
9c8cba37 4634 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4635 uint32_t intr;
4636 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4637
229456fc 4638 trace_kvm_inj_virq(irq);
2714d1d3 4639
fa89a817 4640 ++vcpu->stat.irq_injections;
7ffd92c5 4641 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4642 int inc_eip = 0;
4643 if (vcpu->arch.interrupt.soft)
4644 inc_eip = vcpu->arch.event_exit_inst_len;
4645 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4646 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4647 return;
4648 }
66fd3f7f
GN		 4649 intr = irq | INTR_INFO_VALID_MASK;
4650 if (vcpu->arch.interrupt.soft) {
4651 intr |= INTR_TYPE_SOFT_INTR;
4652 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4653 vmx->vcpu.arch.event_exit_inst_len);
4654 } else
4655 intr |= INTR_TYPE_EXT_INTR;
4656 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4657}
4658
f08864b4
SY		 4659static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4660{
66a5a347
JK		 4661 struct vcpu_vmx *vmx = to_vmx(vcpu);
4662
0b6ac343
NHE		 4663 if (is_guest_mode(vcpu))
4664 return;
4665
3b86cd99
JK		 4666 if (!cpu_has_virtual_nmis()) {
4667 /*
4668 * Tracking the NMI-blocked state in software is built upon
4669 * finding the next open IRQ window. This, in turn, depends on
4670 * well-behaving guests: They have to keep IRQs disabled at
4671 * least as long as the NMI handler runs. Otherwise we may
4672 * cause NMI nesting, maybe breaking the guest. But as this is
4673 * highly unlikely, we can live with the residual risk.
4674 */
4675 vmx->soft_vnmi_blocked = 1;
4676 vmx->vnmi_blocked_time = 0;
4677 }
4678
487b391d 4679 ++vcpu->stat.nmi_injections;
9d58b931 4680 vmx->nmi_known_unmasked = false;
7ffd92c5 4681 if (vmx->rmode.vm86_active) {
71f9833b 4682 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4683 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4684 return;
4685 }
f08864b4
SY		 4686 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4687 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4688}
4689
3cfc3092
JK		 4690static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4691{
4692 if (!cpu_has_virtual_nmis())
4693 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4694 if (to_vmx(vcpu)->nmi_known_unmasked)
4695 return false;
c332c83a 4696 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4697}
4698
4699static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4700{
4701 struct vcpu_vmx *vmx = to_vmx(vcpu);
4702
4703 if (!cpu_has_virtual_nmis()) {
4704 if (vmx->soft_vnmi_blocked != masked) {
4705 vmx->soft_vnmi_blocked = masked;
4706 vmx->vnmi_blocked_time = 0;
4707 }
4708 } else {
9d58b931 4709 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4710 if (masked)
4711 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4712 GUEST_INTR_STATE_NMI);
4713 else
4714 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4715 GUEST_INTR_STATE_NMI);
4716 }
4717}
4718
2505dc9f
JK		 4719static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4720{
b6b8a145
JK		 4721 if (to_vmx(vcpu)->nested.nested_run_pending)
4722 return 0;
ea8ceb83 4723
2505dc9f
JK		 4724 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4725 return 0;
4726
4727 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4728 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4729 | GUEST_INTR_STATE_NMI));
4730}
4731
78646121
GN		 4732static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4733{
b6b8a145
JK		 4734 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4735 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4736 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4737 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4738}
4739
cbc94022
IE		 4740static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4741{
4742 int ret;
4743 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4744 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4745 .guest_phys_addr = addr,
4746 .memory_size = PAGE_SIZE * 3,
4747 .flags = 0,
4748 };
4749
47ae31e2 4750 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4751 if (ret)
4752 return ret;
bfc6d222 4753 kvm->arch.tss_addr = addr;
93ea5388
GN		 4754 if (!init_rmode_tss(kvm))
4755 return -ENOMEM;
4756
cbc94022
IE		 4757 return 0;
4758}
4759
0ca1b4f4 4760static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4761{
77ab6db0 4762 switch (vec) {
77ab6db0 4763 case BP_VECTOR:
c573cd22
JK		 4764 /*
4765 * Update instruction length as we may reinject the exception
4766 * from user space while in guest debugging mode.
4767 */
4768 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4769 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4770 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4771 return false;
4772 /* fall through */
4773 case DB_VECTOR:
4774 if (vcpu->guest_debug &
4775 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4776 return false;
d0bfb940
JK		 4777 /* fall through */
4778 case DE_VECTOR:
77ab6db0
JK		 4779 case OF_VECTOR:
4780 case BR_VECTOR:
4781 case UD_VECTOR:
4782 case DF_VECTOR:
4783 case SS_VECTOR:
4784 case GP_VECTOR:
4785 case MF_VECTOR:
0ca1b4f4
GN		 4786 return true;
4787 break;
77ab6db0 4788 }
0ca1b4f4
GN		 4789 return false;
4790}
4791
4792static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4793 int vec, u32 err_code)
4794{
4795 /*
4796 * Instruction with address size override prefix opcode 0x67
4797 * Cause the #SS fault with 0 error code in VM86 mode.
4798 */
4799 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4800 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4801 if (vcpu->arch.halt_request) {
4802 vcpu->arch.halt_request = 0;
4803 return kvm_emulate_halt(vcpu);
4804 }
4805 return 1;
4806 }
4807 return 0;
4808 }
4809
4810 /*
4811 * Forward all other exceptions that are valid in real mode.
4812 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4813 * the required debugging infrastructure rework.
4814 */
4815 kvm_queue_exception(vcpu, vec);
4816 return 1;
6aa8b732
AK		 4817}
4818
a0861c02
AK		 4819/*
4820 * Trigger machine check on the host. We assume all the MSRs are already set up
4821 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4822 * We pass a fake environment to the machine check handler because we want
4823 * the guest to be always treated like user space, no matter what context
4824 * it used internally.
4825 */
4826static void kvm_machine_check(void)
4827{
4828#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4829 struct pt_regs regs = {
4830 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4831 .flags = X86_EFLAGS_IF,
4832 };
4833
4834 do_machine_check(&regs, 0);
4835#endif
4836}
4837
851ba692 4838static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4839{
4840 /* already handled by vcpu_run */
4841 return 1;
4842}
4843
851ba692 4844static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4845{
1155f76a 4846 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4847 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4848 u32 intr_info, ex_no, error_code;
42dbaa5a 4849 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4850 u32 vect_info;
4851 enum emulation_result er;
4852
1155f76a 4853 vect_info = vmx->idt_vectoring_info;
88786475 4854 intr_info = vmx->exit_intr_info;
6aa8b732 4855
a0861c02 4856 if (is_machine_check(intr_info))
851ba692 4857 return handle_machine_check(vcpu);
a0861c02 4858
e4a41889 4859 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4860 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4861
4862 if (is_no_device(intr_info)) {
5fd86fcf 4863 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4864 return 1;
4865 }
4866
7aa81cc0 4867 if (is_invalid_opcode(intr_info)) {
51d8b661 4868 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4869 if (er != EMULATE_DONE)
7ee5d940 4870 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4871 return 1;
4872 }
4873
6aa8b732 4874 error_code = 0;
2e11384c 4875 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4876 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4877
4878 /*
4879 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4880 * MMIO, it is better to report an internal error.
4881 * See the comments in vmx_handle_exit.
4882 */
4883 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4884 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4885 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4886 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4887 vcpu->run->internal.ndata = 2;
4888 vcpu->run->internal.data[0] = vect_info;
4889 vcpu->run->internal.data[1] = intr_info;
4890 return 0;
4891 }
4892
6aa8b732 4893 if (is_page_fault(intr_info)) {
1439442c 4894 /* EPT won't cause page fault directly */
cf3ace79 4895 BUG_ON(enable_ept);
6aa8b732 4896 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4897 trace_kvm_page_fault(cr2, error_code);
4898
3298b75c 4899 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4900 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4901 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4902 }
4903
d0bfb940 4904 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4905
4906 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4907 return handle_rmode_exception(vcpu, ex_no, error_code);
4908
42dbaa5a
JK		 4909 switch (ex_no) {
4910 case DB_VECTOR:
4911 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4912 if (!(vcpu->guest_debug &
4913 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4914 vcpu->arch.dr6 &= ~15;
6f43ed01 4915 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4916 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4917 skip_emulated_instruction(vcpu);
4918
42dbaa5a
JK		 4919 kvm_queue_exception(vcpu, DB_VECTOR);
4920 return 1;
4921 }
4922 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4923 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4924 /* fall through */
4925 case BP_VECTOR:
c573cd22
JK		 4926 /*
4927 * Update instruction length as we may reinject #BP from
4928 * user space while in guest debugging mode. Reading it for
4929 * #DB as well causes no harm, it is not used in that case.
4930 */
4931 vmx->vcpu.arch.event_exit_inst_len =
4932 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4933 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4934 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4935 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4936 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4937 break;
4938 default:
d0bfb940
JK		 4939 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4940 kvm_run->ex.exception = ex_no;
4941 kvm_run->ex.error_code = error_code;
42dbaa5a 4942 break;
6aa8b732 4943 }
6aa8b732
AK		 4944 return 0;
4945}
4946
851ba692 4947static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4948{
1165f5fe 4949 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4950 return 1;
4951}
4952
851ba692 4953static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4954{
851ba692 4955 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4956 return 0;
4957}
6aa8b732 4958
851ba692 4959static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4960{
bfdaab09 4961 unsigned long exit_qualification;
34c33d16 4962 int size, in, string;
039576c0 4963 unsigned port;
6aa8b732 4964
bfdaab09 4965 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4966 string = (exit_qualification & 16) != 0;
cf8f70bf 4967 in = (exit_qualification & 8) != 0;
e70669ab 4968
cf8f70bf 4969 ++vcpu->stat.io_exits;
e70669ab 4970
cf8f70bf 4971 if (string || in)
51d8b661 4972 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4973
cf8f70bf
GN		 4974 port = exit_qualification >> 16;
4975 size = (exit_qualification & 7) + 1;
e93f36bc 4976 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4977
4978 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4979}
4980
102d8325
IM		 4981static void
4982vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4983{
4984 /*
4985 * Patch in the VMCALL instruction:
4986 */
4987 hypercall[0] = 0x0f;
4988 hypercall[1] = 0x01;
4989 hypercall[2] = 0xc1;
102d8325
IM		 4990}
4991
92fbc7b1
JK		 4992static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4993{
4994 unsigned long always_on = VMXON_CR0_ALWAYSON;
4995
4996 if (nested_vmx_secondary_ctls_high &
4997 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4998 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4999 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5000 return (val & always_on) == always_on;
5001}
5002
0fa06071 5003/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5004static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5005{
eeadf9e7 5006 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5007 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5008 unsigned long orig_val = val;
5009
eeadf9e7
NHE		 5010 /*
5011 * We get here when L2 changed cr0 in a way that did not change
5012 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5013 * but did change L0 shadowed bits. So we first calculate the
5014 * effective cr0 value that L1 would like to write into the
5015 * hardware. It consists of the L2-owned bits from the new
5016 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5017 */
1a0d74e6
JK		 5018 val = (val & ~vmcs12->cr0_guest_host_mask) |
5019 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5020
92fbc7b1 5021 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5022 return 1;
1a0d74e6
JK		 5023
5024 if (kvm_set_cr0(vcpu, val))
5025 return 1;
5026 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5027 return 0;
1a0d74e6
JK		 5028 } else {
5029 if (to_vmx(vcpu)->nested.vmxon &&
5030 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5031 return 1;
eeadf9e7 5032 return kvm_set_cr0(vcpu, val);
1a0d74e6 5033 }
eeadf9e7
NHE		 5034}
5035
5036static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5037{
5038 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5039 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5040 unsigned long orig_val = val;
5041
5042 /* analogously to handle_set_cr0 */
5043 val = (val & ~vmcs12->cr4_guest_host_mask) |
5044 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5045 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5046 return 1;
1a0d74e6 5047 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5048 return 0;
5049 } else
5050 return kvm_set_cr4(vcpu, val);
5051}
5052
5053/* called to set cr0 as approriate for clts instruction exit. */
5054static void handle_clts(struct kvm_vcpu *vcpu)
5055{
5056 if (is_guest_mode(vcpu)) {
5057 /*
5058 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5059 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5060 * just pretend it's off (also in arch.cr0 for fpu_activate).
5061 */
5062 vmcs_writel(CR0_READ_SHADOW,
5063 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5064 vcpu->arch.cr0 &= ~X86_CR0_TS;
5065 } else
5066 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5067}
5068
851ba692 5069static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5070{
229456fc 5071 unsigned long exit_qualification, val;
6aa8b732
AK		 5072 int cr;
5073 int reg;
49a9b07e 5074 int err;
6aa8b732 5075
bfdaab09 5076 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5077 cr = exit_qualification & 15;
5078 reg = (exit_qualification >> 8) & 15;
5079 switch ((exit_qualification >> 4) & 3) {
5080 case 0: /* mov to cr */
1e32c079 5081 val = kvm_register_readl(vcpu, reg);
229456fc 5082 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5083 switch (cr) {
5084 case 0:
eeadf9e7 5085 err = handle_set_cr0(vcpu, val);
db8fcefa 5086 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5087 return 1;
5088 case 3:
2390218b 5089 err = kvm_set_cr3(vcpu, val);
db8fcefa 5090 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5091 return 1;
5092 case 4:
eeadf9e7 5093 err = handle_set_cr4(vcpu, val);
db8fcefa 5094 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5095 return 1;
0a5fff19
GN		 5096 case 8: {
5097 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5098 u8 cr8 = (u8)val;
eea1cff9 5099 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5100 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5101 if (irqchip_in_kernel(vcpu->kvm))
5102 return 1;
5103 if (cr8_prev <= cr8)
5104 return 1;
851ba692 5105 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5106 return 0;
5107 }
4b8073e4 5108 }
6aa8b732 5109 break;
25c4c276 5110 case 2: /* clts */
eeadf9e7 5111 handle_clts(vcpu);
4d4ec087 5112 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5113 skip_emulated_instruction(vcpu);
6b52d186 5114 vmx_fpu_activate(vcpu);
25c4c276 5115 return 1;
6aa8b732
AK		 5116 case 1: /*mov from cr*/
5117 switch (cr) {
5118 case 3:
9f8fe504
AK		 5119 val = kvm_read_cr3(vcpu);
5120 kvm_register_write(vcpu, reg, val);
5121 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5122 skip_emulated_instruction(vcpu);
5123 return 1;
5124 case 8:
229456fc
MT		 5125 val = kvm_get_cr8(vcpu);
5126 kvm_register_write(vcpu, reg, val);
5127 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5128 skip_emulated_instruction(vcpu);
5129 return 1;
5130 }
5131 break;
5132 case 3: /* lmsw */
a1f83a74 5133 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5134 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5135 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5136
5137 skip_emulated_instruction(vcpu);
5138 return 1;
5139 default:
5140 break;
5141 }
851ba692 5142 vcpu->run->exit_reason = 0;
a737f256 5143 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5144 (int)(exit_qualification >> 4) & 3, cr);
5145 return 0;
5146}
5147
851ba692 5148static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5149{
bfdaab09 5150 unsigned long exit_qualification;
6aa8b732
AK		 5151 int dr, reg;
5152
f2483415 5153 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5154 if (!kvm_require_cpl(vcpu, 0))
5155 return 1;
42dbaa5a
JK		 5156 dr = vmcs_readl(GUEST_DR7);
5157 if (dr & DR7_GD) {
5158 /*
5159 * As the vm-exit takes precedence over the debug trap, we
5160 * need to emulate the latter, either for the host or the
5161 * guest debugging itself.
5162 */
5163 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5164 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5165 vcpu->run->debug.arch.dr7 = dr;
5166 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5167 vmcs_readl(GUEST_CS_BASE) +
5168 vmcs_readl(GUEST_RIP);
851ba692
AK		 5169 vcpu->run->debug.arch.exception = DB_VECTOR;
5170 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5171 return 0;
5172 } else {
5173 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5174 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5175 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5176 kvm_queue_exception(vcpu, DB_VECTOR);
5177 return 1;
5178 }
5179 }
5180
81908bf4
PB		 5181 if (vcpu->guest_debug == 0) {
5182 u32 cpu_based_vm_exec_control;
5183
5184 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5185 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5186 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5187
5188 /*
5189 * No more DR vmexits; force a reload of the debug registers
5190 * and reenter on this instruction. The next vmexit will
5191 * retrieve the full state of the debug registers.
5192 */
5193 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5194 return 1;
5195 }
5196
bfdaab09 5197 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5198 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5199 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5200 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5201 unsigned long val;
4c4d563b
JK		 5202
5203 if (kvm_get_dr(vcpu, dr, &val))
5204 return 1;
5205 kvm_register_write(vcpu, reg, val);
020df079 5206 } else
5777392e 5207 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5208 return 1;
5209
6aa8b732
AK		 5210 skip_emulated_instruction(vcpu);
5211 return 1;
5212}
5213
73aaf249
JK		 5214static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5215{
5216 return vcpu->arch.dr6;
5217}
5218
5219static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5220{
5221}
5222
81908bf4
PB		 5223static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5224{
5225 u32 cpu_based_vm_exec_control;
5226
5227 get_debugreg(vcpu->arch.db[0], 0);
5228 get_debugreg(vcpu->arch.db[1], 1);
5229 get_debugreg(vcpu->arch.db[2], 2);
5230 get_debugreg(vcpu->arch.db[3], 3);
5231 get_debugreg(vcpu->arch.dr6, 6);
5232 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5233
5234 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5235
5236 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5237 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5238 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5239}
5240
020df079
GN		 5241static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5242{
5243 vmcs_writel(GUEST_DR7, val);
5244}
5245
851ba692 5246static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5247{
06465c5a
AK		 5248 kvm_emulate_cpuid(vcpu);
5249 return 1;
6aa8b732
AK		 5250}
5251
851ba692 5252static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5253{
ad312c7c 5254 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5255 u64 data;
5256
5257 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5258 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5259 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5260 return 1;
5261 }
5262
229456fc 5263 trace_kvm_msr_read(ecx, data);
2714d1d3 5264
6aa8b732 5265 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5266 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5267 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5268 skip_emulated_instruction(vcpu);
5269 return 1;
5270}
5271
851ba692 5272static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5273{
8fe8ab46 5274 struct msr_data msr;
ad312c7c
ZX		 5275 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5276 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5277 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5278
8fe8ab46
WA		 5279 msr.data = data;
5280 msr.index = ecx;
5281 msr.host_initiated = false;
5282 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5283 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5284 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5285 return 1;
5286 }
5287
59200273 5288 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5289 skip_emulated_instruction(vcpu);
5290 return 1;
5291}
5292
851ba692 5293static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5294{
3842d135 5295 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5296 return 1;
5297}
5298
851ba692 5299static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5300{
85f455f7
ED		 5301 u32 cpu_based_vm_exec_control;
5302
5303 /* clear pending irq */
5304 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5305 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5306 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5307
3842d135
AK		 5308 kvm_make_request(KVM_REQ_EVENT, vcpu);
5309
a26bf12a 5310 ++vcpu->stat.irq_window_exits;
2714d1d3 5311
c1150d8c
DL		 5312 /*
5313 * If the user space waits to inject interrupts, exit as soon as
5314 * possible
5315 */
8061823a 5316 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5317 vcpu->run->request_interrupt_window &&
8061823a 5318 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5319 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5320 return 0;
5321 }
6aa8b732
AK		 5322 return 1;
5323}
5324
851ba692 5325static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5326{
5327 skip_emulated_instruction(vcpu);
d3bef15f 5328 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5329}
5330
851ba692 5331static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5332{
510043da 5333 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5334 kvm_emulate_hypercall(vcpu);
5335 return 1;
c21415e8
IM		 5336}
5337
ec25d5e6
GN		 5338static int handle_invd(struct kvm_vcpu *vcpu)
5339{
51d8b661 5340 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5341}
5342
851ba692 5343static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5344{
f9c617f6 5345 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5346
5347 kvm_mmu_invlpg(vcpu, exit_qualification);
5348 skip_emulated_instruction(vcpu);
5349 return 1;
5350}
5351
fee84b07
AK		 5352static int handle_rdpmc(struct kvm_vcpu *vcpu)
5353{
5354 int err;
5355
5356 err = kvm_rdpmc(vcpu);
5357 kvm_complete_insn_gp(vcpu, err);
5358
5359 return 1;
5360}
5361
851ba692 5362static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5363{
5364 skip_emulated_instruction(vcpu);
f5f48ee1 5365 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5366 return 1;
5367}
5368
2acf923e
DC		 5369static int handle_xsetbv(struct kvm_vcpu *vcpu)
5370{
5371 u64 new_bv = kvm_read_edx_eax(vcpu);
5372 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5373
5374 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5375 skip_emulated_instruction(vcpu);
5376 return 1;
5377}
5378
851ba692 5379static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5380{
58fbbf26
KT		 5381 if (likely(fasteoi)) {
5382 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5383 int access_type, offset;
5384
5385 access_type = exit_qualification & APIC_ACCESS_TYPE;
5386 offset = exit_qualification & APIC_ACCESS_OFFSET;
5387 /*
5388 * Sane guest uses MOV to write EOI, with written value
5389 * not cared. So make a short-circuit here by avoiding
5390 * heavy instruction emulation.
5391 */
5392 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5393 (offset == APIC_EOI)) {
5394 kvm_lapic_set_eoi(vcpu);
5395 skip_emulated_instruction(vcpu);
5396 return 1;
5397 }
5398 }
51d8b661 5399 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5400}
5401
c7c9c56c
YZ		 5402static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5403{
5404 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5405 int vector = exit_qualification & 0xff;
5406
5407 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5408 kvm_apic_set_eoi_accelerated(vcpu, vector);
5409 return 1;
5410}
5411
83d4c286
YZ		 5412static int handle_apic_write(struct kvm_vcpu *vcpu)
5413{
5414 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5415 u32 offset = exit_qualification & 0xfff;
5416
5417 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5418 kvm_apic_write_nodecode(vcpu, offset);
5419 return 1;
5420}
5421
851ba692 5422static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5423{
60637aac 5424 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5425 unsigned long exit_qualification;
e269fb21
JK		 5426 bool has_error_code = false;
5427 u32 error_code = 0;
37817f29 5428 u16 tss_selector;
7f3d35fd 5429 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5430
5431 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5432 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5433 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5434
5435 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5436
5437 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5438 if (reason == TASK_SWITCH_GATE && idt_v) {
5439 switch (type) {
5440 case INTR_TYPE_NMI_INTR:
5441 vcpu->arch.nmi_injected = false;
654f06fc 5442 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5443 break;
5444 case INTR_TYPE_EXT_INTR:
66fd3f7f 5445 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5446 kvm_clear_interrupt_queue(vcpu);
5447 break;
5448 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5449 if (vmx->idt_vectoring_info &
5450 VECTORING_INFO_DELIVER_CODE_MASK) {
5451 has_error_code = true;
5452 error_code =
5453 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5454 }
5455 /* fall through */
64a7ec06
GN		 5456 case INTR_TYPE_SOFT_EXCEPTION:
5457 kvm_clear_exception_queue(vcpu);
5458 break;
5459 default:
5460 break;
5461 }
60637aac 5462 }
37817f29
IE		 5463 tss_selector = exit_qualification;
5464
64a7ec06
GN		 5465 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5466 type != INTR_TYPE_EXT_INTR &&
5467 type != INTR_TYPE_NMI_INTR))
5468 skip_emulated_instruction(vcpu);
5469
7f3d35fd
KW		 5470 if (kvm_task_switch(vcpu, tss_selector,
5471 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5472 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5473 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5474 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5475 vcpu->run->internal.ndata = 0;
42dbaa5a 5476 return 0;
acb54517 5477 }
42dbaa5a
JK		 5478
5479 /* clear all local breakpoint enable flags */
1f854112 5480 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5481
5482 /*
5483 * TODO: What about debug traps on tss switch?
5484 * Are we supposed to inject them and update dr6?
5485 */
5486
5487 return 1;
37817f29
IE		 5488}
5489
851ba692 5490static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5491{
f9c617f6 5492 unsigned long exit_qualification;
1439442c 5493 gpa_t gpa;
4f5982a5 5494 u32 error_code;
1439442c 5495 int gla_validity;
1439442c 5496
f9c617f6 5497 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5498
1439442c
SY		 5499 gla_validity = (exit_qualification >> 7) & 0x3;
5500 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5501 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5502 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5503 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5504 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5505 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5506 (long unsigned int)exit_qualification);
851ba692
AK		 5507 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5508 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5509 return 0;
1439442c
SY		 5510 }
5511
0be9c7a8
GN		 5512 /*
5513 * EPT violation happened while executing iret from NMI,
5514 * "blocked by NMI" bit has to be set before next VM entry.
5515 * There are errata that may cause this bit to not be set:
5516 * AAK134, BY25.
5517 */
bcd1c294
GN		 5518 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5519 cpu_has_virtual_nmis() &&
5520 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5521 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5522
1439442c 5523 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5524 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5525
5526 /* It is a write fault? */
5527 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5528 /* It is a fetch fault? */
5529 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5530 /* ept page table is present? */
5531 error_code |= (exit_qualification >> 3) & 0x1;
5532
25d92081
YZ		 5533 vcpu->arch.exit_qualification = exit_qualification;
5534
4f5982a5 5535 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5536}
5537
68f89400
MT		 5538static u64 ept_rsvd_mask(u64 spte, int level)
5539{
5540 int i;
5541 u64 mask = 0;
5542
5543 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5544 mask |= (1ULL << i);
5545
a32e8459 5546 if (level == 4)
68f89400
MT		 5547 /* bits 7:3 reserved */
5548 mask |= 0xf8;
a32e8459
WL		 5549 else if (spte & (1ULL << 7))
5550 /*
5551 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5552 * level == 1 if the hypervisor is using the ignored bit 7.
5553 */
5554 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5555 else if (level > 1)
5556 /* bits 6:3 reserved */
5557 mask |= 0x78;
68f89400
MT		 5558
5559 return mask;
5560}
5561
5562static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5563 int level)
5564{
5565 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5566
5567 /* 010b (write-only) */
5568 WARN_ON((spte & 0x7) == 0x2);
5569
5570 /* 110b (write/execute) */
5571 WARN_ON((spte & 0x7) == 0x6);
5572
5573 /* 100b (execute-only) and value not supported by logical processor */
5574 if (!cpu_has_vmx_ept_execute_only())
5575 WARN_ON((spte & 0x7) == 0x4);
5576
5577 /* not 000b */
5578 if ((spte & 0x7)) {
5579 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5580
5581 if (rsvd_bits != 0) {
5582 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5583 __func__, rsvd_bits);
5584 WARN_ON(1);
5585 }
5586
a32e8459
WL		 5587 /* bits 5:3 are _not_ reserved for large page or leaf page */
5588 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5589 u64 ept_mem_type = (spte & 0x38) >> 3;
5590
5591 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5592 ept_mem_type == 7) {
5593 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5594 __func__, ept_mem_type);
5595 WARN_ON(1);
5596 }
5597 }
5598 }
5599}
5600
851ba692 5601static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5602{
5603 u64 sptes[4];
ce88decf 5604 int nr_sptes, i, ret;
68f89400
MT		 5605 gpa_t gpa;
5606
5607 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5608 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5609 skip_emulated_instruction(vcpu);
5610 return 1;
5611 }
68f89400 5612
ce88decf 5613 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5614 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5615 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5616 EMULATE_DONE;
f8f55942
XG		 5617
5618 if (unlikely(ret == RET_MMIO_PF_INVALID))
5619 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5620
b37fbea6 5621 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5622 return 1;
5623
5624 /* It is the real ept misconfig */
68f89400
MT		 5625 printk(KERN_ERR "EPT: Misconfiguration.\n");
5626 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5627
5628 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5629
5630 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5631 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5632
851ba692
AK		 5633 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5634 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5635
5636 return 0;
5637}
5638
851ba692 5639static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5640{
5641 u32 cpu_based_vm_exec_control;
5642
5643 /* clear pending NMI */
5644 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5645 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5646 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5647 ++vcpu->stat.nmi_window_exits;
3842d135 5648 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5649
5650 return 1;
5651}
5652
80ced186 5653static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5654{
8b3079a5
AK		 5655 struct vcpu_vmx *vmx = to_vmx(vcpu);
5656 enum emulation_result err = EMULATE_DONE;
80ced186 5657 int ret = 1;
49e9d557
AK		 5658 u32 cpu_exec_ctrl;
5659 bool intr_window_requested;
b8405c18 5660 unsigned count = 130;
49e9d557
AK		 5661
5662 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5663 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5664
98eb2f8b 5665 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5666 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5667 return handle_interrupt_window(&vmx->vcpu);
5668
de87dcdd
AK		 5669 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5670 return 1;
5671
991eebf9 5672 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5673
ac0a48c3 5674 if (err == EMULATE_USER_EXIT) {
94452b9e 5675 ++vcpu->stat.mmio_exits;
80ced186
MG		 5676 ret = 0;
5677 goto out;
5678 }
1d5a4d9b 5679
de5f70e0
AK		 5680 if (err != EMULATE_DONE) {
5681 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5682 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5683 vcpu->run->internal.ndata = 0;
6d77dbfc 5684 return 0;
de5f70e0 5685 }
ea953ef0 5686
8d76c49e
GN		 5687 if (vcpu->arch.halt_request) {
5688 vcpu->arch.halt_request = 0;
5689 ret = kvm_emulate_halt(vcpu);
5690 goto out;
5691 }
5692
ea953ef0 5693 if (signal_pending(current))
80ced186 5694 goto out;
ea953ef0
MG		 5695 if (need_resched())
5696 schedule();
5697 }
5698
80ced186
MG		 5699out:
5700 return ret;
ea953ef0
MG		 5701}
5702
b4a2d31d
RK		 5703static int __grow_ple_window(int val)
5704{
5705 if (ple_window_grow < 1)
5706 return ple_window;
5707
5708 val = min(val, ple_window_actual_max);
5709
5710 if (ple_window_grow < ple_window)
5711 val *= ple_window_grow;
5712 else
5713 val += ple_window_grow;
5714
5715 return val;
5716}
5717
5718static int __shrink_ple_window(int val, int modifier, int minimum)
5719{
5720 if (modifier < 1)
5721 return ple_window;
5722
5723 if (modifier < ple_window)
5724 val /= modifier;
5725 else
5726 val -= modifier;
5727
5728 return max(val, minimum);
5729}
5730
5731static void grow_ple_window(struct kvm_vcpu *vcpu)
5732{
5733 struct vcpu_vmx *vmx = to_vmx(vcpu);
5734 int old = vmx->ple_window;
5735
5736 vmx->ple_window = __grow_ple_window(old);
5737
5738 if (vmx->ple_window != old)
5739 vmx->ple_window_dirty = true;
7b46268d
RK		 5740
5741 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5742}
5743
5744static void shrink_ple_window(struct kvm_vcpu *vcpu)
5745{
5746 struct vcpu_vmx *vmx = to_vmx(vcpu);
5747 int old = vmx->ple_window;
5748
5749 vmx->ple_window = __shrink_ple_window(old,
5750 ple_window_shrink, ple_window);
5751
5752 if (vmx->ple_window != old)
5753 vmx->ple_window_dirty = true;
7b46268d
RK		 5754
5755 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5756}
5757
5758/*
5759 * ple_window_actual_max is computed to be one grow_ple_window() below
5760 * ple_window_max. (See __grow_ple_window for the reason.)
5761 * This prevents overflows, because ple_window_max is int.
5762 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5763 * this process.
5764 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5765 */
5766static void update_ple_window_actual_max(void)
5767{
5768 ple_window_actual_max =
5769 __shrink_ple_window(max(ple_window_max, ple_window),
5770 ple_window_grow, INT_MIN);
5771}
5772
4b8d54f9
ZE		 5773/*
5774 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5775 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5776 */
9fb41ba8 5777static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5778{
b4a2d31d
RK		 5779 if (ple_gap)
5780 grow_ple_window(vcpu);
5781
4b8d54f9
ZE		 5782 skip_emulated_instruction(vcpu);
5783 kvm_vcpu_on_spin(vcpu);
5784
5785 return 1;
5786}
5787
87c00572 5788static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5789{
87c00572 5790 skip_emulated_instruction(vcpu);
59708670
SY		 5791 return 1;
5792}
5793
87c00572
GS		 5794static int handle_mwait(struct kvm_vcpu *vcpu)
5795{
5796 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5797 return handle_nop(vcpu);
5798}
5799
5800static int handle_monitor(struct kvm_vcpu *vcpu)
5801{
5802 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5803 return handle_nop(vcpu);
5804}
5805
ff2f6fe9
NHE		 5806/*
5807 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5808 * We could reuse a single VMCS for all the L2 guests, but we also want the
5809 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5810 * allows keeping them loaded on the processor, and in the future will allow
5811 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5812 * every entry if they never change.
5813 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5814 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5815 *
5816 * The following functions allocate and free a vmcs02 in this pool.
5817 */
5818
5819/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5820static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5821{
5822 struct vmcs02_list *item;
5823 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5824 if (item->vmptr == vmx->nested.current_vmptr) {
5825 list_move(&item->list, &vmx->nested.vmcs02_pool);
5826 return &item->vmcs02;
5827 }
5828
5829 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5830 /* Recycle the least recently used VMCS. */
5831 item = list_entry(vmx->nested.vmcs02_pool.prev,
5832 struct vmcs02_list, list);
5833 item->vmptr = vmx->nested.current_vmptr;
5834 list_move(&item->list, &vmx->nested.vmcs02_pool);
5835 return &item->vmcs02;
5836 }
5837
5838 /* Create a new VMCS */
0fa24ce3 5839 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5840 if (!item)
5841 return NULL;
5842 item->vmcs02.vmcs = alloc_vmcs();
5843 if (!item->vmcs02.vmcs) {
5844 kfree(item);
5845 return NULL;
5846 }
5847 loaded_vmcs_init(&item->vmcs02);
5848 item->vmptr = vmx->nested.current_vmptr;
5849 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5850 vmx->nested.vmcs02_num++;
5851 return &item->vmcs02;
5852}
5853
5854/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5855static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5856{
5857 struct vmcs02_list *item;
5858 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5859 if (item->vmptr == vmptr) {
5860 free_loaded_vmcs(&item->vmcs02);
5861 list_del(&item->list);
5862 kfree(item);
5863 vmx->nested.vmcs02_num--;
5864 return;
5865 }
5866}
5867
5868/*
5869 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5870 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5871 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5872 */
5873static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5874{
5875 struct vmcs02_list *item, *n;
4fa7734c
PB		 5876
5877 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5878 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5879 /*
5880 * Something will leak if the above WARN triggers. Better than
5881 * a use-after-free.
5882 */
5883 if (vmx->loaded_vmcs == &item->vmcs02)
5884 continue;
5885
5886 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5887 list_del(&item->list);
5888 kfree(item);
4fa7734c 5889 vmx->nested.vmcs02_num--;
ff2f6fe9 5890 }
ff2f6fe9
NHE		 5891}
5892
0658fbaa
ACL		 5893/*
5894 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5895 * set the success or error code of an emulated VMX instruction, as specified
5896 * by Vol 2B, VMX Instruction Reference, "Conventions".
5897 */
5898static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5899{
5900 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5901 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5902 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5903}
5904
5905static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5906{
5907 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5908 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5909 X86_EFLAGS_SF | X86_EFLAGS_OF))
5910 | X86_EFLAGS_CF);
5911}
5912
145c28dd 5913static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5914 u32 vm_instruction_error)
5915{
5916 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5917 /*
5918 * failValid writes the error number to the current VMCS, which
5919 * can't be done there isn't a current VMCS.
5920 */
5921 nested_vmx_failInvalid(vcpu);
5922 return;
5923 }
5924 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5925 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5926 X86_EFLAGS_SF | X86_EFLAGS_OF))
5927 | X86_EFLAGS_ZF);
5928 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5929 /*
5930 * We don't need to force a shadow sync because
5931 * VM_INSTRUCTION_ERROR is not shadowed
5932 */
5933}
145c28dd 5934
f4124500
JK		 5935static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5936{
5937 struct vcpu_vmx *vmx =
5938 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5939
5940 vmx->nested.preemption_timer_expired = true;
5941 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5942 kvm_vcpu_kick(&vmx->vcpu);
5943
5944 return HRTIMER_NORESTART;
5945}
5946
19677e32
BD		 5947/*
5948 * Decode the memory-address operand of a vmx instruction, as recorded on an
5949 * exit caused by such an instruction (run by a guest hypervisor).
5950 * On success, returns 0. When the operand is invalid, returns 1 and throws
5951 * #UD or #GP.
5952 */
5953static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5954 unsigned long exit_qualification,
5955 u32 vmx_instruction_info, gva_t *ret)
5956{
5957 /*
5958 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5959 * Execution", on an exit, vmx_instruction_info holds most of the
5960 * addressing components of the operand. Only the displacement part
5961 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5962 * For how an actual address is calculated from all these components,
5963 * refer to Vol. 1, "Operand Addressing".
5964 */
5965 int scaling = vmx_instruction_info & 3;
5966 int addr_size = (vmx_instruction_info >> 7) & 7;
5967 bool is_reg = vmx_instruction_info & (1u << 10);
5968 int seg_reg = (vmx_instruction_info >> 15) & 7;
5969 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5970 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5971 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5972 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5973
5974 if (is_reg) {
5975 kvm_queue_exception(vcpu, UD_VECTOR);
5976 return 1;
5977 }
5978
5979 /* Addr = segment_base + offset */
5980 /* offset = base + [index * scale] + displacement */
5981 *ret = vmx_get_segment_base(vcpu, seg_reg);
5982 if (base_is_valid)
5983 *ret += kvm_register_read(vcpu, base_reg);
5984 if (index_is_valid)
5985 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5986 *ret += exit_qualification; /* holds the displacement */
5987
5988 if (addr_size == 1) /* 32 bit */
5989 *ret &= 0xffffffff;
5990
5991 /*
5992 * TODO: throw #GP (and return 1) in various cases that the VM*
5993 * instructions require it - e.g., offset beyond segment limit,
5994 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5995 * address, and so on. Currently these are not checked.
5996 */
5997 return 0;
5998}
5999
3573e22c
BD		 6000/*
6001 * This function performs the various checks including
6002 * - if it's 4KB aligned
6003 * - No bits beyond the physical address width are set
6004 * - Returns 0 on success or else 1
4291b588 6005 * (Intel SDM Section 30.3)
3573e22c 6006 */
4291b588
BD		 6007static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6008 gpa_t *vmpointer)
3573e22c
BD		 6009{
6010 gva_t gva;
6011 gpa_t vmptr;
6012 struct x86_exception e;
6013 struct page *page;
6014 struct vcpu_vmx *vmx = to_vmx(vcpu);
6015 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6016
6017 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6018 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6019 return 1;
6020
6021 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6022 sizeof(vmptr), &e)) {
6023 kvm_inject_page_fault(vcpu, &e);
6024 return 1;
6025 }
6026
6027 switch (exit_reason) {
6028 case EXIT_REASON_VMON:
6029 /*
6030 * SDM 3: 24.11.5
6031 * The first 4 bytes of VMXON region contain the supported
6032 * VMCS revision identifier
6033 *
6034 * Note - IA32_VMX_BASIC[48] will never be 1
6035 * for the nested case;
6036 * which replaces physical address width with 32
6037 *
6038 */
bc39c4db 6039 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6040 nested_vmx_failInvalid(vcpu);
6041 skip_emulated_instruction(vcpu);
6042 return 1;
6043 }
6044
6045 page = nested_get_page(vcpu, vmptr);
6046 if (page == NULL ||
6047 *(u32 *)kmap(page) != VMCS12_REVISION) {
6048 nested_vmx_failInvalid(vcpu);
6049 kunmap(page);
6050 skip_emulated_instruction(vcpu);
6051 return 1;
6052 }
6053 kunmap(page);
6054 vmx->nested.vmxon_ptr = vmptr;
6055 break;
4291b588 6056 case EXIT_REASON_VMCLEAR:
bc39c4db 6057 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6058 nested_vmx_failValid(vcpu,
6059 VMXERR_VMCLEAR_INVALID_ADDRESS);
6060 skip_emulated_instruction(vcpu);
6061 return 1;
6062 }
6063
6064 if (vmptr == vmx->nested.vmxon_ptr) {
6065 nested_vmx_failValid(vcpu,
6066 VMXERR_VMCLEAR_VMXON_POINTER);
6067 skip_emulated_instruction(vcpu);
6068 return 1;
6069 }
6070 break;
6071 case EXIT_REASON_VMPTRLD:
bc39c4db 6072 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6073 nested_vmx_failValid(vcpu,
6074 VMXERR_VMPTRLD_INVALID_ADDRESS);
6075 skip_emulated_instruction(vcpu);
6076 return 1;
6077 }
3573e22c 6078
4291b588
BD		 6079 if (vmptr == vmx->nested.vmxon_ptr) {
6080 nested_vmx_failValid(vcpu,
6081 VMXERR_VMCLEAR_VMXON_POINTER);
6082 skip_emulated_instruction(vcpu);
6083 return 1;
6084 }
6085 break;
3573e22c
BD		 6086 default:
6087 return 1; /* shouldn't happen */
6088 }
6089
4291b588
BD		 6090 if (vmpointer)
6091 *vmpointer = vmptr;
3573e22c
BD		 6092 return 0;
6093}
6094
ec378aee
NHE		 6095/*
6096 * Emulate the VMXON instruction.
6097 * Currently, we just remember that VMX is active, and do not save or even
6098 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6099 * do not currently need to store anything in that guest-allocated memory
6100 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6101 * argument is different from the VMXON pointer (which the spec says they do).
6102 */
6103static int handle_vmon(struct kvm_vcpu *vcpu)
6104{
6105 struct kvm_segment cs;
6106 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6107 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6108 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6109 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6110
6111 /* The Intel VMX Instruction Reference lists a bunch of bits that
6112 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6113 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6114 * Otherwise, we should fail with #UD. We test these now:
6115 */
6116 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6117 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6118 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6119 kvm_queue_exception(vcpu, UD_VECTOR);
6120 return 1;
6121 }
6122
6123 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6124 if (is_long_mode(vcpu) && !cs.l) {
6125 kvm_queue_exception(vcpu, UD_VECTOR);
6126 return 1;
6127 }
6128
6129 if (vmx_get_cpl(vcpu)) {
6130 kvm_inject_gp(vcpu, 0);
6131 return 1;
6132 }
3573e22c 6133
4291b588 6134 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6135 return 1;
6136
145c28dd
AG		 6137 if (vmx->nested.vmxon) {
6138 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6139 skip_emulated_instruction(vcpu);
6140 return 1;
6141 }
b3897a49
NHE		 6142
6143 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6144 != VMXON_NEEDED_FEATURES) {
6145 kvm_inject_gp(vcpu, 0);
6146 return 1;
6147 }
6148
8de48833
AG		 6149 if (enable_shadow_vmcs) {
6150 shadow_vmcs = alloc_vmcs();
6151 if (!shadow_vmcs)
6152 return -ENOMEM;
6153 /* mark vmcs as shadow */
6154 shadow_vmcs->revision_id |= (1u << 31);
6155 /* init shadow vmcs */
6156 vmcs_clear(shadow_vmcs);
6157 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6158 }
ec378aee 6159
ff2f6fe9
NHE		 6160 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6161 vmx->nested.vmcs02_num = 0;
6162
f4124500
JK		 6163 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6164 HRTIMER_MODE_REL);
6165 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6166
ec378aee
NHE		 6167 vmx->nested.vmxon = true;
6168
6169 skip_emulated_instruction(vcpu);
a25eb114 6170 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6171 return 1;
6172}
6173
6174/*
6175 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6176 * for running VMX instructions (except VMXON, whose prerequisites are
6177 * slightly different). It also specifies what exception to inject otherwise.
6178 */
6179static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6180{
6181 struct kvm_segment cs;
6182 struct vcpu_vmx *vmx = to_vmx(vcpu);
6183
6184 if (!vmx->nested.vmxon) {
6185 kvm_queue_exception(vcpu, UD_VECTOR);
6186 return 0;
6187 }
6188
6189 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6190 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6191 (is_long_mode(vcpu) && !cs.l)) {
6192 kvm_queue_exception(vcpu, UD_VECTOR);
6193 return 0;
6194 }
6195
6196 if (vmx_get_cpl(vcpu)) {
6197 kvm_inject_gp(vcpu, 0);
6198 return 0;
6199 }
6200
6201 return 1;
6202}
6203
e7953d7f
AG		 6204static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6205{
8a1b9dd0 6206 u32 exec_control;
9a2a05b9
PB		 6207 if (vmx->nested.current_vmptr == -1ull)
6208 return;
6209
6210 /* current_vmptr and current_vmcs12 are always set/reset together */
6211 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6212 return;
6213
012f83cb 6214 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6215 /* copy to memory all shadowed fields in case
6216 they were modified */
6217 copy_shadow_to_vmcs12(vmx);
6218 vmx->nested.sync_shadow_vmcs = false;
6219 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6220 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6221 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6222 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6223 }
e7953d7f
AG		 6224 kunmap(vmx->nested.current_vmcs12_page);
6225 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6226 vmx->nested.current_vmptr = -1ull;
6227 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6228}
6229
ec378aee
NHE		 6230/*
6231 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6232 * just stops using VMX.
6233 */
6234static void free_nested(struct vcpu_vmx *vmx)
6235{
6236 if (!vmx->nested.vmxon)
6237 return;
9a2a05b9 6238
ec378aee 6239 vmx->nested.vmxon = false;
9a2a05b9 6240 nested_release_vmcs12(vmx);
e7953d7f
AG		 6241 if (enable_shadow_vmcs)
6242 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6243 /* Unpin physical memory we referred to in current vmcs02 */
6244 if (vmx->nested.apic_access_page) {
6245 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6246 vmx->nested.apic_access_page = NULL;
fe3ef05c 6247 }
a7c0b07d
WL		 6248 if (vmx->nested.virtual_apic_page) {
6249 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6250 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6251 }
ff2f6fe9
NHE		 6252
6253 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6254}
6255
6256/* Emulate the VMXOFF instruction */
6257static int handle_vmoff(struct kvm_vcpu *vcpu)
6258{
6259 if (!nested_vmx_check_permission(vcpu))
6260 return 1;
6261 free_nested(to_vmx(vcpu));
6262 skip_emulated_instruction(vcpu);
a25eb114 6263 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6264 return 1;
6265}
6266
27d6c865
NHE		 6267/* Emulate the VMCLEAR instruction */
6268static int handle_vmclear(struct kvm_vcpu *vcpu)
6269{
6270 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6271 gpa_t vmptr;
6272 struct vmcs12 *vmcs12;
6273 struct page *page;
27d6c865
NHE		 6274
6275 if (!nested_vmx_check_permission(vcpu))
6276 return 1;
6277
4291b588 6278 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6279 return 1;
27d6c865 6280
9a2a05b9 6281 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6282 nested_release_vmcs12(vmx);
27d6c865
NHE		 6283
6284 page = nested_get_page(vcpu, vmptr);
6285 if (page == NULL) {
6286 /*
6287 * For accurate processor emulation, VMCLEAR beyond available
6288 * physical memory should do nothing at all. However, it is
6289 * possible that a nested vmx bug, not a guest hypervisor bug,
6290 * resulted in this case, so let's shut down before doing any
6291 * more damage:
6292 */
6293 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6294 return 1;
6295 }
6296 vmcs12 = kmap(page);
6297 vmcs12->launch_state = 0;
6298 kunmap(page);
6299 nested_release_page(page);
6300
6301 nested_free_vmcs02(vmx, vmptr);
6302
6303 skip_emulated_instruction(vcpu);
6304 nested_vmx_succeed(vcpu);
6305 return 1;
6306}
6307
cd232ad0
NHE		 6308static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6309
6310/* Emulate the VMLAUNCH instruction */
6311static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6312{
6313 return nested_vmx_run(vcpu, true);
6314}
6315
6316/* Emulate the VMRESUME instruction */
6317static int handle_vmresume(struct kvm_vcpu *vcpu)
6318{
6319
6320 return nested_vmx_run(vcpu, false);
6321}
6322
49f705c5
NHE		 6323enum vmcs_field_type {
6324 VMCS_FIELD_TYPE_U16 = 0,
6325 VMCS_FIELD_TYPE_U64 = 1,
6326 VMCS_FIELD_TYPE_U32 = 2,
6327 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6328};
6329
6330static inline int vmcs_field_type(unsigned long field)
6331{
6332 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6333 return VMCS_FIELD_TYPE_U32;
6334 return (field >> 13) & 0x3 ;
6335}
6336
6337static inline int vmcs_field_readonly(unsigned long field)
6338{
6339 return (((field >> 10) & 0x3) == 1);
6340}
6341
6342/*
6343 * Read a vmcs12 field. Since these can have varying lengths and we return
6344 * one type, we chose the biggest type (u64) and zero-extend the return value
6345 * to that size. Note that the caller, handle_vmread, might need to use only
6346 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6347 * 64-bit fields are to be returned).
6348 */
6349static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6350 unsigned long field, u64 *ret)
6351{
6352 short offset = vmcs_field_to_offset(field);
6353 char *p;
6354
6355 if (offset < 0)
6356 return 0;
6357
6358 p = ((char *)(get_vmcs12(vcpu))) + offset;
6359
6360 switch (vmcs_field_type(field)) {
6361 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6362 *ret = *((natural_width *)p);
6363 return 1;
6364 case VMCS_FIELD_TYPE_U16:
6365 *ret = *((u16 *)p);
6366 return 1;
6367 case VMCS_FIELD_TYPE_U32:
6368 *ret = *((u32 *)p);
6369 return 1;
6370 case VMCS_FIELD_TYPE_U64:
6371 *ret = *((u64 *)p);
6372 return 1;
6373 default:
6374 return 0; /* can never happen. */
6375 }
6376}
6377
20b97fea
AG		 6378
6379static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6380 unsigned long field, u64 field_value){
6381 short offset = vmcs_field_to_offset(field);
6382 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6383 if (offset < 0)
6384 return false;
6385
6386 switch (vmcs_field_type(field)) {
6387 case VMCS_FIELD_TYPE_U16:
6388 *(u16 *)p = field_value;
6389 return true;
6390 case VMCS_FIELD_TYPE_U32:
6391 *(u32 *)p = field_value;
6392 return true;
6393 case VMCS_FIELD_TYPE_U64:
6394 *(u64 *)p = field_value;
6395 return true;
6396 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6397 *(natural_width *)p = field_value;
6398 return true;
6399 default:
6400 return false; /* can never happen. */
6401 }
6402
6403}
6404
16f5b903
AG		 6405static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6406{
6407 int i;
6408 unsigned long field;
6409 u64 field_value;
6410 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6411 const unsigned long *fields = shadow_read_write_fields;
6412 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6413
6414 vmcs_load(shadow_vmcs);
6415
6416 for (i = 0; i < num_fields; i++) {
6417 field = fields[i];
6418 switch (vmcs_field_type(field)) {
6419 case VMCS_FIELD_TYPE_U16:
6420 field_value = vmcs_read16(field);
6421 break;
6422 case VMCS_FIELD_TYPE_U32:
6423 field_value = vmcs_read32(field);
6424 break;
6425 case VMCS_FIELD_TYPE_U64:
6426 field_value = vmcs_read64(field);
6427 break;
6428 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6429 field_value = vmcs_readl(field);
6430 break;
6431 }
6432 vmcs12_write_any(&vmx->vcpu, field, field_value);
6433 }
6434
6435 vmcs_clear(shadow_vmcs);
6436 vmcs_load(vmx->loaded_vmcs->vmcs);
6437}
6438
c3114420
AG		 6439static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6440{
c2bae893
MK		 6441 const unsigned long *fields[] = {
6442 shadow_read_write_fields,
6443 shadow_read_only_fields
c3114420 6444 };
c2bae893 6445 const int max_fields[] = {
c3114420
AG		 6446 max_shadow_read_write_fields,
6447 max_shadow_read_only_fields
6448 };
6449 int i, q;
6450 unsigned long field;
6451 u64 field_value = 0;
6452 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6453
6454 vmcs_load(shadow_vmcs);
6455
c2bae893 6456 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6457 for (i = 0; i < max_fields[q]; i++) {
6458 field = fields[q][i];
6459 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6460
6461 switch (vmcs_field_type(field)) {
6462 case VMCS_FIELD_TYPE_U16:
6463 vmcs_write16(field, (u16)field_value);
6464 break;
6465 case VMCS_FIELD_TYPE_U32:
6466 vmcs_write32(field, (u32)field_value);
6467 break;
6468 case VMCS_FIELD_TYPE_U64:
6469 vmcs_write64(field, (u64)field_value);
6470 break;
6471 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6472 vmcs_writel(field, (long)field_value);
6473 break;
6474 }
6475 }
6476 }
6477
6478 vmcs_clear(shadow_vmcs);
6479 vmcs_load(vmx->loaded_vmcs->vmcs);
6480}
6481
49f705c5
NHE		 6482/*
6483 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6484 * used before) all generate the same failure when it is missing.
6485 */
6486static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6487{
6488 struct vcpu_vmx *vmx = to_vmx(vcpu);
6489 if (vmx->nested.current_vmptr == -1ull) {
6490 nested_vmx_failInvalid(vcpu);
6491 skip_emulated_instruction(vcpu);
6492 return 0;
6493 }
6494 return 1;
6495}
6496
6497static int handle_vmread(struct kvm_vcpu *vcpu)
6498{
6499 unsigned long field;
6500 u64 field_value;
6501 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6502 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6503 gva_t gva = 0;
6504
6505 if (!nested_vmx_check_permission(vcpu) ||
6506 !nested_vmx_check_vmcs12(vcpu))
6507 return 1;
6508
6509 /* Decode instruction info and find the field to read */
27e6fb5d 6510 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6511 /* Read the field, zero-extended to a u64 field_value */
6512 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6513 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6514 skip_emulated_instruction(vcpu);
6515 return 1;
6516 }
6517 /*
6518 * Now copy part of this value to register or memory, as requested.
6519 * Note that the number of bits actually copied is 32 or 64 depending
6520 * on the guest's mode (32 or 64 bit), not on the given field's length.
6521 */
6522 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6523 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6524 field_value);
6525 } else {
6526 if (get_vmx_mem_address(vcpu, exit_qualification,
6527 vmx_instruction_info, &gva))
6528 return 1;
6529 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6530 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6531 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6532 }
6533
6534 nested_vmx_succeed(vcpu);
6535 skip_emulated_instruction(vcpu);
6536 return 1;
6537}
6538
6539
6540static int handle_vmwrite(struct kvm_vcpu *vcpu)
6541{
6542 unsigned long field;
6543 gva_t gva;
6544 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6545 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6546 /* The value to write might be 32 or 64 bits, depending on L1's long
6547 * mode, and eventually we need to write that into a field of several
6548 * possible lengths. The code below first zero-extends the value to 64
6549 * bit (field_value), and then copies only the approriate number of
6550 * bits into the vmcs12 field.
6551 */
6552 u64 field_value = 0;
6553 struct x86_exception e;
6554
6555 if (!nested_vmx_check_permission(vcpu) ||
6556 !nested_vmx_check_vmcs12(vcpu))
6557 return 1;
6558
6559 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6560 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6561 (((vmx_instruction_info) >> 3) & 0xf));
6562 else {
6563 if (get_vmx_mem_address(vcpu, exit_qualification,
6564 vmx_instruction_info, &gva))
6565 return 1;
6566 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6567 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6568 kvm_inject_page_fault(vcpu, &e);
6569 return 1;
6570 }
6571 }
6572
6573
27e6fb5d 6574 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6575 if (vmcs_field_readonly(field)) {
6576 nested_vmx_failValid(vcpu,
6577 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6578 skip_emulated_instruction(vcpu);
6579 return 1;
6580 }
6581
20b97fea 6582 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6583 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6584 skip_emulated_instruction(vcpu);
6585 return 1;
6586 }
6587
6588 nested_vmx_succeed(vcpu);
6589 skip_emulated_instruction(vcpu);
6590 return 1;
6591}
6592
63846663
NHE		 6593/* Emulate the VMPTRLD instruction */
6594static int handle_vmptrld(struct kvm_vcpu *vcpu)
6595{
6596 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6597 gpa_t vmptr;
8a1b9dd0 6598 u32 exec_control;
63846663
NHE		 6599
6600 if (!nested_vmx_check_permission(vcpu))
6601 return 1;
6602
4291b588 6603 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6604 return 1;
63846663
NHE		 6605
6606 if (vmx->nested.current_vmptr != vmptr) {
6607 struct vmcs12 *new_vmcs12;
6608 struct page *page;
6609 page = nested_get_page(vcpu, vmptr);
6610 if (page == NULL) {
6611 nested_vmx_failInvalid(vcpu);
6612 skip_emulated_instruction(vcpu);
6613 return 1;
6614 }
6615 new_vmcs12 = kmap(page);
6616 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6617 kunmap(page);
6618 nested_release_page_clean(page);
6619 nested_vmx_failValid(vcpu,
6620 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6621 skip_emulated_instruction(vcpu);
6622 return 1;
6623 }
63846663 6624
9a2a05b9 6625 nested_release_vmcs12(vmx);
63846663
NHE		 6626 vmx->nested.current_vmptr = vmptr;
6627 vmx->nested.current_vmcs12 = new_vmcs12;
6628 vmx->nested.current_vmcs12_page = page;
012f83cb 6629 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6630 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6631 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6632 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6633 vmcs_write64(VMCS_LINK_POINTER,
6634 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6635 vmx->nested.sync_shadow_vmcs = true;
6636 }
63846663
NHE		 6637 }
6638
6639 nested_vmx_succeed(vcpu);
6640 skip_emulated_instruction(vcpu);
6641 return 1;
6642}
6643
6a4d7550
NHE		 6644/* Emulate the VMPTRST instruction */
6645static int handle_vmptrst(struct kvm_vcpu *vcpu)
6646{
6647 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6648 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6649 gva_t vmcs_gva;
6650 struct x86_exception e;
6651
6652 if (!nested_vmx_check_permission(vcpu))
6653 return 1;
6654
6655 if (get_vmx_mem_address(vcpu, exit_qualification,
6656 vmx_instruction_info, &vmcs_gva))
6657 return 1;
6658 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6659 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6660 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6661 sizeof(u64), &e)) {
6662 kvm_inject_page_fault(vcpu, &e);
6663 return 1;
6664 }
6665 nested_vmx_succeed(vcpu);
6666 skip_emulated_instruction(vcpu);
6667 return 1;
6668}
6669
bfd0a56b
NHE		 6670/* Emulate the INVEPT instruction */
6671static int handle_invept(struct kvm_vcpu *vcpu)
6672{
6673 u32 vmx_instruction_info, types;
6674 unsigned long type;
6675 gva_t gva;
6676 struct x86_exception e;
6677 struct {
6678 u64 eptp, gpa;
6679 } operand;
bfd0a56b
NHE		 6680
6681 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6682 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6683 kvm_queue_exception(vcpu, UD_VECTOR);
6684 return 1;
6685 }
6686
6687 if (!nested_vmx_check_permission(vcpu))
6688 return 1;
6689
6690 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6691 kvm_queue_exception(vcpu, UD_VECTOR);
6692 return 1;
6693 }
6694
6695 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6696 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6697
6698 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6699
6700 if (!(types & (1UL << type))) {
6701 nested_vmx_failValid(vcpu,
6702 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6703 return 1;
6704 }
6705
6706 /* According to the Intel VMX instruction reference, the memory
6707 * operand is read even if it isn't needed (e.g., for type==global)
6708 */
6709 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6710 vmx_instruction_info, &gva))
6711 return 1;
6712 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6713 sizeof(operand), &e)) {
6714 kvm_inject_page_fault(vcpu, &e);
6715 return 1;
6716 }
6717
6718 switch (type) {
bfd0a56b
NHE		 6719 case VMX_EPT_EXTENT_GLOBAL:
6720 kvm_mmu_sync_roots(vcpu);
6721 kvm_mmu_flush_tlb(vcpu);
6722 nested_vmx_succeed(vcpu);
6723 break;
6724 default:
4b855078 6725 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6726 BUG_ON(1);
6727 break;
6728 }
6729
6730 skip_emulated_instruction(vcpu);
6731 return 1;
6732}
6733
6aa8b732
AK		 6734/*
6735 * The exit handlers return 1 if the exit was handled fully and guest execution
6736 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6737 * to be done to userspace and return 0.
6738 */
772e0318 6739static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6740 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6741 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6742 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6743 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6744 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6745 [EXIT_REASON_CR_ACCESS] = handle_cr,
6746 [EXIT_REASON_DR_ACCESS] = handle_dr,
6747 [EXIT_REASON_CPUID] = handle_cpuid,
6748 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6749 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6750 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6751 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6752 [EXIT_REASON_INVD] = handle_invd,
a7052897 6753 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6754 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6755 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6756 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6757 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6758 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6759 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6760 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6761 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6762 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6763 [EXIT_REASON_VMOFF] = handle_vmoff,
6764 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6765 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6766 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6767 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6768 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6769 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6770 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6771 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6772 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6773 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6774 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6775 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6776 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6777 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6778 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6779};
6780
6781static const int kvm_vmx_max_exit_handlers =
50a3485c 6782 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6783
908a7bdd
JK		 6784static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6785 struct vmcs12 *vmcs12)
6786{
6787 unsigned long exit_qualification;
6788 gpa_t bitmap, last_bitmap;
6789 unsigned int port;
6790 int size;
6791 u8 b;
6792
908a7bdd 6793 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6794 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6795
6796 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6797
6798 port = exit_qualification >> 16;
6799 size = (exit_qualification & 7) + 1;
6800
6801 last_bitmap = (gpa_t)-1;
6802 b = -1;
6803
6804 while (size > 0) {
6805 if (port < 0x8000)
6806 bitmap = vmcs12->io_bitmap_a;
6807 else if (port < 0x10000)
6808 bitmap = vmcs12->io_bitmap_b;
6809 else
6810 return 1;
6811 bitmap += (port & 0x7fff) / 8;
6812
6813 if (last_bitmap != bitmap)
6814 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6815 return 1;
6816 if (b & (1 << (port & 7)))
6817 return 1;
6818
6819 port++;
6820 size--;
6821 last_bitmap = bitmap;
6822 }
6823
6824 return 0;
6825}
6826
644d711a
NHE		 6827/*
6828 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6829 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6830 * disinterest in the current event (read or write a specific MSR) by using an
6831 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6832 */
6833static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6834 struct vmcs12 *vmcs12, u32 exit_reason)
6835{
6836 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6837 gpa_t bitmap;
6838
cbd29cb6 6839 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6840 return 1;
6841
6842 /*
6843 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6844 * for the four combinations of read/write and low/high MSR numbers.
6845 * First we need to figure out which of the four to use:
6846 */
6847 bitmap = vmcs12->msr_bitmap;
6848 if (exit_reason == EXIT_REASON_MSR_WRITE)
6849 bitmap += 2048;
6850 if (msr_index >= 0xc0000000) {
6851 msr_index -= 0xc0000000;
6852 bitmap += 1024;
6853 }
6854
6855 /* Then read the msr_index'th bit from this bitmap: */
6856 if (msr_index < 1024*8) {
6857 unsigned char b;
bd31a7f5
JK		 6858 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6859 return 1;
644d711a
NHE		 6860 return 1 & (b >> (msr_index & 7));
6861 } else
6862 return 1; /* let L1 handle the wrong parameter */
6863}
6864
6865/*
6866 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6867 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6868 * intercept (via guest_host_mask etc.) the current event.
6869 */
6870static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6871 struct vmcs12 *vmcs12)
6872{
6873 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6874 int cr = exit_qualification & 15;
6875 int reg = (exit_qualification >> 8) & 15;
1e32c079 6876 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6877
6878 switch ((exit_qualification >> 4) & 3) {
6879 case 0: /* mov to cr */
6880 switch (cr) {
6881 case 0:
6882 if (vmcs12->cr0_guest_host_mask &
6883 (val ^ vmcs12->cr0_read_shadow))
6884 return 1;
6885 break;
6886 case 3:
6887 if ((vmcs12->cr3_target_count >= 1 &&
6888 vmcs12->cr3_target_value0 == val) ||
6889 (vmcs12->cr3_target_count >= 2 &&
6890 vmcs12->cr3_target_value1 == val) ||
6891 (vmcs12->cr3_target_count >= 3 &&
6892 vmcs12->cr3_target_value2 == val) ||
6893 (vmcs12->cr3_target_count >= 4 &&
6894 vmcs12->cr3_target_value3 == val))
6895 return 0;
6896 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6897 return 1;
6898 break;
6899 case 4:
6900 if (vmcs12->cr4_guest_host_mask &
6901 (vmcs12->cr4_read_shadow ^ val))
6902 return 1;
6903 break;
6904 case 8:
6905 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6906 return 1;
6907 break;
6908 }
6909 break;
6910 case 2: /* clts */
6911 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6912 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6913 return 1;
6914 break;
6915 case 1: /* mov from cr */
6916 switch (cr) {
6917 case 3:
6918 if (vmcs12->cpu_based_vm_exec_control &
6919 CPU_BASED_CR3_STORE_EXITING)
6920 return 1;
6921 break;
6922 case 8:
6923 if (vmcs12->cpu_based_vm_exec_control &
6924 CPU_BASED_CR8_STORE_EXITING)
6925 return 1;
6926 break;
6927 }
6928 break;
6929 case 3: /* lmsw */
6930 /*
6931 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6932 * cr0. Other attempted changes are ignored, with no exit.
6933 */
6934 if (vmcs12->cr0_guest_host_mask & 0xe &
6935 (val ^ vmcs12->cr0_read_shadow))
6936 return 1;
6937 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6938 !(vmcs12->cr0_read_shadow & 0x1) &&
6939 (val & 0x1))
6940 return 1;
6941 break;
6942 }
6943 return 0;
6944}
6945
6946/*
6947 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6948 * should handle it ourselves in L0 (and then continue L2). Only call this
6949 * when in is_guest_mode (L2).
6950 */
6951static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6952{
644d711a
NHE		 6953 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6954 struct vcpu_vmx *vmx = to_vmx(vcpu);
6955 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6956 u32 exit_reason = vmx->exit_reason;
644d711a 6957
542060ea
JK		 6958 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6959 vmcs_readl(EXIT_QUALIFICATION),
6960 vmx->idt_vectoring_info,
6961 intr_info,
6962 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6963 KVM_ISA_VMX);
6964
644d711a
NHE		 6965 if (vmx->nested.nested_run_pending)
6966 return 0;
6967
6968 if (unlikely(vmx->fail)) {
bd80158a
JK		 6969 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6970 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6971 return 1;
6972 }
6973
6974 switch (exit_reason) {
6975 case EXIT_REASON_EXCEPTION_NMI:
6976 if (!is_exception(intr_info))
6977 return 0;
6978 else if (is_page_fault(intr_info))
6979 return enable_ept;
e504c909 6980 else if (is_no_device(intr_info) &&
ccf9844e 6981 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6982 return 0;
644d711a
NHE		 6983 return vmcs12->exception_bitmap &
6984 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6985 case EXIT_REASON_EXTERNAL_INTERRUPT:
6986 return 0;
6987 case EXIT_REASON_TRIPLE_FAULT:
6988 return 1;
6989 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6990 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6991 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6992 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6993 case EXIT_REASON_TASK_SWITCH:
6994 return 1;
6995 case EXIT_REASON_CPUID:
6996 return 1;
6997 case EXIT_REASON_HLT:
6998 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6999 case EXIT_REASON_INVD:
7000 return 1;
7001 case EXIT_REASON_INVLPG:
7002 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7003 case EXIT_REASON_RDPMC:
7004 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7005 case EXIT_REASON_RDTSC:
7006 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7007 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7008 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7009 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7010 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7011 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 7012 case EXIT_REASON_INVEPT:
644d711a
NHE		 7013 /*
7014 * VMX instructions trap unconditionally. This allows L1 to
7015 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7016 */
7017 return 1;
7018 case EXIT_REASON_CR_ACCESS:
7019 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7020 case EXIT_REASON_DR_ACCESS:
7021 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7022 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7023 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7024 case EXIT_REASON_MSR_READ:
7025 case EXIT_REASON_MSR_WRITE:
7026 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7027 case EXIT_REASON_INVALID_STATE:
7028 return 1;
7029 case EXIT_REASON_MWAIT_INSTRUCTION:
7030 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7031 case EXIT_REASON_MONITOR_INSTRUCTION:
7032 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7033 case EXIT_REASON_PAUSE_INSTRUCTION:
7034 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7035 nested_cpu_has2(vmcs12,
7036 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7037 case EXIT_REASON_MCE_DURING_VMENTRY:
7038 return 0;
7039 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7040 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7041 case EXIT_REASON_APIC_ACCESS:
7042 return nested_cpu_has2(vmcs12,
7043 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7044 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7045 /*
7046 * L0 always deals with the EPT violation. If nested EPT is
7047 * used, and the nested mmu code discovers that the address is
7048 * missing in the guest EPT table (EPT12), the EPT violation
7049 * will be injected with nested_ept_inject_page_fault()
7050 */
7051 return 0;
644d711a 7052 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7053 /*
7054 * L2 never uses directly L1's EPT, but rather L0's own EPT
7055 * table (shadow on EPT) or a merged EPT table that L0 built
7056 * (EPT on EPT). So any problems with the structure of the
7057 * table is L0's fault.
7058 */
644d711a
NHE		 7059 return 0;
7060 case EXIT_REASON_WBINVD:
7061 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7062 case EXIT_REASON_XSETBV:
7063 return 1;
7064 default:
7065 return 1;
7066 }
7067}
7068
586f9607
AK		 7069static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7070{
7071 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7072 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7073}
7074
6aa8b732
AK		 7075/*
7076 * The guest has exited. See if we can fix it or if we need userspace
7077 * assistance.
7078 */
851ba692 7079static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7080{
29bd8a78 7081 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7082 u32 exit_reason = vmx->exit_reason;
1155f76a 7083 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7084
80ced186 7085 /* If guest state is invalid, start emulating */
14168786 7086 if (vmx->emulation_required)
80ced186 7087 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7088
644d711a 7089 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7090 nested_vmx_vmexit(vcpu, exit_reason,
7091 vmcs_read32(VM_EXIT_INTR_INFO),
7092 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7093 return 1;
7094 }
7095
5120702e
MG		 7096 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7097 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7098 vcpu->run->fail_entry.hardware_entry_failure_reason
7099 = exit_reason;
7100 return 0;
7101 }
7102
29bd8a78 7103 if (unlikely(vmx->fail)) {
851ba692
AK		 7104 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7105 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7106 = vmcs_read32(VM_INSTRUCTION_ERROR);
7107 return 0;
7108 }
6aa8b732 7109
b9bf6882
XG		 7110 /*
7111 * Note:
7112 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7113 * delivery event since it indicates guest is accessing MMIO.
7114 * The vm-exit can be triggered again after return to guest that
7115 * will cause infinite loop.
7116 */
d77c26fc 7117 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7118 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7119 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7120 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7121 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7122 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7123 vcpu->run->internal.ndata = 2;
7124 vcpu->run->internal.data[0] = vectoring_info;
7125 vcpu->run->internal.data[1] = exit_reason;
7126 return 0;
7127 }
3b86cd99 7128
644d711a
NHE		 7129 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7130 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7131 get_vmcs12(vcpu))))) {
c4282df9 7132 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7133 vmx->soft_vnmi_blocked = 0;
3b86cd99 7134 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7135 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7136 /*
7137 * This CPU don't support us in finding the end of an
7138 * NMI-blocked window if the guest runs with IRQs
7139 * disabled. So we pull the trigger after 1 s of
7140 * futile waiting, but inform the user about this.
7141 */
7142 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7143 "state on VCPU %d after 1 s timeout\n",
7144 __func__, vcpu->vcpu_id);
7145 vmx->soft_vnmi_blocked = 0;
3b86cd99 7146 }
3b86cd99
JK		 7147 }
7148
6aa8b732
AK		 7149 if (exit_reason < kvm_vmx_max_exit_handlers
7150 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7151 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7152 else {
851ba692
AK		 7153 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7154 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7155 }
7156 return 0;
7157}
7158
95ba8273 7159static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7160{
a7c0b07d
WL		 7161 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7162
7163 if (is_guest_mode(vcpu) &&
7164 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7165 return;
7166
95ba8273 7167 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7168 vmcs_write32(TPR_THRESHOLD, 0);
7169 return;
7170 }
7171
95ba8273 7172 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7173}
7174
8d14695f
YZ		 7175static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7176{
7177 u32 sec_exec_control;
7178
7179 /*
7180 * There is not point to enable virtualize x2apic without enable
7181 * apicv
7182 */
c7c9c56c
YZ		 7183 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7184 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7185 return;
7186
7187 if (!vm_need_tpr_shadow(vcpu->kvm))
7188 return;
7189
7190 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7191
7192 if (set) {
7193 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7194 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7195 } else {
7196 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7197 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7198 }
7199 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7200
7201 vmx_set_msr_bitmap(vcpu);
7202}
7203
c7c9c56c
YZ		 7204static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7205{
7206 u16 status;
7207 u8 old;
7208
7209 if (!vmx_vm_has_apicv(kvm))
7210 return;
7211
7212 if (isr == -1)
7213 isr = 0;
7214
7215 status = vmcs_read16(GUEST_INTR_STATUS);
7216 old = status >> 8;
7217 if (isr != old) {
7218 status &= 0xff;
7219 status |= isr << 8;
7220 vmcs_write16(GUEST_INTR_STATUS, status);
7221 }
7222}
7223
7224static void vmx_set_rvi(int vector)
7225{
7226 u16 status;
7227 u8 old;
7228
7229 status = vmcs_read16(GUEST_INTR_STATUS);
7230 old = (u8)status & 0xff;
7231 if ((u8)vector != old) {
7232 status &= ~0xff;
7233 status |= (u8)vector;
7234 vmcs_write16(GUEST_INTR_STATUS, status);
7235 }
7236}
7237
7238static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7239{
7240 if (max_irr == -1)
7241 return;
7242
963fee16
WL		 7243 /*
7244 * If a vmexit is needed, vmx_check_nested_events handles it.
7245 */
7246 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7247 return;
7248
7249 if (!is_guest_mode(vcpu)) {
7250 vmx_set_rvi(max_irr);
7251 return;
7252 }
7253
7254 /*
7255 * Fall back to pre-APICv interrupt injection since L2
7256 * is run without virtual interrupt delivery.
7257 */
7258 if (!kvm_event_needs_reinjection(vcpu) &&
7259 vmx_interrupt_allowed(vcpu)) {
7260 kvm_queue_interrupt(vcpu, max_irr, false);
7261 vmx_inject_irq(vcpu);
7262 }
c7c9c56c
YZ		 7263}
7264
7265static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7266{
3d81bc7e
YZ		 7267 if (!vmx_vm_has_apicv(vcpu->kvm))
7268 return;
7269
c7c9c56c
YZ		 7270 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7271 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7272 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7273 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7274}
7275
51aa01d1 7276static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7277{
00eba012
AK		 7278 u32 exit_intr_info;
7279
7280 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7281 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7282 return;
7283
c5ca8e57 7284 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7285 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7286
7287 /* Handle machine checks before interrupts are enabled */
00eba012 7288 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7289 kvm_machine_check();
7290
20f65983 7291 /* We need to handle NMIs before interrupts are enabled */
00eba012 7292 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7293 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7294 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7295 asm("int $2");
ff9d07a0
ZY		 7296 kvm_after_handle_nmi(&vmx->vcpu);
7297 }
51aa01d1 7298}
20f65983 7299
a547c6db
YZ		 7300static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7301{
7302 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7303
7304 /*
7305 * If external interrupt exists, IF bit is set in rflags/eflags on the
7306 * interrupt stack frame, and interrupt will be enabled on a return
7307 * from interrupt handler.
7308 */
7309 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7310 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7311 unsigned int vector;
7312 unsigned long entry;
7313 gate_desc *desc;
7314 struct vcpu_vmx *vmx = to_vmx(vcpu);
7315#ifdef CONFIG_X86_64
7316 unsigned long tmp;
7317#endif
7318
7319 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7320 desc = (gate_desc *)vmx->host_idt_base + vector;
7321 entry = gate_offset(*desc);
7322 asm volatile(
7323#ifdef CONFIG_X86_64
7324 "mov %%" _ASM_SP ", %[sp]\n\t"
7325 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7326 "push $%c[ss]\n\t"
7327 "push %[sp]\n\t"
7328#endif
7329 "pushf\n\t"
7330 "orl $0x200, (%%" _ASM_SP ")\n\t"
7331 __ASM_SIZE(push) " $%c[cs]\n\t"
7332 "call *%[entry]\n\t"
7333 :
7334#ifdef CONFIG_X86_64
7335 [sp]"=&r"(tmp)
7336#endif
7337 :
7338 [entry]"r"(entry),
7339 [ss]"i"(__KERNEL_DS),
7340 [cs]"i"(__KERNEL_CS)
7341 );
7342 } else
7343 local_irq_enable();
7344}
7345
da8999d3
LJ		 7346static bool vmx_mpx_supported(void)
7347{
7348 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7349 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7350}
7351
51aa01d1
AK		 7352static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7353{
c5ca8e57 7354 u32 exit_intr_info;
51aa01d1
AK		 7355 bool unblock_nmi;
7356 u8 vector;
7357 bool idtv_info_valid;
7358
7359 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7360
cf393f75 7361 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7362 if (vmx->nmi_known_unmasked)
7363 return;
c5ca8e57
AK		 7364 /*
7365 * Can't use vmx->exit_intr_info since we're not sure what
7366 * the exit reason is.
7367 */
7368 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7369 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7370 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7371 /*
7b4a25cb 7372 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7373 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7374 * a guest IRET fault.
7b4a25cb
GN		 7375 * SDM 3: 23.2.2 (September 2008)
7376 * Bit 12 is undefined in any of the following cases:
7377 * If the VM exit sets the valid bit in the IDT-vectoring
7378 * information field.
7379 * If the VM exit is due to a double fault.
cf393f75 7380 */
7b4a25cb
GN		 7381 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7382 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7383 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7384 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7385 else
7386 vmx->nmi_known_unmasked =
7387 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7388 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7389 } else if (unlikely(vmx->soft_vnmi_blocked))
7390 vmx->vnmi_blocked_time +=
7391 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7392}
7393
3ab66e8a 7394static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7395 u32 idt_vectoring_info,
7396 int instr_len_field,
7397 int error_code_field)
51aa01d1 7398{
51aa01d1
AK		 7399 u8 vector;
7400 int type;
7401 bool idtv_info_valid;
7402
7403 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7404
3ab66e8a
JK		 7405 vcpu->arch.nmi_injected = false;
7406 kvm_clear_exception_queue(vcpu);
7407 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7408
7409 if (!idtv_info_valid)
7410 return;
7411
3ab66e8a 7412 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7413
668f612f
AK		 7414 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7415 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7416
64a7ec06 7417 switch (type) {
37b96e98 7418 case INTR_TYPE_NMI_INTR:
3ab66e8a 7419 vcpu->arch.nmi_injected = true;
668f612f 7420 /*
7b4a25cb 7421 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7422 * Clear bit "block by NMI" before VM entry if a NMI
7423 * delivery faulted.
668f612f 7424 */
3ab66e8a 7425 vmx_set_nmi_mask(vcpu, false);
37b96e98 7426 break;
37b96e98 7427 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7428 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7429 /* fall through */
7430 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7431 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7432 u32 err = vmcs_read32(error_code_field);
851eb667 7433 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7434 } else
851eb667 7435 kvm_requeue_exception(vcpu, vector);
37b96e98 7436 break;
66fd3f7f 7437 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7438 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7439 /* fall through */
37b96e98 7440 case INTR_TYPE_EXT_INTR:
3ab66e8a 7441 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7442 break;
7443 default:
7444 break;
f7d9238f 7445 }
cf393f75
AK		 7446}
7447
83422e17
AK		 7448static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7449{
3ab66e8a 7450 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7451 VM_EXIT_INSTRUCTION_LEN,
7452 IDT_VECTORING_ERROR_CODE);
7453}
7454
b463a6f7
AK		 7455static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7456{
3ab66e8a 7457 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7458 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7459 VM_ENTRY_INSTRUCTION_LEN,
7460 VM_ENTRY_EXCEPTION_ERROR_CODE);
7461
7462 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7463}
7464
d7cd9796
GN		 7465static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7466{
7467 int i, nr_msrs;
7468 struct perf_guest_switch_msr *msrs;
7469
7470 msrs = perf_guest_get_msrs(&nr_msrs);
7471
7472 if (!msrs)
7473 return;
7474
7475 for (i = 0; i < nr_msrs; i++)
7476 if (msrs[i].host == msrs[i].guest)
7477 clear_atomic_switch_msr(vmx, msrs[i].msr);
7478 else
7479 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7480 msrs[i].host);
7481}
7482
a3b5ba49 7483static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7484{
a2fa3e9f 7485 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7486 unsigned long debugctlmsr;
104f226b
AK		 7487
7488 /* Record the guest's net vcpu time for enforced NMI injections. */
7489 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7490 vmx->entry_time = ktime_get();
7491
7492 /* Don't enter VMX if guest state is invalid, let the exit handler
7493 start emulation until we arrive back to a valid state */
14168786 7494 if (vmx->emulation_required)
104f226b
AK		 7495 return;
7496
a7653ecd
RK		 7497 if (vmx->ple_window_dirty) {
7498 vmx->ple_window_dirty = false;
7499 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7500 }
7501
012f83cb
AG		 7502 if (vmx->nested.sync_shadow_vmcs) {
7503 copy_vmcs12_to_shadow(vmx);
7504 vmx->nested.sync_shadow_vmcs = false;
7505 }
7506
104f226b
AK		 7507 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7508 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7509 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7510 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7511
7512 /* When single-stepping over STI and MOV SS, we must clear the
7513 * corresponding interruptibility bits in the guest state. Otherwise
7514 * vmentry fails as it then expects bit 14 (BS) in pending debug
7515 * exceptions being set, but that's not correct for the guest debugging
7516 * case. */
7517 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7518 vmx_set_interrupt_shadow(vcpu, 0);
7519
d7cd9796 7520 atomic_switch_perf_msrs(vmx);
2a7921b7 7521 debugctlmsr = get_debugctlmsr();
d7cd9796 7522
d462b819 7523 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7524 asm(
6aa8b732 7525 /* Store host registers */
b188c81f
AK		 7526 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7527 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7528 "push %%" _ASM_CX " \n\t"
7529 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7530 "je 1f \n\t"
b188c81f 7531 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7532 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7533 "1: \n\t"
d3edefc0 7534 /* Reload cr2 if changed */
b188c81f
AK		 7535 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7536 "mov %%cr2, %%" _ASM_DX " \n\t"
7537 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7538 "je 2f \n\t"
b188c81f 7539 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7540 "2: \n\t"
6aa8b732 7541 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7542 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7543 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7544 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7545 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7546 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7547 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7548 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7549 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7550#ifdef CONFIG_X86_64
e08aa78a
AK		 7551 "mov %c[r8](%0), %%r8 \n\t"
7552 "mov %c[r9](%0), %%r9 \n\t"
7553 "mov %c[r10](%0), %%r10 \n\t"
7554 "mov %c[r11](%0), %%r11 \n\t"
7555 "mov %c[r12](%0), %%r12 \n\t"
7556 "mov %c[r13](%0), %%r13 \n\t"
7557 "mov %c[r14](%0), %%r14 \n\t"
7558 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7559#endif
b188c81f 7560 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7561
6aa8b732 7562 /* Enter guest mode */
83287ea4 7563 "jne 1f \n\t"
4ecac3fd 7564 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7565 "jmp 2f \n\t"
7566 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7567 "2: "
6aa8b732 7568 /* Save guest registers, load host registers, keep flags */
b188c81f 7569 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7570 "pop %0 \n\t"
b188c81f
AK		 7571 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7572 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7573 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7574 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7575 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7576 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7577 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7578#ifdef CONFIG_X86_64
e08aa78a
AK		 7579 "mov %%r8, %c[r8](%0) \n\t"
7580 "mov %%r9, %c[r9](%0) \n\t"
7581 "mov %%r10, %c[r10](%0) \n\t"
7582 "mov %%r11, %c[r11](%0) \n\t"
7583 "mov %%r12, %c[r12](%0) \n\t"
7584 "mov %%r13, %c[r13](%0) \n\t"
7585 "mov %%r14, %c[r14](%0) \n\t"
7586 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7587#endif
b188c81f
AK		 7588 "mov %%cr2, %%" _ASM_AX " \n\t"
7589 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7590
b188c81f 7591 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7592 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7593 ".pushsection .rodata \n\t"
7594 ".global vmx_return \n\t"
7595 "vmx_return: " _ASM_PTR " 2b \n\t"
7596 ".popsection"
e08aa78a 7597 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7598 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7599 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7600 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7601 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7602 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7603 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7604 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7605 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7606 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7607 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7608#ifdef CONFIG_X86_64
ad312c7c
ZX		 7609 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7610 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7611 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7612 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7613 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7614 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7615 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7616 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7617#endif
40712fae
AK		 7618 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7619 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7620 : "cc", "memory"
7621#ifdef CONFIG_X86_64
b188c81f 7622 , "rax", "rbx", "rdi", "rsi"
c2036300 7623 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7624#else
7625 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7626#endif
7627 );
6aa8b732 7628
2a7921b7
GN		 7629 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7630 if (debugctlmsr)
7631 update_debugctlmsr(debugctlmsr);
7632
aa67f609
AK		 7633#ifndef CONFIG_X86_64
7634 /*
7635 * The sysexit path does not restore ds/es, so we must set them to
7636 * a reasonable value ourselves.
7637 *
7638 * We can't defer this to vmx_load_host_state() since that function
7639 * may be executed in interrupt context, which saves and restore segments
7640 * around it, nullifying its effect.
7641 */
7642 loadsegment(ds, __USER_DS);
7643 loadsegment(es, __USER_DS);
7644#endif
7645
6de4f3ad 7646 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7647 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7648 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7649 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7650 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7651 vcpu->arch.regs_dirty = 0;
7652
1155f76a
AK		 7653 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7654
d462b819 7655 vmx->loaded_vmcs->launched = 1;
1b6269db 7656
51aa01d1 7657 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7658 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7659
e0b890d3
GN		 7660 /*
7661 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7662 * we did not inject a still-pending event to L1 now because of
7663 * nested_run_pending, we need to re-enable this bit.
7664 */
7665 if (vmx->nested.nested_run_pending)
7666 kvm_make_request(KVM_REQ_EVENT, vcpu);
7667
7668 vmx->nested.nested_run_pending = 0;
7669
51aa01d1
AK		 7670 vmx_complete_atomic_exit(vmx);
7671 vmx_recover_nmi_blocking(vmx);
cf393f75 7672 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7673}
7674
4fa7734c
PB		 7675static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7676{
7677 struct vcpu_vmx *vmx = to_vmx(vcpu);
7678 int cpu;
7679
7680 if (vmx->loaded_vmcs == &vmx->vmcs01)
7681 return;
7682
7683 cpu = get_cpu();
7684 vmx->loaded_vmcs = &vmx->vmcs01;
7685 vmx_vcpu_put(vcpu);
7686 vmx_vcpu_load(vcpu, cpu);
7687 vcpu->cpu = cpu;
7688 put_cpu();
7689}
7690
6aa8b732
AK		 7691static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7692{
fb3f0f51
RR		 7693 struct vcpu_vmx *vmx = to_vmx(vcpu);
7694
cdbecfc3 7695 free_vpid(vmx);
4fa7734c
PB		 7696 leave_guest_mode(vcpu);
7697 vmx_load_vmcs01(vcpu);
26a865f4 7698 free_nested(vmx);
4fa7734c 7699 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7700 kfree(vmx->guest_msrs);
7701 kvm_vcpu_uninit(vcpu);
a4770347 7702 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7703}
7704
fb3f0f51 7705static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7706{
fb3f0f51 7707 int err;
c16f862d 7708 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7709 int cpu;
6aa8b732 7710
a2fa3e9f 7711 if (!vmx)
fb3f0f51
RR		 7712 return ERR_PTR(-ENOMEM);
7713
2384d2b3
SY		 7714 allocate_vpid(vmx);
7715
fb3f0f51
RR		 7716 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7717 if (err)
7718 goto free_vcpu;
965b58a5 7719
a2fa3e9f 7720 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7721 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7722 > PAGE_SIZE);
0123be42 7723
be6d05cf 7724 err = -ENOMEM;
fb3f0f51 7725 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7726 goto uninit_vcpu;
7727 }
965b58a5 7728
d462b819
NHE		 7729 vmx->loaded_vmcs = &vmx->vmcs01;
7730 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7731 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7732 goto free_msrs;
d462b819
NHE		 7733 if (!vmm_exclusive)
7734 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7735 loaded_vmcs_init(vmx->loaded_vmcs);
7736 if (!vmm_exclusive)
7737 kvm_cpu_vmxoff();
a2fa3e9f 7738
15ad7146
AK		 7739 cpu = get_cpu();
7740 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7741 vmx->vcpu.cpu = cpu;
8b9cf98c 7742 err = vmx_vcpu_setup(vmx);
fb3f0f51 7743 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7744 put_cpu();
fb3f0f51
RR		 7745 if (err)
7746 goto free_vmcs;
a63cb560 7747 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7748 err = alloc_apic_access_page(kvm);
7749 if (err)
5e4a0b3c 7750 goto free_vmcs;
a63cb560 7751 }
fb3f0f51 7752
b927a3ce
SY		 7753 if (enable_ept) {
7754 if (!kvm->arch.ept_identity_map_addr)
7755 kvm->arch.ept_identity_map_addr =
7756 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7757 err = init_rmode_identity_map(kvm);
7758 if (err)
93ea5388 7759 goto free_vmcs;
b927a3ce 7760 }
b7ebfb05 7761
a9d30f33
NHE		 7762 vmx->nested.current_vmptr = -1ull;
7763 vmx->nested.current_vmcs12 = NULL;
7764
fb3f0f51
RR		 7765 return &vmx->vcpu;
7766
7767free_vmcs:
5f3fbc34 7768 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7769free_msrs:
fb3f0f51
RR		 7770 kfree(vmx->guest_msrs);
7771uninit_vcpu:
7772 kvm_vcpu_uninit(&vmx->vcpu);
7773free_vcpu:
cdbecfc3 7774 free_vpid(vmx);
a4770347 7775 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7776 return ERR_PTR(err);
6aa8b732
AK		 7777}
7778
002c7f7c
YS		 7779static void __init vmx_check_processor_compat(void *rtn)
7780{
7781 struct vmcs_config vmcs_conf;
7782
7783 *(int *)rtn = 0;
7784 if (setup_vmcs_config(&vmcs_conf) < 0)
7785 *(int *)rtn = -EIO;
7786 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7787 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7788 smp_processor_id());
7789 *(int *)rtn = -EIO;
7790 }
7791}
7792
67253af5
SY		 7793static int get_ept_level(void)
7794{
7795 return VMX_EPT_DEFAULT_GAW + 1;
7796}
7797
4b12f0de 7798static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7799{
4b12f0de
SY		 7800 u64 ret;
7801
522c68c4
SY		 7802 /* For VT-d and EPT combination
7803 * 1. MMIO: always map as UC
7804 * 2. EPT with VT-d:
7805 * a. VT-d without snooping control feature: can't guarantee the
7806 * result, try to trust guest.
7807 * b. VT-d with snooping control feature: snooping control feature of
7808 * VT-d engine can guarantee the cache correctness. Just set it
7809 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7810 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7811 * consistent with host MTRR
7812 */
4b12f0de
SY		 7813 if (is_mmio)
7814 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7815 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7816 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7817 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7818 else
522c68c4 7819 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7820 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7821
7822 return ret;
64d4d521
SY		 7823}
7824
17cc3935 7825static int vmx_get_lpage_level(void)
344f414f 7826{
878403b7
SY		 7827 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7828 return PT_DIRECTORY_LEVEL;
7829 else
7830 /* For shadow and EPT supported 1GB page */
7831 return PT_PDPE_LEVEL;
344f414f
JR		 7832}
7833
0e851880
SY		 7834static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7835{
4e47c7a6
SY		 7836 struct kvm_cpuid_entry2 *best;
7837 struct vcpu_vmx *vmx = to_vmx(vcpu);
7838 u32 exec_control;
7839
7840 vmx->rdtscp_enabled = false;
7841 if (vmx_rdtscp_supported()) {
7842 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7843 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7844 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7845 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7846 vmx->rdtscp_enabled = true;
7847 else {
7848 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7849 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7850 exec_control);
7851 }
7852 }
7853 }
ad756a16 7854
ad756a16
MJ		 7855 /* Exposing INVPCID only when PCID is exposed */
7856 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7857 if (vmx_invpcid_supported() &&
4f977045 7858 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7859 guest_cpuid_has_pcid(vcpu)) {
29282fde 7860 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7861 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7862 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7863 exec_control);
7864 } else {
29282fde
TI		 7865 if (cpu_has_secondary_exec_ctrls()) {
7866 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7867 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7868 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7869 exec_control);
7870 }
ad756a16 7871 if (best)
4f977045 7872 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7873 }
0e851880
SY		 7874}
7875
d4330ef2
JR		 7876static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7877{
7b8050f5
NHE		 7878 if (func == 1 && nested)
7879 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7880}
7881
25d92081
YZ		 7882static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7883 struct x86_exception *fault)
7884{
533558bc
JK		 7885 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7886 u32 exit_reason;
25d92081
YZ		 7887
7888 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7889 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7890 else
533558bc
JK		 7891 exit_reason = EXIT_REASON_EPT_VIOLATION;
7892 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7893 vmcs12->guest_physical_address = fault->address;
7894}
7895
155a97a3
NHE		 7896/* Callbacks for nested_ept_init_mmu_context: */
7897
7898static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7899{
7900 /* return the page table to be shadowed - in our case, EPT12 */
7901 return get_vmcs12(vcpu)->ept_pointer;
7902}
7903
8a3c1a33 7904static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7905{
8a3c1a33 7906 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7907 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7908
7909 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7910 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7911 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7912
7913 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7914}
7915
7916static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7917{
7918 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7919}
7920
feaf0c7d
GN		 7921static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7922 struct x86_exception *fault)
7923{
7924 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7925
7926 WARN_ON(!is_guest_mode(vcpu));
7927
7928 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7929 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7930 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7931 vmcs_read32(VM_EXIT_INTR_INFO),
7932 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7933 else
7934 kvm_inject_page_fault(vcpu, fault);
7935}
7936
a2bcba50
WL		 7937static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7938 struct vmcs12 *vmcs12)
7939{
7940 struct vcpu_vmx *vmx = to_vmx(vcpu);
7941
7942 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 7943 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 7944 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 7945 return false;
7946
7947 /*
7948 * Translate L1 physical address to host physical
7949 * address for vmcs02. Keep the page pinned, so this
7950 * physical address remains valid. We keep a reference
7951 * to it so we can release it later.
7952 */
7953 if (vmx->nested.apic_access_page) /* shouldn't happen */
7954 nested_release_page(vmx->nested.apic_access_page);
7955 vmx->nested.apic_access_page =
7956 nested_get_page(vcpu, vmcs12->apic_access_addr);
7957 }
a7c0b07d
WL		 7958
7959 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
7960 /* TODO: Also verify bits beyond physical address width are 0 */
7961 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
7962 return false;
7963
7964 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
7965 nested_release_page(vmx->nested.virtual_apic_page);
7966 vmx->nested.virtual_apic_page =
7967 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
7968
7969 /*
7970 * Failing the vm entry is _not_ what the processor does
7971 * but it's basically the only possibility we have.
7972 * We could still enter the guest if CR8 load exits are
7973 * enabled, CR8 store exits are enabled, and virtualize APIC
7974 * access is disabled; in this case the processor would never
7975 * use the TPR shadow and we could simply clear the bit from
7976 * the execution control. But such a configuration is useless,
7977 * so let's keep the code simple.
7978 */
7979 if (!vmx->nested.virtual_apic_page)
7980 return false;
7981 }
7982
a2bcba50
WL		 7983 return true;
7984}
7985
f4124500
JK		 7986static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7987{
7988 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7989 struct vcpu_vmx *vmx = to_vmx(vcpu);
7990
7991 if (vcpu->arch.virtual_tsc_khz == 0)
7992 return;
7993
7994 /* Make sure short timeouts reliably trigger an immediate vmexit.
7995 * hrtimer_start does not guarantee this. */
7996 if (preemption_timeout <= 1) {
7997 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7998 return;
7999 }
8000
8001 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8002 preemption_timeout *= 1000000;
8003 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8004 hrtimer_start(&vmx->nested.preemption_timer,
8005 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8006}
8007
fe3ef05c
NHE		 8008/*
8009 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8010 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8011 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
8012 * guest in a way that will both be appropriate to L1's requests, and our
8013 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8014 * function also has additional necessary side-effects, like setting various
8015 * vcpu->arch fields.
8016 */
8017static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8018{
8019 struct vcpu_vmx *vmx = to_vmx(vcpu);
8020 u32 exec_control;
8021
8022 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8023 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8024 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8025 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8026 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8027 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8028 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8029 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8030 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8031 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8032 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8033 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8034 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8035 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8036 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8037 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8038 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8039 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8040 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8041 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8042 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8043 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8044 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8045 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8046 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8047 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8048 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8049 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8050 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8051 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8052 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8053 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8054 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8055 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8056 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8057 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8058
2996fca0
JK		 8059 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8060 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8061 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8062 } else {
8063 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8064 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8065 }
fe3ef05c
NHE		 8066 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8067 vmcs12->vm_entry_intr_info_field);
8068 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8069 vmcs12->vm_entry_exception_error_code);
8070 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8071 vmcs12->vm_entry_instruction_len);
8072 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8073 vmcs12->guest_interruptibility_info);
fe3ef05c 8074 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8075 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8076 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8077 vmcs12->guest_pending_dbg_exceptions);
8078 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8079 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8080
8081 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8082
f4124500
JK		 8083 exec_control = vmcs12->pin_based_vm_exec_control;
8084 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8085 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8086 PIN_BASED_POSTED_INTR);
f4124500 8087 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8088
f4124500
JK		 8089 vmx->nested.preemption_timer_expired = false;
8090 if (nested_cpu_has_preemption_timer(vmcs12))
8091 vmx_start_preemption_timer(vcpu);
0238ea91 8092
fe3ef05c
NHE		 8093 /*
8094 * Whether page-faults are trapped is determined by a combination of
8095 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8096 * If enable_ept, L0 doesn't care about page faults and we should
8097 * set all of these to L1's desires. However, if !enable_ept, L0 does
8098 * care about (at least some) page faults, and because it is not easy
8099 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8100 * to exit on each and every L2 page fault. This is done by setting
8101 * MASK=MATCH=0 and (see below) EB.PF=1.
8102 * Note that below we don't need special code to set EB.PF beyond the
8103 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8104 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8105 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8106 *
8107 * A problem with this approach (when !enable_ept) is that L1 may be
8108 * injected with more page faults than it asked for. This could have
8109 * caused problems, but in practice existing hypervisors don't care.
8110 * To fix this, we will need to emulate the PFEC checking (on the L1
8111 * page tables), using walk_addr(), when injecting PFs to L1.
8112 */
8113 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8114 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8115 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8116 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8117
8118 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8119 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8120 if (!vmx->rdtscp_enabled)
8121 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8122 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8123 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8124 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8125 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8126 if (nested_cpu_has(vmcs12,
8127 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8128 exec_control |= vmcs12->secondary_vm_exec_control;
8129
8130 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8131 /*
8132 * If translation failed, no matter: This feature asks
8133 * to exit when accessing the given address, and if it
8134 * can never be accessed, this feature won't do
8135 * anything anyway.
8136 */
8137 if (!vmx->nested.apic_access_page)
8138 exec_control &=
8139 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8140 else
8141 vmcs_write64(APIC_ACCESS_ADDR,
8142 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8143 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8144 exec_control |=
8145 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8146 vmcs_write64(APIC_ACCESS_ADDR,
8147 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 8148 }
8149
8150 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8151 }
8152
8153
8154 /*
8155 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8156 * Some constant fields are set here by vmx_set_constant_host_state().
8157 * Other fields are different per CPU, and will be set later when
8158 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8159 */
a547c6db 8160 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8161
8162 /*
8163 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8164 * entry, but only if the current (host) sp changed from the value
8165 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8166 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8167 * here we just force the write to happen on entry.
8168 */
8169 vmx->host_rsp = 0;
8170
8171 exec_control = vmx_exec_control(vmx); /* L0's desires */
8172 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8173 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8174 exec_control &= ~CPU_BASED_TPR_SHADOW;
8175 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8176
8177 if (exec_control & CPU_BASED_TPR_SHADOW) {
8178 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8179 page_to_phys(vmx->nested.virtual_apic_page));
8180 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8181 }
8182
fe3ef05c
NHE		 8183 /*
8184 * Merging of IO and MSR bitmaps not currently supported.
8185 * Rather, exit every time.
8186 */
8187 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8188 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8189 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8190
8191 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8192
8193 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8194 * bitwise-or of what L1 wants to trap for L2, and what we want to
8195 * trap. Note that CR0.TS also needs updating - we do this later.
8196 */
8197 update_exception_bitmap(vcpu);
8198 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8199 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8200
8049d651
NHE		 8201 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8202 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8203 * bits are further modified by vmx_set_efer() below.
8204 */
f4124500 8205 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8206
8207 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8208 * emulated by vmx_set_efer(), below.
8209 */
2961e876 8210 vm_entry_controls_init(vmx,
8049d651
NHE		 8211 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8212 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8213 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8214
44811c02 8215 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8216 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8217 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8218 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8219 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8220
8221
8222 set_cr4_guest_host_mask(vmx);
8223
36be0b9d
PB		 8224 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8225 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8226
27fc51b2
NHE		 8227 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8228 vmcs_write64(TSC_OFFSET,
8229 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8230 else
8231 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8232
8233 if (enable_vpid) {
8234 /*
8235 * Trivially support vpid by letting L2s share their parent
8236 * L1's vpid. TODO: move to a more elaborate solution, giving
8237 * each L2 its own vpid and exposing the vpid feature to L1.
8238 */
8239 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8240 vmx_flush_tlb(vcpu);
8241 }
8242
155a97a3
NHE		 8243 if (nested_cpu_has_ept(vmcs12)) {
8244 kvm_mmu_unload(vcpu);
8245 nested_ept_init_mmu_context(vcpu);
8246 }
8247
fe3ef05c
NHE		 8248 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8249 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8250 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8251 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8252 else
8253 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8254 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8255 vmx_set_efer(vcpu, vcpu->arch.efer);
8256
8257 /*
8258 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8259 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8260 * The CR0_READ_SHADOW is what L2 should have expected to read given
8261 * the specifications by L1; It's not enough to take
8262 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8263 * have more bits than L1 expected.
8264 */
8265 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8266 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8267
8268 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8269 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8270
8271 /* shadow page tables on either EPT or shadow page tables */
8272 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8273 kvm_mmu_reset_context(vcpu);
8274
feaf0c7d
GN		 8275 if (!enable_ept)
8276 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8277
3633cfc3
NHE		 8278 /*
8279 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8280 */
8281 if (enable_ept) {
8282 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8283 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8284 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8285 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8286 }
8287
fe3ef05c
NHE		 8288 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8289 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8290}
8291
cd232ad0
NHE		 8292/*
8293 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8294 * for running an L2 nested guest.
8295 */
8296static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8297{
8298 struct vmcs12 *vmcs12;
8299 struct vcpu_vmx *vmx = to_vmx(vcpu);
8300 int cpu;
8301 struct loaded_vmcs *vmcs02;
384bb783 8302 bool ia32e;
cd232ad0
NHE		 8303
8304 if (!nested_vmx_check_permission(vcpu) ||
8305 !nested_vmx_check_vmcs12(vcpu))
8306 return 1;
8307
8308 skip_emulated_instruction(vcpu);
8309 vmcs12 = get_vmcs12(vcpu);
8310
012f83cb
AG		 8311 if (enable_shadow_vmcs)
8312 copy_shadow_to_vmcs12(vmx);
8313
7c177938
NHE		 8314 /*
8315 * The nested entry process starts with enforcing various prerequisites
8316 * on vmcs12 as required by the Intel SDM, and act appropriately when
8317 * they fail: As the SDM explains, some conditions should cause the
8318 * instruction to fail, while others will cause the instruction to seem
8319 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8320 * To speed up the normal (success) code path, we should avoid checking
8321 * for misconfigurations which will anyway be caught by the processor
8322 * when using the merged vmcs02.
8323 */
8324 if (vmcs12->launch_state == launch) {
8325 nested_vmx_failValid(vcpu,
8326 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8327 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8328 return 1;
8329 }
8330
6dfacadd
JK		 8331 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8332 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8333 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8334 return 1;
8335 }
8336
7c177938 8337 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8338 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8339 /*TODO: Also verify bits beyond physical address width are 0*/
8340 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8341 return 1;
8342 }
8343
a2bcba50 8344 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8345 /*TODO: Also verify bits beyond physical address width are 0*/
8346 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8347 return 1;
8348 }
8349
8350 if (vmcs12->vm_entry_msr_load_count > 0 ||
8351 vmcs12->vm_exit_msr_load_count > 0 ||
8352 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8353 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8354 __func__);
7c177938
NHE		 8355 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8356 return 1;
8357 }
8358
8359 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8360 nested_vmx_true_procbased_ctls_low,
8361 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8362 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8363 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8364 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8365 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8366 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8367 nested_vmx_true_exit_ctls_low,
8368 nested_vmx_exit_ctls_high) ||
7c177938 8369 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8370 nested_vmx_true_entry_ctls_low,
8371 nested_vmx_entry_ctls_high))
7c177938
NHE		 8372 {
8373 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8374 return 1;
8375 }
8376
8377 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8378 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8379 nested_vmx_failValid(vcpu,
8380 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8381 return 1;
8382 }
8383
92fbc7b1 8384 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8385 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8386 nested_vmx_entry_failure(vcpu, vmcs12,
8387 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8388 return 1;
8389 }
8390 if (vmcs12->vmcs_link_pointer != -1ull) {
8391 nested_vmx_entry_failure(vcpu, vmcs12,
8392 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8393 return 1;
8394 }
8395
384bb783 8396 /*
cb0c8cda 8397 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8398 * are performed on the field for the IA32_EFER MSR:
8399 * - Bits reserved in the IA32_EFER MSR must be 0.
8400 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8401 * the IA-32e mode guest VM-exit control. It must also be identical
8402 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8403 * CR0.PG) is 1.
8404 */
8405 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8406 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8407 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8408 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8409 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8410 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8411 nested_vmx_entry_failure(vcpu, vmcs12,
8412 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8413 return 1;
8414 }
8415 }
8416
8417 /*
8418 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8419 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8420 * the values of the LMA and LME bits in the field must each be that of
8421 * the host address-space size VM-exit control.
8422 */
8423 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8424 ia32e = (vmcs12->vm_exit_controls &
8425 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8426 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8427 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8428 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8429 nested_vmx_entry_failure(vcpu, vmcs12,
8430 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8431 return 1;
8432 }
8433 }
8434
7c177938
NHE		 8435 /*
8436 * We're finally done with prerequisite checking, and can start with
8437 * the nested entry.
8438 */
8439
cd232ad0
NHE		 8440 vmcs02 = nested_get_current_vmcs02(vmx);
8441 if (!vmcs02)
8442 return -ENOMEM;
8443
8444 enter_guest_mode(vcpu);
8445
8446 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8447
2996fca0
JK		 8448 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8449 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8450
cd232ad0
NHE		 8451 cpu = get_cpu();
8452 vmx->loaded_vmcs = vmcs02;
8453 vmx_vcpu_put(vcpu);
8454 vmx_vcpu_load(vcpu, cpu);
8455 vcpu->cpu = cpu;
8456 put_cpu();
8457
36c3cc42
JK		 8458 vmx_segment_cache_clear(vmx);
8459
cd232ad0
NHE		 8460 vmcs12->launch_state = 1;
8461
8462 prepare_vmcs02(vcpu, vmcs12);
8463
6dfacadd
JK		 8464 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8465 return kvm_emulate_halt(vcpu);
8466
7af40ad3
JK		 8467 vmx->nested.nested_run_pending = 1;
8468
cd232ad0
NHE		 8469 /*
8470 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8471 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8472 * returned as far as L1 is concerned. It will only return (and set
8473 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8474 */
8475 return 1;
8476}
8477
4704d0be
NHE		 8478/*
8479 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8480 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8481 * This function returns the new value we should put in vmcs12.guest_cr0.
8482 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8483 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8484 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8485 * didn't trap the bit, because if L1 did, so would L0).
8486 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8487 * been modified by L2, and L1 knows it. So just leave the old value of
8488 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8489 * isn't relevant, because if L0 traps this bit it can set it to anything.
8490 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8491 * changed these bits, and therefore they need to be updated, but L0
8492 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8493 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8494 */
8495static inline unsigned long
8496vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8497{
8498 return
8499 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8500 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8501 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8502 vcpu->arch.cr0_guest_owned_bits));
8503}
8504
8505static inline unsigned long
8506vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8507{
8508 return
8509 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8510 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8511 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8512 vcpu->arch.cr4_guest_owned_bits));
8513}
8514
5f3d5799
JK		 8515static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8516 struct vmcs12 *vmcs12)
8517{
8518 u32 idt_vectoring;
8519 unsigned int nr;
8520
851eb667 8521 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8522 nr = vcpu->arch.exception.nr;
8523 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8524
8525 if (kvm_exception_is_soft(nr)) {
8526 vmcs12->vm_exit_instruction_len =
8527 vcpu->arch.event_exit_inst_len;
8528 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8529 } else
8530 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8531
8532 if (vcpu->arch.exception.has_error_code) {
8533 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8534 vmcs12->idt_vectoring_error_code =
8535 vcpu->arch.exception.error_code;
8536 }
8537
8538 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8539 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8540 vmcs12->idt_vectoring_info_field =
8541 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8542 } else if (vcpu->arch.interrupt.pending) {
8543 nr = vcpu->arch.interrupt.nr;
8544 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8545
8546 if (vcpu->arch.interrupt.soft) {
8547 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8548 vmcs12->vm_entry_instruction_len =
8549 vcpu->arch.event_exit_inst_len;
8550 } else
8551 idt_vectoring |= INTR_TYPE_EXT_INTR;
8552
8553 vmcs12->idt_vectoring_info_field = idt_vectoring;
8554 }
8555}
8556
b6b8a145
JK		 8557static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8558{
8559 struct vcpu_vmx *vmx = to_vmx(vcpu);
8560
f4124500
JK		 8561 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8562 vmx->nested.preemption_timer_expired) {
8563 if (vmx->nested.nested_run_pending)
8564 return -EBUSY;
8565 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8566 return 0;
8567 }
8568
b6b8a145 8569 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8570 if (vmx->nested.nested_run_pending ||
8571 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8572 return -EBUSY;
8573 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8574 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8575 INTR_INFO_VALID_MASK, 0);
8576 /*
8577 * The NMI-triggered VM exit counts as injection:
8578 * clear this one and block further NMIs.
8579 */
8580 vcpu->arch.nmi_pending = 0;
8581 vmx_set_nmi_mask(vcpu, true);
8582 return 0;
8583 }
8584
8585 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8586 nested_exit_on_intr(vcpu)) {
8587 if (vmx->nested.nested_run_pending)
8588 return -EBUSY;
8589 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8590 }
8591
8592 return 0;
8593}
8594
f4124500
JK		 8595static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8596{
8597 ktime_t remaining =
8598 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8599 u64 value;
8600
8601 if (ktime_to_ns(remaining) <= 0)
8602 return 0;
8603
8604 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8605 do_div(value, 1000000);
8606 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8607}
8608
4704d0be
NHE		 8609/*
8610 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8611 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8612 * and this function updates it to reflect the changes to the guest state while
8613 * L2 was running (and perhaps made some exits which were handled directly by L0
8614 * without going back to L1), and to reflect the exit reason.
8615 * Note that we do not have to copy here all VMCS fields, just those that
8616 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8617 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8618 * which already writes to vmcs12 directly.
8619 */
533558bc
JK		 8620static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8621 u32 exit_reason, u32 exit_intr_info,
8622 unsigned long exit_qualification)
4704d0be
NHE		 8623{
8624 /* update guest state fields: */
8625 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8626 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8627
4704d0be
NHE		 8628 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8629 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8630 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8631
8632 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8633 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8634 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8635 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8636 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8637 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8638 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8639 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8640 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8641 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8642 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8643 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8644 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8645 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8646 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8647 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8648 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8649 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8650 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8651 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8652 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8653 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8654 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8655 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8656 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8657 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8658 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8659 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8660 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8661 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8662 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8663 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8664 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8665 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8666 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8667 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8668
4704d0be
NHE		 8669 vmcs12->guest_interruptibility_info =
8670 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8671 vmcs12->guest_pending_dbg_exceptions =
8672 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8673 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8674 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8675 else
8676 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8677
f4124500
JK		 8678 if (nested_cpu_has_preemption_timer(vmcs12)) {
8679 if (vmcs12->vm_exit_controls &
8680 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8681 vmcs12->vmx_preemption_timer_value =
8682 vmx_get_preemption_timer_value(vcpu);
8683 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8684 }
7854cbca 8685
3633cfc3
NHE		 8686 /*
8687 * In some cases (usually, nested EPT), L2 is allowed to change its
8688 * own CR3 without exiting. If it has changed it, we must keep it.
8689 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8690 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8691 *
8692 * Additionally, restore L2's PDPTR to vmcs12.
8693 */
8694 if (enable_ept) {
8695 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8696 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8697 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8698 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8699 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8700 }
8701
c18911a2
JK		 8702 vmcs12->vm_entry_controls =
8703 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8704 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8705
2996fca0
JK		 8706 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8707 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8708 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8709 }
8710
4704d0be
NHE		 8711 /* TODO: These cannot have changed unless we have MSR bitmaps and
8712 * the relevant bit asks not to trap the change */
b8c07d55 8713 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8714 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8715 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8716 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8717 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8718 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8719 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8720 if (vmx_mpx_supported())
8721 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8722
8723 /* update exit information fields: */
8724
533558bc
JK		 8725 vmcs12->vm_exit_reason = exit_reason;
8726 vmcs12->exit_qualification = exit_qualification;
4704d0be 8727
533558bc 8728 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8729 if ((vmcs12->vm_exit_intr_info &
8730 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8731 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8732 vmcs12->vm_exit_intr_error_code =
8733 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8734 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8735 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8736 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8737
5f3d5799
JK		 8738 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8739 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8740 * instead of reading the real value. */
4704d0be 8741 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8742
8743 /*
8744 * Transfer the event that L0 or L1 may wanted to inject into
8745 * L2 to IDT_VECTORING_INFO_FIELD.
8746 */
8747 vmcs12_save_pending_event(vcpu, vmcs12);
8748 }
8749
8750 /*
8751 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8752 * preserved above and would only end up incorrectly in L1.
8753 */
8754 vcpu->arch.nmi_injected = false;
8755 kvm_clear_exception_queue(vcpu);
8756 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8757}
8758
8759/*
8760 * A part of what we need to when the nested L2 guest exits and we want to
8761 * run its L1 parent, is to reset L1's guest state to the host state specified
8762 * in vmcs12.
8763 * This function is to be called not only on normal nested exit, but also on
8764 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8765 * Failures During or After Loading Guest State").
8766 * This function should be called when the active VMCS is L1's (vmcs01).
8767 */
733568f9
JK		 8768static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8769 struct vmcs12 *vmcs12)
4704d0be 8770{
21feb4eb
ACL		 8771 struct kvm_segment seg;
8772
4704d0be
NHE		 8773 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8774 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8775 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8776 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8777 else
8778 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8779 vmx_set_efer(vcpu, vcpu->arch.efer);
8780
8781 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8782 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8783 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8784 /*
8785 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8786 * actually changed, because it depends on the current state of
8787 * fpu_active (which may have changed).
8788 * Note that vmx_set_cr0 refers to efer set above.
8789 */
9e3e4dbf 8790 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8791 /*
8792 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8793 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8794 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8795 */
8796 update_exception_bitmap(vcpu);
8797 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8798 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8799
8800 /*
8801 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8802 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8803 */
8804 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8805 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8806
29bf08f1 8807 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8808
4704d0be
NHE		 8809 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8810 kvm_mmu_reset_context(vcpu);
8811
feaf0c7d
GN		 8812 if (!enable_ept)
8813 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8814
4704d0be
NHE		 8815 if (enable_vpid) {
8816 /*
8817 * Trivially support vpid by letting L2s share their parent
8818 * L1's vpid. TODO: move to a more elaborate solution, giving
8819 * each L2 its own vpid and exposing the vpid feature to L1.
8820 */
8821 vmx_flush_tlb(vcpu);
8822 }
8823
8824
8825 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8826 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8827 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8828 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8829 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8830
36be0b9d
PB		 8831 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8832 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8833 vmcs_write64(GUEST_BNDCFGS, 0);
8834
44811c02 8835 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8836 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8837 vcpu->arch.pat = vmcs12->host_ia32_pat;
8838 }
4704d0be
NHE		 8839 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8840 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8841 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8842
21feb4eb
ACL		 8843 /* Set L1 segment info according to Intel SDM
8844 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8845 seg = (struct kvm_segment) {
8846 .base = 0,
8847 .limit = 0xFFFFFFFF,
8848 .selector = vmcs12->host_cs_selector,
8849 .type = 11,
8850 .present = 1,
8851 .s = 1,
8852 .g = 1
8853 };
8854 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8855 seg.l = 1;
8856 else
8857 seg.db = 1;
8858 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8859 seg = (struct kvm_segment) {
8860 .base = 0,
8861 .limit = 0xFFFFFFFF,
8862 .type = 3,
8863 .present = 1,
8864 .s = 1,
8865 .db = 1,
8866 .g = 1
8867 };
8868 seg.selector = vmcs12->host_ds_selector;
8869 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8870 seg.selector = vmcs12->host_es_selector;
8871 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8872 seg.selector = vmcs12->host_ss_selector;
8873 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8874 seg.selector = vmcs12->host_fs_selector;
8875 seg.base = vmcs12->host_fs_base;
8876 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8877 seg.selector = vmcs12->host_gs_selector;
8878 seg.base = vmcs12->host_gs_base;
8879 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8880 seg = (struct kvm_segment) {
205befd9 8881 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8882 .limit = 0x67,
8883 .selector = vmcs12->host_tr_selector,
8884 .type = 11,
8885 .present = 1
8886 };
8887 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8888
503cd0c5
JK		 8889 kvm_set_dr(vcpu, 7, 0x400);
8890 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8891}
8892
8893/*
8894 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8895 * and modify vmcs12 to make it see what it would expect to see there if
8896 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8897 */
533558bc
JK		 8898static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8899 u32 exit_intr_info,
8900 unsigned long exit_qualification)
4704d0be
NHE		 8901{
8902 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8903 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8904
5f3d5799
JK		 8905 /* trying to cancel vmlaunch/vmresume is a bug */
8906 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8907
4704d0be 8908 leave_guest_mode(vcpu);
533558bc
JK		 8909 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8910 exit_qualification);
4704d0be 8911
f3380ca5
WL		 8912 vmx_load_vmcs01(vcpu);
8913
77b0f5d6
BD		 8914 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8915 && nested_exit_intr_ack_set(vcpu)) {
8916 int irq = kvm_cpu_get_interrupt(vcpu);
8917 WARN_ON(irq < 0);
8918 vmcs12->vm_exit_intr_info = irq |
8919 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8920 }
8921
542060ea
JK		 8922 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8923 vmcs12->exit_qualification,
8924 vmcs12->idt_vectoring_info_field,
8925 vmcs12->vm_exit_intr_info,
8926 vmcs12->vm_exit_intr_error_code,
8927 KVM_ISA_VMX);
4704d0be 8928
2961e876
GN		 8929 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8930 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8931 vmx_segment_cache_clear(vmx);
8932
4704d0be
NHE		 8933 /* if no vmcs02 cache requested, remove the one we used */
8934 if (VMCS02_POOL_SIZE == 0)
8935 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8936
8937 load_vmcs12_host_state(vcpu, vmcs12);
8938
27fc51b2 8939 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8940 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8941
8942 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8943 vmx->host_rsp = 0;
8944
8945 /* Unpin physical memory we referred to in vmcs02 */
8946 if (vmx->nested.apic_access_page) {
8947 nested_release_page(vmx->nested.apic_access_page);
48d89b92 8948 vmx->nested.apic_access_page = NULL;
4704d0be 8949 }
a7c0b07d
WL		 8950 if (vmx->nested.virtual_apic_page) {
8951 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 8952 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 8953 }
4704d0be
NHE		 8954
8955 /*
8956 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8957 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8958 * success or failure flag accordingly.
8959 */
8960 if (unlikely(vmx->fail)) {
8961 vmx->fail = 0;
8962 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8963 } else
8964 nested_vmx_succeed(vcpu);
012f83cb
AG		 8965 if (enable_shadow_vmcs)
8966 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8967
8968 /* in case we halted in L2 */
8969 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8970}
8971
42124925
JK		 8972/*
8973 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8974 */
8975static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8976{
8977 if (is_guest_mode(vcpu))
533558bc 8978 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8979 free_nested(to_vmx(vcpu));
8980}
8981
7c177938
NHE		 8982/*
8983 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8984 * 23.7 "VM-entry failures during or after loading guest state" (this also
8985 * lists the acceptable exit-reason and exit-qualification parameters).
8986 * It should only be called before L2 actually succeeded to run, and when
8987 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8988 */
8989static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8990 struct vmcs12 *vmcs12,
8991 u32 reason, unsigned long qualification)
8992{
8993 load_vmcs12_host_state(vcpu, vmcs12);
8994 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8995 vmcs12->exit_qualification = qualification;
8996 nested_vmx_succeed(vcpu);
012f83cb
AG		 8997 if (enable_shadow_vmcs)
8998 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8999}
9000
8a76d7f2
JR		 9001static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9002 struct x86_instruction_info *info,
9003 enum x86_intercept_stage stage)
9004{
9005 return X86EMUL_CONTINUE;
9006}
9007
48d89b92 9008static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9009{
b4a2d31d
RK		 9010 if (ple_gap)
9011 shrink_ple_window(vcpu);
ae97a3b8
RK		 9012}
9013
cbdd1bea 9014static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9015 .cpu_has_kvm_support = cpu_has_kvm_support,
9016 .disabled_by_bios = vmx_disabled_by_bios,
9017 .hardware_setup = hardware_setup,
9018 .hardware_unsetup = hardware_unsetup,
002c7f7c 9019 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9020 .hardware_enable = hardware_enable,
9021 .hardware_disable = hardware_disable,
04547156 9022 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9023
9024 .vcpu_create = vmx_create_vcpu,
9025 .vcpu_free = vmx_free_vcpu,
04d2cc77 9026 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9027
04d2cc77 9028 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9029 .vcpu_load = vmx_vcpu_load,
9030 .vcpu_put = vmx_vcpu_put,
9031
c8639010 9032 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9033 .get_msr = vmx_get_msr,
9034 .set_msr = vmx_set_msr,
9035 .get_segment_base = vmx_get_segment_base,
9036 .get_segment = vmx_get_segment,
9037 .set_segment = vmx_set_segment,
2e4d2653 9038 .get_cpl = vmx_get_cpl,
6aa8b732 9039 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9040 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9041 .decache_cr3 = vmx_decache_cr3,
25c4c276 9042 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9043 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9044 .set_cr3 = vmx_set_cr3,
9045 .set_cr4 = vmx_set_cr4,
6aa8b732 9046 .set_efer = vmx_set_efer,
6aa8b732
AK		 9047 .get_idt = vmx_get_idt,
9048 .set_idt = vmx_set_idt,
9049 .get_gdt = vmx_get_gdt,
9050 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9051 .get_dr6 = vmx_get_dr6,
9052 .set_dr6 = vmx_set_dr6,
020df079 9053 .set_dr7 = vmx_set_dr7,
81908bf4 9054 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9055 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9056 .get_rflags = vmx_get_rflags,
9057 .set_rflags = vmx_set_rflags,
02daab21 9058 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9059
9060 .tlb_flush = vmx_flush_tlb,
6aa8b732 9061
6aa8b732 9062 .run = vmx_vcpu_run,
6062d012 9063 .handle_exit = vmx_handle_exit,
6aa8b732 9064 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9065 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9066 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9067 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9068 .set_irq = vmx_inject_irq,
95ba8273 9069 .set_nmi = vmx_inject_nmi,
298101da 9070 .queue_exception = vmx_queue_exception,
b463a6f7 9071 .cancel_injection = vmx_cancel_injection,
78646121 9072 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9073 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9074 .get_nmi_mask = vmx_get_nmi_mask,
9075 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9076 .enable_nmi_window = enable_nmi_window,
9077 .enable_irq_window = enable_irq_window,
9078 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9079 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 9080 .vm_has_apicv = vmx_vm_has_apicv,
9081 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9082 .hwapic_irr_update = vmx_hwapic_irr_update,
9083 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9084 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9085 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9086
cbc94022 9087 .set_tss_addr = vmx_set_tss_addr,
67253af5 9088 .get_tdp_level = get_ept_level,
4b12f0de 9089 .get_mt_mask = vmx_get_mt_mask,
229456fc 9090
586f9607 9091 .get_exit_info = vmx_get_exit_info,
586f9607 9092
17cc3935 9093 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9094
9095 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9096
9097 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9098 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9099
9100 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9101
9102 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9103
4051b188 9104 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9105 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9106 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9107 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9108 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9109 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9110
9111 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9112
9113 .check_intercept = vmx_check_intercept,
a547c6db 9114 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9115 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9116
9117 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9118
9119 .sched_in = vmx_sched_in,
6aa8b732
AK		 9120};
9121
9122static int __init vmx_init(void)
9123{
8d14695f 9124 int r, i, msr;
26bb0981
AK		 9125
9126 rdmsrl_safe(MSR_EFER, &host_efer);
9127
03916db9 9128 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 9129 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 9130
3e7c73e9 9131 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 9132 if (!vmx_io_bitmap_a)
9133 return -ENOMEM;
9134
2106a548
GC		 9135 r = -ENOMEM;
9136
3e7c73e9 9137 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9138 if (!vmx_io_bitmap_b)
fdef3ad1 9139 goto out;
fdef3ad1 9140
5897297b 9141 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9142 if (!vmx_msr_bitmap_legacy)
25c5f225 9143 goto out1;
2106a548 9144
8d14695f
YZ		 9145 vmx_msr_bitmap_legacy_x2apic =
9146 (unsigned long *)__get_free_page(GFP_KERNEL);
9147 if (!vmx_msr_bitmap_legacy_x2apic)
9148 goto out2;
25c5f225 9149
5897297b 9150 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9151 if (!vmx_msr_bitmap_longmode)
8d14695f 9152 goto out3;
2106a548 9153
8d14695f
YZ		 9154 vmx_msr_bitmap_longmode_x2apic =
9155 (unsigned long *)__get_free_page(GFP_KERNEL);
9156 if (!vmx_msr_bitmap_longmode_x2apic)
9157 goto out4;
4607c2d7
AG		 9158 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9159 if (!vmx_vmread_bitmap)
9160 goto out5;
9161
9162 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9163 if (!vmx_vmwrite_bitmap)
9164 goto out6;
9165
9166 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9167 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9168
fdef3ad1
HQ		 9169 /*
9170 * Allow direct access to the PC debug port (it is often used for I/O
9171 * delays, but the vmexits simply slow things down).
9172 */
3e7c73e9
AK		 9173 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9174 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9175
3e7c73e9 9176 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9177
5897297b
AK		 9178 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9179 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9180
2384d2b3
SY		 9181 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9182
0ee75bea
AK		 9183 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9184 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9185 if (r)
4607c2d7 9186 goto out7;
25c5f225 9187
8f536b76
ZY		 9188#ifdef CONFIG_KEXEC
9189 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9190 crash_vmclear_local_loaded_vmcss);
9191#endif
9192
5897297b
AK		 9193 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9194 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9195 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9196 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9197 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9198 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9199 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9200
8d14695f
YZ		 9201 memcpy(vmx_msr_bitmap_legacy_x2apic,
9202 vmx_msr_bitmap_legacy, PAGE_SIZE);
9203 memcpy(vmx_msr_bitmap_longmode_x2apic,
9204 vmx_msr_bitmap_longmode, PAGE_SIZE);
9205
01e439be 9206 if (enable_apicv) {
8d14695f
YZ		 9207 for (msr = 0x800; msr <= 0x8ff; msr++)
9208 vmx_disable_intercept_msr_read_x2apic(msr);
9209
9210 /* According SDM, in x2apic mode, the whole id reg is used.
9211 * But in KVM, it only use the highest eight bits. Need to
9212 * intercept it */
9213 vmx_enable_intercept_msr_read_x2apic(0x802);
9214 /* TMCCT */
9215 vmx_enable_intercept_msr_read_x2apic(0x839);
9216 /* TPR */
9217 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9218 /* EOI */
9219 vmx_disable_intercept_msr_write_x2apic(0x80b);
9220 /* SELF-IPI */
9221 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9222 }
fdef3ad1 9223
089d034e 9224 if (enable_ept) {
3f6d8c8a
XH		 9225 kvm_mmu_set_mask_ptes(0ull,
9226 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9227 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9228 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9229 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9230 kvm_enable_tdp();
9231 } else
9232 kvm_disable_tdp();
1439442c 9233
b4a2d31d
RK		 9234 update_ple_window_actual_max();
9235
fdef3ad1
HQ		 9236 return 0;
9237
4607c2d7
AG		 9238out7:
9239 free_page((unsigned long)vmx_vmwrite_bitmap);
9240out6:
9241 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9242out5:
9243 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9244out4:
5897297b 9245 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9246out3:
9247 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9248out2:
5897297b 9249 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9250out1:
3e7c73e9 9251 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9252out:
3e7c73e9 9253 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9254 return r;
6aa8b732
AK		 9255}
9256
9257static void __exit vmx_exit(void)
9258{
8d14695f
YZ		 9259 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9260 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9261 free_page((unsigned long)vmx_msr_bitmap_legacy);
9262 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9263 free_page((unsigned long)vmx_io_bitmap_b);
9264 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9265 free_page((unsigned long)vmx_vmwrite_bitmap);
9266 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9267
8f536b76 9268#ifdef CONFIG_KEXEC
3b63a43f 9269 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9270 synchronize_rcu();
9271#endif
9272
cb498ea2 9273 kvm_exit();
6aa8b732
AK		 9274}
9275
9276module_init(vmx_init)
9277module_exit(vmx_exit)
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