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x86, kvm, vmx: Always use LOAD_IA32_EFER if available
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 108 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d974baa3 475 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 476 } host_state;
9c8cba37 477 struct {
7ffd92c5 478 int vm86_active;
78ac8b47 479 ulong save_rflags;
f5f7b2fe
AK		 480 struct kvm_segment segs[8];
481 } rmode;
482 struct {
483 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 484 struct kvm_save_segment {
485 u16 selector;
486 unsigned long base;
487 u32 limit;
488 u32 ar;
f5f7b2fe 489 } seg[8];
2fb92db1 490 } segment_cache;
2384d2b3 491 int vpid;
04fa4d32 492 bool emulation_required;
3b86cd99
JK		 493
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked;
496 ktime_t entry_time;
497 s64 vnmi_blocked_time;
a0861c02 498 u32 exit_reason;
4e47c7a6
SY		 499
500 bool rdtscp_enabled;
ec378aee 501
01e439be
YZ		 502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc;
504
ec378aee
NHE		 505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested;
a7653ecd
RK		 507
508 /* Dynamic PLE window. */
509 int ple_window;
510 bool ple_window_dirty;
a2fa3e9f
GH		 511};
512
2fb92db1
AK		 513enum segment_cache_field {
514 SEG_FIELD_SEL = 0,
515 SEG_FIELD_BASE = 1,
516 SEG_FIELD_LIMIT = 2,
517 SEG_FIELD_AR = 3,
518
519 SEG_FIELD_NR = 4
520};
521
a2fa3e9f
GH		 522static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
523{
fb3f0f51 524 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 525}
526
22bd0358
NHE		 527#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
531
4607c2d7 532
fe2b201b 533static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 534 /*
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
545 */
546 VM_EXIT_REASON,
547 VM_EXIT_INTR_INFO,
548 VM_EXIT_INSTRUCTION_LEN,
549 IDT_VECTORING_INFO_FIELD,
550 IDT_VECTORING_ERROR_CODE,
551 VM_EXIT_INTR_ERROR_CODE,
552 EXIT_QUALIFICATION,
553 GUEST_LINEAR_ADDRESS,
554 GUEST_PHYSICAL_ADDRESS
555};
fe2b201b 556static int max_shadow_read_only_fields =
4607c2d7
AG		 557 ARRAY_SIZE(shadow_read_only_fields);
558
fe2b201b 559static unsigned long shadow_read_write_fields[] = {
a7c0b07d 560 TPR_THRESHOLD,
4607c2d7
AG		 561 GUEST_RIP,
562 GUEST_RSP,
563 GUEST_CR0,
564 GUEST_CR3,
565 GUEST_CR4,
566 GUEST_INTERRUPTIBILITY_INFO,
567 GUEST_RFLAGS,
568 GUEST_CS_SELECTOR,
569 GUEST_CS_AR_BYTES,
570 GUEST_CS_LIMIT,
571 GUEST_CS_BASE,
572 GUEST_ES_BASE,
36be0b9d 573 GUEST_BNDCFGS,
4607c2d7
AG		 574 CR0_GUEST_HOST_MASK,
575 CR0_READ_SHADOW,
576 CR4_READ_SHADOW,
577 TSC_OFFSET,
578 EXCEPTION_BITMAP,
579 CPU_BASED_VM_EXEC_CONTROL,
580 VM_ENTRY_EXCEPTION_ERROR_CODE,
581 VM_ENTRY_INTR_INFO_FIELD,
582 VM_ENTRY_INSTRUCTION_LEN,
583 VM_ENTRY_EXCEPTION_ERROR_CODE,
584 HOST_FS_BASE,
585 HOST_GS_BASE,
586 HOST_FS_SELECTOR,
587 HOST_GS_SELECTOR
588};
fe2b201b 589static int max_shadow_read_write_fields =
4607c2d7
AG		 590 ARRAY_SIZE(shadow_read_write_fields);
591
772e0318 592static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 593 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
594 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
595 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
596 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
597 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
598 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
599 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
600 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
601 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
602 FIELD(HOST_ES_SELECTOR, host_es_selector),
603 FIELD(HOST_CS_SELECTOR, host_cs_selector),
604 FIELD(HOST_SS_SELECTOR, host_ss_selector),
605 FIELD(HOST_DS_SELECTOR, host_ds_selector),
606 FIELD(HOST_FS_SELECTOR, host_fs_selector),
607 FIELD(HOST_GS_SELECTOR, host_gs_selector),
608 FIELD(HOST_TR_SELECTOR, host_tr_selector),
609 FIELD64(IO_BITMAP_A, io_bitmap_a),
610 FIELD64(IO_BITMAP_B, io_bitmap_b),
611 FIELD64(MSR_BITMAP, msr_bitmap),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
615 FIELD64(TSC_OFFSET, tsc_offset),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
617 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
618 FIELD64(EPT_POINTER, ept_pointer),
619 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
620 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
621 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
622 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
623 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
625 FIELD64(GUEST_PDPTR0, guest_pdptr0),
626 FIELD64(GUEST_PDPTR1, guest_pdptr1),
627 FIELD64(GUEST_PDPTR2, guest_pdptr2),
628 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 629 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 630 FIELD64(HOST_IA32_PAT, host_ia32_pat),
631 FIELD64(HOST_IA32_EFER, host_ia32_efer),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
635 FIELD(EXCEPTION_BITMAP, exception_bitmap),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
638 FIELD(CR3_TARGET_COUNT, cr3_target_count),
639 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
640 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
642 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
647 FIELD(TPR_THRESHOLD, tpr_threshold),
648 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
649 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
650 FIELD(VM_EXIT_REASON, vm_exit_reason),
651 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
652 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
653 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
654 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
655 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
656 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
657 FIELD(GUEST_ES_LIMIT, guest_es_limit),
658 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
659 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
660 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
661 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
662 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
663 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
664 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
665 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
666 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
667 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
668 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
669 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
670 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
671 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
672 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
673 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
674 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
676 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
677 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
678 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 679 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 680 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
681 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
682 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
683 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
684 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
685 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
686 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
687 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
688 FIELD(EXIT_QUALIFICATION, exit_qualification),
689 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
690 FIELD(GUEST_CR0, guest_cr0),
691 FIELD(GUEST_CR3, guest_cr3),
692 FIELD(GUEST_CR4, guest_cr4),
693 FIELD(GUEST_ES_BASE, guest_es_base),
694 FIELD(GUEST_CS_BASE, guest_cs_base),
695 FIELD(GUEST_SS_BASE, guest_ss_base),
696 FIELD(GUEST_DS_BASE, guest_ds_base),
697 FIELD(GUEST_FS_BASE, guest_fs_base),
698 FIELD(GUEST_GS_BASE, guest_gs_base),
699 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
700 FIELD(GUEST_TR_BASE, guest_tr_base),
701 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
702 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
703 FIELD(GUEST_DR7, guest_dr7),
704 FIELD(GUEST_RSP, guest_rsp),
705 FIELD(GUEST_RIP, guest_rip),
706 FIELD(GUEST_RFLAGS, guest_rflags),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
708 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
709 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
710 FIELD(HOST_CR0, host_cr0),
711 FIELD(HOST_CR3, host_cr3),
712 FIELD(HOST_CR4, host_cr4),
713 FIELD(HOST_FS_BASE, host_fs_base),
714 FIELD(HOST_GS_BASE, host_gs_base),
715 FIELD(HOST_TR_BASE, host_tr_base),
716 FIELD(HOST_GDTR_BASE, host_gdtr_base),
717 FIELD(HOST_IDTR_BASE, host_idtr_base),
718 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
719 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
720 FIELD(HOST_RSP, host_rsp),
721 FIELD(HOST_RIP, host_rip),
722};
22bd0358
NHE		 723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
a2ae9df7
PB		 726 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
727
728 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
729 vmcs_field_to_offset_table[field] == 0)
730 return -ENOENT;
731
22bd0358
NHE		 732 return vmcs_field_to_offset_table[field];
733}
734
a9d30f33
NHE		 735static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
736{
737 return to_vmx(vcpu)->nested.current_vmcs12;
738}
739
740static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
741{
742 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 743 if (is_error_page(page))
a9d30f33 744 return NULL;
32cad84f 745
a9d30f33
NHE		 746 return page;
747}
748
749static void nested_release_page(struct page *page)
750{
751 kvm_release_page_dirty(page);
752}
753
754static void nested_release_page_clean(struct page *page)
755{
756 kvm_release_page_clean(page);
757}
758
bfd0a56b 759static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 760static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 761static void kvm_cpu_vmxon(u64 addr);
762static void kvm_cpu_vmxoff(void);
93c4adc7 763static bool vmx_mpx_supported(void);
776e58ea 764static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 765static void vmx_set_segment(struct kvm_vcpu *vcpu,
766 struct kvm_segment *var, int seg);
767static void vmx_get_segment(struct kvm_vcpu *vcpu,
768 struct kvm_segment *var, int seg);
d99e4152
GN		 769static bool guest_state_valid(struct kvm_vcpu *vcpu);
770static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 771static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 772static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 773static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 774static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 775
6aa8b732
AK		 776static DEFINE_PER_CPU(struct vmcs *, vmxarea);
777static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 778/*
779 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
780 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
781 */
782static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 783static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 784
3e7c73e9
AK		 785static unsigned long *vmx_io_bitmap_a;
786static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 787static unsigned long *vmx_msr_bitmap_legacy;
788static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 789static unsigned long *vmx_msr_bitmap_legacy_x2apic;
790static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 791static unsigned long *vmx_vmread_bitmap;
792static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 793
110312c8 794static bool cpu_has_load_ia32_efer;
8bf00a52 795static bool cpu_has_load_perf_global_ctrl;
110312c8 796
2384d2b3
SY		 797static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
798static DEFINE_SPINLOCK(vmx_vpid_lock);
799
1c3d14fe 800static struct vmcs_config {
6aa8b732
AK		 801 int size;
802 int order;
803 u32 revision_id;
1c3d14fe
YS		 804 u32 pin_based_exec_ctrl;
805 u32 cpu_based_exec_ctrl;
f78e0e2e 806 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 807 u32 vmexit_ctrl;
808 u32 vmentry_ctrl;
809} vmcs_config;
6aa8b732 810
efff9e53 811static struct vmx_capability {
d56f546d
SY		 812 u32 ept;
813 u32 vpid;
814} vmx_capability;
815
6aa8b732
AK		 816#define VMX_SEGMENT_FIELD(seg) \
817 [VCPU_SREG_##seg] = { \
818 .selector = GUEST_##seg##_SELECTOR, \
819 .base = GUEST_##seg##_BASE, \
820 .limit = GUEST_##seg##_LIMIT, \
821 .ar_bytes = GUEST_##seg##_AR_BYTES, \
822 }
823
772e0318 824static const struct kvm_vmx_segment_field {
6aa8b732
AK		 825 unsigned selector;
826 unsigned base;
827 unsigned limit;
828 unsigned ar_bytes;
829} kvm_vmx_segment_fields[] = {
830 VMX_SEGMENT_FIELD(CS),
831 VMX_SEGMENT_FIELD(DS),
832 VMX_SEGMENT_FIELD(ES),
833 VMX_SEGMENT_FIELD(FS),
834 VMX_SEGMENT_FIELD(GS),
835 VMX_SEGMENT_FIELD(SS),
836 VMX_SEGMENT_FIELD(TR),
837 VMX_SEGMENT_FIELD(LDTR),
838};
839
26bb0981
AK		 840static u64 host_efer;
841
6de4f3ad
AK		 842static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
843
4d56c8a7 844/*
8c06585d 845 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 846 * away by decrementing the array size.
847 */
6aa8b732 848static const u32 vmx_msr_index[] = {
05b3e0c2 849#ifdef CONFIG_X86_64
44ea2b17 850 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 851#endif
8c06585d 852 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 853};
6aa8b732 854
31299944 855static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 856{
857 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
858 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 859 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 860}
861
31299944 862static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 863{
864 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
865 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 866 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 867}
868
31299944 869static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 870{
871 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
872 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 873 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 874}
875
31299944 876static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
880}
881
31299944 882static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 883{
884 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
885 INTR_INFO_VALID_MASK)) ==
886 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
887}
888
31299944 889static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 890{
04547156 891 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 892}
893
31299944 894static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 895{
04547156 896 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 897}
898
31299944 899static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 900{
04547156 901 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 902}
903
31299944 904static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 905{
04547156
SY		 906 return vmcs_config.cpu_based_exec_ctrl &
907 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 908}
909
774ead3a 910static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 911{
04547156
SY		 912 return vmcs_config.cpu_based_2nd_exec_ctrl &
913 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
914}
915
8d14695f
YZ		 916static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
917{
918 return vmcs_config.cpu_based_2nd_exec_ctrl &
919 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
920}
921
83d4c286
YZ		 922static inline bool cpu_has_vmx_apic_register_virt(void)
923{
924 return vmcs_config.cpu_based_2nd_exec_ctrl &
925 SECONDARY_EXEC_APIC_REGISTER_VIRT;
926}
927
c7c9c56c
YZ		 928static inline bool cpu_has_vmx_virtual_intr_delivery(void)
929{
930 return vmcs_config.cpu_based_2nd_exec_ctrl &
931 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
932}
933
01e439be
YZ		 934static inline bool cpu_has_vmx_posted_intr(void)
935{
936 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
937}
938
939static inline bool cpu_has_vmx_apicv(void)
940{
941 return cpu_has_vmx_apic_register_virt() &&
942 cpu_has_vmx_virtual_intr_delivery() &&
943 cpu_has_vmx_posted_intr();
944}
945
04547156
SY		 946static inline bool cpu_has_vmx_flexpriority(void)
947{
948 return cpu_has_vmx_tpr_shadow() &&
949 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 950}
951
e799794e
MT		 952static inline bool cpu_has_vmx_ept_execute_only(void)
953{
31299944 954 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 955}
956
957static inline bool cpu_has_vmx_eptp_uncacheable(void)
958{
31299944 959 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 960}
961
962static inline bool cpu_has_vmx_eptp_writeback(void)
963{
31299944 964 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 965}
966
967static inline bool cpu_has_vmx_ept_2m_page(void)
968{
31299944 969 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 970}
971
878403b7
SY		 972static inline bool cpu_has_vmx_ept_1g_page(void)
973{
31299944 974 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 975}
976
4bc9b982
SY		 977static inline bool cpu_has_vmx_ept_4levels(void)
978{
979 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
980}
981
83c3a331
XH		 982static inline bool cpu_has_vmx_ept_ad_bits(void)
983{
984 return vmx_capability.ept & VMX_EPT_AD_BIT;
985}
986
31299944 987static inline bool cpu_has_vmx_invept_context(void)
d56f546d 988{
31299944 989 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 990}
991
31299944 992static inline bool cpu_has_vmx_invept_global(void)
d56f546d 993{
31299944 994 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 995}
996
518c8aee
GJ		 997static inline bool cpu_has_vmx_invvpid_single(void)
998{
999 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1000}
1001
b9d762fa
GJ		 1002static inline bool cpu_has_vmx_invvpid_global(void)
1003{
1004 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1005}
1006
31299944 1007static inline bool cpu_has_vmx_ept(void)
d56f546d 1008{
04547156
SY		 1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1011}
1012
31299944 1013static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1014{
1015 return vmcs_config.cpu_based_2nd_exec_ctrl &
1016 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1017}
1018
31299944 1019static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1020{
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1023}
1024
31299944 1025static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1026{
6d3e435e 1027 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1028}
1029
31299944 1030static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1031{
04547156
SY		 1032 return vmcs_config.cpu_based_2nd_exec_ctrl &
1033 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1034}
1035
31299944 1036static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1037{
1038 return vmcs_config.cpu_based_2nd_exec_ctrl &
1039 SECONDARY_EXEC_RDTSCP;
1040}
1041
ad756a16
MJ		 1042static inline bool cpu_has_vmx_invpcid(void)
1043{
1044 return vmcs_config.cpu_based_2nd_exec_ctrl &
1045 SECONDARY_EXEC_ENABLE_INVPCID;
1046}
1047
31299944 1048static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1049{
1050 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1051}
1052
f5f48ee1
SY		 1053static inline bool cpu_has_vmx_wbinvd_exit(void)
1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_WBINVD_EXITING;
1057}
1058
abc4fc58
AG		 1059static inline bool cpu_has_vmx_shadow_vmcs(void)
1060{
1061 u64 vmx_msr;
1062 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1063 /* check if the cpu supports writing r/o exit information fields */
1064 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1065 return false;
1066
1067 return vmcs_config.cpu_based_2nd_exec_ctrl &
1068 SECONDARY_EXEC_SHADOW_VMCS;
1069}
1070
04547156
SY		 1071static inline bool report_flexpriority(void)
1072{
1073 return flexpriority_enabled;
1074}
1075
fe3ef05c
NHE		 1076static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1077{
1078 return vmcs12->cpu_based_vm_exec_control & bit;
1079}
1080
1081static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1082{
1083 return (vmcs12->cpu_based_vm_exec_control &
1084 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1085 (vmcs12->secondary_vm_exec_control & bit);
1086}
1087
f5c4368f 1088static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1089{
1090 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f4124500
JK		 1093static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1094{
1095 return vmcs12->pin_based_vm_exec_control &
1096 PIN_BASED_VMX_PREEMPTION_TIMER;
1097}
1098
155a97a3
NHE		 1099static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1100{
1101 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1102}
1103
644d711a
NHE		 1104static inline bool is_exception(u32 intr_info)
1105{
1106 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1107 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1108}
1109
533558bc
JK		 1110static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1111 u32 exit_intr_info,
1112 unsigned long exit_qualification);
7c177938
NHE		 1113static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1114 struct vmcs12 *vmcs12,
1115 u32 reason, unsigned long qualification);
1116
8b9cf98c 1117static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1118{
1119 int i;
1120
a2fa3e9f 1121 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1122 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1123 return i;
1124 return -1;
1125}
1126
2384d2b3
SY		 1127static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1128{
1129 struct {
1130 u64 vpid : 16;
1131 u64 rsvd : 48;
1132 u64 gva;
1133 } operand = { vpid, 0, gva };
1134
4ecac3fd 1135 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1136 /* CF==1 or ZF==1 --> rc = -1 */
1137 "; ja 1f ; ud2 ; 1:"
1138 : : "a"(&operand), "c"(ext) : "cc", "memory");
1139}
1140
1439442c
SY		 1141static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1142{
1143 struct {
1144 u64 eptp, gpa;
1145 } operand = {eptp, gpa};
1146
4ecac3fd 1147 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1148 /* CF==1 or ZF==1 --> rc = -1 */
1149 "; ja 1f ; ud2 ; 1:\n"
1150 : : "a" (&operand), "c" (ext) : "cc", "memory");
1151}
1152
26bb0981 1153static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1154{
1155 int i;
1156
8b9cf98c 1157 i = __find_msr_index(vmx, msr);
a75beee6 1158 if (i >= 0)
a2fa3e9f 1159 return &vmx->guest_msrs[i];
8b6d44c7 1160 return NULL;
7725f0ba
AK		 1161}
1162
6aa8b732
AK		 1163static void vmcs_clear(struct vmcs *vmcs)
1164{
1165 u64 phys_addr = __pa(vmcs);
1166 u8 error;
1167
4ecac3fd 1168 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1169 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1170 : "cc", "memory");
1171 if (error)
1172 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1173 vmcs, phys_addr);
1174}
1175
d462b819
NHE		 1176static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1177{
1178 vmcs_clear(loaded_vmcs->vmcs);
1179 loaded_vmcs->cpu = -1;
1180 loaded_vmcs->launched = 0;
1181}
1182
7725b894
DX		 1183static void vmcs_load(struct vmcs *vmcs)
1184{
1185 u64 phys_addr = __pa(vmcs);
1186 u8 error;
1187
1188 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1189 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1190 : "cc", "memory");
1191 if (error)
2844d849 1192 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1193 vmcs, phys_addr);
1194}
1195
8f536b76
ZY		 1196#ifdef CONFIG_KEXEC
1197/*
1198 * This bitmap is used to indicate whether the vmclear
1199 * operation is enabled on all cpus. All disabled by
1200 * default.
1201 */
1202static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1203
1204static inline void crash_enable_local_vmclear(int cpu)
1205{
1206 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1207}
1208
1209static inline void crash_disable_local_vmclear(int cpu)
1210{
1211 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1212}
1213
1214static inline int crash_local_vmclear_enabled(int cpu)
1215{
1216 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1217}
1218
1219static void crash_vmclear_local_loaded_vmcss(void)
1220{
1221 int cpu = raw_smp_processor_id();
1222 struct loaded_vmcs *v;
1223
1224 if (!crash_local_vmclear_enabled(cpu))
1225 return;
1226
1227 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1228 loaded_vmcss_on_cpu_link)
1229 vmcs_clear(v->vmcs);
1230}
1231#else
1232static inline void crash_enable_local_vmclear(int cpu) { }
1233static inline void crash_disable_local_vmclear(int cpu) { }
1234#endif /* CONFIG_KEXEC */
1235
d462b819 1236static void __loaded_vmcs_clear(void *arg)
6aa8b732 1237{
d462b819 1238 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1239 int cpu = raw_smp_processor_id();
6aa8b732 1240
d462b819
NHE		 1241 if (loaded_vmcs->cpu != cpu)
1242 return; /* vcpu migration can race with cpu offline */
1243 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1244 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1245 crash_disable_local_vmclear(cpu);
d462b819 1246 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1247
1248 /*
1249 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1250 * is before setting loaded_vmcs->vcpu to -1 which is done in
1251 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1252 * then adds the vmcs into percpu list before it is deleted.
1253 */
1254 smp_wmb();
1255
d462b819 1256 loaded_vmcs_init(loaded_vmcs);
8f536b76 1257 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1258}
1259
d462b819 1260static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1261{
e6c7d321
XG		 1262 int cpu = loaded_vmcs->cpu;
1263
1264 if (cpu != -1)
1265 smp_call_function_single(cpu,
1266 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1267}
1268
1760dd49 1269static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1270{
1271 if (vmx->vpid == 0)
1272 return;
1273
518c8aee
GJ		 1274 if (cpu_has_vmx_invvpid_single())
1275 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1276}
1277
b9d762fa
GJ		 1278static inline void vpid_sync_vcpu_global(void)
1279{
1280 if (cpu_has_vmx_invvpid_global())
1281 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1282}
1283
1284static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1285{
1286 if (cpu_has_vmx_invvpid_single())
1760dd49 1287 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1288 else
1289 vpid_sync_vcpu_global();
1290}
1291
1439442c
SY		 1292static inline void ept_sync_global(void)
1293{
1294 if (cpu_has_vmx_invept_global())
1295 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1296}
1297
1298static inline void ept_sync_context(u64 eptp)
1299{
089d034e 1300 if (enable_ept) {
1439442c
SY		 1301 if (cpu_has_vmx_invept_context())
1302 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1303 else
1304 ept_sync_global();
1305 }
1306}
1307
96304217 1308static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1309{
5e520e62 1310 unsigned long value;
6aa8b732 1311
5e520e62
AK		 1312 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1313 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1314 return value;
1315}
1316
96304217 1317static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1318{
1319 return vmcs_readl(field);
1320}
1321
96304217 1322static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1323{
1324 return vmcs_readl(field);
1325}
1326
96304217 1327static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1328{
05b3e0c2 1329#ifdef CONFIG_X86_64
6aa8b732
AK		 1330 return vmcs_readl(field);
1331#else
1332 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1333#endif
1334}
1335
e52de1b8
AK		 1336static noinline void vmwrite_error(unsigned long field, unsigned long value)
1337{
1338 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1339 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1340 dump_stack();
1341}
1342
6aa8b732
AK		 1343static void vmcs_writel(unsigned long field, unsigned long value)
1344{
1345 u8 error;
1346
4ecac3fd 1347 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1348 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1349 if (unlikely(error))
1350 vmwrite_error(field, value);
6aa8b732
AK		 1351}
1352
1353static void vmcs_write16(unsigned long field, u16 value)
1354{
1355 vmcs_writel(field, value);
1356}
1357
1358static void vmcs_write32(unsigned long field, u32 value)
1359{
1360 vmcs_writel(field, value);
1361}
1362
1363static void vmcs_write64(unsigned long field, u64 value)
1364{
6aa8b732 1365 vmcs_writel(field, value);
7682f2d0 1366#ifndef CONFIG_X86_64
6aa8b732
AK		 1367 asm volatile ("");
1368 vmcs_writel(field+1, value >> 32);
1369#endif
1370}
1371
2ab455cc
AL		 1372static void vmcs_clear_bits(unsigned long field, u32 mask)
1373{
1374 vmcs_writel(field, vmcs_readl(field) & ~mask);
1375}
1376
1377static void vmcs_set_bits(unsigned long field, u32 mask)
1378{
1379 vmcs_writel(field, vmcs_readl(field) | mask);
1380}
1381
2961e876
GN		 1382static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1383{
1384 vmcs_write32(VM_ENTRY_CONTROLS, val);
1385 vmx->vm_entry_controls_shadow = val;
1386}
1387
1388static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1389{
1390 if (vmx->vm_entry_controls_shadow != val)
1391 vm_entry_controls_init(vmx, val);
1392}
1393
1394static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1395{
1396 return vmx->vm_entry_controls_shadow;
1397}
1398
1399
1400static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1401{
1402 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1403}
1404
1405static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1406{
1407 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1408}
1409
1410static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1411{
1412 vmcs_write32(VM_EXIT_CONTROLS, val);
1413 vmx->vm_exit_controls_shadow = val;
1414}
1415
1416static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1417{
1418 if (vmx->vm_exit_controls_shadow != val)
1419 vm_exit_controls_init(vmx, val);
1420}
1421
1422static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1423{
1424 return vmx->vm_exit_controls_shadow;
1425}
1426
1427
1428static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1429{
1430 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1431}
1432
1433static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1434{
1435 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1436}
1437
2fb92db1
AK		 1438static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1439{
1440 vmx->segment_cache.bitmask = 0;
1441}
1442
1443static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1444 unsigned field)
1445{
1446 bool ret;
1447 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1448
1449 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1450 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1451 vmx->segment_cache.bitmask = 0;
1452 }
1453 ret = vmx->segment_cache.bitmask & mask;
1454 vmx->segment_cache.bitmask |= mask;
1455 return ret;
1456}
1457
1458static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1459{
1460 u16 *p = &vmx->segment_cache.seg[seg].selector;
1461
1462 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1463 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1464 return *p;
1465}
1466
1467static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1468{
1469 ulong *p = &vmx->segment_cache.seg[seg].base;
1470
1471 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1472 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1473 return *p;
1474}
1475
1476static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1477{
1478 u32 *p = &vmx->segment_cache.seg[seg].limit;
1479
1480 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1481 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1482 return *p;
1483}
1484
1485static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1486{
1487 u32 *p = &vmx->segment_cache.seg[seg].ar;
1488
1489 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1490 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1491 return *p;
1492}
1493
abd3f2d6
AK		 1494static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1495{
1496 u32 eb;
1497
fd7373cc
JK		 1498 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1499 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1500 if ((vcpu->guest_debug &
1501 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1502 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1503 eb |= 1u << BP_VECTOR;
7ffd92c5 1504 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1505 eb = ~0;
089d034e 1506 if (enable_ept)
1439442c 1507 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1508 if (vcpu->fpu_active)
1509 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1510
1511 /* When we are running a nested L2 guest and L1 specified for it a
1512 * certain exception bitmap, we must trap the same exceptions and pass
1513 * them to L1. When running L2, we will only handle the exceptions
1514 * specified above if L1 did not want them.
1515 */
1516 if (is_guest_mode(vcpu))
1517 eb |= get_vmcs12(vcpu)->exception_bitmap;
1518
abd3f2d6
AK		 1519 vmcs_write32(EXCEPTION_BITMAP, eb);
1520}
1521
2961e876
GN		 1522static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1523 unsigned long entry, unsigned long exit)
8bf00a52 1524{
2961e876
GN		 1525 vm_entry_controls_clearbit(vmx, entry);
1526 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1527}
1528
61d2ef2c
AK		 1529static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1530{
1531 unsigned i;
1532 struct msr_autoload *m = &vmx->msr_autoload;
1533
8bf00a52
GN		 1534 switch (msr) {
1535 case MSR_EFER:
1536 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1537 clear_atomic_switch_msr_special(vmx,
1538 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1539 VM_EXIT_LOAD_IA32_EFER);
1540 return;
1541 }
1542 break;
1543 case MSR_CORE_PERF_GLOBAL_CTRL:
1544 if (cpu_has_load_perf_global_ctrl) {
2961e876 1545 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1546 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1547 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1548 return;
1549 }
1550 break;
110312c8
AK		 1551 }
1552
61d2ef2c
AK		 1553 for (i = 0; i < m->nr; ++i)
1554 if (m->guest[i].index == msr)
1555 break;
1556
1557 if (i == m->nr)
1558 return;
1559 --m->nr;
1560 m->guest[i] = m->guest[m->nr];
1561 m->host[i] = m->host[m->nr];
1562 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1563 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1564}
1565
2961e876
GN		 1566static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1567 unsigned long entry, unsigned long exit,
1568 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1569 u64 guest_val, u64 host_val)
8bf00a52
GN		 1570{
1571 vmcs_write64(guest_val_vmcs, guest_val);
1572 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1573 vm_entry_controls_setbit(vmx, entry);
1574 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1575}
1576
61d2ef2c
AK		 1577static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1578 u64 guest_val, u64 host_val)
1579{
1580 unsigned i;
1581 struct msr_autoload *m = &vmx->msr_autoload;
1582
8bf00a52
GN		 1583 switch (msr) {
1584 case MSR_EFER:
1585 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1586 add_atomic_switch_msr_special(vmx,
1587 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1588 VM_EXIT_LOAD_IA32_EFER,
1589 GUEST_IA32_EFER,
1590 HOST_IA32_EFER,
1591 guest_val, host_val);
1592 return;
1593 }
1594 break;
1595 case MSR_CORE_PERF_GLOBAL_CTRL:
1596 if (cpu_has_load_perf_global_ctrl) {
2961e876 1597 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1598 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1599 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1600 GUEST_IA32_PERF_GLOBAL_CTRL,
1601 HOST_IA32_PERF_GLOBAL_CTRL,
1602 guest_val, host_val);
1603 return;
1604 }
1605 break;
110312c8
AK		 1606 }
1607
61d2ef2c
AK		 1608 for (i = 0; i < m->nr; ++i)
1609 if (m->guest[i].index == msr)
1610 break;
1611
e7fc6f93 1612 if (i == NR_AUTOLOAD_MSRS) {
60266204 1613 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1614 "Can't add msr %x\n", msr);
1615 return;
1616 } else if (i == m->nr) {
61d2ef2c
AK		 1617 ++m->nr;
1618 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1619 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1620 }
1621
1622 m->guest[i].index = msr;
1623 m->guest[i].value = guest_val;
1624 m->host[i].index = msr;
1625 m->host[i].value = host_val;
1626}
1627
33ed6329
AK		 1628static void reload_tss(void)
1629{
33ed6329
AK		 1630 /*
1631 * VT restores TR but not its size. Useless.
1632 */
89cbc767 1633 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1634 struct desc_struct *descs;
33ed6329 1635
d359192f 1636 descs = (void *)gdt->address;
33ed6329
AK		 1637 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1638 load_TR_desc();
33ed6329
AK		 1639}
1640
92c0d900 1641static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1642{
3a34a881 1643 u64 guest_efer;
51c6cf66
AK		 1644 u64 ignore_bits;
1645
f6801dff 1646 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1647
51c6cf66 1648 /*
0fa06071 1649 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1650 * outside long mode
1651 */
1652 ignore_bits = EFER_NX | EFER_SCE;
1653#ifdef CONFIG_X86_64
1654 ignore_bits |= EFER_LMA | EFER_LME;
1655 /* SCE is meaningful only in long mode on Intel */
1656 if (guest_efer & EFER_LMA)
1657 ignore_bits &= ~(u64)EFER_SCE;
1658#endif
51c6cf66
AK		 1659 guest_efer &= ~ignore_bits;
1660 guest_efer |= host_efer & ignore_bits;
26bb0981 1661 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1662 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1663
1664 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1665
1666 /*
1667 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1668 * On CPUs that support "load IA32_EFER", always switch EFER
1669 * atomically, since it's faster than switching it manually.
1670 */
1671 if (cpu_has_load_ia32_efer ||
1672 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1673 guest_efer = vmx->vcpu.arch.efer;
1674 if (!(guest_efer & EFER_LMA))
1675 guest_efer &= ~EFER_LME;
1676 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1677 return false;
1678 }
1679
26bb0981 1680 return true;
51c6cf66
AK		 1681}
1682
2d49ec72
GN		 1683static unsigned long segment_base(u16 selector)
1684{
89cbc767 1685 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1686 struct desc_struct *d;
1687 unsigned long table_base;
1688 unsigned long v;
1689
1690 if (!(selector & ~3))
1691 return 0;
1692
d359192f 1693 table_base = gdt->address;
2d49ec72
GN		 1694
1695 if (selector & 4) { /* from ldt */
1696 u16 ldt_selector = kvm_read_ldt();
1697
1698 if (!(ldt_selector & ~3))
1699 return 0;
1700
1701 table_base = segment_base(ldt_selector);
1702 }
1703 d = (struct desc_struct *)(table_base + (selector & ~7));
1704 v = get_desc_base(d);
1705#ifdef CONFIG_X86_64
1706 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1707 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1708#endif
1709 return v;
1710}
1711
1712static inline unsigned long kvm_read_tr_base(void)
1713{
1714 u16 tr;
1715 asm("str %0" : "=g"(tr));
1716 return segment_base(tr);
1717}
1718
04d2cc77 1719static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1720{
04d2cc77 1721 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1722 int i;
04d2cc77 1723
a2fa3e9f 1724 if (vmx->host_state.loaded)
33ed6329
AK		 1725 return;
1726
a2fa3e9f 1727 vmx->host_state.loaded = 1;
33ed6329
AK		 1728 /*
1729 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1730 * allow segment selectors with cpl > 0 or ti == 1.
1731 */
d6e88aec 1732 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1733 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1734 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1735 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1736 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1737 vmx->host_state.fs_reload_needed = 0;
1738 } else {
33ed6329 1739 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1740 vmx->host_state.fs_reload_needed = 1;
33ed6329 1741 }
9581d442 1742 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1743 if (!(vmx->host_state.gs_sel & 7))
1744 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1745 else {
1746 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1747 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1748 }
1749
b2da15ac
AK		 1750#ifdef CONFIG_X86_64
1751 savesegment(ds, vmx->host_state.ds_sel);
1752 savesegment(es, vmx->host_state.es_sel);
1753#endif
1754
33ed6329
AK		 1755#ifdef CONFIG_X86_64
1756 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1757 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1758#else
a2fa3e9f
GH		 1759 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1760 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1761#endif
707c0874
AK		 1762
1763#ifdef CONFIG_X86_64
c8770e7b
AK		 1764 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1765 if (is_long_mode(&vmx->vcpu))
44ea2b17 1766 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1767#endif
da8999d3
LJ		 1768 if (boot_cpu_has(X86_FEATURE_MPX))
1769 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1770 for (i = 0; i < vmx->save_nmsrs; ++i)
1771 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1772 vmx->guest_msrs[i].data,
1773 vmx->guest_msrs[i].mask);
33ed6329
AK		 1774}
1775
a9b21b62 1776static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1777{
a2fa3e9f 1778 if (!vmx->host_state.loaded)
33ed6329
AK		 1779 return;
1780
e1beb1d3 1781 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1782 vmx->host_state.loaded = 0;
c8770e7b
AK		 1783#ifdef CONFIG_X86_64
1784 if (is_long_mode(&vmx->vcpu))
1785 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1786#endif
152d3f2f 1787 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1788 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1789#ifdef CONFIG_X86_64
9581d442 1790 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1791#else
1792 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1793#endif
33ed6329 1794 }
0a77fe4c
AK		 1795 if (vmx->host_state.fs_reload_needed)
1796 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1797#ifdef CONFIG_X86_64
1798 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1799 loadsegment(ds, vmx->host_state.ds_sel);
1800 loadsegment(es, vmx->host_state.es_sel);
1801 }
b2da15ac 1802#endif
152d3f2f 1803 reload_tss();
44ea2b17 1804#ifdef CONFIG_X86_64
c8770e7b 1805 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1806#endif
da8999d3
LJ		 1807 if (vmx->host_state.msr_host_bndcfgs)
1808 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1809 /*
1810 * If the FPU is not active (through the host task or
1811 * the guest vcpu), then restore the cr0.TS bit.
1812 */
1813 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1814 stts();
89cbc767 1815 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1816}
1817
a9b21b62
AK		 1818static void vmx_load_host_state(struct vcpu_vmx *vmx)
1819{
1820 preempt_disable();
1821 __vmx_load_host_state(vmx);
1822 preempt_enable();
1823}
1824
6aa8b732
AK		 1825/*
1826 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1827 * vcpu mutex is already taken.
1828 */
15ad7146 1829static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1830{
a2fa3e9f 1831 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1832 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1833
4610c9cc
DX		 1834 if (!vmm_exclusive)
1835 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1836 else if (vmx->loaded_vmcs->cpu != cpu)
1837 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1838
d462b819
NHE		 1839 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1840 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1841 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1842 }
1843
d462b819 1844 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1845 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1846 unsigned long sysenter_esp;
1847
a8eeb04a 1848 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1849 local_irq_disable();
8f536b76 1850 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1851
1852 /*
1853 * Read loaded_vmcs->cpu should be before fetching
1854 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1855 * See the comments in __loaded_vmcs_clear().
1856 */
1857 smp_rmb();
1858
d462b819
NHE		 1859 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1860 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1861 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1862 local_irq_enable();
1863
6aa8b732
AK		 1864 /*
1865 * Linux uses per-cpu TSS and GDT, so set these when switching
1866 * processors.
1867 */
d6e88aec 1868 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1869 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1870
1871 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1872 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1873 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1874 }
6aa8b732
AK		 1875}
1876
1877static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1878{
a9b21b62 1879 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1880 if (!vmm_exclusive) {
d462b819
NHE		 1881 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1882 vcpu->cpu = -1;
4610c9cc
DX		 1883 kvm_cpu_vmxoff();
1884 }
6aa8b732
AK		 1885}
1886
5fd86fcf
AK		 1887static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1888{
81231c69
AK		 1889 ulong cr0;
1890
5fd86fcf
AK		 1891 if (vcpu->fpu_active)
1892 return;
1893 vcpu->fpu_active = 1;
81231c69
AK		 1894 cr0 = vmcs_readl(GUEST_CR0);
1895 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1896 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1897 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1898 update_exception_bitmap(vcpu);
edcafe3c 1899 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1900 if (is_guest_mode(vcpu))
1901 vcpu->arch.cr0_guest_owned_bits &=
1902 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1903 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1904}
1905
edcafe3c
AK		 1906static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1907
fe3ef05c
NHE		 1908/*
1909 * Return the cr0 value that a nested guest would read. This is a combination
1910 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1911 * its hypervisor (cr0_read_shadow).
1912 */
1913static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1914{
1915 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1916 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1917}
1918static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1919{
1920 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1921 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1922}
1923
5fd86fcf
AK		 1924static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1925{
36cf24e0
NHE		 1926 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1927 * set this *before* calling this function.
1928 */
edcafe3c 1929 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1930 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1931 update_exception_bitmap(vcpu);
edcafe3c
AK		 1932 vcpu->arch.cr0_guest_owned_bits = 0;
1933 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1934 if (is_guest_mode(vcpu)) {
1935 /*
1936 * L1's specified read shadow might not contain the TS bit,
1937 * so now that we turned on shadowing of this bit, we need to
1938 * set this bit of the shadow. Like in nested_vmx_run we need
1939 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1940 * up-to-date here because we just decached cr0.TS (and we'll
1941 * only update vmcs12->guest_cr0 on nested exit).
1942 */
1943 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1944 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1945 (vcpu->arch.cr0 & X86_CR0_TS);
1946 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1947 } else
1948 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1949}
1950
6aa8b732
AK		 1951static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1952{
78ac8b47 1953 unsigned long rflags, save_rflags;
345dcaa8 1954
6de12732
AK		 1955 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1956 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1957 rflags = vmcs_readl(GUEST_RFLAGS);
1958 if (to_vmx(vcpu)->rmode.vm86_active) {
1959 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1960 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1961 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1962 }
1963 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1964 }
6de12732 1965 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1966}
1967
1968static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1969{
6de12732
AK		 1970 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1971 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1972 if (to_vmx(vcpu)->rmode.vm86_active) {
1973 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1974 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1975 }
6aa8b732
AK		 1976 vmcs_writel(GUEST_RFLAGS, rflags);
1977}
1978
37ccdcbe 1979static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1980{
1981 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1982 int ret = 0;
1983
1984 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1985 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1986 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1987 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1988
37ccdcbe 1989 return ret;
2809f5d2
GC		 1990}
1991
1992static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1993{
1994 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1995 u32 interruptibility = interruptibility_old;
1996
1997 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1998
48005f64 1999 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2000 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2001 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2002 interruptibility |= GUEST_INTR_STATE_STI;
2003
2004 if ((interruptibility != interruptibility_old))
2005 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2006}
2007
6aa8b732
AK		 2008static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2009{
2010 unsigned long rip;
6aa8b732 2011
5fdbf976 2012 rip = kvm_rip_read(vcpu);
6aa8b732 2013 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2014 kvm_rip_write(vcpu, rip);
6aa8b732 2015
2809f5d2
GC		 2016 /* skipping an emulated instruction also counts */
2017 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2018}
2019
0b6ac343
NHE		 2020/*
2021 * KVM wants to inject page-faults which it got to the guest. This function
2022 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2023 */
e011c663 2024static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2025{
2026 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2027
e011c663 2028 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2029 return 0;
2030
533558bc
JK		 2031 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2032 vmcs_read32(VM_EXIT_INTR_INFO),
2033 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2034 return 1;
2035}
2036
298101da 2037static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2038 bool has_error_code, u32 error_code,
2039 bool reinject)
298101da 2040{
77ab6db0 2041 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2042 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2043
e011c663
GN		 2044 if (!reinject && is_guest_mode(vcpu) &&
2045 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2046 return;
2047
8ab2d2e2 2048 if (has_error_code) {
77ab6db0 2049 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2050 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2051 }
77ab6db0 2052
7ffd92c5 2053 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2054 int inc_eip = 0;
2055 if (kvm_exception_is_soft(nr))
2056 inc_eip = vcpu->arch.event_exit_inst_len;
2057 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2058 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2059 return;
2060 }
2061
66fd3f7f
GN		 2062 if (kvm_exception_is_soft(nr)) {
2063 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2064 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2065 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2066 } else
2067 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2068
2069 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2070}
2071
4e47c7a6
SY		 2072static bool vmx_rdtscp_supported(void)
2073{
2074 return cpu_has_vmx_rdtscp();
2075}
2076
ad756a16
MJ		 2077static bool vmx_invpcid_supported(void)
2078{
2079 return cpu_has_vmx_invpcid() && enable_ept;
2080}
2081
a75beee6
ED		 2082/*
2083 * Swap MSR entry in host/guest MSR entry array.
2084 */
8b9cf98c 2085static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2086{
26bb0981 2087 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2088
2089 tmp = vmx->guest_msrs[to];
2090 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2091 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2092}
2093
8d14695f
YZ		 2094static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2095{
2096 unsigned long *msr_bitmap;
2097
2098 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2099 if (is_long_mode(vcpu))
2100 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2101 else
2102 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2103 } else {
2104 if (is_long_mode(vcpu))
2105 msr_bitmap = vmx_msr_bitmap_longmode;
2106 else
2107 msr_bitmap = vmx_msr_bitmap_legacy;
2108 }
2109
2110 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2111}
2112
e38aea3e
AK		 2113/*
2114 * Set up the vmcs to automatically save and restore system
2115 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2116 * mode, as fiddling with msrs is very expensive.
2117 */
8b9cf98c 2118static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2119{
26bb0981 2120 int save_nmsrs, index;
e38aea3e 2121
a75beee6
ED		 2122 save_nmsrs = 0;
2123#ifdef CONFIG_X86_64
8b9cf98c 2124 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2125 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2126 if (index >= 0)
8b9cf98c
RR		 2127 move_msr_up(vmx, index, save_nmsrs++);
2128 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2129 if (index >= 0)
8b9cf98c
RR		 2130 move_msr_up(vmx, index, save_nmsrs++);
2131 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2132 if (index >= 0)
8b9cf98c 2133 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2134 index = __find_msr_index(vmx, MSR_TSC_AUX);
2135 if (index >= 0 && vmx->rdtscp_enabled)
2136 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2137 /*
8c06585d 2138 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2139 * if efer.sce is enabled.
2140 */
8c06585d 2141 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2142 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2143 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2144 }
2145#endif
92c0d900
AK		 2146 index = __find_msr_index(vmx, MSR_EFER);
2147 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2148 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2149
26bb0981 2150 vmx->save_nmsrs = save_nmsrs;
5897297b 2151
8d14695f
YZ		 2152 if (cpu_has_vmx_msr_bitmap())
2153 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2154}
2155
6aa8b732
AK		 2156/*
2157 * reads and returns guest's timestamp counter "register"
2158 * guest_tsc = host_tsc + tsc_offset -- 21.3
2159 */
2160static u64 guest_read_tsc(void)
2161{
2162 u64 host_tsc, tsc_offset;
2163
2164 rdtscll(host_tsc);
2165 tsc_offset = vmcs_read64(TSC_OFFSET);
2166 return host_tsc + tsc_offset;
2167}
2168
d5c1785d
NHE		 2169/*
2170 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2171 * counter, even if a nested guest (L2) is currently running.
2172 */
48d89b92 2173static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2174{
886b470c 2175 u64 tsc_offset;
d5c1785d 2176
d5c1785d
NHE		 2177 tsc_offset = is_guest_mode(vcpu) ?
2178 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2179 vmcs_read64(TSC_OFFSET);
2180 return host_tsc + tsc_offset;
2181}
2182
4051b188 2183/*
cc578287
ZA		 2184 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2185 * software catchup for faster rates on slower CPUs.
4051b188 2186 */
cc578287 2187static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2188{
cc578287
ZA		 2189 if (!scale)
2190 return;
2191
2192 if (user_tsc_khz > tsc_khz) {
2193 vcpu->arch.tsc_catchup = 1;
2194 vcpu->arch.tsc_always_catchup = 1;
2195 } else
2196 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2197}
2198
ba904635
WA		 2199static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2200{
2201 return vmcs_read64(TSC_OFFSET);
2202}
2203
6aa8b732 2204/*
99e3e30a 2205 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2206 */
99e3e30a 2207static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2208{
27fc51b2 2209 if (is_guest_mode(vcpu)) {
7991825b 2210 /*
27fc51b2
NHE		 2211 * We're here if L1 chose not to trap WRMSR to TSC. According
2212 * to the spec, this should set L1's TSC; The offset that L1
2213 * set for L2 remains unchanged, and still needs to be added
2214 * to the newly set TSC to get L2's TSC.
7991825b 2215 */
27fc51b2
NHE		 2216 struct vmcs12 *vmcs12;
2217 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2218 /* recalculate vmcs02.TSC_OFFSET: */
2219 vmcs12 = get_vmcs12(vcpu);
2220 vmcs_write64(TSC_OFFSET, offset +
2221 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2222 vmcs12->tsc_offset : 0));
2223 } else {
489223ed
YY		 2224 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2225 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2226 vmcs_write64(TSC_OFFSET, offset);
2227 }
6aa8b732
AK		 2228}
2229
f1e2b260 2230static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2231{
2232 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2233
e48672fa 2234 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2235 if (is_guest_mode(vcpu)) {
2236 /* Even when running L2, the adjustment needs to apply to L1 */
2237 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2238 } else
2239 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2240 offset + adjustment);
e48672fa
ZA		 2241}
2242
857e4099
JR		 2243static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2244{
2245 return target_tsc - native_read_tsc();
2246}
2247
801d3424
NHE		 2248static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2249{
2250 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2251 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2252}
2253
2254/*
2255 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2256 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2257 * all guests if the "nested" module option is off, and can also be disabled
2258 * for a single guest by disabling its VMX cpuid bit.
2259 */
2260static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2261{
2262 return nested && guest_cpuid_has_vmx(vcpu);
2263}
2264
b87a51ae
NHE		 2265/*
2266 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2267 * returned for the various VMX controls MSRs when nested VMX is enabled.
2268 * The same values should also be used to verify that vmcs12 control fields are
2269 * valid during nested entry from L1 to L2.
2270 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2271 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2272 * bit in the high half is on if the corresponding bit in the control field
2273 * may be on. See also vmx_control_verify().
2274 * TODO: allow these variables to be modified (downgraded) by module options
2275 * or other means.
2276 */
2277static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2278static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2279static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2280static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2281static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2282static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2283static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2284static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2285static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2286static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2287static __init void nested_vmx_setup_ctls_msrs(void)
2288{
2289 /*
2290 * Note that as a general rule, the high half of the MSRs (bits in
2291 * the control fields which may be 1) should be initialized by the
2292 * intersection of the underlying hardware's MSR (i.e., features which
2293 * can be supported) and the list of features we want to expose -
2294 * because they are known to be properly supported in our code.
2295 * Also, usually, the low half of the MSRs (bits which must be 1) can
2296 * be set to 0, meaning that L1 may turn off any of these bits. The
2297 * reason is that if one of these bits is necessary, it will appear
2298 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2299 * fields of vmcs01 and vmcs02, will turn these bits off - and
2300 * nested_vmx_exit_handled() will not pass related exits to L1.
2301 * These rules have exceptions below.
2302 */
2303
2304 /* pin-based controls */
eabeaacc
JK		 2305 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2306 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2307 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2308 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2309 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2310 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2311 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2312
3dbcd8da 2313 /* exit controls */
c0dfee58
ACL		 2314 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2315 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2316 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2317
c0dfee58 2318 nested_vmx_exit_ctls_high &=
b87a51ae 2319#ifdef CONFIG_X86_64
c0dfee58 2320 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2321#endif
f4124500
JK		 2322 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2323 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2324 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2325 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2326
36be0b9d
PB		 2327 if (vmx_mpx_supported())
2328 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2329
2996fca0
JK		 2330 /* We support free control of debug control saving. */
2331 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2332 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2333
b87a51ae
NHE		 2334 /* entry controls */
2335 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2336 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2337 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2338 nested_vmx_entry_ctls_high &=
57435349
JK		 2339#ifdef CONFIG_X86_64
2340 VM_ENTRY_IA32E_MODE |
2341#endif
2342 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2343 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2344 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2345 if (vmx_mpx_supported())
2346 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2347
2996fca0
JK		 2348 /* We support free control of debug control loading. */
2349 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2350 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2351
b87a51ae
NHE		 2352 /* cpu-based controls */
2353 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2354 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2355 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2356 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2357 CPU_BASED_VIRTUAL_INTR_PENDING |
2358 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2359 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2360 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2361 CPU_BASED_CR3_STORE_EXITING |
2362#ifdef CONFIG_X86_64
2363 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2364#endif
2365 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2366 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2367 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2368 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2369 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2370 /*
2371 * We can allow some features even when not supported by the
2372 * hardware. For example, L1 can specify an MSR bitmap - and we
2373 * can use it to avoid exits to L1 - even when L0 runs L2
2374 * without MSR bitmaps.
2375 */
560b7ee1
JK		 2376 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2377 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2378
3dcdf3ec
JK		 2379 /* We support free control of CR3 access interception. */
2380 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2381 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2382
b87a51ae
NHE		 2383 /* secondary cpu-based controls */
2384 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2385 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2386 nested_vmx_secondary_ctls_low = 0;
2387 nested_vmx_secondary_ctls_high &=
d6851fbe 2388 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2389 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2390 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2391
afa61f75
NHE		 2392 if (enable_ept) {
2393 /* nested EPT: emulate EPT also to L1 */
2394 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2395 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2396 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2397 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2398 nested_vmx_ept_caps &= vmx_capability.ept;
2399 /*
4b855078
BD		 2400 * For nested guests, we don't do anything specific
2401 * for single context invalidation. Hence, only advertise
2402 * support for global context invalidation.
afa61f75 2403 */
4b855078 2404 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2405 } else
2406 nested_vmx_ept_caps = 0;
2407
c18911a2
JK		 2408 /* miscellaneous data */
2409 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2410 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2411 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2412 VMX_MISC_ACTIVITY_HLT;
c18911a2 2413 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2414}
2415
2416static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2417{
2418 /*
2419 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2420 */
2421 return ((control & high) | low) == control;
2422}
2423
2424static inline u64 vmx_control_msr(u32 low, u32 high)
2425{
2426 return low | ((u64)high << 32);
2427}
2428
cae50139 2429/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2430static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2431{
b87a51ae 2432 switch (msr_index) {
b87a51ae
NHE		 2433 case MSR_IA32_VMX_BASIC:
2434 /*
2435 * This MSR reports some information about VMX support. We
2436 * should return information about the VMX we emulate for the
2437 * guest, and the VMCS structure we give it - not about the
2438 * VMX support of the underlying hardware.
2439 */
3dbcd8da 2440 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2441 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2442 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2443 break;
2444 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2445 case MSR_IA32_VMX_PINBASED_CTLS:
2446 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2447 nested_vmx_pinbased_ctls_high);
2448 break;
2449 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2450 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2451 nested_vmx_procbased_ctls_high);
2452 break;
b87a51ae
NHE		 2453 case MSR_IA32_VMX_PROCBASED_CTLS:
2454 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2455 nested_vmx_procbased_ctls_high);
2456 break;
2457 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2458 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2459 nested_vmx_exit_ctls_high);
2460 break;
b87a51ae
NHE		 2461 case MSR_IA32_VMX_EXIT_CTLS:
2462 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2463 nested_vmx_exit_ctls_high);
2464 break;
2465 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2466 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2467 nested_vmx_entry_ctls_high);
2468 break;
b87a51ae
NHE		 2469 case MSR_IA32_VMX_ENTRY_CTLS:
2470 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2471 nested_vmx_entry_ctls_high);
2472 break;
2473 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2474 *pdata = vmx_control_msr(nested_vmx_misc_low,
2475 nested_vmx_misc_high);
b87a51ae
NHE		 2476 break;
2477 /*
2478 * These MSRs specify bits which the guest must keep fixed (on or off)
2479 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2480 * We picked the standard core2 setting.
2481 */
2482#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2483#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2484 case MSR_IA32_VMX_CR0_FIXED0:
2485 *pdata = VMXON_CR0_ALWAYSON;
2486 break;
2487 case MSR_IA32_VMX_CR0_FIXED1:
2488 *pdata = -1ULL;
2489 break;
2490 case MSR_IA32_VMX_CR4_FIXED0:
2491 *pdata = VMXON_CR4_ALWAYSON;
2492 break;
2493 case MSR_IA32_VMX_CR4_FIXED1:
2494 *pdata = -1ULL;
2495 break;
2496 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2497 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2498 break;
2499 case MSR_IA32_VMX_PROCBASED_CTLS2:
2500 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2501 nested_vmx_secondary_ctls_high);
2502 break;
2503 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2504 /* Currently, no nested vpid support */
2505 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2506 break;
2507 default:
b87a51ae 2508 return 1;
b3897a49
NHE		 2509 }
2510
b87a51ae
NHE		 2511 return 0;
2512}
2513
6aa8b732
AK		 2514/*
2515 * Reads an msr value (of 'msr_index') into 'pdata'.
2516 * Returns 0 on success, non-0 otherwise.
2517 * Assumes vcpu_load() was already called.
2518 */
2519static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2520{
2521 u64 data;
26bb0981 2522 struct shared_msr_entry *msr;
6aa8b732
AK		 2523
2524 if (!pdata) {
2525 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2526 return -EINVAL;
2527 }
2528
2529 switch (msr_index) {
05b3e0c2 2530#ifdef CONFIG_X86_64
6aa8b732
AK		 2531 case MSR_FS_BASE:
2532 data = vmcs_readl(GUEST_FS_BASE);
2533 break;
2534 case MSR_GS_BASE:
2535 data = vmcs_readl(GUEST_GS_BASE);
2536 break;
44ea2b17
AK		 2537 case MSR_KERNEL_GS_BASE:
2538 vmx_load_host_state(to_vmx(vcpu));
2539 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2540 break;
26bb0981 2541#endif
6aa8b732 2542 case MSR_EFER:
3bab1f5d 2543 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2544 case MSR_IA32_TSC:
6aa8b732
AK		 2545 data = guest_read_tsc();
2546 break;
2547 case MSR_IA32_SYSENTER_CS:
2548 data = vmcs_read32(GUEST_SYSENTER_CS);
2549 break;
2550 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2551 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2552 break;
2553 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2554 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2555 break;
0dd376e7 2556 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2557 if (!vmx_mpx_supported())
2558 return 1;
0dd376e7
LJ		 2559 data = vmcs_read64(GUEST_BNDCFGS);
2560 break;
cae50139
JK		 2561 case MSR_IA32_FEATURE_CONTROL:
2562 if (!nested_vmx_allowed(vcpu))
2563 return 1;
2564 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2565 break;
2566 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2567 if (!nested_vmx_allowed(vcpu))
2568 return 1;
2569 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2570 case MSR_TSC_AUX:
2571 if (!to_vmx(vcpu)->rdtscp_enabled)
2572 return 1;
2573 /* Otherwise falls through */
6aa8b732 2574 default:
8b9cf98c 2575 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2576 if (msr) {
2577 data = msr->data;
2578 break;
6aa8b732 2579 }
3bab1f5d 2580 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2581 }
2582
2583 *pdata = data;
2584 return 0;
2585}
2586
cae50139
JK		 2587static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2588
6aa8b732
AK		 2589/*
2590 * Writes msr value into into the appropriate "register".
2591 * Returns 0 on success, non-0 otherwise.
2592 * Assumes vcpu_load() was already called.
2593 */
8fe8ab46 2594static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2595{
a2fa3e9f 2596 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2597 struct shared_msr_entry *msr;
2cc51560 2598 int ret = 0;
8fe8ab46
WA		 2599 u32 msr_index = msr_info->index;
2600 u64 data = msr_info->data;
2cc51560 2601
6aa8b732 2602 switch (msr_index) {
3bab1f5d 2603 case MSR_EFER:
8fe8ab46 2604 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2605 break;
16175a79 2606#ifdef CONFIG_X86_64
6aa8b732 2607 case MSR_FS_BASE:
2fb92db1 2608 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2609 vmcs_writel(GUEST_FS_BASE, data);
2610 break;
2611 case MSR_GS_BASE:
2fb92db1 2612 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2613 vmcs_writel(GUEST_GS_BASE, data);
2614 break;
44ea2b17
AK		 2615 case MSR_KERNEL_GS_BASE:
2616 vmx_load_host_state(vmx);
2617 vmx->msr_guest_kernel_gs_base = data;
2618 break;
6aa8b732
AK		 2619#endif
2620 case MSR_IA32_SYSENTER_CS:
2621 vmcs_write32(GUEST_SYSENTER_CS, data);
2622 break;
2623 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2624 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2625 break;
2626 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2627 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2628 break;
0dd376e7 2629 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2630 if (!vmx_mpx_supported())
2631 return 1;
0dd376e7
LJ		 2632 vmcs_write64(GUEST_BNDCFGS, data);
2633 break;
af24a4e4 2634 case MSR_IA32_TSC:
8fe8ab46 2635 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2636 break;
468d472f
SY		 2637 case MSR_IA32_CR_PAT:
2638 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2639 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2640 return 1;
468d472f
SY		 2641 vmcs_write64(GUEST_IA32_PAT, data);
2642 vcpu->arch.pat = data;
2643 break;
2644 }
8fe8ab46 2645 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2646 break;
ba904635
WA		 2647 case MSR_IA32_TSC_ADJUST:
2648 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2649 break;
cae50139
JK		 2650 case MSR_IA32_FEATURE_CONTROL:
2651 if (!nested_vmx_allowed(vcpu) ||
2652 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2653 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2654 return 1;
2655 vmx->nested.msr_ia32_feature_control = data;
2656 if (msr_info->host_initiated && data == 0)
2657 vmx_leave_nested(vcpu);
2658 break;
2659 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2660 return 1; /* they are read-only */
4e47c7a6
SY		 2661 case MSR_TSC_AUX:
2662 if (!vmx->rdtscp_enabled)
2663 return 1;
2664 /* Check reserved bit, higher 32 bits should be zero */
2665 if ((data >> 32) != 0)
2666 return 1;
2667 /* Otherwise falls through */
6aa8b732 2668 default:
8b9cf98c 2669 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2670 if (msr) {
8b3c3104 2671 u64 old_msr_data = msr->data;
3bab1f5d 2672 msr->data = data;
2225fd56
AK		 2673 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2674 preempt_disable();
8b3c3104
AH		 2675 ret = kvm_set_shared_msr(msr->index, msr->data,
2676 msr->mask);
2225fd56 2677 preempt_enable();
8b3c3104
AH		 2678 if (ret)
2679 msr->data = old_msr_data;
2225fd56 2680 }
3bab1f5d 2681 break;
6aa8b732 2682 }
8fe8ab46 2683 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2684 }
2685
2cc51560 2686 return ret;
6aa8b732
AK		 2687}
2688
5fdbf976 2689static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2690{
5fdbf976
MT		 2691 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2692 switch (reg) {
2693 case VCPU_REGS_RSP:
2694 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2695 break;
2696 case VCPU_REGS_RIP:
2697 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2698 break;
6de4f3ad
AK		 2699 case VCPU_EXREG_PDPTR:
2700 if (enable_ept)
2701 ept_save_pdptrs(vcpu);
2702 break;
5fdbf976
MT		 2703 default:
2704 break;
2705 }
6aa8b732
AK		 2706}
2707
6aa8b732
AK		 2708static __init int cpu_has_kvm_support(void)
2709{
6210e37b 2710 return cpu_has_vmx();
6aa8b732
AK		 2711}
2712
2713static __init int vmx_disabled_by_bios(void)
2714{
2715 u64 msr;
2716
2717 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2718 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2719 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2720 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2721 && tboot_enabled())
2722 return 1;
23f3e991 2723 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2724 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2725 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2726 && !tboot_enabled()) {
2727 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2728 "activate TXT before enabling KVM\n");
cafd6659 2729 return 1;
f9335afe 2730 }
23f3e991
JC		 2731 /* launched w/o TXT and VMX disabled */
2732 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2733 && !tboot_enabled())
2734 return 1;
cafd6659
SW		 2735 }
2736
2737 return 0;
6aa8b732
AK		 2738}
2739
7725b894
DX		 2740static void kvm_cpu_vmxon(u64 addr)
2741{
2742 asm volatile (ASM_VMX_VMXON_RAX
2743 : : "a"(&addr), "m"(addr)
2744 : "memory", "cc");
2745}
2746
13a34e06 2747static int hardware_enable(void)
6aa8b732
AK		 2748{
2749 int cpu = raw_smp_processor_id();
2750 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2751 u64 old, test_bits;
6aa8b732 2752
10474ae8
AG		 2753 if (read_cr4() & X86_CR4_VMXE)
2754 return -EBUSY;
2755
d462b819 2756 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2757
2758 /*
2759 * Now we can enable the vmclear operation in kdump
2760 * since the loaded_vmcss_on_cpu list on this cpu
2761 * has been initialized.
2762 *
2763 * Though the cpu is not in VMX operation now, there
2764 * is no problem to enable the vmclear operation
2765 * for the loaded_vmcss_on_cpu list is empty!
2766 */
2767 crash_enable_local_vmclear(cpu);
2768
6aa8b732 2769 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2770
2771 test_bits = FEATURE_CONTROL_LOCKED;
2772 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2773 if (tboot_enabled())
2774 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2775
2776 if ((old & test_bits) != test_bits) {
6aa8b732 2777 /* enable and lock */
cafd6659
SW		 2778 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2779 }
66aee91a 2780 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2781
4610c9cc
DX		 2782 if (vmm_exclusive) {
2783 kvm_cpu_vmxon(phys_addr);
2784 ept_sync_global();
2785 }
10474ae8 2786
89cbc767 2787 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2788
10474ae8 2789 return 0;
6aa8b732
AK		 2790}
2791
d462b819 2792static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2793{
2794 int cpu = raw_smp_processor_id();
d462b819 2795 struct loaded_vmcs *v, *n;
543e4243 2796
d462b819
NHE		 2797 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2798 loaded_vmcss_on_cpu_link)
2799 __loaded_vmcs_clear(v);
543e4243
AK		 2800}
2801
710ff4a8
EH		 2802
2803/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2804 * tricks.
2805 */
2806static void kvm_cpu_vmxoff(void)
6aa8b732 2807{
4ecac3fd 2808 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2809}
2810
13a34e06 2811static void hardware_disable(void)
710ff4a8 2812{
4610c9cc 2813 if (vmm_exclusive) {
d462b819 2814 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2815 kvm_cpu_vmxoff();
2816 }
7725b894 2817 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2818}
2819
1c3d14fe 2820static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2821 u32 msr, u32 *result)
1c3d14fe
YS		 2822{
2823 u32 vmx_msr_low, vmx_msr_high;
2824 u32 ctl = ctl_min | ctl_opt;
2825
2826 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2827
2828 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2829 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2830
2831 /* Ensure minimum (required) set of control bits are supported. */
2832 if (ctl_min & ~ctl)
002c7f7c 2833 return -EIO;
1c3d14fe
YS		 2834
2835 *result = ctl;
2836 return 0;
2837}
2838
110312c8
AK		 2839static __init bool allow_1_setting(u32 msr, u32 ctl)
2840{
2841 u32 vmx_msr_low, vmx_msr_high;
2842
2843 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2844 return vmx_msr_high & ctl;
2845}
2846
002c7f7c 2847static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2848{
2849 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2850 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2851 u32 _pin_based_exec_control = 0;
2852 u32 _cpu_based_exec_control = 0;
f78e0e2e 2853 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2854 u32 _vmexit_control = 0;
2855 u32 _vmentry_control = 0;
2856
10166744 2857 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2858#ifdef CONFIG_X86_64
2859 CPU_BASED_CR8_LOAD_EXITING |
2860 CPU_BASED_CR8_STORE_EXITING |
2861#endif
d56f546d
SY		 2862 CPU_BASED_CR3_LOAD_EXITING |
2863 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2864 CPU_BASED_USE_IO_BITMAPS |
2865 CPU_BASED_MOV_DR_EXITING |
a7052897 2866 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2867 CPU_BASED_MWAIT_EXITING |
2868 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2869 CPU_BASED_INVLPG_EXITING |
2870 CPU_BASED_RDPMC_EXITING;
443381a8 2871
f78e0e2e 2872 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2873 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2874 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2875 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2876 &_cpu_based_exec_control) < 0)
002c7f7c 2877 return -EIO;
6e5d865c
YS		 2878#ifdef CONFIG_X86_64
2879 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2880 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2881 ~CPU_BASED_CR8_STORE_EXITING;
2882#endif
f78e0e2e 2883 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2884 min2 = 0;
2885 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2886 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2887 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2888 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2889 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2890 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2891 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2892 SECONDARY_EXEC_RDTSCP |
83d4c286 2893 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2894 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2895 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2896 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2897 if (adjust_vmx_controls(min2, opt2,
2898 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2899 &_cpu_based_2nd_exec_control) < 0)
2900 return -EIO;
2901 }
2902#ifndef CONFIG_X86_64
2903 if (!(_cpu_based_2nd_exec_control &
2904 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2905 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2906#endif
83d4c286
YZ		 2907
2908 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2909 _cpu_based_2nd_exec_control &= ~(
8d14695f 2910 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2911 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2912 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2913
d56f546d 2914 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2915 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2916 enabled */
5fff7d27
GN		 2917 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2918 CPU_BASED_CR3_STORE_EXITING |
2919 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2920 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2921 vmx_capability.ept, vmx_capability.vpid);
2922 }
1c3d14fe 2923
81908bf4 2924 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2925#ifdef CONFIG_X86_64
2926 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2927#endif
a547c6db 2928 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2929 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2930 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2931 &_vmexit_control) < 0)
002c7f7c 2932 return -EIO;
1c3d14fe 2933
01e439be
YZ		 2934 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2935 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2936 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2937 &_pin_based_exec_control) < 0)
2938 return -EIO;
2939
2940 if (!(_cpu_based_2nd_exec_control &
2941 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2942 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2943 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2944
c845f9c6 2945 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2946 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2947 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2948 &_vmentry_control) < 0)
002c7f7c 2949 return -EIO;
6aa8b732 2950
c68876fd 2951 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2952
2953 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2954 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2955 return -EIO;
1c3d14fe
YS		 2956
2957#ifdef CONFIG_X86_64
2958 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2959 if (vmx_msr_high & (1u<<16))
002c7f7c 2960 return -EIO;
1c3d14fe
YS		 2961#endif
2962
2963 /* Require Write-Back (WB) memory type for VMCS accesses. */
2964 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2965 return -EIO;
1c3d14fe 2966
002c7f7c
YS		 2967 vmcs_conf->size = vmx_msr_high & 0x1fff;
2968 vmcs_conf->order = get_order(vmcs_config.size);
2969 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2970
002c7f7c
YS		 2971 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2972 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2973 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2974 vmcs_conf->vmexit_ctrl = _vmexit_control;
2975 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2976
110312c8
AK		 2977 cpu_has_load_ia32_efer =
2978 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2979 VM_ENTRY_LOAD_IA32_EFER)
2980 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2981 VM_EXIT_LOAD_IA32_EFER);
2982
8bf00a52
GN		 2983 cpu_has_load_perf_global_ctrl =
2984 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2985 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2986 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2987 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2988
2989 /*
2990 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2991 * but due to arrata below it can't be used. Workaround is to use
2992 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2993 *
2994 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2995 *
2996 * AAK155 (model 26)
2997 * AAP115 (model 30)
2998 * AAT100 (model 37)
2999 * BC86,AAY89,BD102 (model 44)
3000 * BA97 (model 46)
3001 *
3002 */
3003 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3004 switch (boot_cpu_data.x86_model) {
3005 case 26:
3006 case 30:
3007 case 37:
3008 case 44:
3009 case 46:
3010 cpu_has_load_perf_global_ctrl = false;
3011 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3012 "does not work properly. Using workaround\n");
3013 break;
3014 default:
3015 break;
3016 }
3017 }
3018
1c3d14fe 3019 return 0;
c68876fd 3020}
6aa8b732
AK		 3021
3022static struct vmcs *alloc_vmcs_cpu(int cpu)
3023{
3024 int node = cpu_to_node(cpu);
3025 struct page *pages;
3026 struct vmcs *vmcs;
3027
6484eb3e 3028 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3029 if (!pages)
3030 return NULL;
3031 vmcs = page_address(pages);
1c3d14fe
YS		 3032 memset(vmcs, 0, vmcs_config.size);
3033 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3034 return vmcs;
3035}
3036
3037static struct vmcs *alloc_vmcs(void)
3038{
d3b2c338 3039 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3040}
3041
3042static void free_vmcs(struct vmcs *vmcs)
3043{
1c3d14fe 3044 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3045}
3046
d462b819
NHE		 3047/*
3048 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3049 */
3050static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3051{
3052 if (!loaded_vmcs->vmcs)
3053 return;
3054 loaded_vmcs_clear(loaded_vmcs);
3055 free_vmcs(loaded_vmcs->vmcs);
3056 loaded_vmcs->vmcs = NULL;
3057}
3058
39959588 3059static void free_kvm_area(void)
6aa8b732
AK		 3060{
3061 int cpu;
3062
3230bb47 3063 for_each_possible_cpu(cpu) {
6aa8b732 3064 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3065 per_cpu(vmxarea, cpu) = NULL;
3066 }
6aa8b732
AK		 3067}
3068
fe2b201b
BD		 3069static void init_vmcs_shadow_fields(void)
3070{
3071 int i, j;
3072
3073 /* No checks for read only fields yet */
3074
3075 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3076 switch (shadow_read_write_fields[i]) {
3077 case GUEST_BNDCFGS:
3078 if (!vmx_mpx_supported())
3079 continue;
3080 break;
3081 default:
3082 break;
3083 }
3084
3085 if (j < i)
3086 shadow_read_write_fields[j] =
3087 shadow_read_write_fields[i];
3088 j++;
3089 }
3090 max_shadow_read_write_fields = j;
3091
3092 /* shadowed fields guest access without vmexit */
3093 for (i = 0; i < max_shadow_read_write_fields; i++) {
3094 clear_bit(shadow_read_write_fields[i],
3095 vmx_vmwrite_bitmap);
3096 clear_bit(shadow_read_write_fields[i],
3097 vmx_vmread_bitmap);
3098 }
3099 for (i = 0; i < max_shadow_read_only_fields; i++)
3100 clear_bit(shadow_read_only_fields[i],
3101 vmx_vmread_bitmap);
3102}
3103
6aa8b732
AK		 3104static __init int alloc_kvm_area(void)
3105{
3106 int cpu;
3107
3230bb47 3108 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3109 struct vmcs *vmcs;
3110
3111 vmcs = alloc_vmcs_cpu(cpu);
3112 if (!vmcs) {
3113 free_kvm_area();
3114 return -ENOMEM;
3115 }
3116
3117 per_cpu(vmxarea, cpu) = vmcs;
3118 }
3119 return 0;
3120}
3121
14168786
GN		 3122static bool emulation_required(struct kvm_vcpu *vcpu)
3123{
3124 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3125}
3126
91b0aa2c 3127static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3128 struct kvm_segment *save)
6aa8b732 3129{
d99e4152
GN		 3130 if (!emulate_invalid_guest_state) {
3131 /*
3132 * CS and SS RPL should be equal during guest entry according
3133 * to VMX spec, but in reality it is not always so. Since vcpu
3134 * is in the middle of the transition from real mode to
3135 * protected mode it is safe to assume that RPL 0 is a good
3136 * default value.
3137 */
3138 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3139 save->selector &= ~SELECTOR_RPL_MASK;
3140 save->dpl = save->selector & SELECTOR_RPL_MASK;
3141 save->s = 1;
6aa8b732 3142 }
d99e4152 3143 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3144}
3145
3146static void enter_pmode(struct kvm_vcpu *vcpu)
3147{
3148 unsigned long flags;
a89a8fb9 3149 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3150
d99e4152
GN		 3151 /*
3152 * Update real mode segment cache. It may be not up-to-date if sement
3153 * register was written while vcpu was in a guest mode.
3154 */
3155 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3156 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3157 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3158 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3159 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3161
7ffd92c5 3162 vmx->rmode.vm86_active = 0;
6aa8b732 3163
2fb92db1
AK		 3164 vmx_segment_cache_clear(vmx);
3165
f5f7b2fe 3166 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3167
3168 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3169 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3170 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3171 vmcs_writel(GUEST_RFLAGS, flags);
3172
66aee91a
RR		 3173 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3174 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3175
3176 update_exception_bitmap(vcpu);
3177
91b0aa2c
GN		 3178 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3179 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3180 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3181 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3182 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3183 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3184}
3185
f5f7b2fe 3186static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3187{
772e0318 3188 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3189 struct kvm_segment var = *save;
3190
3191 var.dpl = 0x3;
3192 if (seg == VCPU_SREG_CS)
3193 var.type = 0x3;
3194
3195 if (!emulate_invalid_guest_state) {
3196 var.selector = var.base >> 4;
3197 var.base = var.base & 0xffff0;
3198 var.limit = 0xffff;
3199 var.g = 0;
3200 var.db = 0;
3201 var.present = 1;
3202 var.s = 1;
3203 var.l = 0;
3204 var.unusable = 0;
3205 var.type = 0x3;
3206 var.avl = 0;
3207 if (save->base & 0xf)
3208 printk_once(KERN_WARNING "kvm: segment base is not "
3209 "paragraph aligned when entering "
3210 "protected mode (seg=%d)", seg);
3211 }
6aa8b732 3212
d99e4152
GN		 3213 vmcs_write16(sf->selector, var.selector);
3214 vmcs_write32(sf->base, var.base);
3215 vmcs_write32(sf->limit, var.limit);
3216 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3217}
3218
3219static void enter_rmode(struct kvm_vcpu *vcpu)
3220{
3221 unsigned long flags;
a89a8fb9 3222 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3223
f5f7b2fe
AK		 3224 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3225 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3226 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3227 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3228 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3229 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3230 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3231
7ffd92c5 3232 vmx->rmode.vm86_active = 1;
6aa8b732 3233
776e58ea
GN		 3234 /*
3235 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3236 * vcpu. Warn the user that an update is overdue.
776e58ea 3237 */
4918c6ca 3238 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3239 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3240 "called before entering vcpu\n");
776e58ea 3241
2fb92db1
AK		 3242 vmx_segment_cache_clear(vmx);
3243
4918c6ca 3244 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3245 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3246 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3247
3248 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3249 vmx->rmode.save_rflags = flags;
6aa8b732 3250
053de044 3251 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3252
3253 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3254 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3255 update_exception_bitmap(vcpu);
3256
d99e4152
GN		 3257 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3258 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3259 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3260 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3261 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3262 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3263
8668a3c4 3264 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3265}
3266
401d10de
AS		 3267static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3268{
3269 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3270 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3271
3272 if (!msr)
3273 return;
401d10de 3274
44ea2b17
AK		 3275 /*
3276 * Force kernel_gs_base reloading before EFER changes, as control
3277 * of this msr depends on is_long_mode().
3278 */
3279 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3280 vcpu->arch.efer = efer;
401d10de 3281 if (efer & EFER_LMA) {
2961e876 3282 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3283 msr->data = efer;
3284 } else {
2961e876 3285 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3286
3287 msr->data = efer & ~EFER_LME;
3288 }
3289 setup_msrs(vmx);
3290}
3291
05b3e0c2 3292#ifdef CONFIG_X86_64
6aa8b732
AK		 3293
3294static void enter_lmode(struct kvm_vcpu *vcpu)
3295{
3296 u32 guest_tr_ar;
3297
2fb92db1
AK		 3298 vmx_segment_cache_clear(to_vmx(vcpu));
3299
6aa8b732
AK		 3300 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3301 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3302 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3303 __func__);
6aa8b732
AK		 3304 vmcs_write32(GUEST_TR_AR_BYTES,
3305 (guest_tr_ar & ~AR_TYPE_MASK)
3306 | AR_TYPE_BUSY_64_TSS);
3307 }
da38f438 3308 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3309}
3310
3311static void exit_lmode(struct kvm_vcpu *vcpu)
3312{
2961e876 3313 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3314 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3315}
3316
3317#endif
3318
2384d2b3
SY		 3319static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3320{
b9d762fa 3321 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3322 if (enable_ept) {
3323 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3324 return;
4e1096d2 3325 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3326 }
2384d2b3
SY		 3327}
3328
e8467fda
AK		 3329static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3330{
3331 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3332
3333 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3334 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3335}
3336
aff48baa
AK		 3337static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3338{
3339 if (enable_ept && is_paging(vcpu))
3340 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3341 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3342}
3343
25c4c276 3344static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3345{
fc78f519
AK		 3346 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3347
3348 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3349 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3350}
3351
1439442c
SY		 3352static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3353{
d0d538b9
GN		 3354 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3355
6de4f3ad
AK		 3356 if (!test_bit(VCPU_EXREG_PDPTR,
3357 (unsigned long *)&vcpu->arch.regs_dirty))
3358 return;
3359
1439442c 3360 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3361 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3362 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3363 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3364 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3365 }
3366}
3367
8f5d549f
AK		 3368static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3369{
d0d538b9
GN		 3370 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3371
8f5d549f 3372 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3373 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3374 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3375 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3376 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3377 }
6de4f3ad
AK		 3378
3379 __set_bit(VCPU_EXREG_PDPTR,
3380 (unsigned long *)&vcpu->arch.regs_avail);
3381 __set_bit(VCPU_EXREG_PDPTR,
3382 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3383}
3384
5e1746d6 3385static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3386
3387static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3388 unsigned long cr0,
3389 struct kvm_vcpu *vcpu)
3390{
5233dd51
MT		 3391 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3392 vmx_decache_cr3(vcpu);
1439442c
SY		 3393 if (!(cr0 & X86_CR0_PG)) {
3394 /* From paging/starting to nonpaging */
3395 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3396 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3397 (CPU_BASED_CR3_LOAD_EXITING |
3398 CPU_BASED_CR3_STORE_EXITING));
3399 vcpu->arch.cr0 = cr0;
fc78f519 3400 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3401 } else if (!is_paging(vcpu)) {
3402 /* From nonpaging to paging */
3403 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3404 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3405 ~(CPU_BASED_CR3_LOAD_EXITING |
3406 CPU_BASED_CR3_STORE_EXITING));
3407 vcpu->arch.cr0 = cr0;
fc78f519 3408 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3409 }
95eb84a7
SY		 3410
3411 if (!(cr0 & X86_CR0_WP))
3412 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3413}
3414
6aa8b732
AK		 3415static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3416{
7ffd92c5 3417 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3418 unsigned long hw_cr0;
3419
5037878e 3420 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3421 if (enable_unrestricted_guest)
5037878e 3422 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3423 else {
5037878e 3424 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3425
218e763f
GN		 3426 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3427 enter_pmode(vcpu);
6aa8b732 3428
218e763f
GN		 3429 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3430 enter_rmode(vcpu);
3431 }
6aa8b732 3432
05b3e0c2 3433#ifdef CONFIG_X86_64
f6801dff 3434 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3435 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3436 enter_lmode(vcpu);
707d92fa 3437 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3438 exit_lmode(vcpu);
3439 }
3440#endif
3441
089d034e 3442 if (enable_ept)
1439442c
SY		 3443 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3444
02daab21 3445 if (!vcpu->fpu_active)
81231c69 3446 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3447
6aa8b732 3448 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3449 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3450 vcpu->arch.cr0 = cr0;
14168786
GN		 3451
3452 /* depends on vcpu->arch.cr0 to be set to a new value */
3453 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3454}
3455
1439442c
SY		 3456static u64 construct_eptp(unsigned long root_hpa)
3457{
3458 u64 eptp;
3459
3460 /* TODO write the value reading from MSR */
3461 eptp = VMX_EPT_DEFAULT_MT |
3462 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3463 if (enable_ept_ad_bits)
3464 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3465 eptp |= (root_hpa & PAGE_MASK);
3466
3467 return eptp;
3468}
3469
6aa8b732
AK		 3470static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3471{
1439442c
SY		 3472 unsigned long guest_cr3;
3473 u64 eptp;
3474
3475 guest_cr3 = cr3;
089d034e 3476 if (enable_ept) {
1439442c
SY		 3477 eptp = construct_eptp(cr3);
3478 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3479 if (is_paging(vcpu) || is_guest_mode(vcpu))
3480 guest_cr3 = kvm_read_cr3(vcpu);
3481 else
3482 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3483 ept_load_pdptrs(vcpu);
1439442c
SY		 3484 }
3485
2384d2b3 3486 vmx_flush_tlb(vcpu);
1439442c 3487 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3488}
3489
5e1746d6 3490static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3491{
7ffd92c5 3492 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3493 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3494
5e1746d6
NHE		 3495 if (cr4 & X86_CR4_VMXE) {
3496 /*
3497 * To use VMXON (and later other VMX instructions), a guest
3498 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3499 * So basically the check on whether to allow nested VMX
3500 * is here.
3501 */
3502 if (!nested_vmx_allowed(vcpu))
3503 return 1;
1a0d74e6
JK		 3504 }
3505 if (to_vmx(vcpu)->nested.vmxon &&
3506 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3507 return 1;
3508
ad312c7c 3509 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3510 if (enable_ept) {
3511 if (!is_paging(vcpu)) {
3512 hw_cr4 &= ~X86_CR4_PAE;
3513 hw_cr4 |= X86_CR4_PSE;
c08800a5 3514 /*
e1e746b3
FW		 3515 * SMEP/SMAP is disabled if CPU is in non-paging mode
3516 * in hardware. However KVM always uses paging mode to
c08800a5 3517 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3518 * To emulate this behavior, SMEP/SMAP needs to be
3519 * manually disabled when guest switches to non-paging
3520 * mode.
c08800a5 3521 */
e1e746b3 3522 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3523 } else if (!(cr4 & X86_CR4_PAE)) {
3524 hw_cr4 &= ~X86_CR4_PAE;
3525 }
3526 }
1439442c
SY		 3527
3528 vmcs_writel(CR4_READ_SHADOW, cr4);
3529 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3530 return 0;
6aa8b732
AK		 3531}
3532
6aa8b732
AK		 3533static void vmx_get_segment(struct kvm_vcpu *vcpu,
3534 struct kvm_segment *var, int seg)
3535{
a9179499 3536 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3537 u32 ar;
3538
c6ad1153 3539 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3540 *var = vmx->rmode.segs[seg];
a9179499 3541 if (seg == VCPU_SREG_TR
2fb92db1 3542 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3543 return;
1390a28b
AK		 3544 var->base = vmx_read_guest_seg_base(vmx, seg);
3545 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3546 return;
a9179499 3547 }
2fb92db1
AK		 3548 var->base = vmx_read_guest_seg_base(vmx, seg);
3549 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3550 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3551 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3552 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3553 var->type = ar & 15;
3554 var->s = (ar >> 4) & 1;
3555 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3556 /*
3557 * Some userspaces do not preserve unusable property. Since usable
3558 * segment has to be present according to VMX spec we can use present
3559 * property to amend userspace bug by making unusable segment always
3560 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3561 * segment as unusable.
3562 */
3563 var->present = !var->unusable;
6aa8b732
AK		 3564 var->avl = (ar >> 12) & 1;
3565 var->l = (ar >> 13) & 1;
3566 var->db = (ar >> 14) & 1;
3567 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3568}
3569
a9179499
AK		 3570static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3571{
a9179499
AK		 3572 struct kvm_segment s;
3573
3574 if (to_vmx(vcpu)->rmode.vm86_active) {
3575 vmx_get_segment(vcpu, &s, seg);
3576 return s.base;
3577 }
2fb92db1 3578 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3579}
3580
b09408d0 3581static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3582{
b09408d0
MT		 3583 struct vcpu_vmx *vmx = to_vmx(vcpu);
3584
ae9fedc7 3585 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3586 return 0;
ae9fedc7
PB		 3587 else {
3588 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3589 return AR_DPL(ar);
69c73028 3590 }
69c73028
AK		 3591}
3592
653e3108 3593static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3594{
6aa8b732
AK		 3595 u32 ar;
3596
f0495f9b 3597 if (var->unusable || !var->present)
6aa8b732
AK		 3598 ar = 1 << 16;
3599 else {
3600 ar = var->type & 15;
3601 ar |= (var->s & 1) << 4;
3602 ar |= (var->dpl & 3) << 5;
3603 ar |= (var->present & 1) << 7;
3604 ar |= (var->avl & 1) << 12;
3605 ar |= (var->l & 1) << 13;
3606 ar |= (var->db & 1) << 14;
3607 ar |= (var->g & 1) << 15;
3608 }
653e3108
AK		 3609
3610 return ar;
3611}
3612
3613static void vmx_set_segment(struct kvm_vcpu *vcpu,
3614 struct kvm_segment *var, int seg)
3615{
7ffd92c5 3616 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3617 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3618
2fb92db1
AK		 3619 vmx_segment_cache_clear(vmx);
3620
1ecd50a9
GN		 3621 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3622 vmx->rmode.segs[seg] = *var;
3623 if (seg == VCPU_SREG_TR)
3624 vmcs_write16(sf->selector, var->selector);
3625 else if (var->s)
3626 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3627 goto out;
653e3108 3628 }
1ecd50a9 3629
653e3108
AK		 3630 vmcs_writel(sf->base, var->base);
3631 vmcs_write32(sf->limit, var->limit);
3632 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3633
3634 /*
3635 * Fix the "Accessed" bit in AR field of segment registers for older
3636 * qemu binaries.
3637 * IA32 arch specifies that at the time of processor reset the
3638 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3639 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3640 * state vmexit when "unrestricted guest" mode is turned on.
3641 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3642 * tree. Newer qemu binaries with that qemu fix would not need this
3643 * kvm hack.
3644 */
3645 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3646 var->type |= 0x1; /* Accessed */
3a624e29 3647
f924d66d 3648 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3649
3650out:
98eb2f8b 3651 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3652}
3653
6aa8b732
AK		 3654static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3655{
2fb92db1 3656 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3657
3658 *db = (ar >> 14) & 1;
3659 *l = (ar >> 13) & 1;
3660}
3661
89a27f4d 3662static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3663{
89a27f4d
GN		 3664 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3665 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3666}
3667
89a27f4d 3668static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3669{
89a27f4d
GN		 3670 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3671 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3672}
3673
89a27f4d 3674static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3675{
89a27f4d
GN		 3676 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3677 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3678}
3679
89a27f4d 3680static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3681{
89a27f4d
GN		 3682 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3683 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3684}
3685
648dfaa7
MG		 3686static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3687{
3688 struct kvm_segment var;
3689 u32 ar;
3690
3691 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3692 var.dpl = 0x3;
0647f4aa
GN		 3693 if (seg == VCPU_SREG_CS)
3694 var.type = 0x3;
648dfaa7
MG		 3695 ar = vmx_segment_access_rights(&var);
3696
3697 if (var.base != (var.selector << 4))
3698 return false;
89efbed0 3699 if (var.limit != 0xffff)
648dfaa7 3700 return false;
07f42f5f 3701 if (ar != 0xf3)
648dfaa7
MG		 3702 return false;
3703
3704 return true;
3705}
3706
3707static bool code_segment_valid(struct kvm_vcpu *vcpu)
3708{
3709 struct kvm_segment cs;
3710 unsigned int cs_rpl;
3711
3712 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3713 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3714
1872a3f4
AK		 3715 if (cs.unusable)
3716 return false;
648dfaa7
MG		 3717 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3718 return false;
3719 if (!cs.s)
3720 return false;
1872a3f4 3721 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3722 if (cs.dpl > cs_rpl)
3723 return false;
1872a3f4 3724 } else {
648dfaa7
MG		 3725 if (cs.dpl != cs_rpl)
3726 return false;
3727 }
3728 if (!cs.present)
3729 return false;
3730
3731 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3732 return true;
3733}
3734
3735static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3736{
3737 struct kvm_segment ss;
3738 unsigned int ss_rpl;
3739
3740 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3741 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3742
1872a3f4
AK		 3743 if (ss.unusable)
3744 return true;
3745 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3746 return false;
3747 if (!ss.s)
3748 return false;
3749 if (ss.dpl != ss_rpl) /* DPL != RPL */
3750 return false;
3751 if (!ss.present)
3752 return false;
3753
3754 return true;
3755}
3756
3757static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3758{
3759 struct kvm_segment var;
3760 unsigned int rpl;
3761
3762 vmx_get_segment(vcpu, &var, seg);
3763 rpl = var.selector & SELECTOR_RPL_MASK;
3764
1872a3f4
AK		 3765 if (var.unusable)
3766 return true;
648dfaa7
MG		 3767 if (!var.s)
3768 return false;
3769 if (!var.present)
3770 return false;
3771 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3772 if (var.dpl < rpl) /* DPL < RPL */
3773 return false;
3774 }
3775
3776 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3777 * rights flags
3778 */
3779 return true;
3780}
3781
3782static bool tr_valid(struct kvm_vcpu *vcpu)
3783{
3784 struct kvm_segment tr;
3785
3786 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3787
1872a3f4
AK		 3788 if (tr.unusable)
3789 return false;
648dfaa7
MG		 3790 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3791 return false;
1872a3f4 3792 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3793 return false;
3794 if (!tr.present)
3795 return false;
3796
3797 return true;
3798}
3799
3800static bool ldtr_valid(struct kvm_vcpu *vcpu)
3801{
3802 struct kvm_segment ldtr;
3803
3804 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3805
1872a3f4
AK		 3806 if (ldtr.unusable)
3807 return true;
648dfaa7
MG		 3808 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3809 return false;
3810 if (ldtr.type != 2)
3811 return false;
3812 if (!ldtr.present)
3813 return false;
3814
3815 return true;
3816}
3817
3818static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3819{
3820 struct kvm_segment cs, ss;
3821
3822 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3823 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3824
3825 return ((cs.selector & SELECTOR_RPL_MASK) ==
3826 (ss.selector & SELECTOR_RPL_MASK));
3827}
3828
3829/*
3830 * Check if guest state is valid. Returns true if valid, false if
3831 * not.
3832 * We assume that registers are always usable
3833 */
3834static bool guest_state_valid(struct kvm_vcpu *vcpu)
3835{
c5e97c80
GN		 3836 if (enable_unrestricted_guest)
3837 return true;
3838
648dfaa7 3839 /* real mode guest state checks */
f13882d8 3840 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3841 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3842 return false;
3843 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3844 return false;
3845 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3846 return false;
3847 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3848 return false;
3849 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3850 return false;
3851 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3852 return false;
3853 } else {
3854 /* protected mode guest state checks */
3855 if (!cs_ss_rpl_check(vcpu))
3856 return false;
3857 if (!code_segment_valid(vcpu))
3858 return false;
3859 if (!stack_segment_valid(vcpu))
3860 return false;
3861 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3862 return false;
3863 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3864 return false;
3865 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3866 return false;
3867 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3868 return false;
3869 if (!tr_valid(vcpu))
3870 return false;
3871 if (!ldtr_valid(vcpu))
3872 return false;
3873 }
3874 /* TODO:
3875 * - Add checks on RIP
3876 * - Add checks on RFLAGS
3877 */
3878
3879 return true;
3880}
3881
d77c26fc 3882static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3883{
40dcaa9f 3884 gfn_t fn;
195aefde 3885 u16 data = 0;
1f755a82 3886 int idx, r;
6aa8b732 3887
40dcaa9f 3888 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3889 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3890 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3891 if (r < 0)
10589a46 3892 goto out;
195aefde 3893 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3894 r = kvm_write_guest_page(kvm, fn++, &data,
3895 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3896 if (r < 0)
10589a46 3897 goto out;
195aefde
IE		 3898 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3899 if (r < 0)
10589a46 3900 goto out;
195aefde
IE		 3901 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3902 if (r < 0)
10589a46 3903 goto out;
195aefde 3904 data = ~0;
10589a46
MT		 3905 r = kvm_write_guest_page(kvm, fn, &data,
3906 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3907 sizeof(u8));
10589a46 3908out:
40dcaa9f 3909 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3910 return r;
6aa8b732
AK		 3911}
3912
b7ebfb05
SY		 3913static int init_rmode_identity_map(struct kvm *kvm)
3914{
f51770ed 3915 int i, idx, r = 0;
b7ebfb05
SY		 3916 pfn_t identity_map_pfn;
3917 u32 tmp;
3918
089d034e 3919 if (!enable_ept)
f51770ed 3920 return 0;
a255d479
TC		 3921
3922 /* Protect kvm->arch.ept_identity_pagetable_done. */
3923 mutex_lock(&kvm->slots_lock);
3924
f51770ed 3925 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3926 goto out2;
a255d479 3927
b927a3ce 3928 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3929
3930 r = alloc_identity_pagetable(kvm);
f51770ed 3931 if (r < 0)
a255d479
TC		 3932 goto out2;
3933
40dcaa9f 3934 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3935 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3936 if (r < 0)
3937 goto out;
3938 /* Set up identity-mapping pagetable for EPT in real mode */
3939 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3940 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3941 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3942 r = kvm_write_guest_page(kvm, identity_map_pfn,
3943 &tmp, i * sizeof(tmp), sizeof(tmp));
3944 if (r < 0)
3945 goto out;
3946 }
3947 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3948
b7ebfb05 3949out:
40dcaa9f 3950 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3951
3952out2:
3953 mutex_unlock(&kvm->slots_lock);
f51770ed 3954 return r;
b7ebfb05
SY		 3955}
3956
6aa8b732
AK		 3957static void seg_setup(int seg)
3958{
772e0318 3959 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3960 unsigned int ar;
6aa8b732
AK		 3961
3962 vmcs_write16(sf->selector, 0);
3963 vmcs_writel(sf->base, 0);
3964 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3965 ar = 0x93;
3966 if (seg == VCPU_SREG_CS)
3967 ar |= 0x08; /* code segment */
3a624e29
NK		 3968
3969 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3970}
3971
f78e0e2e
SY		 3972static int alloc_apic_access_page(struct kvm *kvm)
3973{
4484141a 3974 struct page *page;
f78e0e2e
SY		 3975 struct kvm_userspace_memory_region kvm_userspace_mem;
3976 int r = 0;
3977
79fac95e 3978 mutex_lock(&kvm->slots_lock);
c24ae0dc 3979 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 3980 goto out;
3981 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3982 kvm_userspace_mem.flags = 0;
73a6d941 3983 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 3984 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3985 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3986 if (r)
3987 goto out;
72dc67a6 3988
73a6d941 3989 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3990 if (is_error_page(page)) {
3991 r = -EFAULT;
3992 goto out;
3993 }
3994
c24ae0dc
TC		 3995 /*
3996 * Do not pin the page in memory, so that memory hot-unplug
3997 * is able to migrate it.
3998 */
3999 put_page(page);
4000 kvm->arch.apic_access_page_done = true;
f78e0e2e 4001out:
79fac95e 4002 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4003 return r;
4004}
4005
b7ebfb05
SY		 4006static int alloc_identity_pagetable(struct kvm *kvm)
4007{
a255d479
TC		 4008 /* Called with kvm->slots_lock held. */
4009
b7ebfb05
SY		 4010 struct kvm_userspace_memory_region kvm_userspace_mem;
4011 int r = 0;
4012
a255d479
TC		 4013 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4014
b7ebfb05
SY		 4015 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4016 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4017 kvm_userspace_mem.guest_phys_addr =
4018 kvm->arch.ept_identity_map_addr;
b7ebfb05 4019 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4020 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4021
b7ebfb05
SY		 4022 return r;
4023}
4024
2384d2b3
SY		 4025static void allocate_vpid(struct vcpu_vmx *vmx)
4026{
4027 int vpid;
4028
4029 vmx->vpid = 0;
919818ab 4030 if (!enable_vpid)
2384d2b3
SY		 4031 return;
4032 spin_lock(&vmx_vpid_lock);
4033 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4034 if (vpid < VMX_NR_VPIDS) {
4035 vmx->vpid = vpid;
4036 __set_bit(vpid, vmx_vpid_bitmap);
4037 }
4038 spin_unlock(&vmx_vpid_lock);
4039}
4040
cdbecfc3
LJ		 4041static void free_vpid(struct vcpu_vmx *vmx)
4042{
4043 if (!enable_vpid)
4044 return;
4045 spin_lock(&vmx_vpid_lock);
4046 if (vmx->vpid != 0)
4047 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4048 spin_unlock(&vmx_vpid_lock);
4049}
4050
8d14695f
YZ		 4051#define MSR_TYPE_R 1
4052#define MSR_TYPE_W 2
4053static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4054 u32 msr, int type)
25c5f225 4055{
3e7c73e9 4056 int f = sizeof(unsigned long);
25c5f225
SY		 4057
4058 if (!cpu_has_vmx_msr_bitmap())
4059 return;
4060
4061 /*
4062 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4063 * have the write-low and read-high bitmap offsets the wrong way round.
4064 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4065 */
25c5f225 4066 if (msr <= 0x1fff) {
8d14695f
YZ		 4067 if (type & MSR_TYPE_R)
4068 /* read-low */
4069 __clear_bit(msr, msr_bitmap + 0x000 / f);
4070
4071 if (type & MSR_TYPE_W)
4072 /* write-low */
4073 __clear_bit(msr, msr_bitmap + 0x800 / f);
4074
25c5f225
SY		 4075 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4076 msr &= 0x1fff;
8d14695f
YZ		 4077 if (type & MSR_TYPE_R)
4078 /* read-high */
4079 __clear_bit(msr, msr_bitmap + 0x400 / f);
4080
4081 if (type & MSR_TYPE_W)
4082 /* write-high */
4083 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4084
4085 }
4086}
4087
4088static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4089 u32 msr, int type)
4090{
4091 int f = sizeof(unsigned long);
4092
4093 if (!cpu_has_vmx_msr_bitmap())
4094 return;
4095
4096 /*
4097 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4098 * have the write-low and read-high bitmap offsets the wrong way round.
4099 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4100 */
4101 if (msr <= 0x1fff) {
4102 if (type & MSR_TYPE_R)
4103 /* read-low */
4104 __set_bit(msr, msr_bitmap + 0x000 / f);
4105
4106 if (type & MSR_TYPE_W)
4107 /* write-low */
4108 __set_bit(msr, msr_bitmap + 0x800 / f);
4109
4110 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4111 msr &= 0x1fff;
4112 if (type & MSR_TYPE_R)
4113 /* read-high */
4114 __set_bit(msr, msr_bitmap + 0x400 / f);
4115
4116 if (type & MSR_TYPE_W)
4117 /* write-high */
4118 __set_bit(msr, msr_bitmap + 0xc00 / f);
4119
25c5f225 4120 }
25c5f225
SY		 4121}
4122
5897297b
AK		 4123static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4124{
4125 if (!longmode_only)
8d14695f
YZ		 4126 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4127 msr, MSR_TYPE_R | MSR_TYPE_W);
4128 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4129 msr, MSR_TYPE_R | MSR_TYPE_W);
4130}
4131
4132static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4133{
4134 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4135 msr, MSR_TYPE_R);
4136 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4137 msr, MSR_TYPE_R);
4138}
4139
4140static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4141{
4142 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4143 msr, MSR_TYPE_R);
4144 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4145 msr, MSR_TYPE_R);
4146}
4147
4148static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4149{
4150 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4151 msr, MSR_TYPE_W);
4152 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4153 msr, MSR_TYPE_W);
5897297b
AK		 4154}
4155
01e439be
YZ		 4156static int vmx_vm_has_apicv(struct kvm *kvm)
4157{
4158 return enable_apicv && irqchip_in_kernel(kvm);
4159}
4160
a20ed54d
YZ		 4161/*
4162 * Send interrupt to vcpu via posted interrupt way.
4163 * 1. If target vcpu is running(non-root mode), send posted interrupt
4164 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4165 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4166 * interrupt from PIR in next vmentry.
4167 */
4168static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4169{
4170 struct vcpu_vmx *vmx = to_vmx(vcpu);
4171 int r;
4172
4173 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4174 return;
4175
4176 r = pi_test_and_set_on(&vmx->pi_desc);
4177 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4178#ifdef CONFIG_SMP
a20ed54d
YZ		 4179 if (!r && (vcpu->mode == IN_GUEST_MODE))
4180 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4181 POSTED_INTR_VECTOR);
4182 else
6ffbbbba 4183#endif
a20ed54d
YZ		 4184 kvm_vcpu_kick(vcpu);
4185}
4186
4187static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4188{
4189 struct vcpu_vmx *vmx = to_vmx(vcpu);
4190
4191 if (!pi_test_and_clear_on(&vmx->pi_desc))
4192 return;
4193
4194 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4195}
4196
4197static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4198{
4199 return;
4200}
4201
a3a8ff8e
NHE		 4202/*
4203 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4204 * will not change in the lifetime of the guest.
4205 * Note that host-state that does change is set elsewhere. E.g., host-state
4206 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4207 */
a547c6db 4208static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4209{
4210 u32 low32, high32;
4211 unsigned long tmpl;
4212 struct desc_ptr dt;
d974baa3 4213 unsigned long cr4;
a3a8ff8e 4214
b1a74bf8 4215 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4216 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4217
d974baa3
AL		 4218 /* Save the most likely value for this task's CR4 in the VMCS. */
4219 cr4 = read_cr4();
4220 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4221 vmx->host_state.vmcs_host_cr4 = cr4;
4222
a3a8ff8e 4223 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4224#ifdef CONFIG_X86_64
4225 /*
4226 * Load null selectors, so we can avoid reloading them in
4227 * __vmx_load_host_state(), in case userspace uses the null selectors
4228 * too (the expected case).
4229 */
4230 vmcs_write16(HOST_DS_SELECTOR, 0);
4231 vmcs_write16(HOST_ES_SELECTOR, 0);
4232#else
a3a8ff8e
NHE		 4233 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4234 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4235#endif
a3a8ff8e
NHE		 4236 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4237 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4238
4239 native_store_idt(&dt);
4240 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4241 vmx->host_idt_base = dt.address;
a3a8ff8e 4242
83287ea4 4243 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4244
4245 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4246 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4247 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4248 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4249
4250 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4251 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4252 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4253 }
4254}
4255
bf8179a0
NHE		 4256static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4257{
4258 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4259 if (enable_ept)
4260 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4261 if (is_guest_mode(&vmx->vcpu))
4262 vmx->vcpu.arch.cr4_guest_owned_bits &=
4263 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4264 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4265}
4266
01e439be
YZ		 4267static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4268{
4269 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4270
4271 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4272 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4273 return pin_based_exec_ctrl;
4274}
4275
bf8179a0
NHE		 4276static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4277{
4278 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4279
4280 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4281 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4282
bf8179a0
NHE		 4283 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4284 exec_control &= ~CPU_BASED_TPR_SHADOW;
4285#ifdef CONFIG_X86_64
4286 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4287 CPU_BASED_CR8_LOAD_EXITING;
4288#endif
4289 }
4290 if (!enable_ept)
4291 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4292 CPU_BASED_CR3_LOAD_EXITING |
4293 CPU_BASED_INVLPG_EXITING;
4294 return exec_control;
4295}
4296
4297static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4298{
4299 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4300 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4301 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4302 if (vmx->vpid == 0)
4303 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4304 if (!enable_ept) {
4305 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4306 enable_unrestricted_guest = 0;
ad756a16
MJ		 4307 /* Enable INVPCID for non-ept guests may cause performance regression. */
4308 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4309 }
4310 if (!enable_unrestricted_guest)
4311 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4312 if (!ple_gap)
4313 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4314 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4315 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4316 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4317 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4318 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4319 (handle_vmptrld).
4320 We can NOT enable shadow_vmcs here because we don't have yet
4321 a current VMCS12
4322 */
4323 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4324 return exec_control;
4325}
4326
ce88decf
XG		 4327static void ept_set_mmio_spte_mask(void)
4328{
4329 /*
4330 * EPT Misconfigurations can be generated if the value of bits 2:0
4331 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4332 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4333 * spte.
4334 */
885032b9 4335 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4336}
4337
6aa8b732
AK		 4338/*
4339 * Sets up the vmcs for emulated real mode.
4340 */
8b9cf98c 4341static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4342{
2e4ce7f5 4343#ifdef CONFIG_X86_64
6aa8b732 4344 unsigned long a;
2e4ce7f5 4345#endif
6aa8b732 4346 int i;
6aa8b732 4347
6aa8b732 4348 /* I/O */
3e7c73e9
AK		 4349 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4350 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4351
4607c2d7
AG		 4352 if (enable_shadow_vmcs) {
4353 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4354 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4355 }
25c5f225 4356 if (cpu_has_vmx_msr_bitmap())
5897297b 4357 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4358
6aa8b732
AK		 4359 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4360
6aa8b732 4361 /* Control */
01e439be 4362 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4363
bf8179a0 4364 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4365
83ff3b9d 4366 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4367 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4368 vmx_secondary_exec_control(vmx));
83ff3b9d 4369 }
f78e0e2e 4370
01e439be 4371 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4372 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4373 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4374 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4375 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4376
4377 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4378
4379 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4380 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4381 }
4382
4b8d54f9
ZE		 4383 if (ple_gap) {
4384 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4385 vmx->ple_window = ple_window;
4386 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4387 }
4388
c3707958
XG		 4389 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4390 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4391 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4392
9581d442
AK		 4393 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4394 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4395 vmx_set_constant_host_state(vmx);
05b3e0c2 4396#ifdef CONFIG_X86_64
6aa8b732
AK		 4397 rdmsrl(MSR_FS_BASE, a);
4398 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4399 rdmsrl(MSR_GS_BASE, a);
4400 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4401#else
4402 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4403 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4404#endif
4405
2cc51560
ED		 4406 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4407 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4408 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4409 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4410 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4411
468d472f 4412 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4413 u32 msr_low, msr_high;
4414 u64 host_pat;
468d472f
SY		 4415 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4416 host_pat = msr_low | ((u64) msr_high << 32);
4417 /* Write the default value follow host pat */
4418 vmcs_write64(GUEST_IA32_PAT, host_pat);
4419 /* Keep arch.pat sync with GUEST_IA32_PAT */
4420 vmx->vcpu.arch.pat = host_pat;
4421 }
4422
03916db9 4423 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4424 u32 index = vmx_msr_index[i];
4425 u32 data_low, data_high;
a2fa3e9f 4426 int j = vmx->nmsrs;
6aa8b732
AK		 4427
4428 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4429 continue;
432bd6cb
AK		 4430 if (wrmsr_safe(index, data_low, data_high) < 0)
4431 continue;
26bb0981
AK		 4432 vmx->guest_msrs[j].index = i;
4433 vmx->guest_msrs[j].data = 0;
d5696725 4434 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4435 ++vmx->nmsrs;
6aa8b732 4436 }
6aa8b732 4437
2961e876
GN		 4438
4439 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4440
4441 /* 22.2.1, 20.8.1 */
2961e876 4442 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4443
e00c8cf2 4444 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4445 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4446
4447 return 0;
4448}
4449
57f252f2 4450static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4451{
4452 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4453 struct msr_data apic_base_msr;
e00c8cf2 4454
7ffd92c5 4455 vmx->rmode.vm86_active = 0;
e00c8cf2 4456
3b86cd99
JK		 4457 vmx->soft_vnmi_blocked = 0;
4458
ad312c7c 4459 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4460 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4461 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4462 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4463 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4464 apic_base_msr.host_initiated = true;
4465 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4466
2fb92db1
AK		 4467 vmx_segment_cache_clear(vmx);
4468
5706be0d 4469 seg_setup(VCPU_SREG_CS);
66450a21 4470 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4471 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4472
4473 seg_setup(VCPU_SREG_DS);
4474 seg_setup(VCPU_SREG_ES);
4475 seg_setup(VCPU_SREG_FS);
4476 seg_setup(VCPU_SREG_GS);
4477 seg_setup(VCPU_SREG_SS);
4478
4479 vmcs_write16(GUEST_TR_SELECTOR, 0);
4480 vmcs_writel(GUEST_TR_BASE, 0);
4481 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4482 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4483
4484 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4485 vmcs_writel(GUEST_LDTR_BASE, 0);
4486 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4487 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4488
4489 vmcs_write32(GUEST_SYSENTER_CS, 0);
4490 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4491 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4492
4493 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4494 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4495
e00c8cf2
AK		 4496 vmcs_writel(GUEST_GDTR_BASE, 0);
4497 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4498
4499 vmcs_writel(GUEST_IDTR_BASE, 0);
4500 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4501
443381a8 4502 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4503 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4504 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4505
e00c8cf2
AK		 4506 /* Special registers */
4507 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4508
4509 setup_msrs(vmx);
4510
6aa8b732
AK		 4511 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4512
f78e0e2e
SY		 4513 if (cpu_has_vmx_tpr_shadow()) {
4514 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4515 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4517 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4518 vmcs_write32(TPR_THRESHOLD, 0);
4519 }
4520
a73896cb 4521 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4522
01e439be
YZ		 4523 if (vmx_vm_has_apicv(vcpu->kvm))
4524 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4525
2384d2b3
SY		 4526 if (vmx->vpid != 0)
4527 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4528
fa40052c 4529 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4530 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4531 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4532 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4533 vmx_fpu_activate(&vmx->vcpu);
4534 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4535
b9d762fa 4536 vpid_sync_context(vmx);
6aa8b732
AK		 4537}
4538
b6f1250e
NHE		 4539/*
4540 * In nested virtualization, check if L1 asked to exit on external interrupts.
4541 * For most existing hypervisors, this will always return true.
4542 */
4543static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4544{
4545 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4546 PIN_BASED_EXT_INTR_MASK;
4547}
4548
77b0f5d6
BD		 4549/*
4550 * In nested virtualization, check if L1 has set
4551 * VM_EXIT_ACK_INTR_ON_EXIT
4552 */
4553static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4554{
4555 return get_vmcs12(vcpu)->vm_exit_controls &
4556 VM_EXIT_ACK_INTR_ON_EXIT;
4557}
4558
ea8ceb83
JK		 4559static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4560{
4561 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4562 PIN_BASED_NMI_EXITING;
4563}
4564
c9a7953f 4565static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4566{
4567 u32 cpu_based_vm_exec_control;
730dca42 4568
3b86cd99
JK		 4569 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4570 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4571 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4572}
4573
c9a7953f 4574static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4575{
4576 u32 cpu_based_vm_exec_control;
4577
c9a7953f
JK		 4578 if (!cpu_has_virtual_nmis() ||
4579 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4580 enable_irq_window(vcpu);
4581 return;
4582 }
3b86cd99
JK		 4583
4584 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4585 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4586 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4587}
4588
66fd3f7f 4589static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4590{
9c8cba37 4591 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4592 uint32_t intr;
4593 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4594
229456fc 4595 trace_kvm_inj_virq(irq);
2714d1d3 4596
fa89a817 4597 ++vcpu->stat.irq_injections;
7ffd92c5 4598 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4599 int inc_eip = 0;
4600 if (vcpu->arch.interrupt.soft)
4601 inc_eip = vcpu->arch.event_exit_inst_len;
4602 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4603 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4604 return;
4605 }
66fd3f7f
GN		 4606 intr = irq | INTR_INFO_VALID_MASK;
4607 if (vcpu->arch.interrupt.soft) {
4608 intr |= INTR_TYPE_SOFT_INTR;
4609 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4610 vmx->vcpu.arch.event_exit_inst_len);
4611 } else
4612 intr |= INTR_TYPE_EXT_INTR;
4613 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4614}
4615
f08864b4
SY		 4616static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4617{
66a5a347
JK		 4618 struct vcpu_vmx *vmx = to_vmx(vcpu);
4619
0b6ac343
NHE		 4620 if (is_guest_mode(vcpu))
4621 return;
4622
3b86cd99
JK		 4623 if (!cpu_has_virtual_nmis()) {
4624 /*
4625 * Tracking the NMI-blocked state in software is built upon
4626 * finding the next open IRQ window. This, in turn, depends on
4627 * well-behaving guests: They have to keep IRQs disabled at
4628 * least as long as the NMI handler runs. Otherwise we may
4629 * cause NMI nesting, maybe breaking the guest. But as this is
4630 * highly unlikely, we can live with the residual risk.
4631 */
4632 vmx->soft_vnmi_blocked = 1;
4633 vmx->vnmi_blocked_time = 0;
4634 }
4635
487b391d 4636 ++vcpu->stat.nmi_injections;
9d58b931 4637 vmx->nmi_known_unmasked = false;
7ffd92c5 4638 if (vmx->rmode.vm86_active) {
71f9833b 4639 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4640 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4641 return;
4642 }
f08864b4
SY		 4643 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4644 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4645}
4646
3cfc3092
JK		 4647static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4648{
4649 if (!cpu_has_virtual_nmis())
4650 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4651 if (to_vmx(vcpu)->nmi_known_unmasked)
4652 return false;
c332c83a 4653 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4654}
4655
4656static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4657{
4658 struct vcpu_vmx *vmx = to_vmx(vcpu);
4659
4660 if (!cpu_has_virtual_nmis()) {
4661 if (vmx->soft_vnmi_blocked != masked) {
4662 vmx->soft_vnmi_blocked = masked;
4663 vmx->vnmi_blocked_time = 0;
4664 }
4665 } else {
9d58b931 4666 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4667 if (masked)
4668 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4669 GUEST_INTR_STATE_NMI);
4670 else
4671 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4672 GUEST_INTR_STATE_NMI);
4673 }
4674}
4675
2505dc9f
JK		 4676static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4677{
b6b8a145
JK		 4678 if (to_vmx(vcpu)->nested.nested_run_pending)
4679 return 0;
ea8ceb83 4680
2505dc9f
JK		 4681 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4682 return 0;
4683
4684 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4685 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4686 | GUEST_INTR_STATE_NMI));
4687}
4688
78646121
GN		 4689static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4690{
b6b8a145
JK		 4691 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4692 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4693 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4694 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4695}
4696
cbc94022
IE		 4697static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4698{
4699 int ret;
4700 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4701 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4702 .guest_phys_addr = addr,
4703 .memory_size = PAGE_SIZE * 3,
4704 .flags = 0,
4705 };
4706
47ae31e2 4707 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4708 if (ret)
4709 return ret;
bfc6d222 4710 kvm->arch.tss_addr = addr;
1f755a82 4711 return init_rmode_tss(kvm);
cbc94022
IE		 4712}
4713
0ca1b4f4 4714static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4715{
77ab6db0 4716 switch (vec) {
77ab6db0 4717 case BP_VECTOR:
c573cd22
JK		 4718 /*
4719 * Update instruction length as we may reinject the exception
4720 * from user space while in guest debugging mode.
4721 */
4722 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4723 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4724 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4725 return false;
4726 /* fall through */
4727 case DB_VECTOR:
4728 if (vcpu->guest_debug &
4729 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4730 return false;
d0bfb940
JK		 4731 /* fall through */
4732 case DE_VECTOR:
77ab6db0
JK		 4733 case OF_VECTOR:
4734 case BR_VECTOR:
4735 case UD_VECTOR:
4736 case DF_VECTOR:
4737 case SS_VECTOR:
4738 case GP_VECTOR:
4739 case MF_VECTOR:
0ca1b4f4
GN		 4740 return true;
4741 break;
77ab6db0 4742 }
0ca1b4f4
GN		 4743 return false;
4744}
4745
4746static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4747 int vec, u32 err_code)
4748{
4749 /*
4750 * Instruction with address size override prefix opcode 0x67
4751 * Cause the #SS fault with 0 error code in VM86 mode.
4752 */
4753 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4754 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4755 if (vcpu->arch.halt_request) {
4756 vcpu->arch.halt_request = 0;
4757 return kvm_emulate_halt(vcpu);
4758 }
4759 return 1;
4760 }
4761 return 0;
4762 }
4763
4764 /*
4765 * Forward all other exceptions that are valid in real mode.
4766 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4767 * the required debugging infrastructure rework.
4768 */
4769 kvm_queue_exception(vcpu, vec);
4770 return 1;
6aa8b732
AK		 4771}
4772
a0861c02
AK		 4773/*
4774 * Trigger machine check on the host. We assume all the MSRs are already set up
4775 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4776 * We pass a fake environment to the machine check handler because we want
4777 * the guest to be always treated like user space, no matter what context
4778 * it used internally.
4779 */
4780static void kvm_machine_check(void)
4781{
4782#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4783 struct pt_regs regs = {
4784 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4785 .flags = X86_EFLAGS_IF,
4786 };
4787
4788 do_machine_check(&regs, 0);
4789#endif
4790}
4791
851ba692 4792static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4793{
4794 /* already handled by vcpu_run */
4795 return 1;
4796}
4797
851ba692 4798static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4799{
1155f76a 4800 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4801 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4802 u32 intr_info, ex_no, error_code;
42dbaa5a 4803 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4804 u32 vect_info;
4805 enum emulation_result er;
4806
1155f76a 4807 vect_info = vmx->idt_vectoring_info;
88786475 4808 intr_info = vmx->exit_intr_info;
6aa8b732 4809
a0861c02 4810 if (is_machine_check(intr_info))
851ba692 4811 return handle_machine_check(vcpu);
a0861c02 4812
e4a41889 4813 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4814 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4815
4816 if (is_no_device(intr_info)) {
5fd86fcf 4817 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4818 return 1;
4819 }
4820
7aa81cc0 4821 if (is_invalid_opcode(intr_info)) {
51d8b661 4822 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4823 if (er != EMULATE_DONE)
7ee5d940 4824 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4825 return 1;
4826 }
4827
6aa8b732 4828 error_code = 0;
2e11384c 4829 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4830 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4831
4832 /*
4833 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4834 * MMIO, it is better to report an internal error.
4835 * See the comments in vmx_handle_exit.
4836 */
4837 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4838 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4839 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4840 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4841 vcpu->run->internal.ndata = 2;
4842 vcpu->run->internal.data[0] = vect_info;
4843 vcpu->run->internal.data[1] = intr_info;
4844 return 0;
4845 }
4846
6aa8b732 4847 if (is_page_fault(intr_info)) {
1439442c 4848 /* EPT won't cause page fault directly */
cf3ace79 4849 BUG_ON(enable_ept);
6aa8b732 4850 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4851 trace_kvm_page_fault(cr2, error_code);
4852
3298b75c 4853 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4854 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4855 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4856 }
4857
d0bfb940 4858 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4859
4860 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4861 return handle_rmode_exception(vcpu, ex_no, error_code);
4862
42dbaa5a
JK		 4863 switch (ex_no) {
4864 case DB_VECTOR:
4865 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4866 if (!(vcpu->guest_debug &
4867 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4868 vcpu->arch.dr6 &= ~15;
6f43ed01 4869 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4870 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4871 skip_emulated_instruction(vcpu);
4872
42dbaa5a
JK		 4873 kvm_queue_exception(vcpu, DB_VECTOR);
4874 return 1;
4875 }
4876 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4877 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4878 /* fall through */
4879 case BP_VECTOR:
c573cd22
JK		 4880 /*
4881 * Update instruction length as we may reinject #BP from
4882 * user space while in guest debugging mode. Reading it for
4883 * #DB as well causes no harm, it is not used in that case.
4884 */
4885 vmx->vcpu.arch.event_exit_inst_len =
4886 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4887 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4888 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4889 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4890 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4891 break;
4892 default:
d0bfb940
JK		 4893 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4894 kvm_run->ex.exception = ex_no;
4895 kvm_run->ex.error_code = error_code;
42dbaa5a 4896 break;
6aa8b732 4897 }
6aa8b732
AK		 4898 return 0;
4899}
4900
851ba692 4901static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4902{
1165f5fe 4903 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4904 return 1;
4905}
4906
851ba692 4907static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4908{
851ba692 4909 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4910 return 0;
4911}
6aa8b732 4912
851ba692 4913static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4914{
bfdaab09 4915 unsigned long exit_qualification;
34c33d16 4916 int size, in, string;
039576c0 4917 unsigned port;
6aa8b732 4918
bfdaab09 4919 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4920 string = (exit_qualification & 16) != 0;
cf8f70bf 4921 in = (exit_qualification & 8) != 0;
e70669ab 4922
cf8f70bf 4923 ++vcpu->stat.io_exits;
e70669ab 4924
cf8f70bf 4925 if (string || in)
51d8b661 4926 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4927
cf8f70bf
GN		 4928 port = exit_qualification >> 16;
4929 size = (exit_qualification & 7) + 1;
e93f36bc 4930 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4931
4932 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4933}
4934
102d8325
IM		 4935static void
4936vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4937{
4938 /*
4939 * Patch in the VMCALL instruction:
4940 */
4941 hypercall[0] = 0x0f;
4942 hypercall[1] = 0x01;
4943 hypercall[2] = 0xc1;
102d8325
IM		 4944}
4945
92fbc7b1
JK		 4946static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4947{
4948 unsigned long always_on = VMXON_CR0_ALWAYSON;
4949
4950 if (nested_vmx_secondary_ctls_high &
4951 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4952 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4953 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4954 return (val & always_on) == always_on;
4955}
4956
0fa06071 4957/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4958static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4959{
eeadf9e7 4960 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4961 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4962 unsigned long orig_val = val;
4963
eeadf9e7
NHE		 4964 /*
4965 * We get here when L2 changed cr0 in a way that did not change
4966 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4967 * but did change L0 shadowed bits. So we first calculate the
4968 * effective cr0 value that L1 would like to write into the
4969 * hardware. It consists of the L2-owned bits from the new
4970 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4971 */
1a0d74e6
JK		 4972 val = (val & ~vmcs12->cr0_guest_host_mask) |
4973 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4974
92fbc7b1 4975 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4976 return 1;
1a0d74e6
JK		 4977
4978 if (kvm_set_cr0(vcpu, val))
4979 return 1;
4980 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4981 return 0;
1a0d74e6
JK		 4982 } else {
4983 if (to_vmx(vcpu)->nested.vmxon &&
4984 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4985 return 1;
eeadf9e7 4986 return kvm_set_cr0(vcpu, val);
1a0d74e6 4987 }
eeadf9e7
NHE		 4988}
4989
4990static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4991{
4992 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4993 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4994 unsigned long orig_val = val;
4995
4996 /* analogously to handle_set_cr0 */
4997 val = (val & ~vmcs12->cr4_guest_host_mask) |
4998 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4999 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5000 return 1;
1a0d74e6 5001 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5002 return 0;
5003 } else
5004 return kvm_set_cr4(vcpu, val);
5005}
5006
5007/* called to set cr0 as approriate for clts instruction exit. */
5008static void handle_clts(struct kvm_vcpu *vcpu)
5009{
5010 if (is_guest_mode(vcpu)) {
5011 /*
5012 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5013 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5014 * just pretend it's off (also in arch.cr0 for fpu_activate).
5015 */
5016 vmcs_writel(CR0_READ_SHADOW,
5017 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5018 vcpu->arch.cr0 &= ~X86_CR0_TS;
5019 } else
5020 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5021}
5022
851ba692 5023static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5024{
229456fc 5025 unsigned long exit_qualification, val;
6aa8b732
AK		 5026 int cr;
5027 int reg;
49a9b07e 5028 int err;
6aa8b732 5029
bfdaab09 5030 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5031 cr = exit_qualification & 15;
5032 reg = (exit_qualification >> 8) & 15;
5033 switch ((exit_qualification >> 4) & 3) {
5034 case 0: /* mov to cr */
1e32c079 5035 val = kvm_register_readl(vcpu, reg);
229456fc 5036 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5037 switch (cr) {
5038 case 0:
eeadf9e7 5039 err = handle_set_cr0(vcpu, val);
db8fcefa 5040 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5041 return 1;
5042 case 3:
2390218b 5043 err = kvm_set_cr3(vcpu, val);
db8fcefa 5044 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5045 return 1;
5046 case 4:
eeadf9e7 5047 err = handle_set_cr4(vcpu, val);
db8fcefa 5048 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5049 return 1;
0a5fff19
GN		 5050 case 8: {
5051 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5052 u8 cr8 = (u8)val;
eea1cff9 5053 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5054 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5055 if (irqchip_in_kernel(vcpu->kvm))
5056 return 1;
5057 if (cr8_prev <= cr8)
5058 return 1;
851ba692 5059 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5060 return 0;
5061 }
4b8073e4 5062 }
6aa8b732 5063 break;
25c4c276 5064 case 2: /* clts */
eeadf9e7 5065 handle_clts(vcpu);
4d4ec087 5066 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5067 skip_emulated_instruction(vcpu);
6b52d186 5068 vmx_fpu_activate(vcpu);
25c4c276 5069 return 1;
6aa8b732
AK		 5070 case 1: /*mov from cr*/
5071 switch (cr) {
5072 case 3:
9f8fe504
AK		 5073 val = kvm_read_cr3(vcpu);
5074 kvm_register_write(vcpu, reg, val);
5075 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5076 skip_emulated_instruction(vcpu);
5077 return 1;
5078 case 8:
229456fc
MT		 5079 val = kvm_get_cr8(vcpu);
5080 kvm_register_write(vcpu, reg, val);
5081 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5082 skip_emulated_instruction(vcpu);
5083 return 1;
5084 }
5085 break;
5086 case 3: /* lmsw */
a1f83a74 5087 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5088 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5089 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5090
5091 skip_emulated_instruction(vcpu);
5092 return 1;
5093 default:
5094 break;
5095 }
851ba692 5096 vcpu->run->exit_reason = 0;
a737f256 5097 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5098 (int)(exit_qualification >> 4) & 3, cr);
5099 return 0;
5100}
5101
851ba692 5102static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5103{
bfdaab09 5104 unsigned long exit_qualification;
16f8a6f9
NA		 5105 int dr, dr7, reg;
5106
5107 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5108 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5109
5110 /* First, if DR does not exist, trigger UD */
5111 if (!kvm_require_dr(vcpu, dr))
5112 return 1;
6aa8b732 5113
f2483415 5114 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5115 if (!kvm_require_cpl(vcpu, 0))
5116 return 1;
16f8a6f9
NA		 5117 dr7 = vmcs_readl(GUEST_DR7);
5118 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5119 /*
5120 * As the vm-exit takes precedence over the debug trap, we
5121 * need to emulate the latter, either for the host or the
5122 * guest debugging itself.
5123 */
5124 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5125 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5126 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5127 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5128 vcpu->run->debug.arch.exception = DB_VECTOR;
5129 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5130 return 0;
5131 } else {
7305eb5d 5132 vcpu->arch.dr6 &= ~15;
6f43ed01 5133 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5134 kvm_queue_exception(vcpu, DB_VECTOR);
5135 return 1;
5136 }
5137 }
5138
81908bf4
PB		 5139 if (vcpu->guest_debug == 0) {
5140 u32 cpu_based_vm_exec_control;
5141
5142 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5143 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5144 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5145
5146 /*
5147 * No more DR vmexits; force a reload of the debug registers
5148 * and reenter on this instruction. The next vmexit will
5149 * retrieve the full state of the debug registers.
5150 */
5151 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5152 return 1;
5153 }
5154
42dbaa5a
JK		 5155 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5156 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5157 unsigned long val;
4c4d563b
JK		 5158
5159 if (kvm_get_dr(vcpu, dr, &val))
5160 return 1;
5161 kvm_register_write(vcpu, reg, val);
020df079 5162 } else
5777392e 5163 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5164 return 1;
5165
6aa8b732
AK		 5166 skip_emulated_instruction(vcpu);
5167 return 1;
5168}
5169
73aaf249
JK		 5170static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5171{
5172 return vcpu->arch.dr6;
5173}
5174
5175static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5176{
5177}
5178
81908bf4
PB		 5179static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5180{
5181 u32 cpu_based_vm_exec_control;
5182
5183 get_debugreg(vcpu->arch.db[0], 0);
5184 get_debugreg(vcpu->arch.db[1], 1);
5185 get_debugreg(vcpu->arch.db[2], 2);
5186 get_debugreg(vcpu->arch.db[3], 3);
5187 get_debugreg(vcpu->arch.dr6, 6);
5188 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5189
5190 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5191
5192 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5193 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5194 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5195}
5196
020df079
GN		 5197static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5198{
5199 vmcs_writel(GUEST_DR7, val);
5200}
5201
851ba692 5202static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5203{
06465c5a
AK		 5204 kvm_emulate_cpuid(vcpu);
5205 return 1;
6aa8b732
AK		 5206}
5207
851ba692 5208static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5209{
ad312c7c 5210 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5211 u64 data;
5212
5213 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5214 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5215 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5216 return 1;
5217 }
5218
229456fc 5219 trace_kvm_msr_read(ecx, data);
2714d1d3 5220
6aa8b732 5221 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5222 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5223 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5224 skip_emulated_instruction(vcpu);
5225 return 1;
5226}
5227
851ba692 5228static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5229{
8fe8ab46 5230 struct msr_data msr;
ad312c7c
ZX		 5231 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5232 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5233 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5234
8fe8ab46
WA		 5235 msr.data = data;
5236 msr.index = ecx;
5237 msr.host_initiated = false;
854e8bb1 5238 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5239 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5240 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5241 return 1;
5242 }
5243
59200273 5244 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5245 skip_emulated_instruction(vcpu);
5246 return 1;
5247}
5248
851ba692 5249static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5250{
3842d135 5251 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5252 return 1;
5253}
5254
851ba692 5255static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5256{
85f455f7
ED		 5257 u32 cpu_based_vm_exec_control;
5258
5259 /* clear pending irq */
5260 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5261 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5262 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5263
3842d135
AK		 5264 kvm_make_request(KVM_REQ_EVENT, vcpu);
5265
a26bf12a 5266 ++vcpu->stat.irq_window_exits;
2714d1d3 5267
c1150d8c
DL		 5268 /*
5269 * If the user space waits to inject interrupts, exit as soon as
5270 * possible
5271 */
8061823a 5272 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5273 vcpu->run->request_interrupt_window &&
8061823a 5274 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5275 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5276 return 0;
5277 }
6aa8b732
AK		 5278 return 1;
5279}
5280
851ba692 5281static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5282{
5283 skip_emulated_instruction(vcpu);
d3bef15f 5284 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5285}
5286
851ba692 5287static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5288{
510043da 5289 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5290 kvm_emulate_hypercall(vcpu);
5291 return 1;
c21415e8
IM		 5292}
5293
ec25d5e6
GN		 5294static int handle_invd(struct kvm_vcpu *vcpu)
5295{
51d8b661 5296 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5297}
5298
851ba692 5299static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5300{
f9c617f6 5301 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5302
5303 kvm_mmu_invlpg(vcpu, exit_qualification);
5304 skip_emulated_instruction(vcpu);
5305 return 1;
5306}
5307
fee84b07
AK		 5308static int handle_rdpmc(struct kvm_vcpu *vcpu)
5309{
5310 int err;
5311
5312 err = kvm_rdpmc(vcpu);
5313 kvm_complete_insn_gp(vcpu, err);
5314
5315 return 1;
5316}
5317
851ba692 5318static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5319{
5320 skip_emulated_instruction(vcpu);
f5f48ee1 5321 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5322 return 1;
5323}
5324
2acf923e
DC		 5325static int handle_xsetbv(struct kvm_vcpu *vcpu)
5326{
5327 u64 new_bv = kvm_read_edx_eax(vcpu);
5328 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5329
5330 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5331 skip_emulated_instruction(vcpu);
5332 return 1;
5333}
5334
851ba692 5335static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5336{
58fbbf26
KT		 5337 if (likely(fasteoi)) {
5338 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5339 int access_type, offset;
5340
5341 access_type = exit_qualification & APIC_ACCESS_TYPE;
5342 offset = exit_qualification & APIC_ACCESS_OFFSET;
5343 /*
5344 * Sane guest uses MOV to write EOI, with written value
5345 * not cared. So make a short-circuit here by avoiding
5346 * heavy instruction emulation.
5347 */
5348 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5349 (offset == APIC_EOI)) {
5350 kvm_lapic_set_eoi(vcpu);
5351 skip_emulated_instruction(vcpu);
5352 return 1;
5353 }
5354 }
51d8b661 5355 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5356}
5357
c7c9c56c
YZ		 5358static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5359{
5360 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5361 int vector = exit_qualification & 0xff;
5362
5363 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5364 kvm_apic_set_eoi_accelerated(vcpu, vector);
5365 return 1;
5366}
5367
83d4c286
YZ		 5368static int handle_apic_write(struct kvm_vcpu *vcpu)
5369{
5370 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5371 u32 offset = exit_qualification & 0xfff;
5372
5373 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5374 kvm_apic_write_nodecode(vcpu, offset);
5375 return 1;
5376}
5377
851ba692 5378static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5379{
60637aac 5380 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5381 unsigned long exit_qualification;
e269fb21
JK		 5382 bool has_error_code = false;
5383 u32 error_code = 0;
37817f29 5384 u16 tss_selector;
7f3d35fd 5385 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5386
5387 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5388 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5389 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5390
5391 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5392
5393 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5394 if (reason == TASK_SWITCH_GATE && idt_v) {
5395 switch (type) {
5396 case INTR_TYPE_NMI_INTR:
5397 vcpu->arch.nmi_injected = false;
654f06fc 5398 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5399 break;
5400 case INTR_TYPE_EXT_INTR:
66fd3f7f 5401 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5402 kvm_clear_interrupt_queue(vcpu);
5403 break;
5404 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5405 if (vmx->idt_vectoring_info &
5406 VECTORING_INFO_DELIVER_CODE_MASK) {
5407 has_error_code = true;
5408 error_code =
5409 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5410 }
5411 /* fall through */
64a7ec06
GN		 5412 case INTR_TYPE_SOFT_EXCEPTION:
5413 kvm_clear_exception_queue(vcpu);
5414 break;
5415 default:
5416 break;
5417 }
60637aac 5418 }
37817f29
IE		 5419 tss_selector = exit_qualification;
5420
64a7ec06
GN		 5421 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5422 type != INTR_TYPE_EXT_INTR &&
5423 type != INTR_TYPE_NMI_INTR))
5424 skip_emulated_instruction(vcpu);
5425
7f3d35fd
KW		 5426 if (kvm_task_switch(vcpu, tss_selector,
5427 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5428 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5429 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5430 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5431 vcpu->run->internal.ndata = 0;
42dbaa5a 5432 return 0;
acb54517 5433 }
42dbaa5a
JK		 5434
5435 /* clear all local breakpoint enable flags */
0e8a0996 5436 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5437
5438 /*
5439 * TODO: What about debug traps on tss switch?
5440 * Are we supposed to inject them and update dr6?
5441 */
5442
5443 return 1;
37817f29
IE		 5444}
5445
851ba692 5446static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5447{
f9c617f6 5448 unsigned long exit_qualification;
1439442c 5449 gpa_t gpa;
4f5982a5 5450 u32 error_code;
1439442c 5451 int gla_validity;
1439442c 5452
f9c617f6 5453 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5454
1439442c
SY		 5455 gla_validity = (exit_qualification >> 7) & 0x3;
5456 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5457 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5458 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5459 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5460 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5461 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5462 (long unsigned int)exit_qualification);
851ba692
AK		 5463 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5464 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5465 return 0;
1439442c
SY		 5466 }
5467
0be9c7a8
GN		 5468 /*
5469 * EPT violation happened while executing iret from NMI,
5470 * "blocked by NMI" bit has to be set before next VM entry.
5471 * There are errata that may cause this bit to not be set:
5472 * AAK134, BY25.
5473 */
bcd1c294
GN		 5474 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5475 cpu_has_virtual_nmis() &&
5476 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5477 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5478
1439442c 5479 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5480 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5481
5482 /* It is a write fault? */
5483 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5484 /* It is a fetch fault? */
5485 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5486 /* ept page table is present? */
5487 error_code |= (exit_qualification >> 3) & 0x1;
5488
25d92081
YZ		 5489 vcpu->arch.exit_qualification = exit_qualification;
5490
4f5982a5 5491 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5492}
5493
68f89400
MT		 5494static u64 ept_rsvd_mask(u64 spte, int level)
5495{
5496 int i;
5497 u64 mask = 0;
5498
5499 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5500 mask |= (1ULL << i);
5501
a32e8459 5502 if (level == 4)
68f89400
MT		 5503 /* bits 7:3 reserved */
5504 mask |= 0xf8;
a32e8459
WL		 5505 else if (spte & (1ULL << 7))
5506 /*
5507 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5508 * level == 1 if the hypervisor is using the ignored bit 7.
5509 */
5510 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5511 else if (level > 1)
5512 /* bits 6:3 reserved */
5513 mask |= 0x78;
68f89400
MT		 5514
5515 return mask;
5516}
5517
5518static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5519 int level)
5520{
5521 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5522
5523 /* 010b (write-only) */
5524 WARN_ON((spte & 0x7) == 0x2);
5525
5526 /* 110b (write/execute) */
5527 WARN_ON((spte & 0x7) == 0x6);
5528
5529 /* 100b (execute-only) and value not supported by logical processor */
5530 if (!cpu_has_vmx_ept_execute_only())
5531 WARN_ON((spte & 0x7) == 0x4);
5532
5533 /* not 000b */
5534 if ((spte & 0x7)) {
5535 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5536
5537 if (rsvd_bits != 0) {
5538 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5539 __func__, rsvd_bits);
5540 WARN_ON(1);
5541 }
5542
a32e8459
WL		 5543 /* bits 5:3 are _not_ reserved for large page or leaf page */
5544 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5545 u64 ept_mem_type = (spte & 0x38) >> 3;
5546
5547 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5548 ept_mem_type == 7) {
5549 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5550 __func__, ept_mem_type);
5551 WARN_ON(1);
5552 }
5553 }
5554 }
5555}
5556
851ba692 5557static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5558{
5559 u64 sptes[4];
ce88decf 5560 int nr_sptes, i, ret;
68f89400
MT		 5561 gpa_t gpa;
5562
5563 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5564 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5565 skip_emulated_instruction(vcpu);
5566 return 1;
5567 }
68f89400 5568
ce88decf 5569 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5570 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5571 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5572 EMULATE_DONE;
f8f55942
XG		 5573
5574 if (unlikely(ret == RET_MMIO_PF_INVALID))
5575 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5576
b37fbea6 5577 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5578 return 1;
5579
5580 /* It is the real ept misconfig */
68f89400
MT		 5581 printk(KERN_ERR "EPT: Misconfiguration.\n");
5582 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5583
5584 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5585
5586 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5587 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5588
851ba692
AK		 5589 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5590 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5591
5592 return 0;
5593}
5594
851ba692 5595static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5596{
5597 u32 cpu_based_vm_exec_control;
5598
5599 /* clear pending NMI */
5600 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5601 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5602 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5603 ++vcpu->stat.nmi_window_exits;
3842d135 5604 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5605
5606 return 1;
5607}
5608
80ced186 5609static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5610{
8b3079a5
AK		 5611 struct vcpu_vmx *vmx = to_vmx(vcpu);
5612 enum emulation_result err = EMULATE_DONE;
80ced186 5613 int ret = 1;
49e9d557
AK		 5614 u32 cpu_exec_ctrl;
5615 bool intr_window_requested;
b8405c18 5616 unsigned count = 130;
49e9d557
AK		 5617
5618 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5619 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5620
98eb2f8b 5621 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5622 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5623 return handle_interrupt_window(&vmx->vcpu);
5624
de87dcdd
AK		 5625 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5626 return 1;
5627
991eebf9 5628 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5629
ac0a48c3 5630 if (err == EMULATE_USER_EXIT) {
94452b9e 5631 ++vcpu->stat.mmio_exits;
80ced186
MG		 5632 ret = 0;
5633 goto out;
5634 }
1d5a4d9b 5635
de5f70e0
AK		 5636 if (err != EMULATE_DONE) {
5637 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5638 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5639 vcpu->run->internal.ndata = 0;
6d77dbfc 5640 return 0;
de5f70e0 5641 }
ea953ef0 5642
8d76c49e
GN		 5643 if (vcpu->arch.halt_request) {
5644 vcpu->arch.halt_request = 0;
5645 ret = kvm_emulate_halt(vcpu);
5646 goto out;
5647 }
5648
ea953ef0 5649 if (signal_pending(current))
80ced186 5650 goto out;
ea953ef0
MG		 5651 if (need_resched())
5652 schedule();
5653 }
5654
80ced186
MG		 5655out:
5656 return ret;
ea953ef0
MG		 5657}
5658
b4a2d31d
RK		 5659static int __grow_ple_window(int val)
5660{
5661 if (ple_window_grow < 1)
5662 return ple_window;
5663
5664 val = min(val, ple_window_actual_max);
5665
5666 if (ple_window_grow < ple_window)
5667 val *= ple_window_grow;
5668 else
5669 val += ple_window_grow;
5670
5671 return val;
5672}
5673
5674static int __shrink_ple_window(int val, int modifier, int minimum)
5675{
5676 if (modifier < 1)
5677 return ple_window;
5678
5679 if (modifier < ple_window)
5680 val /= modifier;
5681 else
5682 val -= modifier;
5683
5684 return max(val, minimum);
5685}
5686
5687static void grow_ple_window(struct kvm_vcpu *vcpu)
5688{
5689 struct vcpu_vmx *vmx = to_vmx(vcpu);
5690 int old = vmx->ple_window;
5691
5692 vmx->ple_window = __grow_ple_window(old);
5693
5694 if (vmx->ple_window != old)
5695 vmx->ple_window_dirty = true;
7b46268d
RK		 5696
5697 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5698}
5699
5700static void shrink_ple_window(struct kvm_vcpu *vcpu)
5701{
5702 struct vcpu_vmx *vmx = to_vmx(vcpu);
5703 int old = vmx->ple_window;
5704
5705 vmx->ple_window = __shrink_ple_window(old,
5706 ple_window_shrink, ple_window);
5707
5708 if (vmx->ple_window != old)
5709 vmx->ple_window_dirty = true;
7b46268d
RK		 5710
5711 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5712}
5713
5714/*
5715 * ple_window_actual_max is computed to be one grow_ple_window() below
5716 * ple_window_max. (See __grow_ple_window for the reason.)
5717 * This prevents overflows, because ple_window_max is int.
5718 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5719 * this process.
5720 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5721 */
5722static void update_ple_window_actual_max(void)
5723{
5724 ple_window_actual_max =
5725 __shrink_ple_window(max(ple_window_max, ple_window),
5726 ple_window_grow, INT_MIN);
5727}
5728
f2c7648d
TC		 5729static __init int hardware_setup(void)
5730{
34a1cd60
TC		 5731 int r = -ENOMEM, i, msr;
5732
5733 rdmsrl_safe(MSR_EFER, &host_efer);
5734
5735 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5736 kvm_define_shared_msr(i, vmx_msr_index[i]);
5737
5738 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5739 if (!vmx_io_bitmap_a)
5740 return r;
5741
5742 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5743 if (!vmx_io_bitmap_b)
5744 goto out;
5745
5746 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5747 if (!vmx_msr_bitmap_legacy)
5748 goto out1;
5749
5750 vmx_msr_bitmap_legacy_x2apic =
5751 (unsigned long *)__get_free_page(GFP_KERNEL);
5752 if (!vmx_msr_bitmap_legacy_x2apic)
5753 goto out2;
5754
5755 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5756 if (!vmx_msr_bitmap_longmode)
5757 goto out3;
5758
5759 vmx_msr_bitmap_longmode_x2apic =
5760 (unsigned long *)__get_free_page(GFP_KERNEL);
5761 if (!vmx_msr_bitmap_longmode_x2apic)
5762 goto out4;
5763 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5764 if (!vmx_vmread_bitmap)
5765 goto out5;
5766
5767 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5768 if (!vmx_vmwrite_bitmap)
5769 goto out6;
5770
5771 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5772 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5773
5774 /*
5775 * Allow direct access to the PC debug port (it is often used for I/O
5776 * delays, but the vmexits simply slow things down).
5777 */
5778 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5779 clear_bit(0x80, vmx_io_bitmap_a);
5780
5781 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5782
5783 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5784 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5785
5786 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5787 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5788 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5789 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5790 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5791 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5792 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5793
5794 memcpy(vmx_msr_bitmap_legacy_x2apic,
5795 vmx_msr_bitmap_legacy, PAGE_SIZE);
5796 memcpy(vmx_msr_bitmap_longmode_x2apic,
5797 vmx_msr_bitmap_longmode, PAGE_SIZE);
5798
5799 if (enable_apicv) {
5800 for (msr = 0x800; msr <= 0x8ff; msr++)
5801 vmx_disable_intercept_msr_read_x2apic(msr);
5802
5803 /* According SDM, in x2apic mode, the whole id reg is used.
5804 * But in KVM, it only use the highest eight bits. Need to
5805 * intercept it */
5806 vmx_enable_intercept_msr_read_x2apic(0x802);
5807 /* TMCCT */
5808 vmx_enable_intercept_msr_read_x2apic(0x839);
5809 /* TPR */
5810 vmx_disable_intercept_msr_write_x2apic(0x808);
5811 /* EOI */
5812 vmx_disable_intercept_msr_write_x2apic(0x80b);
5813 /* SELF-IPI */
5814 vmx_disable_intercept_msr_write_x2apic(0x83f);
5815 }
5816
5817 if (enable_ept) {
5818 kvm_mmu_set_mask_ptes(0ull,
5819 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5820 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5821 0ull, VMX_EPT_EXECUTABLE_MASK);
5822 ept_set_mmio_spte_mask();
5823 kvm_enable_tdp();
5824 } else
5825 kvm_disable_tdp();
5826
5827 update_ple_window_actual_max();
5828
5829 if (setup_vmcs_config(&vmcs_config) < 0) {
5830 r = -EIO;
5831 goto out7;
5832 }
f2c7648d
TC		 5833
5834 if (boot_cpu_has(X86_FEATURE_NX))
5835 kvm_enable_efer_bits(EFER_NX);
5836
5837 if (!cpu_has_vmx_vpid())
5838 enable_vpid = 0;
5839 if (!cpu_has_vmx_shadow_vmcs())
5840 enable_shadow_vmcs = 0;
5841 if (enable_shadow_vmcs)
5842 init_vmcs_shadow_fields();
5843
5844 if (!cpu_has_vmx_ept() ||
5845 !cpu_has_vmx_ept_4levels()) {
5846 enable_ept = 0;
5847 enable_unrestricted_guest = 0;
5848 enable_ept_ad_bits = 0;
5849 }
5850
5851 if (!cpu_has_vmx_ept_ad_bits())
5852 enable_ept_ad_bits = 0;
5853
5854 if (!cpu_has_vmx_unrestricted_guest())
5855 enable_unrestricted_guest = 0;
5856
5857 if (!cpu_has_vmx_flexpriority()) {
5858 flexpriority_enabled = 0;
5859
5860 /*
5861 * set_apic_access_page_addr() is used to reload apic access
5862 * page upon invalidation. No need to do anything if the
5863 * processor does not have the APIC_ACCESS_ADDR VMCS field.
5864 */
5865 kvm_x86_ops->set_apic_access_page_addr = NULL;
5866 }
5867
5868 if (!cpu_has_vmx_tpr_shadow())
5869 kvm_x86_ops->update_cr8_intercept = NULL;
5870
5871 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5872 kvm_disable_largepages();
5873
5874 if (!cpu_has_vmx_ple())
5875 ple_gap = 0;
5876
5877 if (!cpu_has_vmx_apicv())
5878 enable_apicv = 0;
5879
5880 if (enable_apicv)
5881 kvm_x86_ops->update_cr8_intercept = NULL;
5882 else {
5883 kvm_x86_ops->hwapic_irr_update = NULL;
5884 kvm_x86_ops->deliver_posted_interrupt = NULL;
5885 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5886 }
5887
5888 if (nested)
5889 nested_vmx_setup_ctls_msrs();
5890
5891 return alloc_kvm_area();
34a1cd60
TC		 5892
5893out7:
5894 free_page((unsigned long)vmx_vmwrite_bitmap);
5895out6:
5896 free_page((unsigned long)vmx_vmread_bitmap);
5897out5:
5898 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5899out4:
5900 free_page((unsigned long)vmx_msr_bitmap_longmode);
5901out3:
5902 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5903out2:
5904 free_page((unsigned long)vmx_msr_bitmap_legacy);
5905out1:
5906 free_page((unsigned long)vmx_io_bitmap_b);
5907out:
5908 free_page((unsigned long)vmx_io_bitmap_a);
5909
5910 return r;
f2c7648d
TC		 5911}
5912
5913static __exit void hardware_unsetup(void)
5914{
34a1cd60
TC		 5915 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5916 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5917 free_page((unsigned long)vmx_msr_bitmap_legacy);
5918 free_page((unsigned long)vmx_msr_bitmap_longmode);
5919 free_page((unsigned long)vmx_io_bitmap_b);
5920 free_page((unsigned long)vmx_io_bitmap_a);
5921 free_page((unsigned long)vmx_vmwrite_bitmap);
5922 free_page((unsigned long)vmx_vmread_bitmap);
5923
f2c7648d
TC		 5924 free_kvm_area();
5925}
5926
4b8d54f9
ZE		 5927/*
5928 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5929 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5930 */
9fb41ba8 5931static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5932{
b4a2d31d
RK		 5933 if (ple_gap)
5934 grow_ple_window(vcpu);
5935
4b8d54f9
ZE		 5936 skip_emulated_instruction(vcpu);
5937 kvm_vcpu_on_spin(vcpu);
5938
5939 return 1;
5940}
5941
87c00572 5942static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5943{
87c00572 5944 skip_emulated_instruction(vcpu);
59708670
SY		 5945 return 1;
5946}
5947
87c00572
GS		 5948static int handle_mwait(struct kvm_vcpu *vcpu)
5949{
5950 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5951 return handle_nop(vcpu);
5952}
5953
5954static int handle_monitor(struct kvm_vcpu *vcpu)
5955{
5956 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5957 return handle_nop(vcpu);
5958}
5959
ff2f6fe9
NHE		 5960/*
5961 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5962 * We could reuse a single VMCS for all the L2 guests, but we also want the
5963 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5964 * allows keeping them loaded on the processor, and in the future will allow
5965 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5966 * every entry if they never change.
5967 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5968 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5969 *
5970 * The following functions allocate and free a vmcs02 in this pool.
5971 */
5972
5973/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5974static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5975{
5976 struct vmcs02_list *item;
5977 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5978 if (item->vmptr == vmx->nested.current_vmptr) {
5979 list_move(&item->list, &vmx->nested.vmcs02_pool);
5980 return &item->vmcs02;
5981 }
5982
5983 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5984 /* Recycle the least recently used VMCS. */
5985 item = list_entry(vmx->nested.vmcs02_pool.prev,
5986 struct vmcs02_list, list);
5987 item->vmptr = vmx->nested.current_vmptr;
5988 list_move(&item->list, &vmx->nested.vmcs02_pool);
5989 return &item->vmcs02;
5990 }
5991
5992 /* Create a new VMCS */
0fa24ce3 5993 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5994 if (!item)
5995 return NULL;
5996 item->vmcs02.vmcs = alloc_vmcs();
5997 if (!item->vmcs02.vmcs) {
5998 kfree(item);
5999 return NULL;
6000 }
6001 loaded_vmcs_init(&item->vmcs02);
6002 item->vmptr = vmx->nested.current_vmptr;
6003 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6004 vmx->nested.vmcs02_num++;
6005 return &item->vmcs02;
6006}
6007
6008/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6009static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6010{
6011 struct vmcs02_list *item;
6012 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6013 if (item->vmptr == vmptr) {
6014 free_loaded_vmcs(&item->vmcs02);
6015 list_del(&item->list);
6016 kfree(item);
6017 vmx->nested.vmcs02_num--;
6018 return;
6019 }
6020}
6021
6022/*
6023 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6024 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6025 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6026 */
6027static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6028{
6029 struct vmcs02_list *item, *n;
4fa7734c
PB		 6030
6031 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6032 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6033 /*
6034 * Something will leak if the above WARN triggers. Better than
6035 * a use-after-free.
6036 */
6037 if (vmx->loaded_vmcs == &item->vmcs02)
6038 continue;
6039
6040 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6041 list_del(&item->list);
6042 kfree(item);
4fa7734c 6043 vmx->nested.vmcs02_num--;
ff2f6fe9 6044 }
ff2f6fe9
NHE		 6045}
6046
0658fbaa
ACL		 6047/*
6048 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6049 * set the success or error code of an emulated VMX instruction, as specified
6050 * by Vol 2B, VMX Instruction Reference, "Conventions".
6051 */
6052static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6053{
6054 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6055 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6056 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6057}
6058
6059static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6060{
6061 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6062 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6063 X86_EFLAGS_SF | X86_EFLAGS_OF))
6064 | X86_EFLAGS_CF);
6065}
6066
145c28dd 6067static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6068 u32 vm_instruction_error)
6069{
6070 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6071 /*
6072 * failValid writes the error number to the current VMCS, which
6073 * can't be done there isn't a current VMCS.
6074 */
6075 nested_vmx_failInvalid(vcpu);
6076 return;
6077 }
6078 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6079 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6080 X86_EFLAGS_SF | X86_EFLAGS_OF))
6081 | X86_EFLAGS_ZF);
6082 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6083 /*
6084 * We don't need to force a shadow sync because
6085 * VM_INSTRUCTION_ERROR is not shadowed
6086 */
6087}
145c28dd 6088
f4124500
JK		 6089static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6090{
6091 struct vcpu_vmx *vmx =
6092 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6093
6094 vmx->nested.preemption_timer_expired = true;
6095 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6096 kvm_vcpu_kick(&vmx->vcpu);
6097
6098 return HRTIMER_NORESTART;
6099}
6100
19677e32
BD		 6101/*
6102 * Decode the memory-address operand of a vmx instruction, as recorded on an
6103 * exit caused by such an instruction (run by a guest hypervisor).
6104 * On success, returns 0. When the operand is invalid, returns 1 and throws
6105 * #UD or #GP.
6106 */
6107static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6108 unsigned long exit_qualification,
6109 u32 vmx_instruction_info, gva_t *ret)
6110{
6111 /*
6112 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6113 * Execution", on an exit, vmx_instruction_info holds most of the
6114 * addressing components of the operand. Only the displacement part
6115 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6116 * For how an actual address is calculated from all these components,
6117 * refer to Vol. 1, "Operand Addressing".
6118 */
6119 int scaling = vmx_instruction_info & 3;
6120 int addr_size = (vmx_instruction_info >> 7) & 7;
6121 bool is_reg = vmx_instruction_info & (1u << 10);
6122 int seg_reg = (vmx_instruction_info >> 15) & 7;
6123 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6124 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6125 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6126 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6127
6128 if (is_reg) {
6129 kvm_queue_exception(vcpu, UD_VECTOR);
6130 return 1;
6131 }
6132
6133 /* Addr = segment_base + offset */
6134 /* offset = base + [index * scale] + displacement */
6135 *ret = vmx_get_segment_base(vcpu, seg_reg);
6136 if (base_is_valid)
6137 *ret += kvm_register_read(vcpu, base_reg);
6138 if (index_is_valid)
6139 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6140 *ret += exit_qualification; /* holds the displacement */
6141
6142 if (addr_size == 1) /* 32 bit */
6143 *ret &= 0xffffffff;
6144
6145 /*
6146 * TODO: throw #GP (and return 1) in various cases that the VM*
6147 * instructions require it - e.g., offset beyond segment limit,
6148 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6149 * address, and so on. Currently these are not checked.
6150 */
6151 return 0;
6152}
6153
3573e22c
BD		 6154/*
6155 * This function performs the various checks including
6156 * - if it's 4KB aligned
6157 * - No bits beyond the physical address width are set
6158 * - Returns 0 on success or else 1
4291b588 6159 * (Intel SDM Section 30.3)
3573e22c 6160 */
4291b588
BD		 6161static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6162 gpa_t *vmpointer)
3573e22c
BD		 6163{
6164 gva_t gva;
6165 gpa_t vmptr;
6166 struct x86_exception e;
6167 struct page *page;
6168 struct vcpu_vmx *vmx = to_vmx(vcpu);
6169 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6170
6171 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6172 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6173 return 1;
6174
6175 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6176 sizeof(vmptr), &e)) {
6177 kvm_inject_page_fault(vcpu, &e);
6178 return 1;
6179 }
6180
6181 switch (exit_reason) {
6182 case EXIT_REASON_VMON:
6183 /*
6184 * SDM 3: 24.11.5
6185 * The first 4 bytes of VMXON region contain the supported
6186 * VMCS revision identifier
6187 *
6188 * Note - IA32_VMX_BASIC[48] will never be 1
6189 * for the nested case;
6190 * which replaces physical address width with 32
6191 *
6192 */
bc39c4db 6193 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6194 nested_vmx_failInvalid(vcpu);
6195 skip_emulated_instruction(vcpu);
6196 return 1;
6197 }
6198
6199 page = nested_get_page(vcpu, vmptr);
6200 if (page == NULL ||
6201 *(u32 *)kmap(page) != VMCS12_REVISION) {
6202 nested_vmx_failInvalid(vcpu);
6203 kunmap(page);
6204 skip_emulated_instruction(vcpu);
6205 return 1;
6206 }
6207 kunmap(page);
6208 vmx->nested.vmxon_ptr = vmptr;
6209 break;
4291b588 6210 case EXIT_REASON_VMCLEAR:
bc39c4db 6211 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6212 nested_vmx_failValid(vcpu,
6213 VMXERR_VMCLEAR_INVALID_ADDRESS);
6214 skip_emulated_instruction(vcpu);
6215 return 1;
6216 }
6217
6218 if (vmptr == vmx->nested.vmxon_ptr) {
6219 nested_vmx_failValid(vcpu,
6220 VMXERR_VMCLEAR_VMXON_POINTER);
6221 skip_emulated_instruction(vcpu);
6222 return 1;
6223 }
6224 break;
6225 case EXIT_REASON_VMPTRLD:
bc39c4db 6226 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6227 nested_vmx_failValid(vcpu,
6228 VMXERR_VMPTRLD_INVALID_ADDRESS);
6229 skip_emulated_instruction(vcpu);
6230 return 1;
6231 }
3573e22c 6232
4291b588
BD		 6233 if (vmptr == vmx->nested.vmxon_ptr) {
6234 nested_vmx_failValid(vcpu,
6235 VMXERR_VMCLEAR_VMXON_POINTER);
6236 skip_emulated_instruction(vcpu);
6237 return 1;
6238 }
6239 break;
3573e22c
BD		 6240 default:
6241 return 1; /* shouldn't happen */
6242 }
6243
4291b588
BD		 6244 if (vmpointer)
6245 *vmpointer = vmptr;
3573e22c
BD		 6246 return 0;
6247}
6248
ec378aee
NHE		 6249/*
6250 * Emulate the VMXON instruction.
6251 * Currently, we just remember that VMX is active, and do not save or even
6252 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6253 * do not currently need to store anything in that guest-allocated memory
6254 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6255 * argument is different from the VMXON pointer (which the spec says they do).
6256 */
6257static int handle_vmon(struct kvm_vcpu *vcpu)
6258{
6259 struct kvm_segment cs;
6260 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6261 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6262 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6263 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6264
6265 /* The Intel VMX Instruction Reference lists a bunch of bits that
6266 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6267 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6268 * Otherwise, we should fail with #UD. We test these now:
6269 */
6270 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6271 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6272 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6273 kvm_queue_exception(vcpu, UD_VECTOR);
6274 return 1;
6275 }
6276
6277 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6278 if (is_long_mode(vcpu) && !cs.l) {
6279 kvm_queue_exception(vcpu, UD_VECTOR);
6280 return 1;
6281 }
6282
6283 if (vmx_get_cpl(vcpu)) {
6284 kvm_inject_gp(vcpu, 0);
6285 return 1;
6286 }
3573e22c 6287
4291b588 6288 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6289 return 1;
6290
145c28dd
AG		 6291 if (vmx->nested.vmxon) {
6292 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6293 skip_emulated_instruction(vcpu);
6294 return 1;
6295 }
b3897a49
NHE		 6296
6297 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6298 != VMXON_NEEDED_FEATURES) {
6299 kvm_inject_gp(vcpu, 0);
6300 return 1;
6301 }
6302
8de48833
AG		 6303 if (enable_shadow_vmcs) {
6304 shadow_vmcs = alloc_vmcs();
6305 if (!shadow_vmcs)
6306 return -ENOMEM;
6307 /* mark vmcs as shadow */
6308 shadow_vmcs->revision_id |= (1u << 31);
6309 /* init shadow vmcs */
6310 vmcs_clear(shadow_vmcs);
6311 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6312 }
ec378aee 6313
ff2f6fe9
NHE		 6314 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6315 vmx->nested.vmcs02_num = 0;
6316
f4124500
JK		 6317 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6318 HRTIMER_MODE_REL);
6319 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6320
ec378aee
NHE		 6321 vmx->nested.vmxon = true;
6322
6323 skip_emulated_instruction(vcpu);
a25eb114 6324 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6325 return 1;
6326}
6327
6328/*
6329 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6330 * for running VMX instructions (except VMXON, whose prerequisites are
6331 * slightly different). It also specifies what exception to inject otherwise.
6332 */
6333static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6334{
6335 struct kvm_segment cs;
6336 struct vcpu_vmx *vmx = to_vmx(vcpu);
6337
6338 if (!vmx->nested.vmxon) {
6339 kvm_queue_exception(vcpu, UD_VECTOR);
6340 return 0;
6341 }
6342
6343 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6344 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6345 (is_long_mode(vcpu) && !cs.l)) {
6346 kvm_queue_exception(vcpu, UD_VECTOR);
6347 return 0;
6348 }
6349
6350 if (vmx_get_cpl(vcpu)) {
6351 kvm_inject_gp(vcpu, 0);
6352 return 0;
6353 }
6354
6355 return 1;
6356}
6357
e7953d7f
AG		 6358static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6359{
8a1b9dd0 6360 u32 exec_control;
9a2a05b9
PB		 6361 if (vmx->nested.current_vmptr == -1ull)
6362 return;
6363
6364 /* current_vmptr and current_vmcs12 are always set/reset together */
6365 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6366 return;
6367
012f83cb 6368 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6369 /* copy to memory all shadowed fields in case
6370 they were modified */
6371 copy_shadow_to_vmcs12(vmx);
6372 vmx->nested.sync_shadow_vmcs = false;
6373 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6374 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6375 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6376 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6377 }
e7953d7f
AG		 6378 kunmap(vmx->nested.current_vmcs12_page);
6379 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6380 vmx->nested.current_vmptr = -1ull;
6381 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6382}
6383
ec378aee
NHE		 6384/*
6385 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6386 * just stops using VMX.
6387 */
6388static void free_nested(struct vcpu_vmx *vmx)
6389{
6390 if (!vmx->nested.vmxon)
6391 return;
9a2a05b9 6392
ec378aee 6393 vmx->nested.vmxon = false;
9a2a05b9 6394 nested_release_vmcs12(vmx);
e7953d7f
AG		 6395 if (enable_shadow_vmcs)
6396 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6397 /* Unpin physical memory we referred to in current vmcs02 */
6398 if (vmx->nested.apic_access_page) {
6399 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6400 vmx->nested.apic_access_page = NULL;
fe3ef05c 6401 }
a7c0b07d
WL		 6402 if (vmx->nested.virtual_apic_page) {
6403 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6404 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6405 }
ff2f6fe9
NHE		 6406
6407 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6408}
6409
6410/* Emulate the VMXOFF instruction */
6411static int handle_vmoff(struct kvm_vcpu *vcpu)
6412{
6413 if (!nested_vmx_check_permission(vcpu))
6414 return 1;
6415 free_nested(to_vmx(vcpu));
6416 skip_emulated_instruction(vcpu);
a25eb114 6417 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6418 return 1;
6419}
6420
27d6c865
NHE		 6421/* Emulate the VMCLEAR instruction */
6422static int handle_vmclear(struct kvm_vcpu *vcpu)
6423{
6424 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6425 gpa_t vmptr;
6426 struct vmcs12 *vmcs12;
6427 struct page *page;
27d6c865
NHE		 6428
6429 if (!nested_vmx_check_permission(vcpu))
6430 return 1;
6431
4291b588 6432 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6433 return 1;
27d6c865 6434
9a2a05b9 6435 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6436 nested_release_vmcs12(vmx);
27d6c865
NHE		 6437
6438 page = nested_get_page(vcpu, vmptr);
6439 if (page == NULL) {
6440 /*
6441 * For accurate processor emulation, VMCLEAR beyond available
6442 * physical memory should do nothing at all. However, it is
6443 * possible that a nested vmx bug, not a guest hypervisor bug,
6444 * resulted in this case, so let's shut down before doing any
6445 * more damage:
6446 */
6447 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6448 return 1;
6449 }
6450 vmcs12 = kmap(page);
6451 vmcs12->launch_state = 0;
6452 kunmap(page);
6453 nested_release_page(page);
6454
6455 nested_free_vmcs02(vmx, vmptr);
6456
6457 skip_emulated_instruction(vcpu);
6458 nested_vmx_succeed(vcpu);
6459 return 1;
6460}
6461
cd232ad0
NHE		 6462static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6463
6464/* Emulate the VMLAUNCH instruction */
6465static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6466{
6467 return nested_vmx_run(vcpu, true);
6468}
6469
6470/* Emulate the VMRESUME instruction */
6471static int handle_vmresume(struct kvm_vcpu *vcpu)
6472{
6473
6474 return nested_vmx_run(vcpu, false);
6475}
6476
49f705c5
NHE		 6477enum vmcs_field_type {
6478 VMCS_FIELD_TYPE_U16 = 0,
6479 VMCS_FIELD_TYPE_U64 = 1,
6480 VMCS_FIELD_TYPE_U32 = 2,
6481 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6482};
6483
6484static inline int vmcs_field_type(unsigned long field)
6485{
6486 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6487 return VMCS_FIELD_TYPE_U32;
6488 return (field >> 13) & 0x3 ;
6489}
6490
6491static inline int vmcs_field_readonly(unsigned long field)
6492{
6493 return (((field >> 10) & 0x3) == 1);
6494}
6495
6496/*
6497 * Read a vmcs12 field. Since these can have varying lengths and we return
6498 * one type, we chose the biggest type (u64) and zero-extend the return value
6499 * to that size. Note that the caller, handle_vmread, might need to use only
6500 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6501 * 64-bit fields are to be returned).
6502 */
a2ae9df7
PB		 6503static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6504 unsigned long field, u64 *ret)
49f705c5
NHE		 6505{
6506 short offset = vmcs_field_to_offset(field);
6507 char *p;
6508
6509 if (offset < 0)
a2ae9df7 6510 return offset;
49f705c5
NHE		 6511
6512 p = ((char *)(get_vmcs12(vcpu))) + offset;
6513
6514 switch (vmcs_field_type(field)) {
6515 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6516 *ret = *((natural_width *)p);
a2ae9df7 6517 return 0;
49f705c5
NHE		 6518 case VMCS_FIELD_TYPE_U16:
6519 *ret = *((u16 *)p);
a2ae9df7 6520 return 0;
49f705c5
NHE		 6521 case VMCS_FIELD_TYPE_U32:
6522 *ret = *((u32 *)p);
a2ae9df7 6523 return 0;
49f705c5
NHE		 6524 case VMCS_FIELD_TYPE_U64:
6525 *ret = *((u64 *)p);
a2ae9df7 6526 return 0;
49f705c5 6527 default:
a2ae9df7
PB		 6528 WARN_ON(1);
6529 return -ENOENT;
49f705c5
NHE		 6530 }
6531}
6532
20b97fea 6533
a2ae9df7
PB		 6534static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6535 unsigned long field, u64 field_value){
20b97fea
AG		 6536 short offset = vmcs_field_to_offset(field);
6537 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6538 if (offset < 0)
a2ae9df7 6539 return offset;
20b97fea
AG		 6540
6541 switch (vmcs_field_type(field)) {
6542 case VMCS_FIELD_TYPE_U16:
6543 *(u16 *)p = field_value;
a2ae9df7 6544 return 0;
20b97fea
AG		 6545 case VMCS_FIELD_TYPE_U32:
6546 *(u32 *)p = field_value;
a2ae9df7 6547 return 0;
20b97fea
AG		 6548 case VMCS_FIELD_TYPE_U64:
6549 *(u64 *)p = field_value;
a2ae9df7 6550 return 0;
20b97fea
AG		 6551 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6552 *(natural_width *)p = field_value;
a2ae9df7 6553 return 0;
20b97fea 6554 default:
a2ae9df7
PB		 6555 WARN_ON(1);
6556 return -ENOENT;
20b97fea
AG		 6557 }
6558
6559}
6560
16f5b903
AG		 6561static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6562{
6563 int i;
6564 unsigned long field;
6565 u64 field_value;
6566 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6567 const unsigned long *fields = shadow_read_write_fields;
6568 const int num_fields = max_shadow_read_write_fields;
16f5b903 6569
282da870
JK		 6570 preempt_disable();
6571
16f5b903
AG		 6572 vmcs_load(shadow_vmcs);
6573
6574 for (i = 0; i < num_fields; i++) {
6575 field = fields[i];
6576 switch (vmcs_field_type(field)) {
6577 case VMCS_FIELD_TYPE_U16:
6578 field_value = vmcs_read16(field);
6579 break;
6580 case VMCS_FIELD_TYPE_U32:
6581 field_value = vmcs_read32(field);
6582 break;
6583 case VMCS_FIELD_TYPE_U64:
6584 field_value = vmcs_read64(field);
6585 break;
6586 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6587 field_value = vmcs_readl(field);
6588 break;
a2ae9df7
PB		 6589 default:
6590 WARN_ON(1);
6591 continue;
16f5b903
AG		 6592 }
6593 vmcs12_write_any(&vmx->vcpu, field, field_value);
6594 }
6595
6596 vmcs_clear(shadow_vmcs);
6597 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6598
6599 preempt_enable();
16f5b903
AG		 6600}
6601
c3114420
AG		 6602static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6603{
c2bae893
MK		 6604 const unsigned long *fields[] = {
6605 shadow_read_write_fields,
6606 shadow_read_only_fields
c3114420 6607 };
c2bae893 6608 const int max_fields[] = {
c3114420
AG		 6609 max_shadow_read_write_fields,
6610 max_shadow_read_only_fields
6611 };
6612 int i, q;
6613 unsigned long field;
6614 u64 field_value = 0;
6615 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6616
6617 vmcs_load(shadow_vmcs);
6618
c2bae893 6619 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6620 for (i = 0; i < max_fields[q]; i++) {
6621 field = fields[q][i];
6622 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6623
6624 switch (vmcs_field_type(field)) {
6625 case VMCS_FIELD_TYPE_U16:
6626 vmcs_write16(field, (u16)field_value);
6627 break;
6628 case VMCS_FIELD_TYPE_U32:
6629 vmcs_write32(field, (u32)field_value);
6630 break;
6631 case VMCS_FIELD_TYPE_U64:
6632 vmcs_write64(field, (u64)field_value);
6633 break;
6634 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6635 vmcs_writel(field, (long)field_value);
6636 break;
a2ae9df7
PB		 6637 default:
6638 WARN_ON(1);
6639 break;
c3114420
AG		 6640 }
6641 }
6642 }
6643
6644 vmcs_clear(shadow_vmcs);
6645 vmcs_load(vmx->loaded_vmcs->vmcs);
6646}
6647
49f705c5
NHE		 6648/*
6649 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6650 * used before) all generate the same failure when it is missing.
6651 */
6652static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6653{
6654 struct vcpu_vmx *vmx = to_vmx(vcpu);
6655 if (vmx->nested.current_vmptr == -1ull) {
6656 nested_vmx_failInvalid(vcpu);
6657 skip_emulated_instruction(vcpu);
6658 return 0;
6659 }
6660 return 1;
6661}
6662
6663static int handle_vmread(struct kvm_vcpu *vcpu)
6664{
6665 unsigned long field;
6666 u64 field_value;
6667 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6668 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6669 gva_t gva = 0;
6670
6671 if (!nested_vmx_check_permission(vcpu) ||
6672 !nested_vmx_check_vmcs12(vcpu))
6673 return 1;
6674
6675 /* Decode instruction info and find the field to read */
27e6fb5d 6676 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6677 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6678 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6679 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6680 skip_emulated_instruction(vcpu);
6681 return 1;
6682 }
6683 /*
6684 * Now copy part of this value to register or memory, as requested.
6685 * Note that the number of bits actually copied is 32 or 64 depending
6686 * on the guest's mode (32 or 64 bit), not on the given field's length.
6687 */
6688 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6689 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6690 field_value);
6691 } else {
6692 if (get_vmx_mem_address(vcpu, exit_qualification,
6693 vmx_instruction_info, &gva))
6694 return 1;
6695 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6696 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6697 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6698 }
6699
6700 nested_vmx_succeed(vcpu);
6701 skip_emulated_instruction(vcpu);
6702 return 1;
6703}
6704
6705
6706static int handle_vmwrite(struct kvm_vcpu *vcpu)
6707{
6708 unsigned long field;
6709 gva_t gva;
6710 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6711 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6712 /* The value to write might be 32 or 64 bits, depending on L1's long
6713 * mode, and eventually we need to write that into a field of several
6714 * possible lengths. The code below first zero-extends the value to 64
6715 * bit (field_value), and then copies only the approriate number of
6716 * bits into the vmcs12 field.
6717 */
6718 u64 field_value = 0;
6719 struct x86_exception e;
6720
6721 if (!nested_vmx_check_permission(vcpu) ||
6722 !nested_vmx_check_vmcs12(vcpu))
6723 return 1;
6724
6725 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6726 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6727 (((vmx_instruction_info) >> 3) & 0xf));
6728 else {
6729 if (get_vmx_mem_address(vcpu, exit_qualification,
6730 vmx_instruction_info, &gva))
6731 return 1;
6732 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6733 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6734 kvm_inject_page_fault(vcpu, &e);
6735 return 1;
6736 }
6737 }
6738
6739
27e6fb5d 6740 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6741 if (vmcs_field_readonly(field)) {
6742 nested_vmx_failValid(vcpu,
6743 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6744 skip_emulated_instruction(vcpu);
6745 return 1;
6746 }
6747
a2ae9df7 6748 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6749 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6750 skip_emulated_instruction(vcpu);
6751 return 1;
6752 }
6753
6754 nested_vmx_succeed(vcpu);
6755 skip_emulated_instruction(vcpu);
6756 return 1;
6757}
6758
63846663
NHE		 6759/* Emulate the VMPTRLD instruction */
6760static int handle_vmptrld(struct kvm_vcpu *vcpu)
6761{
6762 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6763 gpa_t vmptr;
8a1b9dd0 6764 u32 exec_control;
63846663
NHE		 6765
6766 if (!nested_vmx_check_permission(vcpu))
6767 return 1;
6768
4291b588 6769 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6770 return 1;
63846663
NHE		 6771
6772 if (vmx->nested.current_vmptr != vmptr) {
6773 struct vmcs12 *new_vmcs12;
6774 struct page *page;
6775 page = nested_get_page(vcpu, vmptr);
6776 if (page == NULL) {
6777 nested_vmx_failInvalid(vcpu);
6778 skip_emulated_instruction(vcpu);
6779 return 1;
6780 }
6781 new_vmcs12 = kmap(page);
6782 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6783 kunmap(page);
6784 nested_release_page_clean(page);
6785 nested_vmx_failValid(vcpu,
6786 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6787 skip_emulated_instruction(vcpu);
6788 return 1;
6789 }
63846663 6790
9a2a05b9 6791 nested_release_vmcs12(vmx);
63846663
NHE		 6792 vmx->nested.current_vmptr = vmptr;
6793 vmx->nested.current_vmcs12 = new_vmcs12;
6794 vmx->nested.current_vmcs12_page = page;
012f83cb 6795 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6796 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6797 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6798 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6799 vmcs_write64(VMCS_LINK_POINTER,
6800 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6801 vmx->nested.sync_shadow_vmcs = true;
6802 }
63846663
NHE		 6803 }
6804
6805 nested_vmx_succeed(vcpu);
6806 skip_emulated_instruction(vcpu);
6807 return 1;
6808}
6809
6a4d7550
NHE		 6810/* Emulate the VMPTRST instruction */
6811static int handle_vmptrst(struct kvm_vcpu *vcpu)
6812{
6813 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6814 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6815 gva_t vmcs_gva;
6816 struct x86_exception e;
6817
6818 if (!nested_vmx_check_permission(vcpu))
6819 return 1;
6820
6821 if (get_vmx_mem_address(vcpu, exit_qualification,
6822 vmx_instruction_info, &vmcs_gva))
6823 return 1;
6824 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6825 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6826 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6827 sizeof(u64), &e)) {
6828 kvm_inject_page_fault(vcpu, &e);
6829 return 1;
6830 }
6831 nested_vmx_succeed(vcpu);
6832 skip_emulated_instruction(vcpu);
6833 return 1;
6834}
6835
bfd0a56b
NHE		 6836/* Emulate the INVEPT instruction */
6837static int handle_invept(struct kvm_vcpu *vcpu)
6838{
6839 u32 vmx_instruction_info, types;
6840 unsigned long type;
6841 gva_t gva;
6842 struct x86_exception e;
6843 struct {
6844 u64 eptp, gpa;
6845 } operand;
bfd0a56b
NHE		 6846
6847 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6848 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6849 kvm_queue_exception(vcpu, UD_VECTOR);
6850 return 1;
6851 }
6852
6853 if (!nested_vmx_check_permission(vcpu))
6854 return 1;
6855
6856 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6857 kvm_queue_exception(vcpu, UD_VECTOR);
6858 return 1;
6859 }
6860
6861 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6862 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6863
6864 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6865
6866 if (!(types & (1UL << type))) {
6867 nested_vmx_failValid(vcpu,
6868 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6869 return 1;
6870 }
6871
6872 /* According to the Intel VMX instruction reference, the memory
6873 * operand is read even if it isn't needed (e.g., for type==global)
6874 */
6875 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6876 vmx_instruction_info, &gva))
6877 return 1;
6878 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6879 sizeof(operand), &e)) {
6880 kvm_inject_page_fault(vcpu, &e);
6881 return 1;
6882 }
6883
6884 switch (type) {
bfd0a56b
NHE		 6885 case VMX_EPT_EXTENT_GLOBAL:
6886 kvm_mmu_sync_roots(vcpu);
77c3913b 6887 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6888 nested_vmx_succeed(vcpu);
6889 break;
6890 default:
4b855078 6891 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6892 BUG_ON(1);
6893 break;
6894 }
6895
6896 skip_emulated_instruction(vcpu);
6897 return 1;
6898}
6899
a642fc30
PM		 6900static int handle_invvpid(struct kvm_vcpu *vcpu)
6901{
6902 kvm_queue_exception(vcpu, UD_VECTOR);
6903 return 1;
6904}
6905
6aa8b732
AK		 6906/*
6907 * The exit handlers return 1 if the exit was handled fully and guest execution
6908 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6909 * to be done to userspace and return 0.
6910 */
772e0318 6911static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6912 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6913 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6914 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6915 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6916 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6917 [EXIT_REASON_CR_ACCESS] = handle_cr,
6918 [EXIT_REASON_DR_ACCESS] = handle_dr,
6919 [EXIT_REASON_CPUID] = handle_cpuid,
6920 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6921 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6922 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6923 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6924 [EXIT_REASON_INVD] = handle_invd,
a7052897 6925 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6926 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6927 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6928 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6929 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6930 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6931 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6932 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6933 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6934 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6935 [EXIT_REASON_VMOFF] = handle_vmoff,
6936 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6937 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6938 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6939 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6940 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6941 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6942 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6943 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6944 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6945 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6946 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6947 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6948 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6949 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6950 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 6951 [EXIT_REASON_INVVPID] = handle_invvpid,
6aa8b732
AK		 6952};
6953
6954static const int kvm_vmx_max_exit_handlers =
50a3485c 6955 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6956
908a7bdd
JK		 6957static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6958 struct vmcs12 *vmcs12)
6959{
6960 unsigned long exit_qualification;
6961 gpa_t bitmap, last_bitmap;
6962 unsigned int port;
6963 int size;
6964 u8 b;
6965
908a7bdd 6966 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6967 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6968
6969 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6970
6971 port = exit_qualification >> 16;
6972 size = (exit_qualification & 7) + 1;
6973
6974 last_bitmap = (gpa_t)-1;
6975 b = -1;
6976
6977 while (size > 0) {
6978 if (port < 0x8000)
6979 bitmap = vmcs12->io_bitmap_a;
6980 else if (port < 0x10000)
6981 bitmap = vmcs12->io_bitmap_b;
6982 else
6983 return 1;
6984 bitmap += (port & 0x7fff) / 8;
6985
6986 if (last_bitmap != bitmap)
6987 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6988 return 1;
6989 if (b & (1 << (port & 7)))
6990 return 1;
6991
6992 port++;
6993 size--;
6994 last_bitmap = bitmap;
6995 }
6996
6997 return 0;
6998}
6999
644d711a
NHE		 7000/*
7001 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7002 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7003 * disinterest in the current event (read or write a specific MSR) by using an
7004 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7005 */
7006static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7007 struct vmcs12 *vmcs12, u32 exit_reason)
7008{
7009 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7010 gpa_t bitmap;
7011
cbd29cb6 7012 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7013 return 1;
7014
7015 /*
7016 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7017 * for the four combinations of read/write and low/high MSR numbers.
7018 * First we need to figure out which of the four to use:
7019 */
7020 bitmap = vmcs12->msr_bitmap;
7021 if (exit_reason == EXIT_REASON_MSR_WRITE)
7022 bitmap += 2048;
7023 if (msr_index >= 0xc0000000) {
7024 msr_index -= 0xc0000000;
7025 bitmap += 1024;
7026 }
7027
7028 /* Then read the msr_index'th bit from this bitmap: */
7029 if (msr_index < 1024*8) {
7030 unsigned char b;
bd31a7f5
JK		 7031 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7032 return 1;
644d711a
NHE		 7033 return 1 & (b >> (msr_index & 7));
7034 } else
7035 return 1; /* let L1 handle the wrong parameter */
7036}
7037
7038/*
7039 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7040 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7041 * intercept (via guest_host_mask etc.) the current event.
7042 */
7043static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7044 struct vmcs12 *vmcs12)
7045{
7046 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7047 int cr = exit_qualification & 15;
7048 int reg = (exit_qualification >> 8) & 15;
1e32c079 7049 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7050
7051 switch ((exit_qualification >> 4) & 3) {
7052 case 0: /* mov to cr */
7053 switch (cr) {
7054 case 0:
7055 if (vmcs12->cr0_guest_host_mask &
7056 (val ^ vmcs12->cr0_read_shadow))
7057 return 1;
7058 break;
7059 case 3:
7060 if ((vmcs12->cr3_target_count >= 1 &&
7061 vmcs12->cr3_target_value0 == val) ||
7062 (vmcs12->cr3_target_count >= 2 &&
7063 vmcs12->cr3_target_value1 == val) ||
7064 (vmcs12->cr3_target_count >= 3 &&
7065 vmcs12->cr3_target_value2 == val) ||
7066 (vmcs12->cr3_target_count >= 4 &&
7067 vmcs12->cr3_target_value3 == val))
7068 return 0;
7069 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7070 return 1;
7071 break;
7072 case 4:
7073 if (vmcs12->cr4_guest_host_mask &
7074 (vmcs12->cr4_read_shadow ^ val))
7075 return 1;
7076 break;
7077 case 8:
7078 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7079 return 1;
7080 break;
7081 }
7082 break;
7083 case 2: /* clts */
7084 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7085 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7086 return 1;
7087 break;
7088 case 1: /* mov from cr */
7089 switch (cr) {
7090 case 3:
7091 if (vmcs12->cpu_based_vm_exec_control &
7092 CPU_BASED_CR3_STORE_EXITING)
7093 return 1;
7094 break;
7095 case 8:
7096 if (vmcs12->cpu_based_vm_exec_control &
7097 CPU_BASED_CR8_STORE_EXITING)
7098 return 1;
7099 break;
7100 }
7101 break;
7102 case 3: /* lmsw */
7103 /*
7104 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7105 * cr0. Other attempted changes are ignored, with no exit.
7106 */
7107 if (vmcs12->cr0_guest_host_mask & 0xe &
7108 (val ^ vmcs12->cr0_read_shadow))
7109 return 1;
7110 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7111 !(vmcs12->cr0_read_shadow & 0x1) &&
7112 (val & 0x1))
7113 return 1;
7114 break;
7115 }
7116 return 0;
7117}
7118
7119/*
7120 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7121 * should handle it ourselves in L0 (and then continue L2). Only call this
7122 * when in is_guest_mode (L2).
7123 */
7124static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7125{
644d711a
NHE		 7126 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7127 struct vcpu_vmx *vmx = to_vmx(vcpu);
7128 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7129 u32 exit_reason = vmx->exit_reason;
644d711a 7130
542060ea
JK		 7131 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7132 vmcs_readl(EXIT_QUALIFICATION),
7133 vmx->idt_vectoring_info,
7134 intr_info,
7135 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7136 KVM_ISA_VMX);
7137
644d711a
NHE		 7138 if (vmx->nested.nested_run_pending)
7139 return 0;
7140
7141 if (unlikely(vmx->fail)) {
bd80158a
JK		 7142 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7143 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7144 return 1;
7145 }
7146
7147 switch (exit_reason) {
7148 case EXIT_REASON_EXCEPTION_NMI:
7149 if (!is_exception(intr_info))
7150 return 0;
7151 else if (is_page_fault(intr_info))
7152 return enable_ept;
e504c909 7153 else if (is_no_device(intr_info) &&
ccf9844e 7154 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7155 return 0;
644d711a
NHE		 7156 return vmcs12->exception_bitmap &
7157 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7158 case EXIT_REASON_EXTERNAL_INTERRUPT:
7159 return 0;
7160 case EXIT_REASON_TRIPLE_FAULT:
7161 return 1;
7162 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7163 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7164 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7165 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7166 case EXIT_REASON_TASK_SWITCH:
7167 return 1;
7168 case EXIT_REASON_CPUID:
bc613494
MT		 7169 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7170 return 0;
644d711a
NHE		 7171 return 1;
7172 case EXIT_REASON_HLT:
7173 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7174 case EXIT_REASON_INVD:
7175 return 1;
7176 case EXIT_REASON_INVLPG:
7177 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7178 case EXIT_REASON_RDPMC:
7179 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7180 case EXIT_REASON_RDTSC:
7181 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7182 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7183 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7184 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7185 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7186 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7187 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7188 /*
7189 * VMX instructions trap unconditionally. This allows L1 to
7190 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7191 */
7192 return 1;
7193 case EXIT_REASON_CR_ACCESS:
7194 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7195 case EXIT_REASON_DR_ACCESS:
7196 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7197 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7198 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7199 case EXIT_REASON_MSR_READ:
7200 case EXIT_REASON_MSR_WRITE:
7201 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7202 case EXIT_REASON_INVALID_STATE:
7203 return 1;
7204 case EXIT_REASON_MWAIT_INSTRUCTION:
7205 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7206 case EXIT_REASON_MONITOR_INSTRUCTION:
7207 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7208 case EXIT_REASON_PAUSE_INSTRUCTION:
7209 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7210 nested_cpu_has2(vmcs12,
7211 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7212 case EXIT_REASON_MCE_DURING_VMENTRY:
7213 return 0;
7214 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7215 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7216 case EXIT_REASON_APIC_ACCESS:
7217 return nested_cpu_has2(vmcs12,
7218 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7219 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7220 /*
7221 * L0 always deals with the EPT violation. If nested EPT is
7222 * used, and the nested mmu code discovers that the address is
7223 * missing in the guest EPT table (EPT12), the EPT violation
7224 * will be injected with nested_ept_inject_page_fault()
7225 */
7226 return 0;
644d711a 7227 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7228 /*
7229 * L2 never uses directly L1's EPT, but rather L0's own EPT
7230 * table (shadow on EPT) or a merged EPT table that L0 built
7231 * (EPT on EPT). So any problems with the structure of the
7232 * table is L0's fault.
7233 */
644d711a
NHE		 7234 return 0;
7235 case EXIT_REASON_WBINVD:
7236 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7237 case EXIT_REASON_XSETBV:
7238 return 1;
7239 default:
7240 return 1;
7241 }
7242}
7243
586f9607
AK		 7244static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7245{
7246 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7247 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7248}
7249
6aa8b732
AK		 7250/*
7251 * The guest has exited. See if we can fix it or if we need userspace
7252 * assistance.
7253 */
851ba692 7254static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7255{
29bd8a78 7256 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7257 u32 exit_reason = vmx->exit_reason;
1155f76a 7258 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7259
80ced186 7260 /* If guest state is invalid, start emulating */
14168786 7261 if (vmx->emulation_required)
80ced186 7262 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7263
644d711a 7264 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7265 nested_vmx_vmexit(vcpu, exit_reason,
7266 vmcs_read32(VM_EXIT_INTR_INFO),
7267 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7268 return 1;
7269 }
7270
5120702e
MG		 7271 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7272 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7273 vcpu->run->fail_entry.hardware_entry_failure_reason
7274 = exit_reason;
7275 return 0;
7276 }
7277
29bd8a78 7278 if (unlikely(vmx->fail)) {
851ba692
AK		 7279 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7280 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7281 = vmcs_read32(VM_INSTRUCTION_ERROR);
7282 return 0;
7283 }
6aa8b732 7284
b9bf6882
XG		 7285 /*
7286 * Note:
7287 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7288 * delivery event since it indicates guest is accessing MMIO.
7289 * The vm-exit can be triggered again after return to guest that
7290 * will cause infinite loop.
7291 */
d77c26fc 7292 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7293 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7294 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7295 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7296 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7297 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7298 vcpu->run->internal.ndata = 2;
7299 vcpu->run->internal.data[0] = vectoring_info;
7300 vcpu->run->internal.data[1] = exit_reason;
7301 return 0;
7302 }
3b86cd99 7303
644d711a
NHE		 7304 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7305 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7306 get_vmcs12(vcpu))))) {
c4282df9 7307 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7308 vmx->soft_vnmi_blocked = 0;
3b86cd99 7309 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7310 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7311 /*
7312 * This CPU don't support us in finding the end of an
7313 * NMI-blocked window if the guest runs with IRQs
7314 * disabled. So we pull the trigger after 1 s of
7315 * futile waiting, but inform the user about this.
7316 */
7317 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7318 "state on VCPU %d after 1 s timeout\n",
7319 __func__, vcpu->vcpu_id);
7320 vmx->soft_vnmi_blocked = 0;
3b86cd99 7321 }
3b86cd99
JK		 7322 }
7323
6aa8b732
AK		 7324 if (exit_reason < kvm_vmx_max_exit_handlers
7325 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7326 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7327 else {
2bc19dc3
MT		 7328 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7329 kvm_queue_exception(vcpu, UD_VECTOR);
7330 return 1;
6aa8b732 7331 }
6aa8b732
AK		 7332}
7333
95ba8273 7334static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7335{
a7c0b07d
WL		 7336 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7337
7338 if (is_guest_mode(vcpu) &&
7339 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7340 return;
7341
95ba8273 7342 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7343 vmcs_write32(TPR_THRESHOLD, 0);
7344 return;
7345 }
7346
95ba8273 7347 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7348}
7349
8d14695f
YZ		 7350static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7351{
7352 u32 sec_exec_control;
7353
7354 /*
7355 * There is not point to enable virtualize x2apic without enable
7356 * apicv
7357 */
c7c9c56c
YZ		 7358 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7359 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7360 return;
7361
7362 if (!vm_need_tpr_shadow(vcpu->kvm))
7363 return;
7364
7365 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7366
7367 if (set) {
7368 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7369 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7370 } else {
7371 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7372 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7373 }
7374 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7375
7376 vmx_set_msr_bitmap(vcpu);
7377}
7378
38b99173
TC		 7379static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7380{
7381 struct vcpu_vmx *vmx = to_vmx(vcpu);
7382
7383 /*
7384 * Currently we do not handle the nested case where L2 has an
7385 * APIC access page of its own; that page is still pinned.
7386 * Hence, we skip the case where the VCPU is in guest mode _and_
7387 * L1 prepared an APIC access page for L2.
7388 *
7389 * For the case where L1 and L2 share the same APIC access page
7390 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7391 * in the vmcs12), this function will only update either the vmcs01
7392 * or the vmcs02. If the former, the vmcs02 will be updated by
7393 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7394 * the next L2->L1 exit.
7395 */
7396 if (!is_guest_mode(vcpu) ||
7397 !nested_cpu_has2(vmx->nested.current_vmcs12,
7398 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7399 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7400}
7401
c7c9c56c
YZ		 7402static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7403{
7404 u16 status;
7405 u8 old;
7406
7407 if (!vmx_vm_has_apicv(kvm))
7408 return;
7409
7410 if (isr == -1)
7411 isr = 0;
7412
7413 status = vmcs_read16(GUEST_INTR_STATUS);
7414 old = status >> 8;
7415 if (isr != old) {
7416 status &= 0xff;
7417 status |= isr << 8;
7418 vmcs_write16(GUEST_INTR_STATUS, status);
7419 }
7420}
7421
7422static void vmx_set_rvi(int vector)
7423{
7424 u16 status;
7425 u8 old;
7426
4114c27d
WW		 7427 if (vector == -1)
7428 vector = 0;
7429
c7c9c56c
YZ		 7430 status = vmcs_read16(GUEST_INTR_STATUS);
7431 old = (u8)status & 0xff;
7432 if ((u8)vector != old) {
7433 status &= ~0xff;
7434 status |= (u8)vector;
7435 vmcs_write16(GUEST_INTR_STATUS, status);
7436 }
7437}
7438
7439static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7440{
4114c27d
WW		 7441 if (!is_guest_mode(vcpu)) {
7442 vmx_set_rvi(max_irr);
7443 return;
7444 }
7445
c7c9c56c
YZ		 7446 if (max_irr == -1)
7447 return;
7448
963fee16 7449 /*
4114c27d
WW		 7450 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7451 * handles it.
963fee16 7452 */
4114c27d 7453 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7454 return;
7455
963fee16 7456 /*
4114c27d 7457 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7458 * is run without virtual interrupt delivery.
7459 */
7460 if (!kvm_event_needs_reinjection(vcpu) &&
7461 vmx_interrupt_allowed(vcpu)) {
7462 kvm_queue_interrupt(vcpu, max_irr, false);
7463 vmx_inject_irq(vcpu);
7464 }
c7c9c56c
YZ		 7465}
7466
7467static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7468{
3d81bc7e
YZ		 7469 if (!vmx_vm_has_apicv(vcpu->kvm))
7470 return;
7471
c7c9c56c
YZ		 7472 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7473 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7474 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7475 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7476}
7477
51aa01d1 7478static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7479{
00eba012
AK		 7480 u32 exit_intr_info;
7481
7482 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7483 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7484 return;
7485
c5ca8e57 7486 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7487 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7488
7489 /* Handle machine checks before interrupts are enabled */
00eba012 7490 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7491 kvm_machine_check();
7492
20f65983 7493 /* We need to handle NMIs before interrupts are enabled */
00eba012 7494 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7495 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7496 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7497 asm("int $2");
ff9d07a0
ZY		 7498 kvm_after_handle_nmi(&vmx->vcpu);
7499 }
51aa01d1 7500}
20f65983 7501
a547c6db
YZ		 7502static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7503{
7504 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7505
7506 /*
7507 * If external interrupt exists, IF bit is set in rflags/eflags on the
7508 * interrupt stack frame, and interrupt will be enabled on a return
7509 * from interrupt handler.
7510 */
7511 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7512 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7513 unsigned int vector;
7514 unsigned long entry;
7515 gate_desc *desc;
7516 struct vcpu_vmx *vmx = to_vmx(vcpu);
7517#ifdef CONFIG_X86_64
7518 unsigned long tmp;
7519#endif
7520
7521 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7522 desc = (gate_desc *)vmx->host_idt_base + vector;
7523 entry = gate_offset(*desc);
7524 asm volatile(
7525#ifdef CONFIG_X86_64
7526 "mov %%" _ASM_SP ", %[sp]\n\t"
7527 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7528 "push $%c[ss]\n\t"
7529 "push %[sp]\n\t"
7530#endif
7531 "pushf\n\t"
7532 "orl $0x200, (%%" _ASM_SP ")\n\t"
7533 __ASM_SIZE(push) " $%c[cs]\n\t"
7534 "call *%[entry]\n\t"
7535 :
7536#ifdef CONFIG_X86_64
7537 [sp]"=&r"(tmp)
7538#endif
7539 :
7540 [entry]"r"(entry),
7541 [ss]"i"(__KERNEL_DS),
7542 [cs]"i"(__KERNEL_CS)
7543 );
7544 } else
7545 local_irq_enable();
7546}
7547
da8999d3
LJ		 7548static bool vmx_mpx_supported(void)
7549{
7550 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7551 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7552}
7553
51aa01d1
AK		 7554static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7555{
c5ca8e57 7556 u32 exit_intr_info;
51aa01d1
AK		 7557 bool unblock_nmi;
7558 u8 vector;
7559 bool idtv_info_valid;
7560
7561 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7562
cf393f75 7563 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7564 if (vmx->nmi_known_unmasked)
7565 return;
c5ca8e57
AK		 7566 /*
7567 * Can't use vmx->exit_intr_info since we're not sure what
7568 * the exit reason is.
7569 */
7570 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7571 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7572 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7573 /*
7b4a25cb 7574 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7575 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7576 * a guest IRET fault.
7b4a25cb
GN		 7577 * SDM 3: 23.2.2 (September 2008)
7578 * Bit 12 is undefined in any of the following cases:
7579 * If the VM exit sets the valid bit in the IDT-vectoring
7580 * information field.
7581 * If the VM exit is due to a double fault.
cf393f75 7582 */
7b4a25cb
GN		 7583 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7584 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7585 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7586 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7587 else
7588 vmx->nmi_known_unmasked =
7589 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7590 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7591 } else if (unlikely(vmx->soft_vnmi_blocked))
7592 vmx->vnmi_blocked_time +=
7593 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7594}
7595
3ab66e8a 7596static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7597 u32 idt_vectoring_info,
7598 int instr_len_field,
7599 int error_code_field)
51aa01d1 7600{
51aa01d1
AK		 7601 u8 vector;
7602 int type;
7603 bool idtv_info_valid;
7604
7605 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7606
3ab66e8a
JK		 7607 vcpu->arch.nmi_injected = false;
7608 kvm_clear_exception_queue(vcpu);
7609 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7610
7611 if (!idtv_info_valid)
7612 return;
7613
3ab66e8a 7614 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7615
668f612f
AK		 7616 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7617 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7618
64a7ec06 7619 switch (type) {
37b96e98 7620 case INTR_TYPE_NMI_INTR:
3ab66e8a 7621 vcpu->arch.nmi_injected = true;
668f612f 7622 /*
7b4a25cb 7623 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7624 * Clear bit "block by NMI" before VM entry if a NMI
7625 * delivery faulted.
668f612f 7626 */
3ab66e8a 7627 vmx_set_nmi_mask(vcpu, false);
37b96e98 7628 break;
37b96e98 7629 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7630 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7631 /* fall through */
7632 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7633 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7634 u32 err = vmcs_read32(error_code_field);
851eb667 7635 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7636 } else
851eb667 7637 kvm_requeue_exception(vcpu, vector);
37b96e98 7638 break;
66fd3f7f 7639 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7640 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7641 /* fall through */
37b96e98 7642 case INTR_TYPE_EXT_INTR:
3ab66e8a 7643 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7644 break;
7645 default:
7646 break;
f7d9238f 7647 }
cf393f75
AK		 7648}
7649
83422e17
AK		 7650static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7651{
3ab66e8a 7652 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7653 VM_EXIT_INSTRUCTION_LEN,
7654 IDT_VECTORING_ERROR_CODE);
7655}
7656
b463a6f7
AK		 7657static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7658{
3ab66e8a 7659 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7660 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7661 VM_ENTRY_INSTRUCTION_LEN,
7662 VM_ENTRY_EXCEPTION_ERROR_CODE);
7663
7664 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7665}
7666
d7cd9796
GN		 7667static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7668{
7669 int i, nr_msrs;
7670 struct perf_guest_switch_msr *msrs;
7671
7672 msrs = perf_guest_get_msrs(&nr_msrs);
7673
7674 if (!msrs)
7675 return;
7676
7677 for (i = 0; i < nr_msrs; i++)
7678 if (msrs[i].host == msrs[i].guest)
7679 clear_atomic_switch_msr(vmx, msrs[i].msr);
7680 else
7681 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7682 msrs[i].host);
7683}
7684
a3b5ba49 7685static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7686{
a2fa3e9f 7687 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7688 unsigned long debugctlmsr, cr4;
104f226b
AK		 7689
7690 /* Record the guest's net vcpu time for enforced NMI injections. */
7691 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7692 vmx->entry_time = ktime_get();
7693
7694 /* Don't enter VMX if guest state is invalid, let the exit handler
7695 start emulation until we arrive back to a valid state */
14168786 7696 if (vmx->emulation_required)
104f226b
AK		 7697 return;
7698
a7653ecd
RK		 7699 if (vmx->ple_window_dirty) {
7700 vmx->ple_window_dirty = false;
7701 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7702 }
7703
012f83cb
AG		 7704 if (vmx->nested.sync_shadow_vmcs) {
7705 copy_vmcs12_to_shadow(vmx);
7706 vmx->nested.sync_shadow_vmcs = false;
7707 }
7708
104f226b
AK		 7709 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7710 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7711 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7712 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7713
d974baa3
AL		 7714 cr4 = read_cr4();
7715 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7716 vmcs_writel(HOST_CR4, cr4);
7717 vmx->host_state.vmcs_host_cr4 = cr4;
7718 }
7719
104f226b
AK		 7720 /* When single-stepping over STI and MOV SS, we must clear the
7721 * corresponding interruptibility bits in the guest state. Otherwise
7722 * vmentry fails as it then expects bit 14 (BS) in pending debug
7723 * exceptions being set, but that's not correct for the guest debugging
7724 * case. */
7725 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7726 vmx_set_interrupt_shadow(vcpu, 0);
7727
d7cd9796 7728 atomic_switch_perf_msrs(vmx);
2a7921b7 7729 debugctlmsr = get_debugctlmsr();
d7cd9796 7730
d462b819 7731 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7732 asm(
6aa8b732 7733 /* Store host registers */
b188c81f
AK		 7734 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7735 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7736 "push %%" _ASM_CX " \n\t"
7737 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7738 "je 1f \n\t"
b188c81f 7739 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7740 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7741 "1: \n\t"
d3edefc0 7742 /* Reload cr2 if changed */
b188c81f
AK		 7743 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7744 "mov %%cr2, %%" _ASM_DX " \n\t"
7745 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7746 "je 2f \n\t"
b188c81f 7747 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7748 "2: \n\t"
6aa8b732 7749 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7750 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7751 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7752 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7753 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7754 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7755 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7756 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7757 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7758#ifdef CONFIG_X86_64
e08aa78a
AK		 7759 "mov %c[r8](%0), %%r8 \n\t"
7760 "mov %c[r9](%0), %%r9 \n\t"
7761 "mov %c[r10](%0), %%r10 \n\t"
7762 "mov %c[r11](%0), %%r11 \n\t"
7763 "mov %c[r12](%0), %%r12 \n\t"
7764 "mov %c[r13](%0), %%r13 \n\t"
7765 "mov %c[r14](%0), %%r14 \n\t"
7766 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7767#endif
b188c81f 7768 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7769
6aa8b732 7770 /* Enter guest mode */
83287ea4 7771 "jne 1f \n\t"
4ecac3fd 7772 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7773 "jmp 2f \n\t"
7774 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7775 "2: "
6aa8b732 7776 /* Save guest registers, load host registers, keep flags */
b188c81f 7777 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7778 "pop %0 \n\t"
b188c81f
AK		 7779 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7780 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7781 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7782 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7783 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7784 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7785 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7786#ifdef CONFIG_X86_64
e08aa78a
AK		 7787 "mov %%r8, %c[r8](%0) \n\t"
7788 "mov %%r9, %c[r9](%0) \n\t"
7789 "mov %%r10, %c[r10](%0) \n\t"
7790 "mov %%r11, %c[r11](%0) \n\t"
7791 "mov %%r12, %c[r12](%0) \n\t"
7792 "mov %%r13, %c[r13](%0) \n\t"
7793 "mov %%r14, %c[r14](%0) \n\t"
7794 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7795#endif
b188c81f
AK		 7796 "mov %%cr2, %%" _ASM_AX " \n\t"
7797 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7798
b188c81f 7799 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7800 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7801 ".pushsection .rodata \n\t"
7802 ".global vmx_return \n\t"
7803 "vmx_return: " _ASM_PTR " 2b \n\t"
7804 ".popsection"
e08aa78a 7805 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7806 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7807 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7808 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7809 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7810 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7811 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7812 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7813 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7814 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7815 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7816#ifdef CONFIG_X86_64
ad312c7c
ZX		 7817 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7818 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7819 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7820 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7821 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7822 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7823 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7824 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7825#endif
40712fae
AK		 7826 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7827 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7828 : "cc", "memory"
7829#ifdef CONFIG_X86_64
b188c81f 7830 , "rax", "rbx", "rdi", "rsi"
c2036300 7831 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7832#else
7833 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7834#endif
7835 );
6aa8b732 7836
2a7921b7
GN		 7837 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7838 if (debugctlmsr)
7839 update_debugctlmsr(debugctlmsr);
7840
aa67f609
AK		 7841#ifndef CONFIG_X86_64
7842 /*
7843 * The sysexit path does not restore ds/es, so we must set them to
7844 * a reasonable value ourselves.
7845 *
7846 * We can't defer this to vmx_load_host_state() since that function
7847 * may be executed in interrupt context, which saves and restore segments
7848 * around it, nullifying its effect.
7849 */
7850 loadsegment(ds, __USER_DS);
7851 loadsegment(es, __USER_DS);
7852#endif
7853
6de4f3ad 7854 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7855 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7856 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7857 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7858 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7859 vcpu->arch.regs_dirty = 0;
7860
1155f76a
AK		 7861 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7862
d462b819 7863 vmx->loaded_vmcs->launched = 1;
1b6269db 7864
51aa01d1 7865 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7866 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7867
e0b890d3
GN		 7868 /*
7869 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7870 * we did not inject a still-pending event to L1 now because of
7871 * nested_run_pending, we need to re-enable this bit.
7872 */
7873 if (vmx->nested.nested_run_pending)
7874 kvm_make_request(KVM_REQ_EVENT, vcpu);
7875
7876 vmx->nested.nested_run_pending = 0;
7877
51aa01d1
AK		 7878 vmx_complete_atomic_exit(vmx);
7879 vmx_recover_nmi_blocking(vmx);
cf393f75 7880 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7881}
7882
4fa7734c
PB		 7883static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7884{
7885 struct vcpu_vmx *vmx = to_vmx(vcpu);
7886 int cpu;
7887
7888 if (vmx->loaded_vmcs == &vmx->vmcs01)
7889 return;
7890
7891 cpu = get_cpu();
7892 vmx->loaded_vmcs = &vmx->vmcs01;
7893 vmx_vcpu_put(vcpu);
7894 vmx_vcpu_load(vcpu, cpu);
7895 vcpu->cpu = cpu;
7896 put_cpu();
7897}
7898
6aa8b732
AK		 7899static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7900{
fb3f0f51
RR		 7901 struct vcpu_vmx *vmx = to_vmx(vcpu);
7902
cdbecfc3 7903 free_vpid(vmx);
4fa7734c
PB		 7904 leave_guest_mode(vcpu);
7905 vmx_load_vmcs01(vcpu);
26a865f4 7906 free_nested(vmx);
4fa7734c 7907 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7908 kfree(vmx->guest_msrs);
7909 kvm_vcpu_uninit(vcpu);
a4770347 7910 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7911}
7912
fb3f0f51 7913static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7914{
fb3f0f51 7915 int err;
c16f862d 7916 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7917 int cpu;
6aa8b732 7918
a2fa3e9f 7919 if (!vmx)
fb3f0f51
RR		 7920 return ERR_PTR(-ENOMEM);
7921
2384d2b3
SY		 7922 allocate_vpid(vmx);
7923
fb3f0f51
RR		 7924 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7925 if (err)
7926 goto free_vcpu;
965b58a5 7927
a2fa3e9f 7928 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7929 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7930 > PAGE_SIZE);
0123be42 7931
be6d05cf 7932 err = -ENOMEM;
fb3f0f51 7933 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7934 goto uninit_vcpu;
7935 }
965b58a5 7936
d462b819
NHE		 7937 vmx->loaded_vmcs = &vmx->vmcs01;
7938 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7939 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7940 goto free_msrs;
d462b819
NHE		 7941 if (!vmm_exclusive)
7942 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7943 loaded_vmcs_init(vmx->loaded_vmcs);
7944 if (!vmm_exclusive)
7945 kvm_cpu_vmxoff();
a2fa3e9f 7946
15ad7146
AK		 7947 cpu = get_cpu();
7948 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7949 vmx->vcpu.cpu = cpu;
8b9cf98c 7950 err = vmx_vcpu_setup(vmx);
fb3f0f51 7951 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7952 put_cpu();
fb3f0f51
RR		 7953 if (err)
7954 goto free_vmcs;
a63cb560 7955 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7956 err = alloc_apic_access_page(kvm);
7957 if (err)
5e4a0b3c 7958 goto free_vmcs;
a63cb560 7959 }
fb3f0f51 7960
b927a3ce
SY		 7961 if (enable_ept) {
7962 if (!kvm->arch.ept_identity_map_addr)
7963 kvm->arch.ept_identity_map_addr =
7964 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7965 err = init_rmode_identity_map(kvm);
7966 if (err)
93ea5388 7967 goto free_vmcs;
b927a3ce 7968 }
b7ebfb05 7969
a9d30f33
NHE		 7970 vmx->nested.current_vmptr = -1ull;
7971 vmx->nested.current_vmcs12 = NULL;
7972
fb3f0f51
RR		 7973 return &vmx->vcpu;
7974
7975free_vmcs:
5f3fbc34 7976 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7977free_msrs:
fb3f0f51
RR		 7978 kfree(vmx->guest_msrs);
7979uninit_vcpu:
7980 kvm_vcpu_uninit(&vmx->vcpu);
7981free_vcpu:
cdbecfc3 7982 free_vpid(vmx);
a4770347 7983 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7984 return ERR_PTR(err);
6aa8b732
AK		 7985}
7986
002c7f7c
YS		 7987static void __init vmx_check_processor_compat(void *rtn)
7988{
7989 struct vmcs_config vmcs_conf;
7990
7991 *(int *)rtn = 0;
7992 if (setup_vmcs_config(&vmcs_conf) < 0)
7993 *(int *)rtn = -EIO;
7994 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7995 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7996 smp_processor_id());
7997 *(int *)rtn = -EIO;
7998 }
7999}
8000
67253af5
SY		 8001static int get_ept_level(void)
8002{
8003 return VMX_EPT_DEFAULT_GAW + 1;
8004}
8005
4b12f0de 8006static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8007{
4b12f0de
SY		 8008 u64 ret;
8009
522c68c4
SY		 8010 /* For VT-d and EPT combination
8011 * 1. MMIO: always map as UC
8012 * 2. EPT with VT-d:
8013 * a. VT-d without snooping control feature: can't guarantee the
8014 * result, try to trust guest.
8015 * b. VT-d with snooping control feature: snooping control feature of
8016 * VT-d engine can guarantee the cache correctness. Just set it
8017 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8018 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8019 * consistent with host MTRR
8020 */
4b12f0de
SY		 8021 if (is_mmio)
8022 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8023 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8024 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8025 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8026 else
522c68c4 8027 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8028 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8029
8030 return ret;
64d4d521
SY		 8031}
8032
17cc3935 8033static int vmx_get_lpage_level(void)
344f414f 8034{
878403b7
SY		 8035 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8036 return PT_DIRECTORY_LEVEL;
8037 else
8038 /* For shadow and EPT supported 1GB page */
8039 return PT_PDPE_LEVEL;
344f414f
JR		 8040}
8041
0e851880
SY		 8042static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8043{
4e47c7a6
SY		 8044 struct kvm_cpuid_entry2 *best;
8045 struct vcpu_vmx *vmx = to_vmx(vcpu);
8046 u32 exec_control;
8047
8048 vmx->rdtscp_enabled = false;
8049 if (vmx_rdtscp_supported()) {
8050 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8051 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8052 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8053 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8054 vmx->rdtscp_enabled = true;
8055 else {
8056 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8057 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8058 exec_control);
8059 }
8060 }
8061 }
ad756a16 8062
ad756a16
MJ		 8063 /* Exposing INVPCID only when PCID is exposed */
8064 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8065 if (vmx_invpcid_supported() &&
4f977045 8066 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8067 guest_cpuid_has_pcid(vcpu)) {
29282fde 8068 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8069 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8070 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8071 exec_control);
8072 } else {
29282fde
TI		 8073 if (cpu_has_secondary_exec_ctrls()) {
8074 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8075 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8076 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8077 exec_control);
8078 }
ad756a16 8079 if (best)
4f977045 8080 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8081 }
0e851880
SY		 8082}
8083
d4330ef2
JR		 8084static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8085{
7b8050f5
NHE		 8086 if (func == 1 && nested)
8087 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8088}
8089
25d92081
YZ		 8090static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8091 struct x86_exception *fault)
8092{
533558bc
JK		 8093 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8094 u32 exit_reason;
25d92081
YZ		 8095
8096 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8097 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8098 else
533558bc
JK		 8099 exit_reason = EXIT_REASON_EPT_VIOLATION;
8100 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8101 vmcs12->guest_physical_address = fault->address;
8102}
8103
155a97a3
NHE		 8104/* Callbacks for nested_ept_init_mmu_context: */
8105
8106static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8107{
8108 /* return the page table to be shadowed - in our case, EPT12 */
8109 return get_vmcs12(vcpu)->ept_pointer;
8110}
8111
8a3c1a33 8112static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8113{
8a3c1a33 8114 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 8115 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8116
8117 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8118 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8119 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8120
8121 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8122}
8123
8124static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8125{
8126 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8127}
8128
feaf0c7d
GN		 8129static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8130 struct x86_exception *fault)
8131{
8132 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8133
8134 WARN_ON(!is_guest_mode(vcpu));
8135
8136 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8137 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 8138 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8139 vmcs_read32(VM_EXIT_INTR_INFO),
8140 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8141 else
8142 kvm_inject_page_fault(vcpu, fault);
8143}
8144
a2bcba50
WL		 8145static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8146 struct vmcs12 *vmcs12)
8147{
8148 struct vcpu_vmx *vmx = to_vmx(vcpu);
8149
8150 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8151 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8152 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8153 return false;
8154
8155 /*
8156 * Translate L1 physical address to host physical
8157 * address for vmcs02. Keep the page pinned, so this
8158 * physical address remains valid. We keep a reference
8159 * to it so we can release it later.
8160 */
8161 if (vmx->nested.apic_access_page) /* shouldn't happen */
8162 nested_release_page(vmx->nested.apic_access_page);
8163 vmx->nested.apic_access_page =
8164 nested_get_page(vcpu, vmcs12->apic_access_addr);
8165 }
a7c0b07d
WL		 8166
8167 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8168 /* TODO: Also verify bits beyond physical address width are 0 */
8169 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8170 return false;
8171
8172 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8173 nested_release_page(vmx->nested.virtual_apic_page);
8174 vmx->nested.virtual_apic_page =
8175 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8176
8177 /*
8178 * Failing the vm entry is _not_ what the processor does
8179 * but it's basically the only possibility we have.
8180 * We could still enter the guest if CR8 load exits are
8181 * enabled, CR8 store exits are enabled, and virtualize APIC
8182 * access is disabled; in this case the processor would never
8183 * use the TPR shadow and we could simply clear the bit from
8184 * the execution control. But such a configuration is useless,
8185 * so let's keep the code simple.
8186 */
8187 if (!vmx->nested.virtual_apic_page)
8188 return false;
8189 }
8190
a2bcba50
WL		 8191 return true;
8192}
8193
f4124500
JK		 8194static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8195{
8196 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8197 struct vcpu_vmx *vmx = to_vmx(vcpu);
8198
8199 if (vcpu->arch.virtual_tsc_khz == 0)
8200 return;
8201
8202 /* Make sure short timeouts reliably trigger an immediate vmexit.
8203 * hrtimer_start does not guarantee this. */
8204 if (preemption_timeout <= 1) {
8205 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8206 return;
8207 }
8208
8209 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8210 preemption_timeout *= 1000000;
8211 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8212 hrtimer_start(&vmx->nested.preemption_timer,
8213 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8214}
8215
fe3ef05c
NHE		 8216/*
8217 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8218 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8219 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8220 * guest in a way that will both be appropriate to L1's requests, and our
8221 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8222 * function also has additional necessary side-effects, like setting various
8223 * vcpu->arch fields.
8224 */
8225static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8226{
8227 struct vcpu_vmx *vmx = to_vmx(vcpu);
8228 u32 exec_control;
8229
8230 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8231 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8232 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8233 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8234 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8235 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8236 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8237 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8238 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8239 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8240 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8241 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8242 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8243 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8244 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8245 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8246 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8247 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8248 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8249 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8250 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8251 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8252 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8253 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8254 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8255 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8256 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8257 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8258 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8259 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8260 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8261 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8262 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8263 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8264 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8265 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8266
2996fca0
JK		 8267 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8268 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8269 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8270 } else {
8271 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8272 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8273 }
fe3ef05c
NHE		 8274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8275 vmcs12->vm_entry_intr_info_field);
8276 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8277 vmcs12->vm_entry_exception_error_code);
8278 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8279 vmcs12->vm_entry_instruction_len);
8280 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8281 vmcs12->guest_interruptibility_info);
fe3ef05c 8282 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8283 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8284 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8285 vmcs12->guest_pending_dbg_exceptions);
8286 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8287 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8288
8289 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8290
f4124500
JK		 8291 exec_control = vmcs12->pin_based_vm_exec_control;
8292 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8293 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8294 PIN_BASED_POSTED_INTR);
f4124500 8295 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8296
f4124500
JK		 8297 vmx->nested.preemption_timer_expired = false;
8298 if (nested_cpu_has_preemption_timer(vmcs12))
8299 vmx_start_preemption_timer(vcpu);
0238ea91 8300
fe3ef05c
NHE		 8301 /*
8302 * Whether page-faults are trapped is determined by a combination of
8303 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8304 * If enable_ept, L0 doesn't care about page faults and we should
8305 * set all of these to L1's desires. However, if !enable_ept, L0 does
8306 * care about (at least some) page faults, and because it is not easy
8307 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8308 * to exit on each and every L2 page fault. This is done by setting
8309 * MASK=MATCH=0 and (see below) EB.PF=1.
8310 * Note that below we don't need special code to set EB.PF beyond the
8311 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8312 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8313 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8314 *
8315 * A problem with this approach (when !enable_ept) is that L1 may be
8316 * injected with more page faults than it asked for. This could have
8317 * caused problems, but in practice existing hypervisors don't care.
8318 * To fix this, we will need to emulate the PFEC checking (on the L1
8319 * page tables), using walk_addr(), when injecting PFs to L1.
8320 */
8321 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8322 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8323 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8324 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8325
8326 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8327 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8328 if (!vmx->rdtscp_enabled)
8329 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8330 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8331 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8332 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8333 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8334 if (nested_cpu_has(vmcs12,
8335 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8336 exec_control |= vmcs12->secondary_vm_exec_control;
8337
8338 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8339 /*
8340 * If translation failed, no matter: This feature asks
8341 * to exit when accessing the given address, and if it
8342 * can never be accessed, this feature won't do
8343 * anything anyway.
8344 */
8345 if (!vmx->nested.apic_access_page)
8346 exec_control &=
8347 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8348 else
8349 vmcs_write64(APIC_ACCESS_ADDR,
8350 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8351 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8352 exec_control |=
8353 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8354 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8355 }
8356
8357 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8358 }
8359
8360
8361 /*
8362 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8363 * Some constant fields are set here by vmx_set_constant_host_state().
8364 * Other fields are different per CPU, and will be set later when
8365 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8366 */
a547c6db 8367 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8368
8369 /*
8370 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8371 * entry, but only if the current (host) sp changed from the value
8372 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8373 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8374 * here we just force the write to happen on entry.
8375 */
8376 vmx->host_rsp = 0;
8377
8378 exec_control = vmx_exec_control(vmx); /* L0's desires */
8379 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8380 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8381 exec_control &= ~CPU_BASED_TPR_SHADOW;
8382 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8383
8384 if (exec_control & CPU_BASED_TPR_SHADOW) {
8385 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8386 page_to_phys(vmx->nested.virtual_apic_page));
8387 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8388 }
8389
fe3ef05c
NHE		 8390 /*
8391 * Merging of IO and MSR bitmaps not currently supported.
8392 * Rather, exit every time.
8393 */
8394 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8395 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8396 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8397
8398 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8399
8400 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8401 * bitwise-or of what L1 wants to trap for L2, and what we want to
8402 * trap. Note that CR0.TS also needs updating - we do this later.
8403 */
8404 update_exception_bitmap(vcpu);
8405 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8406 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8407
8049d651
NHE		 8408 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8409 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8410 * bits are further modified by vmx_set_efer() below.
8411 */
f4124500 8412 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8413
8414 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8415 * emulated by vmx_set_efer(), below.
8416 */
2961e876 8417 vm_entry_controls_init(vmx,
8049d651
NHE		 8418 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8419 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8420 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8421
44811c02 8422 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8423 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8424 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8425 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8426 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8427
8428
8429 set_cr4_guest_host_mask(vmx);
8430
36be0b9d
PB		 8431 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8432 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8433
27fc51b2
NHE		 8434 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8435 vmcs_write64(TSC_OFFSET,
8436 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8437 else
8438 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8439
8440 if (enable_vpid) {
8441 /*
8442 * Trivially support vpid by letting L2s share their parent
8443 * L1's vpid. TODO: move to a more elaborate solution, giving
8444 * each L2 its own vpid and exposing the vpid feature to L1.
8445 */
8446 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8447 vmx_flush_tlb(vcpu);
8448 }
8449
155a97a3
NHE		 8450 if (nested_cpu_has_ept(vmcs12)) {
8451 kvm_mmu_unload(vcpu);
8452 nested_ept_init_mmu_context(vcpu);
8453 }
8454
fe3ef05c
NHE		 8455 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8456 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8457 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8458 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8459 else
8460 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8461 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8462 vmx_set_efer(vcpu, vcpu->arch.efer);
8463
8464 /*
8465 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8466 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8467 * The CR0_READ_SHADOW is what L2 should have expected to read given
8468 * the specifications by L1; It's not enough to take
8469 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8470 * have more bits than L1 expected.
8471 */
8472 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8473 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8474
8475 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8476 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8477
8478 /* shadow page tables on either EPT or shadow page tables */
8479 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8480 kvm_mmu_reset_context(vcpu);
8481
feaf0c7d
GN		 8482 if (!enable_ept)
8483 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8484
3633cfc3
NHE		 8485 /*
8486 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8487 */
8488 if (enable_ept) {
8489 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8490 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8491 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8492 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8493 }
8494
fe3ef05c
NHE		 8495 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8496 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8497}
8498
cd232ad0
NHE		 8499/*
8500 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8501 * for running an L2 nested guest.
8502 */
8503static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8504{
8505 struct vmcs12 *vmcs12;
8506 struct vcpu_vmx *vmx = to_vmx(vcpu);
8507 int cpu;
8508 struct loaded_vmcs *vmcs02;
384bb783 8509 bool ia32e;
cd232ad0
NHE		 8510
8511 if (!nested_vmx_check_permission(vcpu) ||
8512 !nested_vmx_check_vmcs12(vcpu))
8513 return 1;
8514
8515 skip_emulated_instruction(vcpu);
8516 vmcs12 = get_vmcs12(vcpu);
8517
012f83cb
AG		 8518 if (enable_shadow_vmcs)
8519 copy_shadow_to_vmcs12(vmx);
8520
7c177938
NHE		 8521 /*
8522 * The nested entry process starts with enforcing various prerequisites
8523 * on vmcs12 as required by the Intel SDM, and act appropriately when
8524 * they fail: As the SDM explains, some conditions should cause the
8525 * instruction to fail, while others will cause the instruction to seem
8526 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8527 * To speed up the normal (success) code path, we should avoid checking
8528 * for misconfigurations which will anyway be caught by the processor
8529 * when using the merged vmcs02.
8530 */
8531 if (vmcs12->launch_state == launch) {
8532 nested_vmx_failValid(vcpu,
8533 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8534 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8535 return 1;
8536 }
8537
6dfacadd
JK		 8538 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8539 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8540 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8541 return 1;
8542 }
8543
7c177938 8544 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8545 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8546 /*TODO: Also verify bits beyond physical address width are 0*/
8547 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8548 return 1;
8549 }
8550
a2bcba50 8551 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8552 /*TODO: Also verify bits beyond physical address width are 0*/
8553 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8554 return 1;
8555 }
8556
8557 if (vmcs12->vm_entry_msr_load_count > 0 ||
8558 vmcs12->vm_exit_msr_load_count > 0 ||
8559 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8560 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8561 __func__);
7c177938
NHE		 8562 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8563 return 1;
8564 }
8565
8566 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8567 nested_vmx_true_procbased_ctls_low,
8568 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8569 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8570 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8571 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8572 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8573 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8574 nested_vmx_true_exit_ctls_low,
8575 nested_vmx_exit_ctls_high) ||
7c177938 8576 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8577 nested_vmx_true_entry_ctls_low,
8578 nested_vmx_entry_ctls_high))
7c177938
NHE		 8579 {
8580 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8581 return 1;
8582 }
8583
8584 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8585 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8586 nested_vmx_failValid(vcpu,
8587 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8588 return 1;
8589 }
8590
92fbc7b1 8591 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8592 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8593 nested_vmx_entry_failure(vcpu, vmcs12,
8594 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8595 return 1;
8596 }
8597 if (vmcs12->vmcs_link_pointer != -1ull) {
8598 nested_vmx_entry_failure(vcpu, vmcs12,
8599 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8600 return 1;
8601 }
8602
384bb783 8603 /*
cb0c8cda 8604 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8605 * are performed on the field for the IA32_EFER MSR:
8606 * - Bits reserved in the IA32_EFER MSR must be 0.
8607 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8608 * the IA-32e mode guest VM-exit control. It must also be identical
8609 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8610 * CR0.PG) is 1.
8611 */
8612 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8613 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8614 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8615 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8616 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8617 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8618 nested_vmx_entry_failure(vcpu, vmcs12,
8619 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8620 return 1;
8621 }
8622 }
8623
8624 /*
8625 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8626 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8627 * the values of the LMA and LME bits in the field must each be that of
8628 * the host address-space size VM-exit control.
8629 */
8630 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8631 ia32e = (vmcs12->vm_exit_controls &
8632 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8633 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8634 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8635 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8636 nested_vmx_entry_failure(vcpu, vmcs12,
8637 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8638 return 1;
8639 }
8640 }
8641
7c177938
NHE		 8642 /*
8643 * We're finally done with prerequisite checking, and can start with
8644 * the nested entry.
8645 */
8646
cd232ad0
NHE		 8647 vmcs02 = nested_get_current_vmcs02(vmx);
8648 if (!vmcs02)
8649 return -ENOMEM;
8650
8651 enter_guest_mode(vcpu);
8652
8653 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8654
2996fca0
JK		 8655 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8656 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8657
cd232ad0
NHE		 8658 cpu = get_cpu();
8659 vmx->loaded_vmcs = vmcs02;
8660 vmx_vcpu_put(vcpu);
8661 vmx_vcpu_load(vcpu, cpu);
8662 vcpu->cpu = cpu;
8663 put_cpu();
8664
36c3cc42
JK		 8665 vmx_segment_cache_clear(vmx);
8666
cd232ad0
NHE		 8667 vmcs12->launch_state = 1;
8668
8669 prepare_vmcs02(vcpu, vmcs12);
8670
6dfacadd
JK		 8671 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8672 return kvm_emulate_halt(vcpu);
8673
7af40ad3
JK		 8674 vmx->nested.nested_run_pending = 1;
8675
cd232ad0
NHE		 8676 /*
8677 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8678 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8679 * returned as far as L1 is concerned. It will only return (and set
8680 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8681 */
8682 return 1;
8683}
8684
4704d0be
NHE		 8685/*
8686 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8687 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8688 * This function returns the new value we should put in vmcs12.guest_cr0.
8689 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8690 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8691 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8692 * didn't trap the bit, because if L1 did, so would L0).
8693 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8694 * been modified by L2, and L1 knows it. So just leave the old value of
8695 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8696 * isn't relevant, because if L0 traps this bit it can set it to anything.
8697 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8698 * changed these bits, and therefore they need to be updated, but L0
8699 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8700 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8701 */
8702static inline unsigned long
8703vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8704{
8705 return
8706 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8707 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8708 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8709 vcpu->arch.cr0_guest_owned_bits));
8710}
8711
8712static inline unsigned long
8713vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8714{
8715 return
8716 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8717 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8718 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8719 vcpu->arch.cr4_guest_owned_bits));
8720}
8721
5f3d5799
JK		 8722static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8723 struct vmcs12 *vmcs12)
8724{
8725 u32 idt_vectoring;
8726 unsigned int nr;
8727
851eb667 8728 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8729 nr = vcpu->arch.exception.nr;
8730 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8731
8732 if (kvm_exception_is_soft(nr)) {
8733 vmcs12->vm_exit_instruction_len =
8734 vcpu->arch.event_exit_inst_len;
8735 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8736 } else
8737 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8738
8739 if (vcpu->arch.exception.has_error_code) {
8740 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8741 vmcs12->idt_vectoring_error_code =
8742 vcpu->arch.exception.error_code;
8743 }
8744
8745 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8746 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8747 vmcs12->idt_vectoring_info_field =
8748 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8749 } else if (vcpu->arch.interrupt.pending) {
8750 nr = vcpu->arch.interrupt.nr;
8751 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8752
8753 if (vcpu->arch.interrupt.soft) {
8754 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8755 vmcs12->vm_entry_instruction_len =
8756 vcpu->arch.event_exit_inst_len;
8757 } else
8758 idt_vectoring |= INTR_TYPE_EXT_INTR;
8759
8760 vmcs12->idt_vectoring_info_field = idt_vectoring;
8761 }
8762}
8763
b6b8a145
JK		 8764static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8765{
8766 struct vcpu_vmx *vmx = to_vmx(vcpu);
8767
f4124500
JK		 8768 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8769 vmx->nested.preemption_timer_expired) {
8770 if (vmx->nested.nested_run_pending)
8771 return -EBUSY;
8772 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8773 return 0;
8774 }
8775
b6b8a145 8776 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8777 if (vmx->nested.nested_run_pending ||
8778 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8779 return -EBUSY;
8780 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8781 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8782 INTR_INFO_VALID_MASK, 0);
8783 /*
8784 * The NMI-triggered VM exit counts as injection:
8785 * clear this one and block further NMIs.
8786 */
8787 vcpu->arch.nmi_pending = 0;
8788 vmx_set_nmi_mask(vcpu, true);
8789 return 0;
8790 }
8791
8792 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8793 nested_exit_on_intr(vcpu)) {
8794 if (vmx->nested.nested_run_pending)
8795 return -EBUSY;
8796 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8797 }
8798
8799 return 0;
8800}
8801
f4124500
JK		 8802static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8803{
8804 ktime_t remaining =
8805 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8806 u64 value;
8807
8808 if (ktime_to_ns(remaining) <= 0)
8809 return 0;
8810
8811 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8812 do_div(value, 1000000);
8813 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8814}
8815
4704d0be
NHE		 8816/*
8817 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8818 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8819 * and this function updates it to reflect the changes to the guest state while
8820 * L2 was running (and perhaps made some exits which were handled directly by L0
8821 * without going back to L1), and to reflect the exit reason.
8822 * Note that we do not have to copy here all VMCS fields, just those that
8823 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8824 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8825 * which already writes to vmcs12 directly.
8826 */
533558bc
JK		 8827static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8828 u32 exit_reason, u32 exit_intr_info,
8829 unsigned long exit_qualification)
4704d0be
NHE		 8830{
8831 /* update guest state fields: */
8832 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8833 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8834
4704d0be
NHE		 8835 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8836 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8837 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8838
8839 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8840 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8841 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8842 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8843 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8844 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8845 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8846 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8847 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8848 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8849 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8850 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8851 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8852 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8853 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8854 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8855 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8856 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8857 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8858 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8859 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8860 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8861 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8862 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8863 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8864 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8865 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8866 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8867 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8868 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8869 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8870 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8871 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8872 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8873 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8874 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8875
4704d0be
NHE		 8876 vmcs12->guest_interruptibility_info =
8877 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8878 vmcs12->guest_pending_dbg_exceptions =
8879 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8880 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8881 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8882 else
8883 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8884
f4124500
JK		 8885 if (nested_cpu_has_preemption_timer(vmcs12)) {
8886 if (vmcs12->vm_exit_controls &
8887 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8888 vmcs12->vmx_preemption_timer_value =
8889 vmx_get_preemption_timer_value(vcpu);
8890 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8891 }
7854cbca 8892
3633cfc3
NHE		 8893 /*
8894 * In some cases (usually, nested EPT), L2 is allowed to change its
8895 * own CR3 without exiting. If it has changed it, we must keep it.
8896 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8897 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8898 *
8899 * Additionally, restore L2's PDPTR to vmcs12.
8900 */
8901 if (enable_ept) {
8902 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8903 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8904 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8905 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8906 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8907 }
8908
c18911a2
JK		 8909 vmcs12->vm_entry_controls =
8910 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8911 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8912
2996fca0
JK		 8913 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8914 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8915 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8916 }
8917
4704d0be
NHE		 8918 /* TODO: These cannot have changed unless we have MSR bitmaps and
8919 * the relevant bit asks not to trap the change */
b8c07d55 8920 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8921 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8922 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8923 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8924 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8925 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8926 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8927 if (vmx_mpx_supported())
8928 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8929
8930 /* update exit information fields: */
8931
533558bc
JK		 8932 vmcs12->vm_exit_reason = exit_reason;
8933 vmcs12->exit_qualification = exit_qualification;
4704d0be 8934
533558bc 8935 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8936 if ((vmcs12->vm_exit_intr_info &
8937 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8938 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8939 vmcs12->vm_exit_intr_error_code =
8940 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8941 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8942 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8943 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8944
5f3d5799
JK		 8945 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8946 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8947 * instead of reading the real value. */
4704d0be 8948 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8949
8950 /*
8951 * Transfer the event that L0 or L1 may wanted to inject into
8952 * L2 to IDT_VECTORING_INFO_FIELD.
8953 */
8954 vmcs12_save_pending_event(vcpu, vmcs12);
8955 }
8956
8957 /*
8958 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8959 * preserved above and would only end up incorrectly in L1.
8960 */
8961 vcpu->arch.nmi_injected = false;
8962 kvm_clear_exception_queue(vcpu);
8963 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8964}
8965
8966/*
8967 * A part of what we need to when the nested L2 guest exits and we want to
8968 * run its L1 parent, is to reset L1's guest state to the host state specified
8969 * in vmcs12.
8970 * This function is to be called not only on normal nested exit, but also on
8971 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8972 * Failures During or After Loading Guest State").
8973 * This function should be called when the active VMCS is L1's (vmcs01).
8974 */
733568f9
JK		 8975static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8976 struct vmcs12 *vmcs12)
4704d0be 8977{
21feb4eb
ACL		 8978 struct kvm_segment seg;
8979
4704d0be
NHE		 8980 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8981 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8982 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8983 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8984 else
8985 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8986 vmx_set_efer(vcpu, vcpu->arch.efer);
8987
8988 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8989 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8990 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8991 /*
8992 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8993 * actually changed, because it depends on the current state of
8994 * fpu_active (which may have changed).
8995 * Note that vmx_set_cr0 refers to efer set above.
8996 */
9e3e4dbf 8997 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8998 /*
8999 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9000 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9001 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9002 */
9003 update_exception_bitmap(vcpu);
9004 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9005 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9006
9007 /*
9008 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9009 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9010 */
9011 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9012 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9013
29bf08f1 9014 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9015
4704d0be
NHE		 9016 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9017 kvm_mmu_reset_context(vcpu);
9018
feaf0c7d
GN		 9019 if (!enable_ept)
9020 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9021
4704d0be
NHE		 9022 if (enable_vpid) {
9023 /*
9024 * Trivially support vpid by letting L2s share their parent
9025 * L1's vpid. TODO: move to a more elaborate solution, giving
9026 * each L2 its own vpid and exposing the vpid feature to L1.
9027 */
9028 vmx_flush_tlb(vcpu);
9029 }
9030
9031
9032 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9033 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9034 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9035 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9036 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9037
36be0b9d
PB		 9038 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9039 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9040 vmcs_write64(GUEST_BNDCFGS, 0);
9041
44811c02 9042 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9043 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9044 vcpu->arch.pat = vmcs12->host_ia32_pat;
9045 }
4704d0be
NHE		 9046 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9047 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9048 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9049
21feb4eb
ACL		 9050 /* Set L1 segment info according to Intel SDM
9051 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9052 seg = (struct kvm_segment) {
9053 .base = 0,
9054 .limit = 0xFFFFFFFF,
9055 .selector = vmcs12->host_cs_selector,
9056 .type = 11,
9057 .present = 1,
9058 .s = 1,
9059 .g = 1
9060 };
9061 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9062 seg.l = 1;
9063 else
9064 seg.db = 1;
9065 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9066 seg = (struct kvm_segment) {
9067 .base = 0,
9068 .limit = 0xFFFFFFFF,
9069 .type = 3,
9070 .present = 1,
9071 .s = 1,
9072 .db = 1,
9073 .g = 1
9074 };
9075 seg.selector = vmcs12->host_ds_selector;
9076 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9077 seg.selector = vmcs12->host_es_selector;
9078 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9079 seg.selector = vmcs12->host_ss_selector;
9080 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9081 seg.selector = vmcs12->host_fs_selector;
9082 seg.base = vmcs12->host_fs_base;
9083 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9084 seg.selector = vmcs12->host_gs_selector;
9085 seg.base = vmcs12->host_gs_base;
9086 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9087 seg = (struct kvm_segment) {
205befd9 9088 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9089 .limit = 0x67,
9090 .selector = vmcs12->host_tr_selector,
9091 .type = 11,
9092 .present = 1
9093 };
9094 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9095
503cd0c5
JK		 9096 kvm_set_dr(vcpu, 7, 0x400);
9097 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 9098}
9099
9100/*
9101 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9102 * and modify vmcs12 to make it see what it would expect to see there if
9103 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9104 */
533558bc
JK		 9105static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9106 u32 exit_intr_info,
9107 unsigned long exit_qualification)
4704d0be
NHE		 9108{
9109 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9110 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9111
5f3d5799
JK		 9112 /* trying to cancel vmlaunch/vmresume is a bug */
9113 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9114
4704d0be 9115 leave_guest_mode(vcpu);
533558bc
JK		 9116 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9117 exit_qualification);
4704d0be 9118
f3380ca5
WL		 9119 vmx_load_vmcs01(vcpu);
9120
77b0f5d6
BD		 9121 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9122 && nested_exit_intr_ack_set(vcpu)) {
9123 int irq = kvm_cpu_get_interrupt(vcpu);
9124 WARN_ON(irq < 0);
9125 vmcs12->vm_exit_intr_info = irq |
9126 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9127 }
9128
542060ea
JK		 9129 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9130 vmcs12->exit_qualification,
9131 vmcs12->idt_vectoring_info_field,
9132 vmcs12->vm_exit_intr_info,
9133 vmcs12->vm_exit_intr_error_code,
9134 KVM_ISA_VMX);
4704d0be 9135
2961e876
GN		 9136 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9137 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9138 vmx_segment_cache_clear(vmx);
9139
4704d0be
NHE		 9140 /* if no vmcs02 cache requested, remove the one we used */
9141 if (VMCS02_POOL_SIZE == 0)
9142 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9143
9144 load_vmcs12_host_state(vcpu, vmcs12);
9145
27fc51b2 9146 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9147 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9148
9149 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9150 vmx->host_rsp = 0;
9151
9152 /* Unpin physical memory we referred to in vmcs02 */
9153 if (vmx->nested.apic_access_page) {
9154 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9155 vmx->nested.apic_access_page = NULL;
4704d0be 9156 }
a7c0b07d
WL		 9157 if (vmx->nested.virtual_apic_page) {
9158 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9159 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9160 }
4704d0be 9161
38b99173
TC		 9162 /*
9163 * We are now running in L2, mmu_notifier will force to reload the
9164 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9165 */
9166 kvm_vcpu_reload_apic_access_page(vcpu);
9167
4704d0be
NHE		 9168 /*
9169 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9170 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9171 * success or failure flag accordingly.
9172 */
9173 if (unlikely(vmx->fail)) {
9174 vmx->fail = 0;
9175 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9176 } else
9177 nested_vmx_succeed(vcpu);
012f83cb
AG		 9178 if (enable_shadow_vmcs)
9179 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9180
9181 /* in case we halted in L2 */
9182 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9183}
9184
42124925
JK		 9185/*
9186 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9187 */
9188static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9189{
9190 if (is_guest_mode(vcpu))
533558bc 9191 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9192 free_nested(to_vmx(vcpu));
9193}
9194
7c177938
NHE		 9195/*
9196 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9197 * 23.7 "VM-entry failures during or after loading guest state" (this also
9198 * lists the acceptable exit-reason and exit-qualification parameters).
9199 * It should only be called before L2 actually succeeded to run, and when
9200 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9201 */
9202static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9203 struct vmcs12 *vmcs12,
9204 u32 reason, unsigned long qualification)
9205{
9206 load_vmcs12_host_state(vcpu, vmcs12);
9207 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9208 vmcs12->exit_qualification = qualification;
9209 nested_vmx_succeed(vcpu);
012f83cb
AG		 9210 if (enable_shadow_vmcs)
9211 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9212}
9213
8a76d7f2
JR		 9214static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9215 struct x86_instruction_info *info,
9216 enum x86_intercept_stage stage)
9217{
9218 return X86EMUL_CONTINUE;
9219}
9220
48d89b92 9221static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9222{
b4a2d31d
RK		 9223 if (ple_gap)
9224 shrink_ple_window(vcpu);
ae97a3b8
RK		 9225}
9226
cbdd1bea 9227static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9228 .cpu_has_kvm_support = cpu_has_kvm_support,
9229 .disabled_by_bios = vmx_disabled_by_bios,
9230 .hardware_setup = hardware_setup,
9231 .hardware_unsetup = hardware_unsetup,
002c7f7c 9232 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9233 .hardware_enable = hardware_enable,
9234 .hardware_disable = hardware_disable,
04547156 9235 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9236
9237 .vcpu_create = vmx_create_vcpu,
9238 .vcpu_free = vmx_free_vcpu,
04d2cc77 9239 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9240
04d2cc77 9241 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9242 .vcpu_load = vmx_vcpu_load,
9243 .vcpu_put = vmx_vcpu_put,
9244
c8639010 9245 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9246 .get_msr = vmx_get_msr,
9247 .set_msr = vmx_set_msr,
9248 .get_segment_base = vmx_get_segment_base,
9249 .get_segment = vmx_get_segment,
9250 .set_segment = vmx_set_segment,
2e4d2653 9251 .get_cpl = vmx_get_cpl,
6aa8b732 9252 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9253 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9254 .decache_cr3 = vmx_decache_cr3,
25c4c276 9255 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9256 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9257 .set_cr3 = vmx_set_cr3,
9258 .set_cr4 = vmx_set_cr4,
6aa8b732 9259 .set_efer = vmx_set_efer,
6aa8b732
AK		 9260 .get_idt = vmx_get_idt,
9261 .set_idt = vmx_set_idt,
9262 .get_gdt = vmx_get_gdt,
9263 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9264 .get_dr6 = vmx_get_dr6,
9265 .set_dr6 = vmx_set_dr6,
020df079 9266 .set_dr7 = vmx_set_dr7,
81908bf4 9267 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9268 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9269 .get_rflags = vmx_get_rflags,
9270 .set_rflags = vmx_set_rflags,
02daab21 9271 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9272
9273 .tlb_flush = vmx_flush_tlb,
6aa8b732 9274
6aa8b732 9275 .run = vmx_vcpu_run,
6062d012 9276 .handle_exit = vmx_handle_exit,
6aa8b732 9277 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9278 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9279 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9280 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9281 .set_irq = vmx_inject_irq,
95ba8273 9282 .set_nmi = vmx_inject_nmi,
298101da 9283 .queue_exception = vmx_queue_exception,
b463a6f7 9284 .cancel_injection = vmx_cancel_injection,
78646121 9285 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9286 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9287 .get_nmi_mask = vmx_get_nmi_mask,
9288 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9289 .enable_nmi_window = enable_nmi_window,
9290 .enable_irq_window = enable_irq_window,
9291 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9292 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9293 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9294 .vm_has_apicv = vmx_vm_has_apicv,
9295 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9296 .hwapic_irr_update = vmx_hwapic_irr_update,
9297 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9298 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9299 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9300
cbc94022 9301 .set_tss_addr = vmx_set_tss_addr,
67253af5 9302 .get_tdp_level = get_ept_level,
4b12f0de 9303 .get_mt_mask = vmx_get_mt_mask,
229456fc 9304
586f9607 9305 .get_exit_info = vmx_get_exit_info,
586f9607 9306
17cc3935 9307 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9308
9309 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9310
9311 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9312 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9313
9314 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9315
9316 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9317
4051b188 9318 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9319 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9320 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9321 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9322 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9323 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9324
9325 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9326
9327 .check_intercept = vmx_check_intercept,
a547c6db 9328 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9329 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9330
9331 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9332
9333 .sched_in = vmx_sched_in,
6aa8b732
AK		 9334};
9335
9336static int __init vmx_init(void)
9337{
34a1cd60
TC		 9338 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9339 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9340 if (r)
34a1cd60 9341 return r;
25c5f225 9342
8f536b76
ZY		 9343#ifdef CONFIG_KEXEC
9344 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9345 crash_vmclear_local_loaded_vmcss);
9346#endif
9347
fdef3ad1 9348 return 0;
6aa8b732
AK		 9349}
9350
9351static void __exit vmx_exit(void)
9352{
8f536b76 9353#ifdef CONFIG_KEXEC
3b63a43f 9354 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9355 synchronize_rcu();
9356#endif
9357
cb498ea2 9358 kvm_exit();
6aa8b732
AK		 9359}
9360
9361module_init(vmx_init)
9362module_exit(vmx_exit)
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