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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 | 26 | |
055403b2 | 27 | #include "qemu-common.h" |
6180a181 FB |
28 | #include "cpu.h" |
29 | #include "exec-all.h" | |
b67d9a52 | 30 | #include "tcg.h" |
b3c7724c | 31 | #include "hw/hw.h" |
cc9e98cb | 32 | #include "hw/qdev.h" |
74576198 | 33 | #include "osdep.h" |
7ba1e619 | 34 | #include "kvm.h" |
29e922b6 | 35 | #include "qemu-timer.h" |
53a5960a PB |
36 | #if defined(CONFIG_USER_ONLY) |
37 | #include <qemu.h> | |
fd052bf6 | 38 | #include <signal.h> |
f01576f1 JL |
39 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
40 | #include <sys/param.h> | |
41 | #if __FreeBSD_version >= 700104 | |
42 | #define HAVE_KINFO_GETVMMAP | |
43 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
44 | #include <sys/time.h> | |
45 | #include <sys/proc.h> | |
46 | #include <machine/profile.h> | |
47 | #define _KERNEL | |
48 | #include <sys/user.h> | |
49 | #undef _KERNEL | |
50 | #undef sigqueue | |
51 | #include <libutil.h> | |
52 | #endif | |
53 | #endif | |
53a5960a | 54 | #endif |
54936004 | 55 | |
fd6ce8f6 | 56 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 57 | //#define DEBUG_FLUSH |
9fa3e853 | 58 | //#define DEBUG_TLB |
67d3b957 | 59 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
60 | |
61 | /* make various TB consistency checks */ | |
5fafdf24 TS |
62 | //#define DEBUG_TB_CHECK |
63 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 64 | |
1196be37 | 65 | //#define DEBUG_IOPORT |
db7b5426 | 66 | //#define DEBUG_SUBPAGE |
1196be37 | 67 | |
99773bd4 PB |
68 | #if !defined(CONFIG_USER_ONLY) |
69 | /* TB consistency checks only implemented for usermode emulation. */ | |
70 | #undef DEBUG_TB_CHECK | |
71 | #endif | |
72 | ||
9fa3e853 FB |
73 | #define SMC_BITMAP_USE_THRESHOLD 10 |
74 | ||
bdaf78e0 | 75 | static TranslationBlock *tbs; |
24ab68ac | 76 | static int code_gen_max_blocks; |
9fa3e853 | 77 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 78 | static int nb_tbs; |
eb51d102 | 79 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 80 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 81 | |
141ac468 BS |
82 | #if defined(__arm__) || defined(__sparc_v9__) |
83 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
84 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
85 | section close to code segment. */ |
86 | #define code_gen_section \ | |
87 | __attribute__((__section__(".gen_code"))) \ | |
88 | __attribute__((aligned (32))) | |
f8e2af11 SW |
89 | #elif defined(_WIN32) |
90 | /* Maximum alignment for Win32 is 16. */ | |
91 | #define code_gen_section \ | |
92 | __attribute__((aligned (16))) | |
d03d860b BS |
93 | #else |
94 | #define code_gen_section \ | |
95 | __attribute__((aligned (32))) | |
96 | #endif | |
97 | ||
98 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
99 | static uint8_t *code_gen_buffer; |
100 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 101 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 102 | static unsigned long code_gen_buffer_max_size; |
24ab68ac | 103 | static uint8_t *code_gen_ptr; |
fd6ce8f6 | 104 | |
e2eef170 | 105 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 106 | int phys_ram_fd; |
74576198 | 107 | static int in_migration; |
94a6b54f | 108 | |
f471a17e | 109 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; |
e2eef170 | 110 | #endif |
9fa3e853 | 111 | |
6a00d601 FB |
112 | CPUState *first_cpu; |
113 | /* current CPU in the current thread. It is only valid inside | |
114 | cpu_exec() */ | |
5fafdf24 | 115 | CPUState *cpu_single_env; |
2e70f6ef | 116 | /* 0 = Do not count executed instructions. |
bf20dc07 | 117 | 1 = Precise instruction counting. |
2e70f6ef PB |
118 | 2 = Adaptive rate instruction counting. */ |
119 | int use_icount = 0; | |
120 | /* Current instruction counter. While executing translated code this may | |
121 | include some instructions that have not yet been executed. */ | |
122 | int64_t qemu_icount; | |
6a00d601 | 123 | |
54936004 | 124 | typedef struct PageDesc { |
92e873b9 | 125 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 126 | TranslationBlock *first_tb; |
9fa3e853 FB |
127 | /* in order to optimize self modifying code, we count the number |
128 | of lookups we do to a given page to use a bitmap */ | |
129 | unsigned int code_write_count; | |
130 | uint8_t *code_bitmap; | |
131 | #if defined(CONFIG_USER_ONLY) | |
132 | unsigned long flags; | |
133 | #endif | |
54936004 FB |
134 | } PageDesc; |
135 | ||
41c1b1c9 | 136 | /* In system mode we want L1_MAP to be based on ram offsets, |
5cd2c5b6 RH |
137 | while in user mode we want it to be based on virtual addresses. */ |
138 | #if !defined(CONFIG_USER_ONLY) | |
41c1b1c9 PB |
139 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
140 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
141 | #else | |
5cd2c5b6 | 142 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
41c1b1c9 | 143 | #endif |
bedb69ea | 144 | #else |
5cd2c5b6 | 145 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
bedb69ea | 146 | #endif |
54936004 | 147 | |
5cd2c5b6 RH |
148 | /* Size of the L2 (and L3, etc) page tables. */ |
149 | #define L2_BITS 10 | |
54936004 FB |
150 | #define L2_SIZE (1 << L2_BITS) |
151 | ||
5cd2c5b6 RH |
152 | /* The bits remaining after N lower levels of page tables. */ |
153 | #define P_L1_BITS_REM \ | |
154 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
155 | #define V_L1_BITS_REM \ | |
156 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
157 | ||
158 | /* Size of the L1 page table. Avoid silly small sizes. */ | |
159 | #if P_L1_BITS_REM < 4 | |
160 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) | |
161 | #else | |
162 | #define P_L1_BITS P_L1_BITS_REM | |
163 | #endif | |
164 | ||
165 | #if V_L1_BITS_REM < 4 | |
166 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
167 | #else | |
168 | #define V_L1_BITS V_L1_BITS_REM | |
169 | #endif | |
170 | ||
171 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) | |
172 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
173 | ||
174 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) | |
175 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
176 | ||
83fb7adf FB |
177 | unsigned long qemu_real_host_page_size; |
178 | unsigned long qemu_host_page_bits; | |
179 | unsigned long qemu_host_page_size; | |
180 | unsigned long qemu_host_page_mask; | |
54936004 | 181 | |
5cd2c5b6 RH |
182 | /* This is a multi-level map on the virtual address space. |
183 | The bottom level has pointers to PageDesc. */ | |
184 | static void *l1_map[V_L1_SIZE]; | |
54936004 | 185 | |
e2eef170 | 186 | #if !defined(CONFIG_USER_ONLY) |
41c1b1c9 PB |
187 | typedef struct PhysPageDesc { |
188 | /* offset in host memory of the page + io_index in the low bits */ | |
189 | ram_addr_t phys_offset; | |
190 | ram_addr_t region_offset; | |
191 | } PhysPageDesc; | |
192 | ||
5cd2c5b6 RH |
193 | /* This is a multi-level map on the physical address space. |
194 | The bottom level has pointers to PhysPageDesc. */ | |
195 | static void *l1_phys_map[P_L1_SIZE]; | |
6d9a1304 | 196 | |
e2eef170 PB |
197 | static void io_mem_init(void); |
198 | ||
33417e70 | 199 | /* io memory support */ |
33417e70 FB |
200 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
201 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 202 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 203 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
204 | static int io_mem_watch; |
205 | #endif | |
33417e70 | 206 | |
34865134 | 207 | /* log support */ |
1e8b27ca JR |
208 | #ifdef WIN32 |
209 | static const char *logfilename = "qemu.log"; | |
210 | #else | |
d9b630fd | 211 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 212 | #endif |
34865134 FB |
213 | FILE *logfile; |
214 | int loglevel; | |
e735b91c | 215 | static int log_append = 0; |
34865134 | 216 | |
e3db7226 | 217 | /* statistics */ |
b3755a91 | 218 | #if !defined(CONFIG_USER_ONLY) |
e3db7226 | 219 | static int tlb_flush_count; |
b3755a91 | 220 | #endif |
e3db7226 FB |
221 | static int tb_flush_count; |
222 | static int tb_phys_invalidate_count; | |
223 | ||
7cb69cae FB |
224 | #ifdef _WIN32 |
225 | static void map_exec(void *addr, long size) | |
226 | { | |
227 | DWORD old_protect; | |
228 | VirtualProtect(addr, size, | |
229 | PAGE_EXECUTE_READWRITE, &old_protect); | |
230 | ||
231 | } | |
232 | #else | |
233 | static void map_exec(void *addr, long size) | |
234 | { | |
4369415f | 235 | unsigned long start, end, page_size; |
7cb69cae | 236 | |
4369415f | 237 | page_size = getpagesize(); |
7cb69cae | 238 | start = (unsigned long)addr; |
4369415f | 239 | start &= ~(page_size - 1); |
7cb69cae FB |
240 | |
241 | end = (unsigned long)addr + size; | |
4369415f FB |
242 | end += page_size - 1; |
243 | end &= ~(page_size - 1); | |
7cb69cae FB |
244 | |
245 | mprotect((void *)start, end - start, | |
246 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
247 | } | |
248 | #endif | |
249 | ||
b346ff46 | 250 | static void page_init(void) |
54936004 | 251 | { |
83fb7adf | 252 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 253 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
254 | #ifdef _WIN32 |
255 | { | |
256 | SYSTEM_INFO system_info; | |
257 | ||
258 | GetSystemInfo(&system_info); | |
259 | qemu_real_host_page_size = system_info.dwPageSize; | |
260 | } | |
261 | #else | |
262 | qemu_real_host_page_size = getpagesize(); | |
263 | #endif | |
83fb7adf FB |
264 | if (qemu_host_page_size == 0) |
265 | qemu_host_page_size = qemu_real_host_page_size; | |
266 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
267 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
268 | qemu_host_page_bits = 0; | |
269 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
270 | qemu_host_page_bits++; | |
271 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
50a9569b | 272 | |
2e9a5713 | 273 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
50a9569b | 274 | { |
f01576f1 JL |
275 | #ifdef HAVE_KINFO_GETVMMAP |
276 | struct kinfo_vmentry *freep; | |
277 | int i, cnt; | |
278 | ||
279 | freep = kinfo_getvmmap(getpid(), &cnt); | |
280 | if (freep) { | |
281 | mmap_lock(); | |
282 | for (i = 0; i < cnt; i++) { | |
283 | unsigned long startaddr, endaddr; | |
284 | ||
285 | startaddr = freep[i].kve_start; | |
286 | endaddr = freep[i].kve_end; | |
287 | if (h2g_valid(startaddr)) { | |
288 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
289 | ||
290 | if (h2g_valid(endaddr)) { | |
291 | endaddr = h2g(endaddr); | |
fd436907 | 292 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
293 | } else { |
294 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
295 | endaddr = ~0ul; | |
fd436907 | 296 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
297 | #endif |
298 | } | |
299 | } | |
300 | } | |
301 | free(freep); | |
302 | mmap_unlock(); | |
303 | } | |
304 | #else | |
50a9569b | 305 | FILE *f; |
50a9569b | 306 | |
0776590d | 307 | last_brk = (unsigned long)sbrk(0); |
5cd2c5b6 | 308 | |
fd436907 | 309 | f = fopen("/compat/linux/proc/self/maps", "r"); |
50a9569b | 310 | if (f) { |
5cd2c5b6 RH |
311 | mmap_lock(); |
312 | ||
50a9569b | 313 | do { |
5cd2c5b6 RH |
314 | unsigned long startaddr, endaddr; |
315 | int n; | |
316 | ||
317 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
318 | ||
319 | if (n == 2 && h2g_valid(startaddr)) { | |
320 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
321 | ||
322 | if (h2g_valid(endaddr)) { | |
323 | endaddr = h2g(endaddr); | |
324 | } else { | |
325 | endaddr = ~0ul; | |
326 | } | |
327 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
50a9569b AZ |
328 | } |
329 | } while (!feof(f)); | |
5cd2c5b6 | 330 | |
50a9569b | 331 | fclose(f); |
5cd2c5b6 | 332 | mmap_unlock(); |
50a9569b | 333 | } |
f01576f1 | 334 | #endif |
50a9569b AZ |
335 | } |
336 | #endif | |
54936004 FB |
337 | } |
338 | ||
41c1b1c9 | 339 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
54936004 | 340 | { |
41c1b1c9 PB |
341 | PageDesc *pd; |
342 | void **lp; | |
343 | int i; | |
344 | ||
5cd2c5b6 | 345 | #if defined(CONFIG_USER_ONLY) |
2e9a5713 | 346 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ |
5cd2c5b6 RH |
347 | # define ALLOC(P, SIZE) \ |
348 | do { \ | |
349 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
350 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
5cd2c5b6 RH |
351 | } while (0) |
352 | #else | |
353 | # define ALLOC(P, SIZE) \ | |
354 | do { P = qemu_mallocz(SIZE); } while (0) | |
17e2377a | 355 | #endif |
434929bf | 356 | |
5cd2c5b6 RH |
357 | /* Level 1. Always allocated. */ |
358 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
359 | ||
360 | /* Level 2..N-1. */ | |
361 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
362 | void **p = *lp; | |
363 | ||
364 | if (p == NULL) { | |
365 | if (!alloc) { | |
366 | return NULL; | |
367 | } | |
368 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
369 | *lp = p; | |
17e2377a | 370 | } |
5cd2c5b6 RH |
371 | |
372 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
373 | } | |
374 | ||
375 | pd = *lp; | |
376 | if (pd == NULL) { | |
377 | if (!alloc) { | |
378 | return NULL; | |
379 | } | |
380 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
381 | *lp = pd; | |
54936004 | 382 | } |
5cd2c5b6 RH |
383 | |
384 | #undef ALLOC | |
5cd2c5b6 RH |
385 | |
386 | return pd + (index & (L2_SIZE - 1)); | |
54936004 FB |
387 | } |
388 | ||
41c1b1c9 | 389 | static inline PageDesc *page_find(tb_page_addr_t index) |
54936004 | 390 | { |
5cd2c5b6 | 391 | return page_find_alloc(index, 0); |
fd6ce8f6 FB |
392 | } |
393 | ||
6d9a1304 | 394 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 395 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 396 | { |
e3f4e2a4 | 397 | PhysPageDesc *pd; |
5cd2c5b6 RH |
398 | void **lp; |
399 | int i; | |
92e873b9 | 400 | |
5cd2c5b6 RH |
401 | /* Level 1. Always allocated. */ |
402 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); | |
108c49b8 | 403 | |
5cd2c5b6 RH |
404 | /* Level 2..N-1. */ |
405 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
406 | void **p = *lp; | |
407 | if (p == NULL) { | |
408 | if (!alloc) { | |
409 | return NULL; | |
410 | } | |
411 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); | |
412 | } | |
413 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
108c49b8 | 414 | } |
5cd2c5b6 | 415 | |
e3f4e2a4 | 416 | pd = *lp; |
5cd2c5b6 | 417 | if (pd == NULL) { |
e3f4e2a4 | 418 | int i; |
5cd2c5b6 RH |
419 | |
420 | if (!alloc) { | |
108c49b8 | 421 | return NULL; |
5cd2c5b6 RH |
422 | } |
423 | ||
424 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); | |
425 | ||
67c4d23c | 426 | for (i = 0; i < L2_SIZE; i++) { |
5cd2c5b6 RH |
427 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
428 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; | |
67c4d23c | 429 | } |
92e873b9 | 430 | } |
5cd2c5b6 RH |
431 | |
432 | return pd + (index & (L2_SIZE - 1)); | |
92e873b9 FB |
433 | } |
434 | ||
c227f099 | 435 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 436 | { |
108c49b8 | 437 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
438 | } |
439 | ||
c227f099 AL |
440 | static void tlb_protect_code(ram_addr_t ram_addr); |
441 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 442 | target_ulong vaddr); |
c8a706fe PB |
443 | #define mmap_lock() do { } while(0) |
444 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 445 | #endif |
fd6ce8f6 | 446 | |
4369415f FB |
447 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
448 | ||
449 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 450 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
451 | user mode. It will change when a dedicated libc will be used */ |
452 | #define USE_STATIC_CODE_GEN_BUFFER | |
453 | #endif | |
454 | ||
455 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
ebf50fb3 AJ |
456 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
457 | __attribute__((aligned (CODE_GEN_ALIGN))); | |
4369415f FB |
458 | #endif |
459 | ||
8fcd3692 | 460 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 461 | { |
4369415f FB |
462 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
463 | code_gen_buffer = static_code_gen_buffer; | |
464 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
465 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
466 | #else | |
26a5f13b FB |
467 | code_gen_buffer_size = tb_size; |
468 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
469 | #if defined(CONFIG_USER_ONLY) |
470 | /* in user mode, phys_ram_size is not meaningful */ | |
471 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
472 | #else | |
ccbb4d44 | 473 | /* XXX: needs adjustments */ |
94a6b54f | 474 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 475 | #endif |
26a5f13b FB |
476 | } |
477 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
478 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
479 | /* The code gen buffer location may have constraints depending on | |
480 | the host cpu and OS */ | |
481 | #if defined(__linux__) | |
482 | { | |
483 | int flags; | |
141ac468 BS |
484 | void *start = NULL; |
485 | ||
26a5f13b FB |
486 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
487 | #if defined(__x86_64__) | |
488 | flags |= MAP_32BIT; | |
489 | /* Cannot map more than that */ | |
490 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
491 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
492 | #elif defined(__sparc_v9__) |
493 | // Map the buffer below 2G, so we can use direct calls and branches | |
494 | flags |= MAP_FIXED; | |
495 | start = (void *) 0x60000000UL; | |
496 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
497 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 498 | #elif defined(__arm__) |
63d41246 | 499 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
500 | flags |= MAP_FIXED; |
501 | start = (void *) 0x01000000UL; | |
502 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
503 | code_gen_buffer_size = 16 * 1024 * 1024; | |
eba0b893 RH |
504 | #elif defined(__s390x__) |
505 | /* Map the buffer so that we can use direct calls and branches. */ | |
506 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
507 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { | |
508 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; | |
509 | } | |
510 | start = (void *)0x90000000UL; | |
26a5f13b | 511 | #endif |
141ac468 BS |
512 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
513 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
514 | flags, -1, 0); |
515 | if (code_gen_buffer == MAP_FAILED) { | |
516 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
517 | exit(1); | |
518 | } | |
519 | } | |
cbb608a5 BS |
520 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
521 | || defined(__DragonFly__) || defined(__OpenBSD__) | |
06e67a82 AL |
522 | { |
523 | int flags; | |
524 | void *addr = NULL; | |
525 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
526 | #if defined(__x86_64__) | |
527 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
528 | * 0x40000000 is free */ | |
529 | flags |= MAP_FIXED; | |
530 | addr = (void *)0x40000000; | |
531 | /* Cannot map more than that */ | |
532 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
533 | code_gen_buffer_size = (800 * 1024 * 1024); | |
4cd31ad2 BS |
534 | #elif defined(__sparc_v9__) |
535 | // Map the buffer below 2G, so we can use direct calls and branches | |
536 | flags |= MAP_FIXED; | |
537 | addr = (void *) 0x60000000UL; | |
538 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { | |
539 | code_gen_buffer_size = (512 * 1024 * 1024); | |
540 | } | |
06e67a82 AL |
541 | #endif |
542 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
543 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
544 | flags, -1, 0); | |
545 | if (code_gen_buffer == MAP_FAILED) { | |
546 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
547 | exit(1); | |
548 | } | |
549 | } | |
26a5f13b FB |
550 | #else |
551 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
552 | map_exec(code_gen_buffer, code_gen_buffer_size); |
553 | #endif | |
4369415f | 554 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
555 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
556 | code_gen_buffer_max_size = code_gen_buffer_size - | |
239fda31 | 557 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); |
26a5f13b FB |
558 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
559 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
560 | } | |
561 | ||
562 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
563 | (in bytes) allocated to the translation buffer. Zero means default | |
564 | size. */ | |
565 | void cpu_exec_init_all(unsigned long tb_size) | |
566 | { | |
26a5f13b FB |
567 | cpu_gen_init(); |
568 | code_gen_alloc(tb_size); | |
569 | code_gen_ptr = code_gen_buffer; | |
4369415f | 570 | page_init(); |
e2eef170 | 571 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 572 | io_mem_init(); |
e2eef170 | 573 | #endif |
9002ec79 RH |
574 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
575 | /* There's no guest base to take into account, so go ahead and | |
576 | initialize the prologue now. */ | |
577 | tcg_prologue_init(&tcg_ctx); | |
578 | #endif | |
26a5f13b FB |
579 | } |
580 | ||
9656f324 PB |
581 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
582 | ||
e59fb374 | 583 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
584 | { |
585 | CPUState *env = opaque; | |
9656f324 | 586 | |
3098dba0 AJ |
587 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
588 | version_id is increased. */ | |
589 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
590 | tlb_flush(env, 1); |
591 | ||
592 | return 0; | |
593 | } | |
e7f4eff7 JQ |
594 | |
595 | static const VMStateDescription vmstate_cpu_common = { | |
596 | .name = "cpu_common", | |
597 | .version_id = 1, | |
598 | .minimum_version_id = 1, | |
599 | .minimum_version_id_old = 1, | |
e7f4eff7 JQ |
600 | .post_load = cpu_common_post_load, |
601 | .fields = (VMStateField []) { | |
602 | VMSTATE_UINT32(halted, CPUState), | |
603 | VMSTATE_UINT32(interrupt_request, CPUState), | |
604 | VMSTATE_END_OF_LIST() | |
605 | } | |
606 | }; | |
9656f324 PB |
607 | #endif |
608 | ||
950f1472 GC |
609 | CPUState *qemu_get_cpu(int cpu) |
610 | { | |
611 | CPUState *env = first_cpu; | |
612 | ||
613 | while (env) { | |
614 | if (env->cpu_index == cpu) | |
615 | break; | |
616 | env = env->next_cpu; | |
617 | } | |
618 | ||
619 | return env; | |
620 | } | |
621 | ||
6a00d601 | 622 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 623 | { |
6a00d601 FB |
624 | CPUState **penv; |
625 | int cpu_index; | |
626 | ||
c2764719 PB |
627 | #if defined(CONFIG_USER_ONLY) |
628 | cpu_list_lock(); | |
629 | #endif | |
6a00d601 FB |
630 | env->next_cpu = NULL; |
631 | penv = &first_cpu; | |
632 | cpu_index = 0; | |
633 | while (*penv != NULL) { | |
1e9fa730 | 634 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
635 | cpu_index++; |
636 | } | |
637 | env->cpu_index = cpu_index; | |
268a362c | 638 | env->numa_node = 0; |
72cf2d4f BS |
639 | QTAILQ_INIT(&env->breakpoints); |
640 | QTAILQ_INIT(&env->watchpoints); | |
dc7a09cf JK |
641 | #ifndef CONFIG_USER_ONLY |
642 | env->thread_id = qemu_get_thread_id(); | |
643 | #endif | |
6a00d601 | 644 | *penv = env; |
c2764719 PB |
645 | #if defined(CONFIG_USER_ONLY) |
646 | cpu_list_unlock(); | |
647 | #endif | |
b3c7724c | 648 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
0be71e32 AW |
649 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
650 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, | |
b3c7724c PB |
651 | cpu_save, cpu_load, env); |
652 | #endif | |
fd6ce8f6 FB |
653 | } |
654 | ||
d1a1eb74 TG |
655 | /* Allocate a new translation block. Flush the translation buffer if |
656 | too many translation blocks or too much generated code. */ | |
657 | static TranslationBlock *tb_alloc(target_ulong pc) | |
658 | { | |
659 | TranslationBlock *tb; | |
660 | ||
661 | if (nb_tbs >= code_gen_max_blocks || | |
662 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
663 | return NULL; | |
664 | tb = &tbs[nb_tbs++]; | |
665 | tb->pc = pc; | |
666 | tb->cflags = 0; | |
667 | return tb; | |
668 | } | |
669 | ||
670 | void tb_free(TranslationBlock *tb) | |
671 | { | |
672 | /* In practice this is mostly used for single use temporary TB | |
673 | Ignore the hard cases and just back up if this TB happens to | |
674 | be the last one generated. */ | |
675 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
676 | code_gen_ptr = tb->tc_ptr; | |
677 | nb_tbs--; | |
678 | } | |
679 | } | |
680 | ||
9fa3e853 FB |
681 | static inline void invalidate_page_bitmap(PageDesc *p) |
682 | { | |
683 | if (p->code_bitmap) { | |
59817ccb | 684 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
685 | p->code_bitmap = NULL; |
686 | } | |
687 | p->code_write_count = 0; | |
688 | } | |
689 | ||
5cd2c5b6 RH |
690 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
691 | ||
692 | static void page_flush_tb_1 (int level, void **lp) | |
fd6ce8f6 | 693 | { |
5cd2c5b6 | 694 | int i; |
fd6ce8f6 | 695 | |
5cd2c5b6 RH |
696 | if (*lp == NULL) { |
697 | return; | |
698 | } | |
699 | if (level == 0) { | |
700 | PageDesc *pd = *lp; | |
7296abac | 701 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
702 | pd[i].first_tb = NULL; |
703 | invalidate_page_bitmap(pd + i); | |
fd6ce8f6 | 704 | } |
5cd2c5b6 RH |
705 | } else { |
706 | void **pp = *lp; | |
7296abac | 707 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
708 | page_flush_tb_1 (level - 1, pp + i); |
709 | } | |
710 | } | |
711 | } | |
712 | ||
713 | static void page_flush_tb(void) | |
714 | { | |
715 | int i; | |
716 | for (i = 0; i < V_L1_SIZE; i++) { | |
717 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
fd6ce8f6 FB |
718 | } |
719 | } | |
720 | ||
721 | /* flush all the translation blocks */ | |
d4e8164f | 722 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 723 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 724 | { |
6a00d601 | 725 | CPUState *env; |
0124311e | 726 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
727 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
728 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
729 | nb_tbs, nb_tbs > 0 ? | |
730 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 731 | #endif |
26a5f13b | 732 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
733 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
734 | ||
fd6ce8f6 | 735 | nb_tbs = 0; |
3b46e624 | 736 | |
6a00d601 FB |
737 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
738 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
739 | } | |
9fa3e853 | 740 | |
8a8a608f | 741 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 742 | page_flush_tb(); |
9fa3e853 | 743 | |
fd6ce8f6 | 744 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
745 | /* XXX: flush processor icache at this point if cache flush is |
746 | expensive */ | |
e3db7226 | 747 | tb_flush_count++; |
fd6ce8f6 FB |
748 | } |
749 | ||
750 | #ifdef DEBUG_TB_CHECK | |
751 | ||
bc98a7ef | 752 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
753 | { |
754 | TranslationBlock *tb; | |
755 | int i; | |
756 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
757 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
758 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
759 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
760 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
761 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
762 | " PC=%08lx size=%04x\n", | |
99773bd4 | 763 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
764 | } |
765 | } | |
766 | } | |
767 | } | |
768 | ||
769 | /* verify that all the pages have correct rights for code */ | |
770 | static void tb_page_check(void) | |
771 | { | |
772 | TranslationBlock *tb; | |
773 | int i, flags1, flags2; | |
3b46e624 | 774 | |
99773bd4 PB |
775 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
776 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
777 | flags1 = page_get_flags(tb->pc); |
778 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
779 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
780 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 781 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
782 | } |
783 | } | |
784 | } | |
785 | } | |
786 | ||
787 | #endif | |
788 | ||
789 | /* invalidate one TB */ | |
790 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
791 | int next_offset) | |
792 | { | |
793 | TranslationBlock *tb1; | |
794 | for(;;) { | |
795 | tb1 = *ptb; | |
796 | if (tb1 == tb) { | |
797 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
798 | break; | |
799 | } | |
800 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
801 | } | |
802 | } | |
803 | ||
9fa3e853 FB |
804 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
805 | { | |
806 | TranslationBlock *tb1; | |
807 | unsigned int n1; | |
808 | ||
809 | for(;;) { | |
810 | tb1 = *ptb; | |
811 | n1 = (long)tb1 & 3; | |
812 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
813 | if (tb1 == tb) { | |
814 | *ptb = tb1->page_next[n1]; | |
815 | break; | |
816 | } | |
817 | ptb = &tb1->page_next[n1]; | |
818 | } | |
819 | } | |
820 | ||
d4e8164f FB |
821 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
822 | { | |
823 | TranslationBlock *tb1, **ptb; | |
824 | unsigned int n1; | |
825 | ||
826 | ptb = &tb->jmp_next[n]; | |
827 | tb1 = *ptb; | |
828 | if (tb1) { | |
829 | /* find tb(n) in circular list */ | |
830 | for(;;) { | |
831 | tb1 = *ptb; | |
832 | n1 = (long)tb1 & 3; | |
833 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
834 | if (n1 == n && tb1 == tb) | |
835 | break; | |
836 | if (n1 == 2) { | |
837 | ptb = &tb1->jmp_first; | |
838 | } else { | |
839 | ptb = &tb1->jmp_next[n1]; | |
840 | } | |
841 | } | |
842 | /* now we can suppress tb(n) from the list */ | |
843 | *ptb = tb->jmp_next[n]; | |
844 | ||
845 | tb->jmp_next[n] = NULL; | |
846 | } | |
847 | } | |
848 | ||
849 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
850 | another TB */ | |
851 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
852 | { | |
853 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
854 | } | |
855 | ||
41c1b1c9 | 856 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
fd6ce8f6 | 857 | { |
6a00d601 | 858 | CPUState *env; |
8a40a180 | 859 | PageDesc *p; |
d4e8164f | 860 | unsigned int h, n1; |
41c1b1c9 | 861 | tb_page_addr_t phys_pc; |
8a40a180 | 862 | TranslationBlock *tb1, *tb2; |
3b46e624 | 863 | |
8a40a180 FB |
864 | /* remove the TB from the hash list */ |
865 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
866 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 867 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
868 | offsetof(TranslationBlock, phys_hash_next)); |
869 | ||
870 | /* remove the TB from the page list */ | |
871 | if (tb->page_addr[0] != page_addr) { | |
872 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
873 | tb_page_remove(&p->first_tb, tb); | |
874 | invalidate_page_bitmap(p); | |
875 | } | |
876 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
877 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
878 | tb_page_remove(&p->first_tb, tb); | |
879 | invalidate_page_bitmap(p); | |
880 | } | |
881 | ||
36bdbe54 | 882 | tb_invalidated_flag = 1; |
59817ccb | 883 | |
fd6ce8f6 | 884 | /* remove the TB from the hash list */ |
8a40a180 | 885 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
886 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
887 | if (env->tb_jmp_cache[h] == tb) | |
888 | env->tb_jmp_cache[h] = NULL; | |
889 | } | |
d4e8164f FB |
890 | |
891 | /* suppress this TB from the two jump lists */ | |
892 | tb_jmp_remove(tb, 0); | |
893 | tb_jmp_remove(tb, 1); | |
894 | ||
895 | /* suppress any remaining jumps to this TB */ | |
896 | tb1 = tb->jmp_first; | |
897 | for(;;) { | |
898 | n1 = (long)tb1 & 3; | |
899 | if (n1 == 2) | |
900 | break; | |
901 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
902 | tb2 = tb1->jmp_next[n1]; | |
903 | tb_reset_jump(tb1, n1); | |
904 | tb1->jmp_next[n1] = NULL; | |
905 | tb1 = tb2; | |
906 | } | |
907 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 908 | |
e3db7226 | 909 | tb_phys_invalidate_count++; |
9fa3e853 FB |
910 | } |
911 | ||
912 | static inline void set_bits(uint8_t *tab, int start, int len) | |
913 | { | |
914 | int end, mask, end1; | |
915 | ||
916 | end = start + len; | |
917 | tab += start >> 3; | |
918 | mask = 0xff << (start & 7); | |
919 | if ((start & ~7) == (end & ~7)) { | |
920 | if (start < end) { | |
921 | mask &= ~(0xff << (end & 7)); | |
922 | *tab |= mask; | |
923 | } | |
924 | } else { | |
925 | *tab++ |= mask; | |
926 | start = (start + 8) & ~7; | |
927 | end1 = end & ~7; | |
928 | while (start < end1) { | |
929 | *tab++ = 0xff; | |
930 | start += 8; | |
931 | } | |
932 | if (start < end) { | |
933 | mask = ~(0xff << (end & 7)); | |
934 | *tab |= mask; | |
935 | } | |
936 | } | |
937 | } | |
938 | ||
939 | static void build_page_bitmap(PageDesc *p) | |
940 | { | |
941 | int n, tb_start, tb_end; | |
942 | TranslationBlock *tb; | |
3b46e624 | 943 | |
b2a7081a | 944 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
945 | |
946 | tb = p->first_tb; | |
947 | while (tb != NULL) { | |
948 | n = (long)tb & 3; | |
949 | tb = (TranslationBlock *)((long)tb & ~3); | |
950 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
951 | if (n == 0) { | |
952 | /* NOTE: tb_end may be after the end of the page, but | |
953 | it is not a problem */ | |
954 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
955 | tb_end = tb_start + tb->size; | |
956 | if (tb_end > TARGET_PAGE_SIZE) | |
957 | tb_end = TARGET_PAGE_SIZE; | |
958 | } else { | |
959 | tb_start = 0; | |
960 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
961 | } | |
962 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
963 | tb = tb->page_next[n]; | |
964 | } | |
965 | } | |
966 | ||
2e70f6ef PB |
967 | TranslationBlock *tb_gen_code(CPUState *env, |
968 | target_ulong pc, target_ulong cs_base, | |
969 | int flags, int cflags) | |
d720b93d FB |
970 | { |
971 | TranslationBlock *tb; | |
972 | uint8_t *tc_ptr; | |
41c1b1c9 PB |
973 | tb_page_addr_t phys_pc, phys_page2; |
974 | target_ulong virt_page2; | |
d720b93d FB |
975 | int code_gen_size; |
976 | ||
41c1b1c9 | 977 | phys_pc = get_page_addr_code(env, pc); |
c27004ec | 978 | tb = tb_alloc(pc); |
d720b93d FB |
979 | if (!tb) { |
980 | /* flush must be done */ | |
981 | tb_flush(env); | |
982 | /* cannot fail at this point */ | |
c27004ec | 983 | tb = tb_alloc(pc); |
2e70f6ef PB |
984 | /* Don't forget to invalidate previous TB info. */ |
985 | tb_invalidated_flag = 1; | |
d720b93d FB |
986 | } |
987 | tc_ptr = code_gen_ptr; | |
988 | tb->tc_ptr = tc_ptr; | |
989 | tb->cs_base = cs_base; | |
990 | tb->flags = flags; | |
991 | tb->cflags = cflags; | |
d07bde88 | 992 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 993 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 994 | |
d720b93d | 995 | /* check next page if needed */ |
c27004ec | 996 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 997 | phys_page2 = -1; |
c27004ec | 998 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
41c1b1c9 | 999 | phys_page2 = get_page_addr_code(env, virt_page2); |
d720b93d | 1000 | } |
41c1b1c9 | 1001 | tb_link_page(tb, phys_pc, phys_page2); |
2e70f6ef | 1002 | return tb; |
d720b93d | 1003 | } |
3b46e624 | 1004 | |
9fa3e853 FB |
1005 | /* invalidate all TBs which intersect with the target physical page |
1006 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
1007 | the same physical page. 'is_cpu_write_access' should be true if called |
1008 | from a real cpu write access: the virtual CPU will exit the current | |
1009 | TB if code is modified inside this TB. */ | |
41c1b1c9 | 1010 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
d720b93d FB |
1011 | int is_cpu_write_access) |
1012 | { | |
6b917547 | 1013 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 1014 | CPUState *env = cpu_single_env; |
41c1b1c9 | 1015 | tb_page_addr_t tb_start, tb_end; |
6b917547 AL |
1016 | PageDesc *p; |
1017 | int n; | |
1018 | #ifdef TARGET_HAS_PRECISE_SMC | |
1019 | int current_tb_not_found = is_cpu_write_access; | |
1020 | TranslationBlock *current_tb = NULL; | |
1021 | int current_tb_modified = 0; | |
1022 | target_ulong current_pc = 0; | |
1023 | target_ulong current_cs_base = 0; | |
1024 | int current_flags = 0; | |
1025 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1026 | |
1027 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 1028 | if (!p) |
9fa3e853 | 1029 | return; |
5fafdf24 | 1030 | if (!p->code_bitmap && |
d720b93d FB |
1031 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
1032 | is_cpu_write_access) { | |
9fa3e853 FB |
1033 | /* build code bitmap */ |
1034 | build_page_bitmap(p); | |
1035 | } | |
1036 | ||
1037 | /* we remove all the TBs in the range [start, end[ */ | |
1038 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
1039 | tb = p->first_tb; | |
1040 | while (tb != NULL) { | |
1041 | n = (long)tb & 3; | |
1042 | tb = (TranslationBlock *)((long)tb & ~3); | |
1043 | tb_next = tb->page_next[n]; | |
1044 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1045 | if (n == 0) { | |
1046 | /* NOTE: tb_end may be after the end of the page, but | |
1047 | it is not a problem */ | |
1048 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1049 | tb_end = tb_start + tb->size; | |
1050 | } else { | |
1051 | tb_start = tb->page_addr[1]; | |
1052 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1053 | } | |
1054 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
1055 | #ifdef TARGET_HAS_PRECISE_SMC |
1056 | if (current_tb_not_found) { | |
1057 | current_tb_not_found = 0; | |
1058 | current_tb = NULL; | |
2e70f6ef | 1059 | if (env->mem_io_pc) { |
d720b93d | 1060 | /* now we have a real cpu fault */ |
2e70f6ef | 1061 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
1062 | } |
1063 | } | |
1064 | if (current_tb == tb && | |
2e70f6ef | 1065 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1066 | /* If we are modifying the current TB, we must stop |
1067 | its execution. We could be more precise by checking | |
1068 | that the modification is after the current PC, but it | |
1069 | would require a specialized function to partially | |
1070 | restore the CPU state */ | |
3b46e624 | 1071 | |
d720b93d | 1072 | current_tb_modified = 1; |
618ba8e6 | 1073 | cpu_restore_state(current_tb, env, env->mem_io_pc); |
6b917547 AL |
1074 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1075 | ¤t_flags); | |
d720b93d FB |
1076 | } |
1077 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
1078 | /* we need to do that to handle the case where a signal |
1079 | occurs while doing tb_phys_invalidate() */ | |
1080 | saved_tb = NULL; | |
1081 | if (env) { | |
1082 | saved_tb = env->current_tb; | |
1083 | env->current_tb = NULL; | |
1084 | } | |
9fa3e853 | 1085 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
1086 | if (env) { |
1087 | env->current_tb = saved_tb; | |
1088 | if (env->interrupt_request && env->current_tb) | |
1089 | cpu_interrupt(env, env->interrupt_request); | |
1090 | } | |
9fa3e853 FB |
1091 | } |
1092 | tb = tb_next; | |
1093 | } | |
1094 | #if !defined(CONFIG_USER_ONLY) | |
1095 | /* if no code remaining, no need to continue to use slow writes */ | |
1096 | if (!p->first_tb) { | |
1097 | invalidate_page_bitmap(p); | |
d720b93d | 1098 | if (is_cpu_write_access) { |
2e70f6ef | 1099 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1100 | } |
1101 | } | |
1102 | #endif | |
1103 | #ifdef TARGET_HAS_PRECISE_SMC | |
1104 | if (current_tb_modified) { | |
1105 | /* we generate a block containing just the instruction | |
1106 | modifying the memory. It will ensure that it cannot modify | |
1107 | itself */ | |
ea1c1802 | 1108 | env->current_tb = NULL; |
2e70f6ef | 1109 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1110 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1111 | } |
fd6ce8f6 | 1112 | #endif |
9fa3e853 | 1113 | } |
fd6ce8f6 | 1114 | |
9fa3e853 | 1115 | /* len must be <= 8 and start must be a multiple of len */ |
41c1b1c9 | 1116 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
9fa3e853 FB |
1117 | { |
1118 | PageDesc *p; | |
1119 | int offset, b; | |
59817ccb | 1120 | #if 0 |
a4193c8a | 1121 | if (1) { |
93fcfe39 AL |
1122 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1123 | cpu_single_env->mem_io_vaddr, len, | |
1124 | cpu_single_env->eip, | |
1125 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1126 | } |
1127 | #endif | |
9fa3e853 | 1128 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1129 | if (!p) |
9fa3e853 FB |
1130 | return; |
1131 | if (p->code_bitmap) { | |
1132 | offset = start & ~TARGET_PAGE_MASK; | |
1133 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1134 | if (b & ((1 << len) - 1)) | |
1135 | goto do_invalidate; | |
1136 | } else { | |
1137 | do_invalidate: | |
d720b93d | 1138 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1139 | } |
1140 | } | |
1141 | ||
9fa3e853 | 1142 | #if !defined(CONFIG_SOFTMMU) |
41c1b1c9 | 1143 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d720b93d | 1144 | unsigned long pc, void *puc) |
9fa3e853 | 1145 | { |
6b917547 | 1146 | TranslationBlock *tb; |
9fa3e853 | 1147 | PageDesc *p; |
6b917547 | 1148 | int n; |
d720b93d | 1149 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1150 | TranslationBlock *current_tb = NULL; |
d720b93d | 1151 | CPUState *env = cpu_single_env; |
6b917547 AL |
1152 | int current_tb_modified = 0; |
1153 | target_ulong current_pc = 0; | |
1154 | target_ulong current_cs_base = 0; | |
1155 | int current_flags = 0; | |
d720b93d | 1156 | #endif |
9fa3e853 FB |
1157 | |
1158 | addr &= TARGET_PAGE_MASK; | |
1159 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1160 | if (!p) |
9fa3e853 FB |
1161 | return; |
1162 | tb = p->first_tb; | |
d720b93d FB |
1163 | #ifdef TARGET_HAS_PRECISE_SMC |
1164 | if (tb && pc != 0) { | |
1165 | current_tb = tb_find_pc(pc); | |
1166 | } | |
1167 | #endif | |
9fa3e853 FB |
1168 | while (tb != NULL) { |
1169 | n = (long)tb & 3; | |
1170 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1171 | #ifdef TARGET_HAS_PRECISE_SMC |
1172 | if (current_tb == tb && | |
2e70f6ef | 1173 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1174 | /* If we are modifying the current TB, we must stop |
1175 | its execution. We could be more precise by checking | |
1176 | that the modification is after the current PC, but it | |
1177 | would require a specialized function to partially | |
1178 | restore the CPU state */ | |
3b46e624 | 1179 | |
d720b93d | 1180 | current_tb_modified = 1; |
618ba8e6 | 1181 | cpu_restore_state(current_tb, env, pc); |
6b917547 AL |
1182 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1183 | ¤t_flags); | |
d720b93d FB |
1184 | } |
1185 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1186 | tb_phys_invalidate(tb, addr); |
1187 | tb = tb->page_next[n]; | |
1188 | } | |
fd6ce8f6 | 1189 | p->first_tb = NULL; |
d720b93d FB |
1190 | #ifdef TARGET_HAS_PRECISE_SMC |
1191 | if (current_tb_modified) { | |
1192 | /* we generate a block containing just the instruction | |
1193 | modifying the memory. It will ensure that it cannot modify | |
1194 | itself */ | |
ea1c1802 | 1195 | env->current_tb = NULL; |
2e70f6ef | 1196 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1197 | cpu_resume_from_signal(env, puc); |
1198 | } | |
1199 | #endif | |
fd6ce8f6 | 1200 | } |
9fa3e853 | 1201 | #endif |
fd6ce8f6 FB |
1202 | |
1203 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1204 | static inline void tb_alloc_page(TranslationBlock *tb, |
41c1b1c9 | 1205 | unsigned int n, tb_page_addr_t page_addr) |
fd6ce8f6 FB |
1206 | { |
1207 | PageDesc *p; | |
9fa3e853 FB |
1208 | TranslationBlock *last_first_tb; |
1209 | ||
1210 | tb->page_addr[n] = page_addr; | |
5cd2c5b6 | 1211 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
9fa3e853 FB |
1212 | tb->page_next[n] = p->first_tb; |
1213 | last_first_tb = p->first_tb; | |
1214 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1215 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1216 | |
107db443 | 1217 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1218 | |
9fa3e853 | 1219 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1220 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1221 | target_ulong addr; |
1222 | PageDesc *p2; | |
9fa3e853 FB |
1223 | int prot; |
1224 | ||
fd6ce8f6 FB |
1225 | /* force the host page as non writable (writes will have a |
1226 | page fault + mprotect overhead) */ | |
53a5960a | 1227 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1228 | prot = 0; |
53a5960a PB |
1229 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1230 | addr += TARGET_PAGE_SIZE) { | |
1231 | ||
1232 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1233 | if (!p2) | |
1234 | continue; | |
1235 | prot |= p2->flags; | |
1236 | p2->flags &= ~PAGE_WRITE; | |
53a5960a | 1237 | } |
5fafdf24 | 1238 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1239 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1240 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1241 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1242 | page_addr); |
fd6ce8f6 | 1243 | #endif |
fd6ce8f6 | 1244 | } |
9fa3e853 FB |
1245 | #else |
1246 | /* if some code is already present, then the pages are already | |
1247 | protected. So we handle the case where only the first TB is | |
1248 | allocated in a physical page */ | |
1249 | if (!last_first_tb) { | |
6a00d601 | 1250 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1251 | } |
1252 | #endif | |
d720b93d FB |
1253 | |
1254 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1255 | } |
1256 | ||
9fa3e853 FB |
1257 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1258 | (-1) to indicate that only one page contains the TB. */ | |
41c1b1c9 PB |
1259 | void tb_link_page(TranslationBlock *tb, |
1260 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) | |
d4e8164f | 1261 | { |
9fa3e853 FB |
1262 | unsigned int h; |
1263 | TranslationBlock **ptb; | |
1264 | ||
c8a706fe PB |
1265 | /* Grab the mmap lock to stop another thread invalidating this TB |
1266 | before we are done. */ | |
1267 | mmap_lock(); | |
9fa3e853 FB |
1268 | /* add in the physical hash table */ |
1269 | h = tb_phys_hash_func(phys_pc); | |
1270 | ptb = &tb_phys_hash[h]; | |
1271 | tb->phys_hash_next = *ptb; | |
1272 | *ptb = tb; | |
fd6ce8f6 FB |
1273 | |
1274 | /* add in the page list */ | |
9fa3e853 FB |
1275 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1276 | if (phys_page2 != -1) | |
1277 | tb_alloc_page(tb, 1, phys_page2); | |
1278 | else | |
1279 | tb->page_addr[1] = -1; | |
9fa3e853 | 1280 | |
d4e8164f FB |
1281 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1282 | tb->jmp_next[0] = NULL; | |
1283 | tb->jmp_next[1] = NULL; | |
1284 | ||
1285 | /* init original jump addresses */ | |
1286 | if (tb->tb_next_offset[0] != 0xffff) | |
1287 | tb_reset_jump(tb, 0); | |
1288 | if (tb->tb_next_offset[1] != 0xffff) | |
1289 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1290 | |
1291 | #ifdef DEBUG_TB_CHECK | |
1292 | tb_page_check(); | |
1293 | #endif | |
c8a706fe | 1294 | mmap_unlock(); |
fd6ce8f6 FB |
1295 | } |
1296 | ||
9fa3e853 FB |
1297 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1298 | tb[1].tc_ptr. Return NULL if not found */ | |
1299 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1300 | { |
9fa3e853 FB |
1301 | int m_min, m_max, m; |
1302 | unsigned long v; | |
1303 | TranslationBlock *tb; | |
a513fe19 FB |
1304 | |
1305 | if (nb_tbs <= 0) | |
1306 | return NULL; | |
1307 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1308 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1309 | return NULL; | |
1310 | /* binary search (cf Knuth) */ | |
1311 | m_min = 0; | |
1312 | m_max = nb_tbs - 1; | |
1313 | while (m_min <= m_max) { | |
1314 | m = (m_min + m_max) >> 1; | |
1315 | tb = &tbs[m]; | |
1316 | v = (unsigned long)tb->tc_ptr; | |
1317 | if (v == tc_ptr) | |
1318 | return tb; | |
1319 | else if (tc_ptr < v) { | |
1320 | m_max = m - 1; | |
1321 | } else { | |
1322 | m_min = m + 1; | |
1323 | } | |
5fafdf24 | 1324 | } |
a513fe19 FB |
1325 | return &tbs[m_max]; |
1326 | } | |
7501267e | 1327 | |
ea041c0e FB |
1328 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1329 | ||
1330 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1331 | { | |
1332 | TranslationBlock *tb1, *tb_next, **ptb; | |
1333 | unsigned int n1; | |
1334 | ||
1335 | tb1 = tb->jmp_next[n]; | |
1336 | if (tb1 != NULL) { | |
1337 | /* find head of list */ | |
1338 | for(;;) { | |
1339 | n1 = (long)tb1 & 3; | |
1340 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1341 | if (n1 == 2) | |
1342 | break; | |
1343 | tb1 = tb1->jmp_next[n1]; | |
1344 | } | |
1345 | /* we are now sure now that tb jumps to tb1 */ | |
1346 | tb_next = tb1; | |
1347 | ||
1348 | /* remove tb from the jmp_first list */ | |
1349 | ptb = &tb_next->jmp_first; | |
1350 | for(;;) { | |
1351 | tb1 = *ptb; | |
1352 | n1 = (long)tb1 & 3; | |
1353 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1354 | if (n1 == n && tb1 == tb) | |
1355 | break; | |
1356 | ptb = &tb1->jmp_next[n1]; | |
1357 | } | |
1358 | *ptb = tb->jmp_next[n]; | |
1359 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1360 | |
ea041c0e FB |
1361 | /* suppress the jump to next tb in generated code */ |
1362 | tb_reset_jump(tb, n); | |
1363 | ||
0124311e | 1364 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1365 | tb_reset_jump_recursive(tb_next); |
1366 | } | |
1367 | } | |
1368 | ||
1369 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1370 | { | |
1371 | tb_reset_jump_recursive2(tb, 0); | |
1372 | tb_reset_jump_recursive2(tb, 1); | |
1373 | } | |
1374 | ||
1fddef4b | 1375 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1376 | #if defined(CONFIG_USER_ONLY) |
1377 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1378 | { | |
1379 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1380 | } | |
1381 | #else | |
d720b93d FB |
1382 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1383 | { | |
c227f099 | 1384 | target_phys_addr_t addr; |
9b3c35e0 | 1385 | target_ulong pd; |
c227f099 | 1386 | ram_addr_t ram_addr; |
c2f07f81 | 1387 | PhysPageDesc *p; |
d720b93d | 1388 | |
c2f07f81 PB |
1389 | addr = cpu_get_phys_page_debug(env, pc); |
1390 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1391 | if (!p) { | |
1392 | pd = IO_MEM_UNASSIGNED; | |
1393 | } else { | |
1394 | pd = p->phys_offset; | |
1395 | } | |
1396 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1397 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1398 | } |
c27004ec | 1399 | #endif |
94df27fd | 1400 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1401 | |
c527ee8f PB |
1402 | #if defined(CONFIG_USER_ONLY) |
1403 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1404 | ||
1405 | { | |
1406 | } | |
1407 | ||
1408 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1409 | int flags, CPUWatchpoint **watchpoint) | |
1410 | { | |
1411 | return -ENOSYS; | |
1412 | } | |
1413 | #else | |
6658ffb8 | 1414 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1415 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1416 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1417 | { |
b4051334 | 1418 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1419 | CPUWatchpoint *wp; |
6658ffb8 | 1420 | |
b4051334 AL |
1421 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1422 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1423 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1424 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1425 | return -EINVAL; | |
1426 | } | |
a1d1bb31 | 1427 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1428 | |
1429 | wp->vaddr = addr; | |
b4051334 | 1430 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1431 | wp->flags = flags; |
1432 | ||
2dc9f411 | 1433 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1434 | if (flags & BP_GDB) |
72cf2d4f | 1435 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1436 | else |
72cf2d4f | 1437 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1438 | |
6658ffb8 | 1439 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1440 | |
1441 | if (watchpoint) | |
1442 | *watchpoint = wp; | |
1443 | return 0; | |
6658ffb8 PB |
1444 | } |
1445 | ||
a1d1bb31 AL |
1446 | /* Remove a specific watchpoint. */ |
1447 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1448 | int flags) | |
6658ffb8 | 1449 | { |
b4051334 | 1450 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1451 | CPUWatchpoint *wp; |
6658ffb8 | 1452 | |
72cf2d4f | 1453 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1454 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1455 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1456 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1457 | return 0; |
1458 | } | |
1459 | } | |
a1d1bb31 | 1460 | return -ENOENT; |
6658ffb8 PB |
1461 | } |
1462 | ||
a1d1bb31 AL |
1463 | /* Remove a specific watchpoint by reference. */ |
1464 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1465 | { | |
72cf2d4f | 1466 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1467 | |
a1d1bb31 AL |
1468 | tlb_flush_page(env, watchpoint->vaddr); |
1469 | ||
1470 | qemu_free(watchpoint); | |
1471 | } | |
1472 | ||
1473 | /* Remove all matching watchpoints. */ | |
1474 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1475 | { | |
c0ce998e | 1476 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1477 | |
72cf2d4f | 1478 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1479 | if (wp->flags & mask) |
1480 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1481 | } |
7d03f82f | 1482 | } |
c527ee8f | 1483 | #endif |
7d03f82f | 1484 | |
a1d1bb31 AL |
1485 | /* Add a breakpoint. */ |
1486 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1487 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1488 | { |
1fddef4b | 1489 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1490 | CPUBreakpoint *bp; |
3b46e624 | 1491 | |
a1d1bb31 | 1492 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1493 | |
a1d1bb31 AL |
1494 | bp->pc = pc; |
1495 | bp->flags = flags; | |
1496 | ||
2dc9f411 | 1497 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1498 | if (flags & BP_GDB) |
72cf2d4f | 1499 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1500 | else |
72cf2d4f | 1501 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1502 | |
d720b93d | 1503 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1504 | |
1505 | if (breakpoint) | |
1506 | *breakpoint = bp; | |
4c3a88a2 FB |
1507 | return 0; |
1508 | #else | |
a1d1bb31 | 1509 | return -ENOSYS; |
4c3a88a2 FB |
1510 | #endif |
1511 | } | |
1512 | ||
a1d1bb31 AL |
1513 | /* Remove a specific breakpoint. */ |
1514 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1515 | { | |
7d03f82f | 1516 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1517 | CPUBreakpoint *bp; |
1518 | ||
72cf2d4f | 1519 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1520 | if (bp->pc == pc && bp->flags == flags) { |
1521 | cpu_breakpoint_remove_by_ref(env, bp); | |
1522 | return 0; | |
1523 | } | |
7d03f82f | 1524 | } |
a1d1bb31 AL |
1525 | return -ENOENT; |
1526 | #else | |
1527 | return -ENOSYS; | |
7d03f82f EI |
1528 | #endif |
1529 | } | |
1530 | ||
a1d1bb31 AL |
1531 | /* Remove a specific breakpoint by reference. */ |
1532 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1533 | { |
1fddef4b | 1534 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1535 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1536 | |
a1d1bb31 AL |
1537 | breakpoint_invalidate(env, breakpoint->pc); |
1538 | ||
1539 | qemu_free(breakpoint); | |
1540 | #endif | |
1541 | } | |
1542 | ||
1543 | /* Remove all matching breakpoints. */ | |
1544 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1545 | { | |
1546 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1547 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1548 | |
72cf2d4f | 1549 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1550 | if (bp->flags & mask) |
1551 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1552 | } |
4c3a88a2 FB |
1553 | #endif |
1554 | } | |
1555 | ||
c33a346e FB |
1556 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1557 | CPU loop after each instruction */ | |
1558 | void cpu_single_step(CPUState *env, int enabled) | |
1559 | { | |
1fddef4b | 1560 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1561 | if (env->singlestep_enabled != enabled) { |
1562 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1563 | if (kvm_enabled()) |
1564 | kvm_update_guest_debug(env, 0); | |
1565 | else { | |
ccbb4d44 | 1566 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1567 | /* XXX: only flush what is necessary */ |
1568 | tb_flush(env); | |
1569 | } | |
c33a346e FB |
1570 | } |
1571 | #endif | |
1572 | } | |
1573 | ||
34865134 FB |
1574 | /* enable or disable low levels log */ |
1575 | void cpu_set_log(int log_flags) | |
1576 | { | |
1577 | loglevel = log_flags; | |
1578 | if (loglevel && !logfile) { | |
11fcfab4 | 1579 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1580 | if (!logfile) { |
1581 | perror(logfilename); | |
1582 | _exit(1); | |
1583 | } | |
9fa3e853 FB |
1584 | #if !defined(CONFIG_SOFTMMU) |
1585 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1586 | { | |
b55266b5 | 1587 | static char logfile_buf[4096]; |
9fa3e853 FB |
1588 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1589 | } | |
bf65f53f FN |
1590 | #elif !defined(_WIN32) |
1591 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1592 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1593 | #endif |
e735b91c PB |
1594 | log_append = 1; |
1595 | } | |
1596 | if (!loglevel && logfile) { | |
1597 | fclose(logfile); | |
1598 | logfile = NULL; | |
34865134 FB |
1599 | } |
1600 | } | |
1601 | ||
1602 | void cpu_set_log_filename(const char *filename) | |
1603 | { | |
1604 | logfilename = strdup(filename); | |
e735b91c PB |
1605 | if (logfile) { |
1606 | fclose(logfile); | |
1607 | logfile = NULL; | |
1608 | } | |
1609 | cpu_set_log(loglevel); | |
34865134 | 1610 | } |
c33a346e | 1611 | |
3098dba0 | 1612 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1613 | { |
3098dba0 AJ |
1614 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1615 | problem and hope the cpu will stop of its own accord. For userspace | |
1616 | emulation this often isn't actually as bad as it sounds. Often | |
1617 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1618 | TranslationBlock *tb; |
c227f099 | 1619 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1620 | |
cab1b4bd | 1621 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1622 | tb = env->current_tb; |
1623 | /* if the cpu is currently executing code, we must unlink it and | |
1624 | all the potentially executing TB */ | |
f76cfe56 | 1625 | if (tb) { |
3098dba0 AJ |
1626 | env->current_tb = NULL; |
1627 | tb_reset_jump_recursive(tb); | |
be214e6c | 1628 | } |
cab1b4bd | 1629 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1630 | } |
1631 | ||
97ffbd8d | 1632 | #ifndef CONFIG_USER_ONLY |
3098dba0 | 1633 | /* mask must never be zero, except for A20 change call */ |
ec6959d0 | 1634 | static void tcg_handle_interrupt(CPUState *env, int mask) |
3098dba0 AJ |
1635 | { |
1636 | int old_mask; | |
be214e6c | 1637 | |
2e70f6ef | 1638 | old_mask = env->interrupt_request; |
68a79315 | 1639 | env->interrupt_request |= mask; |
3098dba0 | 1640 | |
8edac960 AL |
1641 | /* |
1642 | * If called from iothread context, wake the target cpu in | |
1643 | * case its halted. | |
1644 | */ | |
b7680cb6 | 1645 | if (!qemu_cpu_is_self(env)) { |
8edac960 AL |
1646 | qemu_cpu_kick(env); |
1647 | return; | |
1648 | } | |
8edac960 | 1649 | |
2e70f6ef | 1650 | if (use_icount) { |
266910c4 | 1651 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1652 | if (!can_do_io(env) |
be214e6c | 1653 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1654 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1655 | } | |
2e70f6ef | 1656 | } else { |
3098dba0 | 1657 | cpu_unlink_tb(env); |
ea041c0e FB |
1658 | } |
1659 | } | |
1660 | ||
ec6959d0 JK |
1661 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; |
1662 | ||
97ffbd8d JK |
1663 | #else /* CONFIG_USER_ONLY */ |
1664 | ||
1665 | void cpu_interrupt(CPUState *env, int mask) | |
1666 | { | |
1667 | env->interrupt_request |= mask; | |
1668 | cpu_unlink_tb(env); | |
1669 | } | |
1670 | #endif /* CONFIG_USER_ONLY */ | |
1671 | ||
b54ad049 FB |
1672 | void cpu_reset_interrupt(CPUState *env, int mask) |
1673 | { | |
1674 | env->interrupt_request &= ~mask; | |
1675 | } | |
1676 | ||
3098dba0 AJ |
1677 | void cpu_exit(CPUState *env) |
1678 | { | |
1679 | env->exit_request = 1; | |
1680 | cpu_unlink_tb(env); | |
1681 | } | |
1682 | ||
c7cd6a37 | 1683 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1684 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1685 | "show generated host assembly code for each compiled TB" }, |
1686 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1687 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1688 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1689 | "show micro ops for each compiled TB" }, |
f193c797 | 1690 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1691 | "show micro ops " |
1692 | #ifdef TARGET_I386 | |
1693 | "before eflags optimization and " | |
f193c797 | 1694 | #endif |
e01a1157 | 1695 | "after liveness analysis" }, |
f193c797 FB |
1696 | { CPU_LOG_INT, "int", |
1697 | "show interrupts/exceptions in short format" }, | |
1698 | { CPU_LOG_EXEC, "exec", | |
1699 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1700 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1701 | "show CPU state before block translation" }, |
f193c797 FB |
1702 | #ifdef TARGET_I386 |
1703 | { CPU_LOG_PCALL, "pcall", | |
1704 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1705 | { CPU_LOG_RESET, "cpu_reset", |
1706 | "show CPU state before CPU resets" }, | |
f193c797 | 1707 | #endif |
8e3a9fd2 | 1708 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1709 | { CPU_LOG_IOPORT, "ioport", |
1710 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1711 | #endif |
f193c797 FB |
1712 | { 0, NULL, NULL }, |
1713 | }; | |
1714 | ||
f6f3fbca MT |
1715 | #ifndef CONFIG_USER_ONLY |
1716 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1717 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1718 | ||
1719 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
9742bf26 | 1720 | ram_addr_t size, |
0fd542fb MT |
1721 | ram_addr_t phys_offset, |
1722 | bool log_dirty) | |
f6f3fbca MT |
1723 | { |
1724 | CPUPhysMemoryClient *client; | |
1725 | QLIST_FOREACH(client, &memory_client_list, list) { | |
0fd542fb | 1726 | client->set_memory(client, start_addr, size, phys_offset, log_dirty); |
f6f3fbca MT |
1727 | } |
1728 | } | |
1729 | ||
1730 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
9742bf26 | 1731 | target_phys_addr_t end) |
f6f3fbca MT |
1732 | { |
1733 | CPUPhysMemoryClient *client; | |
1734 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1735 | int r = client->sync_dirty_bitmap(client, start, end); | |
1736 | if (r < 0) | |
1737 | return r; | |
1738 | } | |
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | static int cpu_notify_migration_log(int enable) | |
1743 | { | |
1744 | CPUPhysMemoryClient *client; | |
1745 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1746 | int r = client->migration_log(client, enable); | |
1747 | if (r < 0) | |
1748 | return r; | |
1749 | } | |
1750 | return 0; | |
1751 | } | |
1752 | ||
2173a75f AW |
1753 | struct last_map { |
1754 | target_phys_addr_t start_addr; | |
1755 | ram_addr_t size; | |
1756 | ram_addr_t phys_offset; | |
1757 | }; | |
1758 | ||
8d4c78e7 AW |
1759 | /* The l1_phys_map provides the upper P_L1_BITs of the guest physical |
1760 | * address. Each intermediate table provides the next L2_BITs of guest | |
1761 | * physical address space. The number of levels vary based on host and | |
1762 | * guest configuration, making it efficient to build the final guest | |
1763 | * physical address by seeding the L1 offset and shifting and adding in | |
1764 | * each L2 offset as we recurse through them. */ | |
2173a75f AW |
1765 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, int level, |
1766 | void **lp, target_phys_addr_t addr, | |
1767 | struct last_map *map) | |
f6f3fbca | 1768 | { |
5cd2c5b6 | 1769 | int i; |
f6f3fbca | 1770 | |
5cd2c5b6 RH |
1771 | if (*lp == NULL) { |
1772 | return; | |
1773 | } | |
1774 | if (level == 0) { | |
1775 | PhysPageDesc *pd = *lp; | |
8d4c78e7 | 1776 | addr <<= L2_BITS + TARGET_PAGE_BITS; |
7296abac | 1777 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 | 1778 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
2173a75f AW |
1779 | target_phys_addr_t start_addr = addr | i << TARGET_PAGE_BITS; |
1780 | ||
1781 | if (map->size && | |
1782 | start_addr == map->start_addr + map->size && | |
1783 | pd[i].phys_offset == map->phys_offset + map->size) { | |
1784 | ||
1785 | map->size += TARGET_PAGE_SIZE; | |
1786 | continue; | |
1787 | } else if (map->size) { | |
1788 | client->set_memory(client, map->start_addr, | |
1789 | map->size, map->phys_offset, false); | |
1790 | } | |
1791 | ||
1792 | map->start_addr = start_addr; | |
1793 | map->size = TARGET_PAGE_SIZE; | |
1794 | map->phys_offset = pd[i].phys_offset; | |
f6f3fbca | 1795 | } |
5cd2c5b6 RH |
1796 | } |
1797 | } else { | |
1798 | void **pp = *lp; | |
7296abac | 1799 | for (i = 0; i < L2_SIZE; ++i) { |
8d4c78e7 | 1800 | phys_page_for_each_1(client, level - 1, pp + i, |
2173a75f | 1801 | (addr << L2_BITS) | i, map); |
f6f3fbca MT |
1802 | } |
1803 | } | |
1804 | } | |
1805 | ||
1806 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1807 | { | |
5cd2c5b6 | 1808 | int i; |
2173a75f AW |
1809 | struct last_map map = { }; |
1810 | ||
5cd2c5b6 RH |
1811 | for (i = 0; i < P_L1_SIZE; ++i) { |
1812 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, | |
2173a75f AW |
1813 | l1_phys_map + i, i, &map); |
1814 | } | |
1815 | if (map.size) { | |
1816 | client->set_memory(client, map.start_addr, map.size, map.phys_offset, | |
1817 | false); | |
f6f3fbca | 1818 | } |
f6f3fbca MT |
1819 | } |
1820 | ||
1821 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1822 | { | |
1823 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1824 | phys_page_for_each(client); | |
1825 | } | |
1826 | ||
1827 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1828 | { | |
1829 | QLIST_REMOVE(client, list); | |
1830 | } | |
1831 | #endif | |
1832 | ||
f193c797 FB |
1833 | static int cmp1(const char *s1, int n, const char *s2) |
1834 | { | |
1835 | if (strlen(s2) != n) | |
1836 | return 0; | |
1837 | return memcmp(s1, s2, n) == 0; | |
1838 | } | |
3b46e624 | 1839 | |
f193c797 FB |
1840 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1841 | int cpu_str_to_log_mask(const char *str) | |
1842 | { | |
c7cd6a37 | 1843 | const CPULogItem *item; |
f193c797 FB |
1844 | int mask; |
1845 | const char *p, *p1; | |
1846 | ||
1847 | p = str; | |
1848 | mask = 0; | |
1849 | for(;;) { | |
1850 | p1 = strchr(p, ','); | |
1851 | if (!p1) | |
1852 | p1 = p + strlen(p); | |
9742bf26 YT |
1853 | if(cmp1(p,p1-p,"all")) { |
1854 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1855 | mask |= item->mask; | |
1856 | } | |
1857 | } else { | |
1858 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1859 | if (cmp1(p, p1 - p, item->name)) | |
1860 | goto found; | |
1861 | } | |
1862 | return 0; | |
f193c797 | 1863 | } |
f193c797 FB |
1864 | found: |
1865 | mask |= item->mask; | |
1866 | if (*p1 != ',') | |
1867 | break; | |
1868 | p = p1 + 1; | |
1869 | } | |
1870 | return mask; | |
1871 | } | |
ea041c0e | 1872 | |
7501267e FB |
1873 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1874 | { | |
1875 | va_list ap; | |
493ae1f0 | 1876 | va_list ap2; |
7501267e FB |
1877 | |
1878 | va_start(ap, fmt); | |
493ae1f0 | 1879 | va_copy(ap2, ap); |
7501267e FB |
1880 | fprintf(stderr, "qemu: fatal: "); |
1881 | vfprintf(stderr, fmt, ap); | |
1882 | fprintf(stderr, "\n"); | |
1883 | #ifdef TARGET_I386 | |
7fe48483 FB |
1884 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1885 | #else | |
1886 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1887 | #endif |
93fcfe39 AL |
1888 | if (qemu_log_enabled()) { |
1889 | qemu_log("qemu: fatal: "); | |
1890 | qemu_log_vprintf(fmt, ap2); | |
1891 | qemu_log("\n"); | |
f9373291 | 1892 | #ifdef TARGET_I386 |
93fcfe39 | 1893 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1894 | #else |
93fcfe39 | 1895 | log_cpu_state(env, 0); |
f9373291 | 1896 | #endif |
31b1a7b4 | 1897 | qemu_log_flush(); |
93fcfe39 | 1898 | qemu_log_close(); |
924edcae | 1899 | } |
493ae1f0 | 1900 | va_end(ap2); |
f9373291 | 1901 | va_end(ap); |
fd052bf6 RV |
1902 | #if defined(CONFIG_USER_ONLY) |
1903 | { | |
1904 | struct sigaction act; | |
1905 | sigfillset(&act.sa_mask); | |
1906 | act.sa_handler = SIG_DFL; | |
1907 | sigaction(SIGABRT, &act, NULL); | |
1908 | } | |
1909 | #endif | |
7501267e FB |
1910 | abort(); |
1911 | } | |
1912 | ||
c5be9f08 TS |
1913 | CPUState *cpu_copy(CPUState *env) |
1914 | { | |
01ba9816 | 1915 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1916 | CPUState *next_cpu = new_env->next_cpu; |
1917 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1918 | #if defined(TARGET_HAS_ICE) |
1919 | CPUBreakpoint *bp; | |
1920 | CPUWatchpoint *wp; | |
1921 | #endif | |
1922 | ||
c5be9f08 | 1923 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1924 | |
1925 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1926 | new_env->next_cpu = next_cpu; |
1927 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1928 | |
1929 | /* Clone all break/watchpoints. | |
1930 | Note: Once we support ptrace with hw-debug register access, make sure | |
1931 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1932 | QTAILQ_INIT(&env->breakpoints); |
1933 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1934 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1935 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1936 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1937 | } | |
72cf2d4f | 1938 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1939 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1940 | wp->flags, NULL); | |
1941 | } | |
1942 | #endif | |
1943 | ||
c5be9f08 TS |
1944 | return new_env; |
1945 | } | |
1946 | ||
0124311e FB |
1947 | #if !defined(CONFIG_USER_ONLY) |
1948 | ||
5c751e99 EI |
1949 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1950 | { | |
1951 | unsigned int i; | |
1952 | ||
1953 | /* Discard jump cache entries for any tb which might potentially | |
1954 | overlap the flushed page. */ | |
1955 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1956 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1957 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1958 | |
1959 | i = tb_jmp_cache_hash_page(addr); | |
1960 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1961 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1962 | } |
1963 | ||
08738984 IK |
1964 | static CPUTLBEntry s_cputlb_empty_entry = { |
1965 | .addr_read = -1, | |
1966 | .addr_write = -1, | |
1967 | .addr_code = -1, | |
1968 | .addend = -1, | |
1969 | }; | |
1970 | ||
ee8b7021 FB |
1971 | /* NOTE: if flush_global is true, also flush global entries (not |
1972 | implemented yet) */ | |
1973 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1974 | { |
33417e70 | 1975 | int i; |
0124311e | 1976 | |
9fa3e853 FB |
1977 | #if defined(DEBUG_TLB) |
1978 | printf("tlb_flush:\n"); | |
1979 | #endif | |
0124311e FB |
1980 | /* must reset current TB so that interrupts cannot modify the |
1981 | links while we are modifying them */ | |
1982 | env->current_tb = NULL; | |
1983 | ||
33417e70 | 1984 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1985 | int mmu_idx; |
1986 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1987 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1988 | } |
33417e70 | 1989 | } |
9fa3e853 | 1990 | |
8a40a180 | 1991 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1992 | |
d4c430a8 PB |
1993 | env->tlb_flush_addr = -1; |
1994 | env->tlb_flush_mask = 0; | |
e3db7226 | 1995 | tlb_flush_count++; |
33417e70 FB |
1996 | } |
1997 | ||
274da6b2 | 1998 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1999 | { |
5fafdf24 | 2000 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 2001 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 2002 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 2003 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 2004 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 2005 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 2006 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 2007 | } |
61382a50 FB |
2008 | } |
2009 | ||
2e12669a | 2010 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 2011 | { |
8a40a180 | 2012 | int i; |
cfde4bd9 | 2013 | int mmu_idx; |
0124311e | 2014 | |
9fa3e853 | 2015 | #if defined(DEBUG_TLB) |
108c49b8 | 2016 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 2017 | #endif |
d4c430a8 PB |
2018 | /* Check if we need to flush due to large pages. */ |
2019 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { | |
2020 | #if defined(DEBUG_TLB) | |
2021 | printf("tlb_flush_page: forced full flush (" | |
2022 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", | |
2023 | env->tlb_flush_addr, env->tlb_flush_mask); | |
2024 | #endif | |
2025 | tlb_flush(env, 1); | |
2026 | return; | |
2027 | } | |
0124311e FB |
2028 | /* must reset current TB so that interrupts cannot modify the |
2029 | links while we are modifying them */ | |
2030 | env->current_tb = NULL; | |
61382a50 FB |
2031 | |
2032 | addr &= TARGET_PAGE_MASK; | |
2033 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
2034 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2035 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 2036 | |
5c751e99 | 2037 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
2038 | } |
2039 | ||
9fa3e853 FB |
2040 | /* update the TLBs so that writes to code in the virtual page 'addr' |
2041 | can be detected */ | |
c227f099 | 2042 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 2043 | { |
5fafdf24 | 2044 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
2045 | ram_addr + TARGET_PAGE_SIZE, |
2046 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
2047 | } |
2048 | ||
9fa3e853 | 2049 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 2050 | tested for self modifying code */ |
c227f099 | 2051 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 2052 | target_ulong vaddr) |
9fa3e853 | 2053 | { |
f7c11b53 | 2054 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
1ccde1cb FB |
2055 | } |
2056 | ||
5fafdf24 | 2057 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
2058 | unsigned long start, unsigned long length) |
2059 | { | |
2060 | unsigned long addr; | |
84b7b8e7 FB |
2061 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
2062 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 2063 | if ((addr - start) < length) { |
0f459d16 | 2064 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
2065 | } |
2066 | } | |
2067 | } | |
2068 | ||
5579c7f3 | 2069 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 2070 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 2071 | int dirty_flags) |
1ccde1cb FB |
2072 | { |
2073 | CPUState *env; | |
4f2ac237 | 2074 | unsigned long length, start1; |
f7c11b53 | 2075 | int i; |
1ccde1cb FB |
2076 | |
2077 | start &= TARGET_PAGE_MASK; | |
2078 | end = TARGET_PAGE_ALIGN(end); | |
2079 | ||
2080 | length = end - start; | |
2081 | if (length == 0) | |
2082 | return; | |
f7c11b53 | 2083 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
f23db169 | 2084 | |
1ccde1cb FB |
2085 | /* we modify the TLB cache so that the dirty bit will be set again |
2086 | when accessing the range */ | |
b2e0a138 | 2087 | start1 = (unsigned long)qemu_safe_ram_ptr(start); |
5579c7f3 PB |
2088 | /* Chek that we don't span multiple blocks - this breaks the |
2089 | address comparisons below. */ | |
b2e0a138 | 2090 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 |
5579c7f3 PB |
2091 | != (end - 1) - start) { |
2092 | abort(); | |
2093 | } | |
2094 | ||
6a00d601 | 2095 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
2096 | int mmu_idx; |
2097 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2098 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2099 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2100 | start1, length); | |
2101 | } | |
6a00d601 | 2102 | } |
1ccde1cb FB |
2103 | } |
2104 | ||
74576198 AL |
2105 | int cpu_physical_memory_set_dirty_tracking(int enable) |
2106 | { | |
f6f3fbca | 2107 | int ret = 0; |
74576198 | 2108 | in_migration = enable; |
f6f3fbca MT |
2109 | ret = cpu_notify_migration_log(!!enable); |
2110 | return ret; | |
74576198 AL |
2111 | } |
2112 | ||
2113 | int cpu_physical_memory_get_dirty_tracking(void) | |
2114 | { | |
2115 | return in_migration; | |
2116 | } | |
2117 | ||
c227f099 AL |
2118 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
2119 | target_phys_addr_t end_addr) | |
2bec46dc | 2120 | { |
7b8f3b78 | 2121 | int ret; |
151f7749 | 2122 | |
f6f3fbca | 2123 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
151f7749 | 2124 | return ret; |
2bec46dc AL |
2125 | } |
2126 | ||
e5896b12 AP |
2127 | int cpu_physical_log_start(target_phys_addr_t start_addr, |
2128 | ram_addr_t size) | |
2129 | { | |
2130 | CPUPhysMemoryClient *client; | |
2131 | QLIST_FOREACH(client, &memory_client_list, list) { | |
2132 | if (client->log_start) { | |
2133 | int r = client->log_start(client, start_addr, size); | |
2134 | if (r < 0) { | |
2135 | return r; | |
2136 | } | |
2137 | } | |
2138 | } | |
2139 | return 0; | |
2140 | } | |
2141 | ||
2142 | int cpu_physical_log_stop(target_phys_addr_t start_addr, | |
2143 | ram_addr_t size) | |
2144 | { | |
2145 | CPUPhysMemoryClient *client; | |
2146 | QLIST_FOREACH(client, &memory_client_list, list) { | |
2147 | if (client->log_stop) { | |
2148 | int r = client->log_stop(client, start_addr, size); | |
2149 | if (r < 0) { | |
2150 | return r; | |
2151 | } | |
2152 | } | |
2153 | } | |
2154 | return 0; | |
2155 | } | |
2156 | ||
3a7d929e FB |
2157 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2158 | { | |
c227f099 | 2159 | ram_addr_t ram_addr; |
5579c7f3 | 2160 | void *p; |
3a7d929e | 2161 | |
84b7b8e7 | 2162 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
2163 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2164 | + tlb_entry->addend); | |
e890261f | 2165 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
3a7d929e | 2166 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2167 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2168 | } |
2169 | } | |
2170 | } | |
2171 | ||
2172 | /* update the TLB according to the current state of the dirty bits */ | |
2173 | void cpu_tlb_update_dirty(CPUState *env) | |
2174 | { | |
2175 | int i; | |
cfde4bd9 IY |
2176 | int mmu_idx; |
2177 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2178 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2179 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2180 | } | |
3a7d929e FB |
2181 | } |
2182 | ||
0f459d16 | 2183 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2184 | { |
0f459d16 PB |
2185 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2186 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2187 | } |
2188 | ||
0f459d16 PB |
2189 | /* update the TLB corresponding to virtual page vaddr |
2190 | so that it is no longer dirty */ | |
2191 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2192 | { |
1ccde1cb | 2193 | int i; |
cfde4bd9 | 2194 | int mmu_idx; |
1ccde1cb | 2195 | |
0f459d16 | 2196 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2197 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2198 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2199 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2200 | } |
2201 | ||
d4c430a8 PB |
2202 | /* Our TLB does not support large pages, so remember the area covered by |
2203 | large pages and trigger a full TLB flush if these are invalidated. */ | |
2204 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, | |
2205 | target_ulong size) | |
2206 | { | |
2207 | target_ulong mask = ~(size - 1); | |
2208 | ||
2209 | if (env->tlb_flush_addr == (target_ulong)-1) { | |
2210 | env->tlb_flush_addr = vaddr & mask; | |
2211 | env->tlb_flush_mask = mask; | |
2212 | return; | |
2213 | } | |
2214 | /* Extend the existing region to include the new page. | |
2215 | This is a compromise between unnecessary flushes and the cost | |
2216 | of maintaining a full variable size TLB. */ | |
2217 | mask &= env->tlb_flush_mask; | |
2218 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { | |
2219 | mask <<= 1; | |
2220 | } | |
2221 | env->tlb_flush_addr &= mask; | |
2222 | env->tlb_flush_mask = mask; | |
2223 | } | |
2224 | ||
2225 | /* Add a new TLB entry. At most one entry for a given virtual address | |
2226 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | |
2227 | supplied size is only used by tlb_flush_page. */ | |
2228 | void tlb_set_page(CPUState *env, target_ulong vaddr, | |
2229 | target_phys_addr_t paddr, int prot, | |
2230 | int mmu_idx, target_ulong size) | |
9fa3e853 | 2231 | { |
92e873b9 | 2232 | PhysPageDesc *p; |
4f2ac237 | 2233 | unsigned long pd; |
9fa3e853 | 2234 | unsigned int index; |
4f2ac237 | 2235 | target_ulong address; |
0f459d16 | 2236 | target_ulong code_address; |
355b1943 | 2237 | unsigned long addend; |
84b7b8e7 | 2238 | CPUTLBEntry *te; |
a1d1bb31 | 2239 | CPUWatchpoint *wp; |
c227f099 | 2240 | target_phys_addr_t iotlb; |
9fa3e853 | 2241 | |
d4c430a8 PB |
2242 | assert(size >= TARGET_PAGE_SIZE); |
2243 | if (size != TARGET_PAGE_SIZE) { | |
2244 | tlb_add_large_page(env, vaddr, size); | |
2245 | } | |
92e873b9 | 2246 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2247 | if (!p) { |
2248 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2249 | } else { |
2250 | pd = p->phys_offset; | |
9fa3e853 FB |
2251 | } |
2252 | #if defined(DEBUG_TLB) | |
7fd3f494 SW |
2253 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
2254 | " prot=%x idx=%d pd=0x%08lx\n", | |
2255 | vaddr, paddr, prot, mmu_idx, pd); | |
9fa3e853 FB |
2256 | #endif |
2257 | ||
0f459d16 PB |
2258 | address = vaddr; |
2259 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2260 | /* IO memory case (romd handled later) */ | |
2261 | address |= TLB_MMIO; | |
2262 | } | |
5579c7f3 | 2263 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2264 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2265 | /* Normal RAM. */ | |
2266 | iotlb = pd & TARGET_PAGE_MASK; | |
2267 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2268 | iotlb |= IO_MEM_NOTDIRTY; | |
2269 | else | |
2270 | iotlb |= IO_MEM_ROM; | |
2271 | } else { | |
ccbb4d44 | 2272 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2273 | It would be nice to pass an offset from the base address |
2274 | of that region. This would avoid having to special case RAM, | |
2275 | and avoid full address decoding in every device. | |
2276 | We can't use the high bits of pd for this because | |
2277 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2278 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2279 | if (p) { | |
8da3ff18 PB |
2280 | iotlb += p->region_offset; |
2281 | } else { | |
2282 | iotlb += paddr; | |
2283 | } | |
0f459d16 PB |
2284 | } |
2285 | ||
2286 | code_address = address; | |
2287 | /* Make accesses to pages with watchpoints go via the | |
2288 | watchpoint trap routines. */ | |
72cf2d4f | 2289 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2290 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
bf298f83 JK |
2291 | /* Avoid trapping reads of pages with a write breakpoint. */ |
2292 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
2293 | iotlb = io_mem_watch + paddr; | |
2294 | address |= TLB_MMIO; | |
2295 | break; | |
2296 | } | |
6658ffb8 | 2297 | } |
0f459d16 | 2298 | } |
d79acba4 | 2299 | |
0f459d16 PB |
2300 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2301 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2302 | te = &env->tlb_table[mmu_idx][index]; | |
2303 | te->addend = addend - vaddr; | |
2304 | if (prot & PAGE_READ) { | |
2305 | te->addr_read = address; | |
2306 | } else { | |
2307 | te->addr_read = -1; | |
2308 | } | |
5c751e99 | 2309 | |
0f459d16 PB |
2310 | if (prot & PAGE_EXEC) { |
2311 | te->addr_code = code_address; | |
2312 | } else { | |
2313 | te->addr_code = -1; | |
2314 | } | |
2315 | if (prot & PAGE_WRITE) { | |
2316 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2317 | (pd & IO_MEM_ROMD)) { | |
2318 | /* Write access calls the I/O callback. */ | |
2319 | te->addr_write = address | TLB_MMIO; | |
2320 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2321 | !cpu_physical_memory_is_dirty(pd)) { | |
2322 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2323 | } else { |
0f459d16 | 2324 | te->addr_write = address; |
9fa3e853 | 2325 | } |
0f459d16 PB |
2326 | } else { |
2327 | te->addr_write = -1; | |
9fa3e853 | 2328 | } |
9fa3e853 FB |
2329 | } |
2330 | ||
0124311e FB |
2331 | #else |
2332 | ||
ee8b7021 | 2333 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2334 | { |
2335 | } | |
2336 | ||
2e12669a | 2337 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2338 | { |
2339 | } | |
2340 | ||
edf8e2af MW |
2341 | /* |
2342 | * Walks guest process memory "regions" one by one | |
2343 | * and calls callback function 'fn' for each region. | |
2344 | */ | |
5cd2c5b6 RH |
2345 | |
2346 | struct walk_memory_regions_data | |
2347 | { | |
2348 | walk_memory_regions_fn fn; | |
2349 | void *priv; | |
2350 | unsigned long start; | |
2351 | int prot; | |
2352 | }; | |
2353 | ||
2354 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
b480d9b7 | 2355 | abi_ulong end, int new_prot) |
5cd2c5b6 RH |
2356 | { |
2357 | if (data->start != -1ul) { | |
2358 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2359 | if (rc != 0) { | |
2360 | return rc; | |
2361 | } | |
2362 | } | |
2363 | ||
2364 | data->start = (new_prot ? end : -1ul); | |
2365 | data->prot = new_prot; | |
2366 | ||
2367 | return 0; | |
2368 | } | |
2369 | ||
2370 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
b480d9b7 | 2371 | abi_ulong base, int level, void **lp) |
5cd2c5b6 | 2372 | { |
b480d9b7 | 2373 | abi_ulong pa; |
5cd2c5b6 RH |
2374 | int i, rc; |
2375 | ||
2376 | if (*lp == NULL) { | |
2377 | return walk_memory_regions_end(data, base, 0); | |
2378 | } | |
2379 | ||
2380 | if (level == 0) { | |
2381 | PageDesc *pd = *lp; | |
7296abac | 2382 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
2383 | int prot = pd[i].flags; |
2384 | ||
2385 | pa = base | (i << TARGET_PAGE_BITS); | |
2386 | if (prot != data->prot) { | |
2387 | rc = walk_memory_regions_end(data, pa, prot); | |
2388 | if (rc != 0) { | |
2389 | return rc; | |
9fa3e853 | 2390 | } |
9fa3e853 | 2391 | } |
5cd2c5b6 RH |
2392 | } |
2393 | } else { | |
2394 | void **pp = *lp; | |
7296abac | 2395 | for (i = 0; i < L2_SIZE; ++i) { |
b480d9b7 PB |
2396 | pa = base | ((abi_ulong)i << |
2397 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
5cd2c5b6 RH |
2398 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
2399 | if (rc != 0) { | |
2400 | return rc; | |
2401 | } | |
2402 | } | |
2403 | } | |
2404 | ||
2405 | return 0; | |
2406 | } | |
2407 | ||
2408 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2409 | { | |
2410 | struct walk_memory_regions_data data; | |
2411 | unsigned long i; | |
2412 | ||
2413 | data.fn = fn; | |
2414 | data.priv = priv; | |
2415 | data.start = -1ul; | |
2416 | data.prot = 0; | |
2417 | ||
2418 | for (i = 0; i < V_L1_SIZE; i++) { | |
b480d9b7 | 2419 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
5cd2c5b6 RH |
2420 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
2421 | if (rc != 0) { | |
2422 | return rc; | |
9fa3e853 | 2423 | } |
33417e70 | 2424 | } |
5cd2c5b6 RH |
2425 | |
2426 | return walk_memory_regions_end(&data, 0, 0); | |
edf8e2af MW |
2427 | } |
2428 | ||
b480d9b7 PB |
2429 | static int dump_region(void *priv, abi_ulong start, |
2430 | abi_ulong end, unsigned long prot) | |
edf8e2af MW |
2431 | { |
2432 | FILE *f = (FILE *)priv; | |
2433 | ||
b480d9b7 PB |
2434 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
2435 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
edf8e2af MW |
2436 | start, end, end - start, |
2437 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2438 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2439 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2440 | ||
2441 | return (0); | |
2442 | } | |
2443 | ||
2444 | /* dump memory mappings */ | |
2445 | void page_dump(FILE *f) | |
2446 | { | |
2447 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2448 | "start", "end", "size", "prot"); | |
2449 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2450 | } |
2451 | ||
53a5960a | 2452 | int page_get_flags(target_ulong address) |
33417e70 | 2453 | { |
9fa3e853 FB |
2454 | PageDesc *p; |
2455 | ||
2456 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2457 | if (!p) |
9fa3e853 FB |
2458 | return 0; |
2459 | return p->flags; | |
2460 | } | |
2461 | ||
376a7909 RH |
2462 | /* Modify the flags of a page and invalidate the code if necessary. |
2463 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2464 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
53a5960a | 2465 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 | 2466 | { |
376a7909 RH |
2467 | target_ulong addr, len; |
2468 | ||
2469 | /* This function should never be called with addresses outside the | |
2470 | guest address space. If this assert fires, it probably indicates | |
2471 | a missing call to h2g_valid. */ | |
b480d9b7 PB |
2472 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2473 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2474 | #endif |
2475 | assert(start < end); | |
9fa3e853 FB |
2476 | |
2477 | start = start & TARGET_PAGE_MASK; | |
2478 | end = TARGET_PAGE_ALIGN(end); | |
376a7909 RH |
2479 | |
2480 | if (flags & PAGE_WRITE) { | |
9fa3e853 | 2481 | flags |= PAGE_WRITE_ORG; |
376a7909 RH |
2482 | } |
2483 | ||
2484 | for (addr = start, len = end - start; | |
2485 | len != 0; | |
2486 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2487 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2488 | ||
2489 | /* If the write protection bit is set, then we invalidate | |
2490 | the code inside. */ | |
5fafdf24 | 2491 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2492 | (flags & PAGE_WRITE) && |
2493 | p->first_tb) { | |
d720b93d | 2494 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2495 | } |
2496 | p->flags = flags; | |
2497 | } | |
33417e70 FB |
2498 | } |
2499 | ||
3d97b40b TS |
2500 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2501 | { | |
2502 | PageDesc *p; | |
2503 | target_ulong end; | |
2504 | target_ulong addr; | |
2505 | ||
376a7909 RH |
2506 | /* This function should never be called with addresses outside the |
2507 | guest address space. If this assert fires, it probably indicates | |
2508 | a missing call to h2g_valid. */ | |
338e9e6c BS |
2509 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2510 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2511 | #endif |
2512 | ||
3e0650a9 RH |
2513 | if (len == 0) { |
2514 | return 0; | |
2515 | } | |
376a7909 RH |
2516 | if (start + len - 1 < start) { |
2517 | /* We've wrapped around. */ | |
55f280c9 | 2518 | return -1; |
376a7909 | 2519 | } |
55f280c9 | 2520 | |
3d97b40b TS |
2521 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2522 | start = start & TARGET_PAGE_MASK; | |
2523 | ||
376a7909 RH |
2524 | for (addr = start, len = end - start; |
2525 | len != 0; | |
2526 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
3d97b40b TS |
2527 | p = page_find(addr >> TARGET_PAGE_BITS); |
2528 | if( !p ) | |
2529 | return -1; | |
2530 | if( !(p->flags & PAGE_VALID) ) | |
2531 | return -1; | |
2532 | ||
dae3270c | 2533 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2534 | return -1; |
dae3270c FB |
2535 | if (flags & PAGE_WRITE) { |
2536 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2537 | return -1; | |
2538 | /* unprotect the page if it was put read-only because it | |
2539 | contains translated code */ | |
2540 | if (!(p->flags & PAGE_WRITE)) { | |
2541 | if (!page_unprotect(addr, 0, NULL)) | |
2542 | return -1; | |
2543 | } | |
2544 | return 0; | |
2545 | } | |
3d97b40b TS |
2546 | } |
2547 | return 0; | |
2548 | } | |
2549 | ||
9fa3e853 | 2550 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2551 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2552 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 | 2553 | { |
45d679d6 AJ |
2554 | unsigned int prot; |
2555 | PageDesc *p; | |
53a5960a | 2556 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2557 | |
c8a706fe PB |
2558 | /* Technically this isn't safe inside a signal handler. However we |
2559 | know this only ever happens in a synchronous SEGV handler, so in | |
2560 | practice it seems to be ok. */ | |
2561 | mmap_lock(); | |
2562 | ||
45d679d6 AJ |
2563 | p = page_find(address >> TARGET_PAGE_BITS); |
2564 | if (!p) { | |
c8a706fe | 2565 | mmap_unlock(); |
9fa3e853 | 2566 | return 0; |
c8a706fe | 2567 | } |
45d679d6 | 2568 | |
9fa3e853 FB |
2569 | /* if the page was really writable, then we change its |
2570 | protection back to writable */ | |
45d679d6 AJ |
2571 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
2572 | host_start = address & qemu_host_page_mask; | |
2573 | host_end = host_start + qemu_host_page_size; | |
2574 | ||
2575 | prot = 0; | |
2576 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
2577 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2578 | p->flags |= PAGE_WRITE; | |
2579 | prot |= p->flags; | |
2580 | ||
9fa3e853 FB |
2581 | /* and since the content will be modified, we must invalidate |
2582 | the corresponding translated code. */ | |
45d679d6 | 2583 | tb_invalidate_phys_page(addr, pc, puc); |
9fa3e853 | 2584 | #ifdef DEBUG_TB_CHECK |
45d679d6 | 2585 | tb_invalidate_check(addr); |
9fa3e853 | 2586 | #endif |
9fa3e853 | 2587 | } |
45d679d6 AJ |
2588 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
2589 | prot & PAGE_BITS); | |
2590 | ||
2591 | mmap_unlock(); | |
2592 | return 1; | |
9fa3e853 | 2593 | } |
c8a706fe | 2594 | mmap_unlock(); |
9fa3e853 FB |
2595 | return 0; |
2596 | } | |
2597 | ||
6a00d601 FB |
2598 | static inline void tlb_set_dirty(CPUState *env, |
2599 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2600 | { |
2601 | } | |
9fa3e853 FB |
2602 | #endif /* defined(CONFIG_USER_ONLY) */ |
2603 | ||
e2eef170 | 2604 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2605 | |
c04b2b78 PB |
2606 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2607 | typedef struct subpage_t { | |
2608 | target_phys_addr_t base; | |
f6405247 RH |
2609 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
2610 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; | |
c04b2b78 PB |
2611 | } subpage_t; |
2612 | ||
c227f099 AL |
2613 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2614 | ram_addr_t memory, ram_addr_t region_offset); | |
f6405247 RH |
2615 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2616 | ram_addr_t orig_memory, | |
2617 | ram_addr_t region_offset); | |
db7b5426 BS |
2618 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2619 | need_subpage) \ | |
2620 | do { \ | |
2621 | if (addr > start_addr) \ | |
2622 | start_addr2 = 0; \ | |
2623 | else { \ | |
2624 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2625 | if (start_addr2 > 0) \ | |
2626 | need_subpage = 1; \ | |
2627 | } \ | |
2628 | \ | |
49e9fba2 | 2629 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2630 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2631 | else { \ | |
2632 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2633 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2634 | need_subpage = 1; \ | |
2635 | } \ | |
2636 | } while (0) | |
2637 | ||
8f2498f9 MT |
2638 | /* register physical memory. |
2639 | For RAM, 'size' must be a multiple of the target page size. | |
2640 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2641 | io memory page. The address used when calling the IO function is |
2642 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2643 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2644 | before calculating this offset. This should not be a problem unless |
2645 | the low bits of start_addr and region_offset differ. */ | |
0fd542fb | 2646 | void cpu_register_physical_memory_log(target_phys_addr_t start_addr, |
c227f099 AL |
2647 | ram_addr_t size, |
2648 | ram_addr_t phys_offset, | |
0fd542fb MT |
2649 | ram_addr_t region_offset, |
2650 | bool log_dirty) | |
33417e70 | 2651 | { |
c227f099 | 2652 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2653 | PhysPageDesc *p; |
9d42037b | 2654 | CPUState *env; |
c227f099 | 2655 | ram_addr_t orig_size = size; |
f6405247 | 2656 | subpage_t *subpage; |
33417e70 | 2657 | |
3b8e6a2d | 2658 | assert(size); |
0fd542fb | 2659 | cpu_notify_set_memory(start_addr, size, phys_offset, log_dirty); |
f6f3fbca | 2660 | |
67c4d23c PB |
2661 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2662 | region_offset = start_addr; | |
2663 | } | |
8da3ff18 | 2664 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2665 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2666 | end_addr = start_addr + (target_phys_addr_t)size; |
3b8e6a2d EI |
2667 | |
2668 | addr = start_addr; | |
2669 | do { | |
db7b5426 BS |
2670 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2671 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2672 | ram_addr_t orig_memory = p->phys_offset; |
2673 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2674 | int need_subpage = 0; |
2675 | ||
2676 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2677 | need_subpage); | |
f6405247 | 2678 | if (need_subpage) { |
db7b5426 BS |
2679 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2680 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2681 | &p->phys_offset, orig_memory, |
2682 | p->region_offset); | |
db7b5426 BS |
2683 | } else { |
2684 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2685 | >> IO_MEM_SHIFT]; | |
2686 | } | |
8da3ff18 PB |
2687 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2688 | region_offset); | |
2689 | p->region_offset = 0; | |
db7b5426 BS |
2690 | } else { |
2691 | p->phys_offset = phys_offset; | |
2692 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2693 | (phys_offset & IO_MEM_ROMD)) | |
2694 | phys_offset += TARGET_PAGE_SIZE; | |
2695 | } | |
2696 | } else { | |
2697 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2698 | p->phys_offset = phys_offset; | |
8da3ff18 | 2699 | p->region_offset = region_offset; |
db7b5426 | 2700 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2701 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2702 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2703 | } else { |
c227f099 | 2704 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2705 | int need_subpage = 0; |
2706 | ||
2707 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2708 | end_addr2, need_subpage); | |
2709 | ||
f6405247 | 2710 | if (need_subpage) { |
db7b5426 | 2711 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2712 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2713 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2714 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2715 | phys_offset, region_offset); |
2716 | p->region_offset = 0; | |
db7b5426 BS |
2717 | } |
2718 | } | |
2719 | } | |
8da3ff18 | 2720 | region_offset += TARGET_PAGE_SIZE; |
3b8e6a2d EI |
2721 | addr += TARGET_PAGE_SIZE; |
2722 | } while (addr != end_addr); | |
3b46e624 | 2723 | |
9d42037b FB |
2724 | /* since each CPU stores ram addresses in its TLB cache, we must |
2725 | reset the modified entries */ | |
2726 | /* XXX: slow ! */ | |
2727 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2728 | tlb_flush(env, 1); | |
2729 | } | |
33417e70 FB |
2730 | } |
2731 | ||
ba863458 | 2732 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2733 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2734 | { |
2735 | PhysPageDesc *p; | |
2736 | ||
2737 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2738 | if (!p) | |
2739 | return IO_MEM_UNASSIGNED; | |
2740 | return p->phys_offset; | |
2741 | } | |
2742 | ||
c227f099 | 2743 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2744 | { |
2745 | if (kvm_enabled()) | |
2746 | kvm_coalesce_mmio_region(addr, size); | |
2747 | } | |
2748 | ||
c227f099 | 2749 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2750 | { |
2751 | if (kvm_enabled()) | |
2752 | kvm_uncoalesce_mmio_region(addr, size); | |
2753 | } | |
2754 | ||
62a2744c SY |
2755 | void qemu_flush_coalesced_mmio_buffer(void) |
2756 | { | |
2757 | if (kvm_enabled()) | |
2758 | kvm_flush_coalesced_mmio_buffer(); | |
2759 | } | |
2760 | ||
c902760f MT |
2761 | #if defined(__linux__) && !defined(TARGET_S390X) |
2762 | ||
2763 | #include <sys/vfs.h> | |
2764 | ||
2765 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2766 | ||
2767 | static long gethugepagesize(const char *path) | |
2768 | { | |
2769 | struct statfs fs; | |
2770 | int ret; | |
2771 | ||
2772 | do { | |
9742bf26 | 2773 | ret = statfs(path, &fs); |
c902760f MT |
2774 | } while (ret != 0 && errno == EINTR); |
2775 | ||
2776 | if (ret != 0) { | |
9742bf26 YT |
2777 | perror(path); |
2778 | return 0; | |
c902760f MT |
2779 | } |
2780 | ||
2781 | if (fs.f_type != HUGETLBFS_MAGIC) | |
9742bf26 | 2782 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
c902760f MT |
2783 | |
2784 | return fs.f_bsize; | |
2785 | } | |
2786 | ||
04b16653 AW |
2787 | static void *file_ram_alloc(RAMBlock *block, |
2788 | ram_addr_t memory, | |
2789 | const char *path) | |
c902760f MT |
2790 | { |
2791 | char *filename; | |
2792 | void *area; | |
2793 | int fd; | |
2794 | #ifdef MAP_POPULATE | |
2795 | int flags; | |
2796 | #endif | |
2797 | unsigned long hpagesize; | |
2798 | ||
2799 | hpagesize = gethugepagesize(path); | |
2800 | if (!hpagesize) { | |
9742bf26 | 2801 | return NULL; |
c902760f MT |
2802 | } |
2803 | ||
2804 | if (memory < hpagesize) { | |
2805 | return NULL; | |
2806 | } | |
2807 | ||
2808 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2809 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2810 | return NULL; | |
2811 | } | |
2812 | ||
2813 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
9742bf26 | 2814 | return NULL; |
c902760f MT |
2815 | } |
2816 | ||
2817 | fd = mkstemp(filename); | |
2818 | if (fd < 0) { | |
9742bf26 YT |
2819 | perror("unable to create backing store for hugepages"); |
2820 | free(filename); | |
2821 | return NULL; | |
c902760f MT |
2822 | } |
2823 | unlink(filename); | |
2824 | free(filename); | |
2825 | ||
2826 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2827 | ||
2828 | /* | |
2829 | * ftruncate is not supported by hugetlbfs in older | |
2830 | * hosts, so don't bother bailing out on errors. | |
2831 | * If anything goes wrong with it under other filesystems, | |
2832 | * mmap will fail. | |
2833 | */ | |
2834 | if (ftruncate(fd, memory)) | |
9742bf26 | 2835 | perror("ftruncate"); |
c902760f MT |
2836 | |
2837 | #ifdef MAP_POPULATE | |
2838 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2839 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2840 | * to sidestep this quirk. | |
2841 | */ | |
2842 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2843 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2844 | #else | |
2845 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2846 | #endif | |
2847 | if (area == MAP_FAILED) { | |
9742bf26 YT |
2848 | perror("file_ram_alloc: can't mmap RAM pages"); |
2849 | close(fd); | |
2850 | return (NULL); | |
c902760f | 2851 | } |
04b16653 | 2852 | block->fd = fd; |
c902760f MT |
2853 | return area; |
2854 | } | |
2855 | #endif | |
2856 | ||
d17b5288 | 2857 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
2858 | { |
2859 | RAMBlock *block, *next_block; | |
09d7ae90 | 2860 | ram_addr_t offset = 0, mingap = ULONG_MAX; |
04b16653 AW |
2861 | |
2862 | if (QLIST_EMPTY(&ram_list.blocks)) | |
2863 | return 0; | |
2864 | ||
2865 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2866 | ram_addr_t end, next = ULONG_MAX; | |
2867 | ||
2868 | end = block->offset + block->length; | |
2869 | ||
2870 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { | |
2871 | if (next_block->offset >= end) { | |
2872 | next = MIN(next, next_block->offset); | |
2873 | } | |
2874 | } | |
2875 | if (next - end >= size && next - end < mingap) { | |
2876 | offset = end; | |
2877 | mingap = next - end; | |
2878 | } | |
2879 | } | |
2880 | return offset; | |
2881 | } | |
2882 | ||
2883 | static ram_addr_t last_ram_offset(void) | |
d17b5288 AW |
2884 | { |
2885 | RAMBlock *block; | |
2886 | ram_addr_t last = 0; | |
2887 | ||
2888 | QLIST_FOREACH(block, &ram_list.blocks, next) | |
2889 | last = MAX(last, block->offset + block->length); | |
2890 | ||
2891 | return last; | |
2892 | } | |
2893 | ||
84b89d78 | 2894 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
6977dfe6 | 2895 | ram_addr_t size, void *host) |
84b89d78 CM |
2896 | { |
2897 | RAMBlock *new_block, *block; | |
2898 | ||
2899 | size = TARGET_PAGE_ALIGN(size); | |
2900 | new_block = qemu_mallocz(sizeof(*new_block)); | |
2901 | ||
2902 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { | |
2903 | char *id = dev->parent_bus->info->get_dev_path(dev); | |
2904 | if (id) { | |
2905 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
2906 | qemu_free(id); | |
2907 | } | |
2908 | } | |
2909 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2910 | ||
2911 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2912 | if (!strcmp(block->idstr, new_block->idstr)) { | |
2913 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", | |
2914 | new_block->idstr); | |
2915 | abort(); | |
2916 | } | |
2917 | } | |
2918 | ||
6977dfe6 YT |
2919 | if (host) { |
2920 | new_block->host = host; | |
cd19cfa2 | 2921 | new_block->flags |= RAM_PREALLOC_MASK; |
6977dfe6 YT |
2922 | } else { |
2923 | if (mem_path) { | |
c902760f | 2924 | #if defined (__linux__) && !defined(TARGET_S390X) |
6977dfe6 YT |
2925 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
2926 | if (!new_block->host) { | |
2927 | new_block->host = qemu_vmalloc(size); | |
e78815a5 | 2928 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2929 | } |
c902760f | 2930 | #else |
6977dfe6 YT |
2931 | fprintf(stderr, "-mem-path option unsupported\n"); |
2932 | exit(1); | |
c902760f | 2933 | #endif |
6977dfe6 | 2934 | } else { |
6b02494d | 2935 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
6977dfe6 YT |
2936 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ |
2937 | new_block->host = mmap((void*)0x1000000, size, | |
2938 | PROT_EXEC|PROT_READ|PROT_WRITE, | |
2939 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
6b02494d | 2940 | #else |
6977dfe6 | 2941 | new_block->host = qemu_vmalloc(size); |
6b02494d | 2942 | #endif |
e78815a5 | 2943 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2944 | } |
c902760f | 2945 | } |
6977dfe6 | 2946 | |
d17b5288 | 2947 | new_block->offset = find_ram_offset(size); |
94a6b54f PB |
2948 | new_block->length = size; |
2949 | ||
f471a17e | 2950 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
94a6b54f | 2951 | |
f471a17e | 2952 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, |
04b16653 | 2953 | last_ram_offset() >> TARGET_PAGE_BITS); |
d17b5288 | 2954 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
94a6b54f PB |
2955 | 0xff, size >> TARGET_PAGE_BITS); |
2956 | ||
6f0437e8 JK |
2957 | if (kvm_enabled()) |
2958 | kvm_setup_guest_memory(new_block->host, size); | |
2959 | ||
94a6b54f PB |
2960 | return new_block->offset; |
2961 | } | |
e9a1ab19 | 2962 | |
6977dfe6 YT |
2963 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) |
2964 | { | |
2965 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); | |
2966 | } | |
2967 | ||
c227f099 | 2968 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2969 | { |
04b16653 AW |
2970 | RAMBlock *block; |
2971 | ||
2972 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2973 | if (addr == block->offset) { | |
2974 | QLIST_REMOVE(block, next); | |
cd19cfa2 HY |
2975 | if (block->flags & RAM_PREALLOC_MASK) { |
2976 | ; | |
2977 | } else if (mem_path) { | |
04b16653 AW |
2978 | #if defined (__linux__) && !defined(TARGET_S390X) |
2979 | if (block->fd) { | |
2980 | munmap(block->host, block->length); | |
2981 | close(block->fd); | |
2982 | } else { | |
2983 | qemu_vfree(block->host); | |
2984 | } | |
fd28aa13 JK |
2985 | #else |
2986 | abort(); | |
04b16653 AW |
2987 | #endif |
2988 | } else { | |
2989 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
2990 | munmap(block->host, block->length); | |
2991 | #else | |
2992 | qemu_vfree(block->host); | |
2993 | #endif | |
2994 | } | |
2995 | qemu_free(block); | |
2996 | return; | |
2997 | } | |
2998 | } | |
2999 | ||
e9a1ab19 FB |
3000 | } |
3001 | ||
cd19cfa2 HY |
3002 | #ifndef _WIN32 |
3003 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
3004 | { | |
3005 | RAMBlock *block; | |
3006 | ram_addr_t offset; | |
3007 | int flags; | |
3008 | void *area, *vaddr; | |
3009 | ||
3010 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3011 | offset = addr - block->offset; | |
3012 | if (offset < block->length) { | |
3013 | vaddr = block->host + offset; | |
3014 | if (block->flags & RAM_PREALLOC_MASK) { | |
3015 | ; | |
3016 | } else { | |
3017 | flags = MAP_FIXED; | |
3018 | munmap(vaddr, length); | |
3019 | if (mem_path) { | |
3020 | #if defined(__linux__) && !defined(TARGET_S390X) | |
3021 | if (block->fd) { | |
3022 | #ifdef MAP_POPULATE | |
3023 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : | |
3024 | MAP_PRIVATE; | |
3025 | #else | |
3026 | flags |= MAP_PRIVATE; | |
3027 | #endif | |
3028 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3029 | flags, block->fd, offset); | |
3030 | } else { | |
3031 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3032 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3033 | flags, -1, 0); | |
3034 | } | |
fd28aa13 JK |
3035 | #else |
3036 | abort(); | |
cd19cfa2 HY |
3037 | #endif |
3038 | } else { | |
3039 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
3040 | flags |= MAP_SHARED | MAP_ANONYMOUS; | |
3041 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, | |
3042 | flags, -1, 0); | |
3043 | #else | |
3044 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3045 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3046 | flags, -1, 0); | |
3047 | #endif | |
3048 | } | |
3049 | if (area != vaddr) { | |
3050 | fprintf(stderr, "Could not remap addr: %lx@%lx\n", | |
3051 | length, addr); | |
3052 | exit(1); | |
3053 | } | |
3054 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); | |
3055 | } | |
3056 | return; | |
3057 | } | |
3058 | } | |
3059 | } | |
3060 | #endif /* !_WIN32 */ | |
3061 | ||
dc828ca1 | 3062 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
3063 | With the exception of the softmmu code in this file, this should |
3064 | only be used for local memory (e.g. video ram) that the device owns, | |
3065 | and knows it isn't going to access beyond the end of the block. | |
3066 | ||
3067 | It should not be used for general purpose DMA. | |
3068 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
3069 | */ | |
c227f099 | 3070 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 3071 | { |
94a6b54f PB |
3072 | RAMBlock *block; |
3073 | ||
f471a17e AW |
3074 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
3075 | if (addr - block->offset < block->length) { | |
7d82af38 VP |
3076 | /* Move this entry to to start of the list. */ |
3077 | if (block != QLIST_FIRST(&ram_list.blocks)) { | |
3078 | QLIST_REMOVE(block, next); | |
3079 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); | |
3080 | } | |
f471a17e AW |
3081 | return block->host + (addr - block->offset); |
3082 | } | |
94a6b54f | 3083 | } |
f471a17e AW |
3084 | |
3085 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3086 | abort(); | |
3087 | ||
3088 | return NULL; | |
dc828ca1 PB |
3089 | } |
3090 | ||
b2e0a138 MT |
3091 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
3092 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. | |
3093 | */ | |
3094 | void *qemu_safe_ram_ptr(ram_addr_t addr) | |
3095 | { | |
3096 | RAMBlock *block; | |
3097 | ||
3098 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3099 | if (addr - block->offset < block->length) { | |
3100 | return block->host + (addr - block->offset); | |
3101 | } | |
3102 | } | |
3103 | ||
3104 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3105 | abort(); | |
3106 | ||
3107 | return NULL; | |
3108 | } | |
3109 | ||
e890261f | 3110 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
5579c7f3 | 3111 | { |
94a6b54f PB |
3112 | RAMBlock *block; |
3113 | uint8_t *host = ptr; | |
3114 | ||
f471a17e AW |
3115 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
3116 | if (host - block->host < block->length) { | |
e890261f MT |
3117 | *ram_addr = block->offset + (host - block->host); |
3118 | return 0; | |
f471a17e | 3119 | } |
94a6b54f | 3120 | } |
e890261f MT |
3121 | return -1; |
3122 | } | |
f471a17e | 3123 | |
e890261f MT |
3124 | /* Some of the softmmu routines need to translate from a host pointer |
3125 | (typically a TLB entry) back to a ram offset. */ | |
3126 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) | |
3127 | { | |
3128 | ram_addr_t ram_addr; | |
f471a17e | 3129 | |
e890261f MT |
3130 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
3131 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
3132 | abort(); | |
3133 | } | |
3134 | return ram_addr; | |
5579c7f3 PB |
3135 | } |
3136 | ||
c227f099 | 3137 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 3138 | { |
67d3b957 | 3139 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 3140 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 3141 | #endif |
faed1c2a | 3142 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3143 | do_unassigned_access(addr, 0, 0, 0, 1); |
3144 | #endif | |
3145 | return 0; | |
3146 | } | |
3147 | ||
c227f099 | 3148 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
3149 | { |
3150 | #ifdef DEBUG_UNASSIGNED | |
3151 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3152 | #endif | |
faed1c2a | 3153 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3154 | do_unassigned_access(addr, 0, 0, 0, 2); |
3155 | #endif | |
3156 | return 0; | |
3157 | } | |
3158 | ||
c227f099 | 3159 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
3160 | { |
3161 | #ifdef DEBUG_UNASSIGNED | |
3162 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3163 | #endif | |
faed1c2a | 3164 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 3165 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 3166 | #endif |
33417e70 FB |
3167 | return 0; |
3168 | } | |
3169 | ||
c227f099 | 3170 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 3171 | { |
67d3b957 | 3172 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 3173 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 3174 | #endif |
faed1c2a | 3175 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3176 | do_unassigned_access(addr, 1, 0, 0, 1); |
3177 | #endif | |
3178 | } | |
3179 | ||
c227f099 | 3180 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
3181 | { |
3182 | #ifdef DEBUG_UNASSIGNED | |
3183 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3184 | #endif | |
faed1c2a | 3185 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3186 | do_unassigned_access(addr, 1, 0, 0, 2); |
3187 | #endif | |
3188 | } | |
3189 | ||
c227f099 | 3190 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
3191 | { |
3192 | #ifdef DEBUG_UNASSIGNED | |
3193 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3194 | #endif | |
faed1c2a | 3195 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 3196 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 3197 | #endif |
33417e70 FB |
3198 | } |
3199 | ||
d60efc6b | 3200 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 3201 | unassigned_mem_readb, |
e18231a3 BS |
3202 | unassigned_mem_readw, |
3203 | unassigned_mem_readl, | |
33417e70 FB |
3204 | }; |
3205 | ||
d60efc6b | 3206 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 3207 | unassigned_mem_writeb, |
e18231a3 BS |
3208 | unassigned_mem_writew, |
3209 | unassigned_mem_writel, | |
33417e70 FB |
3210 | }; |
3211 | ||
c227f099 | 3212 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3213 | uint32_t val) |
9fa3e853 | 3214 | { |
3a7d929e | 3215 | int dirty_flags; |
f7c11b53 | 3216 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3217 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3218 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3219 | tb_invalidate_phys_page_fast(ram_addr, 1); |
f7c11b53 | 3220 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3221 | #endif |
3a7d929e | 3222 | } |
5579c7f3 | 3223 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3224 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3225 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3226 | /* we remove the notdirty callback only if the code has been |
3227 | flushed */ | |
3228 | if (dirty_flags == 0xff) | |
2e70f6ef | 3229 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3230 | } |
3231 | ||
c227f099 | 3232 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3233 | uint32_t val) |
9fa3e853 | 3234 | { |
3a7d929e | 3235 | int dirty_flags; |
f7c11b53 | 3236 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3237 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3238 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3239 | tb_invalidate_phys_page_fast(ram_addr, 2); |
f7c11b53 | 3240 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3241 | #endif |
3a7d929e | 3242 | } |
5579c7f3 | 3243 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3244 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3245 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3246 | /* we remove the notdirty callback only if the code has been |
3247 | flushed */ | |
3248 | if (dirty_flags == 0xff) | |
2e70f6ef | 3249 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3250 | } |
3251 | ||
c227f099 | 3252 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3253 | uint32_t val) |
9fa3e853 | 3254 | { |
3a7d929e | 3255 | int dirty_flags; |
f7c11b53 | 3256 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3257 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3258 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3259 | tb_invalidate_phys_page_fast(ram_addr, 4); |
f7c11b53 | 3260 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3261 | #endif |
3a7d929e | 3262 | } |
5579c7f3 | 3263 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3264 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3265 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3266 | /* we remove the notdirty callback only if the code has been |
3267 | flushed */ | |
3268 | if (dirty_flags == 0xff) | |
2e70f6ef | 3269 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3270 | } |
3271 | ||
d60efc6b | 3272 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
3273 | NULL, /* never used */ |
3274 | NULL, /* never used */ | |
3275 | NULL, /* never used */ | |
3276 | }; | |
3277 | ||
d60efc6b | 3278 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
3279 | notdirty_mem_writeb, |
3280 | notdirty_mem_writew, | |
3281 | notdirty_mem_writel, | |
3282 | }; | |
3283 | ||
0f459d16 | 3284 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 3285 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
3286 | { |
3287 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
3288 | target_ulong pc, cs_base; |
3289 | TranslationBlock *tb; | |
0f459d16 | 3290 | target_ulong vaddr; |
a1d1bb31 | 3291 | CPUWatchpoint *wp; |
06d55cc1 | 3292 | int cpu_flags; |
0f459d16 | 3293 | |
06d55cc1 AL |
3294 | if (env->watchpoint_hit) { |
3295 | /* We re-entered the check after replacing the TB. Now raise | |
3296 | * the debug interrupt so that is will trigger after the | |
3297 | * current instruction. */ | |
3298 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
3299 | return; | |
3300 | } | |
2e70f6ef | 3301 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 3302 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
3303 | if ((vaddr == (wp->vaddr & len_mask) || |
3304 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
3305 | wp->flags |= BP_WATCHPOINT_HIT; |
3306 | if (!env->watchpoint_hit) { | |
3307 | env->watchpoint_hit = wp; | |
3308 | tb = tb_find_pc(env->mem_io_pc); | |
3309 | if (!tb) { | |
3310 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
3311 | "pc=%p", (void *)env->mem_io_pc); | |
3312 | } | |
618ba8e6 | 3313 | cpu_restore_state(tb, env, env->mem_io_pc); |
6e140f28 AL |
3314 | tb_phys_invalidate(tb, -1); |
3315 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
3316 | env->exception_index = EXCP_DEBUG; | |
3317 | } else { | |
3318 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
3319 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
3320 | } | |
3321 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 3322 | } |
6e140f28 AL |
3323 | } else { |
3324 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
3325 | } |
3326 | } | |
3327 | } | |
3328 | ||
6658ffb8 PB |
3329 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
3330 | so these check for a hit then pass through to the normal out-of-line | |
3331 | phys routines. */ | |
c227f099 | 3332 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3333 | { |
b4051334 | 3334 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
3335 | return ldub_phys(addr); |
3336 | } | |
3337 | ||
c227f099 | 3338 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3339 | { |
b4051334 | 3340 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
3341 | return lduw_phys(addr); |
3342 | } | |
3343 | ||
c227f099 | 3344 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3345 | { |
b4051334 | 3346 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
3347 | return ldl_phys(addr); |
3348 | } | |
3349 | ||
c227f099 | 3350 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3351 | uint32_t val) |
3352 | { | |
b4051334 | 3353 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
3354 | stb_phys(addr, val); |
3355 | } | |
3356 | ||
c227f099 | 3357 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3358 | uint32_t val) |
3359 | { | |
b4051334 | 3360 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
3361 | stw_phys(addr, val); |
3362 | } | |
3363 | ||
c227f099 | 3364 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3365 | uint32_t val) |
3366 | { | |
b4051334 | 3367 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
3368 | stl_phys(addr, val); |
3369 | } | |
3370 | ||
d60efc6b | 3371 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
3372 | watch_mem_readb, |
3373 | watch_mem_readw, | |
3374 | watch_mem_readl, | |
3375 | }; | |
3376 | ||
d60efc6b | 3377 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
3378 | watch_mem_writeb, |
3379 | watch_mem_writew, | |
3380 | watch_mem_writel, | |
3381 | }; | |
6658ffb8 | 3382 | |
f6405247 RH |
3383 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
3384 | target_phys_addr_t addr, | |
3385 | unsigned int len) | |
db7b5426 | 3386 | { |
f6405247 | 3387 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
3388 | #if defined(DEBUG_SUBPAGE) |
3389 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3390 | mmio, len, addr, idx); | |
3391 | #endif | |
db7b5426 | 3392 | |
f6405247 RH |
3393 | addr += mmio->region_offset[idx]; |
3394 | idx = mmio->sub_io_index[idx]; | |
3395 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); | |
db7b5426 BS |
3396 | } |
3397 | ||
c227f099 | 3398 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
f6405247 | 3399 | uint32_t value, unsigned int len) |
db7b5426 | 3400 | { |
f6405247 | 3401 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 | 3402 | #if defined(DEBUG_SUBPAGE) |
f6405247 RH |
3403 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
3404 | __func__, mmio, len, addr, idx, value); | |
db7b5426 | 3405 | #endif |
f6405247 RH |
3406 | |
3407 | addr += mmio->region_offset[idx]; | |
3408 | idx = mmio->sub_io_index[idx]; | |
3409 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); | |
db7b5426 BS |
3410 | } |
3411 | ||
c227f099 | 3412 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3413 | { |
db7b5426 BS |
3414 | return subpage_readlen(opaque, addr, 0); |
3415 | } | |
3416 | ||
c227f099 | 3417 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3418 | uint32_t value) |
3419 | { | |
db7b5426 BS |
3420 | subpage_writelen(opaque, addr, value, 0); |
3421 | } | |
3422 | ||
c227f099 | 3423 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3424 | { |
db7b5426 BS |
3425 | return subpage_readlen(opaque, addr, 1); |
3426 | } | |
3427 | ||
c227f099 | 3428 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3429 | uint32_t value) |
3430 | { | |
db7b5426 BS |
3431 | subpage_writelen(opaque, addr, value, 1); |
3432 | } | |
3433 | ||
c227f099 | 3434 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3435 | { |
db7b5426 BS |
3436 | return subpage_readlen(opaque, addr, 2); |
3437 | } | |
3438 | ||
f6405247 RH |
3439 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
3440 | uint32_t value) | |
db7b5426 | 3441 | { |
db7b5426 BS |
3442 | subpage_writelen(opaque, addr, value, 2); |
3443 | } | |
3444 | ||
d60efc6b | 3445 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
3446 | &subpage_readb, |
3447 | &subpage_readw, | |
3448 | &subpage_readl, | |
3449 | }; | |
3450 | ||
d60efc6b | 3451 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
3452 | &subpage_writeb, |
3453 | &subpage_writew, | |
3454 | &subpage_writel, | |
3455 | }; | |
3456 | ||
c227f099 AL |
3457 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
3458 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
3459 | { |
3460 | int idx, eidx; | |
3461 | ||
3462 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3463 | return -1; | |
3464 | idx = SUBPAGE_IDX(start); | |
3465 | eidx = SUBPAGE_IDX(end); | |
3466 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 3467 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
3468 | mmio, start, end, idx, eidx, memory); |
3469 | #endif | |
95c318f5 GN |
3470 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
3471 | memory = IO_MEM_UNASSIGNED; | |
f6405247 | 3472 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
db7b5426 | 3473 | for (; idx <= eidx; idx++) { |
f6405247 RH |
3474 | mmio->sub_io_index[idx] = memory; |
3475 | mmio->region_offset[idx] = region_offset; | |
db7b5426 BS |
3476 | } |
3477 | ||
3478 | return 0; | |
3479 | } | |
3480 | ||
f6405247 RH |
3481 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
3482 | ram_addr_t orig_memory, | |
3483 | ram_addr_t region_offset) | |
db7b5426 | 3484 | { |
c227f099 | 3485 | subpage_t *mmio; |
db7b5426 BS |
3486 | int subpage_memory; |
3487 | ||
c227f099 | 3488 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
3489 | |
3490 | mmio->base = base; | |
2507c12a AG |
3491 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio, |
3492 | DEVICE_NATIVE_ENDIAN); | |
db7b5426 | 3493 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3494 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3495 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3496 | #endif |
1eec614b | 3497 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
f6405247 | 3498 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
db7b5426 BS |
3499 | |
3500 | return mmio; | |
3501 | } | |
3502 | ||
88715657 AL |
3503 | static int get_free_io_mem_idx(void) |
3504 | { | |
3505 | int i; | |
3506 | ||
3507 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3508 | if (!io_mem_used[i]) { | |
3509 | io_mem_used[i] = 1; | |
3510 | return i; | |
3511 | } | |
c6703b47 | 3512 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3513 | return -1; |
3514 | } | |
3515 | ||
dd310534 AG |
3516 | /* |
3517 | * Usually, devices operate in little endian mode. There are devices out | |
3518 | * there that operate in big endian too. Each device gets byte swapped | |
3519 | * mmio if plugged onto a CPU that does the other endianness. | |
3520 | * | |
3521 | * CPU Device swap? | |
3522 | * | |
3523 | * little little no | |
3524 | * little big yes | |
3525 | * big little yes | |
3526 | * big big no | |
3527 | */ | |
3528 | ||
3529 | typedef struct SwapEndianContainer { | |
3530 | CPUReadMemoryFunc *read[3]; | |
3531 | CPUWriteMemoryFunc *write[3]; | |
3532 | void *opaque; | |
3533 | } SwapEndianContainer; | |
3534 | ||
3535 | static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr) | |
3536 | { | |
3537 | uint32_t val; | |
3538 | SwapEndianContainer *c = opaque; | |
3539 | val = c->read[0](c->opaque, addr); | |
3540 | return val; | |
3541 | } | |
3542 | ||
3543 | static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr) | |
3544 | { | |
3545 | uint32_t val; | |
3546 | SwapEndianContainer *c = opaque; | |
3547 | val = bswap16(c->read[1](c->opaque, addr)); | |
3548 | return val; | |
3549 | } | |
3550 | ||
3551 | static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr) | |
3552 | { | |
3553 | uint32_t val; | |
3554 | SwapEndianContainer *c = opaque; | |
3555 | val = bswap32(c->read[2](c->opaque, addr)); | |
3556 | return val; | |
3557 | } | |
3558 | ||
3559 | static CPUReadMemoryFunc * const swapendian_readfn[3]={ | |
3560 | swapendian_mem_readb, | |
3561 | swapendian_mem_readw, | |
3562 | swapendian_mem_readl | |
3563 | }; | |
3564 | ||
3565 | static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr, | |
3566 | uint32_t val) | |
3567 | { | |
3568 | SwapEndianContainer *c = opaque; | |
3569 | c->write[0](c->opaque, addr, val); | |
3570 | } | |
3571 | ||
3572 | static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr, | |
3573 | uint32_t val) | |
3574 | { | |
3575 | SwapEndianContainer *c = opaque; | |
3576 | c->write[1](c->opaque, addr, bswap16(val)); | |
3577 | } | |
3578 | ||
3579 | static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr, | |
3580 | uint32_t val) | |
3581 | { | |
3582 | SwapEndianContainer *c = opaque; | |
3583 | c->write[2](c->opaque, addr, bswap32(val)); | |
3584 | } | |
3585 | ||
3586 | static CPUWriteMemoryFunc * const swapendian_writefn[3]={ | |
3587 | swapendian_mem_writeb, | |
3588 | swapendian_mem_writew, | |
3589 | swapendian_mem_writel | |
3590 | }; | |
3591 | ||
3592 | static void swapendian_init(int io_index) | |
3593 | { | |
3594 | SwapEndianContainer *c = qemu_malloc(sizeof(SwapEndianContainer)); | |
3595 | int i; | |
3596 | ||
3597 | /* Swap mmio for big endian targets */ | |
3598 | c->opaque = io_mem_opaque[io_index]; | |
3599 | for (i = 0; i < 3; i++) { | |
3600 | c->read[i] = io_mem_read[io_index][i]; | |
3601 | c->write[i] = io_mem_write[io_index][i]; | |
3602 | ||
3603 | io_mem_read[io_index][i] = swapendian_readfn[i]; | |
3604 | io_mem_write[io_index][i] = swapendian_writefn[i]; | |
3605 | } | |
3606 | io_mem_opaque[io_index] = c; | |
3607 | } | |
3608 | ||
3609 | static void swapendian_del(int io_index) | |
3610 | { | |
3611 | if (io_mem_read[io_index][0] == swapendian_readfn[0]) { | |
3612 | qemu_free(io_mem_opaque[io_index]); | |
3613 | } | |
3614 | } | |
3615 | ||
33417e70 FB |
3616 | /* mem_read and mem_write are arrays of functions containing the |
3617 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3618 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3619 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3620 | modified. If it is zero, a new io zone is allocated. The return |
3621 | value can be used with cpu_register_physical_memory(). (-1) is | |
3622 | returned if error. */ | |
1eed09cb | 3623 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
3624 | CPUReadMemoryFunc * const *mem_read, |
3625 | CPUWriteMemoryFunc * const *mem_write, | |
dd310534 | 3626 | void *opaque, enum device_endian endian) |
33417e70 | 3627 | { |
3cab721d RH |
3628 | int i; |
3629 | ||
33417e70 | 3630 | if (io_index <= 0) { |
88715657 AL |
3631 | io_index = get_free_io_mem_idx(); |
3632 | if (io_index == -1) | |
3633 | return io_index; | |
33417e70 | 3634 | } else { |
1eed09cb | 3635 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3636 | if (io_index >= IO_MEM_NB_ENTRIES) |
3637 | return -1; | |
3638 | } | |
b5ff1b31 | 3639 | |
3cab721d RH |
3640 | for (i = 0; i < 3; ++i) { |
3641 | io_mem_read[io_index][i] | |
3642 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); | |
3643 | } | |
3644 | for (i = 0; i < 3; ++i) { | |
3645 | io_mem_write[io_index][i] | |
3646 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); | |
3647 | } | |
a4193c8a | 3648 | io_mem_opaque[io_index] = opaque; |
f6405247 | 3649 | |
dd310534 AG |
3650 | switch (endian) { |
3651 | case DEVICE_BIG_ENDIAN: | |
3652 | #ifndef TARGET_WORDS_BIGENDIAN | |
3653 | swapendian_init(io_index); | |
3654 | #endif | |
3655 | break; | |
3656 | case DEVICE_LITTLE_ENDIAN: | |
3657 | #ifdef TARGET_WORDS_BIGENDIAN | |
3658 | swapendian_init(io_index); | |
3659 | #endif | |
3660 | break; | |
3661 | case DEVICE_NATIVE_ENDIAN: | |
3662 | default: | |
3663 | break; | |
3664 | } | |
3665 | ||
f6405247 | 3666 | return (io_index << IO_MEM_SHIFT); |
33417e70 | 3667 | } |
61382a50 | 3668 | |
d60efc6b BS |
3669 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
3670 | CPUWriteMemoryFunc * const *mem_write, | |
dd310534 | 3671 | void *opaque, enum device_endian endian) |
1eed09cb | 3672 | { |
2507c12a | 3673 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian); |
1eed09cb AK |
3674 | } |
3675 | ||
88715657 AL |
3676 | void cpu_unregister_io_memory(int io_table_address) |
3677 | { | |
3678 | int i; | |
3679 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3680 | ||
dd310534 AG |
3681 | swapendian_del(io_index); |
3682 | ||
88715657 AL |
3683 | for (i=0;i < 3; i++) { |
3684 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3685 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3686 | } | |
3687 | io_mem_opaque[io_index] = NULL; | |
3688 | io_mem_used[io_index] = 0; | |
3689 | } | |
3690 | ||
e9179ce1 AK |
3691 | static void io_mem_init(void) |
3692 | { | |
3693 | int i; | |
3694 | ||
2507c12a AG |
3695 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, |
3696 | unassigned_mem_write, NULL, | |
3697 | DEVICE_NATIVE_ENDIAN); | |
3698 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, | |
3699 | unassigned_mem_write, NULL, | |
3700 | DEVICE_NATIVE_ENDIAN); | |
3701 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, | |
3702 | notdirty_mem_write, NULL, | |
3703 | DEVICE_NATIVE_ENDIAN); | |
e9179ce1 AK |
3704 | for (i=0; i<5; i++) |
3705 | io_mem_used[i] = 1; | |
3706 | ||
3707 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
2507c12a AG |
3708 | watch_mem_write, NULL, |
3709 | DEVICE_NATIVE_ENDIAN); | |
e9179ce1 AK |
3710 | } |
3711 | ||
e2eef170 PB |
3712 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3713 | ||
13eb76e0 FB |
3714 | /* physical memory access (slow version, mainly for debug) */ |
3715 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3716 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3717 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3718 | { |
3719 | int l, flags; | |
3720 | target_ulong page; | |
53a5960a | 3721 | void * p; |
13eb76e0 FB |
3722 | |
3723 | while (len > 0) { | |
3724 | page = addr & TARGET_PAGE_MASK; | |
3725 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3726 | if (l > len) | |
3727 | l = len; | |
3728 | flags = page_get_flags(page); | |
3729 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3730 | return -1; |
13eb76e0 FB |
3731 | if (is_write) { |
3732 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3733 | return -1; |
579a97f7 | 3734 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3735 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3736 | return -1; |
72fb7daa AJ |
3737 | memcpy(p, buf, l); |
3738 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3739 | } else { |
3740 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3741 | return -1; |
579a97f7 | 3742 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3743 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3744 | return -1; |
72fb7daa | 3745 | memcpy(buf, p, l); |
5b257578 | 3746 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3747 | } |
3748 | len -= l; | |
3749 | buf += l; | |
3750 | addr += l; | |
3751 | } | |
a68fe89c | 3752 | return 0; |
13eb76e0 | 3753 | } |
8df1cd07 | 3754 | |
13eb76e0 | 3755 | #else |
c227f099 | 3756 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3757 | int len, int is_write) |
3758 | { | |
3759 | int l, io_index; | |
3760 | uint8_t *ptr; | |
3761 | uint32_t val; | |
c227f099 | 3762 | target_phys_addr_t page; |
2e12669a | 3763 | unsigned long pd; |
92e873b9 | 3764 | PhysPageDesc *p; |
3b46e624 | 3765 | |
13eb76e0 FB |
3766 | while (len > 0) { |
3767 | page = addr & TARGET_PAGE_MASK; | |
3768 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3769 | if (l > len) | |
3770 | l = len; | |
92e873b9 | 3771 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3772 | if (!p) { |
3773 | pd = IO_MEM_UNASSIGNED; | |
3774 | } else { | |
3775 | pd = p->phys_offset; | |
3776 | } | |
3b46e624 | 3777 | |
13eb76e0 | 3778 | if (is_write) { |
3a7d929e | 3779 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3780 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3781 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3782 | if (p) |
6c2934db | 3783 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3784 | /* XXX: could force cpu_single_env to NULL to avoid |
3785 | potential bugs */ | |
6c2934db | 3786 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3787 | /* 32 bit write access */ |
c27004ec | 3788 | val = ldl_p(buf); |
6c2934db | 3789 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3790 | l = 4; |
6c2934db | 3791 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3792 | /* 16 bit write access */ |
c27004ec | 3793 | val = lduw_p(buf); |
6c2934db | 3794 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3795 | l = 2; |
3796 | } else { | |
1c213d19 | 3797 | /* 8 bit write access */ |
c27004ec | 3798 | val = ldub_p(buf); |
6c2934db | 3799 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3800 | l = 1; |
3801 | } | |
3802 | } else { | |
b448f2f3 FB |
3803 | unsigned long addr1; |
3804 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3805 | /* RAM case */ |
5579c7f3 | 3806 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3807 | memcpy(ptr, buf, l); |
3a7d929e FB |
3808 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3809 | /* invalidate code */ | |
3810 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3811 | /* set dirty bit */ | |
f7c11b53 YT |
3812 | cpu_physical_memory_set_dirty_flags( |
3813 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3814 | } |
13eb76e0 FB |
3815 | } |
3816 | } else { | |
5fafdf24 | 3817 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3818 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3819 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3820 | /* I/O case */ |
3821 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3822 | if (p) |
6c2934db AJ |
3823 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3824 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3825 | /* 32 bit read access */ |
6c2934db | 3826 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3827 | stl_p(buf, val); |
13eb76e0 | 3828 | l = 4; |
6c2934db | 3829 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3830 | /* 16 bit read access */ |
6c2934db | 3831 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3832 | stw_p(buf, val); |
13eb76e0 FB |
3833 | l = 2; |
3834 | } else { | |
1c213d19 | 3835 | /* 8 bit read access */ |
6c2934db | 3836 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3837 | stb_p(buf, val); |
13eb76e0 FB |
3838 | l = 1; |
3839 | } | |
3840 | } else { | |
3841 | /* RAM case */ | |
5579c7f3 | 3842 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3843 | (addr & ~TARGET_PAGE_MASK); |
3844 | memcpy(buf, ptr, l); | |
3845 | } | |
3846 | } | |
3847 | len -= l; | |
3848 | buf += l; | |
3849 | addr += l; | |
3850 | } | |
3851 | } | |
8df1cd07 | 3852 | |
d0ecd2aa | 3853 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3854 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3855 | const uint8_t *buf, int len) |
3856 | { | |
3857 | int l; | |
3858 | uint8_t *ptr; | |
c227f099 | 3859 | target_phys_addr_t page; |
d0ecd2aa FB |
3860 | unsigned long pd; |
3861 | PhysPageDesc *p; | |
3b46e624 | 3862 | |
d0ecd2aa FB |
3863 | while (len > 0) { |
3864 | page = addr & TARGET_PAGE_MASK; | |
3865 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3866 | if (l > len) | |
3867 | l = len; | |
3868 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3869 | if (!p) { | |
3870 | pd = IO_MEM_UNASSIGNED; | |
3871 | } else { | |
3872 | pd = p->phys_offset; | |
3873 | } | |
3b46e624 | 3874 | |
d0ecd2aa | 3875 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3876 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3877 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3878 | /* do nothing */ |
3879 | } else { | |
3880 | unsigned long addr1; | |
3881 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3882 | /* ROM/RAM case */ | |
5579c7f3 | 3883 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3884 | memcpy(ptr, buf, l); |
3885 | } | |
3886 | len -= l; | |
3887 | buf += l; | |
3888 | addr += l; | |
3889 | } | |
3890 | } | |
3891 | ||
6d16c2f8 AL |
3892 | typedef struct { |
3893 | void *buffer; | |
c227f099 AL |
3894 | target_phys_addr_t addr; |
3895 | target_phys_addr_t len; | |
6d16c2f8 AL |
3896 | } BounceBuffer; |
3897 | ||
3898 | static BounceBuffer bounce; | |
3899 | ||
ba223c29 AL |
3900 | typedef struct MapClient { |
3901 | void *opaque; | |
3902 | void (*callback)(void *opaque); | |
72cf2d4f | 3903 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3904 | } MapClient; |
3905 | ||
72cf2d4f BS |
3906 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3907 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3908 | |
3909 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3910 | { | |
3911 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3912 | ||
3913 | client->opaque = opaque; | |
3914 | client->callback = callback; | |
72cf2d4f | 3915 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3916 | return client; |
3917 | } | |
3918 | ||
3919 | void cpu_unregister_map_client(void *_client) | |
3920 | { | |
3921 | MapClient *client = (MapClient *)_client; | |
3922 | ||
72cf2d4f | 3923 | QLIST_REMOVE(client, link); |
34d5e948 | 3924 | qemu_free(client); |
ba223c29 AL |
3925 | } |
3926 | ||
3927 | static void cpu_notify_map_clients(void) | |
3928 | { | |
3929 | MapClient *client; | |
3930 | ||
72cf2d4f BS |
3931 | while (!QLIST_EMPTY(&map_client_list)) { |
3932 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3933 | client->callback(client->opaque); |
34d5e948 | 3934 | cpu_unregister_map_client(client); |
ba223c29 AL |
3935 | } |
3936 | } | |
3937 | ||
6d16c2f8 AL |
3938 | /* Map a physical memory region into a host virtual address. |
3939 | * May map a subset of the requested range, given by and returned in *plen. | |
3940 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3941 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3942 | * Use cpu_register_map_client() to know when retrying the map operation is |
3943 | * likely to succeed. | |
6d16c2f8 | 3944 | */ |
c227f099 AL |
3945 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3946 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3947 | int is_write) |
3948 | { | |
c227f099 AL |
3949 | target_phys_addr_t len = *plen; |
3950 | target_phys_addr_t done = 0; | |
6d16c2f8 AL |
3951 | int l; |
3952 | uint8_t *ret = NULL; | |
3953 | uint8_t *ptr; | |
c227f099 | 3954 | target_phys_addr_t page; |
6d16c2f8 AL |
3955 | unsigned long pd; |
3956 | PhysPageDesc *p; | |
3957 | unsigned long addr1; | |
3958 | ||
3959 | while (len > 0) { | |
3960 | page = addr & TARGET_PAGE_MASK; | |
3961 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3962 | if (l > len) | |
3963 | l = len; | |
3964 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3965 | if (!p) { | |
3966 | pd = IO_MEM_UNASSIGNED; | |
3967 | } else { | |
3968 | pd = p->phys_offset; | |
3969 | } | |
3970 | ||
3971 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3972 | if (done || bounce.buffer) { | |
3973 | break; | |
3974 | } | |
3975 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3976 | bounce.addr = addr; | |
3977 | bounce.len = l; | |
3978 | if (!is_write) { | |
54f7b4a3 | 3979 | cpu_physical_memory_read(addr, bounce.buffer, l); |
6d16c2f8 AL |
3980 | } |
3981 | ptr = bounce.buffer; | |
3982 | } else { | |
3983 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3984 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3985 | } |
3986 | if (!done) { | |
3987 | ret = ptr; | |
3988 | } else if (ret + done != ptr) { | |
3989 | break; | |
3990 | } | |
3991 | ||
3992 | len -= l; | |
3993 | addr += l; | |
3994 | done += l; | |
3995 | } | |
3996 | *plen = done; | |
3997 | return ret; | |
3998 | } | |
3999 | ||
4000 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
4001 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
4002 | * the amount of memory that was actually read or written by the caller. | |
4003 | */ | |
c227f099 AL |
4004 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
4005 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
4006 | { |
4007 | if (buffer != bounce.buffer) { | |
4008 | if (is_write) { | |
e890261f | 4009 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
6d16c2f8 AL |
4010 | while (access_len) { |
4011 | unsigned l; | |
4012 | l = TARGET_PAGE_SIZE; | |
4013 | if (l > access_len) | |
4014 | l = access_len; | |
4015 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4016 | /* invalidate code */ | |
4017 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
4018 | /* set dirty bit */ | |
f7c11b53 YT |
4019 | cpu_physical_memory_set_dirty_flags( |
4020 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
6d16c2f8 AL |
4021 | } |
4022 | addr1 += l; | |
4023 | access_len -= l; | |
4024 | } | |
4025 | } | |
4026 | return; | |
4027 | } | |
4028 | if (is_write) { | |
4029 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
4030 | } | |
f8a83245 | 4031 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 4032 | bounce.buffer = NULL; |
ba223c29 | 4033 | cpu_notify_map_clients(); |
6d16c2f8 | 4034 | } |
d0ecd2aa | 4035 | |
8df1cd07 | 4036 | /* warning: addr must be aligned */ |
c227f099 | 4037 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
4038 | { |
4039 | int io_index; | |
4040 | uint8_t *ptr; | |
4041 | uint32_t val; | |
4042 | unsigned long pd; | |
4043 | PhysPageDesc *p; | |
4044 | ||
4045 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4046 | if (!p) { | |
4047 | pd = IO_MEM_UNASSIGNED; | |
4048 | } else { | |
4049 | pd = p->phys_offset; | |
4050 | } | |
3b46e624 | 4051 | |
5fafdf24 | 4052 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 4053 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
4054 | /* I/O case */ |
4055 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
4056 | if (p) |
4057 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
4058 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
4059 | } else { | |
4060 | /* RAM case */ | |
5579c7f3 | 4061 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
4062 | (addr & ~TARGET_PAGE_MASK); |
4063 | val = ldl_p(ptr); | |
4064 | } | |
4065 | return val; | |
4066 | } | |
4067 | ||
84b7b8e7 | 4068 | /* warning: addr must be aligned */ |
c227f099 | 4069 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
4070 | { |
4071 | int io_index; | |
4072 | uint8_t *ptr; | |
4073 | uint64_t val; | |
4074 | unsigned long pd; | |
4075 | PhysPageDesc *p; | |
4076 | ||
4077 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4078 | if (!p) { | |
4079 | pd = IO_MEM_UNASSIGNED; | |
4080 | } else { | |
4081 | pd = p->phys_offset; | |
4082 | } | |
3b46e624 | 4083 | |
2a4188a3 FB |
4084 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
4085 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
4086 | /* I/O case */ |
4087 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
4088 | if (p) |
4089 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
4090 | #ifdef TARGET_WORDS_BIGENDIAN |
4091 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
4092 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
4093 | #else | |
4094 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
4095 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
4096 | #endif | |
4097 | } else { | |
4098 | /* RAM case */ | |
5579c7f3 | 4099 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
4100 | (addr & ~TARGET_PAGE_MASK); |
4101 | val = ldq_p(ptr); | |
4102 | } | |
4103 | return val; | |
4104 | } | |
4105 | ||
aab33094 | 4106 | /* XXX: optimize */ |
c227f099 | 4107 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
4108 | { |
4109 | uint8_t val; | |
4110 | cpu_physical_memory_read(addr, &val, 1); | |
4111 | return val; | |
4112 | } | |
4113 | ||
733f0b02 | 4114 | /* warning: addr must be aligned */ |
c227f099 | 4115 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 | 4116 | { |
733f0b02 MT |
4117 | int io_index; |
4118 | uint8_t *ptr; | |
4119 | uint64_t val; | |
4120 | unsigned long pd; | |
4121 | PhysPageDesc *p; | |
4122 | ||
4123 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4124 | if (!p) { | |
4125 | pd = IO_MEM_UNASSIGNED; | |
4126 | } else { | |
4127 | pd = p->phys_offset; | |
4128 | } | |
4129 | ||
4130 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
4131 | !(pd & IO_MEM_ROMD)) { | |
4132 | /* I/O case */ | |
4133 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4134 | if (p) | |
4135 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4136 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); | |
4137 | } else { | |
4138 | /* RAM case */ | |
4139 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
4140 | (addr & ~TARGET_PAGE_MASK); | |
4141 | val = lduw_p(ptr); | |
4142 | } | |
4143 | return val; | |
aab33094 FB |
4144 | } |
4145 | ||
8df1cd07 FB |
4146 | /* warning: addr must be aligned. The ram page is not masked as dirty |
4147 | and the code inside is not invalidated. It is useful if the dirty | |
4148 | bits are used to track modified PTEs */ | |
c227f099 | 4149 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
4150 | { |
4151 | int io_index; | |
4152 | uint8_t *ptr; | |
4153 | unsigned long pd; | |
4154 | PhysPageDesc *p; | |
4155 | ||
4156 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4157 | if (!p) { | |
4158 | pd = IO_MEM_UNASSIGNED; | |
4159 | } else { | |
4160 | pd = p->phys_offset; | |
4161 | } | |
3b46e624 | 4162 | |
3a7d929e | 4163 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 4164 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
4165 | if (p) |
4166 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
4167 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
4168 | } else { | |
74576198 | 4169 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 4170 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 4171 | stl_p(ptr, val); |
74576198 AL |
4172 | |
4173 | if (unlikely(in_migration)) { | |
4174 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4175 | /* invalidate code */ | |
4176 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4177 | /* set dirty bit */ | |
f7c11b53 YT |
4178 | cpu_physical_memory_set_dirty_flags( |
4179 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
74576198 AL |
4180 | } |
4181 | } | |
8df1cd07 FB |
4182 | } |
4183 | } | |
4184 | ||
c227f099 | 4185 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
4186 | { |
4187 | int io_index; | |
4188 | uint8_t *ptr; | |
4189 | unsigned long pd; | |
4190 | PhysPageDesc *p; | |
4191 | ||
4192 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4193 | if (!p) { | |
4194 | pd = IO_MEM_UNASSIGNED; | |
4195 | } else { | |
4196 | pd = p->phys_offset; | |
4197 | } | |
3b46e624 | 4198 | |
bc98a7ef JM |
4199 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
4200 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
4201 | if (p) |
4202 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
4203 | #ifdef TARGET_WORDS_BIGENDIAN |
4204 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
4205 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
4206 | #else | |
4207 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
4208 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
4209 | #endif | |
4210 | } else { | |
5579c7f3 | 4211 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
4212 | (addr & ~TARGET_PAGE_MASK); |
4213 | stq_p(ptr, val); | |
4214 | } | |
4215 | } | |
4216 | ||
8df1cd07 | 4217 | /* warning: addr must be aligned */ |
c227f099 | 4218 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
4219 | { |
4220 | int io_index; | |
4221 | uint8_t *ptr; | |
4222 | unsigned long pd; | |
4223 | PhysPageDesc *p; | |
4224 | ||
4225 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4226 | if (!p) { | |
4227 | pd = IO_MEM_UNASSIGNED; | |
4228 | } else { | |
4229 | pd = p->phys_offset; | |
4230 | } | |
3b46e624 | 4231 | |
3a7d929e | 4232 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 4233 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
4234 | if (p) |
4235 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
4236 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
4237 | } else { | |
4238 | unsigned long addr1; | |
4239 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4240 | /* RAM case */ | |
5579c7f3 | 4241 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 4242 | stl_p(ptr, val); |
3a7d929e FB |
4243 | if (!cpu_physical_memory_is_dirty(addr1)) { |
4244 | /* invalidate code */ | |
4245 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4246 | /* set dirty bit */ | |
f7c11b53 YT |
4247 | cpu_physical_memory_set_dirty_flags(addr1, |
4248 | (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 4249 | } |
8df1cd07 FB |
4250 | } |
4251 | } | |
4252 | ||
aab33094 | 4253 | /* XXX: optimize */ |
c227f099 | 4254 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
4255 | { |
4256 | uint8_t v = val; | |
4257 | cpu_physical_memory_write(addr, &v, 1); | |
4258 | } | |
4259 | ||
733f0b02 | 4260 | /* warning: addr must be aligned */ |
c227f099 | 4261 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 | 4262 | { |
733f0b02 MT |
4263 | int io_index; |
4264 | uint8_t *ptr; | |
4265 | unsigned long pd; | |
4266 | PhysPageDesc *p; | |
4267 | ||
4268 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4269 | if (!p) { | |
4270 | pd = IO_MEM_UNASSIGNED; | |
4271 | } else { | |
4272 | pd = p->phys_offset; | |
4273 | } | |
4274 | ||
4275 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
4276 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4277 | if (p) | |
4278 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4279 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); | |
4280 | } else { | |
4281 | unsigned long addr1; | |
4282 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4283 | /* RAM case */ | |
4284 | ptr = qemu_get_ram_ptr(addr1); | |
4285 | stw_p(ptr, val); | |
4286 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4287 | /* invalidate code */ | |
4288 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); | |
4289 | /* set dirty bit */ | |
4290 | cpu_physical_memory_set_dirty_flags(addr1, | |
4291 | (0xff & ~CODE_DIRTY_FLAG)); | |
4292 | } | |
4293 | } | |
aab33094 FB |
4294 | } |
4295 | ||
4296 | /* XXX: optimize */ | |
c227f099 | 4297 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
4298 | { |
4299 | val = tswap64(val); | |
71d2b725 | 4300 | cpu_physical_memory_write(addr, &val, 8); |
aab33094 FB |
4301 | } |
4302 | ||
5e2972fd | 4303 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 4304 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 4305 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
4306 | { |
4307 | int l; | |
c227f099 | 4308 | target_phys_addr_t phys_addr; |
9b3c35e0 | 4309 | target_ulong page; |
13eb76e0 FB |
4310 | |
4311 | while (len > 0) { | |
4312 | page = addr & TARGET_PAGE_MASK; | |
4313 | phys_addr = cpu_get_phys_page_debug(env, page); | |
4314 | /* if no physical page mapped, return an error */ | |
4315 | if (phys_addr == -1) | |
4316 | return -1; | |
4317 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4318 | if (l > len) | |
4319 | l = len; | |
5e2972fd | 4320 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
4321 | if (is_write) |
4322 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
4323 | else | |
5e2972fd | 4324 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
4325 | len -= l; |
4326 | buf += l; | |
4327 | addr += l; | |
4328 | } | |
4329 | return 0; | |
4330 | } | |
a68fe89c | 4331 | #endif |
13eb76e0 | 4332 | |
2e70f6ef PB |
4333 | /* in deterministic execution mode, instructions doing device I/Os |
4334 | must be at the end of the TB */ | |
4335 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
4336 | { | |
4337 | TranslationBlock *tb; | |
4338 | uint32_t n, cflags; | |
4339 | target_ulong pc, cs_base; | |
4340 | uint64_t flags; | |
4341 | ||
4342 | tb = tb_find_pc((unsigned long)retaddr); | |
4343 | if (!tb) { | |
4344 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
4345 | retaddr); | |
4346 | } | |
4347 | n = env->icount_decr.u16.low + tb->icount; | |
618ba8e6 | 4348 | cpu_restore_state(tb, env, (unsigned long)retaddr); |
2e70f6ef | 4349 | /* Calculate how many instructions had been executed before the fault |
bf20dc07 | 4350 | occurred. */ |
2e70f6ef PB |
4351 | n = n - env->icount_decr.u16.low; |
4352 | /* Generate a new TB ending on the I/O insn. */ | |
4353 | n++; | |
4354 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
4355 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 4356 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
4357 | branch. */ |
4358 | #if defined(TARGET_MIPS) | |
4359 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
4360 | env->active_tc.PC -= 4; | |
4361 | env->icount_decr.u16.low++; | |
4362 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
4363 | } | |
4364 | #elif defined(TARGET_SH4) | |
4365 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
4366 | && n > 1) { | |
4367 | env->pc -= 2; | |
4368 | env->icount_decr.u16.low++; | |
4369 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
4370 | } | |
4371 | #endif | |
4372 | /* This should never happen. */ | |
4373 | if (n > CF_COUNT_MASK) | |
4374 | cpu_abort(env, "TB too big during recompile"); | |
4375 | ||
4376 | cflags = n | CF_LAST_IO; | |
4377 | pc = tb->pc; | |
4378 | cs_base = tb->cs_base; | |
4379 | flags = tb->flags; | |
4380 | tb_phys_invalidate(tb, -1); | |
4381 | /* FIXME: In theory this could raise an exception. In practice | |
4382 | we have already translated the block once so it's probably ok. */ | |
4383 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 4384 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
4385 | the first in the TB) then we end up generating a whole new TB and |
4386 | repeating the fault, which is horribly inefficient. | |
4387 | Better would be to execute just this insn uncached, or generate a | |
4388 | second new TB. */ | |
4389 | cpu_resume_from_signal(env, NULL); | |
4390 | } | |
4391 | ||
b3755a91 PB |
4392 | #if !defined(CONFIG_USER_ONLY) |
4393 | ||
055403b2 | 4394 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
e3db7226 FB |
4395 | { |
4396 | int i, target_code_size, max_target_code_size; | |
4397 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
4398 | TranslationBlock *tb; | |
3b46e624 | 4399 | |
e3db7226 FB |
4400 | target_code_size = 0; |
4401 | max_target_code_size = 0; | |
4402 | cross_page = 0; | |
4403 | direct_jmp_count = 0; | |
4404 | direct_jmp2_count = 0; | |
4405 | for(i = 0; i < nb_tbs; i++) { | |
4406 | tb = &tbs[i]; | |
4407 | target_code_size += tb->size; | |
4408 | if (tb->size > max_target_code_size) | |
4409 | max_target_code_size = tb->size; | |
4410 | if (tb->page_addr[1] != -1) | |
4411 | cross_page++; | |
4412 | if (tb->tb_next_offset[0] != 0xffff) { | |
4413 | direct_jmp_count++; | |
4414 | if (tb->tb_next_offset[1] != 0xffff) { | |
4415 | direct_jmp2_count++; | |
4416 | } | |
4417 | } | |
4418 | } | |
4419 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 4420 | cpu_fprintf(f, "Translation buffer state:\n"); |
055403b2 | 4421 | cpu_fprintf(f, "gen code size %td/%ld\n", |
26a5f13b FB |
4422 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
4423 | cpu_fprintf(f, "TB count %d/%d\n", | |
4424 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 4425 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
4426 | nb_tbs ? target_code_size / nb_tbs : 0, |
4427 | max_target_code_size); | |
055403b2 | 4428 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
4429 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
4430 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
4431 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
4432 | cross_page, | |
e3db7226 FB |
4433 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
4434 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 4435 | direct_jmp_count, |
e3db7226 FB |
4436 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
4437 | direct_jmp2_count, | |
4438 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 4439 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
4440 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
4441 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
4442 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 4443 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
4444 | } |
4445 | ||
61382a50 FB |
4446 | #define MMUSUFFIX _cmmu |
4447 | #define GETPC() NULL | |
4448 | #define env cpu_single_env | |
b769d8fe | 4449 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
4450 | |
4451 | #define SHIFT 0 | |
4452 | #include "softmmu_template.h" | |
4453 | ||
4454 | #define SHIFT 1 | |
4455 | #include "softmmu_template.h" | |
4456 | ||
4457 | #define SHIFT 2 | |
4458 | #include "softmmu_template.h" | |
4459 | ||
4460 | #define SHIFT 3 | |
4461 | #include "softmmu_template.h" | |
4462 | ||
4463 | #undef env | |
4464 | ||
4465 | #endif |