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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 FB |
26 | #include <stdlib.h> |
27 | #include <stdio.h> | |
28 | #include <stdarg.h> | |
29 | #include <string.h> | |
30 | #include <errno.h> | |
31 | #include <unistd.h> | |
32 | #include <inttypes.h> | |
33 | ||
6180a181 FB |
34 | #include "cpu.h" |
35 | #include "exec-all.h" | |
ca10f867 | 36 | #include "qemu-common.h" |
b67d9a52 | 37 | #include "tcg.h" |
b3c7724c | 38 | #include "hw/hw.h" |
74576198 | 39 | #include "osdep.h" |
7ba1e619 | 40 | #include "kvm.h" |
29e922b6 | 41 | #include "qemu-timer.h" |
53a5960a PB |
42 | #if defined(CONFIG_USER_ONLY) |
43 | #include <qemu.h> | |
fd052bf6 | 44 | #include <signal.h> |
f01576f1 JL |
45 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
46 | #include <sys/param.h> | |
47 | #if __FreeBSD_version >= 700104 | |
48 | #define HAVE_KINFO_GETVMMAP | |
49 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
50 | #include <sys/time.h> | |
51 | #include <sys/proc.h> | |
52 | #include <machine/profile.h> | |
53 | #define _KERNEL | |
54 | #include <sys/user.h> | |
55 | #undef _KERNEL | |
56 | #undef sigqueue | |
57 | #include <libutil.h> | |
58 | #endif | |
59 | #endif | |
53a5960a | 60 | #endif |
54936004 | 61 | |
fd6ce8f6 | 62 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 63 | //#define DEBUG_FLUSH |
9fa3e853 | 64 | //#define DEBUG_TLB |
67d3b957 | 65 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
66 | |
67 | /* make various TB consistency checks */ | |
5fafdf24 TS |
68 | //#define DEBUG_TB_CHECK |
69 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 70 | |
1196be37 | 71 | //#define DEBUG_IOPORT |
db7b5426 | 72 | //#define DEBUG_SUBPAGE |
1196be37 | 73 | |
99773bd4 PB |
74 | #if !defined(CONFIG_USER_ONLY) |
75 | /* TB consistency checks only implemented for usermode emulation. */ | |
76 | #undef DEBUG_TB_CHECK | |
77 | #endif | |
78 | ||
9fa3e853 FB |
79 | #define SMC_BITMAP_USE_THRESHOLD 10 |
80 | ||
bdaf78e0 | 81 | static TranslationBlock *tbs; |
26a5f13b | 82 | int code_gen_max_blocks; |
9fa3e853 | 83 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 84 | static int nb_tbs; |
eb51d102 | 85 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 86 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 87 | |
141ac468 BS |
88 | #if defined(__arm__) || defined(__sparc_v9__) |
89 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
90 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
91 | section close to code segment. */ |
92 | #define code_gen_section \ | |
93 | __attribute__((__section__(".gen_code"))) \ | |
94 | __attribute__((aligned (32))) | |
f8e2af11 SW |
95 | #elif defined(_WIN32) |
96 | /* Maximum alignment for Win32 is 16. */ | |
97 | #define code_gen_section \ | |
98 | __attribute__((aligned (16))) | |
d03d860b BS |
99 | #else |
100 | #define code_gen_section \ | |
101 | __attribute__((aligned (32))) | |
102 | #endif | |
103 | ||
104 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
105 | static uint8_t *code_gen_buffer; |
106 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 107 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 108 | static unsigned long code_gen_buffer_max_size; |
fd6ce8f6 FB |
109 | uint8_t *code_gen_ptr; |
110 | ||
e2eef170 | 111 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 112 | int phys_ram_fd; |
74576198 | 113 | static int in_migration; |
94a6b54f | 114 | |
f471a17e | 115 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; |
e2eef170 | 116 | #endif |
9fa3e853 | 117 | |
6a00d601 FB |
118 | CPUState *first_cpu; |
119 | /* current CPU in the current thread. It is only valid inside | |
120 | cpu_exec() */ | |
5fafdf24 | 121 | CPUState *cpu_single_env; |
2e70f6ef | 122 | /* 0 = Do not count executed instructions. |
bf20dc07 | 123 | 1 = Precise instruction counting. |
2e70f6ef PB |
124 | 2 = Adaptive rate instruction counting. */ |
125 | int use_icount = 0; | |
126 | /* Current instruction counter. While executing translated code this may | |
127 | include some instructions that have not yet been executed. */ | |
128 | int64_t qemu_icount; | |
6a00d601 | 129 | |
54936004 | 130 | typedef struct PageDesc { |
92e873b9 | 131 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 132 | TranslationBlock *first_tb; |
9fa3e853 FB |
133 | /* in order to optimize self modifying code, we count the number |
134 | of lookups we do to a given page to use a bitmap */ | |
135 | unsigned int code_write_count; | |
136 | uint8_t *code_bitmap; | |
137 | #if defined(CONFIG_USER_ONLY) | |
138 | unsigned long flags; | |
139 | #endif | |
54936004 FB |
140 | } PageDesc; |
141 | ||
41c1b1c9 | 142 | /* In system mode we want L1_MAP to be based on ram offsets, |
5cd2c5b6 RH |
143 | while in user mode we want it to be based on virtual addresses. */ |
144 | #if !defined(CONFIG_USER_ONLY) | |
41c1b1c9 PB |
145 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
146 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
147 | #else | |
5cd2c5b6 | 148 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
41c1b1c9 | 149 | #endif |
bedb69ea | 150 | #else |
5cd2c5b6 | 151 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
bedb69ea | 152 | #endif |
54936004 | 153 | |
5cd2c5b6 RH |
154 | /* Size of the L2 (and L3, etc) page tables. */ |
155 | #define L2_BITS 10 | |
54936004 FB |
156 | #define L2_SIZE (1 << L2_BITS) |
157 | ||
5cd2c5b6 RH |
158 | /* The bits remaining after N lower levels of page tables. */ |
159 | #define P_L1_BITS_REM \ | |
160 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
161 | #define V_L1_BITS_REM \ | |
162 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
163 | ||
164 | /* Size of the L1 page table. Avoid silly small sizes. */ | |
165 | #if P_L1_BITS_REM < 4 | |
166 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) | |
167 | #else | |
168 | #define P_L1_BITS P_L1_BITS_REM | |
169 | #endif | |
170 | ||
171 | #if V_L1_BITS_REM < 4 | |
172 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
173 | #else | |
174 | #define V_L1_BITS V_L1_BITS_REM | |
175 | #endif | |
176 | ||
177 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) | |
178 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
179 | ||
180 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) | |
181 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
182 | ||
83fb7adf FB |
183 | unsigned long qemu_real_host_page_size; |
184 | unsigned long qemu_host_page_bits; | |
185 | unsigned long qemu_host_page_size; | |
186 | unsigned long qemu_host_page_mask; | |
54936004 | 187 | |
5cd2c5b6 RH |
188 | /* This is a multi-level map on the virtual address space. |
189 | The bottom level has pointers to PageDesc. */ | |
190 | static void *l1_map[V_L1_SIZE]; | |
54936004 | 191 | |
e2eef170 | 192 | #if !defined(CONFIG_USER_ONLY) |
41c1b1c9 PB |
193 | typedef struct PhysPageDesc { |
194 | /* offset in host memory of the page + io_index in the low bits */ | |
195 | ram_addr_t phys_offset; | |
196 | ram_addr_t region_offset; | |
197 | } PhysPageDesc; | |
198 | ||
5cd2c5b6 RH |
199 | /* This is a multi-level map on the physical address space. |
200 | The bottom level has pointers to PhysPageDesc. */ | |
201 | static void *l1_phys_map[P_L1_SIZE]; | |
6d9a1304 | 202 | |
e2eef170 PB |
203 | static void io_mem_init(void); |
204 | ||
33417e70 | 205 | /* io memory support */ |
33417e70 FB |
206 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
207 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 208 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 209 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
210 | static int io_mem_watch; |
211 | #endif | |
33417e70 | 212 | |
34865134 | 213 | /* log support */ |
1e8b27ca JR |
214 | #ifdef WIN32 |
215 | static const char *logfilename = "qemu.log"; | |
216 | #else | |
d9b630fd | 217 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 218 | #endif |
34865134 FB |
219 | FILE *logfile; |
220 | int loglevel; | |
e735b91c | 221 | static int log_append = 0; |
34865134 | 222 | |
e3db7226 | 223 | /* statistics */ |
b3755a91 | 224 | #if !defined(CONFIG_USER_ONLY) |
e3db7226 | 225 | static int tlb_flush_count; |
b3755a91 | 226 | #endif |
e3db7226 FB |
227 | static int tb_flush_count; |
228 | static int tb_phys_invalidate_count; | |
229 | ||
7cb69cae FB |
230 | #ifdef _WIN32 |
231 | static void map_exec(void *addr, long size) | |
232 | { | |
233 | DWORD old_protect; | |
234 | VirtualProtect(addr, size, | |
235 | PAGE_EXECUTE_READWRITE, &old_protect); | |
236 | ||
237 | } | |
238 | #else | |
239 | static void map_exec(void *addr, long size) | |
240 | { | |
4369415f | 241 | unsigned long start, end, page_size; |
7cb69cae | 242 | |
4369415f | 243 | page_size = getpagesize(); |
7cb69cae | 244 | start = (unsigned long)addr; |
4369415f | 245 | start &= ~(page_size - 1); |
7cb69cae FB |
246 | |
247 | end = (unsigned long)addr + size; | |
4369415f FB |
248 | end += page_size - 1; |
249 | end &= ~(page_size - 1); | |
7cb69cae FB |
250 | |
251 | mprotect((void *)start, end - start, | |
252 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
253 | } | |
254 | #endif | |
255 | ||
b346ff46 | 256 | static void page_init(void) |
54936004 | 257 | { |
83fb7adf | 258 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 259 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
260 | #ifdef _WIN32 |
261 | { | |
262 | SYSTEM_INFO system_info; | |
263 | ||
264 | GetSystemInfo(&system_info); | |
265 | qemu_real_host_page_size = system_info.dwPageSize; | |
266 | } | |
267 | #else | |
268 | qemu_real_host_page_size = getpagesize(); | |
269 | #endif | |
83fb7adf FB |
270 | if (qemu_host_page_size == 0) |
271 | qemu_host_page_size = qemu_real_host_page_size; | |
272 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
273 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
274 | qemu_host_page_bits = 0; | |
275 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
276 | qemu_host_page_bits++; | |
277 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
50a9569b | 278 | |
2e9a5713 | 279 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
50a9569b | 280 | { |
f01576f1 JL |
281 | #ifdef HAVE_KINFO_GETVMMAP |
282 | struct kinfo_vmentry *freep; | |
283 | int i, cnt; | |
284 | ||
285 | freep = kinfo_getvmmap(getpid(), &cnt); | |
286 | if (freep) { | |
287 | mmap_lock(); | |
288 | for (i = 0; i < cnt; i++) { | |
289 | unsigned long startaddr, endaddr; | |
290 | ||
291 | startaddr = freep[i].kve_start; | |
292 | endaddr = freep[i].kve_end; | |
293 | if (h2g_valid(startaddr)) { | |
294 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
295 | ||
296 | if (h2g_valid(endaddr)) { | |
297 | endaddr = h2g(endaddr); | |
fd436907 | 298 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
299 | } else { |
300 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
301 | endaddr = ~0ul; | |
fd436907 | 302 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
303 | #endif |
304 | } | |
305 | } | |
306 | } | |
307 | free(freep); | |
308 | mmap_unlock(); | |
309 | } | |
310 | #else | |
50a9569b | 311 | FILE *f; |
50a9569b | 312 | |
0776590d | 313 | last_brk = (unsigned long)sbrk(0); |
5cd2c5b6 | 314 | |
fd436907 | 315 | f = fopen("/compat/linux/proc/self/maps", "r"); |
50a9569b | 316 | if (f) { |
5cd2c5b6 RH |
317 | mmap_lock(); |
318 | ||
50a9569b | 319 | do { |
5cd2c5b6 RH |
320 | unsigned long startaddr, endaddr; |
321 | int n; | |
322 | ||
323 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
324 | ||
325 | if (n == 2 && h2g_valid(startaddr)) { | |
326 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
327 | ||
328 | if (h2g_valid(endaddr)) { | |
329 | endaddr = h2g(endaddr); | |
330 | } else { | |
331 | endaddr = ~0ul; | |
332 | } | |
333 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
50a9569b AZ |
334 | } |
335 | } while (!feof(f)); | |
5cd2c5b6 | 336 | |
50a9569b | 337 | fclose(f); |
5cd2c5b6 | 338 | mmap_unlock(); |
50a9569b | 339 | } |
f01576f1 | 340 | #endif |
50a9569b AZ |
341 | } |
342 | #endif | |
54936004 FB |
343 | } |
344 | ||
41c1b1c9 | 345 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
54936004 | 346 | { |
41c1b1c9 PB |
347 | PageDesc *pd; |
348 | void **lp; | |
349 | int i; | |
350 | ||
5cd2c5b6 | 351 | #if defined(CONFIG_USER_ONLY) |
2e9a5713 | 352 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ |
5cd2c5b6 RH |
353 | # define ALLOC(P, SIZE) \ |
354 | do { \ | |
355 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
356 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
5cd2c5b6 RH |
357 | } while (0) |
358 | #else | |
359 | # define ALLOC(P, SIZE) \ | |
360 | do { P = qemu_mallocz(SIZE); } while (0) | |
17e2377a | 361 | #endif |
434929bf | 362 | |
5cd2c5b6 RH |
363 | /* Level 1. Always allocated. */ |
364 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
365 | ||
366 | /* Level 2..N-1. */ | |
367 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
368 | void **p = *lp; | |
369 | ||
370 | if (p == NULL) { | |
371 | if (!alloc) { | |
372 | return NULL; | |
373 | } | |
374 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
375 | *lp = p; | |
17e2377a | 376 | } |
5cd2c5b6 RH |
377 | |
378 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
379 | } | |
380 | ||
381 | pd = *lp; | |
382 | if (pd == NULL) { | |
383 | if (!alloc) { | |
384 | return NULL; | |
385 | } | |
386 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
387 | *lp = pd; | |
54936004 | 388 | } |
5cd2c5b6 RH |
389 | |
390 | #undef ALLOC | |
5cd2c5b6 RH |
391 | |
392 | return pd + (index & (L2_SIZE - 1)); | |
54936004 FB |
393 | } |
394 | ||
41c1b1c9 | 395 | static inline PageDesc *page_find(tb_page_addr_t index) |
54936004 | 396 | { |
5cd2c5b6 | 397 | return page_find_alloc(index, 0); |
fd6ce8f6 FB |
398 | } |
399 | ||
6d9a1304 | 400 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 401 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 402 | { |
e3f4e2a4 | 403 | PhysPageDesc *pd; |
5cd2c5b6 RH |
404 | void **lp; |
405 | int i; | |
92e873b9 | 406 | |
5cd2c5b6 RH |
407 | /* Level 1. Always allocated. */ |
408 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); | |
108c49b8 | 409 | |
5cd2c5b6 RH |
410 | /* Level 2..N-1. */ |
411 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
412 | void **p = *lp; | |
413 | if (p == NULL) { | |
414 | if (!alloc) { | |
415 | return NULL; | |
416 | } | |
417 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); | |
418 | } | |
419 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
108c49b8 | 420 | } |
5cd2c5b6 | 421 | |
e3f4e2a4 | 422 | pd = *lp; |
5cd2c5b6 | 423 | if (pd == NULL) { |
e3f4e2a4 | 424 | int i; |
5cd2c5b6 RH |
425 | |
426 | if (!alloc) { | |
108c49b8 | 427 | return NULL; |
5cd2c5b6 RH |
428 | } |
429 | ||
430 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); | |
431 | ||
67c4d23c | 432 | for (i = 0; i < L2_SIZE; i++) { |
5cd2c5b6 RH |
433 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
434 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; | |
67c4d23c | 435 | } |
92e873b9 | 436 | } |
5cd2c5b6 RH |
437 | |
438 | return pd + (index & (L2_SIZE - 1)); | |
92e873b9 FB |
439 | } |
440 | ||
c227f099 | 441 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 442 | { |
108c49b8 | 443 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
444 | } |
445 | ||
c227f099 AL |
446 | static void tlb_protect_code(ram_addr_t ram_addr); |
447 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 448 | target_ulong vaddr); |
c8a706fe PB |
449 | #define mmap_lock() do { } while(0) |
450 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 451 | #endif |
fd6ce8f6 | 452 | |
4369415f FB |
453 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
454 | ||
455 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 456 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
457 | user mode. It will change when a dedicated libc will be used */ |
458 | #define USE_STATIC_CODE_GEN_BUFFER | |
459 | #endif | |
460 | ||
461 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
ebf50fb3 AJ |
462 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
463 | __attribute__((aligned (CODE_GEN_ALIGN))); | |
4369415f FB |
464 | #endif |
465 | ||
8fcd3692 | 466 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 467 | { |
4369415f FB |
468 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
469 | code_gen_buffer = static_code_gen_buffer; | |
470 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
471 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
472 | #else | |
26a5f13b FB |
473 | code_gen_buffer_size = tb_size; |
474 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
475 | #if defined(CONFIG_USER_ONLY) |
476 | /* in user mode, phys_ram_size is not meaningful */ | |
477 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
478 | #else | |
ccbb4d44 | 479 | /* XXX: needs adjustments */ |
94a6b54f | 480 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 481 | #endif |
26a5f13b FB |
482 | } |
483 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
484 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
485 | /* The code gen buffer location may have constraints depending on | |
486 | the host cpu and OS */ | |
487 | #if defined(__linux__) | |
488 | { | |
489 | int flags; | |
141ac468 BS |
490 | void *start = NULL; |
491 | ||
26a5f13b FB |
492 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
493 | #if defined(__x86_64__) | |
494 | flags |= MAP_32BIT; | |
495 | /* Cannot map more than that */ | |
496 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
497 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
498 | #elif defined(__sparc_v9__) |
499 | // Map the buffer below 2G, so we can use direct calls and branches | |
500 | flags |= MAP_FIXED; | |
501 | start = (void *) 0x60000000UL; | |
502 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
503 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 504 | #elif defined(__arm__) |
63d41246 | 505 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
506 | flags |= MAP_FIXED; |
507 | start = (void *) 0x01000000UL; | |
508 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
509 | code_gen_buffer_size = 16 * 1024 * 1024; | |
eba0b893 RH |
510 | #elif defined(__s390x__) |
511 | /* Map the buffer so that we can use direct calls and branches. */ | |
512 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
513 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { | |
514 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; | |
515 | } | |
516 | start = (void *)0x90000000UL; | |
26a5f13b | 517 | #endif |
141ac468 BS |
518 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
519 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
520 | flags, -1, 0); |
521 | if (code_gen_buffer == MAP_FAILED) { | |
522 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
523 | exit(1); | |
524 | } | |
525 | } | |
a167ba50 | 526 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
06e67a82 AL |
527 | { |
528 | int flags; | |
529 | void *addr = NULL; | |
530 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
531 | #if defined(__x86_64__) | |
532 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
533 | * 0x40000000 is free */ | |
534 | flags |= MAP_FIXED; | |
535 | addr = (void *)0x40000000; | |
536 | /* Cannot map more than that */ | |
537 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
538 | code_gen_buffer_size = (800 * 1024 * 1024); | |
539 | #endif | |
540 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
541 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
542 | flags, -1, 0); | |
543 | if (code_gen_buffer == MAP_FAILED) { | |
544 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
545 | exit(1); | |
546 | } | |
547 | } | |
26a5f13b FB |
548 | #else |
549 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
550 | map_exec(code_gen_buffer, code_gen_buffer_size); |
551 | #endif | |
4369415f | 552 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
553 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
554 | code_gen_buffer_max_size = code_gen_buffer_size - | |
239fda31 | 555 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); |
26a5f13b FB |
556 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
557 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
558 | } | |
559 | ||
560 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
561 | (in bytes) allocated to the translation buffer. Zero means default | |
562 | size. */ | |
563 | void cpu_exec_init_all(unsigned long tb_size) | |
564 | { | |
26a5f13b FB |
565 | cpu_gen_init(); |
566 | code_gen_alloc(tb_size); | |
567 | code_gen_ptr = code_gen_buffer; | |
4369415f | 568 | page_init(); |
e2eef170 | 569 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 570 | io_mem_init(); |
e2eef170 | 571 | #endif |
9002ec79 RH |
572 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
573 | /* There's no guest base to take into account, so go ahead and | |
574 | initialize the prologue now. */ | |
575 | tcg_prologue_init(&tcg_ctx); | |
576 | #endif | |
26a5f13b FB |
577 | } |
578 | ||
9656f324 PB |
579 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
580 | ||
e59fb374 | 581 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
582 | { |
583 | CPUState *env = opaque; | |
9656f324 | 584 | |
3098dba0 AJ |
585 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
586 | version_id is increased. */ | |
587 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
588 | tlb_flush(env, 1); |
589 | ||
590 | return 0; | |
591 | } | |
e7f4eff7 JQ |
592 | |
593 | static const VMStateDescription vmstate_cpu_common = { | |
594 | .name = "cpu_common", | |
595 | .version_id = 1, | |
596 | .minimum_version_id = 1, | |
597 | .minimum_version_id_old = 1, | |
e7f4eff7 JQ |
598 | .post_load = cpu_common_post_load, |
599 | .fields = (VMStateField []) { | |
600 | VMSTATE_UINT32(halted, CPUState), | |
601 | VMSTATE_UINT32(interrupt_request, CPUState), | |
602 | VMSTATE_END_OF_LIST() | |
603 | } | |
604 | }; | |
9656f324 PB |
605 | #endif |
606 | ||
950f1472 GC |
607 | CPUState *qemu_get_cpu(int cpu) |
608 | { | |
609 | CPUState *env = first_cpu; | |
610 | ||
611 | while (env) { | |
612 | if (env->cpu_index == cpu) | |
613 | break; | |
614 | env = env->next_cpu; | |
615 | } | |
616 | ||
617 | return env; | |
618 | } | |
619 | ||
6a00d601 | 620 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 621 | { |
6a00d601 FB |
622 | CPUState **penv; |
623 | int cpu_index; | |
624 | ||
c2764719 PB |
625 | #if defined(CONFIG_USER_ONLY) |
626 | cpu_list_lock(); | |
627 | #endif | |
6a00d601 FB |
628 | env->next_cpu = NULL; |
629 | penv = &first_cpu; | |
630 | cpu_index = 0; | |
631 | while (*penv != NULL) { | |
1e9fa730 | 632 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
633 | cpu_index++; |
634 | } | |
635 | env->cpu_index = cpu_index; | |
268a362c | 636 | env->numa_node = 0; |
72cf2d4f BS |
637 | QTAILQ_INIT(&env->breakpoints); |
638 | QTAILQ_INIT(&env->watchpoints); | |
6a00d601 | 639 | *penv = env; |
c2764719 PB |
640 | #if defined(CONFIG_USER_ONLY) |
641 | cpu_list_unlock(); | |
642 | #endif | |
b3c7724c | 643 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
0be71e32 AW |
644 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
645 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, | |
b3c7724c PB |
646 | cpu_save, cpu_load, env); |
647 | #endif | |
fd6ce8f6 FB |
648 | } |
649 | ||
9fa3e853 FB |
650 | static inline void invalidate_page_bitmap(PageDesc *p) |
651 | { | |
652 | if (p->code_bitmap) { | |
59817ccb | 653 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
654 | p->code_bitmap = NULL; |
655 | } | |
656 | p->code_write_count = 0; | |
657 | } | |
658 | ||
5cd2c5b6 RH |
659 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
660 | ||
661 | static void page_flush_tb_1 (int level, void **lp) | |
fd6ce8f6 | 662 | { |
5cd2c5b6 | 663 | int i; |
fd6ce8f6 | 664 | |
5cd2c5b6 RH |
665 | if (*lp == NULL) { |
666 | return; | |
667 | } | |
668 | if (level == 0) { | |
669 | PageDesc *pd = *lp; | |
7296abac | 670 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
671 | pd[i].first_tb = NULL; |
672 | invalidate_page_bitmap(pd + i); | |
fd6ce8f6 | 673 | } |
5cd2c5b6 RH |
674 | } else { |
675 | void **pp = *lp; | |
7296abac | 676 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
677 | page_flush_tb_1 (level - 1, pp + i); |
678 | } | |
679 | } | |
680 | } | |
681 | ||
682 | static void page_flush_tb(void) | |
683 | { | |
684 | int i; | |
685 | for (i = 0; i < V_L1_SIZE; i++) { | |
686 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
fd6ce8f6 FB |
687 | } |
688 | } | |
689 | ||
690 | /* flush all the translation blocks */ | |
d4e8164f | 691 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 692 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 693 | { |
6a00d601 | 694 | CPUState *env; |
0124311e | 695 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
696 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
697 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
698 | nb_tbs, nb_tbs > 0 ? | |
699 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 700 | #endif |
26a5f13b | 701 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
702 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
703 | ||
fd6ce8f6 | 704 | nb_tbs = 0; |
3b46e624 | 705 | |
6a00d601 FB |
706 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
707 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
708 | } | |
9fa3e853 | 709 | |
8a8a608f | 710 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 711 | page_flush_tb(); |
9fa3e853 | 712 | |
fd6ce8f6 | 713 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
714 | /* XXX: flush processor icache at this point if cache flush is |
715 | expensive */ | |
e3db7226 | 716 | tb_flush_count++; |
fd6ce8f6 FB |
717 | } |
718 | ||
719 | #ifdef DEBUG_TB_CHECK | |
720 | ||
bc98a7ef | 721 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
722 | { |
723 | TranslationBlock *tb; | |
724 | int i; | |
725 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
726 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
727 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
728 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
729 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
730 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
731 | " PC=%08lx size=%04x\n", | |
99773bd4 | 732 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
733 | } |
734 | } | |
735 | } | |
736 | } | |
737 | ||
738 | /* verify that all the pages have correct rights for code */ | |
739 | static void tb_page_check(void) | |
740 | { | |
741 | TranslationBlock *tb; | |
742 | int i, flags1, flags2; | |
3b46e624 | 743 | |
99773bd4 PB |
744 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
745 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
746 | flags1 = page_get_flags(tb->pc); |
747 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
748 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
749 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 750 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
751 | } |
752 | } | |
753 | } | |
754 | } | |
755 | ||
756 | #endif | |
757 | ||
758 | /* invalidate one TB */ | |
759 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
760 | int next_offset) | |
761 | { | |
762 | TranslationBlock *tb1; | |
763 | for(;;) { | |
764 | tb1 = *ptb; | |
765 | if (tb1 == tb) { | |
766 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
767 | break; | |
768 | } | |
769 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
770 | } | |
771 | } | |
772 | ||
9fa3e853 FB |
773 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
774 | { | |
775 | TranslationBlock *tb1; | |
776 | unsigned int n1; | |
777 | ||
778 | for(;;) { | |
779 | tb1 = *ptb; | |
780 | n1 = (long)tb1 & 3; | |
781 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
782 | if (tb1 == tb) { | |
783 | *ptb = tb1->page_next[n1]; | |
784 | break; | |
785 | } | |
786 | ptb = &tb1->page_next[n1]; | |
787 | } | |
788 | } | |
789 | ||
d4e8164f FB |
790 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
791 | { | |
792 | TranslationBlock *tb1, **ptb; | |
793 | unsigned int n1; | |
794 | ||
795 | ptb = &tb->jmp_next[n]; | |
796 | tb1 = *ptb; | |
797 | if (tb1) { | |
798 | /* find tb(n) in circular list */ | |
799 | for(;;) { | |
800 | tb1 = *ptb; | |
801 | n1 = (long)tb1 & 3; | |
802 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
803 | if (n1 == n && tb1 == tb) | |
804 | break; | |
805 | if (n1 == 2) { | |
806 | ptb = &tb1->jmp_first; | |
807 | } else { | |
808 | ptb = &tb1->jmp_next[n1]; | |
809 | } | |
810 | } | |
811 | /* now we can suppress tb(n) from the list */ | |
812 | *ptb = tb->jmp_next[n]; | |
813 | ||
814 | tb->jmp_next[n] = NULL; | |
815 | } | |
816 | } | |
817 | ||
818 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
819 | another TB */ | |
820 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
821 | { | |
822 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
823 | } | |
824 | ||
41c1b1c9 | 825 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
fd6ce8f6 | 826 | { |
6a00d601 | 827 | CPUState *env; |
8a40a180 | 828 | PageDesc *p; |
d4e8164f | 829 | unsigned int h, n1; |
41c1b1c9 | 830 | tb_page_addr_t phys_pc; |
8a40a180 | 831 | TranslationBlock *tb1, *tb2; |
3b46e624 | 832 | |
8a40a180 FB |
833 | /* remove the TB from the hash list */ |
834 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
835 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 836 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
837 | offsetof(TranslationBlock, phys_hash_next)); |
838 | ||
839 | /* remove the TB from the page list */ | |
840 | if (tb->page_addr[0] != page_addr) { | |
841 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
842 | tb_page_remove(&p->first_tb, tb); | |
843 | invalidate_page_bitmap(p); | |
844 | } | |
845 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
846 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
847 | tb_page_remove(&p->first_tb, tb); | |
848 | invalidate_page_bitmap(p); | |
849 | } | |
850 | ||
36bdbe54 | 851 | tb_invalidated_flag = 1; |
59817ccb | 852 | |
fd6ce8f6 | 853 | /* remove the TB from the hash list */ |
8a40a180 | 854 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
855 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
856 | if (env->tb_jmp_cache[h] == tb) | |
857 | env->tb_jmp_cache[h] = NULL; | |
858 | } | |
d4e8164f FB |
859 | |
860 | /* suppress this TB from the two jump lists */ | |
861 | tb_jmp_remove(tb, 0); | |
862 | tb_jmp_remove(tb, 1); | |
863 | ||
864 | /* suppress any remaining jumps to this TB */ | |
865 | tb1 = tb->jmp_first; | |
866 | for(;;) { | |
867 | n1 = (long)tb1 & 3; | |
868 | if (n1 == 2) | |
869 | break; | |
870 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
871 | tb2 = tb1->jmp_next[n1]; | |
872 | tb_reset_jump(tb1, n1); | |
873 | tb1->jmp_next[n1] = NULL; | |
874 | tb1 = tb2; | |
875 | } | |
876 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 877 | |
e3db7226 | 878 | tb_phys_invalidate_count++; |
9fa3e853 FB |
879 | } |
880 | ||
881 | static inline void set_bits(uint8_t *tab, int start, int len) | |
882 | { | |
883 | int end, mask, end1; | |
884 | ||
885 | end = start + len; | |
886 | tab += start >> 3; | |
887 | mask = 0xff << (start & 7); | |
888 | if ((start & ~7) == (end & ~7)) { | |
889 | if (start < end) { | |
890 | mask &= ~(0xff << (end & 7)); | |
891 | *tab |= mask; | |
892 | } | |
893 | } else { | |
894 | *tab++ |= mask; | |
895 | start = (start + 8) & ~7; | |
896 | end1 = end & ~7; | |
897 | while (start < end1) { | |
898 | *tab++ = 0xff; | |
899 | start += 8; | |
900 | } | |
901 | if (start < end) { | |
902 | mask = ~(0xff << (end & 7)); | |
903 | *tab |= mask; | |
904 | } | |
905 | } | |
906 | } | |
907 | ||
908 | static void build_page_bitmap(PageDesc *p) | |
909 | { | |
910 | int n, tb_start, tb_end; | |
911 | TranslationBlock *tb; | |
3b46e624 | 912 | |
b2a7081a | 913 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
914 | |
915 | tb = p->first_tb; | |
916 | while (tb != NULL) { | |
917 | n = (long)tb & 3; | |
918 | tb = (TranslationBlock *)((long)tb & ~3); | |
919 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
920 | if (n == 0) { | |
921 | /* NOTE: tb_end may be after the end of the page, but | |
922 | it is not a problem */ | |
923 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
924 | tb_end = tb_start + tb->size; | |
925 | if (tb_end > TARGET_PAGE_SIZE) | |
926 | tb_end = TARGET_PAGE_SIZE; | |
927 | } else { | |
928 | tb_start = 0; | |
929 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
930 | } | |
931 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
932 | tb = tb->page_next[n]; | |
933 | } | |
934 | } | |
935 | ||
2e70f6ef PB |
936 | TranslationBlock *tb_gen_code(CPUState *env, |
937 | target_ulong pc, target_ulong cs_base, | |
938 | int flags, int cflags) | |
d720b93d FB |
939 | { |
940 | TranslationBlock *tb; | |
941 | uint8_t *tc_ptr; | |
41c1b1c9 PB |
942 | tb_page_addr_t phys_pc, phys_page2; |
943 | target_ulong virt_page2; | |
d720b93d FB |
944 | int code_gen_size; |
945 | ||
41c1b1c9 | 946 | phys_pc = get_page_addr_code(env, pc); |
c27004ec | 947 | tb = tb_alloc(pc); |
d720b93d FB |
948 | if (!tb) { |
949 | /* flush must be done */ | |
950 | tb_flush(env); | |
951 | /* cannot fail at this point */ | |
c27004ec | 952 | tb = tb_alloc(pc); |
2e70f6ef PB |
953 | /* Don't forget to invalidate previous TB info. */ |
954 | tb_invalidated_flag = 1; | |
d720b93d FB |
955 | } |
956 | tc_ptr = code_gen_ptr; | |
957 | tb->tc_ptr = tc_ptr; | |
958 | tb->cs_base = cs_base; | |
959 | tb->flags = flags; | |
960 | tb->cflags = cflags; | |
d07bde88 | 961 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 962 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 963 | |
d720b93d | 964 | /* check next page if needed */ |
c27004ec | 965 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 966 | phys_page2 = -1; |
c27004ec | 967 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
41c1b1c9 | 968 | phys_page2 = get_page_addr_code(env, virt_page2); |
d720b93d | 969 | } |
41c1b1c9 | 970 | tb_link_page(tb, phys_pc, phys_page2); |
2e70f6ef | 971 | return tb; |
d720b93d | 972 | } |
3b46e624 | 973 | |
9fa3e853 FB |
974 | /* invalidate all TBs which intersect with the target physical page |
975 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
976 | the same physical page. 'is_cpu_write_access' should be true if called |
977 | from a real cpu write access: the virtual CPU will exit the current | |
978 | TB if code is modified inside this TB. */ | |
41c1b1c9 | 979 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
d720b93d FB |
980 | int is_cpu_write_access) |
981 | { | |
6b917547 | 982 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 983 | CPUState *env = cpu_single_env; |
41c1b1c9 | 984 | tb_page_addr_t tb_start, tb_end; |
6b917547 AL |
985 | PageDesc *p; |
986 | int n; | |
987 | #ifdef TARGET_HAS_PRECISE_SMC | |
988 | int current_tb_not_found = is_cpu_write_access; | |
989 | TranslationBlock *current_tb = NULL; | |
990 | int current_tb_modified = 0; | |
991 | target_ulong current_pc = 0; | |
992 | target_ulong current_cs_base = 0; | |
993 | int current_flags = 0; | |
994 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
995 | |
996 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 997 | if (!p) |
9fa3e853 | 998 | return; |
5fafdf24 | 999 | if (!p->code_bitmap && |
d720b93d FB |
1000 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
1001 | is_cpu_write_access) { | |
9fa3e853 FB |
1002 | /* build code bitmap */ |
1003 | build_page_bitmap(p); | |
1004 | } | |
1005 | ||
1006 | /* we remove all the TBs in the range [start, end[ */ | |
1007 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
1008 | tb = p->first_tb; | |
1009 | while (tb != NULL) { | |
1010 | n = (long)tb & 3; | |
1011 | tb = (TranslationBlock *)((long)tb & ~3); | |
1012 | tb_next = tb->page_next[n]; | |
1013 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1014 | if (n == 0) { | |
1015 | /* NOTE: tb_end may be after the end of the page, but | |
1016 | it is not a problem */ | |
1017 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1018 | tb_end = tb_start + tb->size; | |
1019 | } else { | |
1020 | tb_start = tb->page_addr[1]; | |
1021 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1022 | } | |
1023 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
1024 | #ifdef TARGET_HAS_PRECISE_SMC |
1025 | if (current_tb_not_found) { | |
1026 | current_tb_not_found = 0; | |
1027 | current_tb = NULL; | |
2e70f6ef | 1028 | if (env->mem_io_pc) { |
d720b93d | 1029 | /* now we have a real cpu fault */ |
2e70f6ef | 1030 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
1031 | } |
1032 | } | |
1033 | if (current_tb == tb && | |
2e70f6ef | 1034 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1035 | /* If we are modifying the current TB, we must stop |
1036 | its execution. We could be more precise by checking | |
1037 | that the modification is after the current PC, but it | |
1038 | would require a specialized function to partially | |
1039 | restore the CPU state */ | |
3b46e624 | 1040 | |
d720b93d | 1041 | current_tb_modified = 1; |
5fafdf24 | 1042 | cpu_restore_state(current_tb, env, |
2e70f6ef | 1043 | env->mem_io_pc, NULL); |
6b917547 AL |
1044 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1045 | ¤t_flags); | |
d720b93d FB |
1046 | } |
1047 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
1048 | /* we need to do that to handle the case where a signal |
1049 | occurs while doing tb_phys_invalidate() */ | |
1050 | saved_tb = NULL; | |
1051 | if (env) { | |
1052 | saved_tb = env->current_tb; | |
1053 | env->current_tb = NULL; | |
1054 | } | |
9fa3e853 | 1055 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
1056 | if (env) { |
1057 | env->current_tb = saved_tb; | |
1058 | if (env->interrupt_request && env->current_tb) | |
1059 | cpu_interrupt(env, env->interrupt_request); | |
1060 | } | |
9fa3e853 FB |
1061 | } |
1062 | tb = tb_next; | |
1063 | } | |
1064 | #if !defined(CONFIG_USER_ONLY) | |
1065 | /* if no code remaining, no need to continue to use slow writes */ | |
1066 | if (!p->first_tb) { | |
1067 | invalidate_page_bitmap(p); | |
d720b93d | 1068 | if (is_cpu_write_access) { |
2e70f6ef | 1069 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1070 | } |
1071 | } | |
1072 | #endif | |
1073 | #ifdef TARGET_HAS_PRECISE_SMC | |
1074 | if (current_tb_modified) { | |
1075 | /* we generate a block containing just the instruction | |
1076 | modifying the memory. It will ensure that it cannot modify | |
1077 | itself */ | |
ea1c1802 | 1078 | env->current_tb = NULL; |
2e70f6ef | 1079 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1080 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1081 | } |
fd6ce8f6 | 1082 | #endif |
9fa3e853 | 1083 | } |
fd6ce8f6 | 1084 | |
9fa3e853 | 1085 | /* len must be <= 8 and start must be a multiple of len */ |
41c1b1c9 | 1086 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
9fa3e853 FB |
1087 | { |
1088 | PageDesc *p; | |
1089 | int offset, b; | |
59817ccb | 1090 | #if 0 |
a4193c8a | 1091 | if (1) { |
93fcfe39 AL |
1092 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1093 | cpu_single_env->mem_io_vaddr, len, | |
1094 | cpu_single_env->eip, | |
1095 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1096 | } |
1097 | #endif | |
9fa3e853 | 1098 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1099 | if (!p) |
9fa3e853 FB |
1100 | return; |
1101 | if (p->code_bitmap) { | |
1102 | offset = start & ~TARGET_PAGE_MASK; | |
1103 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1104 | if (b & ((1 << len) - 1)) | |
1105 | goto do_invalidate; | |
1106 | } else { | |
1107 | do_invalidate: | |
d720b93d | 1108 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1109 | } |
1110 | } | |
1111 | ||
9fa3e853 | 1112 | #if !defined(CONFIG_SOFTMMU) |
41c1b1c9 | 1113 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d720b93d | 1114 | unsigned long pc, void *puc) |
9fa3e853 | 1115 | { |
6b917547 | 1116 | TranslationBlock *tb; |
9fa3e853 | 1117 | PageDesc *p; |
6b917547 | 1118 | int n; |
d720b93d | 1119 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1120 | TranslationBlock *current_tb = NULL; |
d720b93d | 1121 | CPUState *env = cpu_single_env; |
6b917547 AL |
1122 | int current_tb_modified = 0; |
1123 | target_ulong current_pc = 0; | |
1124 | target_ulong current_cs_base = 0; | |
1125 | int current_flags = 0; | |
d720b93d | 1126 | #endif |
9fa3e853 FB |
1127 | |
1128 | addr &= TARGET_PAGE_MASK; | |
1129 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1130 | if (!p) |
9fa3e853 FB |
1131 | return; |
1132 | tb = p->first_tb; | |
d720b93d FB |
1133 | #ifdef TARGET_HAS_PRECISE_SMC |
1134 | if (tb && pc != 0) { | |
1135 | current_tb = tb_find_pc(pc); | |
1136 | } | |
1137 | #endif | |
9fa3e853 FB |
1138 | while (tb != NULL) { |
1139 | n = (long)tb & 3; | |
1140 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1141 | #ifdef TARGET_HAS_PRECISE_SMC |
1142 | if (current_tb == tb && | |
2e70f6ef | 1143 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1144 | /* If we are modifying the current TB, we must stop |
1145 | its execution. We could be more precise by checking | |
1146 | that the modification is after the current PC, but it | |
1147 | would require a specialized function to partially | |
1148 | restore the CPU state */ | |
3b46e624 | 1149 | |
d720b93d FB |
1150 | current_tb_modified = 1; |
1151 | cpu_restore_state(current_tb, env, pc, puc); | |
6b917547 AL |
1152 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1153 | ¤t_flags); | |
d720b93d FB |
1154 | } |
1155 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1156 | tb_phys_invalidate(tb, addr); |
1157 | tb = tb->page_next[n]; | |
1158 | } | |
fd6ce8f6 | 1159 | p->first_tb = NULL; |
d720b93d FB |
1160 | #ifdef TARGET_HAS_PRECISE_SMC |
1161 | if (current_tb_modified) { | |
1162 | /* we generate a block containing just the instruction | |
1163 | modifying the memory. It will ensure that it cannot modify | |
1164 | itself */ | |
ea1c1802 | 1165 | env->current_tb = NULL; |
2e70f6ef | 1166 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1167 | cpu_resume_from_signal(env, puc); |
1168 | } | |
1169 | #endif | |
fd6ce8f6 | 1170 | } |
9fa3e853 | 1171 | #endif |
fd6ce8f6 FB |
1172 | |
1173 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1174 | static inline void tb_alloc_page(TranslationBlock *tb, |
41c1b1c9 | 1175 | unsigned int n, tb_page_addr_t page_addr) |
fd6ce8f6 FB |
1176 | { |
1177 | PageDesc *p; | |
9fa3e853 FB |
1178 | TranslationBlock *last_first_tb; |
1179 | ||
1180 | tb->page_addr[n] = page_addr; | |
5cd2c5b6 | 1181 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
9fa3e853 FB |
1182 | tb->page_next[n] = p->first_tb; |
1183 | last_first_tb = p->first_tb; | |
1184 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1185 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1186 | |
107db443 | 1187 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1188 | |
9fa3e853 | 1189 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1190 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1191 | target_ulong addr; |
1192 | PageDesc *p2; | |
9fa3e853 FB |
1193 | int prot; |
1194 | ||
fd6ce8f6 FB |
1195 | /* force the host page as non writable (writes will have a |
1196 | page fault + mprotect overhead) */ | |
53a5960a | 1197 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1198 | prot = 0; |
53a5960a PB |
1199 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1200 | addr += TARGET_PAGE_SIZE) { | |
1201 | ||
1202 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1203 | if (!p2) | |
1204 | continue; | |
1205 | prot |= p2->flags; | |
1206 | p2->flags &= ~PAGE_WRITE; | |
53a5960a | 1207 | } |
5fafdf24 | 1208 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1209 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1210 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1211 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1212 | page_addr); |
fd6ce8f6 | 1213 | #endif |
fd6ce8f6 | 1214 | } |
9fa3e853 FB |
1215 | #else |
1216 | /* if some code is already present, then the pages are already | |
1217 | protected. So we handle the case where only the first TB is | |
1218 | allocated in a physical page */ | |
1219 | if (!last_first_tb) { | |
6a00d601 | 1220 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1221 | } |
1222 | #endif | |
d720b93d FB |
1223 | |
1224 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1225 | } |
1226 | ||
1227 | /* Allocate a new translation block. Flush the translation buffer if | |
1228 | too many translation blocks or too much generated code. */ | |
c27004ec | 1229 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1230 | { |
1231 | TranslationBlock *tb; | |
fd6ce8f6 | 1232 | |
26a5f13b FB |
1233 | if (nb_tbs >= code_gen_max_blocks || |
1234 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1235 | return NULL; |
fd6ce8f6 FB |
1236 | tb = &tbs[nb_tbs++]; |
1237 | tb->pc = pc; | |
b448f2f3 | 1238 | tb->cflags = 0; |
d4e8164f FB |
1239 | return tb; |
1240 | } | |
1241 | ||
2e70f6ef PB |
1242 | void tb_free(TranslationBlock *tb) |
1243 | { | |
bf20dc07 | 1244 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1245 | Ignore the hard cases and just back up if this TB happens to |
1246 | be the last one generated. */ | |
1247 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1248 | code_gen_ptr = tb->tc_ptr; | |
1249 | nb_tbs--; | |
1250 | } | |
1251 | } | |
1252 | ||
9fa3e853 FB |
1253 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1254 | (-1) to indicate that only one page contains the TB. */ | |
41c1b1c9 PB |
1255 | void tb_link_page(TranslationBlock *tb, |
1256 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) | |
d4e8164f | 1257 | { |
9fa3e853 FB |
1258 | unsigned int h; |
1259 | TranslationBlock **ptb; | |
1260 | ||
c8a706fe PB |
1261 | /* Grab the mmap lock to stop another thread invalidating this TB |
1262 | before we are done. */ | |
1263 | mmap_lock(); | |
9fa3e853 FB |
1264 | /* add in the physical hash table */ |
1265 | h = tb_phys_hash_func(phys_pc); | |
1266 | ptb = &tb_phys_hash[h]; | |
1267 | tb->phys_hash_next = *ptb; | |
1268 | *ptb = tb; | |
fd6ce8f6 FB |
1269 | |
1270 | /* add in the page list */ | |
9fa3e853 FB |
1271 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1272 | if (phys_page2 != -1) | |
1273 | tb_alloc_page(tb, 1, phys_page2); | |
1274 | else | |
1275 | tb->page_addr[1] = -1; | |
9fa3e853 | 1276 | |
d4e8164f FB |
1277 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1278 | tb->jmp_next[0] = NULL; | |
1279 | tb->jmp_next[1] = NULL; | |
1280 | ||
1281 | /* init original jump addresses */ | |
1282 | if (tb->tb_next_offset[0] != 0xffff) | |
1283 | tb_reset_jump(tb, 0); | |
1284 | if (tb->tb_next_offset[1] != 0xffff) | |
1285 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1286 | |
1287 | #ifdef DEBUG_TB_CHECK | |
1288 | tb_page_check(); | |
1289 | #endif | |
c8a706fe | 1290 | mmap_unlock(); |
fd6ce8f6 FB |
1291 | } |
1292 | ||
9fa3e853 FB |
1293 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1294 | tb[1].tc_ptr. Return NULL if not found */ | |
1295 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1296 | { |
9fa3e853 FB |
1297 | int m_min, m_max, m; |
1298 | unsigned long v; | |
1299 | TranslationBlock *tb; | |
a513fe19 FB |
1300 | |
1301 | if (nb_tbs <= 0) | |
1302 | return NULL; | |
1303 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1304 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1305 | return NULL; | |
1306 | /* binary search (cf Knuth) */ | |
1307 | m_min = 0; | |
1308 | m_max = nb_tbs - 1; | |
1309 | while (m_min <= m_max) { | |
1310 | m = (m_min + m_max) >> 1; | |
1311 | tb = &tbs[m]; | |
1312 | v = (unsigned long)tb->tc_ptr; | |
1313 | if (v == tc_ptr) | |
1314 | return tb; | |
1315 | else if (tc_ptr < v) { | |
1316 | m_max = m - 1; | |
1317 | } else { | |
1318 | m_min = m + 1; | |
1319 | } | |
5fafdf24 | 1320 | } |
a513fe19 FB |
1321 | return &tbs[m_max]; |
1322 | } | |
7501267e | 1323 | |
ea041c0e FB |
1324 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1325 | ||
1326 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1327 | { | |
1328 | TranslationBlock *tb1, *tb_next, **ptb; | |
1329 | unsigned int n1; | |
1330 | ||
1331 | tb1 = tb->jmp_next[n]; | |
1332 | if (tb1 != NULL) { | |
1333 | /* find head of list */ | |
1334 | for(;;) { | |
1335 | n1 = (long)tb1 & 3; | |
1336 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1337 | if (n1 == 2) | |
1338 | break; | |
1339 | tb1 = tb1->jmp_next[n1]; | |
1340 | } | |
1341 | /* we are now sure now that tb jumps to tb1 */ | |
1342 | tb_next = tb1; | |
1343 | ||
1344 | /* remove tb from the jmp_first list */ | |
1345 | ptb = &tb_next->jmp_first; | |
1346 | for(;;) { | |
1347 | tb1 = *ptb; | |
1348 | n1 = (long)tb1 & 3; | |
1349 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1350 | if (n1 == n && tb1 == tb) | |
1351 | break; | |
1352 | ptb = &tb1->jmp_next[n1]; | |
1353 | } | |
1354 | *ptb = tb->jmp_next[n]; | |
1355 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1356 | |
ea041c0e FB |
1357 | /* suppress the jump to next tb in generated code */ |
1358 | tb_reset_jump(tb, n); | |
1359 | ||
0124311e | 1360 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1361 | tb_reset_jump_recursive(tb_next); |
1362 | } | |
1363 | } | |
1364 | ||
1365 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1366 | { | |
1367 | tb_reset_jump_recursive2(tb, 0); | |
1368 | tb_reset_jump_recursive2(tb, 1); | |
1369 | } | |
1370 | ||
1fddef4b | 1371 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1372 | #if defined(CONFIG_USER_ONLY) |
1373 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1374 | { | |
1375 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1376 | } | |
1377 | #else | |
d720b93d FB |
1378 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1379 | { | |
c227f099 | 1380 | target_phys_addr_t addr; |
9b3c35e0 | 1381 | target_ulong pd; |
c227f099 | 1382 | ram_addr_t ram_addr; |
c2f07f81 | 1383 | PhysPageDesc *p; |
d720b93d | 1384 | |
c2f07f81 PB |
1385 | addr = cpu_get_phys_page_debug(env, pc); |
1386 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1387 | if (!p) { | |
1388 | pd = IO_MEM_UNASSIGNED; | |
1389 | } else { | |
1390 | pd = p->phys_offset; | |
1391 | } | |
1392 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1393 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1394 | } |
c27004ec | 1395 | #endif |
94df27fd | 1396 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1397 | |
c527ee8f PB |
1398 | #if defined(CONFIG_USER_ONLY) |
1399 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1400 | ||
1401 | { | |
1402 | } | |
1403 | ||
1404 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1405 | int flags, CPUWatchpoint **watchpoint) | |
1406 | { | |
1407 | return -ENOSYS; | |
1408 | } | |
1409 | #else | |
6658ffb8 | 1410 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1411 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1412 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1413 | { |
b4051334 | 1414 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1415 | CPUWatchpoint *wp; |
6658ffb8 | 1416 | |
b4051334 AL |
1417 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1418 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1419 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1420 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1421 | return -EINVAL; | |
1422 | } | |
a1d1bb31 | 1423 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1424 | |
1425 | wp->vaddr = addr; | |
b4051334 | 1426 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1427 | wp->flags = flags; |
1428 | ||
2dc9f411 | 1429 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1430 | if (flags & BP_GDB) |
72cf2d4f | 1431 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1432 | else |
72cf2d4f | 1433 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1434 | |
6658ffb8 | 1435 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1436 | |
1437 | if (watchpoint) | |
1438 | *watchpoint = wp; | |
1439 | return 0; | |
6658ffb8 PB |
1440 | } |
1441 | ||
a1d1bb31 AL |
1442 | /* Remove a specific watchpoint. */ |
1443 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1444 | int flags) | |
6658ffb8 | 1445 | { |
b4051334 | 1446 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1447 | CPUWatchpoint *wp; |
6658ffb8 | 1448 | |
72cf2d4f | 1449 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1450 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1451 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1452 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1453 | return 0; |
1454 | } | |
1455 | } | |
a1d1bb31 | 1456 | return -ENOENT; |
6658ffb8 PB |
1457 | } |
1458 | ||
a1d1bb31 AL |
1459 | /* Remove a specific watchpoint by reference. */ |
1460 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1461 | { | |
72cf2d4f | 1462 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1463 | |
a1d1bb31 AL |
1464 | tlb_flush_page(env, watchpoint->vaddr); |
1465 | ||
1466 | qemu_free(watchpoint); | |
1467 | } | |
1468 | ||
1469 | /* Remove all matching watchpoints. */ | |
1470 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1471 | { | |
c0ce998e | 1472 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1473 | |
72cf2d4f | 1474 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1475 | if (wp->flags & mask) |
1476 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1477 | } |
7d03f82f | 1478 | } |
c527ee8f | 1479 | #endif |
7d03f82f | 1480 | |
a1d1bb31 AL |
1481 | /* Add a breakpoint. */ |
1482 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1483 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1484 | { |
1fddef4b | 1485 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1486 | CPUBreakpoint *bp; |
3b46e624 | 1487 | |
a1d1bb31 | 1488 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1489 | |
a1d1bb31 AL |
1490 | bp->pc = pc; |
1491 | bp->flags = flags; | |
1492 | ||
2dc9f411 | 1493 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1494 | if (flags & BP_GDB) |
72cf2d4f | 1495 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1496 | else |
72cf2d4f | 1497 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1498 | |
d720b93d | 1499 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1500 | |
1501 | if (breakpoint) | |
1502 | *breakpoint = bp; | |
4c3a88a2 FB |
1503 | return 0; |
1504 | #else | |
a1d1bb31 | 1505 | return -ENOSYS; |
4c3a88a2 FB |
1506 | #endif |
1507 | } | |
1508 | ||
a1d1bb31 AL |
1509 | /* Remove a specific breakpoint. */ |
1510 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1511 | { | |
7d03f82f | 1512 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1513 | CPUBreakpoint *bp; |
1514 | ||
72cf2d4f | 1515 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1516 | if (bp->pc == pc && bp->flags == flags) { |
1517 | cpu_breakpoint_remove_by_ref(env, bp); | |
1518 | return 0; | |
1519 | } | |
7d03f82f | 1520 | } |
a1d1bb31 AL |
1521 | return -ENOENT; |
1522 | #else | |
1523 | return -ENOSYS; | |
7d03f82f EI |
1524 | #endif |
1525 | } | |
1526 | ||
a1d1bb31 AL |
1527 | /* Remove a specific breakpoint by reference. */ |
1528 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1529 | { |
1fddef4b | 1530 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1531 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1532 | |
a1d1bb31 AL |
1533 | breakpoint_invalidate(env, breakpoint->pc); |
1534 | ||
1535 | qemu_free(breakpoint); | |
1536 | #endif | |
1537 | } | |
1538 | ||
1539 | /* Remove all matching breakpoints. */ | |
1540 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1541 | { | |
1542 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1543 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1544 | |
72cf2d4f | 1545 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1546 | if (bp->flags & mask) |
1547 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1548 | } |
4c3a88a2 FB |
1549 | #endif |
1550 | } | |
1551 | ||
c33a346e FB |
1552 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1553 | CPU loop after each instruction */ | |
1554 | void cpu_single_step(CPUState *env, int enabled) | |
1555 | { | |
1fddef4b | 1556 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1557 | if (env->singlestep_enabled != enabled) { |
1558 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1559 | if (kvm_enabled()) |
1560 | kvm_update_guest_debug(env, 0); | |
1561 | else { | |
ccbb4d44 | 1562 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1563 | /* XXX: only flush what is necessary */ |
1564 | tb_flush(env); | |
1565 | } | |
c33a346e FB |
1566 | } |
1567 | #endif | |
1568 | } | |
1569 | ||
34865134 FB |
1570 | /* enable or disable low levels log */ |
1571 | void cpu_set_log(int log_flags) | |
1572 | { | |
1573 | loglevel = log_flags; | |
1574 | if (loglevel && !logfile) { | |
11fcfab4 | 1575 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1576 | if (!logfile) { |
1577 | perror(logfilename); | |
1578 | _exit(1); | |
1579 | } | |
9fa3e853 FB |
1580 | #if !defined(CONFIG_SOFTMMU) |
1581 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1582 | { | |
b55266b5 | 1583 | static char logfile_buf[4096]; |
9fa3e853 FB |
1584 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1585 | } | |
bf65f53f FN |
1586 | #elif !defined(_WIN32) |
1587 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1588 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1589 | #endif |
e735b91c PB |
1590 | log_append = 1; |
1591 | } | |
1592 | if (!loglevel && logfile) { | |
1593 | fclose(logfile); | |
1594 | logfile = NULL; | |
34865134 FB |
1595 | } |
1596 | } | |
1597 | ||
1598 | void cpu_set_log_filename(const char *filename) | |
1599 | { | |
1600 | logfilename = strdup(filename); | |
e735b91c PB |
1601 | if (logfile) { |
1602 | fclose(logfile); | |
1603 | logfile = NULL; | |
1604 | } | |
1605 | cpu_set_log(loglevel); | |
34865134 | 1606 | } |
c33a346e | 1607 | |
3098dba0 | 1608 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1609 | { |
3098dba0 AJ |
1610 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1611 | problem and hope the cpu will stop of its own accord. For userspace | |
1612 | emulation this often isn't actually as bad as it sounds. Often | |
1613 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1614 | TranslationBlock *tb; |
c227f099 | 1615 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1616 | |
cab1b4bd | 1617 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1618 | tb = env->current_tb; |
1619 | /* if the cpu is currently executing code, we must unlink it and | |
1620 | all the potentially executing TB */ | |
f76cfe56 | 1621 | if (tb) { |
3098dba0 AJ |
1622 | env->current_tb = NULL; |
1623 | tb_reset_jump_recursive(tb); | |
be214e6c | 1624 | } |
cab1b4bd | 1625 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1626 | } |
1627 | ||
1628 | /* mask must never be zero, except for A20 change call */ | |
1629 | void cpu_interrupt(CPUState *env, int mask) | |
1630 | { | |
1631 | int old_mask; | |
be214e6c | 1632 | |
2e70f6ef | 1633 | old_mask = env->interrupt_request; |
68a79315 | 1634 | env->interrupt_request |= mask; |
3098dba0 | 1635 | |
8edac960 AL |
1636 | #ifndef CONFIG_USER_ONLY |
1637 | /* | |
1638 | * If called from iothread context, wake the target cpu in | |
1639 | * case its halted. | |
1640 | */ | |
1641 | if (!qemu_cpu_self(env)) { | |
1642 | qemu_cpu_kick(env); | |
1643 | return; | |
1644 | } | |
1645 | #endif | |
1646 | ||
2e70f6ef | 1647 | if (use_icount) { |
266910c4 | 1648 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1649 | #ifndef CONFIG_USER_ONLY |
2e70f6ef | 1650 | if (!can_do_io(env) |
be214e6c | 1651 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1652 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1653 | } | |
1654 | #endif | |
1655 | } else { | |
3098dba0 | 1656 | cpu_unlink_tb(env); |
ea041c0e FB |
1657 | } |
1658 | } | |
1659 | ||
b54ad049 FB |
1660 | void cpu_reset_interrupt(CPUState *env, int mask) |
1661 | { | |
1662 | env->interrupt_request &= ~mask; | |
1663 | } | |
1664 | ||
3098dba0 AJ |
1665 | void cpu_exit(CPUState *env) |
1666 | { | |
1667 | env->exit_request = 1; | |
1668 | cpu_unlink_tb(env); | |
1669 | } | |
1670 | ||
c7cd6a37 | 1671 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1672 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1673 | "show generated host assembly code for each compiled TB" }, |
1674 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1675 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1676 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1677 | "show micro ops for each compiled TB" }, |
f193c797 | 1678 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1679 | "show micro ops " |
1680 | #ifdef TARGET_I386 | |
1681 | "before eflags optimization and " | |
f193c797 | 1682 | #endif |
e01a1157 | 1683 | "after liveness analysis" }, |
f193c797 FB |
1684 | { CPU_LOG_INT, "int", |
1685 | "show interrupts/exceptions in short format" }, | |
1686 | { CPU_LOG_EXEC, "exec", | |
1687 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1688 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1689 | "show CPU state before block translation" }, |
f193c797 FB |
1690 | #ifdef TARGET_I386 |
1691 | { CPU_LOG_PCALL, "pcall", | |
1692 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1693 | { CPU_LOG_RESET, "cpu_reset", |
1694 | "show CPU state before CPU resets" }, | |
f193c797 | 1695 | #endif |
8e3a9fd2 | 1696 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1697 | { CPU_LOG_IOPORT, "ioport", |
1698 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1699 | #endif |
f193c797 FB |
1700 | { 0, NULL, NULL }, |
1701 | }; | |
1702 | ||
f6f3fbca MT |
1703 | #ifndef CONFIG_USER_ONLY |
1704 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1705 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1706 | ||
1707 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
1708 | ram_addr_t size, | |
1709 | ram_addr_t phys_offset) | |
1710 | { | |
1711 | CPUPhysMemoryClient *client; | |
1712 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1713 | client->set_memory(client, start_addr, size, phys_offset); | |
1714 | } | |
1715 | } | |
1716 | ||
1717 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
1718 | target_phys_addr_t end) | |
1719 | { | |
1720 | CPUPhysMemoryClient *client; | |
1721 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1722 | int r = client->sync_dirty_bitmap(client, start, end); | |
1723 | if (r < 0) | |
1724 | return r; | |
1725 | } | |
1726 | return 0; | |
1727 | } | |
1728 | ||
1729 | static int cpu_notify_migration_log(int enable) | |
1730 | { | |
1731 | CPUPhysMemoryClient *client; | |
1732 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1733 | int r = client->migration_log(client, enable); | |
1734 | if (r < 0) | |
1735 | return r; | |
1736 | } | |
1737 | return 0; | |
1738 | } | |
1739 | ||
5cd2c5b6 RH |
1740 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, |
1741 | int level, void **lp) | |
f6f3fbca | 1742 | { |
5cd2c5b6 | 1743 | int i; |
f6f3fbca | 1744 | |
5cd2c5b6 RH |
1745 | if (*lp == NULL) { |
1746 | return; | |
1747 | } | |
1748 | if (level == 0) { | |
1749 | PhysPageDesc *pd = *lp; | |
7296abac | 1750 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
1751 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
1752 | client->set_memory(client, pd[i].region_offset, | |
1753 | TARGET_PAGE_SIZE, pd[i].phys_offset); | |
f6f3fbca | 1754 | } |
5cd2c5b6 RH |
1755 | } |
1756 | } else { | |
1757 | void **pp = *lp; | |
7296abac | 1758 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 | 1759 | phys_page_for_each_1(client, level - 1, pp + i); |
f6f3fbca MT |
1760 | } |
1761 | } | |
1762 | } | |
1763 | ||
1764 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1765 | { | |
5cd2c5b6 RH |
1766 | int i; |
1767 | for (i = 0; i < P_L1_SIZE; ++i) { | |
1768 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, | |
1769 | l1_phys_map + 1); | |
f6f3fbca | 1770 | } |
f6f3fbca MT |
1771 | } |
1772 | ||
1773 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1774 | { | |
1775 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1776 | phys_page_for_each(client); | |
1777 | } | |
1778 | ||
1779 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1780 | { | |
1781 | QLIST_REMOVE(client, list); | |
1782 | } | |
1783 | #endif | |
1784 | ||
f193c797 FB |
1785 | static int cmp1(const char *s1, int n, const char *s2) |
1786 | { | |
1787 | if (strlen(s2) != n) | |
1788 | return 0; | |
1789 | return memcmp(s1, s2, n) == 0; | |
1790 | } | |
3b46e624 | 1791 | |
f193c797 FB |
1792 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1793 | int cpu_str_to_log_mask(const char *str) | |
1794 | { | |
c7cd6a37 | 1795 | const CPULogItem *item; |
f193c797 FB |
1796 | int mask; |
1797 | const char *p, *p1; | |
1798 | ||
1799 | p = str; | |
1800 | mask = 0; | |
1801 | for(;;) { | |
1802 | p1 = strchr(p, ','); | |
1803 | if (!p1) | |
1804 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1805 | if(cmp1(p,p1-p,"all")) { |
1806 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1807 | mask |= item->mask; | |
1808 | } | |
1809 | } else { | |
f193c797 FB |
1810 | for(item = cpu_log_items; item->mask != 0; item++) { |
1811 | if (cmp1(p, p1 - p, item->name)) | |
1812 | goto found; | |
1813 | } | |
1814 | return 0; | |
8e3a9fd2 | 1815 | } |
f193c797 FB |
1816 | found: |
1817 | mask |= item->mask; | |
1818 | if (*p1 != ',') | |
1819 | break; | |
1820 | p = p1 + 1; | |
1821 | } | |
1822 | return mask; | |
1823 | } | |
ea041c0e | 1824 | |
7501267e FB |
1825 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1826 | { | |
1827 | va_list ap; | |
493ae1f0 | 1828 | va_list ap2; |
7501267e FB |
1829 | |
1830 | va_start(ap, fmt); | |
493ae1f0 | 1831 | va_copy(ap2, ap); |
7501267e FB |
1832 | fprintf(stderr, "qemu: fatal: "); |
1833 | vfprintf(stderr, fmt, ap); | |
1834 | fprintf(stderr, "\n"); | |
1835 | #ifdef TARGET_I386 | |
7fe48483 FB |
1836 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1837 | #else | |
1838 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1839 | #endif |
93fcfe39 AL |
1840 | if (qemu_log_enabled()) { |
1841 | qemu_log("qemu: fatal: "); | |
1842 | qemu_log_vprintf(fmt, ap2); | |
1843 | qemu_log("\n"); | |
f9373291 | 1844 | #ifdef TARGET_I386 |
93fcfe39 | 1845 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1846 | #else |
93fcfe39 | 1847 | log_cpu_state(env, 0); |
f9373291 | 1848 | #endif |
31b1a7b4 | 1849 | qemu_log_flush(); |
93fcfe39 | 1850 | qemu_log_close(); |
924edcae | 1851 | } |
493ae1f0 | 1852 | va_end(ap2); |
f9373291 | 1853 | va_end(ap); |
fd052bf6 RV |
1854 | #if defined(CONFIG_USER_ONLY) |
1855 | { | |
1856 | struct sigaction act; | |
1857 | sigfillset(&act.sa_mask); | |
1858 | act.sa_handler = SIG_DFL; | |
1859 | sigaction(SIGABRT, &act, NULL); | |
1860 | } | |
1861 | #endif | |
7501267e FB |
1862 | abort(); |
1863 | } | |
1864 | ||
c5be9f08 TS |
1865 | CPUState *cpu_copy(CPUState *env) |
1866 | { | |
01ba9816 | 1867 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1868 | CPUState *next_cpu = new_env->next_cpu; |
1869 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1870 | #if defined(TARGET_HAS_ICE) |
1871 | CPUBreakpoint *bp; | |
1872 | CPUWatchpoint *wp; | |
1873 | #endif | |
1874 | ||
c5be9f08 | 1875 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1876 | |
1877 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1878 | new_env->next_cpu = next_cpu; |
1879 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1880 | |
1881 | /* Clone all break/watchpoints. | |
1882 | Note: Once we support ptrace with hw-debug register access, make sure | |
1883 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1884 | QTAILQ_INIT(&env->breakpoints); |
1885 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1886 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1887 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1888 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1889 | } | |
72cf2d4f | 1890 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1891 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1892 | wp->flags, NULL); | |
1893 | } | |
1894 | #endif | |
1895 | ||
c5be9f08 TS |
1896 | return new_env; |
1897 | } | |
1898 | ||
0124311e FB |
1899 | #if !defined(CONFIG_USER_ONLY) |
1900 | ||
5c751e99 EI |
1901 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1902 | { | |
1903 | unsigned int i; | |
1904 | ||
1905 | /* Discard jump cache entries for any tb which might potentially | |
1906 | overlap the flushed page. */ | |
1907 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1908 | memset (&env->tb_jmp_cache[i], 0, | |
1909 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1910 | ||
1911 | i = tb_jmp_cache_hash_page(addr); | |
1912 | memset (&env->tb_jmp_cache[i], 0, | |
1913 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1914 | } | |
1915 | ||
08738984 IK |
1916 | static CPUTLBEntry s_cputlb_empty_entry = { |
1917 | .addr_read = -1, | |
1918 | .addr_write = -1, | |
1919 | .addr_code = -1, | |
1920 | .addend = -1, | |
1921 | }; | |
1922 | ||
ee8b7021 FB |
1923 | /* NOTE: if flush_global is true, also flush global entries (not |
1924 | implemented yet) */ | |
1925 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1926 | { |
33417e70 | 1927 | int i; |
0124311e | 1928 | |
9fa3e853 FB |
1929 | #if defined(DEBUG_TLB) |
1930 | printf("tlb_flush:\n"); | |
1931 | #endif | |
0124311e FB |
1932 | /* must reset current TB so that interrupts cannot modify the |
1933 | links while we are modifying them */ | |
1934 | env->current_tb = NULL; | |
1935 | ||
33417e70 | 1936 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1937 | int mmu_idx; |
1938 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1939 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1940 | } |
33417e70 | 1941 | } |
9fa3e853 | 1942 | |
8a40a180 | 1943 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1944 | |
d4c430a8 PB |
1945 | env->tlb_flush_addr = -1; |
1946 | env->tlb_flush_mask = 0; | |
e3db7226 | 1947 | tlb_flush_count++; |
33417e70 FB |
1948 | } |
1949 | ||
274da6b2 | 1950 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1951 | { |
5fafdf24 | 1952 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1953 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1954 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1955 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1956 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 1957 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 1958 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 1959 | } |
61382a50 FB |
1960 | } |
1961 | ||
2e12669a | 1962 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1963 | { |
8a40a180 | 1964 | int i; |
cfde4bd9 | 1965 | int mmu_idx; |
0124311e | 1966 | |
9fa3e853 | 1967 | #if defined(DEBUG_TLB) |
108c49b8 | 1968 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1969 | #endif |
d4c430a8 PB |
1970 | /* Check if we need to flush due to large pages. */ |
1971 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { | |
1972 | #if defined(DEBUG_TLB) | |
1973 | printf("tlb_flush_page: forced full flush (" | |
1974 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", | |
1975 | env->tlb_flush_addr, env->tlb_flush_mask); | |
1976 | #endif | |
1977 | tlb_flush(env, 1); | |
1978 | return; | |
1979 | } | |
0124311e FB |
1980 | /* must reset current TB so that interrupts cannot modify the |
1981 | links while we are modifying them */ | |
1982 | env->current_tb = NULL; | |
61382a50 FB |
1983 | |
1984 | addr &= TARGET_PAGE_MASK; | |
1985 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
1986 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
1987 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 1988 | |
5c751e99 | 1989 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
1990 | } |
1991 | ||
9fa3e853 FB |
1992 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1993 | can be detected */ | |
c227f099 | 1994 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1995 | { |
5fafdf24 | 1996 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1997 | ram_addr + TARGET_PAGE_SIZE, |
1998 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1999 | } |
2000 | ||
9fa3e853 | 2001 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 2002 | tested for self modifying code */ |
c227f099 | 2003 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 2004 | target_ulong vaddr) |
9fa3e853 | 2005 | { |
f7c11b53 | 2006 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
1ccde1cb FB |
2007 | } |
2008 | ||
5fafdf24 | 2009 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
2010 | unsigned long start, unsigned long length) |
2011 | { | |
2012 | unsigned long addr; | |
84b7b8e7 FB |
2013 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
2014 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 2015 | if ((addr - start) < length) { |
0f459d16 | 2016 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
2017 | } |
2018 | } | |
2019 | } | |
2020 | ||
5579c7f3 | 2021 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 2022 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 2023 | int dirty_flags) |
1ccde1cb FB |
2024 | { |
2025 | CPUState *env; | |
4f2ac237 | 2026 | unsigned long length, start1; |
f7c11b53 | 2027 | int i; |
1ccde1cb FB |
2028 | |
2029 | start &= TARGET_PAGE_MASK; | |
2030 | end = TARGET_PAGE_ALIGN(end); | |
2031 | ||
2032 | length = end - start; | |
2033 | if (length == 0) | |
2034 | return; | |
f7c11b53 | 2035 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
f23db169 | 2036 | |
1ccde1cb FB |
2037 | /* we modify the TLB cache so that the dirty bit will be set again |
2038 | when accessing the range */ | |
5579c7f3 PB |
2039 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
2040 | /* Chek that we don't span multiple blocks - this breaks the | |
2041 | address comparisons below. */ | |
2042 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 | |
2043 | != (end - 1) - start) { | |
2044 | abort(); | |
2045 | } | |
2046 | ||
6a00d601 | 2047 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
2048 | int mmu_idx; |
2049 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2050 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2051 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2052 | start1, length); | |
2053 | } | |
6a00d601 | 2054 | } |
1ccde1cb FB |
2055 | } |
2056 | ||
74576198 AL |
2057 | int cpu_physical_memory_set_dirty_tracking(int enable) |
2058 | { | |
f6f3fbca | 2059 | int ret = 0; |
74576198 | 2060 | in_migration = enable; |
f6f3fbca MT |
2061 | ret = cpu_notify_migration_log(!!enable); |
2062 | return ret; | |
74576198 AL |
2063 | } |
2064 | ||
2065 | int cpu_physical_memory_get_dirty_tracking(void) | |
2066 | { | |
2067 | return in_migration; | |
2068 | } | |
2069 | ||
c227f099 AL |
2070 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
2071 | target_phys_addr_t end_addr) | |
2bec46dc | 2072 | { |
7b8f3b78 | 2073 | int ret; |
151f7749 | 2074 | |
f6f3fbca | 2075 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
151f7749 | 2076 | return ret; |
2bec46dc AL |
2077 | } |
2078 | ||
3a7d929e FB |
2079 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2080 | { | |
c227f099 | 2081 | ram_addr_t ram_addr; |
5579c7f3 | 2082 | void *p; |
3a7d929e | 2083 | |
84b7b8e7 | 2084 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
2085 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2086 | + tlb_entry->addend); | |
2087 | ram_addr = qemu_ram_addr_from_host(p); | |
3a7d929e | 2088 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2089 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2090 | } |
2091 | } | |
2092 | } | |
2093 | ||
2094 | /* update the TLB according to the current state of the dirty bits */ | |
2095 | void cpu_tlb_update_dirty(CPUState *env) | |
2096 | { | |
2097 | int i; | |
cfde4bd9 IY |
2098 | int mmu_idx; |
2099 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2100 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2101 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2102 | } | |
3a7d929e FB |
2103 | } |
2104 | ||
0f459d16 | 2105 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2106 | { |
0f459d16 PB |
2107 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2108 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2109 | } |
2110 | ||
0f459d16 PB |
2111 | /* update the TLB corresponding to virtual page vaddr |
2112 | so that it is no longer dirty */ | |
2113 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2114 | { |
1ccde1cb | 2115 | int i; |
cfde4bd9 | 2116 | int mmu_idx; |
1ccde1cb | 2117 | |
0f459d16 | 2118 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2119 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2120 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2121 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2122 | } |
2123 | ||
d4c430a8 PB |
2124 | /* Our TLB does not support large pages, so remember the area covered by |
2125 | large pages and trigger a full TLB flush if these are invalidated. */ | |
2126 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, | |
2127 | target_ulong size) | |
2128 | { | |
2129 | target_ulong mask = ~(size - 1); | |
2130 | ||
2131 | if (env->tlb_flush_addr == (target_ulong)-1) { | |
2132 | env->tlb_flush_addr = vaddr & mask; | |
2133 | env->tlb_flush_mask = mask; | |
2134 | return; | |
2135 | } | |
2136 | /* Extend the existing region to include the new page. | |
2137 | This is a compromise between unnecessary flushes and the cost | |
2138 | of maintaining a full variable size TLB. */ | |
2139 | mask &= env->tlb_flush_mask; | |
2140 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { | |
2141 | mask <<= 1; | |
2142 | } | |
2143 | env->tlb_flush_addr &= mask; | |
2144 | env->tlb_flush_mask = mask; | |
2145 | } | |
2146 | ||
2147 | /* Add a new TLB entry. At most one entry for a given virtual address | |
2148 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | |
2149 | supplied size is only used by tlb_flush_page. */ | |
2150 | void tlb_set_page(CPUState *env, target_ulong vaddr, | |
2151 | target_phys_addr_t paddr, int prot, | |
2152 | int mmu_idx, target_ulong size) | |
9fa3e853 | 2153 | { |
92e873b9 | 2154 | PhysPageDesc *p; |
4f2ac237 | 2155 | unsigned long pd; |
9fa3e853 | 2156 | unsigned int index; |
4f2ac237 | 2157 | target_ulong address; |
0f459d16 | 2158 | target_ulong code_address; |
355b1943 | 2159 | unsigned long addend; |
84b7b8e7 | 2160 | CPUTLBEntry *te; |
a1d1bb31 | 2161 | CPUWatchpoint *wp; |
c227f099 | 2162 | target_phys_addr_t iotlb; |
9fa3e853 | 2163 | |
d4c430a8 PB |
2164 | assert(size >= TARGET_PAGE_SIZE); |
2165 | if (size != TARGET_PAGE_SIZE) { | |
2166 | tlb_add_large_page(env, vaddr, size); | |
2167 | } | |
92e873b9 | 2168 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2169 | if (!p) { |
2170 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2171 | } else { |
2172 | pd = p->phys_offset; | |
9fa3e853 FB |
2173 | } |
2174 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
2175 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
2176 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
2177 | #endif |
2178 | ||
0f459d16 PB |
2179 | address = vaddr; |
2180 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2181 | /* IO memory case (romd handled later) */ | |
2182 | address |= TLB_MMIO; | |
2183 | } | |
5579c7f3 | 2184 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2185 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2186 | /* Normal RAM. */ | |
2187 | iotlb = pd & TARGET_PAGE_MASK; | |
2188 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2189 | iotlb |= IO_MEM_NOTDIRTY; | |
2190 | else | |
2191 | iotlb |= IO_MEM_ROM; | |
2192 | } else { | |
ccbb4d44 | 2193 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2194 | It would be nice to pass an offset from the base address |
2195 | of that region. This would avoid having to special case RAM, | |
2196 | and avoid full address decoding in every device. | |
2197 | We can't use the high bits of pd for this because | |
2198 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2199 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2200 | if (p) { | |
8da3ff18 PB |
2201 | iotlb += p->region_offset; |
2202 | } else { | |
2203 | iotlb += paddr; | |
2204 | } | |
0f459d16 PB |
2205 | } |
2206 | ||
2207 | code_address = address; | |
2208 | /* Make accesses to pages with watchpoints go via the | |
2209 | watchpoint trap routines. */ | |
72cf2d4f | 2210 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2211 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
bf298f83 JK |
2212 | /* Avoid trapping reads of pages with a write breakpoint. */ |
2213 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
2214 | iotlb = io_mem_watch + paddr; | |
2215 | address |= TLB_MMIO; | |
2216 | break; | |
2217 | } | |
6658ffb8 | 2218 | } |
0f459d16 | 2219 | } |
d79acba4 | 2220 | |
0f459d16 PB |
2221 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2222 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2223 | te = &env->tlb_table[mmu_idx][index]; | |
2224 | te->addend = addend - vaddr; | |
2225 | if (prot & PAGE_READ) { | |
2226 | te->addr_read = address; | |
2227 | } else { | |
2228 | te->addr_read = -1; | |
2229 | } | |
5c751e99 | 2230 | |
0f459d16 PB |
2231 | if (prot & PAGE_EXEC) { |
2232 | te->addr_code = code_address; | |
2233 | } else { | |
2234 | te->addr_code = -1; | |
2235 | } | |
2236 | if (prot & PAGE_WRITE) { | |
2237 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2238 | (pd & IO_MEM_ROMD)) { | |
2239 | /* Write access calls the I/O callback. */ | |
2240 | te->addr_write = address | TLB_MMIO; | |
2241 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2242 | !cpu_physical_memory_is_dirty(pd)) { | |
2243 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2244 | } else { |
0f459d16 | 2245 | te->addr_write = address; |
9fa3e853 | 2246 | } |
0f459d16 PB |
2247 | } else { |
2248 | te->addr_write = -1; | |
9fa3e853 | 2249 | } |
9fa3e853 FB |
2250 | } |
2251 | ||
0124311e FB |
2252 | #else |
2253 | ||
ee8b7021 | 2254 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2255 | { |
2256 | } | |
2257 | ||
2e12669a | 2258 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2259 | { |
2260 | } | |
2261 | ||
edf8e2af MW |
2262 | /* |
2263 | * Walks guest process memory "regions" one by one | |
2264 | * and calls callback function 'fn' for each region. | |
2265 | */ | |
5cd2c5b6 RH |
2266 | |
2267 | struct walk_memory_regions_data | |
2268 | { | |
2269 | walk_memory_regions_fn fn; | |
2270 | void *priv; | |
2271 | unsigned long start; | |
2272 | int prot; | |
2273 | }; | |
2274 | ||
2275 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
b480d9b7 | 2276 | abi_ulong end, int new_prot) |
5cd2c5b6 RH |
2277 | { |
2278 | if (data->start != -1ul) { | |
2279 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2280 | if (rc != 0) { | |
2281 | return rc; | |
2282 | } | |
2283 | } | |
2284 | ||
2285 | data->start = (new_prot ? end : -1ul); | |
2286 | data->prot = new_prot; | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
2291 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
b480d9b7 | 2292 | abi_ulong base, int level, void **lp) |
5cd2c5b6 | 2293 | { |
b480d9b7 | 2294 | abi_ulong pa; |
5cd2c5b6 RH |
2295 | int i, rc; |
2296 | ||
2297 | if (*lp == NULL) { | |
2298 | return walk_memory_regions_end(data, base, 0); | |
2299 | } | |
2300 | ||
2301 | if (level == 0) { | |
2302 | PageDesc *pd = *lp; | |
7296abac | 2303 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
2304 | int prot = pd[i].flags; |
2305 | ||
2306 | pa = base | (i << TARGET_PAGE_BITS); | |
2307 | if (prot != data->prot) { | |
2308 | rc = walk_memory_regions_end(data, pa, prot); | |
2309 | if (rc != 0) { | |
2310 | return rc; | |
9fa3e853 | 2311 | } |
9fa3e853 | 2312 | } |
5cd2c5b6 RH |
2313 | } |
2314 | } else { | |
2315 | void **pp = *lp; | |
7296abac | 2316 | for (i = 0; i < L2_SIZE; ++i) { |
b480d9b7 PB |
2317 | pa = base | ((abi_ulong)i << |
2318 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
5cd2c5b6 RH |
2319 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
2320 | if (rc != 0) { | |
2321 | return rc; | |
2322 | } | |
2323 | } | |
2324 | } | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
2329 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2330 | { | |
2331 | struct walk_memory_regions_data data; | |
2332 | unsigned long i; | |
2333 | ||
2334 | data.fn = fn; | |
2335 | data.priv = priv; | |
2336 | data.start = -1ul; | |
2337 | data.prot = 0; | |
2338 | ||
2339 | for (i = 0; i < V_L1_SIZE; i++) { | |
b480d9b7 | 2340 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
5cd2c5b6 RH |
2341 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
2342 | if (rc != 0) { | |
2343 | return rc; | |
9fa3e853 | 2344 | } |
33417e70 | 2345 | } |
5cd2c5b6 RH |
2346 | |
2347 | return walk_memory_regions_end(&data, 0, 0); | |
edf8e2af MW |
2348 | } |
2349 | ||
b480d9b7 PB |
2350 | static int dump_region(void *priv, abi_ulong start, |
2351 | abi_ulong end, unsigned long prot) | |
edf8e2af MW |
2352 | { |
2353 | FILE *f = (FILE *)priv; | |
2354 | ||
b480d9b7 PB |
2355 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
2356 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
edf8e2af MW |
2357 | start, end, end - start, |
2358 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2359 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2360 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2361 | ||
2362 | return (0); | |
2363 | } | |
2364 | ||
2365 | /* dump memory mappings */ | |
2366 | void page_dump(FILE *f) | |
2367 | { | |
2368 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2369 | "start", "end", "size", "prot"); | |
2370 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2371 | } |
2372 | ||
53a5960a | 2373 | int page_get_flags(target_ulong address) |
33417e70 | 2374 | { |
9fa3e853 FB |
2375 | PageDesc *p; |
2376 | ||
2377 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2378 | if (!p) |
9fa3e853 FB |
2379 | return 0; |
2380 | return p->flags; | |
2381 | } | |
2382 | ||
376a7909 RH |
2383 | /* Modify the flags of a page and invalidate the code if necessary. |
2384 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2385 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
53a5960a | 2386 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 | 2387 | { |
376a7909 RH |
2388 | target_ulong addr, len; |
2389 | ||
2390 | /* This function should never be called with addresses outside the | |
2391 | guest address space. If this assert fires, it probably indicates | |
2392 | a missing call to h2g_valid. */ | |
b480d9b7 PB |
2393 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2394 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2395 | #endif |
2396 | assert(start < end); | |
9fa3e853 FB |
2397 | |
2398 | start = start & TARGET_PAGE_MASK; | |
2399 | end = TARGET_PAGE_ALIGN(end); | |
376a7909 RH |
2400 | |
2401 | if (flags & PAGE_WRITE) { | |
9fa3e853 | 2402 | flags |= PAGE_WRITE_ORG; |
376a7909 RH |
2403 | } |
2404 | ||
2405 | for (addr = start, len = end - start; | |
2406 | len != 0; | |
2407 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2408 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2409 | ||
2410 | /* If the write protection bit is set, then we invalidate | |
2411 | the code inside. */ | |
5fafdf24 | 2412 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2413 | (flags & PAGE_WRITE) && |
2414 | p->first_tb) { | |
d720b93d | 2415 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2416 | } |
2417 | p->flags = flags; | |
2418 | } | |
33417e70 FB |
2419 | } |
2420 | ||
3d97b40b TS |
2421 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2422 | { | |
2423 | PageDesc *p; | |
2424 | target_ulong end; | |
2425 | target_ulong addr; | |
2426 | ||
376a7909 RH |
2427 | /* This function should never be called with addresses outside the |
2428 | guest address space. If this assert fires, it probably indicates | |
2429 | a missing call to h2g_valid. */ | |
338e9e6c BS |
2430 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2431 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2432 | #endif |
2433 | ||
3e0650a9 RH |
2434 | if (len == 0) { |
2435 | return 0; | |
2436 | } | |
376a7909 RH |
2437 | if (start + len - 1 < start) { |
2438 | /* We've wrapped around. */ | |
55f280c9 | 2439 | return -1; |
376a7909 | 2440 | } |
55f280c9 | 2441 | |
3d97b40b TS |
2442 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2443 | start = start & TARGET_PAGE_MASK; | |
2444 | ||
376a7909 RH |
2445 | for (addr = start, len = end - start; |
2446 | len != 0; | |
2447 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
3d97b40b TS |
2448 | p = page_find(addr >> TARGET_PAGE_BITS); |
2449 | if( !p ) | |
2450 | return -1; | |
2451 | if( !(p->flags & PAGE_VALID) ) | |
2452 | return -1; | |
2453 | ||
dae3270c | 2454 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2455 | return -1; |
dae3270c FB |
2456 | if (flags & PAGE_WRITE) { |
2457 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2458 | return -1; | |
2459 | /* unprotect the page if it was put read-only because it | |
2460 | contains translated code */ | |
2461 | if (!(p->flags & PAGE_WRITE)) { | |
2462 | if (!page_unprotect(addr, 0, NULL)) | |
2463 | return -1; | |
2464 | } | |
2465 | return 0; | |
2466 | } | |
3d97b40b TS |
2467 | } |
2468 | return 0; | |
2469 | } | |
2470 | ||
9fa3e853 | 2471 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2472 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2473 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 | 2474 | { |
45d679d6 AJ |
2475 | unsigned int prot; |
2476 | PageDesc *p; | |
53a5960a | 2477 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2478 | |
c8a706fe PB |
2479 | /* Technically this isn't safe inside a signal handler. However we |
2480 | know this only ever happens in a synchronous SEGV handler, so in | |
2481 | practice it seems to be ok. */ | |
2482 | mmap_lock(); | |
2483 | ||
45d679d6 AJ |
2484 | p = page_find(address >> TARGET_PAGE_BITS); |
2485 | if (!p) { | |
c8a706fe | 2486 | mmap_unlock(); |
9fa3e853 | 2487 | return 0; |
c8a706fe | 2488 | } |
45d679d6 | 2489 | |
9fa3e853 FB |
2490 | /* if the page was really writable, then we change its |
2491 | protection back to writable */ | |
45d679d6 AJ |
2492 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
2493 | host_start = address & qemu_host_page_mask; | |
2494 | host_end = host_start + qemu_host_page_size; | |
2495 | ||
2496 | prot = 0; | |
2497 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
2498 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2499 | p->flags |= PAGE_WRITE; | |
2500 | prot |= p->flags; | |
2501 | ||
9fa3e853 FB |
2502 | /* and since the content will be modified, we must invalidate |
2503 | the corresponding translated code. */ | |
45d679d6 | 2504 | tb_invalidate_phys_page(addr, pc, puc); |
9fa3e853 | 2505 | #ifdef DEBUG_TB_CHECK |
45d679d6 | 2506 | tb_invalidate_check(addr); |
9fa3e853 | 2507 | #endif |
9fa3e853 | 2508 | } |
45d679d6 AJ |
2509 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
2510 | prot & PAGE_BITS); | |
2511 | ||
2512 | mmap_unlock(); | |
2513 | return 1; | |
9fa3e853 | 2514 | } |
c8a706fe | 2515 | mmap_unlock(); |
9fa3e853 FB |
2516 | return 0; |
2517 | } | |
2518 | ||
6a00d601 FB |
2519 | static inline void tlb_set_dirty(CPUState *env, |
2520 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2521 | { |
2522 | } | |
9fa3e853 FB |
2523 | #endif /* defined(CONFIG_USER_ONLY) */ |
2524 | ||
e2eef170 | 2525 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2526 | |
c04b2b78 PB |
2527 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2528 | typedef struct subpage_t { | |
2529 | target_phys_addr_t base; | |
f6405247 RH |
2530 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
2531 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; | |
c04b2b78 PB |
2532 | } subpage_t; |
2533 | ||
c227f099 AL |
2534 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2535 | ram_addr_t memory, ram_addr_t region_offset); | |
f6405247 RH |
2536 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2537 | ram_addr_t orig_memory, | |
2538 | ram_addr_t region_offset); | |
db7b5426 BS |
2539 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2540 | need_subpage) \ | |
2541 | do { \ | |
2542 | if (addr > start_addr) \ | |
2543 | start_addr2 = 0; \ | |
2544 | else { \ | |
2545 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2546 | if (start_addr2 > 0) \ | |
2547 | need_subpage = 1; \ | |
2548 | } \ | |
2549 | \ | |
49e9fba2 | 2550 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2551 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2552 | else { \ | |
2553 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2554 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2555 | need_subpage = 1; \ | |
2556 | } \ | |
2557 | } while (0) | |
2558 | ||
8f2498f9 MT |
2559 | /* register physical memory. |
2560 | For RAM, 'size' must be a multiple of the target page size. | |
2561 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2562 | io memory page. The address used when calling the IO function is |
2563 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2564 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2565 | before calculating this offset. This should not be a problem unless |
2566 | the low bits of start_addr and region_offset differ. */ | |
c227f099 AL |
2567 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
2568 | ram_addr_t size, | |
2569 | ram_addr_t phys_offset, | |
2570 | ram_addr_t region_offset) | |
33417e70 | 2571 | { |
c227f099 | 2572 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2573 | PhysPageDesc *p; |
9d42037b | 2574 | CPUState *env; |
c227f099 | 2575 | ram_addr_t orig_size = size; |
f6405247 | 2576 | subpage_t *subpage; |
33417e70 | 2577 | |
f6f3fbca MT |
2578 | cpu_notify_set_memory(start_addr, size, phys_offset); |
2579 | ||
67c4d23c PB |
2580 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2581 | region_offset = start_addr; | |
2582 | } | |
8da3ff18 | 2583 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2584 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2585 | end_addr = start_addr + (target_phys_addr_t)size; |
49e9fba2 | 2586 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
db7b5426 BS |
2587 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2588 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2589 | ram_addr_t orig_memory = p->phys_offset; |
2590 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2591 | int need_subpage = 0; |
2592 | ||
2593 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2594 | need_subpage); | |
f6405247 | 2595 | if (need_subpage) { |
db7b5426 BS |
2596 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2597 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2598 | &p->phys_offset, orig_memory, |
2599 | p->region_offset); | |
db7b5426 BS |
2600 | } else { |
2601 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2602 | >> IO_MEM_SHIFT]; | |
2603 | } | |
8da3ff18 PB |
2604 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2605 | region_offset); | |
2606 | p->region_offset = 0; | |
db7b5426 BS |
2607 | } else { |
2608 | p->phys_offset = phys_offset; | |
2609 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2610 | (phys_offset & IO_MEM_ROMD)) | |
2611 | phys_offset += TARGET_PAGE_SIZE; | |
2612 | } | |
2613 | } else { | |
2614 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2615 | p->phys_offset = phys_offset; | |
8da3ff18 | 2616 | p->region_offset = region_offset; |
db7b5426 | 2617 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2618 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2619 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2620 | } else { |
c227f099 | 2621 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2622 | int need_subpage = 0; |
2623 | ||
2624 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2625 | end_addr2, need_subpage); | |
2626 | ||
f6405247 | 2627 | if (need_subpage) { |
db7b5426 | 2628 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2629 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2630 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2631 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2632 | phys_offset, region_offset); |
2633 | p->region_offset = 0; | |
db7b5426 BS |
2634 | } |
2635 | } | |
2636 | } | |
8da3ff18 | 2637 | region_offset += TARGET_PAGE_SIZE; |
33417e70 | 2638 | } |
3b46e624 | 2639 | |
9d42037b FB |
2640 | /* since each CPU stores ram addresses in its TLB cache, we must |
2641 | reset the modified entries */ | |
2642 | /* XXX: slow ! */ | |
2643 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2644 | tlb_flush(env, 1); | |
2645 | } | |
33417e70 FB |
2646 | } |
2647 | ||
ba863458 | 2648 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2649 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2650 | { |
2651 | PhysPageDesc *p; | |
2652 | ||
2653 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2654 | if (!p) | |
2655 | return IO_MEM_UNASSIGNED; | |
2656 | return p->phys_offset; | |
2657 | } | |
2658 | ||
c227f099 | 2659 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2660 | { |
2661 | if (kvm_enabled()) | |
2662 | kvm_coalesce_mmio_region(addr, size); | |
2663 | } | |
2664 | ||
c227f099 | 2665 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2666 | { |
2667 | if (kvm_enabled()) | |
2668 | kvm_uncoalesce_mmio_region(addr, size); | |
2669 | } | |
2670 | ||
62a2744c SY |
2671 | void qemu_flush_coalesced_mmio_buffer(void) |
2672 | { | |
2673 | if (kvm_enabled()) | |
2674 | kvm_flush_coalesced_mmio_buffer(); | |
2675 | } | |
2676 | ||
c902760f MT |
2677 | #if defined(__linux__) && !defined(TARGET_S390X) |
2678 | ||
2679 | #include <sys/vfs.h> | |
2680 | ||
2681 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2682 | ||
2683 | static long gethugepagesize(const char *path) | |
2684 | { | |
2685 | struct statfs fs; | |
2686 | int ret; | |
2687 | ||
2688 | do { | |
2689 | ret = statfs(path, &fs); | |
2690 | } while (ret != 0 && errno == EINTR); | |
2691 | ||
2692 | if (ret != 0) { | |
6adc0549 | 2693 | perror(path); |
c902760f MT |
2694 | return 0; |
2695 | } | |
2696 | ||
2697 | if (fs.f_type != HUGETLBFS_MAGIC) | |
2698 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); | |
2699 | ||
2700 | return fs.f_bsize; | |
2701 | } | |
2702 | ||
2703 | static void *file_ram_alloc(ram_addr_t memory, const char *path) | |
2704 | { | |
2705 | char *filename; | |
2706 | void *area; | |
2707 | int fd; | |
2708 | #ifdef MAP_POPULATE | |
2709 | int flags; | |
2710 | #endif | |
2711 | unsigned long hpagesize; | |
2712 | ||
2713 | hpagesize = gethugepagesize(path); | |
2714 | if (!hpagesize) { | |
2715 | return NULL; | |
2716 | } | |
2717 | ||
2718 | if (memory < hpagesize) { | |
2719 | return NULL; | |
2720 | } | |
2721 | ||
2722 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2723 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2724 | return NULL; | |
2725 | } | |
2726 | ||
2727 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
2728 | return NULL; | |
2729 | } | |
2730 | ||
2731 | fd = mkstemp(filename); | |
2732 | if (fd < 0) { | |
6adc0549 | 2733 | perror("unable to create backing store for hugepages"); |
c902760f MT |
2734 | free(filename); |
2735 | return NULL; | |
2736 | } | |
2737 | unlink(filename); | |
2738 | free(filename); | |
2739 | ||
2740 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2741 | ||
2742 | /* | |
2743 | * ftruncate is not supported by hugetlbfs in older | |
2744 | * hosts, so don't bother bailing out on errors. | |
2745 | * If anything goes wrong with it under other filesystems, | |
2746 | * mmap will fail. | |
2747 | */ | |
2748 | if (ftruncate(fd, memory)) | |
2749 | perror("ftruncate"); | |
2750 | ||
2751 | #ifdef MAP_POPULATE | |
2752 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2753 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2754 | * to sidestep this quirk. | |
2755 | */ | |
2756 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2757 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2758 | #else | |
2759 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2760 | #endif | |
2761 | if (area == MAP_FAILED) { | |
2762 | perror("file_ram_alloc: can't mmap RAM pages"); | |
2763 | close(fd); | |
2764 | return (NULL); | |
2765 | } | |
2766 | return area; | |
2767 | } | |
2768 | #endif | |
2769 | ||
d17b5288 AW |
2770 | static ram_addr_t find_ram_offset(ram_addr_t size) |
2771 | { | |
2772 | RAMBlock *block; | |
2773 | ram_addr_t last = 0; | |
2774 | ||
2775 | QLIST_FOREACH(block, &ram_list.blocks, next) | |
2776 | last = MAX(last, block->offset + block->length); | |
2777 | ||
2778 | return last; | |
2779 | } | |
2780 | ||
c227f099 | 2781 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
94a6b54f PB |
2782 | { |
2783 | RAMBlock *new_block; | |
2784 | ||
94a6b54f PB |
2785 | size = TARGET_PAGE_ALIGN(size); |
2786 | new_block = qemu_malloc(sizeof(*new_block)); | |
2787 | ||
c902760f MT |
2788 | if (mem_path) { |
2789 | #if defined (__linux__) && !defined(TARGET_S390X) | |
2790 | new_block->host = file_ram_alloc(size, mem_path); | |
618a568d MT |
2791 | if (!new_block->host) { |
2792 | new_block->host = qemu_vmalloc(size); | |
2793 | #ifdef MADV_MERGEABLE | |
2794 | madvise(new_block->host, size, MADV_MERGEABLE); | |
2795 | #endif | |
2796 | } | |
c902760f MT |
2797 | #else |
2798 | fprintf(stderr, "-mem-path option unsupported\n"); | |
2799 | exit(1); | |
2800 | #endif | |
2801 | } else { | |
6b02494d | 2802 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
c902760f MT |
2803 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ |
2804 | new_block->host = mmap((void*)0x1000000, size, | |
2805 | PROT_EXEC|PROT_READ|PROT_WRITE, | |
2806 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
6b02494d | 2807 | #else |
c902760f | 2808 | new_block->host = qemu_vmalloc(size); |
6b02494d | 2809 | #endif |
ccb167e9 | 2810 | #ifdef MADV_MERGEABLE |
c902760f | 2811 | madvise(new_block->host, size, MADV_MERGEABLE); |
ccb167e9 | 2812 | #endif |
c902760f | 2813 | } |
d17b5288 | 2814 | new_block->offset = find_ram_offset(size); |
94a6b54f PB |
2815 | new_block->length = size; |
2816 | ||
f471a17e | 2817 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
94a6b54f | 2818 | |
f471a17e | 2819 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, |
d17b5288 AW |
2820 | (new_block->offset + size) >> TARGET_PAGE_BITS); |
2821 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), | |
94a6b54f PB |
2822 | 0xff, size >> TARGET_PAGE_BITS); |
2823 | ||
6f0437e8 JK |
2824 | if (kvm_enabled()) |
2825 | kvm_setup_guest_memory(new_block->host, size); | |
2826 | ||
94a6b54f PB |
2827 | return new_block->offset; |
2828 | } | |
e9a1ab19 | 2829 | |
c227f099 | 2830 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2831 | { |
94a6b54f | 2832 | /* TODO: implement this. */ |
e9a1ab19 FB |
2833 | } |
2834 | ||
dc828ca1 | 2835 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
2836 | With the exception of the softmmu code in this file, this should |
2837 | only be used for local memory (e.g. video ram) that the device owns, | |
2838 | and knows it isn't going to access beyond the end of the block. | |
2839 | ||
2840 | It should not be used for general purpose DMA. | |
2841 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
2842 | */ | |
c227f099 | 2843 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 2844 | { |
94a6b54f PB |
2845 | RAMBlock *block; |
2846 | ||
f471a17e AW |
2847 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
2848 | if (addr - block->offset < block->length) { | |
2849 | QLIST_REMOVE(block, next); | |
2850 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); | |
2851 | return block->host + (addr - block->offset); | |
2852 | } | |
94a6b54f | 2853 | } |
f471a17e AW |
2854 | |
2855 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
2856 | abort(); | |
2857 | ||
2858 | return NULL; | |
dc828ca1 PB |
2859 | } |
2860 | ||
5579c7f3 PB |
2861 | /* Some of the softmmu routines need to translate from a host pointer |
2862 | (typically a TLB entry) back to a ram offset. */ | |
c227f099 | 2863 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
5579c7f3 | 2864 | { |
94a6b54f PB |
2865 | RAMBlock *block; |
2866 | uint8_t *host = ptr; | |
2867 | ||
f471a17e AW |
2868 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
2869 | if (host - block->host < block->length) { | |
2870 | return block->offset + (host - block->host); | |
2871 | } | |
94a6b54f | 2872 | } |
f471a17e AW |
2873 | |
2874 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
2875 | abort(); | |
2876 | ||
2877 | return 0; | |
5579c7f3 PB |
2878 | } |
2879 | ||
c227f099 | 2880 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2881 | { |
67d3b957 | 2882 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2883 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2884 | #endif |
faed1c2a | 2885 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2886 | do_unassigned_access(addr, 0, 0, 0, 1); |
2887 | #endif | |
2888 | return 0; | |
2889 | } | |
2890 | ||
c227f099 | 2891 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2892 | { |
2893 | #ifdef DEBUG_UNASSIGNED | |
2894 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2895 | #endif | |
faed1c2a | 2896 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2897 | do_unassigned_access(addr, 0, 0, 0, 2); |
2898 | #endif | |
2899 | return 0; | |
2900 | } | |
2901 | ||
c227f099 | 2902 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2903 | { |
2904 | #ifdef DEBUG_UNASSIGNED | |
2905 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2906 | #endif | |
faed1c2a | 2907 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2908 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 2909 | #endif |
33417e70 FB |
2910 | return 0; |
2911 | } | |
2912 | ||
c227f099 | 2913 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2914 | { |
67d3b957 | 2915 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2916 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2917 | #endif |
faed1c2a | 2918 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2919 | do_unassigned_access(addr, 1, 0, 0, 1); |
2920 | #endif | |
2921 | } | |
2922 | ||
c227f099 | 2923 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2924 | { |
2925 | #ifdef DEBUG_UNASSIGNED | |
2926 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2927 | #endif | |
faed1c2a | 2928 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2929 | do_unassigned_access(addr, 1, 0, 0, 2); |
2930 | #endif | |
2931 | } | |
2932 | ||
c227f099 | 2933 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2934 | { |
2935 | #ifdef DEBUG_UNASSIGNED | |
2936 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2937 | #endif | |
faed1c2a | 2938 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2939 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 2940 | #endif |
33417e70 FB |
2941 | } |
2942 | ||
d60efc6b | 2943 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 2944 | unassigned_mem_readb, |
e18231a3 BS |
2945 | unassigned_mem_readw, |
2946 | unassigned_mem_readl, | |
33417e70 FB |
2947 | }; |
2948 | ||
d60efc6b | 2949 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 2950 | unassigned_mem_writeb, |
e18231a3 BS |
2951 | unassigned_mem_writew, |
2952 | unassigned_mem_writel, | |
33417e70 FB |
2953 | }; |
2954 | ||
c227f099 | 2955 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2956 | uint32_t val) |
9fa3e853 | 2957 | { |
3a7d929e | 2958 | int dirty_flags; |
f7c11b53 | 2959 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 2960 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 2961 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 2962 | tb_invalidate_phys_page_fast(ram_addr, 1); |
f7c11b53 | 2963 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 2964 | #endif |
3a7d929e | 2965 | } |
5579c7f3 | 2966 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 2967 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 2968 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
2969 | /* we remove the notdirty callback only if the code has been |
2970 | flushed */ | |
2971 | if (dirty_flags == 0xff) | |
2e70f6ef | 2972 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2973 | } |
2974 | ||
c227f099 | 2975 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2976 | uint32_t val) |
9fa3e853 | 2977 | { |
3a7d929e | 2978 | int dirty_flags; |
f7c11b53 | 2979 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 2980 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 2981 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 2982 | tb_invalidate_phys_page_fast(ram_addr, 2); |
f7c11b53 | 2983 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 2984 | #endif |
3a7d929e | 2985 | } |
5579c7f3 | 2986 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 2987 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 2988 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
2989 | /* we remove the notdirty callback only if the code has been |
2990 | flushed */ | |
2991 | if (dirty_flags == 0xff) | |
2e70f6ef | 2992 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2993 | } |
2994 | ||
c227f099 | 2995 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2996 | uint32_t val) |
9fa3e853 | 2997 | { |
3a7d929e | 2998 | int dirty_flags; |
f7c11b53 | 2999 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3000 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3001 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3002 | tb_invalidate_phys_page_fast(ram_addr, 4); |
f7c11b53 | 3003 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3004 | #endif |
3a7d929e | 3005 | } |
5579c7f3 | 3006 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3007 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3008 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3009 | /* we remove the notdirty callback only if the code has been |
3010 | flushed */ | |
3011 | if (dirty_flags == 0xff) | |
2e70f6ef | 3012 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3013 | } |
3014 | ||
d60efc6b | 3015 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
3016 | NULL, /* never used */ |
3017 | NULL, /* never used */ | |
3018 | NULL, /* never used */ | |
3019 | }; | |
3020 | ||
d60efc6b | 3021 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
3022 | notdirty_mem_writeb, |
3023 | notdirty_mem_writew, | |
3024 | notdirty_mem_writel, | |
3025 | }; | |
3026 | ||
0f459d16 | 3027 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 3028 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
3029 | { |
3030 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
3031 | target_ulong pc, cs_base; |
3032 | TranslationBlock *tb; | |
0f459d16 | 3033 | target_ulong vaddr; |
a1d1bb31 | 3034 | CPUWatchpoint *wp; |
06d55cc1 | 3035 | int cpu_flags; |
0f459d16 | 3036 | |
06d55cc1 AL |
3037 | if (env->watchpoint_hit) { |
3038 | /* We re-entered the check after replacing the TB. Now raise | |
3039 | * the debug interrupt so that is will trigger after the | |
3040 | * current instruction. */ | |
3041 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
3042 | return; | |
3043 | } | |
2e70f6ef | 3044 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 3045 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
3046 | if ((vaddr == (wp->vaddr & len_mask) || |
3047 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
3048 | wp->flags |= BP_WATCHPOINT_HIT; |
3049 | if (!env->watchpoint_hit) { | |
3050 | env->watchpoint_hit = wp; | |
3051 | tb = tb_find_pc(env->mem_io_pc); | |
3052 | if (!tb) { | |
3053 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
3054 | "pc=%p", (void *)env->mem_io_pc); | |
3055 | } | |
3056 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); | |
3057 | tb_phys_invalidate(tb, -1); | |
3058 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
3059 | env->exception_index = EXCP_DEBUG; | |
3060 | } else { | |
3061 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
3062 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
3063 | } | |
3064 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 3065 | } |
6e140f28 AL |
3066 | } else { |
3067 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
3068 | } |
3069 | } | |
3070 | } | |
3071 | ||
6658ffb8 PB |
3072 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
3073 | so these check for a hit then pass through to the normal out-of-line | |
3074 | phys routines. */ | |
c227f099 | 3075 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3076 | { |
b4051334 | 3077 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
3078 | return ldub_phys(addr); |
3079 | } | |
3080 | ||
c227f099 | 3081 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3082 | { |
b4051334 | 3083 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
3084 | return lduw_phys(addr); |
3085 | } | |
3086 | ||
c227f099 | 3087 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3088 | { |
b4051334 | 3089 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
3090 | return ldl_phys(addr); |
3091 | } | |
3092 | ||
c227f099 | 3093 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3094 | uint32_t val) |
3095 | { | |
b4051334 | 3096 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
3097 | stb_phys(addr, val); |
3098 | } | |
3099 | ||
c227f099 | 3100 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3101 | uint32_t val) |
3102 | { | |
b4051334 | 3103 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
3104 | stw_phys(addr, val); |
3105 | } | |
3106 | ||
c227f099 | 3107 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3108 | uint32_t val) |
3109 | { | |
b4051334 | 3110 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
3111 | stl_phys(addr, val); |
3112 | } | |
3113 | ||
d60efc6b | 3114 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
3115 | watch_mem_readb, |
3116 | watch_mem_readw, | |
3117 | watch_mem_readl, | |
3118 | }; | |
3119 | ||
d60efc6b | 3120 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
3121 | watch_mem_writeb, |
3122 | watch_mem_writew, | |
3123 | watch_mem_writel, | |
3124 | }; | |
6658ffb8 | 3125 | |
f6405247 RH |
3126 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
3127 | target_phys_addr_t addr, | |
3128 | unsigned int len) | |
db7b5426 | 3129 | { |
f6405247 | 3130 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
3131 | #if defined(DEBUG_SUBPAGE) |
3132 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3133 | mmio, len, addr, idx); | |
3134 | #endif | |
db7b5426 | 3135 | |
f6405247 RH |
3136 | addr += mmio->region_offset[idx]; |
3137 | idx = mmio->sub_io_index[idx]; | |
3138 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); | |
db7b5426 BS |
3139 | } |
3140 | ||
c227f099 | 3141 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
f6405247 | 3142 | uint32_t value, unsigned int len) |
db7b5426 | 3143 | { |
f6405247 | 3144 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 | 3145 | #if defined(DEBUG_SUBPAGE) |
f6405247 RH |
3146 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
3147 | __func__, mmio, len, addr, idx, value); | |
db7b5426 | 3148 | #endif |
f6405247 RH |
3149 | |
3150 | addr += mmio->region_offset[idx]; | |
3151 | idx = mmio->sub_io_index[idx]; | |
3152 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); | |
db7b5426 BS |
3153 | } |
3154 | ||
c227f099 | 3155 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3156 | { |
db7b5426 BS |
3157 | return subpage_readlen(opaque, addr, 0); |
3158 | } | |
3159 | ||
c227f099 | 3160 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3161 | uint32_t value) |
3162 | { | |
db7b5426 BS |
3163 | subpage_writelen(opaque, addr, value, 0); |
3164 | } | |
3165 | ||
c227f099 | 3166 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3167 | { |
db7b5426 BS |
3168 | return subpage_readlen(opaque, addr, 1); |
3169 | } | |
3170 | ||
c227f099 | 3171 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3172 | uint32_t value) |
3173 | { | |
db7b5426 BS |
3174 | subpage_writelen(opaque, addr, value, 1); |
3175 | } | |
3176 | ||
c227f099 | 3177 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3178 | { |
db7b5426 BS |
3179 | return subpage_readlen(opaque, addr, 2); |
3180 | } | |
3181 | ||
f6405247 RH |
3182 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
3183 | uint32_t value) | |
db7b5426 | 3184 | { |
db7b5426 BS |
3185 | subpage_writelen(opaque, addr, value, 2); |
3186 | } | |
3187 | ||
d60efc6b | 3188 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
3189 | &subpage_readb, |
3190 | &subpage_readw, | |
3191 | &subpage_readl, | |
3192 | }; | |
3193 | ||
d60efc6b | 3194 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
3195 | &subpage_writeb, |
3196 | &subpage_writew, | |
3197 | &subpage_writel, | |
3198 | }; | |
3199 | ||
c227f099 AL |
3200 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
3201 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
3202 | { |
3203 | int idx, eidx; | |
3204 | ||
3205 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3206 | return -1; | |
3207 | idx = SUBPAGE_IDX(start); | |
3208 | eidx = SUBPAGE_IDX(end); | |
3209 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 3210 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
3211 | mmio, start, end, idx, eidx, memory); |
3212 | #endif | |
f6405247 | 3213 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
db7b5426 | 3214 | for (; idx <= eidx; idx++) { |
f6405247 RH |
3215 | mmio->sub_io_index[idx] = memory; |
3216 | mmio->region_offset[idx] = region_offset; | |
db7b5426 BS |
3217 | } |
3218 | ||
3219 | return 0; | |
3220 | } | |
3221 | ||
f6405247 RH |
3222 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
3223 | ram_addr_t orig_memory, | |
3224 | ram_addr_t region_offset) | |
db7b5426 | 3225 | { |
c227f099 | 3226 | subpage_t *mmio; |
db7b5426 BS |
3227 | int subpage_memory; |
3228 | ||
c227f099 | 3229 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
3230 | |
3231 | mmio->base = base; | |
1eed09cb | 3232 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
db7b5426 | 3233 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3234 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3235 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3236 | #endif |
1eec614b | 3237 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
f6405247 | 3238 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
db7b5426 BS |
3239 | |
3240 | return mmio; | |
3241 | } | |
3242 | ||
88715657 AL |
3243 | static int get_free_io_mem_idx(void) |
3244 | { | |
3245 | int i; | |
3246 | ||
3247 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3248 | if (!io_mem_used[i]) { | |
3249 | io_mem_used[i] = 1; | |
3250 | return i; | |
3251 | } | |
c6703b47 | 3252 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3253 | return -1; |
3254 | } | |
3255 | ||
33417e70 FB |
3256 | /* mem_read and mem_write are arrays of functions containing the |
3257 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3258 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3259 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3260 | modified. If it is zero, a new io zone is allocated. The return |
3261 | value can be used with cpu_register_physical_memory(). (-1) is | |
3262 | returned if error. */ | |
1eed09cb | 3263 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
3264 | CPUReadMemoryFunc * const *mem_read, |
3265 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb | 3266 | void *opaque) |
33417e70 | 3267 | { |
3cab721d RH |
3268 | int i; |
3269 | ||
33417e70 | 3270 | if (io_index <= 0) { |
88715657 AL |
3271 | io_index = get_free_io_mem_idx(); |
3272 | if (io_index == -1) | |
3273 | return io_index; | |
33417e70 | 3274 | } else { |
1eed09cb | 3275 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3276 | if (io_index >= IO_MEM_NB_ENTRIES) |
3277 | return -1; | |
3278 | } | |
b5ff1b31 | 3279 | |
3cab721d RH |
3280 | for (i = 0; i < 3; ++i) { |
3281 | io_mem_read[io_index][i] | |
3282 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); | |
3283 | } | |
3284 | for (i = 0; i < 3; ++i) { | |
3285 | io_mem_write[io_index][i] | |
3286 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); | |
3287 | } | |
a4193c8a | 3288 | io_mem_opaque[io_index] = opaque; |
f6405247 RH |
3289 | |
3290 | return (io_index << IO_MEM_SHIFT); | |
33417e70 | 3291 | } |
61382a50 | 3292 | |
d60efc6b BS |
3293 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
3294 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb AK |
3295 | void *opaque) |
3296 | { | |
3297 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); | |
3298 | } | |
3299 | ||
88715657 AL |
3300 | void cpu_unregister_io_memory(int io_table_address) |
3301 | { | |
3302 | int i; | |
3303 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3304 | ||
3305 | for (i=0;i < 3; i++) { | |
3306 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3307 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3308 | } | |
3309 | io_mem_opaque[io_index] = NULL; | |
3310 | io_mem_used[io_index] = 0; | |
3311 | } | |
3312 | ||
e9179ce1 AK |
3313 | static void io_mem_init(void) |
3314 | { | |
3315 | int i; | |
3316 | ||
3317 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); | |
3318 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); | |
3319 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); | |
3320 | for (i=0; i<5; i++) | |
3321 | io_mem_used[i] = 1; | |
3322 | ||
3323 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
3324 | watch_mem_write, NULL); | |
e9179ce1 AK |
3325 | } |
3326 | ||
e2eef170 PB |
3327 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3328 | ||
13eb76e0 FB |
3329 | /* physical memory access (slow version, mainly for debug) */ |
3330 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3331 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3332 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3333 | { |
3334 | int l, flags; | |
3335 | target_ulong page; | |
53a5960a | 3336 | void * p; |
13eb76e0 FB |
3337 | |
3338 | while (len > 0) { | |
3339 | page = addr & TARGET_PAGE_MASK; | |
3340 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3341 | if (l > len) | |
3342 | l = len; | |
3343 | flags = page_get_flags(page); | |
3344 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3345 | return -1; |
13eb76e0 FB |
3346 | if (is_write) { |
3347 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3348 | return -1; |
579a97f7 | 3349 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3350 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3351 | return -1; |
72fb7daa AJ |
3352 | memcpy(p, buf, l); |
3353 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3354 | } else { |
3355 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3356 | return -1; |
579a97f7 | 3357 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3358 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3359 | return -1; |
72fb7daa | 3360 | memcpy(buf, p, l); |
5b257578 | 3361 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3362 | } |
3363 | len -= l; | |
3364 | buf += l; | |
3365 | addr += l; | |
3366 | } | |
a68fe89c | 3367 | return 0; |
13eb76e0 | 3368 | } |
8df1cd07 | 3369 | |
13eb76e0 | 3370 | #else |
c227f099 | 3371 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3372 | int len, int is_write) |
3373 | { | |
3374 | int l, io_index; | |
3375 | uint8_t *ptr; | |
3376 | uint32_t val; | |
c227f099 | 3377 | target_phys_addr_t page; |
2e12669a | 3378 | unsigned long pd; |
92e873b9 | 3379 | PhysPageDesc *p; |
3b46e624 | 3380 | |
13eb76e0 FB |
3381 | while (len > 0) { |
3382 | page = addr & TARGET_PAGE_MASK; | |
3383 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3384 | if (l > len) | |
3385 | l = len; | |
92e873b9 | 3386 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3387 | if (!p) { |
3388 | pd = IO_MEM_UNASSIGNED; | |
3389 | } else { | |
3390 | pd = p->phys_offset; | |
3391 | } | |
3b46e624 | 3392 | |
13eb76e0 | 3393 | if (is_write) { |
3a7d929e | 3394 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3395 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3396 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3397 | if (p) |
6c2934db | 3398 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3399 | /* XXX: could force cpu_single_env to NULL to avoid |
3400 | potential bugs */ | |
6c2934db | 3401 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3402 | /* 32 bit write access */ |
c27004ec | 3403 | val = ldl_p(buf); |
6c2934db | 3404 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3405 | l = 4; |
6c2934db | 3406 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3407 | /* 16 bit write access */ |
c27004ec | 3408 | val = lduw_p(buf); |
6c2934db | 3409 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3410 | l = 2; |
3411 | } else { | |
1c213d19 | 3412 | /* 8 bit write access */ |
c27004ec | 3413 | val = ldub_p(buf); |
6c2934db | 3414 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3415 | l = 1; |
3416 | } | |
3417 | } else { | |
b448f2f3 FB |
3418 | unsigned long addr1; |
3419 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3420 | /* RAM case */ |
5579c7f3 | 3421 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3422 | memcpy(ptr, buf, l); |
3a7d929e FB |
3423 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3424 | /* invalidate code */ | |
3425 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3426 | /* set dirty bit */ | |
f7c11b53 YT |
3427 | cpu_physical_memory_set_dirty_flags( |
3428 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3429 | } |
13eb76e0 FB |
3430 | } |
3431 | } else { | |
5fafdf24 | 3432 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3433 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3434 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3435 | /* I/O case */ |
3436 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3437 | if (p) |
6c2934db AJ |
3438 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3439 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3440 | /* 32 bit read access */ |
6c2934db | 3441 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3442 | stl_p(buf, val); |
13eb76e0 | 3443 | l = 4; |
6c2934db | 3444 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3445 | /* 16 bit read access */ |
6c2934db | 3446 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3447 | stw_p(buf, val); |
13eb76e0 FB |
3448 | l = 2; |
3449 | } else { | |
1c213d19 | 3450 | /* 8 bit read access */ |
6c2934db | 3451 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3452 | stb_p(buf, val); |
13eb76e0 FB |
3453 | l = 1; |
3454 | } | |
3455 | } else { | |
3456 | /* RAM case */ | |
5579c7f3 | 3457 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3458 | (addr & ~TARGET_PAGE_MASK); |
3459 | memcpy(buf, ptr, l); | |
3460 | } | |
3461 | } | |
3462 | len -= l; | |
3463 | buf += l; | |
3464 | addr += l; | |
3465 | } | |
3466 | } | |
8df1cd07 | 3467 | |
d0ecd2aa | 3468 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3469 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3470 | const uint8_t *buf, int len) |
3471 | { | |
3472 | int l; | |
3473 | uint8_t *ptr; | |
c227f099 | 3474 | target_phys_addr_t page; |
d0ecd2aa FB |
3475 | unsigned long pd; |
3476 | PhysPageDesc *p; | |
3b46e624 | 3477 | |
d0ecd2aa FB |
3478 | while (len > 0) { |
3479 | page = addr & TARGET_PAGE_MASK; | |
3480 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3481 | if (l > len) | |
3482 | l = len; | |
3483 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3484 | if (!p) { | |
3485 | pd = IO_MEM_UNASSIGNED; | |
3486 | } else { | |
3487 | pd = p->phys_offset; | |
3488 | } | |
3b46e624 | 3489 | |
d0ecd2aa | 3490 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3491 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3492 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3493 | /* do nothing */ |
3494 | } else { | |
3495 | unsigned long addr1; | |
3496 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3497 | /* ROM/RAM case */ | |
5579c7f3 | 3498 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3499 | memcpy(ptr, buf, l); |
3500 | } | |
3501 | len -= l; | |
3502 | buf += l; | |
3503 | addr += l; | |
3504 | } | |
3505 | } | |
3506 | ||
6d16c2f8 AL |
3507 | typedef struct { |
3508 | void *buffer; | |
c227f099 AL |
3509 | target_phys_addr_t addr; |
3510 | target_phys_addr_t len; | |
6d16c2f8 AL |
3511 | } BounceBuffer; |
3512 | ||
3513 | static BounceBuffer bounce; | |
3514 | ||
ba223c29 AL |
3515 | typedef struct MapClient { |
3516 | void *opaque; | |
3517 | void (*callback)(void *opaque); | |
72cf2d4f | 3518 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3519 | } MapClient; |
3520 | ||
72cf2d4f BS |
3521 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3522 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3523 | |
3524 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3525 | { | |
3526 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3527 | ||
3528 | client->opaque = opaque; | |
3529 | client->callback = callback; | |
72cf2d4f | 3530 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3531 | return client; |
3532 | } | |
3533 | ||
3534 | void cpu_unregister_map_client(void *_client) | |
3535 | { | |
3536 | MapClient *client = (MapClient *)_client; | |
3537 | ||
72cf2d4f | 3538 | QLIST_REMOVE(client, link); |
34d5e948 | 3539 | qemu_free(client); |
ba223c29 AL |
3540 | } |
3541 | ||
3542 | static void cpu_notify_map_clients(void) | |
3543 | { | |
3544 | MapClient *client; | |
3545 | ||
72cf2d4f BS |
3546 | while (!QLIST_EMPTY(&map_client_list)) { |
3547 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3548 | client->callback(client->opaque); |
34d5e948 | 3549 | cpu_unregister_map_client(client); |
ba223c29 AL |
3550 | } |
3551 | } | |
3552 | ||
6d16c2f8 AL |
3553 | /* Map a physical memory region into a host virtual address. |
3554 | * May map a subset of the requested range, given by and returned in *plen. | |
3555 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3556 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3557 | * Use cpu_register_map_client() to know when retrying the map operation is |
3558 | * likely to succeed. | |
6d16c2f8 | 3559 | */ |
c227f099 AL |
3560 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3561 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3562 | int is_write) |
3563 | { | |
c227f099 AL |
3564 | target_phys_addr_t len = *plen; |
3565 | target_phys_addr_t done = 0; | |
6d16c2f8 AL |
3566 | int l; |
3567 | uint8_t *ret = NULL; | |
3568 | uint8_t *ptr; | |
c227f099 | 3569 | target_phys_addr_t page; |
6d16c2f8 AL |
3570 | unsigned long pd; |
3571 | PhysPageDesc *p; | |
3572 | unsigned long addr1; | |
3573 | ||
3574 | while (len > 0) { | |
3575 | page = addr & TARGET_PAGE_MASK; | |
3576 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3577 | if (l > len) | |
3578 | l = len; | |
3579 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3580 | if (!p) { | |
3581 | pd = IO_MEM_UNASSIGNED; | |
3582 | } else { | |
3583 | pd = p->phys_offset; | |
3584 | } | |
3585 | ||
3586 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3587 | if (done || bounce.buffer) { | |
3588 | break; | |
3589 | } | |
3590 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3591 | bounce.addr = addr; | |
3592 | bounce.len = l; | |
3593 | if (!is_write) { | |
3594 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); | |
3595 | } | |
3596 | ptr = bounce.buffer; | |
3597 | } else { | |
3598 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3599 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3600 | } |
3601 | if (!done) { | |
3602 | ret = ptr; | |
3603 | } else if (ret + done != ptr) { | |
3604 | break; | |
3605 | } | |
3606 | ||
3607 | len -= l; | |
3608 | addr += l; | |
3609 | done += l; | |
3610 | } | |
3611 | *plen = done; | |
3612 | return ret; | |
3613 | } | |
3614 | ||
3615 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3616 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3617 | * the amount of memory that was actually read or written by the caller. | |
3618 | */ | |
c227f099 AL |
3619 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
3620 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
3621 | { |
3622 | if (buffer != bounce.buffer) { | |
3623 | if (is_write) { | |
c227f099 | 3624 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); |
6d16c2f8 AL |
3625 | while (access_len) { |
3626 | unsigned l; | |
3627 | l = TARGET_PAGE_SIZE; | |
3628 | if (l > access_len) | |
3629 | l = access_len; | |
3630 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3631 | /* invalidate code */ | |
3632 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3633 | /* set dirty bit */ | |
f7c11b53 YT |
3634 | cpu_physical_memory_set_dirty_flags( |
3635 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
6d16c2f8 AL |
3636 | } |
3637 | addr1 += l; | |
3638 | access_len -= l; | |
3639 | } | |
3640 | } | |
3641 | return; | |
3642 | } | |
3643 | if (is_write) { | |
3644 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3645 | } | |
f8a83245 | 3646 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3647 | bounce.buffer = NULL; |
ba223c29 | 3648 | cpu_notify_map_clients(); |
6d16c2f8 | 3649 | } |
d0ecd2aa | 3650 | |
8df1cd07 | 3651 | /* warning: addr must be aligned */ |
c227f099 | 3652 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
3653 | { |
3654 | int io_index; | |
3655 | uint8_t *ptr; | |
3656 | uint32_t val; | |
3657 | unsigned long pd; | |
3658 | PhysPageDesc *p; | |
3659 | ||
3660 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3661 | if (!p) { | |
3662 | pd = IO_MEM_UNASSIGNED; | |
3663 | } else { | |
3664 | pd = p->phys_offset; | |
3665 | } | |
3b46e624 | 3666 | |
5fafdf24 | 3667 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3668 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
3669 | /* I/O case */ |
3670 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3671 | if (p) |
3672 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3673 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
3674 | } else { | |
3675 | /* RAM case */ | |
5579c7f3 | 3676 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
3677 | (addr & ~TARGET_PAGE_MASK); |
3678 | val = ldl_p(ptr); | |
3679 | } | |
3680 | return val; | |
3681 | } | |
3682 | ||
84b7b8e7 | 3683 | /* warning: addr must be aligned */ |
c227f099 | 3684 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
3685 | { |
3686 | int io_index; | |
3687 | uint8_t *ptr; | |
3688 | uint64_t val; | |
3689 | unsigned long pd; | |
3690 | PhysPageDesc *p; | |
3691 | ||
3692 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3693 | if (!p) { | |
3694 | pd = IO_MEM_UNASSIGNED; | |
3695 | } else { | |
3696 | pd = p->phys_offset; | |
3697 | } | |
3b46e624 | 3698 | |
2a4188a3 FB |
3699 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
3700 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
3701 | /* I/O case */ |
3702 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3703 | if (p) |
3704 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
3705 | #ifdef TARGET_WORDS_BIGENDIAN |
3706 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
3707 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
3708 | #else | |
3709 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
3710 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
3711 | #endif | |
3712 | } else { | |
3713 | /* RAM case */ | |
5579c7f3 | 3714 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
3715 | (addr & ~TARGET_PAGE_MASK); |
3716 | val = ldq_p(ptr); | |
3717 | } | |
3718 | return val; | |
3719 | } | |
3720 | ||
aab33094 | 3721 | /* XXX: optimize */ |
c227f099 | 3722 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
3723 | { |
3724 | uint8_t val; | |
3725 | cpu_physical_memory_read(addr, &val, 1); | |
3726 | return val; | |
3727 | } | |
3728 | ||
733f0b02 | 3729 | /* warning: addr must be aligned */ |
c227f099 | 3730 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 | 3731 | { |
733f0b02 MT |
3732 | int io_index; |
3733 | uint8_t *ptr; | |
3734 | uint64_t val; | |
3735 | unsigned long pd; | |
3736 | PhysPageDesc *p; | |
3737 | ||
3738 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3739 | if (!p) { | |
3740 | pd = IO_MEM_UNASSIGNED; | |
3741 | } else { | |
3742 | pd = p->phys_offset; | |
3743 | } | |
3744 | ||
3745 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
3746 | !(pd & IO_MEM_ROMD)) { | |
3747 | /* I/O case */ | |
3748 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3749 | if (p) | |
3750 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
3751 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); | |
3752 | } else { | |
3753 | /* RAM case */ | |
3754 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
3755 | (addr & ~TARGET_PAGE_MASK); | |
3756 | val = lduw_p(ptr); | |
3757 | } | |
3758 | return val; | |
aab33094 FB |
3759 | } |
3760 | ||
8df1cd07 FB |
3761 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3762 | and the code inside is not invalidated. It is useful if the dirty | |
3763 | bits are used to track modified PTEs */ | |
c227f099 | 3764 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3765 | { |
3766 | int io_index; | |
3767 | uint8_t *ptr; | |
3768 | unsigned long pd; | |
3769 | PhysPageDesc *p; | |
3770 | ||
3771 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3772 | if (!p) { | |
3773 | pd = IO_MEM_UNASSIGNED; | |
3774 | } else { | |
3775 | pd = p->phys_offset; | |
3776 | } | |
3b46e624 | 3777 | |
3a7d929e | 3778 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3779 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3780 | if (p) |
3781 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3782 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3783 | } else { | |
74576198 | 3784 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 3785 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3786 | stl_p(ptr, val); |
74576198 AL |
3787 | |
3788 | if (unlikely(in_migration)) { | |
3789 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3790 | /* invalidate code */ | |
3791 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3792 | /* set dirty bit */ | |
f7c11b53 YT |
3793 | cpu_physical_memory_set_dirty_flags( |
3794 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
74576198 AL |
3795 | } |
3796 | } | |
8df1cd07 FB |
3797 | } |
3798 | } | |
3799 | ||
c227f099 | 3800 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
3801 | { |
3802 | int io_index; | |
3803 | uint8_t *ptr; | |
3804 | unsigned long pd; | |
3805 | PhysPageDesc *p; | |
3806 | ||
3807 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3808 | if (!p) { | |
3809 | pd = IO_MEM_UNASSIGNED; | |
3810 | } else { | |
3811 | pd = p->phys_offset; | |
3812 | } | |
3b46e624 | 3813 | |
bc98a7ef JM |
3814 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3815 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3816 | if (p) |
3817 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
3818 | #ifdef TARGET_WORDS_BIGENDIAN |
3819 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3820 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3821 | #else | |
3822 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3823 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3824 | #endif | |
3825 | } else { | |
5579c7f3 | 3826 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3827 | (addr & ~TARGET_PAGE_MASK); |
3828 | stq_p(ptr, val); | |
3829 | } | |
3830 | } | |
3831 | ||
8df1cd07 | 3832 | /* warning: addr must be aligned */ |
c227f099 | 3833 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3834 | { |
3835 | int io_index; | |
3836 | uint8_t *ptr; | |
3837 | unsigned long pd; | |
3838 | PhysPageDesc *p; | |
3839 | ||
3840 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3841 | if (!p) { | |
3842 | pd = IO_MEM_UNASSIGNED; | |
3843 | } else { | |
3844 | pd = p->phys_offset; | |
3845 | } | |
3b46e624 | 3846 | |
3a7d929e | 3847 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3848 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3849 | if (p) |
3850 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3851 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3852 | } else { | |
3853 | unsigned long addr1; | |
3854 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3855 | /* RAM case */ | |
5579c7f3 | 3856 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3857 | stl_p(ptr, val); |
3a7d929e FB |
3858 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3859 | /* invalidate code */ | |
3860 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3861 | /* set dirty bit */ | |
f7c11b53 YT |
3862 | cpu_physical_memory_set_dirty_flags(addr1, |
3863 | (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3864 | } |
8df1cd07 FB |
3865 | } |
3866 | } | |
3867 | ||
aab33094 | 3868 | /* XXX: optimize */ |
c227f099 | 3869 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3870 | { |
3871 | uint8_t v = val; | |
3872 | cpu_physical_memory_write(addr, &v, 1); | |
3873 | } | |
3874 | ||
733f0b02 | 3875 | /* warning: addr must be aligned */ |
c227f099 | 3876 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 | 3877 | { |
733f0b02 MT |
3878 | int io_index; |
3879 | uint8_t *ptr; | |
3880 | unsigned long pd; | |
3881 | PhysPageDesc *p; | |
3882 | ||
3883 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3884 | if (!p) { | |
3885 | pd = IO_MEM_UNASSIGNED; | |
3886 | } else { | |
3887 | pd = p->phys_offset; | |
3888 | } | |
3889 | ||
3890 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3891 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3892 | if (p) | |
3893 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
3894 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); | |
3895 | } else { | |
3896 | unsigned long addr1; | |
3897 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3898 | /* RAM case */ | |
3899 | ptr = qemu_get_ram_ptr(addr1); | |
3900 | stw_p(ptr, val); | |
3901 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3902 | /* invalidate code */ | |
3903 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); | |
3904 | /* set dirty bit */ | |
3905 | cpu_physical_memory_set_dirty_flags(addr1, | |
3906 | (0xff & ~CODE_DIRTY_FLAG)); | |
3907 | } | |
3908 | } | |
aab33094 FB |
3909 | } |
3910 | ||
3911 | /* XXX: optimize */ | |
c227f099 | 3912 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
3913 | { |
3914 | val = tswap64(val); | |
3915 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
3916 | } | |
3917 | ||
5e2972fd | 3918 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 3919 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 3920 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3921 | { |
3922 | int l; | |
c227f099 | 3923 | target_phys_addr_t phys_addr; |
9b3c35e0 | 3924 | target_ulong page; |
13eb76e0 FB |
3925 | |
3926 | while (len > 0) { | |
3927 | page = addr & TARGET_PAGE_MASK; | |
3928 | phys_addr = cpu_get_phys_page_debug(env, page); | |
3929 | /* if no physical page mapped, return an error */ | |
3930 | if (phys_addr == -1) | |
3931 | return -1; | |
3932 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3933 | if (l > len) | |
3934 | l = len; | |
5e2972fd | 3935 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
3936 | if (is_write) |
3937 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
3938 | else | |
5e2972fd | 3939 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
3940 | len -= l; |
3941 | buf += l; | |
3942 | addr += l; | |
3943 | } | |
3944 | return 0; | |
3945 | } | |
a68fe89c | 3946 | #endif |
13eb76e0 | 3947 | |
2e70f6ef PB |
3948 | /* in deterministic execution mode, instructions doing device I/Os |
3949 | must be at the end of the TB */ | |
3950 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
3951 | { | |
3952 | TranslationBlock *tb; | |
3953 | uint32_t n, cflags; | |
3954 | target_ulong pc, cs_base; | |
3955 | uint64_t flags; | |
3956 | ||
3957 | tb = tb_find_pc((unsigned long)retaddr); | |
3958 | if (!tb) { | |
3959 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
3960 | retaddr); | |
3961 | } | |
3962 | n = env->icount_decr.u16.low + tb->icount; | |
3963 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
3964 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 3965 | occurred. */ |
2e70f6ef PB |
3966 | n = n - env->icount_decr.u16.low; |
3967 | /* Generate a new TB ending on the I/O insn. */ | |
3968 | n++; | |
3969 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
3970 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 3971 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
3972 | branch. */ |
3973 | #if defined(TARGET_MIPS) | |
3974 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
3975 | env->active_tc.PC -= 4; | |
3976 | env->icount_decr.u16.low++; | |
3977 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
3978 | } | |
3979 | #elif defined(TARGET_SH4) | |
3980 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
3981 | && n > 1) { | |
3982 | env->pc -= 2; | |
3983 | env->icount_decr.u16.low++; | |
3984 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
3985 | } | |
3986 | #endif | |
3987 | /* This should never happen. */ | |
3988 | if (n > CF_COUNT_MASK) | |
3989 | cpu_abort(env, "TB too big during recompile"); | |
3990 | ||
3991 | cflags = n | CF_LAST_IO; | |
3992 | pc = tb->pc; | |
3993 | cs_base = tb->cs_base; | |
3994 | flags = tb->flags; | |
3995 | tb_phys_invalidate(tb, -1); | |
3996 | /* FIXME: In theory this could raise an exception. In practice | |
3997 | we have already translated the block once so it's probably ok. */ | |
3998 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 3999 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
4000 | the first in the TB) then we end up generating a whole new TB and |
4001 | repeating the fault, which is horribly inefficient. | |
4002 | Better would be to execute just this insn uncached, or generate a | |
4003 | second new TB. */ | |
4004 | cpu_resume_from_signal(env, NULL); | |
4005 | } | |
4006 | ||
b3755a91 PB |
4007 | #if !defined(CONFIG_USER_ONLY) |
4008 | ||
e3db7226 FB |
4009 | void dump_exec_info(FILE *f, |
4010 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
4011 | { | |
4012 | int i, target_code_size, max_target_code_size; | |
4013 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
4014 | TranslationBlock *tb; | |
3b46e624 | 4015 | |
e3db7226 FB |
4016 | target_code_size = 0; |
4017 | max_target_code_size = 0; | |
4018 | cross_page = 0; | |
4019 | direct_jmp_count = 0; | |
4020 | direct_jmp2_count = 0; | |
4021 | for(i = 0; i < nb_tbs; i++) { | |
4022 | tb = &tbs[i]; | |
4023 | target_code_size += tb->size; | |
4024 | if (tb->size > max_target_code_size) | |
4025 | max_target_code_size = tb->size; | |
4026 | if (tb->page_addr[1] != -1) | |
4027 | cross_page++; | |
4028 | if (tb->tb_next_offset[0] != 0xffff) { | |
4029 | direct_jmp_count++; | |
4030 | if (tb->tb_next_offset[1] != 0xffff) { | |
4031 | direct_jmp2_count++; | |
4032 | } | |
4033 | } | |
4034 | } | |
4035 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 4036 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
4037 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
4038 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
4039 | cpu_fprintf(f, "TB count %d/%d\n", | |
4040 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 4041 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
4042 | nb_tbs ? target_code_size / nb_tbs : 0, |
4043 | max_target_code_size); | |
5fafdf24 | 4044 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
4045 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
4046 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
4047 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
4048 | cross_page, | |
e3db7226 FB |
4049 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
4050 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 4051 | direct_jmp_count, |
e3db7226 FB |
4052 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
4053 | direct_jmp2_count, | |
4054 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 4055 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
4056 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
4057 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
4058 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 4059 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
4060 | } |
4061 | ||
61382a50 FB |
4062 | #define MMUSUFFIX _cmmu |
4063 | #define GETPC() NULL | |
4064 | #define env cpu_single_env | |
b769d8fe | 4065 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
4066 | |
4067 | #define SHIFT 0 | |
4068 | #include "softmmu_template.h" | |
4069 | ||
4070 | #define SHIFT 1 | |
4071 | #include "softmmu_template.h" | |
4072 | ||
4073 | #define SHIFT 2 | |
4074 | #include "softmmu_template.h" | |
4075 | ||
4076 | #define SHIFT 3 | |
4077 | #include "softmmu_template.h" | |
4078 | ||
4079 | #undef env | |
4080 | ||
4081 | #endif |