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1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
b6a0aa05 22#include "qemu/osdep.h"
4684a204 23#include "qemu/error-report.h"
6333e93c 24#include "qapi/error.h"
1da12ec4
LT		 25#include "hw/sysbus.h"
26#include "exec/address-spaces.h"
27#include "intel_iommu_internal.h"
7df953bd 28#include "hw/pci/pci.h"
3cb3b154 29#include "hw/pci/pci_bus.h"
621d983a 30#include "hw/i386/pc.h"
dea651a9 31#include "hw/i386/apic-msidef.h"
04af0e18
PX		 32#include "hw/boards.h"
33#include "hw/i386/x86-iommu.h"
cb135f59 34#include "hw/pci-host/q35.h"
4684a204 35#include "sysemu/kvm.h"
32946019 36#include "hw/i386/apic_internal.h"
fb506e70 37#include "kvm_i386.h"
bc535e59 38#include "trace.h"
1da12ec4 39
1da12ec4
LT		 40static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
41 uint64_t wmask, uint64_t w1cmask)
42{
43 stq_le_p(&s->csr[addr], val);
44 stq_le_p(&s->wmask[addr], wmask);
45 stq_le_p(&s->w1cmask[addr], w1cmask);
46}
47
48static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
49{
50 stq_le_p(&s->womask[addr], mask);
51}
52
53static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
54 uint32_t wmask, uint32_t w1cmask)
55{
56 stl_le_p(&s->csr[addr], val);
57 stl_le_p(&s->wmask[addr], wmask);
58 stl_le_p(&s->w1cmask[addr], w1cmask);
59}
60
61static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
62{
63 stl_le_p(&s->womask[addr], mask);
64}
65
66/* "External" get/set operations */
67static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
68{
69 uint64_t oldval = ldq_le_p(&s->csr[addr]);
70 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
71 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
72 stq_le_p(&s->csr[addr],
73 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
74}
75
76static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
77{
78 uint32_t oldval = ldl_le_p(&s->csr[addr]);
79 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
80 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
81 stl_le_p(&s->csr[addr],
82 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
83}
84
85static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
86{
87 uint64_t val = ldq_le_p(&s->csr[addr]);
88 uint64_t womask = ldq_le_p(&s->womask[addr]);
89 return val & ~womask;
90}
91
92static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
93{
94 uint32_t val = ldl_le_p(&s->csr[addr]);
95 uint32_t womask = ldl_le_p(&s->womask[addr]);
96 return val & ~womask;
97}
98
99/* "Internal" get/set operations */
100static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
101{
102 return ldq_le_p(&s->csr[addr]);
103}
104
105static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
106{
107 return ldl_le_p(&s->csr[addr]);
108}
109
110static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
111{
112 stq_le_p(&s->csr[addr], val);
113}
114
115static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
116 uint32_t clear, uint32_t mask)
117{
118 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
119 stl_le_p(&s->csr[addr], new_val);
120 return new_val;
121}
122
123static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
124 uint64_t clear, uint64_t mask)
125{
126 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
127 stq_le_p(&s->csr[addr], new_val);
128 return new_val;
129}
130
1d9efa73
PX		 131static inline void vtd_iommu_lock(IntelIOMMUState *s)
132{
133 qemu_mutex_lock(&s->iommu_lock);
134}
135
136static inline void vtd_iommu_unlock(IntelIOMMUState *s)
137{
138 qemu_mutex_unlock(&s->iommu_lock);
139}
140
4f8a62a9
PX		 141/* Whether the address space needs to notify new mappings */
142static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as)
143{
144 return as->notifier_flags & IOMMU_NOTIFIER_MAP;
145}
146
b5a280c0
LT		 147/* GHashTable functions */
148static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
149{
150 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
151}
152
153static guint vtd_uint64_hash(gconstpointer v)
154{
155 return (guint)*(const uint64_t *)v;
156}
157
158static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
159 gpointer user_data)
160{
161 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
162 uint16_t domain_id = *(uint16_t *)user_data;
163 return entry->domain_id == domain_id;
164}
165
d66b969b
JW		 166/* The shift of an addr for a certain level of paging structure */
167static inline uint32_t vtd_slpt_level_shift(uint32_t level)
168{
7e58326a 169 assert(level != 0);
d66b969b
JW		 170 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
171}
172
173static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
174{
175 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
176}
177
b5a280c0
LT		 178static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
179 gpointer user_data)
180{
181 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
182 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
d66b969b
JW		 183 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
184 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
b5a280c0 185 return (entry->domain_id == info->domain_id) &&
d66b969b
JW		 186 (((entry->gfn & info->mask) == gfn) ||
187 (entry->gfn == gfn_tlb));
b5a280c0
LT		 188}
189
d92fa2dc 190/* Reset all the gen of VTDAddressSpace to zero and set the gen of
1d9efa73 191 * IntelIOMMUState to 1. Must be called with IOMMU lock held.
d92fa2dc 192 */
1d9efa73 193static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
d92fa2dc 194{
d92fa2dc 195 VTDAddressSpace *vtd_as;
7df953bd
KO		 196 VTDBus *vtd_bus;
197 GHashTableIter bus_it;
d92fa2dc
LT		 198 uint32_t devfn_it;
199
7feb51b7
PX		 200 trace_vtd_context_cache_reset();
201
7df953bd
KO		 202 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
203
7df953bd 204 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
bf33cc75 205 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 206 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 207 if (!vtd_as) {
208 continue;
209 }
210 vtd_as->context_cache_entry.context_cache_gen = 0;
211 }
212 }
213 s->context_cache_gen = 1;
214}
215
1d9efa73
PX		 216/* Must be called with IOMMU lock held. */
217static void vtd_reset_iotlb_locked(IntelIOMMUState *s)
b5a280c0
LT		 218{
219 assert(s->iotlb);
220 g_hash_table_remove_all(s->iotlb);
221}
222
1d9efa73
PX		 223static void vtd_reset_iotlb(IntelIOMMUState *s)
224{
225 vtd_iommu_lock(s);
226 vtd_reset_iotlb_locked(s);
227 vtd_iommu_unlock(s);
228}
229
bacabb0a 230static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
d66b969b
JW		 231 uint32_t level)
232{
233 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
234 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
235}
236
237static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
238{
239 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
240}
241
1d9efa73 242/* Must be called with IOMMU lock held */
b5a280c0
LT		 243static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
244 hwaddr addr)
245{
d66b969b 246 VTDIOTLBEntry *entry;
b5a280c0 247 uint64_t key;
d66b969b
JW		 248 int level;
249
250 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
251 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
252 source_id, level);
253 entry = g_hash_table_lookup(s->iotlb, &key);
254 if (entry) {
255 goto out;
256 }
257 }
b5a280c0 258
d66b969b
JW		 259out:
260 return entry;
b5a280c0
LT		 261}
262
1d9efa73 263/* Must be with IOMMU lock held */
b5a280c0
LT		 264static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
265 uint16_t domain_id, hwaddr addr, uint64_t slpte,
07f7b733 266 uint8_t access_flags, uint32_t level)
b5a280c0
LT		 267{
268 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
269 uint64_t *key = g_malloc(sizeof(*key));
d66b969b 270 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
b5a280c0 271
6c441e1d 272 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
b5a280c0 273 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
6c441e1d 274 trace_vtd_iotlb_reset("iotlb exceeds size limit");
1d9efa73 275 vtd_reset_iotlb_locked(s);
b5a280c0
LT		 276 }
277
278 entry->gfn = gfn;
279 entry->domain_id = domain_id;
280 entry->slpte = slpte;
07f7b733 281 entry->access_flags = access_flags;
d66b969b
JW		 282 entry->mask = vtd_slpt_level_page_mask(level);
283 *key = vtd_get_iotlb_key(gfn, source_id, level);
b5a280c0
LT		 284 g_hash_table_replace(s->iotlb, key, entry);
285}
286
1da12ec4
LT		 287/* Given the reg addr of both the message data and address, generate an
288 * interrupt via MSI.
289 */
290static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
291 hwaddr mesg_data_reg)
292{
32946019 293 MSIMessage msi;
1da12ec4
LT		 294
295 assert(mesg_data_reg < DMAR_REG_SIZE);
296 assert(mesg_addr_reg < DMAR_REG_SIZE);
297
32946019
RK		 298 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
299 msi.data = vtd_get_long_raw(s, mesg_data_reg);
1da12ec4 300
7feb51b7
PX		 301 trace_vtd_irq_generate(msi.address, msi.data);
302
32946019 303 apic_get_class()->send_msi(&msi);
1da12ec4
LT		 304}
305
306/* Generate a fault event to software via MSI if conditions are met.
307 * Notice that the value of FSTS_REG being passed to it should be the one
308 * before any update.
309 */
310static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
311{
312 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
313 pre_fsts & VTD_FSTS_IQE) {
7feb51b7
PX		 314 trace_vtd_err("There are previous interrupt conditions "
315 "to be serviced by software, fault event "
316 "is not generated.");
1da12ec4
LT		 317 return;
318 }
319 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
320 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
7feb51b7 321 trace_vtd_err("Interrupt Mask set, irq is not generated.");
1da12ec4
LT		 322 } else {
323 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
324 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
325 }
326}
327
328/* Check if the Fault (F) field of the Fault Recording Register referenced by
329 * @index is Set.
330 */
331static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
332{
333 /* Each reg is 128-bit */
334 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
335 addr += 8; /* Access the high 64-bit half */
336
337 assert(index < DMAR_FRCD_REG_NR);
338
339 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
340}
341
342/* Update the PPF field of Fault Status Register.
343 * Should be called whenever change the F field of any fault recording
344 * registers.
345 */
346static void vtd_update_fsts_ppf(IntelIOMMUState *s)
347{
348 uint32_t i;
349 uint32_t ppf_mask = 0;
350
351 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
352 if (vtd_is_frcd_set(s, i)) {
353 ppf_mask = VTD_FSTS_PPF;
354 break;
355 }
356 }
357 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
7feb51b7 358 trace_vtd_fsts_ppf(!!ppf_mask);
1da12ec4
LT		 359}
360
361static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
362{
363 /* Each reg is 128-bit */
364 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
365 addr += 8; /* Access the high 64-bit half */
366
367 assert(index < DMAR_FRCD_REG_NR);
368
369 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
370 vtd_update_fsts_ppf(s);
371}
372
373/* Must not update F field now, should be done later */
374static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
375 uint16_t source_id, hwaddr addr,
376 VTDFaultReason fault, bool is_write)
377{
378 uint64_t hi = 0, lo;
379 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
380
381 assert(index < DMAR_FRCD_REG_NR);
382
383 lo = VTD_FRCD_FI(addr);
384 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
385 if (!is_write) {
386 hi |= VTD_FRCD_T;
387 }
388 vtd_set_quad_raw(s, frcd_reg_addr, lo);
389 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
7feb51b7
PX		 390
391 trace_vtd_frr_new(index, hi, lo);
1da12ec4
LT		 392}
393
394/* Try to collapse multiple pending faults from the same requester */
395static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
396{
397 uint32_t i;
398 uint64_t frcd_reg;
399 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
400
401 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
402 frcd_reg = vtd_get_quad_raw(s, addr);
1da12ec4
LT		 403 if ((frcd_reg & VTD_FRCD_F) &&
404 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
405 return true;
406 }
407 addr += 16; /* 128-bit for each */
408 }
409 return false;
410}
411
412/* Log and report an DMAR (address translation) fault to software */
413static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
414 hwaddr addr, VTDFaultReason fault,
415 bool is_write)
416{
417 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
418
419 assert(fault < VTD_FR_MAX);
420
421 if (fault == VTD_FR_RESERVED_ERR) {
422 /* This is not a normal fault reason case. Drop it. */
423 return;
424 }
7feb51b7
PX		 425
426 trace_vtd_dmar_fault(source_id, fault, addr, is_write);
427
1da12ec4 428 if (fsts_reg & VTD_FSTS_PFO) {
7feb51b7
PX		 429 trace_vtd_err("New fault is not recorded due to "
430 "Primary Fault Overflow.");
1da12ec4
LT		 431 return;
432 }
7feb51b7 433
1da12ec4 434 if (vtd_try_collapse_fault(s, source_id)) {
7feb51b7
PX		 435 trace_vtd_err("New fault is not recorded due to "
436 "compression of faults.");
1da12ec4
LT		 437 return;
438 }
7feb51b7 439
1da12ec4 440 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
7feb51b7
PX		 441 trace_vtd_err("Next Fault Recording Reg is used, "
442 "new fault is not recorded, set PFO field.");
1da12ec4
LT		 443 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
444 return;
445 }
446
447 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
448
449 if (fsts_reg & VTD_FSTS_PPF) {
7feb51b7
PX		 450 trace_vtd_err("There are pending faults already, "
451 "fault event is not generated.");
1da12ec4
LT		 452 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
453 s->next_frcd_reg++;
454 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
455 s->next_frcd_reg = 0;
456 }
457 } else {
458 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
459 VTD_FSTS_FRI(s->next_frcd_reg));
460 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
461 s->next_frcd_reg++;
462 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
463 s->next_frcd_reg = 0;
464 }
465 /* This case actually cause the PPF to be Set.
466 * So generate fault event (interrupt).
467 */
468 vtd_generate_fault_event(s, fsts_reg);
469 }
470}
471
ed7b8fbc
LT		 472/* Handle Invalidation Queue Errors of queued invalidation interface error
473 * conditions.
474 */
475static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
476{
477 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
478
479 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
480 vtd_generate_fault_event(s, fsts_reg);
481}
482
483/* Set the IWC field and try to generate an invalidation completion interrupt */
484static void vtd_generate_completion_event(IntelIOMMUState *s)
485{
ed7b8fbc 486 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
bc535e59 487 trace_vtd_inv_desc_wait_irq("One pending, skip current");
ed7b8fbc
LT		 488 return;
489 }
490 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
491 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
492 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
bc535e59
PX		 493 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
494 "new event not generated");
ed7b8fbc
LT		 495 return;
496 } else {
497 /* Generate the interrupt event */
bc535e59 498 trace_vtd_inv_desc_wait_irq("Generating complete event");
ed7b8fbc
LT		 499 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
500 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
501 }
502}
503
1da12ec4
LT		 504static inline bool vtd_root_entry_present(VTDRootEntry *root)
505{
506 return root->val & VTD_ROOT_ENTRY_P;
507}
508
509static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
510 VTDRootEntry *re)
511{
512 dma_addr_t addr;
513
514 addr = s->root + index * sizeof(*re);
515 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
6c441e1d 516 trace_vtd_re_invalid(re->rsvd, re->val);
1da12ec4
LT		 517 re->val = 0;
518 return -VTD_FR_ROOT_TABLE_INV;
519 }
520 re->val = le64_to_cpu(re->val);
521 return 0;
522}
523
8f7d7161 524static inline bool vtd_ce_present(VTDContextEntry *context)
1da12ec4
LT		 525{
526 return context->lo & VTD_CONTEXT_ENTRY_P;
527}
528
529static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
530 VTDContextEntry *ce)
531{
532 dma_addr_t addr;
533
6c441e1d 534 /* we have checked that root entry is present */
1da12ec4
LT		 535 addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
536 if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
6c441e1d 537 trace_vtd_re_invalid(root->rsvd, root->val);
1da12ec4
LT		 538 return -VTD_FR_CONTEXT_TABLE_INV;
539 }
540 ce->lo = le64_to_cpu(ce->lo);
541 ce->hi = le64_to_cpu(ce->hi);
542 return 0;
543}
544
8f7d7161 545static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
1da12ec4
LT		 546{
547 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
548}
549
37f51384 550static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
1da12ec4 551{
37f51384 552 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw);
1da12ec4
LT		 553}
554
555/* Whether the pte indicates the address of the page frame */
556static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
557{
558 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
559}
560
561/* Get the content of a spte located in @base_addr[@index] */
562static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
563{
564 uint64_t slpte;
565
566 assert(index < VTD_SL_PT_ENTRY_NR);
567
568 if (dma_memory_read(&address_space_memory,
569 base_addr + index * sizeof(slpte), &slpte,
570 sizeof(slpte))) {
571 slpte = (uint64_t)-1;
572 return slpte;
573 }
574 slpte = le64_to_cpu(slpte);
575 return slpte;
576}
577
6e905564
PX		 578/* Given an iova and the level of paging structure, return the offset
579 * of current level.
1da12ec4 580 */
6e905564 581static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
1da12ec4 582{
6e905564 583 return (iova >> vtd_slpt_level_shift(level)) &
1da12ec4
LT		 584 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
585}
586
587/* Check Capability Register to see if the @level of page-table is supported */
588static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
589{
590 return VTD_CAP_SAGAW_MASK & s->cap &
591 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
592}
593
594/* Get the page-table level that hardware should use for the second-level
595 * page-table walk from the Address Width field of context-entry.
596 */
8f7d7161 597static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce)
1da12ec4
LT		 598{
599 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
600}
601
8f7d7161 602static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce)
1da12ec4
LT		 603{
604 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
605}
606
127ff5c3
PX		 607static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce)
608{
609 return ce->lo & VTD_CONTEXT_ENTRY_TT;
610}
611
f80c9874
PX		 612/* Return true if check passed, otherwise false */
613static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
614 VTDContextEntry *ce)
615{
616 switch (vtd_ce_get_type(ce)) {
617 case VTD_CONTEXT_TT_MULTI_LEVEL:
618 /* Always supported */
619 break;
620 case VTD_CONTEXT_TT_DEV_IOTLB:
621 if (!x86_iommu->dt_supported) {
622 return false;
623 }
624 break;
dbaabb25
PX		 625 case VTD_CONTEXT_TT_PASS_THROUGH:
626 if (!x86_iommu->pt_supported) {
627 return false;
628 }
629 break;
f80c9874
PX		 630 default:
631 /* Unknwon type */
632 return false;
633 }
634 return true;
635}
636
37f51384 637static inline uint64_t vtd_iova_limit(VTDContextEntry *ce, uint8_t aw)
f06a696d 638{
8f7d7161 639 uint32_t ce_agaw = vtd_ce_get_agaw(ce);
37f51384 640 return 1ULL << MIN(ce_agaw, aw);
f06a696d
PX		 641}
642
643/* Return true if IOVA passes range check, otherwise false. */
37f51384
PS		 644static inline bool vtd_iova_range_check(uint64_t iova, VTDContextEntry *ce,
645 uint8_t aw)
f06a696d
PX		 646{
647 /*
648 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
649 * in CAP_REG and AW in context-entry.
650 */
37f51384 651 return !(iova & ~(vtd_iova_limit(ce, aw) - 1));
f06a696d
PX		 652}
653
92e5d85e
PS		 654/*
655 * Rsvd field masks for spte:
656 * Index [1] to [4] 4k pages
657 * Index [5] to [8] large pages
658 */
659static uint64_t vtd_paging_entry_rsvd_field[9];
1da12ec4
LT		 660
661static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
662{
663 if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
664 /* Maybe large page */
665 return slpte & vtd_paging_entry_rsvd_field[level + 4];
666 } else {
667 return slpte & vtd_paging_entry_rsvd_field[level];
668 }
669}
670
dbaabb25
PX		 671/* Find the VTD address space associated with a given bus number */
672static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
673{
674 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
675 if (!vtd_bus) {
676 /*
677 * Iterate over the registered buses to find the one which
678 * currently hold this bus number, and update the bus_num
679 * lookup table:
680 */
681 GHashTableIter iter;
682
683 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
684 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
685 if (pci_bus_num(vtd_bus->bus) == bus_num) {
686 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
687 return vtd_bus;
688 }
689 }
690 }
691 return vtd_bus;
692}
693
6e905564 694/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
1da12ec4
LT		 695 * of the translation, can be used for deciding the size of large page.
696 */
6e905564
PX		 697static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
698 uint64_t *slptep, uint32_t *slpte_level,
37f51384 699 bool *reads, bool *writes, uint8_t aw_bits)
1da12ec4 700{
8f7d7161
PX		 701 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
702 uint32_t level = vtd_ce_get_level(ce);
1da12ec4
LT		 703 uint32_t offset;
704 uint64_t slpte;
1da12ec4
LT		 705 uint64_t access_right_check;
706
37f51384 707 if (!vtd_iova_range_check(iova, ce, aw_bits)) {
7feb51b7 708 trace_vtd_err_dmar_iova_overflow(iova);
1da12ec4
LT		 709 return -VTD_FR_ADDR_BEYOND_MGAW;
710 }
711
712 /* FIXME: what is the Atomics request here? */
713 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
714
715 while (true) {
6e905564 716 offset = vtd_iova_level_offset(iova, level);
1da12ec4
LT		 717 slpte = vtd_get_slpte(addr, offset);
718
719 if (slpte == (uint64_t)-1) {
7feb51b7 720 trace_vtd_err_dmar_slpte_read_error(iova, level);
8f7d7161 721 if (level == vtd_ce_get_level(ce)) {
1da12ec4
LT		 722 /* Invalid programming of context-entry */
723 return -VTD_FR_CONTEXT_ENTRY_INV;
724 } else {
725 return -VTD_FR_PAGING_ENTRY_INV;
726 }
727 }
728 *reads = (*reads) && (slpte & VTD_SL_R);
729 *writes = (*writes) && (slpte & VTD_SL_W);
730 if (!(slpte & access_right_check)) {
7feb51b7 731 trace_vtd_err_dmar_slpte_perm_error(iova, level, slpte, is_write);
1da12ec4
LT		 732 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
733 }
734 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
7feb51b7 735 trace_vtd_err_dmar_slpte_resv_error(iova, level, slpte);
1da12ec4
LT		 736 return -VTD_FR_PAGING_ENTRY_RSVD;
737 }
738
739 if (vtd_is_last_slpte(slpte, level)) {
740 *slptep = slpte;
741 *slpte_level = level;
742 return 0;
743 }
37f51384 744 addr = vtd_get_slpte_addr(slpte, aw_bits);
1da12ec4
LT		 745 level--;
746 }
747}
748
f06a696d
PX		 749typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
750
fe215b0c
PX		 751/**
752 * Constant information used during page walking
753 *
754 * @hook_fn: hook func to be called when detected page
755 * @private: private data to be passed into hook func
756 * @notify_unmap: whether we should notify invalid entries
2f764fa8 757 * @as: VT-d address space of the device
fe215b0c 758 * @aw: maximum address width
d118c06e 759 * @domain: domain ID of the page walk
fe215b0c
PX		 760 */
761typedef struct {
2f764fa8 762 VTDAddressSpace *as;
fe215b0c
PX		 763 vtd_page_walk_hook hook_fn;
764 void *private;
765 bool notify_unmap;
766 uint8_t aw;
d118c06e 767 uint16_t domain_id;
fe215b0c
PX		 768} vtd_page_walk_info;
769
d118c06e 770static int vtd_page_walk_one(IOMMUTLBEntry *entry, vtd_page_walk_info *info)
36d2d52b 771{
fe215b0c
PX		 772 vtd_page_walk_hook hook_fn = info->hook_fn;
773 void *private = info->private;
774
36d2d52b 775 assert(hook_fn);
d118c06e
PX		 776 trace_vtd_page_walk_one(info->domain_id, entry->iova,
777 entry->translated_addr, entry->addr_mask,
778 entry->perm);
36d2d52b
PX		 779 return hook_fn(entry, private);
780}
781
f06a696d
PX		 782/**
783 * vtd_page_walk_level - walk over specific level for IOVA range
784 *
785 * @addr: base GPA addr to start the walk
786 * @start: IOVA range start address
787 * @end: IOVA range end address (start <= addr < end)
f06a696d
PX		 788 * @read: whether parent level has read permission
789 * @write: whether parent level has write permission
fe215b0c 790 * @info: constant information for the page walk
f06a696d
PX		 791 */
792static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
fe215b0c
PX		 793 uint64_t end, uint32_t level, bool read,
794 bool write, vtd_page_walk_info *info)
f06a696d
PX		 795{
796 bool read_cur, write_cur, entry_valid;
797 uint32_t offset;
798 uint64_t slpte;
799 uint64_t subpage_size, subpage_mask;
800 IOMMUTLBEntry entry;
801 uint64_t iova = start;
802 uint64_t iova_next;
803 int ret = 0;
804
805 trace_vtd_page_walk_level(addr, level, start, end);
806
807 subpage_size = 1ULL << vtd_slpt_level_shift(level);
808 subpage_mask = vtd_slpt_level_page_mask(level);
809
810 while (iova < end) {
811 iova_next = (iova & subpage_mask) + subpage_size;
812
813 offset = vtd_iova_level_offset(iova, level);
814 slpte = vtd_get_slpte(addr, offset);
815
816 if (slpte == (uint64_t)-1) {
817 trace_vtd_page_walk_skip_read(iova, iova_next);
818 goto next;
819 }
820
821 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
822 trace_vtd_page_walk_skip_reserve(iova, iova_next);
823 goto next;
824 }
825
826 /* Permissions are stacked with parents' */
827 read_cur = read && (slpte & VTD_SL_R);
828 write_cur = write && (slpte & VTD_SL_W);
829
830 /*
831 * As long as we have either read/write permission, this is a
832 * valid entry. The rule works for both page entries and page
833 * table entries.
834 */
835 entry_valid = read_cur | write_cur;
836
36d2d52b
PX		 837 entry.target_as = &address_space_memory;
838 entry.iova = iova & subpage_mask;
839 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
840 entry.addr_mask = ~subpage_mask;
841
f06a696d 842 if (vtd_is_last_slpte(slpte, level)) {
f06a696d 843 /* NOTE: this is only meaningful if entry_valid == true */
fe215b0c
PX		 844 entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
845 if (!entry_valid && !info->notify_unmap) {
f06a696d
PX		 846 trace_vtd_page_walk_skip_perm(iova, iova_next);
847 goto next;
848 }
d118c06e 849 ret = vtd_page_walk_one(&entry, info);
36d2d52b
PX		 850 if (ret < 0) {
851 return ret;
f06a696d
PX		 852 }
853 } else {
854 if (!entry_valid) {
fe215b0c 855 if (info->notify_unmap) {
36d2d52b
PX		 856 /*
857 * The whole entry is invalid; unmap it all.
858 * Translated address is meaningless, zero it.
859 */
860 entry.translated_addr = 0x0;
d118c06e 861 ret = vtd_page_walk_one(&entry, info);
36d2d52b
PX		 862 if (ret < 0) {
863 return ret;
864 }
865 } else {
866 trace_vtd_page_walk_skip_perm(iova, iova_next);
867 }
f06a696d
PX		 868 goto next;
869 }
fe215b0c
PX		 870 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw),
871 iova, MIN(iova_next, end), level - 1,
872 read_cur, write_cur, info);
f06a696d
PX		 873 if (ret < 0) {
874 return ret;
875 }
876 }
877
878next:
879 iova = iova_next;
880 }
881
882 return 0;
883}
884
885/**
886 * vtd_page_walk - walk specific IOVA range, and call the hook
887 *
888 * @ce: context entry to walk upon
889 * @start: IOVA address to start the walk
890 * @end: IOVA range end address (start <= addr < end)
fe215b0c 891 * @info: page walking information struct
f06a696d
PX		 892 */
893static int vtd_page_walk(VTDContextEntry *ce, uint64_t start, uint64_t end,
fe215b0c 894 vtd_page_walk_info *info)
f06a696d 895{
8f7d7161
PX		 896 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
897 uint32_t level = vtd_ce_get_level(ce);
f06a696d 898
fe215b0c 899 if (!vtd_iova_range_check(start, ce, info->aw)) {
f06a696d
PX		 900 return -VTD_FR_ADDR_BEYOND_MGAW;
901 }
902
fe215b0c 903 if (!vtd_iova_range_check(end, ce, info->aw)) {
f06a696d 904 /* Fix end so that it reaches the maximum */
fe215b0c 905 end = vtd_iova_limit(ce, info->aw);
f06a696d
PX		 906 }
907
fe215b0c 908 return vtd_page_walk_level(addr, start, end, level, true, true, info);
f06a696d
PX		 909}
910
1da12ec4
LT		 911/* Map a device to its corresponding domain (context-entry) */
912static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
913 uint8_t devfn, VTDContextEntry *ce)
914{
915 VTDRootEntry re;
916 int ret_fr;
f80c9874 917 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
1da12ec4
LT		 918
919 ret_fr = vtd_get_root_entry(s, bus_num, &re);
920 if (ret_fr) {
921 return ret_fr;
922 }
923
924 if (!vtd_root_entry_present(&re)) {
6c441e1d
PX		 925 /* Not error - it's okay we don't have root entry. */
926 trace_vtd_re_not_present(bus_num);
1da12ec4 927 return -VTD_FR_ROOT_ENTRY_P;
f80c9874
PX		 928 }
929
37f51384 930 if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD(s->aw_bits))) {
6c441e1d 931 trace_vtd_re_invalid(re.rsvd, re.val);
1da12ec4
LT		 932 return -VTD_FR_ROOT_ENTRY_RSVD;
933 }
934
935 ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
936 if (ret_fr) {
937 return ret_fr;
938 }
939
8f7d7161 940 if (!vtd_ce_present(ce)) {
6c441e1d
PX		 941 /* Not error - it's okay we don't have context entry. */
942 trace_vtd_ce_not_present(bus_num, devfn);
1da12ec4 943 return -VTD_FR_CONTEXT_ENTRY_P;
f80c9874
PX		 944 }
945
946 if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
37f51384 947 (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) {
6c441e1d 948 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4
LT		 949 return -VTD_FR_CONTEXT_ENTRY_RSVD;
950 }
f80c9874 951
1da12ec4 952 /* Check if the programming of context-entry is valid */
8f7d7161 953 if (!vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
6c441e1d 954 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4 955 return -VTD_FR_CONTEXT_ENTRY_INV;
1da12ec4 956 }
f80c9874
PX		 957
958 /* Do translation type check */
959 if (!vtd_ce_type_check(x86_iommu, ce)) {
960 trace_vtd_ce_invalid(ce->hi, ce->lo);
961 return -VTD_FR_CONTEXT_ENTRY_INV;
962 }
963
1da12ec4
LT		 964 return 0;
965}
966
dbaabb25
PX		 967/*
968 * Fetch translation type for specific device. Returns <0 if error
969 * happens, otherwise return the shifted type to check against
970 * VTD_CONTEXT_TT_*.
971 */
972static int vtd_dev_get_trans_type(VTDAddressSpace *as)
973{
974 IntelIOMMUState *s;
975 VTDContextEntry ce;
976 int ret;
977
978 s = as->iommu_state;
979
980 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus),
981 as->devfn, &ce);
982 if (ret) {
983 return ret;
984 }
985
986 return vtd_ce_get_type(&ce);
987}
988
989static bool vtd_dev_pt_enabled(VTDAddressSpace *as)
990{
991 int ret;
992
993 assert(as);
994
995 ret = vtd_dev_get_trans_type(as);
996 if (ret < 0) {
997 /*
998 * Possibly failed to parse the context entry for some reason
999 * (e.g., during init, or any guest configuration errors on
1000 * context entries). We should assume PT not enabled for
1001 * safety.
1002 */
1003 return false;
1004 }
1005
1006 return ret == VTD_CONTEXT_TT_PASS_THROUGH;
1007}
1008
1009/* Return whether the device is using IOMMU translation. */
1010static bool vtd_switch_address_space(VTDAddressSpace *as)
1011{
1012 bool use_iommu;
66a4a031
PX		 1013 /* Whether we need to take the BQL on our own */
1014 bool take_bql = !qemu_mutex_iothread_locked();
dbaabb25
PX		 1015
1016 assert(as);
1017
1018 use_iommu = as->iommu_state->dmar_enabled & !vtd_dev_pt_enabled(as);
1019
1020 trace_vtd_switch_address_space(pci_bus_num(as->bus),
1021 VTD_PCI_SLOT(as->devfn),
1022 VTD_PCI_FUNC(as->devfn),
1023 use_iommu);
1024
66a4a031
PX		 1025 /*
1026 * It's possible that we reach here without BQL, e.g., when called
1027 * from vtd_pt_enable_fast_path(). However the memory APIs need
1028 * it. We'd better make sure we have had it already, or, take it.
1029 */
1030 if (take_bql) {
1031 qemu_mutex_lock_iothread();
1032 }
1033
dbaabb25
PX		 1034 /* Turn off first then on the other */
1035 if (use_iommu) {
1036 memory_region_set_enabled(&as->sys_alias, false);
3df9d748 1037 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true);
dbaabb25 1038 } else {
3df9d748 1039 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false);
dbaabb25
PX		 1040 memory_region_set_enabled(&as->sys_alias, true);
1041 }
1042
66a4a031
PX		 1043 if (take_bql) {
1044 qemu_mutex_unlock_iothread();
1045 }
1046
dbaabb25
PX		 1047 return use_iommu;
1048}
1049
1050static void vtd_switch_address_space_all(IntelIOMMUState *s)
1051{
1052 GHashTableIter iter;
1053 VTDBus *vtd_bus;
1054 int i;
1055
1056 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1057 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
bf33cc75 1058 for (i = 0; i < PCI_DEVFN_MAX; i++) {
dbaabb25
PX		 1059 if (!vtd_bus->dev_as[i]) {
1060 continue;
1061 }
1062 vtd_switch_address_space(vtd_bus->dev_as[i]);
1063 }
1064 }
1065}
1066
1da12ec4
LT		 1067static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
1068{
1069 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
1070}
1071
1072static const bool vtd_qualified_faults[] = {
1073 [VTD_FR_RESERVED] = false,
1074 [VTD_FR_ROOT_ENTRY_P] = false,
1075 [VTD_FR_CONTEXT_ENTRY_P] = true,
1076 [VTD_FR_CONTEXT_ENTRY_INV] = true,
1077 [VTD_FR_ADDR_BEYOND_MGAW] = true,
1078 [VTD_FR_WRITE] = true,
1079 [VTD_FR_READ] = true,
1080 [VTD_FR_PAGING_ENTRY_INV] = true,
1081 [VTD_FR_ROOT_TABLE_INV] = false,
1082 [VTD_FR_CONTEXT_TABLE_INV] = false,
1083 [VTD_FR_ROOT_ENTRY_RSVD] = false,
1084 [VTD_FR_PAGING_ENTRY_RSVD] = true,
1085 [VTD_FR_CONTEXT_ENTRY_TT] = true,
1086 [VTD_FR_RESERVED_ERR] = false,
1087 [VTD_FR_MAX] = false,
1088};
1089
1090/* To see if a fault condition is "qualified", which is reported to software
1091 * only if the FPD field in the context-entry used to process the faulting
1092 * request is 0.
1093 */
1094static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
1095{
1096 return vtd_qualified_faults[fault];
1097}
1098
1099static inline bool vtd_is_interrupt_addr(hwaddr addr)
1100{
1101 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
1102}
1103
dbaabb25
PX		 1104static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
1105{
1106 VTDBus *vtd_bus;
1107 VTDAddressSpace *vtd_as;
1108 bool success = false;
1109
1110 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
1111 if (!vtd_bus) {
1112 goto out;
1113 }
1114
1115 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
1116 if (!vtd_as) {
1117 goto out;
1118 }
1119
1120 if (vtd_switch_address_space(vtd_as) == false) {
1121 /* We switched off IOMMU region successfully. */
1122 success = true;
1123 }
1124
1125out:
1126 trace_vtd_pt_enable_fast_path(source_id, success);
1127}
1128
1da12ec4
LT		 1129/* Map dev to context-entry then do a paging-structures walk to do a iommu
1130 * translation.
79e2b9ae
PB		 1131 *
1132 * Called from RCU critical section.
1133 *
1da12ec4
LT		 1134 * @bus_num: The bus number
1135 * @devfn: The devfn, which is the combined of device and function number
1136 * @is_write: The access is a write operation
1137 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
b9313021
PX		 1138 *
1139 * Returns true if translation is successful, otherwise false.
1da12ec4 1140 */
b9313021 1141static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1da12ec4
LT		 1142 uint8_t devfn, hwaddr addr, bool is_write,
1143 IOMMUTLBEntry *entry)
1144{
d92fa2dc 1145 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4 1146 VTDContextEntry ce;
7df953bd 1147 uint8_t bus_num = pci_bus_num(bus);
1d9efa73 1148 VTDContextCacheEntry *cc_entry;
d66b969b 1149 uint64_t slpte, page_mask;
1da12ec4
LT		 1150 uint32_t level;
1151 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
1152 int ret_fr;
1153 bool is_fpd_set = false;
1154 bool reads = true;
1155 bool writes = true;
07f7b733 1156 uint8_t access_flags;
b5a280c0 1157 VTDIOTLBEntry *iotlb_entry;
1da12ec4 1158
046ab7e9
PX		 1159 /*
1160 * We have standalone memory region for interrupt addresses, we
1161 * should never receive translation requests in this region.
1162 */
1163 assert(!vtd_is_interrupt_addr(addr));
1164
1d9efa73
PX		 1165 vtd_iommu_lock(s);
1166
1167 cc_entry = &vtd_as->context_cache_entry;
1168
b5a280c0
LT		 1169 /* Try to fetch slpte form IOTLB */
1170 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
1171 if (iotlb_entry) {
6c441e1d
PX		 1172 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
1173 iotlb_entry->domain_id);
b5a280c0 1174 slpte = iotlb_entry->slpte;
07f7b733 1175 access_flags = iotlb_entry->access_flags;
d66b969b 1176 page_mask = iotlb_entry->mask;
b5a280c0
LT		 1177 goto out;
1178 }
b9313021 1179
d92fa2dc
LT		 1180 /* Try to fetch context-entry from cache first */
1181 if (cc_entry->context_cache_gen == s->context_cache_gen) {
6c441e1d
PX		 1182 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
1183 cc_entry->context_entry.lo,
1184 cc_entry->context_cache_gen);
d92fa2dc
LT		 1185 ce = cc_entry->context_entry;
1186 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1187 } else {
1188 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
1189 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1190 if (ret_fr) {
1191 ret_fr = -ret_fr;
1192 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1193 trace_vtd_fault_disabled();
d92fa2dc
LT		 1194 } else {
1195 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1196 }
b9313021 1197 goto error;
1da12ec4 1198 }
d92fa2dc 1199 /* Update context-cache */
6c441e1d
PX		 1200 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
1201 cc_entry->context_cache_gen,
1202 s->context_cache_gen);
d92fa2dc
LT		 1203 cc_entry->context_entry = ce;
1204 cc_entry->context_cache_gen = s->context_cache_gen;
1da12ec4
LT		 1205 }
1206
dbaabb25
PX		 1207 /*
1208 * We don't need to translate for pass-through context entries.
1209 * Also, let's ignore IOTLB caching as well for PT devices.
1210 */
1211 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
892721d9 1212 entry->iova = addr & VTD_PAGE_MASK_4K;
dbaabb25 1213 entry->translated_addr = entry->iova;
892721d9 1214 entry->addr_mask = ~VTD_PAGE_MASK_4K;
dbaabb25
PX		 1215 entry->perm = IOMMU_RW;
1216 trace_vtd_translate_pt(source_id, entry->iova);
1217
1218 /*
1219 * When this happens, it means firstly caching-mode is not
1220 * enabled, and this is the first passthrough translation for
1221 * the device. Let's enable the fast path for passthrough.
1222 *
1223 * When passthrough is disabled again for the device, we can
1224 * capture it via the context entry invalidation, then the
1225 * IOMMU region can be swapped back.
1226 */
1227 vtd_pt_enable_fast_path(s, source_id);
1d9efa73 1228 vtd_iommu_unlock(s);
b9313021 1229 return true;
dbaabb25
PX		 1230 }
1231
6e905564 1232 ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
37f51384 1233 &reads, &writes, s->aw_bits);
1da12ec4
LT		 1234 if (ret_fr) {
1235 ret_fr = -ret_fr;
1236 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1237 trace_vtd_fault_disabled();
1da12ec4
LT		 1238 } else {
1239 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1240 }
b9313021 1241 goto error;
1da12ec4
LT		 1242 }
1243
d66b969b 1244 page_mask = vtd_slpt_level_page_mask(level);
07f7b733 1245 access_flags = IOMMU_ACCESS_FLAG(reads, writes);
b5a280c0 1246 vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
07f7b733 1247 access_flags, level);
b5a280c0 1248out:
1d9efa73 1249 vtd_iommu_unlock(s);
d66b969b 1250 entry->iova = addr & page_mask;
37f51384 1251 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
d66b969b 1252 entry->addr_mask = ~page_mask;
07f7b733 1253 entry->perm = access_flags;
b9313021
PX		 1254 return true;
1255
1256error:
1d9efa73 1257 vtd_iommu_unlock(s);
b9313021
PX		 1258 entry->iova = 0;
1259 entry->translated_addr = 0;
1260 entry->addr_mask = 0;
1261 entry->perm = IOMMU_NONE;
1262 return false;
1da12ec4
LT		 1263}
1264
1265static void vtd_root_table_setup(IntelIOMMUState *s)
1266{
1267 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
1268 s->root_extended = s->root & VTD_RTADDR_RTT;
37f51384 1269 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits);
1da12ec4 1270
7feb51b7 1271 trace_vtd_reg_dmar_root(s->root, s->root_extended);
1da12ec4
LT		 1272}
1273
02a2cbc8
PX		 1274static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
1275 uint32_t index, uint32_t mask)
1276{
1277 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
1278}
1279
a5861439
PX		 1280static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
1281{
1282 uint64_t value = 0;
1283 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
1284 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
37f51384 1285 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits);
28589311 1286 s->intr_eime = value & VTD_IRTA_EIME;
a5861439 1287
02a2cbc8
PX		 1288 /* Notify global invalidation */
1289 vtd_iec_notify_all(s, true, 0, 0);
a5861439 1290
7feb51b7 1291 trace_vtd_reg_ir_root(s->intr_root, s->intr_size);
a5861439
PX		 1292}
1293
dd4d607e
PX		 1294static void vtd_iommu_replay_all(IntelIOMMUState *s)
1295{
b4a4ba0d 1296 VTDAddressSpace *vtd_as;
dd4d607e 1297
b4a4ba0d
PX		 1298 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
1299 memory_region_iommu_replay_all(&vtd_as->iommu);
dd4d607e
PX		 1300 }
1301}
1302
d92fa2dc
LT		 1303static void vtd_context_global_invalidate(IntelIOMMUState *s)
1304{
bc535e59 1305 trace_vtd_inv_desc_cc_global();
1d9efa73
PX		 1306 /* Protects context cache */
1307 vtd_iommu_lock(s);
d92fa2dc
LT		 1308 s->context_cache_gen++;
1309 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
1d9efa73 1310 vtd_reset_context_cache_locked(s);
d92fa2dc 1311 }
1d9efa73 1312 vtd_iommu_unlock(s);
dbaabb25 1313 vtd_switch_address_space_all(s);
dd4d607e
PX		 1314 /*
1315 * From VT-d spec 6.5.2.1, a global context entry invalidation
1316 * should be followed by a IOTLB global invalidation, so we should
1317 * be safe even without this. Hoewever, let's replay the region as
1318 * well to be safer, and go back here when we need finer tunes for
1319 * VT-d emulation codes.
1320 */
1321 vtd_iommu_replay_all(s);
d92fa2dc
LT		 1322}
1323
1324/* Do a context-cache device-selective invalidation.
1325 * @func_mask: FM field after shifting
1326 */
1327static void vtd_context_device_invalidate(IntelIOMMUState *s,
1328 uint16_t source_id,
1329 uint16_t func_mask)
1330{
1331 uint16_t mask;
7df953bd 1332 VTDBus *vtd_bus;
d92fa2dc 1333 VTDAddressSpace *vtd_as;
bc535e59 1334 uint8_t bus_n, devfn;
d92fa2dc
LT		 1335 uint16_t devfn_it;
1336
bc535e59
PX		 1337 trace_vtd_inv_desc_cc_devices(source_id, func_mask);
1338
d92fa2dc
LT		 1339 switch (func_mask & 3) {
1340 case 0:
1341 mask = 0; /* No bits in the SID field masked */
1342 break;
1343 case 1:
1344 mask = 4; /* Mask bit 2 in the SID field */
1345 break;
1346 case 2:
1347 mask = 6; /* Mask bit 2:1 in the SID field */
1348 break;
1349 case 3:
1350 mask = 7; /* Mask bit 2:0 in the SID field */
1351 break;
1352 }
6cb99acc 1353 mask = ~mask;
bc535e59
PX		 1354
1355 bus_n = VTD_SID_TO_BUS(source_id);
1356 vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
7df953bd 1357 if (vtd_bus) {
d92fa2dc 1358 devfn = VTD_SID_TO_DEVFN(source_id);
bf33cc75 1359 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 1360 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc 1361 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
bc535e59
PX		 1362 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
1363 VTD_PCI_FUNC(devfn_it));
1d9efa73 1364 vtd_iommu_lock(s);
d92fa2dc 1365 vtd_as->context_cache_entry.context_cache_gen = 0;
1d9efa73 1366 vtd_iommu_unlock(s);
dbaabb25
PX		 1367 /*
1368 * Do switch address space when needed, in case if the
1369 * device passthrough bit is switched.
1370 */
1371 vtd_switch_address_space(vtd_as);
dd4d607e
PX		 1372 /*
1373 * So a device is moving out of (or moving into) a
1374 * domain, a replay() suites here to notify all the
1375 * IOMMU_NOTIFIER_MAP registers about this change.
1376 * This won't bring bad even if we have no such
1377 * notifier registered - the IOMMU notification
1378 * framework will skip MAP notifications if that
1379 * happened.
1380 */
1381 memory_region_iommu_replay_all(&vtd_as->iommu);
d92fa2dc
LT		 1382 }
1383 }
1384 }
1385}
1386
1da12ec4
LT		 1387/* Context-cache invalidation
1388 * Returns the Context Actual Invalidation Granularity.
1389 * @val: the content of the CCMD_REG
1390 */
1391static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1392{
1393 uint64_t caig;
1394 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1395
1396 switch (type) {
d92fa2dc 1397 case VTD_CCMD_DOMAIN_INVL:
d92fa2dc 1398 /* Fall through */
1da12ec4 1399 case VTD_CCMD_GLOBAL_INVL:
1da12ec4 1400 caig = VTD_CCMD_GLOBAL_INVL_A;
d92fa2dc 1401 vtd_context_global_invalidate(s);
1da12ec4
LT		 1402 break;
1403
1404 case VTD_CCMD_DEVICE_INVL:
1da12ec4 1405 caig = VTD_CCMD_DEVICE_INVL_A;
d92fa2dc 1406 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1da12ec4
LT		 1407 break;
1408
1409 default:
7feb51b7 1410 trace_vtd_err("Context cache invalidate type error.");
1da12ec4
LT		 1411 caig = 0;
1412 }
1413 return caig;
1414}
1415
b5a280c0
LT		 1416static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1417{
7feb51b7 1418 trace_vtd_inv_desc_iotlb_global();
b5a280c0 1419 vtd_reset_iotlb(s);
dd4d607e 1420 vtd_iommu_replay_all(s);
b5a280c0
LT		 1421}
1422
1423static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1424{
dd4d607e
PX		 1425 VTDContextEntry ce;
1426 VTDAddressSpace *vtd_as;
1427
7feb51b7
PX		 1428 trace_vtd_inv_desc_iotlb_domain(domain_id);
1429
1d9efa73 1430 vtd_iommu_lock(s);
b5a280c0
LT		 1431 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1432 &domain_id);
1d9efa73 1433 vtd_iommu_unlock(s);
dd4d607e 1434
b4a4ba0d 1435 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
dd4d607e
PX		 1436 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1437 vtd_as->devfn, &ce) &&
1438 domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1439 memory_region_iommu_replay_all(&vtd_as->iommu);
1440 }
1441 }
1442}
1443
1444static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry *entry,
1445 void *private)
1446{
3df9d748 1447 memory_region_notify_iommu((IOMMUMemoryRegion *)private, *entry);
dd4d607e
PX		 1448 return 0;
1449}
1450
1451static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
1452 uint16_t domain_id, hwaddr addr,
1453 uint8_t am)
1454{
b4a4ba0d 1455 VTDAddressSpace *vtd_as;
dd4d607e
PX		 1456 VTDContextEntry ce;
1457 int ret;
4f8a62a9 1458 hwaddr size = (1 << am) * VTD_PAGE_SIZE;
dd4d607e 1459
b4a4ba0d 1460 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) {
dd4d607e
PX		 1461 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1462 vtd_as->devfn, &ce);
1463 if (!ret && domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
4f8a62a9 1464 if (vtd_as_has_map_notifier(vtd_as)) {
fe215b0c
PX		 1465 vtd_page_walk_info info = {
1466 .hook_fn = vtd_page_invalidate_notify_hook,
1467 .private = (void *)&vtd_as->iommu,
1468 .notify_unmap = true,
1469 .aw = s->aw_bits,
2f764fa8 1470 .as = vtd_as,
d118c06e 1471 .domain_id = domain_id,
fe215b0c
PX		 1472 };
1473
4f8a62a9
PX		 1474 /*
1475 * As long as we have MAP notifications registered in
1476 * any of our IOMMU notifiers, we need to sync the
1477 * shadow page table.
1478 */
fe215b0c 1479 vtd_page_walk(&ce, addr, addr + size, &info);
4f8a62a9
PX		 1480 } else {
1481 /*
1482 * For UNMAP-only notifiers, we don't need to walk the
1483 * page tables. We just deliver the PSI down to
1484 * invalidate caches.
1485 */
1486 IOMMUTLBEntry entry = {
1487 .target_as = &address_space_memory,
1488 .iova = addr,
1489 .translated_addr = 0,
1490 .addr_mask = size - 1,
1491 .perm = IOMMU_NONE,
1492 };
1493 memory_region_notify_iommu(&vtd_as->iommu, entry);
1494 }
dd4d607e
PX		 1495 }
1496 }
b5a280c0
LT		 1497}
1498
1499static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1500 hwaddr addr, uint8_t am)
1501{
1502 VTDIOTLBPageInvInfo info;
1503
7feb51b7
PX		 1504 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
1505
b5a280c0
LT		 1506 assert(am <= VTD_MAMV);
1507 info.domain_id = domain_id;
d66b969b 1508 info.addr = addr;
b5a280c0 1509 info.mask = ~((1 << am) - 1);
1d9efa73 1510 vtd_iommu_lock(s);
b5a280c0 1511 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
1d9efa73 1512 vtd_iommu_unlock(s);
dd4d607e 1513 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);
b5a280c0
LT		 1514}
1515
1da12ec4
LT		 1516/* Flush IOTLB
1517 * Returns the IOTLB Actual Invalidation Granularity.
1518 * @val: the content of the IOTLB_REG
1519 */
1520static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1521{
1522 uint64_t iaig;
1523 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
b5a280c0
LT		 1524 uint16_t domain_id;
1525 hwaddr addr;
1526 uint8_t am;
1da12ec4
LT		 1527
1528 switch (type) {
1529 case VTD_TLB_GLOBAL_FLUSH:
1da12ec4 1530 iaig = VTD_TLB_GLOBAL_FLUSH_A;
b5a280c0 1531 vtd_iotlb_global_invalidate(s);
1da12ec4
LT		 1532 break;
1533
1534 case VTD_TLB_DSI_FLUSH:
b5a280c0 1535 domain_id = VTD_TLB_DID(val);
1da12ec4 1536 iaig = VTD_TLB_DSI_FLUSH_A;
b5a280c0 1537 vtd_iotlb_domain_invalidate(s, domain_id);
1da12ec4
LT		 1538 break;
1539
1540 case VTD_TLB_PSI_FLUSH:
b5a280c0
LT		 1541 domain_id = VTD_TLB_DID(val);
1542 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1543 am = VTD_IVA_AM(addr);
1544 addr = VTD_IVA_ADDR(addr);
b5a280c0 1545 if (am > VTD_MAMV) {
7feb51b7 1546 trace_vtd_err("IOTLB PSI flush: address mask overflow.");
b5a280c0
LT		 1547 iaig = 0;
1548 break;
1549 }
1da12ec4 1550 iaig = VTD_TLB_PSI_FLUSH_A;
b5a280c0 1551 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1da12ec4
LT		 1552 break;
1553
1554 default:
7feb51b7 1555 trace_vtd_err("IOTLB flush: invalid granularity.");
1da12ec4
LT		 1556 iaig = 0;
1557 }
1558 return iaig;
1559}
1560
8991c460 1561static void vtd_fetch_inv_desc(IntelIOMMUState *s);
ed7b8fbc
LT		 1562
1563static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1564{
1565 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1566 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1567}
1568
1569static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1570{
1571 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1572
7feb51b7
PX		 1573 trace_vtd_inv_qi_enable(en);
1574
ed7b8fbc 1575 if (en) {
37f51384 1576 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits);
8991c460
LP		 1577 /* 2^(x+8) entries */
1578 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1579 s->qi_enabled = true;
1580 trace_vtd_inv_qi_setup(s->iq, s->iq_size);
1581 /* Ok - report back to driver */
1582 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1583
1584 if (s->iq_tail != 0) {
1585 /*
1586 * This is a spec violation but Windows guests are known to set up
1587 * Queued Invalidation this way so we allow the write and process
1588 * Invalidation Descriptors right away.
1589 */
1590 trace_vtd_warn_invalid_qi_tail(s->iq_tail);
1591 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1592 vtd_fetch_inv_desc(s);
1593 }
ed7b8fbc
LT		 1594 }
1595 } else {
1596 if (vtd_queued_inv_disable_check(s)) {
1597 /* disable Queued Invalidation */
1598 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1599 s->iq_head = 0;
1600 s->qi_enabled = false;
1601 /* Ok - report back to driver */
1602 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1603 } else {
7feb51b7 1604 trace_vtd_err_qi_disable(s->iq_head, s->iq_tail, s->iq_last_desc_type);
ed7b8fbc
LT		 1605 }
1606 }
1607}
1608
1da12ec4
LT		 1609/* Set Root Table Pointer */
1610static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1611{
1da12ec4
LT		 1612 vtd_root_table_setup(s);
1613 /* Ok - report back to driver */
1614 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1615}
1616
a5861439
PX		 1617/* Set Interrupt Remap Table Pointer */
1618static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1619{
a5861439
PX		 1620 vtd_interrupt_remap_table_setup(s);
1621 /* Ok - report back to driver */
1622 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1623}
1624
1da12ec4
LT		 1625/* Handle Translation Enable/Disable */
1626static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1627{
558e0024
PX		 1628 if (s->dmar_enabled == en) {
1629 return;
1630 }
1631
7feb51b7 1632 trace_vtd_dmar_enable(en);
1da12ec4
LT		 1633
1634 if (en) {
1635 s->dmar_enabled = true;
1636 /* Ok - report back to driver */
1637 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1638 } else {
1639 s->dmar_enabled = false;
1640
1641 /* Clear the index of Fault Recording Register */
1642 s->next_frcd_reg = 0;
1643 /* Ok - report back to driver */
1644 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1645 }
558e0024
PX		 1646
1647 vtd_switch_address_space_all(s);
1da12ec4
LT		 1648}
1649
80de52ba
PX		 1650/* Handle Interrupt Remap Enable/Disable */
1651static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1652{
7feb51b7 1653 trace_vtd_ir_enable(en);
80de52ba
PX		 1654
1655 if (en) {
1656 s->intr_enabled = true;
1657 /* Ok - report back to driver */
1658 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1659 } else {
1660 s->intr_enabled = false;
1661 /* Ok - report back to driver */
1662 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1663 }
1664}
1665
1da12ec4
LT		 1666/* Handle write to Global Command Register */
1667static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1668{
1669 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1670 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1671 uint32_t changed = status ^ val;
1672
7feb51b7 1673 trace_vtd_reg_write_gcmd(status, val);
1da12ec4
LT		 1674 if (changed & VTD_GCMD_TE) {
1675 /* Translation enable/disable */
1676 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1677 }
1678 if (val & VTD_GCMD_SRTP) {
1679 /* Set/update the root-table pointer */
1680 vtd_handle_gcmd_srtp(s);
1681 }
ed7b8fbc
LT		 1682 if (changed & VTD_GCMD_QIE) {
1683 /* Queued Invalidation Enable */
1684 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1685 }
a5861439
PX		 1686 if (val & VTD_GCMD_SIRTP) {
1687 /* Set/update the interrupt remapping root-table pointer */
1688 vtd_handle_gcmd_sirtp(s);
1689 }
80de52ba
PX		 1690 if (changed & VTD_GCMD_IRE) {
1691 /* Interrupt remap enable/disable */
1692 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1693 }
1da12ec4
LT		 1694}
1695
1696/* Handle write to Context Command Register */
1697static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1698{
1699 uint64_t ret;
1700 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1701
1702 /* Context-cache invalidation request */
1703 if (val & VTD_CCMD_ICC) {
ed7b8fbc 1704 if (s->qi_enabled) {
7feb51b7
PX		 1705 trace_vtd_err("Queued Invalidation enabled, "
1706 "should not use register-based invalidation");
ed7b8fbc
LT		 1707 return;
1708 }
1da12ec4
LT		 1709 ret = vtd_context_cache_invalidate(s, val);
1710 /* Invalidation completed. Change something to show */
1711 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1712 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1713 ret);
1da12ec4
LT		 1714 }
1715}
1716
1717/* Handle write to IOTLB Invalidation Register */
1718static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1719{
1720 uint64_t ret;
1721 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1722
1723 /* IOTLB invalidation request */
1724 if (val & VTD_TLB_IVT) {
ed7b8fbc 1725 if (s->qi_enabled) {
7feb51b7
PX		 1726 trace_vtd_err("Queued Invalidation enabled, "
1727 "should not use register-based invalidation.");
ed7b8fbc
LT		 1728 return;
1729 }
1da12ec4
LT		 1730 ret = vtd_iotlb_flush(s, val);
1731 /* Invalidation completed. Change something to show */
1732 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1733 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1734 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1da12ec4
LT		 1735 }
1736}
1737
ed7b8fbc
LT		 1738/* Fetch an Invalidation Descriptor from the Invalidation Queue */
1739static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1740 VTDInvDesc *inv_desc)
1741{
1742 dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1743 if (dma_memory_read(&address_space_memory, addr, inv_desc,
1744 sizeof(*inv_desc))) {
7feb51b7 1745 trace_vtd_err("Read INV DESC failed.");
ed7b8fbc
LT		 1746 inv_desc->lo = 0;
1747 inv_desc->hi = 0;
ed7b8fbc
LT		 1748 return false;
1749 }
1750 inv_desc->lo = le64_to_cpu(inv_desc->lo);
1751 inv_desc->hi = le64_to_cpu(inv_desc->hi);
1752 return true;
1753}
1754
1755static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1756{
1757 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1758 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
bc535e59 1759 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1760 return false;
1761 }
1762 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1763 /* Status Write */
1764 uint32_t status_data = (uint32_t)(inv_desc->lo >>
1765 VTD_INV_DESC_WAIT_DATA_SHIFT);
1766
1767 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1768
1769 /* FIXME: need to be masked with HAW? */
1770 dma_addr_t status_addr = inv_desc->hi;
bc535e59 1771 trace_vtd_inv_desc_wait_sw(status_addr, status_data);
ed7b8fbc
LT		 1772 status_data = cpu_to_le32(status_data);
1773 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1774 sizeof(status_data))) {
bc535e59 1775 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1776 return false;
1777 }
1778 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1779 /* Interrupt flag */
ed7b8fbc
LT		 1780 vtd_generate_completion_event(s);
1781 } else {
bc535e59 1782 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1783 return false;
1784 }
1785 return true;
1786}
1787
d92fa2dc
LT		 1788static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1789 VTDInvDesc *inv_desc)
1790{
bc535e59
PX		 1791 uint16_t sid, fmask;
1792
d92fa2dc 1793 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
bc535e59 1794 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1795 return false;
1796 }
1797 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1798 case VTD_INV_DESC_CC_DOMAIN:
bc535e59
PX		 1799 trace_vtd_inv_desc_cc_domain(
1800 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
d92fa2dc
LT		 1801 /* Fall through */
1802 case VTD_INV_DESC_CC_GLOBAL:
d92fa2dc
LT		 1803 vtd_context_global_invalidate(s);
1804 break;
1805
1806 case VTD_INV_DESC_CC_DEVICE:
bc535e59
PX		 1807 sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
1808 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
1809 vtd_context_device_invalidate(s, sid, fmask);
d92fa2dc
LT		 1810 break;
1811
1812 default:
bc535e59 1813 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1814 return false;
1815 }
1816 return true;
1817}
1818
b5a280c0
LT		 1819static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1820{
1821 uint16_t domain_id;
1822 uint8_t am;
1823 hwaddr addr;
1824
1825 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1826 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
bc535e59 1827 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1828 return false;
1829 }
1830
1831 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1832 case VTD_INV_DESC_IOTLB_GLOBAL:
b5a280c0
LT		 1833 vtd_iotlb_global_invalidate(s);
1834 break;
1835
1836 case VTD_INV_DESC_IOTLB_DOMAIN:
1837 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
b5a280c0
LT		 1838 vtd_iotlb_domain_invalidate(s, domain_id);
1839 break;
1840
1841 case VTD_INV_DESC_IOTLB_PAGE:
1842 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1843 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1844 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
b5a280c0 1845 if (am > VTD_MAMV) {
bc535e59 1846 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1847 return false;
1848 }
1849 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1850 break;
1851
1852 default:
bc535e59 1853 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1854 return false;
1855 }
1856 return true;
1857}
1858
02a2cbc8
PX		 1859static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
1860 VTDInvDesc *inv_desc)
1861{
7feb51b7
PX		 1862 trace_vtd_inv_desc_iec(inv_desc->iec.granularity,
1863 inv_desc->iec.index,
1864 inv_desc->iec.index_mask);
02a2cbc8
PX		 1865
1866 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
1867 inv_desc->iec.index,
1868 inv_desc->iec.index_mask);
554f5e16
JW		 1869 return true;
1870}
1871
1872static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
1873 VTDInvDesc *inv_desc)
1874{
1875 VTDAddressSpace *vtd_dev_as;
1876 IOMMUTLBEntry entry;
1877 struct VTDBus *vtd_bus;
1878 hwaddr addr;
1879 uint64_t sz;
1880 uint16_t sid;
1881 uint8_t devfn;
1882 bool size;
1883 uint8_t bus_num;
1884
1885 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
1886 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
1887 devfn = sid & 0xff;
1888 bus_num = sid >> 8;
1889 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
1890
1891 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
1892 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
7feb51b7 1893 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
554f5e16
JW		 1894 return false;
1895 }
1896
1897 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
1898 if (!vtd_bus) {
1899 goto done;
1900 }
1901
1902 vtd_dev_as = vtd_bus->dev_as[devfn];
1903 if (!vtd_dev_as) {
1904 goto done;
1905 }
1906
04eb6247
JW		 1907 /* According to ATS spec table 2.4:
1908 * S = 0, bits 15:12 = xxxx range size: 4K
1909 * S = 1, bits 15:12 = xxx0 range size: 8K
1910 * S = 1, bits 15:12 = xx01 range size: 16K
1911 * S = 1, bits 15:12 = x011 range size: 32K
1912 * S = 1, bits 15:12 = 0111 range size: 64K
1913 * ...
1914 */
554f5e16 1915 if (size) {
04eb6247 1916 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
554f5e16
JW		 1917 addr &= ~(sz - 1);
1918 } else {
1919 sz = VTD_PAGE_SIZE;
1920 }
02a2cbc8 1921
554f5e16
JW		 1922 entry.target_as = &vtd_dev_as->as;
1923 entry.addr_mask = sz - 1;
1924 entry.iova = addr;
1925 entry.perm = IOMMU_NONE;
1926 entry.translated_addr = 0;
10315b9b 1927 memory_region_notify_iommu(&vtd_dev_as->iommu, entry);
554f5e16
JW		 1928
1929done:
02a2cbc8
PX		 1930 return true;
1931}
1932
ed7b8fbc
LT		 1933static bool vtd_process_inv_desc(IntelIOMMUState *s)
1934{
1935 VTDInvDesc inv_desc;
1936 uint8_t desc_type;
1937
7feb51b7 1938 trace_vtd_inv_qi_head(s->iq_head);
ed7b8fbc
LT		 1939 if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1940 s->iq_last_desc_type = VTD_INV_DESC_NONE;
1941 return false;
1942 }
1943 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1944 /* FIXME: should update at first or at last? */
1945 s->iq_last_desc_type = desc_type;
1946
1947 switch (desc_type) {
1948 case VTD_INV_DESC_CC:
bc535e59 1949 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
d92fa2dc
LT		 1950 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1951 return false;
1952 }
ed7b8fbc
LT		 1953 break;
1954
1955 case VTD_INV_DESC_IOTLB:
bc535e59 1956 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
b5a280c0
LT		 1957 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1958 return false;
1959 }
ed7b8fbc
LT		 1960 break;
1961
1962 case VTD_INV_DESC_WAIT:
bc535e59 1963 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1964 if (!vtd_process_wait_desc(s, &inv_desc)) {
1965 return false;
1966 }
1967 break;
1968
b7910472 1969 case VTD_INV_DESC_IEC:
bc535e59 1970 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
02a2cbc8
PX		 1971 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
1972 return false;
1973 }
b7910472
PX		 1974 break;
1975
554f5e16 1976 case VTD_INV_DESC_DEVICE:
7feb51b7 1977 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
554f5e16
JW		 1978 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
1979 return false;
1980 }
1981 break;
1982
ed7b8fbc 1983 default:
bc535e59 1984 trace_vtd_inv_desc_invalid(inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1985 return false;
1986 }
1987 s->iq_head++;
1988 if (s->iq_head == s->iq_size) {
1989 s->iq_head = 0;
1990 }
1991 return true;
1992}
1993
1994/* Try to fetch and process more Invalidation Descriptors */
1995static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1996{
7feb51b7
PX		 1997 trace_vtd_inv_qi_fetch();
1998
ed7b8fbc
LT		 1999 if (s->iq_tail >= s->iq_size) {
2000 /* Detects an invalid Tail pointer */
7feb51b7 2001 trace_vtd_err_qi_tail(s->iq_tail, s->iq_size);
ed7b8fbc
LT		 2002 vtd_handle_inv_queue_error(s);
2003 return;
2004 }
2005 while (s->iq_head != s->iq_tail) {
2006 if (!vtd_process_inv_desc(s)) {
2007 /* Invalidation Queue Errors */
2008 vtd_handle_inv_queue_error(s);
2009 break;
2010 }
2011 /* Must update the IQH_REG in time */
2012 vtd_set_quad_raw(s, DMAR_IQH_REG,
2013 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
2014 VTD_IQH_QH_MASK);
2015 }
2016}
2017
2018/* Handle write to Invalidation Queue Tail Register */
2019static void vtd_handle_iqt_write(IntelIOMMUState *s)
2020{
2021 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
2022
2023 s->iq_tail = VTD_IQT_QT(val);
7feb51b7
PX		 2024 trace_vtd_inv_qi_tail(s->iq_tail);
2025
ed7b8fbc
LT		 2026 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
2027 /* Process Invalidation Queue here */
2028 vtd_fetch_inv_desc(s);
2029 }
2030}
2031
1da12ec4
LT		 2032static void vtd_handle_fsts_write(IntelIOMMUState *s)
2033{
2034 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
2035 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
2036 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
2037
2038 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
2039 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
7feb51b7 2040 trace_vtd_fsts_clear_ip();
1da12ec4 2041 }
ed7b8fbc
LT		 2042 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
2043 * Descriptors if there are any when Queued Invalidation is enabled?
2044 */
1da12ec4
LT		 2045}
2046
2047static void vtd_handle_fectl_write(IntelIOMMUState *s)
2048{
2049 uint32_t fectl_reg;
2050 /* FIXME: when software clears the IM field, check the IP field. But do we
2051 * need to compare the old value and the new value to conclude that
2052 * software clears the IM field? Or just check if the IM field is zero?
2053 */
2054 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
7feb51b7
PX		 2055
2056 trace_vtd_reg_write_fectl(fectl_reg);
2057
1da12ec4
LT		 2058 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
2059 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
2060 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1da12ec4
LT		 2061 }
2062}
2063
ed7b8fbc
LT		 2064static void vtd_handle_ics_write(IntelIOMMUState *s)
2065{
2066 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
2067 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
2068
2069 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
7feb51b7 2070 trace_vtd_reg_ics_clear_ip();
ed7b8fbc 2071 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
ed7b8fbc
LT		 2072 }
2073}
2074
2075static void vtd_handle_iectl_write(IntelIOMMUState *s)
2076{
2077 uint32_t iectl_reg;
2078 /* FIXME: when software clears the IM field, check the IP field. But do we
2079 * need to compare the old value and the new value to conclude that
2080 * software clears the IM field? Or just check if the IM field is zero?
2081 */
2082 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
7feb51b7
PX		 2083
2084 trace_vtd_reg_write_iectl(iectl_reg);
2085
ed7b8fbc
LT		 2086 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
2087 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
2088 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
ed7b8fbc
LT		 2089 }
2090}
2091
1da12ec4
LT		 2092static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
2093{
2094 IntelIOMMUState *s = opaque;
2095 uint64_t val;
2096
7feb51b7
PX		 2097 trace_vtd_reg_read(addr, size);
2098
1da12ec4 2099 if (addr + size > DMAR_REG_SIZE) {
7feb51b7 2100 trace_vtd_err("Read MMIO over range.");
1da12ec4
LT		 2101 return (uint64_t)-1;
2102 }
2103
2104 switch (addr) {
2105 /* Root Table Address Register, 64-bit */
2106 case DMAR_RTADDR_REG:
2107 if (size == 4) {
2108 val = s->root & ((1ULL << 32) - 1);
2109 } else {
2110 val = s->root;
2111 }
2112 break;
2113
2114 case DMAR_RTADDR_REG_HI:
2115 assert(size == 4);
2116 val = s->root >> 32;
2117 break;
2118
ed7b8fbc
LT		 2119 /* Invalidation Queue Address Register, 64-bit */
2120 case DMAR_IQA_REG:
2121 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
2122 if (size == 4) {
2123 val = val & ((1ULL << 32) - 1);
2124 }
2125 break;
2126
2127 case DMAR_IQA_REG_HI:
2128 assert(size == 4);
2129 val = s->iq >> 32;
2130 break;
2131
1da12ec4
LT		 2132 default:
2133 if (size == 4) {
2134 val = vtd_get_long(s, addr);
2135 } else {
2136 val = vtd_get_quad(s, addr);
2137 }
2138 }
7feb51b7 2139
1da12ec4
LT		 2140 return val;
2141}
2142
2143static void vtd_mem_write(void *opaque, hwaddr addr,
2144 uint64_t val, unsigned size)
2145{
2146 IntelIOMMUState *s = opaque;
2147
7feb51b7
PX		 2148 trace_vtd_reg_write(addr, size, val);
2149
1da12ec4 2150 if (addr + size > DMAR_REG_SIZE) {
7feb51b7 2151 trace_vtd_err("Write MMIO over range.");
1da12ec4
LT		 2152 return;
2153 }
2154
2155 switch (addr) {
2156 /* Global Command Register, 32-bit */
2157 case DMAR_GCMD_REG:
1da12ec4
LT		 2158 vtd_set_long(s, addr, val);
2159 vtd_handle_gcmd_write(s);
2160 break;
2161
2162 /* Context Command Register, 64-bit */
2163 case DMAR_CCMD_REG:
1da12ec4
LT		 2164 if (size == 4) {
2165 vtd_set_long(s, addr, val);
2166 } else {
2167 vtd_set_quad(s, addr, val);
2168 vtd_handle_ccmd_write(s);
2169 }
2170 break;
2171
2172 case DMAR_CCMD_REG_HI:
1da12ec4
LT		 2173 assert(size == 4);
2174 vtd_set_long(s, addr, val);
2175 vtd_handle_ccmd_write(s);
2176 break;
2177
2178 /* IOTLB Invalidation Register, 64-bit */
2179 case DMAR_IOTLB_REG:
1da12ec4
LT		 2180 if (size == 4) {
2181 vtd_set_long(s, addr, val);
2182 } else {
2183 vtd_set_quad(s, addr, val);
2184 vtd_handle_iotlb_write(s);
2185 }
2186 break;
2187
2188 case DMAR_IOTLB_REG_HI:
1da12ec4
LT		 2189 assert(size == 4);
2190 vtd_set_long(s, addr, val);
2191 vtd_handle_iotlb_write(s);
2192 break;
2193
b5a280c0
LT		 2194 /* Invalidate Address Register, 64-bit */
2195 case DMAR_IVA_REG:
b5a280c0
LT		 2196 if (size == 4) {
2197 vtd_set_long(s, addr, val);
2198 } else {
2199 vtd_set_quad(s, addr, val);
2200 }
2201 break;
2202
2203 case DMAR_IVA_REG_HI:
b5a280c0
LT		 2204 assert(size == 4);
2205 vtd_set_long(s, addr, val);
2206 break;
2207
1da12ec4
LT		 2208 /* Fault Status Register, 32-bit */
2209 case DMAR_FSTS_REG:
1da12ec4
LT		 2210 assert(size == 4);
2211 vtd_set_long(s, addr, val);
2212 vtd_handle_fsts_write(s);
2213 break;
2214
2215 /* Fault Event Control Register, 32-bit */
2216 case DMAR_FECTL_REG:
1da12ec4
LT		 2217 assert(size == 4);
2218 vtd_set_long(s, addr, val);
2219 vtd_handle_fectl_write(s);
2220 break;
2221
2222 /* Fault Event Data Register, 32-bit */
2223 case DMAR_FEDATA_REG:
1da12ec4
LT		 2224 assert(size == 4);
2225 vtd_set_long(s, addr, val);
2226 break;
2227
2228 /* Fault Event Address Register, 32-bit */
2229 case DMAR_FEADDR_REG:
b7a7bb35
JK		 2230 if (size == 4) {
2231 vtd_set_long(s, addr, val);
2232 } else {
2233 /*
2234 * While the register is 32-bit only, some guests (Xen...) write to
2235 * it with 64-bit.
2236 */
2237 vtd_set_quad(s, addr, val);
2238 }
1da12ec4
LT		 2239 break;
2240
2241 /* Fault Event Upper Address Register, 32-bit */
2242 case DMAR_FEUADDR_REG:
1da12ec4
LT		 2243 assert(size == 4);
2244 vtd_set_long(s, addr, val);
2245 break;
2246
2247 /* Protected Memory Enable Register, 32-bit */
2248 case DMAR_PMEN_REG:
1da12ec4
LT		 2249 assert(size == 4);
2250 vtd_set_long(s, addr, val);
2251 break;
2252
2253 /* Root Table Address Register, 64-bit */
2254 case DMAR_RTADDR_REG:
1da12ec4
LT		 2255 if (size == 4) {
2256 vtd_set_long(s, addr, val);
2257 } else {
2258 vtd_set_quad(s, addr, val);
2259 }
2260 break;
2261
2262 case DMAR_RTADDR_REG_HI:
1da12ec4
LT		 2263 assert(size == 4);
2264 vtd_set_long(s, addr, val);
2265 break;
2266
ed7b8fbc
LT		 2267 /* Invalidation Queue Tail Register, 64-bit */
2268 case DMAR_IQT_REG:
ed7b8fbc
LT		 2269 if (size == 4) {
2270 vtd_set_long(s, addr, val);
2271 } else {
2272 vtd_set_quad(s, addr, val);
2273 }
2274 vtd_handle_iqt_write(s);
2275 break;
2276
2277 case DMAR_IQT_REG_HI:
ed7b8fbc
LT		 2278 assert(size == 4);
2279 vtd_set_long(s, addr, val);
2280 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2281 break;
2282
2283 /* Invalidation Queue Address Register, 64-bit */
2284 case DMAR_IQA_REG:
ed7b8fbc
LT		 2285 if (size == 4) {
2286 vtd_set_long(s, addr, val);
2287 } else {
2288 vtd_set_quad(s, addr, val);
2289 }
2290 break;
2291
2292 case DMAR_IQA_REG_HI:
ed7b8fbc
LT		 2293 assert(size == 4);
2294 vtd_set_long(s, addr, val);
2295 break;
2296
2297 /* Invalidation Completion Status Register, 32-bit */
2298 case DMAR_ICS_REG:
ed7b8fbc
LT		 2299 assert(size == 4);
2300 vtd_set_long(s, addr, val);
2301 vtd_handle_ics_write(s);
2302 break;
2303
2304 /* Invalidation Event Control Register, 32-bit */
2305 case DMAR_IECTL_REG:
ed7b8fbc
LT		 2306 assert(size == 4);
2307 vtd_set_long(s, addr, val);
2308 vtd_handle_iectl_write(s);
2309 break;
2310
2311 /* Invalidation Event Data Register, 32-bit */
2312 case DMAR_IEDATA_REG:
ed7b8fbc
LT		 2313 assert(size == 4);
2314 vtd_set_long(s, addr, val);
2315 break;
2316
2317 /* Invalidation Event Address Register, 32-bit */
2318 case DMAR_IEADDR_REG:
ed7b8fbc
LT		 2319 assert(size == 4);
2320 vtd_set_long(s, addr, val);
2321 break;
2322
2323 /* Invalidation Event Upper Address Register, 32-bit */
2324 case DMAR_IEUADDR_REG:
ed7b8fbc
LT		 2325 assert(size == 4);
2326 vtd_set_long(s, addr, val);
2327 break;
2328
1da12ec4
LT		 2329 /* Fault Recording Registers, 128-bit */
2330 case DMAR_FRCD_REG_0_0:
1da12ec4
LT		 2331 if (size == 4) {
2332 vtd_set_long(s, addr, val);
2333 } else {
2334 vtd_set_quad(s, addr, val);
2335 }
2336 break;
2337
2338 case DMAR_FRCD_REG_0_1:
1da12ec4
LT		 2339 assert(size == 4);
2340 vtd_set_long(s, addr, val);
2341 break;
2342
2343 case DMAR_FRCD_REG_0_2:
1da12ec4
LT		 2344 if (size == 4) {
2345 vtd_set_long(s, addr, val);
2346 } else {
2347 vtd_set_quad(s, addr, val);
2348 /* May clear bit 127 (Fault), update PPF */
2349 vtd_update_fsts_ppf(s);
2350 }
2351 break;
2352
2353 case DMAR_FRCD_REG_0_3:
1da12ec4
LT		 2354 assert(size == 4);
2355 vtd_set_long(s, addr, val);
2356 /* May clear bit 127 (Fault), update PPF */
2357 vtd_update_fsts_ppf(s);
2358 break;
2359
a5861439 2360 case DMAR_IRTA_REG:
a5861439
PX		 2361 if (size == 4) {
2362 vtd_set_long(s, addr, val);
2363 } else {
2364 vtd_set_quad(s, addr, val);
2365 }
2366 break;
2367
2368 case DMAR_IRTA_REG_HI:
a5861439
PX		 2369 assert(size == 4);
2370 vtd_set_long(s, addr, val);
2371 break;
2372
1da12ec4 2373 default:
1da12ec4
LT		 2374 if (size == 4) {
2375 vtd_set_long(s, addr, val);
2376 } else {
2377 vtd_set_quad(s, addr, val);
2378 }
2379 }
2380}
2381
3df9d748 2382static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
bf55b7af 2383 IOMMUAccessFlags flag)
1da12ec4
LT		 2384{
2385 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2386 IntelIOMMUState *s = vtd_as->iommu_state;
b9313021
PX		 2387 IOMMUTLBEntry iotlb = {
2388 /* We'll fill in the rest later. */
1da12ec4 2389 .target_as = &address_space_memory,
1da12ec4 2390 };
b9313021 2391 bool success;
1da12ec4 2392
b9313021
PX		 2393 if (likely(s->dmar_enabled)) {
2394 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn,
2395 addr, flag & IOMMU_WO, &iotlb);
2396 } else {
1da12ec4 2397 /* DMAR disabled, passthrough, use 4k-page*/
b9313021
PX		 2398 iotlb.iova = addr & VTD_PAGE_MASK_4K;
2399 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K;
2400 iotlb.addr_mask = ~VTD_PAGE_MASK_4K;
2401 iotlb.perm = IOMMU_RW;
2402 success = true;
1da12ec4
LT		 2403 }
2404
b9313021
PX		 2405 if (likely(success)) {
2406 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
2407 VTD_PCI_SLOT(vtd_as->devfn),
2408 VTD_PCI_FUNC(vtd_as->devfn),
2409 iotlb.iova, iotlb.translated_addr,
2410 iotlb.addr_mask);
2411 } else {
2412 trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus),
2413 VTD_PCI_SLOT(vtd_as->devfn),
2414 VTD_PCI_FUNC(vtd_as->devfn),
2415 iotlb.iova);
2416 }
7feb51b7 2417
b9313021 2418 return iotlb;
1da12ec4
LT		 2419}
2420
3df9d748 2421static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu,
5bf3d319
PX		 2422 IOMMUNotifierFlag old,
2423 IOMMUNotifierFlag new)
3cb3b154
AW		 2424{
2425 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
dd4d607e 2426 IntelIOMMUState *s = vtd_as->iommu_state;
3cb3b154 2427
dd4d607e 2428 if (!s->caching_mode && new & IOMMU_NOTIFIER_MAP) {
4c427a4c 2429 error_report("We need to set caching-mode=1 for intel-iommu to enable "
dd4d607e 2430 "device assignment with IOMMU protection.");
a3276f78
PX		 2431 exit(1);
2432 }
dd4d607e 2433
4f8a62a9
PX		 2434 /* Update per-address-space notifier flags */
2435 vtd_as->notifier_flags = new;
2436
dd4d607e 2437 if (old == IOMMU_NOTIFIER_NONE) {
b4a4ba0d
PX		 2438 QLIST_INSERT_HEAD(&s->vtd_as_with_notifiers, vtd_as, next);
2439 } else if (new == IOMMU_NOTIFIER_NONE) {
2440 QLIST_REMOVE(vtd_as, next);
dd4d607e 2441 }
3cb3b154
AW		 2442}
2443
552a1e01
PX		 2444static int vtd_post_load(void *opaque, int version_id)
2445{
2446 IntelIOMMUState *iommu = opaque;
2447
2448 /*
2449 * Memory regions are dynamically turned on/off depending on
2450 * context entry configurations from the guest. After migration,
2451 * we need to make sure the memory regions are still correct.
2452 */
2453 vtd_switch_address_space_all(iommu);
2454
2455 return 0;
2456}
2457
1da12ec4
LT		 2458static const VMStateDescription vtd_vmstate = {
2459 .name = "iommu-intel",
8cdcf3c1
PX		 2460 .version_id = 1,
2461 .minimum_version_id = 1,
2462 .priority = MIG_PRI_IOMMU,
552a1e01 2463 .post_load = vtd_post_load,
8cdcf3c1
PX		 2464 .fields = (VMStateField[]) {
2465 VMSTATE_UINT64(root, IntelIOMMUState),
2466 VMSTATE_UINT64(intr_root, IntelIOMMUState),
2467 VMSTATE_UINT64(iq, IntelIOMMUState),
2468 VMSTATE_UINT32(intr_size, IntelIOMMUState),
2469 VMSTATE_UINT16(iq_head, IntelIOMMUState),
2470 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
2471 VMSTATE_UINT16(iq_size, IntelIOMMUState),
2472 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
2473 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
2474 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
2475 VMSTATE_BOOL(root_extended, IntelIOMMUState),
2476 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
2477 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
2478 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
2479 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
2480 VMSTATE_END_OF_LIST()
2481 }
1da12ec4
LT		 2482};
2483
2484static const MemoryRegionOps vtd_mem_ops = {
2485 .read = vtd_mem_read,
2486 .write = vtd_mem_write,
2487 .endianness = DEVICE_LITTLE_ENDIAN,
2488 .impl = {
2489 .min_access_size = 4,
2490 .max_access_size = 8,
2491 },
2492 .valid = {
2493 .min_access_size = 4,
2494 .max_access_size = 8,
2495 },
2496};
2497
2498static Property vtd_properties[] = {
2499 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
e6b6af05
RK		 2500 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
2501 ON_OFF_AUTO_AUTO),
fb506e70 2502 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
37f51384
PS		 2503 DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState, aw_bits,
2504 VTD_HOST_ADDRESS_WIDTH),
3b40f0e5 2505 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
1da12ec4
LT		 2506 DEFINE_PROP_END_OF_LIST(),
2507};
2508
651e4cef
PX		 2509/* Read IRTE entry with specific index */
2510static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
bc38ee10 2511 VTD_IR_TableEntry *entry, uint16_t sid)
651e4cef 2512{
ede9c94a
PX		 2513 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
2514 {0xffff, 0xfffb, 0xfff9, 0xfff8};
651e4cef 2515 dma_addr_t addr = 0x00;
ede9c94a
PX		 2516 uint16_t mask, source_id;
2517 uint8_t bus, bus_max, bus_min;
651e4cef
PX		 2518
2519 addr = iommu->intr_root + index * sizeof(*entry);
2520 if (dma_memory_read(&address_space_memory, addr, entry,
2521 sizeof(*entry))) {
7feb51b7 2522 trace_vtd_err("Memory read failed for IRTE.");
651e4cef
PX		 2523 return -VTD_FR_IR_ROOT_INVAL;
2524 }
2525
7feb51b7
PX		 2526 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]),
2527 le64_to_cpu(entry->data[0]));
2528
bc38ee10 2529 if (!entry->irte.present) {
7feb51b7
PX		 2530 trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
2531 le64_to_cpu(entry->data[0]));
651e4cef
PX		 2532 return -VTD_FR_IR_ENTRY_P;
2533 }
2534
bc38ee10
MT		 2535 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
2536 entry->irte.__reserved_2) {
7feb51b7
PX		 2537 trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
2538 le64_to_cpu(entry->data[0]));
651e4cef
PX		 2539 return -VTD_FR_IR_IRTE_RSVD;
2540 }
2541
ede9c94a
PX		 2542 if (sid != X86_IOMMU_SID_INVALID) {
2543 /* Validate IRTE SID */
bc38ee10
MT		 2544 source_id = le32_to_cpu(entry->irte.source_id);
2545 switch (entry->irte.sid_vtype) {
ede9c94a 2546 case VTD_SVT_NONE:
ede9c94a
PX		 2547 break;
2548
2549 case VTD_SVT_ALL:
bc38ee10 2550 mask = vtd_svt_mask[entry->irte.sid_q];
ede9c94a 2551 if ((source_id & mask) != (sid & mask)) {
7feb51b7 2552 trace_vtd_err_irte_sid(index, sid, source_id);
ede9c94a
PX		 2553 return -VTD_FR_IR_SID_ERR;
2554 }
2555 break;
2556
2557 case VTD_SVT_BUS:
2558 bus_max = source_id >> 8;
2559 bus_min = source_id & 0xff;
2560 bus = sid >> 8;
2561 if (bus > bus_max || bus < bus_min) {
7feb51b7 2562 trace_vtd_err_irte_sid_bus(index, bus, bus_min, bus_max);
ede9c94a
PX		 2563 return -VTD_FR_IR_SID_ERR;
2564 }
2565 break;
2566
2567 default:
7feb51b7 2568 trace_vtd_err_irte_svt(index, entry->irte.sid_vtype);
ede9c94a
PX		 2569 /* Take this as verification failure. */
2570 return -VTD_FR_IR_SID_ERR;
2571 break;
2572 }
2573 }
651e4cef
PX		 2574
2575 return 0;
2576}
2577
2578/* Fetch IRQ information of specific IR index */
ede9c94a
PX		 2579static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
2580 VTDIrq *irq, uint16_t sid)
651e4cef 2581{
bc38ee10 2582 VTD_IR_TableEntry irte = {};
651e4cef
PX		 2583 int ret = 0;
2584
ede9c94a 2585 ret = vtd_irte_get(iommu, index, &irte, sid);
651e4cef
PX		 2586 if (ret) {
2587 return ret;
2588 }
2589
bc38ee10
MT		 2590 irq->trigger_mode = irte.irte.trigger_mode;
2591 irq->vector = irte.irte.vector;
2592 irq->delivery_mode = irte.irte.delivery_mode;
2593 irq->dest = le32_to_cpu(irte.irte.dest_id);
28589311 2594 if (!iommu->intr_eime) {
651e4cef
PX		 2595#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2596#define VTD_IR_APIC_DEST_SHIFT (8)
28589311
JK		 2597 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
2598 VTD_IR_APIC_DEST_SHIFT;
2599 }
bc38ee10
MT		 2600 irq->dest_mode = irte.irte.dest_mode;
2601 irq->redir_hint = irte.irte.redir_hint;
651e4cef 2602
7feb51b7
PX		 2603 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
2604 irq->delivery_mode, irq->dest, irq->dest_mode);
651e4cef
PX		 2605
2606 return 0;
2607}
2608
2609/* Generate one MSI message from VTDIrq info */
2610static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2611{
2612 VTD_MSIMessage msg = {};
2613
2614 /* Generate address bits */
2615 msg.dest_mode = irq->dest_mode;
2616 msg.redir_hint = irq->redir_hint;
2617 msg.dest = irq->dest;
32946019 2618 msg.__addr_hi = irq->dest & 0xffffff00;
651e4cef
PX		 2619 msg.__addr_head = cpu_to_le32(0xfee);
2620 /* Keep this from original MSI address bits */
2621 msg.__not_used = irq->msi_addr_last_bits;
2622
2623 /* Generate data bits */
2624 msg.vector = irq->vector;
2625 msg.delivery_mode = irq->delivery_mode;
2626 msg.level = 1;
2627 msg.trigger_mode = irq->trigger_mode;
2628
2629 msg_out->address = msg.msi_addr;
2630 msg_out->data = msg.msi_data;
2631}
2632
2633/* Interrupt remapping for MSI/MSI-X entry */
2634static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2635 MSIMessage *origin,
ede9c94a
PX		 2636 MSIMessage *translated,
2637 uint16_t sid)
651e4cef
PX		 2638{
2639 int ret = 0;
2640 VTD_IR_MSIAddress addr;
2641 uint16_t index;
09cd058a 2642 VTDIrq irq = {};
651e4cef
PX		 2643
2644 assert(origin && translated);
2645
7feb51b7
PX		 2646 trace_vtd_ir_remap_msi_req(origin->address, origin->data);
2647
651e4cef 2648 if (!iommu || !iommu->intr_enabled) {
e7a3b91f
PX		 2649 memcpy(translated, origin, sizeof(*origin));
2650 goto out;
651e4cef
PX		 2651 }
2652
2653 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
7feb51b7
PX		 2654 trace_vtd_err("MSI address high 32 bits non-zero when "
2655 "Interrupt Remapping enabled.");
651e4cef
PX		 2656 return -VTD_FR_IR_REQ_RSVD;
2657 }
2658
2659 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
1a43713b 2660 if (addr.addr.__head != 0xfee) {
7feb51b7 2661 trace_vtd_err("MSI addr low 32 bit invalid.");
651e4cef
PX		 2662 return -VTD_FR_IR_REQ_RSVD;
2663 }
2664
2665 /* This is compatible mode. */
bc38ee10 2666 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
e7a3b91f
PX		 2667 memcpy(translated, origin, sizeof(*origin));
2668 goto out;
651e4cef
PX		 2669 }
2670
bc38ee10 2671 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
651e4cef
PX		 2672
2673#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2674#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2675
bc38ee10 2676 if (addr.addr.sub_valid) {
651e4cef
PX		 2677 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2678 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2679 }
2680
ede9c94a 2681 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
651e4cef
PX		 2682 if (ret) {
2683 return ret;
2684 }
2685
bc38ee10 2686 if (addr.addr.sub_valid) {
7feb51b7 2687 trace_vtd_ir_remap_type("MSI");
651e4cef 2688 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
7feb51b7 2689 trace_vtd_err_ir_msi_invalid(sid, origin->address, origin->data);
651e4cef
PX		 2690 return -VTD_FR_IR_REQ_RSVD;
2691 }
2692 } else {
2693 uint8_t vector = origin->data & 0xff;
dea651a9
FW		 2694 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
2695
7feb51b7 2696 trace_vtd_ir_remap_type("IOAPIC");
651e4cef
PX		 2697 /* IOAPIC entry vector should be aligned with IRTE vector
2698 * (see vt-d spec 5.1.5.1). */
2699 if (vector != irq.vector) {
7feb51b7 2700 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector);
651e4cef 2701 }
dea651a9
FW		 2702
2703 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2704 * (see vt-d spec 5.1.5.1). */
2705 if (trigger_mode != irq.trigger_mode) {
7feb51b7
PX		 2706 trace_vtd_warn_ir_trigger(sid, index, trigger_mode,
2707 irq.trigger_mode);
dea651a9 2708 }
651e4cef
PX		 2709 }
2710
2711 /*
2712 * We'd better keep the last two bits, assuming that guest OS
2713 * might modify it. Keep it does not hurt after all.
2714 */
bc38ee10 2715 irq.msi_addr_last_bits = addr.addr.__not_care;
651e4cef
PX		 2716
2717 /* Translate VTDIrq to MSI message */
2718 vtd_generate_msi_message(&irq, translated);
2719
e7a3b91f 2720out:
7feb51b7
PX		 2721 trace_vtd_ir_remap_msi(origin->address, origin->data,
2722 translated->address, translated->data);
651e4cef
PX		 2723 return 0;
2724}
2725
8b5ed7df
PX		 2726static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
2727 MSIMessage *dst, uint16_t sid)
2728{
ede9c94a
PX		 2729 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
2730 src, dst, sid);
8b5ed7df
PX		 2731}
2732
651e4cef
PX		 2733static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2734 uint64_t *data, unsigned size,
2735 MemTxAttrs attrs)
2736{
2737 return MEMTX_OK;
2738}
2739
2740static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2741 uint64_t value, unsigned size,
2742 MemTxAttrs attrs)
2743{
2744 int ret = 0;
09cd058a 2745 MSIMessage from = {}, to = {};
ede9c94a 2746 uint16_t sid = X86_IOMMU_SID_INVALID;
651e4cef
PX		 2747
2748 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2749 from.data = (uint32_t) value;
2750
ede9c94a
PX		 2751 if (!attrs.unspecified) {
2752 /* We have explicit Source ID */
2753 sid = attrs.requester_id;
2754 }
2755
2756 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
651e4cef
PX		 2757 if (ret) {
2758 /* TODO: report error */
651e4cef
PX		 2759 /* Drop this interrupt */
2760 return MEMTX_ERROR;
2761 }
2762
32946019 2763 apic_get_class()->send_msi(&to);
651e4cef
PX		 2764
2765 return MEMTX_OK;
2766}
2767
2768static const MemoryRegionOps vtd_mem_ir_ops = {
2769 .read_with_attrs = vtd_mem_ir_read,
2770 .write_with_attrs = vtd_mem_ir_write,
2771 .endianness = DEVICE_LITTLE_ENDIAN,
2772 .impl = {
2773 .min_access_size = 4,
2774 .max_access_size = 4,
2775 },
2776 .valid = {
2777 .min_access_size = 4,
2778 .max_access_size = 4,
2779 },
2780};
7df953bd
KO		 2781
2782VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2783{
2784 uintptr_t key = (uintptr_t)bus;
2785 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2786 VTDAddressSpace *vtd_dev_as;
e0a3c8cc 2787 char name[128];
7df953bd
KO		 2788
2789 if (!vtd_bus) {
2d3fc581
JW		 2790 uintptr_t *new_key = g_malloc(sizeof(*new_key));
2791 *new_key = (uintptr_t)bus;
7df953bd 2792 /* No corresponding free() */
04af0e18 2793 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
bf33cc75 2794 PCI_DEVFN_MAX);
7df953bd 2795 vtd_bus->bus = bus;
2d3fc581 2796 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
7df953bd
KO		 2797 }
2798
2799 vtd_dev_as = vtd_bus->dev_as[devfn];
2800
2801 if (!vtd_dev_as) {
e0a3c8cc 2802 snprintf(name, sizeof(name), "intel_iommu_devfn_%d", devfn);
7df953bd
KO		 2803 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2804
2805 vtd_dev_as->bus = bus;
2806 vtd_dev_as->devfn = (uint8_t)devfn;
2807 vtd_dev_as->iommu_state = s;
2808 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
558e0024
PX		 2809
2810 /*
2811 * Memory region relationships looks like (Address range shows
2812 * only lower 32 bits to make it short in length...):
2813 *
2814 * |-----------------+-------------------+----------|
2815 * | Name | Address range | Priority |
2816 * |-----------------+-------------------+----------+
2817 * | vtd_root | 00000000-ffffffff | 0 |
2818 * | intel_iommu | 00000000-ffffffff | 1 |
2819 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2820 * | intel_iommu_ir | fee00000-feefffff | 64 |
2821 * |-----------------+-------------------+----------|
2822 *
2823 * We enable/disable DMAR by switching enablement for
2824 * vtd_sys_alias and intel_iommu regions. IR region is always
2825 * enabled.
2826 */
1221a474
AK		 2827 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu),
2828 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s),
2829 "intel_iommu_dmar",
558e0024
PX		 2830 UINT64_MAX);
2831 memory_region_init_alias(&vtd_dev_as->sys_alias, OBJECT(s),
2832 "vtd_sys_alias", get_system_memory(),
2833 0, memory_region_size(get_system_memory()));
651e4cef
PX		 2834 memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2835 &vtd_mem_ir_ops, s, "intel_iommu_ir",
2836 VTD_INTERRUPT_ADDR_SIZE);
558e0024
PX		 2837 memory_region_init(&vtd_dev_as->root, OBJECT(s),
2838 "vtd_root", UINT64_MAX);
2839 memory_region_add_subregion_overlap(&vtd_dev_as->root,
2840 VTD_INTERRUPT_ADDR_FIRST,
2841 &vtd_dev_as->iommu_ir, 64);
2842 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, name);
2843 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
2844 &vtd_dev_as->sys_alias, 1);
2845 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
3df9d748
AK		 2846 MEMORY_REGION(&vtd_dev_as->iommu),
2847 1);
558e0024 2848 vtd_switch_address_space(vtd_dev_as);
7df953bd
KO		 2849 }
2850 return vtd_dev_as;
2851}
2852
dd4d607e
PX		 2853/* Unmap the whole range in the notifier's scope. */
2854static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
2855{
2856 IOMMUTLBEntry entry;
2857 hwaddr size;
2858 hwaddr start = n->start;
2859 hwaddr end = n->end;
37f51384 2860 IntelIOMMUState *s = as->iommu_state;
dd4d607e
PX		 2861
2862 /*
2863 * Note: all the codes in this function has a assumption that IOVA
2864 * bits are no more than VTD_MGAW bits (which is restricted by
2865 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2866 */
2867
37f51384 2868 if (end > VTD_ADDRESS_SIZE(s->aw_bits)) {
dd4d607e
PX		 2869 /*
2870 * Don't need to unmap regions that is bigger than the whole
2871 * VT-d supported address space size
2872 */
37f51384 2873 end = VTD_ADDRESS_SIZE(s->aw_bits);
dd4d607e
PX		 2874 }
2875
2876 assert(start <= end);
2877 size = end - start;
2878
2879 if (ctpop64(size) != 1) {
2880 /*
2881 * This size cannot format a correct mask. Let's enlarge it to
2882 * suite the minimum available mask.
2883 */
2884 int n = 64 - clz64(size);
37f51384 2885 if (n > s->aw_bits) {
dd4d607e 2886 /* should not happen, but in case it happens, limit it */
37f51384 2887 n = s->aw_bits;
dd4d607e
PX		 2888 }
2889 size = 1ULL << n;
2890 }
2891
2892 entry.target_as = &address_space_memory;
2893 /* Adjust iova for the size */
2894 entry.iova = n->start & ~(size - 1);
2895 /* This field is meaningless for unmap */
2896 entry.translated_addr = 0;
2897 entry.perm = IOMMU_NONE;
2898 entry.addr_mask = size - 1;
2899
2900 trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
2901 VTD_PCI_SLOT(as->devfn),
2902 VTD_PCI_FUNC(as->devfn),
2903 entry.iova, size);
2904
2905 memory_region_notify_one(n, &entry);
2906}
2907
2908static void vtd_address_space_unmap_all(IntelIOMMUState *s)
2909{
dd4d607e
PX		 2910 VTDAddressSpace *vtd_as;
2911 IOMMUNotifier *n;
2912
b4a4ba0d 2913 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
dd4d607e
PX		 2914 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
2915 vtd_address_space_unmap(vtd_as, n);
2916 }
2917 }
2918}
2919
f06a696d
PX		 2920static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private)
2921{
2922 memory_region_notify_one((IOMMUNotifier *)private, entry);
2923 return 0;
2924}
2925
3df9d748 2926static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f06a696d 2927{
3df9d748 2928 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu);
f06a696d
PX		 2929 IntelIOMMUState *s = vtd_as->iommu_state;
2930 uint8_t bus_n = pci_bus_num(vtd_as->bus);
2931 VTDContextEntry ce;
2932
dd4d607e
PX		 2933 /*
2934 * The replay can be triggered by either a invalidation or a newly
2935 * created entry. No matter what, we release existing mappings
2936 * (it means flushing caches for UNMAP-only registers).
2937 */
2938 vtd_address_space_unmap(vtd_as, n);
2939
f06a696d 2940 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
f06a696d
PX		 2941 trace_vtd_replay_ce_valid(bus_n, PCI_SLOT(vtd_as->devfn),
2942 PCI_FUNC(vtd_as->devfn),
2943 VTD_CONTEXT_ENTRY_DID(ce.hi),
2944 ce.hi, ce.lo);
4f8a62a9
PX		 2945 if (vtd_as_has_map_notifier(vtd_as)) {
2946 /* This is required only for MAP typed notifiers */
fe215b0c
PX		 2947 vtd_page_walk_info info = {
2948 .hook_fn = vtd_replay_hook,
2949 .private = (void *)n,
2950 .notify_unmap = false,
2951 .aw = s->aw_bits,
2f764fa8 2952 .as = vtd_as,
d118c06e 2953 .domain_id = VTD_CONTEXT_ENTRY_DID(ce.hi),
fe215b0c
PX		 2954 };
2955
2956 vtd_page_walk(&ce, 0, ~0ULL, &info);
4f8a62a9 2957 }
f06a696d
PX		 2958 } else {
2959 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
2960 PCI_FUNC(vtd_as->devfn));
2961 }
2962
2963 return;
2964}
2965
1da12ec4
LT		 2966/* Do the initialization. It will also be called when reset, so pay
2967 * attention when adding new initialization stuff.
2968 */
2969static void vtd_init(IntelIOMMUState *s)
2970{
d54bd7f8
PX		 2971 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2972
1da12ec4
LT		 2973 memset(s->csr, 0, DMAR_REG_SIZE);
2974 memset(s->wmask, 0, DMAR_REG_SIZE);
2975 memset(s->w1cmask, 0, DMAR_REG_SIZE);
2976 memset(s->womask, 0, DMAR_REG_SIZE);
2977
1da12ec4
LT		 2978 s->root = 0;
2979 s->root_extended = false;
2980 s->dmar_enabled = false;
2981 s->iq_head = 0;
2982 s->iq_tail = 0;
2983 s->iq = 0;
2984 s->iq_size = 0;
2985 s->qi_enabled = false;
2986 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2987 s->next_frcd_reg = 0;
92e5d85e
PS		 2988 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
2989 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
37f51384
PS		 2990 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits);
2991 if (s->aw_bits == VTD_HOST_AW_48BIT) {
2992 s->cap |= VTD_CAP_SAGAW_48bit;
2993 }
ed7b8fbc 2994 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
1da12ec4 2995
92e5d85e
PS		 2996 /*
2997 * Rsvd field masks for spte
2998 */
2999 vtd_paging_entry_rsvd_field[0] = ~0ULL;
37f51384
PS		 3000 vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
3001 vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
3002 vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
3003 vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
3004 vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
3005 vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
3006 vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
3007 vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
92e5d85e 3008
d54bd7f8 3009 if (x86_iommu->intr_supported) {
e6b6af05
RK		 3010 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
3011 if (s->intr_eim == ON_OFF_AUTO_ON) {
3012 s->ecap |= VTD_ECAP_EIM;
3013 }
3014 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
d54bd7f8
PX		 3015 }
3016
554f5e16
JW		 3017 if (x86_iommu->dt_supported) {
3018 s->ecap |= VTD_ECAP_DT;
3019 }
3020
dbaabb25
PX		 3021 if (x86_iommu->pt_supported) {
3022 s->ecap |= VTD_ECAP_PT;
3023 }
3024
3b40f0e5
ABD		 3025 if (s->caching_mode) {
3026 s->cap |= VTD_CAP_CM;
3027 }
3028
1d9efa73
PX		 3029 vtd_iommu_lock(s);
3030 vtd_reset_context_cache_locked(s);
3031 vtd_reset_iotlb_locked(s);
3032 vtd_iommu_unlock(s);
d92fa2dc 3033
1da12ec4
LT		 3034 /* Define registers with default values and bit semantics */
3035 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
3036 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
3037 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
3038 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
3039 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
3040 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
3041 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
3042 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
3043 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
3044
3045 /* Advanced Fault Logging not supported */
3046 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
3047 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
3048 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
3049 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
3050
3051 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
3052 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
3053 */
3054 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
3055
3056 /* Treated as RO for implementations that PLMR and PHMR fields reported
3057 * as Clear in the CAP_REG.
3058 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
3059 */
3060 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
3061
ed7b8fbc
LT		 3062 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
3063 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
3064 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
3065 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
3066 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
3067 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
3068 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
3069 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
3070 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
3071
1da12ec4
LT		 3072 /* IOTLB registers */
3073 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
3074 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
3075 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
3076
3077 /* Fault Recording Registers, 128-bit */
3078 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
3079 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
a5861439
PX		 3080
3081 /*
28589311 3082 * Interrupt remapping registers.
a5861439 3083 */
28589311 3084 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
1da12ec4
LT		 3085}
3086
3087/* Should not reset address_spaces when reset because devices will still use
3088 * the address space they got at first (won't ask the bus again).
3089 */
3090static void vtd_reset(DeviceState *dev)
3091{
3092 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
3093
1da12ec4 3094 vtd_init(s);
dd4d607e
PX		 3095
3096 /*
3097 * When device reset, throw away all mappings and external caches
3098 */
3099 vtd_address_space_unmap_all(s);
1da12ec4
LT		 3100}
3101
621d983a
MA		 3102static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
3103{
3104 IntelIOMMUState *s = opaque;
3105 VTDAddressSpace *vtd_as;
3106
bf33cc75 3107 assert(0 <= devfn && devfn < PCI_DEVFN_MAX);
621d983a
MA		 3108
3109 vtd_as = vtd_find_add_as(s, bus, devfn);
3110 return &vtd_as->as;
3111}
3112
e6b6af05 3113static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
6333e93c 3114{
e6b6af05
RK		 3115 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3116
6333e93c
RK		 3117 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
3118 if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() &&
3119 !kvm_irqchip_is_split()) {
3120 error_setg(errp, "Intel Interrupt Remapping cannot work with "
3121 "kernel-irqchip=on, please use 'split|off'.");
3122 return false;
3123 }
e6b6af05
RK		 3124 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu->intr_supported) {
3125 error_setg(errp, "eim=on cannot be selected without intremap=on");
3126 return false;
3127 }
3128
3129 if (s->intr_eim == ON_OFF_AUTO_AUTO) {
fb506e70
RK		 3130 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim)
3131 && x86_iommu->intr_supported ?
e6b6af05
RK		 3132 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
3133 }
fb506e70
RK		 3134 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) {
3135 if (!kvm_irqchip_in_kernel()) {
3136 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split");
3137 return false;
3138 }
3139 if (!kvm_enable_x2apic()) {
3140 error_setg(errp, "eim=on requires support on the KVM side"
3141 "(X2APIC_API, first shipped in v4.7)");
3142 return false;
3143 }
3144 }
e6b6af05 3145
37f51384
PS		 3146 /* Currently only address widths supported are 39 and 48 bits */
3147 if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
3148 (s->aw_bits != VTD_HOST_AW_48BIT)) {
3149 error_setg(errp, "Supported values for x-aw-bits are: %d, %d",
3150 VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
3151 return false;
3152 }
3153
6333e93c
RK		 3154 return true;
3155}
3156
1da12ec4
LT		 3157static void vtd_realize(DeviceState *dev, Error **errp)
3158{
ef0e8fc7 3159 MachineState *ms = MACHINE(qdev_get_machine());
29396ed9
MG		 3160 PCMachineState *pcms = PC_MACHINE(ms);
3161 PCIBus *bus = pcms->bus;
1da12ec4 3162 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
4684a204 3163 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
1da12ec4 3164
fb9f5926 3165 x86_iommu->type = TYPE_INTEL;
6333e93c 3166
e6b6af05 3167 if (!vtd_decide_config(s, errp)) {
6333e93c
RK		 3168 return;
3169 }
3170
b4a4ba0d 3171 QLIST_INIT(&s->vtd_as_with_notifiers);
1d9efa73 3172 qemu_mutex_init(&s->iommu_lock);
7df953bd 3173 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
1da12ec4
LT		 3174 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
3175 "intel_iommu", DMAR_REG_SIZE);
3176 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
b5a280c0
LT		 3177 /* No corresponding destroy */
3178 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3179 g_free, g_free);
7df953bd
KO		 3180 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3181 g_free, g_free);
1da12ec4 3182 vtd_init(s);
621d983a
MA		 3183 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
3184 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
cb135f59
PX		 3185 /* Pseudo address space under root PCI bus. */
3186 pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
1da12ec4
LT		 3187}
3188
3189static void vtd_class_init(ObjectClass *klass, void *data)
3190{
3191 DeviceClass *dc = DEVICE_CLASS(klass);
1c7955c4 3192 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
1da12ec4
LT		 3193
3194 dc->reset = vtd_reset;
1da12ec4
LT		 3195 dc->vmsd = &vtd_vmstate;
3196 dc->props = vtd_properties;
621d983a 3197 dc->hotpluggable = false;
1c7955c4 3198 x86_class->realize = vtd_realize;
8b5ed7df 3199 x86_class->int_remap = vtd_int_remap;
8ab5700c 3200 /* Supported by the pc-q35-* machine types */
e4f4fb1e 3201 dc->user_creatable = true;
1da12ec4
LT		 3202}
3203
3204static const TypeInfo vtd_info = {
3205 .name = TYPE_INTEL_IOMMU_DEVICE,
1c7955c4 3206 .parent = TYPE_X86_IOMMU_DEVICE,
1da12ec4
LT		 3207 .instance_size = sizeof(IntelIOMMUState),
3208 .class_init = vtd_class_init,
3209};
3210
1221a474
AK		 3211static void vtd_iommu_memory_region_class_init(ObjectClass *klass,
3212 void *data)
3213{
3214 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
3215
3216 imrc->translate = vtd_iommu_translate;
3217 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed;
3218 imrc->replay = vtd_iommu_replay;
3219}
3220
3221static const TypeInfo vtd_iommu_memory_region_info = {
3222 .parent = TYPE_IOMMU_MEMORY_REGION,
3223 .name = TYPE_INTEL_IOMMU_MEMORY_REGION,
3224 .class_init = vtd_iommu_memory_region_class_init,
3225};
3226
1da12ec4
LT		 3227static void vtd_register_types(void)
3228{
1da12ec4 3229 type_register_static(&vtd_info);
1221a474 3230 type_register_static(&vtd_iommu_memory_region_info);
1da12ec4
LT		 3231}
3232
3233type_init(vtd_register_types)
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