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Merge remote-tracking branch 'kraxel/seabios-a810e4e' into staging
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
022c62cb 2#include "exec/gdbstub.h"
7b59220e 3#include "helper.h"
1de7afc9 4#include "qemu/host-utils.h"
9c17d615 5#include "sysemu/sysemu.h"
1de7afc9 6#include "qemu/bitops.h"
0b03bdfc 7
4a501606
PM		 8#ifndef CONFIG_USER_ONLY
9static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
a8170e5e 11 hwaddr *phys_ptr, int *prot,
4a501606
PM		 12 target_ulong *page_size);
13#endif
14
0ecb72a5 15static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 16{
17 int nregs;
18
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
21 if (reg < nregs) {
22 stfq_le_p(buf, env->vfp.regs[reg]);
23 return 8;
24 }
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
27 nregs += 16;
28 if (reg < nregs) {
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
31 return 16;
32 }
33 }
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
38 }
39 return 0;
40}
41
0ecb72a5 42static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 43{
44 int nregs;
45
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
47 if (reg < nregs) {
48 env->vfp.regs[reg] = ldfq_le_p(buf);
49 return 8;
50 }
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
52 nregs += 16;
53 if (reg < nregs) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
56 return 16;
57 }
58 }
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 63 }
64 return 0;
65}
66
c983fe6c
PM		 67static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
68{
69 env->cp15.c3 = value;
70 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
71 return 0;
72}
73
08de207b
PM		 74static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
75{
76 if (env->cp15.c13_fcse != value) {
77 /* Unlike real hardware the qemu TLB uses virtual addresses,
78 * not modified virtual addresses, so this causes a TLB flush.
79 */
80 tlb_flush(env, 1);
81 env->cp15.c13_fcse = value;
82 }
83 return 0;
84}
85static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
86 uint64_t value)
87{
88 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
89 /* For VMSA (when not using the LPAE long descriptor page table
90 * format) this register includes the ASID, so do a TLB flush.
91 * For PMSA it is purely a process ID and no action is needed.
92 */
93 tlb_flush(env, 1);
94 }
95 env->cp15.c13_context = value;
96 return 0;
97}
98
d929823f
PM		 99static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
100 uint64_t value)
101{
102 /* Invalidate all (TLBIALL) */
103 tlb_flush(env, 1);
104 return 0;
105}
106
107static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
108 uint64_t value)
109{
110 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
111 tlb_flush_page(env, value & TARGET_PAGE_MASK);
112 return 0;
113}
114
115static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
116 uint64_t value)
117{
118 /* Invalidate by ASID (TLBIASID) */
119 tlb_flush(env, value == 0);
120 return 0;
121}
122
123static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
124 uint64_t value)
125{
126 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
127 tlb_flush_page(env, value & TARGET_PAGE_MASK);
128 return 0;
129}
130
e9aa6c21
PM		 131static const ARMCPRegInfo cp_reginfo[] = {
132 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
133 * version" bits will read as a reserved value, which should cause
134 * Linux to not try to use the debug hardware.
135 */
136 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
137 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 138 /* MMU Domain access control / MPU write buffer control */
139 { .name = "DACR", .cp = 15,
140 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
141 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
142 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 143 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
144 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
145 .resetvalue = 0, .writefn = fcse_write },
146 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
147 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
148 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 149 /* ??? This covers not just the impdef TLB lockdown registers but also
150 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 */
152 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
153 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 154 /* MMU TLB control. Note that the wildcarding means we cover not just
155 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 */
157 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
158 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
159 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
160 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
161 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
162 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
163 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
164 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 165 /* Cache maintenance ops; some of this space may be overridden later. */
166 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
167 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
168 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 169 REGINFO_SENTINEL
170};
171
7d57f408
PM		 172static const ARMCPRegInfo not_v6_cp_reginfo[] = {
173 /* Not all pre-v6 cores implemented this WFI, so this is slightly
174 * over-broad.
175 */
176 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
177 .access = PL1_W, .type = ARM_CP_WFI },
178 REGINFO_SENTINEL
179};
180
181static const ARMCPRegInfo not_v7_cp_reginfo[] = {
182 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
183 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 */
185 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
186 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 187 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
188 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
189 * OMAPCP will override this space.
190 */
191 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
192 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
193 .resetvalue = 0 },
194 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
195 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
196 .resetvalue = 0 },
776d4e5c
PM		 197 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
198 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
199 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 200 REGINFO_SENTINEL
201};
202
2771db27
PM		 203static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
204{
205 if (env->cp15.c1_coproc != value) {
206 env->cp15.c1_coproc = value;
207 /* ??? Is this safe when called from within a TB? */
208 tb_flush(env);
209 }
210 return 0;
211}
212
7d57f408
PM		 213static const ARMCPRegInfo v6_cp_reginfo[] = {
214 /* prefetch by MVA in v6, NOP in v7 */
215 { .name = "MVA_prefetch",
216 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
217 .access = PL1_W, .type = ARM_CP_NOP },
218 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
219 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 220 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 221 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 222 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 223 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 224 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
225 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
226 .resetvalue = 0, },
227 /* Watchpoint Fault Address Register : should actually only be present
228 * for 1136, 1176, 11MPCore.
229 */
230 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
231 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 232 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
233 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
234 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 235 REGINFO_SENTINEL
236};
237
200ac0ef
PM		 238static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
239 uint64_t *value)
240{
241 /* Generic performance monitor register read function for where
242 * user access may be allowed by PMUSERENR.
243 */
244 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
245 return EXCP_UDEF;
246 }
247 *value = CPREG_FIELD32(env, ri);
248 return 0;
249}
250
251static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
252 uint64_t value)
253{
254 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
255 return EXCP_UDEF;
256 }
257 /* only the DP, X, D and E bits are writable */
258 env->cp15.c9_pmcr &= ~0x39;
259 env->cp15.c9_pmcr |= (value & 0x39);
260 return 0;
261}
262
263static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
264 uint64_t value)
265{
266 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
267 return EXCP_UDEF;
268 }
269 value &= (1 << 31);
270 env->cp15.c9_pmcnten |= value;
271 return 0;
272}
273
274static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
275 uint64_t value)
276{
277 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
278 return EXCP_UDEF;
279 }
280 value &= (1 << 31);
281 env->cp15.c9_pmcnten &= ~value;
282 return 0;
283}
284
285static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
286 uint64_t value)
287{
288 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
289 return EXCP_UDEF;
290 }
291 env->cp15.c9_pmovsr &= ~value;
292 return 0;
293}
294
295static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
296 uint64_t value)
297{
298 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
299 return EXCP_UDEF;
300 }
301 env->cp15.c9_pmxevtyper = value & 0xff;
302 return 0;
303}
304
305static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
306 uint64_t value)
307{
308 env->cp15.c9_pmuserenr = value & 1;
309 return 0;
310}
311
312static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
313 uint64_t value)
314{
315 /* We have no event counters so only the C bit can be changed */
316 value &= (1 << 31);
317 env->cp15.c9_pminten |= value;
318 return 0;
319}
320
321static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
322 uint64_t value)
323{
324 value &= (1 << 31);
325 env->cp15.c9_pminten &= ~value;
326 return 0;
327}
328
776d4e5c
PM		 329static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
330 uint64_t *value)
331{
332 ARMCPU *cpu = arm_env_get_cpu(env);
333 *value = cpu->ccsidr[env->cp15.c0_cssel];
334 return 0;
335}
336
337static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
338 uint64_t value)
339{
340 env->cp15.c0_cssel = value & 0xf;
341 return 0;
342}
343
e9aa6c21
PM		 344static const ARMCPRegInfo v7_cp_reginfo[] = {
345 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
346 * debug components
347 */
348 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
349 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 350 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 351 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 352 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
353 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
354 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 355 /* Performance monitors are implementation defined in v7,
356 * but with an ARM recommended set of registers, which we
357 * follow (although we don't actually implement any counters)
358 *
359 * Performance registers fall into three categories:
360 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
361 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
362 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
363 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
364 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
365 */
366 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
367 .access = PL0_RW, .resetvalue = 0,
368 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
369 .readfn = pmreg_read, .writefn = pmcntenset_write },
370 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
371 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
372 .readfn = pmreg_read, .writefn = pmcntenclr_write },
373 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
374 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
375 .readfn = pmreg_read, .writefn = pmovsr_write },
376 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
377 * respect PMUSERENR.
378 */
379 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
380 .access = PL0_W, .type = ARM_CP_NOP },
381 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
382 * We choose to RAZ/WI. XXX should respect PMUSERENR.
383 */
384 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
385 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
386 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
387 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
388 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
390 .access = PL0_RW,
391 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
392 .readfn = pmreg_read, .writefn = pmxevtyper_write },
393 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
394 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
395 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
396 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
397 .access = PL0_R | PL1_RW,
398 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
399 .resetvalue = 0,
400 .writefn = pmuserenr_write },
401 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
402 .access = PL1_RW,
403 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
404 .resetvalue = 0,
405 .writefn = pmintenset_write },
406 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
407 .access = PL1_RW,
408 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
409 .resetvalue = 0,
410 .writefn = pmintenclr_write },
2771db27
PM		 411 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
412 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
413 .resetvalue = 0, },
776d4e5c
PM		 414 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
415 .access = PL1_R, .readfn = ccsidr_read },
416 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
417 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
418 .writefn = csselr_write, .resetvalue = 0 },
419 /* Auxiliary ID register: this actually has an IMPDEF value but for now
420 * just RAZ for all cores:
421 */
422 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
423 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 424 REGINFO_SENTINEL
425};
426
c326b979
PM		 427static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
428{
429 value &= 1;
430 env->teecr = value;
431 return 0;
432}
433
434static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
435 uint64_t *value)
436{
437 /* This is a helper function because the user access rights
438 * depend on the value of the TEECR.
439 */
440 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
441 return EXCP_UDEF;
442 }
443 *value = env->teehbr;
444 return 0;
445}
446
447static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
448 uint64_t value)
449{
450 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
451 return EXCP_UDEF;
452 }
453 env->teehbr = value;
454 return 0;
455}
456
457static const ARMCPRegInfo t2ee_cp_reginfo[] = {
458 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
459 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
460 .resetvalue = 0,
461 .writefn = teecr_write },
462 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
463 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
464 .resetvalue = 0,
465 .readfn = teehbr_read, .writefn = teehbr_write },
466 REGINFO_SENTINEL
467};
468
4d31c596
PM		 469static const ARMCPRegInfo v6k_cp_reginfo[] = {
470 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
471 .access = PL0_RW,
472 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
473 .resetvalue = 0 },
474 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
475 .access = PL0_R|PL1_W,
476 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
477 .resetvalue = 0 },
478 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
479 .access = PL1_RW,
480 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
481 .resetvalue = 0 },
482 REGINFO_SENTINEL
483};
484
6cc7a3ae
PM		 485static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
486 /* Dummy implementation: RAZ/WI the whole crn=14 space */
487 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
488 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
489 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
490 REGINFO_SENTINEL
491};
492
4a501606
PM		 493static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
494{
891a2fe7
PM		 495 if (arm_feature(env, ARM_FEATURE_LPAE)) {
496 env->cp15.c7_par = value;
497 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 498 env->cp15.c7_par = value & 0xfffff6ff;
499 } else {
500 env->cp15.c7_par = value & 0xfffff1ff;
501 }
502 return 0;
503}
504
505#ifndef CONFIG_USER_ONLY
506/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 507
508/* Return true if extended addresses are enabled, ie this is an
509 * LPAE implementation and we are using the long-descriptor translation
510 * table format because the TTBCR EAE bit is set.
511 */
512static inline bool extended_addresses_enabled(CPUARMState *env)
513{
514 return arm_feature(env, ARM_FEATURE_LPAE)
515 && (env->cp15.c2_control & (1 << 31));
516}
517
4a501606
PM		 518static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
519{
a8170e5e 520 hwaddr phys_addr;
4a501606
PM		 521 target_ulong page_size;
522 int prot;
523 int ret, is_user = ri->opc2 & 2;
524 int access_type = ri->opc2 & 1;
525
526 if (ri->opc2 & 4) {
527 /* Other states are only available with TrustZone */
528 return EXCP_UDEF;
529 }
530 ret = get_phys_addr(env, value, access_type, is_user,
531 &phys_addr, &prot, &page_size);
702a9357
PM		 532 if (extended_addresses_enabled(env)) {
533 /* ret is a DFSR/IFSR value for the long descriptor
534 * translation table format, but with WnR always clear.
535 * Convert it to a 64-bit PAR.
536 */
537 uint64_t par64 = (1 << 11); /* LPAE bit always set */
538 if (ret == 0) {
539 par64 |= phys_addr & ~0xfffULL;
540 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 541 } else {
702a9357
PM		 542 par64 |= 1; /* F */
543 par64 |= (ret & 0x3f) << 1; /* FS */
544 /* Note that S2WLK and FSTAGE are always zero, because we don't
545 * implement virtualization and therefore there can't be a stage 2
546 * fault.
547 */
4a501606 548 }
702a9357
PM		 549 env->cp15.c7_par = par64;
550 env->cp15.c7_par_hi = par64 >> 32;
4a501606 551 } else {
702a9357
PM		 552 /* ret is a DFSR/IFSR value for the short descriptor
553 * translation table format (with WnR always clear).
554 * Convert it to a 32-bit PAR.
555 */
556 if (ret == 0) {
557 /* We do not set any attribute bits in the PAR */
558 if (page_size == (1 << 24)
559 && arm_feature(env, ARM_FEATURE_V7)) {
560 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
561 } else {
562 env->cp15.c7_par = phys_addr & 0xfffff000;
563 }
564 } else {
565 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
566 ((ret & (12 << 1)) >> 6) |
567 ((ret & 0xf) << 1) | 1;
568 }
569 env->cp15.c7_par_hi = 0;
4a501606
PM		 570 }
571 return 0;
572}
573#endif
574
575static const ARMCPRegInfo vapa_cp_reginfo[] = {
576 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
577 .access = PL1_RW, .resetvalue = 0,
578 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
579 .writefn = par_write },
580#ifndef CONFIG_USER_ONLY
581 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
582 .access = PL1_W, .writefn = ats_write },
583#endif
584 REGINFO_SENTINEL
585};
586
18032bec
PM		 587/* Return basic MPU access permission bits. */
588static uint32_t simple_mpu_ap_bits(uint32_t val)
589{
590 uint32_t ret;
591 uint32_t mask;
592 int i;
593 ret = 0;
594 mask = 3;
595 for (i = 0; i < 16; i += 2) {
596 ret |= (val >> i) & mask;
597 mask <<= 2;
598 }
599 return ret;
600}
601
602/* Pad basic MPU access permission bits to extended format. */
603static uint32_t extended_mpu_ap_bits(uint32_t val)
604{
605 uint32_t ret;
606 uint32_t mask;
607 int i;
608 ret = 0;
609 mask = 3;
610 for (i = 0; i < 16; i += 2) {
611 ret |= (val & mask) << i;
612 mask <<= 2;
613 }
614 return ret;
615}
616
617static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
618 uint64_t value)
619{
620 env->cp15.c5_data = extended_mpu_ap_bits(value);
621 return 0;
622}
623
624static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
625 uint64_t *value)
626{
627 *value = simple_mpu_ap_bits(env->cp15.c5_data);
628 return 0;
629}
630
631static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
632 uint64_t value)
633{
634 env->cp15.c5_insn = extended_mpu_ap_bits(value);
635 return 0;
636}
637
638static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
639 uint64_t *value)
640{
641 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
642 return 0;
643}
644
06d76f31
PM		 645static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
646 uint64_t *value)
647{
599d64f6 648 if (ri->crm >= 8) {
06d76f31
PM		 649 return EXCP_UDEF;
650 }
651 *value = env->cp15.c6_region[ri->crm];
652 return 0;
653}
654
655static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
656 uint64_t value)
657{
599d64f6 658 if (ri->crm >= 8) {
06d76f31
PM		 659 return EXCP_UDEF;
660 }
661 env->cp15.c6_region[ri->crm] = value;
662 return 0;
663}
664
18032bec
PM		 665static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
666 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
667 .access = PL1_RW,
668 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
669 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
670 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
671 .access = PL1_RW,
672 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
673 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
674 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
675 .access = PL1_RW,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
677 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
678 .access = PL1_RW,
679 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 680 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
681 .access = PL1_RW,
682 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
683 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
684 .access = PL1_RW,
685 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 686 /* Protection region base and size registers */
687 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
688 .opc2 = CP_ANY, .access = PL1_RW,
689 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 690 REGINFO_SENTINEL
691};
692
ecce5c3c
PM		 693static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695{
e42c4db3
PM		 696 if (arm_feature(env, ARM_FEATURE_LPAE)) {
697 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
698 /* With LPAE the TTBCR could result in a change of ASID
699 * via the TTBCR.A1 bit, so do a TLB flush.
700 */
701 tlb_flush(env, 1);
702 } else {
703 value &= 7;
704 }
705 /* Note that we always calculate c2_mask and c2_base_mask, but
706 * they are only used for short-descriptor tables (ie if EAE is 0);
707 * for long-descriptor tables the TTBCR fields are used differently
708 * and the c2_mask and c2_base_mask values are meaningless.
709 */
ecce5c3c
PM		 710 env->cp15.c2_control = value;
711 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
712 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
713 return 0;
714}
715
716static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
717{
718 env->cp15.c2_base_mask = 0xffffc000u;
719 env->cp15.c2_control = 0;
720 env->cp15.c2_mask = 0;
721}
722
18032bec
PM		 723static const ARMCPRegInfo vmsa_cp_reginfo[] = {
724 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
725 .access = PL1_RW,
726 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
727 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
728 .access = PL1_RW,
729 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 730 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
731 .access = PL1_RW,
732 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
733 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
734 .access = PL1_RW,
81a60ada 735 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 736 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
737 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
738 .resetfn = vmsa_ttbcr_reset,
739 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 740 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
741 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
742 .resetvalue = 0, },
18032bec
PM		 743 REGINFO_SENTINEL
744};
745
1047b9d7
PM		 746static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
747 uint64_t value)
748{
749 env->cp15.c15_ticonfig = value & 0xe7;
750 /* The OS_TYPE bit in this register changes the reported CPUID! */
751 env->cp15.c0_cpuid = (value & (1 << 5)) ?
752 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
753 return 0;
754}
755
756static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
757 uint64_t value)
758{
759 env->cp15.c15_threadid = value & 0xffff;
760 return 0;
761}
762
763static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
764 uint64_t value)
765{
766 /* Wait-for-interrupt (deprecated) */
767 cpu_interrupt(env, CPU_INTERRUPT_HALT);
768 return 0;
769}
770
c4804214
PM		 771static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
772 uint64_t value)
773{
774 /* On OMAP there are registers indicating the max/min index of dcache lines
775 * containing a dirty line; cache flush operations have to reset these.
776 */
777 env->cp15.c15_i_max = 0x000;
778 env->cp15.c15_i_min = 0xff0;
779 return 0;
780}
781
18032bec
PM		 782static const ARMCPRegInfo omap_cp_reginfo[] = {
783 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
784 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
785 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 786 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
787 .access = PL1_RW, .type = ARM_CP_NOP },
788 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
789 .access = PL1_RW,
790 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
791 .writefn = omap_ticonfig_write },
792 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
793 .access = PL1_RW,
794 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
795 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
796 .access = PL1_RW, .resetvalue = 0xff0,
797 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
798 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
799 .access = PL1_RW,
800 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
801 .writefn = omap_threadid_write },
802 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
803 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
804 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
805 /* TODO: Peripheral port remap register:
806 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
807 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
808 * when MMU is off.
809 */
c4804214
PM		 810 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
811 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
812 .writefn = omap_cachemaint_write },
34f90529
PM		 813 { .name = "C9", .cp = 15, .crn = 9,
814 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
815 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 816 REGINFO_SENTINEL
817};
818
819static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
820 uint64_t value)
821{
822 value &= 0x3fff;
823 if (env->cp15.c15_cpar != value) {
824 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
825 tb_flush(env);
826 env->cp15.c15_cpar = value;
827 }
828 return 0;
829}
830
831static const ARMCPRegInfo xscale_cp_reginfo[] = {
832 { .name = "XSCALE_CPAR",
833 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
834 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
835 .writefn = xscale_cpar_write, },
2771db27
PM		 836 { .name = "XSCALE_AUXCR",
837 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
838 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
839 .resetvalue = 0, },
1047b9d7
PM		 840 REGINFO_SENTINEL
841};
842
843static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
844 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
845 * implementation of this implementation-defined space.
846 * Ideally this should eventually disappear in favour of actually
847 * implementing the correct behaviour for all cores.
848 */
849 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
850 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
851 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 852 REGINFO_SENTINEL
853};
854
c4804214
PM		 855static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
856 /* Cache status: RAZ because we have no cache so it's always clean */
857 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
858 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
859 REGINFO_SENTINEL
860};
861
862static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
863 /* We never have a a block transfer operation in progress */
864 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
865 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
30b05bba
PM		 866 /* The cache ops themselves: these all NOP for QEMU */
867 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
868 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
869 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
870 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
871 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
872 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
873 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
874 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
875 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
876 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
877 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
878 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 879 REGINFO_SENTINEL
880};
881
882static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
883 /* The cache test-and-clean instructions always return (1 << 30)
884 * to indicate that there are no dirty cache lines.
885 */
886 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
887 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
888 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
889 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
890 REGINFO_SENTINEL
891};
892
34f90529
PM		 893static const ARMCPRegInfo strongarm_cp_reginfo[] = {
894 /* Ignore ReadBuffer accesses */
895 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
896 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
897 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
898 .resetvalue = 0 },
899 REGINFO_SENTINEL
900};
901
81bdde9d
PM		 902static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
903 uint64_t *value)
904{
905 uint32_t mpidr = env->cpu_index;
906 /* We don't support setting cluster ID ([8..11])
907 * so these bits always RAZ.
908 */
909 if (arm_feature(env, ARM_FEATURE_V7MP)) {
910 mpidr |= (1 << 31);
911 /* Cores which are uniprocessor (non-coherent)
912 * but still implement the MP extensions set
913 * bit 30. (For instance, A9UP.) However we do
914 * not currently model any of those cores.
915 */
916 }
917 *value = mpidr;
918 return 0;
919}
920
921static const ARMCPRegInfo mpidr_cp_reginfo[] = {
922 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
923 .access = PL1_R, .readfn = mpidr_read },
924 REGINFO_SENTINEL
925};
926
891a2fe7
PM		 927static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
928{
929 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
930 return 0;
931}
932
933static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
934{
935 env->cp15.c7_par_hi = value >> 32;
936 env->cp15.c7_par = value;
937 return 0;
938}
939
940static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
941{
942 env->cp15.c7_par_hi = 0;
943 env->cp15.c7_par = 0;
944}
945
946static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
947 uint64_t *value)
948{
949 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
950 return 0;
951}
952
953static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
954 uint64_t value)
955{
956 env->cp15.c2_base0_hi = value >> 32;
957 env->cp15.c2_base0 = value;
958 /* Writes to the 64 bit format TTBRs may change the ASID */
959 tlb_flush(env, 1);
960 return 0;
961}
962
963static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
964{
965 env->cp15.c2_base0_hi = 0;
966 env->cp15.c2_base0 = 0;
967}
968
969static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
970 uint64_t *value)
971{
972 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
973 return 0;
974}
975
976static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
977 uint64_t value)
978{
979 env->cp15.c2_base1_hi = value >> 32;
980 env->cp15.c2_base1 = value;
981 return 0;
982}
983
984static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
985{
986 env->cp15.c2_base1_hi = 0;
987 env->cp15.c2_base1 = 0;
988}
989
7ac681cf 990static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 991 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 992 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
993 */
994 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
995 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
996 .resetvalue = 0 },
997 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
998 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
999 .resetvalue = 0 },
f9fc619a
PM		 1000 /* 64 bit access versions of the (dummy) debug registers */
1001 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1002 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1003 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1004 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1005 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1006 .access = PL1_RW, .type = ARM_CP_64BIT,
1007 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1008 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1009 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1010 .writefn = ttbr064_write, .resetfn = ttbr064_reset },
1011 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1012 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1013 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1014 REGINFO_SENTINEL
1015};
1016
2771db27
PM		 1017static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1018{
1019 env->cp15.c1_sys = value;
1020 /* ??? Lots of these bits are not implemented. */
1021 /* This may enable/disable the MMU, so do a TLB flush. */
1022 tlb_flush(env, 1);
1023 return 0;
1024}
1025
2ceb98c0
PM		 1026void register_cp_regs_for_features(ARMCPU *cpu)
1027{
1028 /* Register all the coprocessor registers based on feature bits */
1029 CPUARMState *env = &cpu->env;
1030 if (arm_feature(env, ARM_FEATURE_M)) {
1031 /* M profile has no coprocessor registers */
1032 return;
1033 }
1034
e9aa6c21 1035 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1036 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1037 /* The ID registers all have impdef reset values */
1038 ARMCPRegInfo v6_idregs[] = {
1039 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1040 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1041 .resetvalue = cpu->id_pfr0 },
1042 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1043 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1044 .resetvalue = cpu->id_pfr1 },
1045 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1046 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1047 .resetvalue = cpu->id_dfr0 },
1048 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1049 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1050 .resetvalue = cpu->id_afr0 },
1051 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1052 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1053 .resetvalue = cpu->id_mmfr0 },
1054 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1055 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1056 .resetvalue = cpu->id_mmfr1 },
1057 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1058 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1059 .resetvalue = cpu->id_mmfr2 },
1060 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1061 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1062 .resetvalue = cpu->id_mmfr3 },
1063 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1064 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1065 .resetvalue = cpu->id_isar0 },
1066 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1067 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1068 .resetvalue = cpu->id_isar1 },
1069 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1070 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1071 .resetvalue = cpu->id_isar2 },
1072 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1073 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1074 .resetvalue = cpu->id_isar3 },
1075 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1076 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1077 .resetvalue = cpu->id_isar4 },
1078 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1079 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1080 .resetvalue = cpu->id_isar5 },
1081 /* 6..7 are as yet unallocated and must RAZ */
1082 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1083 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1084 .resetvalue = 0 },
1085 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1086 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1087 .resetvalue = 0 },
1088 REGINFO_SENTINEL
1089 };
1090 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1091 define_arm_cp_regs(cpu, v6_cp_reginfo);
1092 } else {
1093 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1094 }
4d31c596
PM		 1095 if (arm_feature(env, ARM_FEATURE_V6K)) {
1096 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1097 }
e9aa6c21 1098 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1099 /* v7 performance monitor control register: same implementor
1100 * field as main ID register, and we implement no event counters.
1101 */
1102 ARMCPRegInfo pmcr = {
1103 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1104 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1105 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1106 .readfn = pmreg_read, .writefn = pmcr_write
1107 };
776d4e5c
PM		 1108 ARMCPRegInfo clidr = {
1109 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1110 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1111 };
200ac0ef 1112 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1113 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1114 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1115 } else {
1116 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1117 }
18032bec
PM		 1118 if (arm_feature(env, ARM_FEATURE_MPU)) {
1119 /* These are the MPU registers prior to PMSAv6. Any new
1120 * PMSA core later than the ARM946 will require that we
1121 * implement the PMSAv6 or PMSAv7 registers, which are
1122 * completely different.
1123 */
1124 assert(!arm_feature(env, ARM_FEATURE_V6));
1125 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1126 } else {
1127 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1128 }
c326b979
PM		 1129 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1130 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1131 }
6cc7a3ae
PM		 1132 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1133 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1134 }
4a501606
PM		 1135 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1136 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1137 }
c4804214
PM		 1138 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1139 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1140 }
1141 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1142 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1143 }
1144 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1145 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1146 }
18032bec
PM		 1147 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1148 define_arm_cp_regs(cpu, omap_cp_reginfo);
1149 }
34f90529
PM		 1150 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1151 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1152 }
1047b9d7
PM		 1153 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1154 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1155 }
1156 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1157 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1158 }
81bdde9d
PM		 1159 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1160 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1161 }
7ac681cf
PM		 1162 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1163 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1164 }
7884849c
PM		 1165 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1166 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1167 * be read-only (ie write causes UNDEF exception).
1168 */
1169 {
1170 ARMCPRegInfo id_cp_reginfo[] = {
1171 /* Note that the MIDR isn't a simple constant register because
1172 * of the TI925 behaviour where writes to another register can
1173 * cause the MIDR value to change.
1174 */
1175 { .name = "MIDR",
1176 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1177 .access = PL1_R, .resetvalue = cpu->midr,
1178 .writefn = arm_cp_write_ignore,
1179 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1180 { .name = "CTR",
1181 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1182 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1183 { .name = "TCMTR",
1184 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1185 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1186 { .name = "TLBTR",
1187 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1188 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1189 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1190 { .name = "DUMMY",
1191 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1192 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1193 { .name = "DUMMY",
1194 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1195 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1196 { .name = "DUMMY",
1197 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1198 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1199 { .name = "DUMMY",
1200 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1201 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1202 { .name = "DUMMY",
1203 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1204 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1205 REGINFO_SENTINEL
1206 };
1207 ARMCPRegInfo crn0_wi_reginfo = {
1208 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1209 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1210 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1211 };
1212 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1213 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1214 ARMCPRegInfo *r;
1215 /* Register the blanket "writes ignored" value first to cover the
1216 * whole space. Then define the specific ID registers, but update
1217 * their access field to allow write access, so that they ignore
1218 * writes rather than causing them to UNDEF.
1219 */
1220 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1221 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1222 r->access = PL1_RW;
1223 define_one_arm_cp_reg(cpu, r);
1224 }
1225 } else {
1226 /* Just register the standard ID registers (read-only, meaning
1227 * that writes will UNDEF).
1228 */
1229 define_arm_cp_regs(cpu, id_cp_reginfo);
1230 }
1231 }
1232
2771db27
PM		 1233 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1234 ARMCPRegInfo auxcr = {
1235 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1236 .access = PL1_RW, .type = ARM_CP_CONST,
1237 .resetvalue = cpu->reset_auxcr
1238 };
1239 define_one_arm_cp_reg(cpu, &auxcr);
1240 }
1241
1242 /* Generic registers whose values depend on the implementation */
1243 {
1244 ARMCPRegInfo sctlr = {
1245 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1246 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1247 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1248 };
1249 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1250 /* Normally we would always end the TB on an SCTLR write, but Linux
1251 * arch/arm/mach-pxa/sleep.S expects two instructions following
1252 * an MMU enable to execute from cache. Imitate this behaviour.
1253 */
1254 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1255 }
1256 define_one_arm_cp_reg(cpu, &sctlr);
1257 }
2ceb98c0
PM		 1258}
1259
778c3a06 1260ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1261{
dec9c2d4 1262 ARMCPU *cpu;
40f137e1 1263 CPUARMState *env;
b26eefb6 1264 static int inited = 0;
40f137e1 1265
777dc784 1266 if (!object_class_by_name(cpu_model)) {
aaed909a 1267 return NULL;
777dc784
PM		 1268 }
1269 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 1270 env = &cpu->env;
777dc784 1271 env->cpu_model_str = cpu_model;
581be094 1272 arm_cpu_realize(cpu);
777dc784 1273
f4fc247b 1274 if (tcg_enabled() && !inited) {
b26eefb6
PB		 1275 inited = 1;
1276 arm_translate_init();
1277 }
1278
df90dadb 1279 cpu_reset(CPU(cpu));
56aebc89
PB		 1280 if (arm_feature(env, ARM_FEATURE_NEON)) {
1281 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1282 51, "arm-neon.xml", 0);
1283 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1284 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1285 35, "arm-vfp3.xml", 0);
1286 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1287 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1288 19, "arm-vfp.xml", 0);
1289 }
0bf46a40 1290 qemu_init_vcpu(env);
778c3a06 1291 return cpu;
40f137e1
PB		 1292}
1293
777dc784
PM		 1294/* Sort alphabetically by type name, except for "any". */
1295static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1296{
777dc784
PM		 1297 ObjectClass *class_a = (ObjectClass *)a;
1298 ObjectClass *class_b = (ObjectClass *)b;
1299 const char *name_a, *name_b;
5adb4839 1300
777dc784
PM		 1301 name_a = object_class_get_name(class_a);
1302 name_b = object_class_get_name(class_b);
1303 if (strcmp(name_a, "any") == 0) {
1304 return 1;
1305 } else if (strcmp(name_b, "any") == 0) {
1306 return -1;
1307 } else {
1308 return strcmp(name_a, name_b);
5adb4839
PB		 1309 }
1310}
1311
777dc784 1312static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1313{
777dc784 1314 ObjectClass *oc = data;
92a31361 1315 CPUListState *s = user_data;
3371d272 1316
777dc784
PM		 1317 (*s->cpu_fprintf)(s->file, " %s\n",
1318 object_class_get_name(oc));
1319}
1320
1321void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1322{
92a31361 1323 CPUListState s = {
777dc784
PM		 1324 .file = f,
1325 .cpu_fprintf = cpu_fprintf,
1326 };
1327 GSList *list;
1328
1329 list = object_class_get_list(TYPE_ARM_CPU, false);
1330 list = g_slist_sort(list, arm_cpu_list_compare);
1331 (*cpu_fprintf)(f, "Available CPUs:\n");
1332 g_slist_foreach(list, arm_cpu_list_entry, &s);
1333 g_slist_free(list);
40f137e1
PB		 1334}
1335
4b6a83fb
PM		 1336void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1337 const ARMCPRegInfo *r, void *opaque)
1338{
1339 /* Define implementations of coprocessor registers.
1340 * We store these in a hashtable because typically
1341 * there are less than 150 registers in a space which
1342 * is 16*16*16*8*8 = 262144 in size.
1343 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1344 * If a register is defined twice then the second definition is
1345 * used, so this can be used to define some generic registers and
1346 * then override them with implementation specific variations.
1347 * At least one of the original and the second definition should
1348 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1349 * against accidental use.
1350 */
1351 int crm, opc1, opc2;
1352 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1353 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1354 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1355 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1356 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1357 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1358 /* 64 bit registers have only CRm and Opc1 fields */
1359 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1360 /* Check that the register definition has enough info to handle
1361 * reads and writes if they are permitted.
1362 */
1363 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1364 if (r->access & PL3_R) {
1365 assert(r->fieldoffset || r->readfn);
1366 }
1367 if (r->access & PL3_W) {
1368 assert(r->fieldoffset || r->writefn);
1369 }
1370 }
1371 /* Bad type field probably means missing sentinel at end of reg list */
1372 assert(cptype_valid(r->type));
1373 for (crm = crmmin; crm <= crmmax; crm++) {
1374 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1375 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1376 uint32_t *key = g_new(uint32_t, 1);
1377 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1378 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1379 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1380 r2->opaque = opaque;
1381 /* Make sure reginfo passed to helpers for wildcarded regs
1382 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1383 */
1384 r2->crm = crm;
1385 r2->opc1 = opc1;
1386 r2->opc2 = opc2;
1387 /* Overriding of an existing definition must be explicitly
1388 * requested.
1389 */
1390 if (!(r->type & ARM_CP_OVERRIDE)) {
1391 ARMCPRegInfo *oldreg;
1392 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1393 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1394 fprintf(stderr, "Register redefined: cp=%d %d bit "
1395 "crn=%d crm=%d opc1=%d opc2=%d, "
1396 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1397 r2->crn, r2->crm, r2->opc1, r2->opc2,
1398 oldreg->name, r2->name);
1399 assert(0);
1400 }
1401 }
1402 g_hash_table_insert(cpu->cp_regs, key, r2);
1403 }
1404 }
1405 }
1406}
1407
1408void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1409 const ARMCPRegInfo *regs, void *opaque)
1410{
1411 /* Define a whole list of registers */
1412 const ARMCPRegInfo *r;
1413 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1414 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1415 }
1416}
1417
1418const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1419{
1420 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1421}
1422
1423int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1424 uint64_t value)
1425{
1426 /* Helper coprocessor write function for write-ignore registers */
1427 return 0;
1428}
1429
1430int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1431{
1432 /* Helper coprocessor write function for read-as-zero registers */
1433 *value = 0;
1434 return 0;
1435}
1436
0ecb72a5 1437static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1438{
1439 /* Return true if it is not valid for us to switch to
1440 * this CPU mode (ie all the UNPREDICTABLE cases in
1441 * the ARM ARM CPSRWriteByInstr pseudocode).
1442 */
1443 switch (mode) {
1444 case ARM_CPU_MODE_USR:
1445 case ARM_CPU_MODE_SYS:
1446 case ARM_CPU_MODE_SVC:
1447 case ARM_CPU_MODE_ABT:
1448 case ARM_CPU_MODE_UND:
1449 case ARM_CPU_MODE_IRQ:
1450 case ARM_CPU_MODE_FIQ:
1451 return 0;
1452 default:
1453 return 1;
1454 }
1455}
1456
2f4a40e5
AZ		 1457uint32_t cpsr_read(CPUARMState *env)
1458{
1459 int ZF;
6fbe23d5
PB		 1460 ZF = (env->ZF == 0);
1461 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1462 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1463 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1464 | ((env->condexec_bits & 0xfc) << 8)
1465 | (env->GE << 16);
1466}
1467
1468void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1469{
2f4a40e5 1470 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1471 env->ZF = (~val) & CPSR_Z;
1472 env->NF = val;
2f4a40e5
AZ		 1473 env->CF = (val >> 29) & 1;
1474 env->VF = (val << 3) & 0x80000000;
1475 }
1476 if (mask & CPSR_Q)
1477 env->QF = ((val & CPSR_Q) != 0);
1478 if (mask & CPSR_T)
1479 env->thumb = ((val & CPSR_T) != 0);
1480 if (mask & CPSR_IT_0_1) {
1481 env->condexec_bits &= ~3;
1482 env->condexec_bits |= (val >> 25) & 3;
1483 }
1484 if (mask & CPSR_IT_2_7) {
1485 env->condexec_bits &= 3;
1486 env->condexec_bits |= (val >> 8) & 0xfc;
1487 }
1488 if (mask & CPSR_GE) {
1489 env->GE = (val >> 16) & 0xf;
1490 }
1491
1492 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1493 if (bad_mode_switch(env, val & CPSR_M)) {
1494 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1495 * We choose to ignore the attempt and leave the CPSR M field
1496 * untouched.
1497 */
1498 mask &= ~CPSR_M;
1499 } else {
1500 switch_mode(env, val & CPSR_M);
1501 }
2f4a40e5
AZ		 1502 }
1503 mask &= ~CACHED_CPSR_BITS;
1504 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1505}
1506
b26eefb6
PB		 1507/* Sign/zero extend */
1508uint32_t HELPER(sxtb16)(uint32_t x)
1509{
1510 uint32_t res;
1511 res = (uint16_t)(int8_t)x;
1512 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1513 return res;
1514}
1515
1516uint32_t HELPER(uxtb16)(uint32_t x)
1517{
1518 uint32_t res;
1519 res = (uint16_t)(uint8_t)x;
1520 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1521 return res;
1522}
1523
f51bbbfe
PB		 1524uint32_t HELPER(clz)(uint32_t x)
1525{
7bbcb0af 1526 return clz32(x);
f51bbbfe
PB		 1527}
1528
3670669c
PB		 1529int32_t HELPER(sdiv)(int32_t num, int32_t den)
1530{
1531 if (den == 0)
1532 return 0;
686eeb93
AJ		 1533 if (num == INT_MIN && den == -1)
1534 return INT_MIN;
3670669c
PB		 1535 return num / den;
1536}
1537
1538uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1539{
1540 if (den == 0)
1541 return 0;
1542 return num / den;
1543}
1544
1545uint32_t HELPER(rbit)(uint32_t x)
1546{
1547 x = ((x & 0xff000000) >> 24)
1548 | ((x & 0x00ff0000) >> 8)
1549 | ((x & 0x0000ff00) << 8)
1550 | ((x & 0x000000ff) << 24);
1551 x = ((x & 0xf0f0f0f0) >> 4)
1552 | ((x & 0x0f0f0f0f) << 4);
1553 x = ((x & 0x88888888) >> 3)
1554 | ((x & 0x44444444) >> 1)
1555 | ((x & 0x22222222) << 1)
1556 | ((x & 0x11111111) << 3);
1557 return x;
1558}
1559
5fafdf24 1560#if defined(CONFIG_USER_ONLY)
b5ff1b31 1561
0ecb72a5 1562void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 1563{
1564 env->exception_index = -1;
1565}
1566
0ecb72a5 1567int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1568 int mmu_idx)
b5ff1b31
FB		 1569{
1570 if (rw == 2) {
1571 env->exception_index = EXCP_PREFETCH_ABORT;
1572 env->cp15.c6_insn = address;
1573 } else {
1574 env->exception_index = EXCP_DATA_ABORT;
1575 env->cp15.c6_data = address;
1576 }
1577 return 1;
1578}
1579
9ee6e8bb 1580/* These should probably raise undefined insn exceptions. */
0ecb72a5 1581void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1582{
1583 cpu_abort(env, "v7m_mrs %d\n", reg);
1584}
1585
0ecb72a5 1586uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1587{
1588 cpu_abort(env, "v7m_mrs %d\n", reg);
1589 return 0;
1590}
1591
0ecb72a5 1592void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1593{
1594 if (mode != ARM_CPU_MODE_USR)
1595 cpu_abort(env, "Tried to switch out of user mode\n");
1596}
1597
0ecb72a5 1598void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1599{
1600 cpu_abort(env, "banked r13 write\n");
1601}
1602
0ecb72a5 1603uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1604{
1605 cpu_abort(env, "banked r13 read\n");
1606 return 0;
1607}
1608
b5ff1b31
FB		 1609#else
1610
1611/* Map CPU modes onto saved register banks. */
0ecb72a5 1612static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 1613{
1614 switch (mode) {
1615 case ARM_CPU_MODE_USR:
1616 case ARM_CPU_MODE_SYS:
1617 return 0;
1618 case ARM_CPU_MODE_SVC:
1619 return 1;
1620 case ARM_CPU_MODE_ABT:
1621 return 2;
1622 case ARM_CPU_MODE_UND:
1623 return 3;
1624 case ARM_CPU_MODE_IRQ:
1625 return 4;
1626 case ARM_CPU_MODE_FIQ:
1627 return 5;
1628 }
1b9e01c1 1629 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 1630 return -1;
1631}
1632
0ecb72a5 1633void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1634{
1635 int old_mode;
1636 int i;
1637
1638 old_mode = env->uncached_cpsr & CPSR_M;
1639 if (mode == old_mode)
1640 return;
1641
1642 if (old_mode == ARM_CPU_MODE_FIQ) {
1643 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1644 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1645 } else if (mode == ARM_CPU_MODE_FIQ) {
1646 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1647 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1648 }
1649
1b9e01c1 1650 i = bank_number(env, old_mode);
b5ff1b31
FB		 1651 env->banked_r13[i] = env->regs[13];
1652 env->banked_r14[i] = env->regs[14];
1653 env->banked_spsr[i] = env->spsr;
1654
1b9e01c1 1655 i = bank_number(env, mode);
b5ff1b31
FB		 1656 env->regs[13] = env->banked_r13[i];
1657 env->regs[14] = env->banked_r14[i];
1658 env->spsr = env->banked_spsr[i];
1659}
1660
9ee6e8bb
PB		 1661static void v7m_push(CPUARMState *env, uint32_t val)
1662{
1663 env->regs[13] -= 4;
1664 stl_phys(env->regs[13], val);
1665}
1666
1667static uint32_t v7m_pop(CPUARMState *env)
1668{
1669 uint32_t val;
1670 val = ldl_phys(env->regs[13]);
1671 env->regs[13] += 4;
1672 return val;
1673}
1674
1675/* Switch to V7M main or process stack pointer. */
1676static void switch_v7m_sp(CPUARMState *env, int process)
1677{
1678 uint32_t tmp;
1679 if (env->v7m.current_sp != process) {
1680 tmp = env->v7m.other_sp;
1681 env->v7m.other_sp = env->regs[13];
1682 env->regs[13] = tmp;
1683 env->v7m.current_sp = process;
1684 }
1685}
1686
1687static void do_v7m_exception_exit(CPUARMState *env)
1688{
1689 uint32_t type;
1690 uint32_t xpsr;
1691
1692 type = env->regs[15];
1693 if (env->v7m.exception != 0)
983fe826 1694 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1695
1696 /* Switch to the target stack. */
1697 switch_v7m_sp(env, (type & 4) != 0);
1698 /* Pop registers. */
1699 env->regs[0] = v7m_pop(env);
1700 env->regs[1] = v7m_pop(env);
1701 env->regs[2] = v7m_pop(env);
1702 env->regs[3] = v7m_pop(env);
1703 env->regs[12] = v7m_pop(env);
1704 env->regs[14] = v7m_pop(env);
1705 env->regs[15] = v7m_pop(env);
1706 xpsr = v7m_pop(env);
1707 xpsr_write(env, xpsr, 0xfffffdff);
1708 /* Undo stack alignment. */
1709 if (xpsr & 0x200)
1710 env->regs[13] |= 4;
1711 /* ??? The exception return type specifies Thread/Handler mode. However
1712 this is also implied by the xPSR value. Not sure what to do
1713 if there is a mismatch. */
1714 /* ??? Likewise for mismatches between the CONTROL register and the stack
1715 pointer. */
1716}
1717
2b3ea315 1718static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1719{
1720 uint32_t xpsr = xpsr_read(env);
1721 uint32_t lr;
1722 uint32_t addr;
1723
1724 lr = 0xfffffff1;
1725 if (env->v7m.current_sp)
1726 lr |= 4;
1727 if (env->v7m.exception == 0)
1728 lr |= 8;
1729
1730 /* For exceptions we just mark as pending on the NVIC, and let that
1731 handle it. */
1732 /* TODO: Need to escalate if the current priority is higher than the
1733 one we're raising. */
1734 switch (env->exception_index) {
1735 case EXCP_UDEF:
983fe826 1736 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1737 return;
1738 case EXCP_SWI:
1739 env->regs[15] += 2;
983fe826 1740 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1741 return;
1742 case EXCP_PREFETCH_ABORT:
1743 case EXCP_DATA_ABORT:
983fe826 1744 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1745 return;
1746 case EXCP_BKPT:
2ad207d4
PB		 1747 if (semihosting_enabled) {
1748 int nr;
d31dd73e 1749 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1750 if (nr == 0xab) {
1751 env->regs[15] += 2;
1752 env->regs[0] = do_arm_semihosting(env);
1753 return;
1754 }
1755 }
983fe826 1756 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1757 return;
1758 case EXCP_IRQ:
983fe826 1759 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1760 break;
1761 case EXCP_EXCEPTION_EXIT:
1762 do_v7m_exception_exit(env);
1763 return;
1764 default:
1765 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1766 return; /* Never happens. Keep compiler happy. */
1767 }
1768
1769 /* Align stack pointer. */
1770 /* ??? Should only do this if Configuration Control Register
1771 STACKALIGN bit is set. */
1772 if (env->regs[13] & 4) {
ab19b0ec 1773 env->regs[13] -= 4;
9ee6e8bb
PB		 1774 xpsr |= 0x200;
1775 }
6c95676b 1776 /* Switch to the handler mode. */
9ee6e8bb
PB		 1777 v7m_push(env, xpsr);
1778 v7m_push(env, env->regs[15]);
1779 v7m_push(env, env->regs[14]);
1780 v7m_push(env, env->regs[12]);
1781 v7m_push(env, env->regs[3]);
1782 v7m_push(env, env->regs[2]);
1783 v7m_push(env, env->regs[1]);
1784 v7m_push(env, env->regs[0]);
1785 switch_v7m_sp(env, 0);
c98d174c
PM		 1786 /* Clear IT bits */
1787 env->condexec_bits = 0;
9ee6e8bb
PB		 1788 env->regs[14] = lr;
1789 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1790 env->regs[15] = addr & 0xfffffffe;
1791 env->thumb = addr & 1;
1792}
1793
b5ff1b31
FB		 1794/* Handle a CPU exception. */
1795void do_interrupt(CPUARMState *env)
1796{
1797 uint32_t addr;
1798 uint32_t mask;
1799 int new_mode;
1800 uint32_t offset;
1801
9ee6e8bb
PB		 1802 if (IS_M(env)) {
1803 do_interrupt_v7m(env);
1804 return;
1805 }
b5ff1b31
FB		 1806 /* TODO: Vectored interrupt controller. */
1807 switch (env->exception_index) {
1808 case EXCP_UDEF:
1809 new_mode = ARM_CPU_MODE_UND;
1810 addr = 0x04;
1811 mask = CPSR_I;
1812 if (env->thumb)
1813 offset = 2;
1814 else
1815 offset = 4;
1816 break;
1817 case EXCP_SWI:
8e71621f
PB		 1818 if (semihosting_enabled) {
1819 /* Check for semihosting interrupt. */
1820 if (env->thumb) {
d31dd73e
BS		 1821 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
1822 & 0xff;
8e71621f 1823 } else {
d31dd73e 1824 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 1825 & 0xffffff;
8e71621f
PB		 1826 }
1827 /* Only intercept calls from privileged modes, to provide some
1828 semblance of security. */
1829 if (((mask == 0x123456 && !env->thumb)
1830 || (mask == 0xab && env->thumb))
1831 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1832 env->regs[0] = do_arm_semihosting(env);
1833 return;
1834 }
1835 }
b5ff1b31
FB		 1836 new_mode = ARM_CPU_MODE_SVC;
1837 addr = 0x08;
1838 mask = CPSR_I;
601d70b9 1839 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1840 offset = 0;
1841 break;
06c949e6 1842 case EXCP_BKPT:
9ee6e8bb 1843 /* See if this is a semihosting syscall. */
2ad207d4 1844 if (env->thumb && semihosting_enabled) {
d31dd73e 1845 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1846 if (mask == 0xab
1847 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1848 env->regs[15] += 2;
1849 env->regs[0] = do_arm_semihosting(env);
1850 return;
1851 }
1852 }
81c05daf 1853 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1854 /* Fall through to prefetch abort. */
1855 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1856 new_mode = ARM_CPU_MODE_ABT;
1857 addr = 0x0c;
1858 mask = CPSR_A | CPSR_I;
1859 offset = 4;
1860 break;
1861 case EXCP_DATA_ABORT:
1862 new_mode = ARM_CPU_MODE_ABT;
1863 addr = 0x10;
1864 mask = CPSR_A | CPSR_I;
1865 offset = 8;
1866 break;
1867 case EXCP_IRQ:
1868 new_mode = ARM_CPU_MODE_IRQ;
1869 addr = 0x18;
1870 /* Disable IRQ and imprecise data aborts. */
1871 mask = CPSR_A | CPSR_I;
1872 offset = 4;
1873 break;
1874 case EXCP_FIQ:
1875 new_mode = ARM_CPU_MODE_FIQ;
1876 addr = 0x1c;
1877 /* Disable FIQ, IRQ and imprecise data aborts. */
1878 mask = CPSR_A | CPSR_I | CPSR_F;
1879 offset = 4;
1880 break;
1881 default:
1882 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1883 return; /* Never happens. Keep compiler happy. */
1884 }
1885 /* High vectors. */
1886 if (env->cp15.c1_sys & (1 << 13)) {
1887 addr += 0xffff0000;
1888 }
1889 switch_mode (env, new_mode);
1890 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1891 /* Clear IT bits. */
1892 env->condexec_bits = 0;
30a8cac1 1893 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1894 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1895 env->uncached_cpsr |= mask;
be5e7a76
DES		 1896 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1897 * and we should just guard the thumb mode on V4 */
1898 if (arm_feature(env, ARM_FEATURE_V4T)) {
1899 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1900 }
b5ff1b31
FB		 1901 env->regs[14] = env->regs[15] + offset;
1902 env->regs[15] = addr;
1903 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1904}
1905
1906/* Check section/page access permissions.
1907 Returns the page protection flags, or zero if the access is not
1908 permitted. */
0ecb72a5 1909static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1910 int access_type, int is_user)
b5ff1b31 1911{
9ee6e8bb
PB		 1912 int prot_ro;
1913
dd4ebc2e 1914 if (domain_prot == 3) {
b5ff1b31 1915 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1916 }
b5ff1b31 1917
9ee6e8bb
PB		 1918 if (access_type == 1)
1919 prot_ro = 0;
1920 else
1921 prot_ro = PAGE_READ;
1922
b5ff1b31
FB		 1923 switch (ap) {
1924 case 0:
78600320 1925 if (access_type == 1)
b5ff1b31
FB		 1926 return 0;
1927 switch ((env->cp15.c1_sys >> 8) & 3) {
1928 case 1:
1929 return is_user ? 0 : PAGE_READ;
1930 case 2:
1931 return PAGE_READ;
1932 default:
1933 return 0;
1934 }
1935 case 1:
1936 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1937 case 2:
1938 if (is_user)
9ee6e8bb 1939 return prot_ro;
b5ff1b31
FB		 1940 else
1941 return PAGE_READ | PAGE_WRITE;
1942 case 3:
1943 return PAGE_READ | PAGE_WRITE;
d4934d18 1944 case 4: /* Reserved. */
9ee6e8bb
PB		 1945 return 0;
1946 case 5:
1947 return is_user ? 0 : prot_ro;
1948 case 6:
1949 return prot_ro;
d4934d18 1950 case 7:
0ab06d83 1951 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1952 return 0;
1953 return prot_ro;
b5ff1b31
FB		 1954 default:
1955 abort();
1956 }
1957}
1958
0ecb72a5 1959static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1960{
1961 uint32_t table;
1962
1963 if (address & env->cp15.c2_mask)
1964 table = env->cp15.c2_base1 & 0xffffc000;
1965 else
1966 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1967
1968 table |= (address >> 18) & 0x3ffc;
1969 return table;
1970}
1971
0ecb72a5 1972static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 1973 int is_user, hwaddr *phys_ptr,
77a71dd1 1974 int *prot, target_ulong *page_size)
b5ff1b31
FB		 1975{
1976 int code;
1977 uint32_t table;
1978 uint32_t desc;
1979 int type;
1980 int ap;
1981 int domain;
dd4ebc2e 1982 int domain_prot;
a8170e5e 1983 hwaddr phys_addr;
b5ff1b31 1984
9ee6e8bb
PB		 1985 /* Pagetable walk. */
1986 /* Lookup l1 descriptor. */
b2fa1797 1987 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1988 desc = ldl_phys(table);
1989 type = (desc & 3);
dd4ebc2e
JCD		 1990 domain = (desc >> 5) & 0x0f;
1991 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1992 if (type == 0) {
601d70b9 1993 /* Section translation fault. */
9ee6e8bb
PB		 1994 code = 5;
1995 goto do_fault;
1996 }
dd4ebc2e 1997 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1998 if (type == 2)
1999 code = 9; /* Section domain fault. */
2000 else
2001 code = 11; /* Page domain fault. */
2002 goto do_fault;
2003 }
2004 if (type == 2) {
2005 /* 1Mb section. */
2006 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2007 ap = (desc >> 10) & 3;
2008 code = 13;
d4c430a8 2009 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2010 } else {
2011 /* Lookup l2 entry. */
2012 if (type == 1) {
2013 /* Coarse pagetable. */
2014 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2015 } else {
2016 /* Fine pagetable. */
2017 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2018 }
2019 desc = ldl_phys(table);
2020 switch (desc & 3) {
2021 case 0: /* Page translation fault. */
2022 code = 7;
2023 goto do_fault;
2024 case 1: /* 64k page. */
2025 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2026 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2027 *page_size = 0x10000;
ce819861 2028 break;
9ee6e8bb
PB		 2029 case 2: /* 4k page. */
2030 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2031 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2032 *page_size = 0x1000;
ce819861 2033 break;
9ee6e8bb
PB		 2034 case 3: /* 1k page. */
2035 if (type == 1) {
2036 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2037 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2038 } else {
2039 /* Page translation fault. */
2040 code = 7;
2041 goto do_fault;
2042 }
2043 } else {
2044 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2045 }
2046 ap = (desc >> 4) & 3;
d4c430a8 2047 *page_size = 0x400;
ce819861
PB		 2048 break;
2049 default:
9ee6e8bb
PB		 2050 /* Never happens, but compiler isn't smart enough to tell. */
2051 abort();
ce819861 2052 }
9ee6e8bb
PB		 2053 code = 15;
2054 }
dd4ebc2e 2055 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2056 if (!*prot) {
2057 /* Access permission fault. */
2058 goto do_fault;
2059 }
3ad493fc 2060 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2061 *phys_ptr = phys_addr;
2062 return 0;
2063do_fault:
2064 return code | (domain << 4);
2065}
2066
0ecb72a5 2067static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2068 int is_user, hwaddr *phys_ptr,
77a71dd1 2069 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2070{
2071 int code;
2072 uint32_t table;
2073 uint32_t desc;
2074 uint32_t xn;
de9b05b8 2075 uint32_t pxn = 0;
9ee6e8bb
PB		 2076 int type;
2077 int ap;
de9b05b8 2078 int domain = 0;
dd4ebc2e 2079 int domain_prot;
a8170e5e 2080 hwaddr phys_addr;
9ee6e8bb
PB		 2081
2082 /* Pagetable walk. */
2083 /* Lookup l1 descriptor. */
b2fa1797 2084 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2085 desc = ldl_phys(table);
2086 type = (desc & 3);
de9b05b8
PM		 2087 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2088 /* Section translation fault, or attempt to use the encoding
2089 * which is Reserved on implementations without PXN.
2090 */
9ee6e8bb 2091 code = 5;
9ee6e8bb 2092 goto do_fault;
de9b05b8
PM		 2093 }
2094 if ((type == 1) || !(desc & (1 << 18))) {
2095 /* Page or Section. */
dd4ebc2e 2096 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2097 }
dd4ebc2e
JCD		 2098 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2099 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2100 if (type != 1) {
9ee6e8bb 2101 code = 9; /* Section domain fault. */
de9b05b8 2102 } else {
9ee6e8bb 2103 code = 11; /* Page domain fault. */
de9b05b8 2104 }
9ee6e8bb
PB		 2105 goto do_fault;
2106 }
de9b05b8 2107 if (type != 1) {
9ee6e8bb
PB		 2108 if (desc & (1 << 18)) {
2109 /* Supersection. */
2110 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2111 *page_size = 0x1000000;
b5ff1b31 2112 } else {
9ee6e8bb
PB		 2113 /* Section. */
2114 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2115 *page_size = 0x100000;
b5ff1b31 2116 }
9ee6e8bb
PB		 2117 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2118 xn = desc & (1 << 4);
de9b05b8 2119 pxn = desc & 1;
9ee6e8bb
PB		 2120 code = 13;
2121 } else {
de9b05b8
PM		 2122 if (arm_feature(env, ARM_FEATURE_PXN)) {
2123 pxn = (desc >> 2) & 1;
2124 }
9ee6e8bb
PB		 2125 /* Lookup l2 entry. */
2126 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2127 desc = ldl_phys(table);
2128 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2129 switch (desc & 3) {
2130 case 0: /* Page translation fault. */
2131 code = 7;
b5ff1b31 2132 goto do_fault;
9ee6e8bb
PB		 2133 case 1: /* 64k page. */
2134 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2135 xn = desc & (1 << 15);
d4c430a8 2136 *page_size = 0x10000;
9ee6e8bb
PB		 2137 break;
2138 case 2: case 3: /* 4k page. */
2139 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2140 xn = desc & 1;
d4c430a8 2141 *page_size = 0x1000;
9ee6e8bb
PB		 2142 break;
2143 default:
2144 /* Never happens, but compiler isn't smart enough to tell. */
2145 abort();
b5ff1b31 2146 }
9ee6e8bb
PB		 2147 code = 15;
2148 }
dd4ebc2e 2149 if (domain_prot == 3) {
c0034328
JR		 2150 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2151 } else {
de9b05b8
PM		 2152 if (pxn && !is_user) {
2153 xn = 1;
2154 }
c0034328
JR		 2155 if (xn && access_type == 2)
2156 goto do_fault;
9ee6e8bb 2157
c0034328
JR		 2158 /* The simplified model uses AP[0] as an access control bit. */
2159 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2160 /* Access flag fault. */
2161 code = (code == 15) ? 6 : 3;
2162 goto do_fault;
2163 }
dd4ebc2e 2164 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2165 if (!*prot) {
2166 /* Access permission fault. */
2167 goto do_fault;
2168 }
2169 if (!xn) {
2170 *prot |= PAGE_EXEC;
2171 }
3ad493fc 2172 }
9ee6e8bb 2173 *phys_ptr = phys_addr;
b5ff1b31
FB		 2174 return 0;
2175do_fault:
2176 return code | (domain << 4);
2177}
2178
3dde962f
PM		 2179/* Fault type for long-descriptor MMU fault reporting; this corresponds
2180 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2181 */
2182typedef enum {
2183 translation_fault = 1,
2184 access_fault = 2,
2185 permission_fault = 3,
2186} MMUFaultType;
2187
2188static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2189 int access_type, int is_user,
a8170e5e 2190 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 2191 target_ulong *page_size_ptr)
2192{
2193 /* Read an LPAE long-descriptor translation table. */
2194 MMUFaultType fault_type = translation_fault;
2195 uint32_t level = 1;
2196 uint32_t epd;
2197 uint32_t tsz;
2198 uint64_t ttbr;
2199 int ttbr_select;
2200 int n;
a8170e5e 2201 hwaddr descaddr;
3dde962f
PM		 2202 uint32_t tableattrs;
2203 target_ulong page_size;
2204 uint32_t attrs;
2205
2206 /* Determine whether this address is in the region controlled by
2207 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2208 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2209 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2210 */
2211 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2212 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2213 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2214 /* there is a ttbr0 region and we are in it (high bits all zero) */
2215 ttbr_select = 0;
2216 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2217 /* there is a ttbr1 region and we are in it (high bits all one) */
2218 ttbr_select = 1;
2219 } else if (!t0sz) {
2220 /* ttbr0 region is "everything not in the ttbr1 region" */
2221 ttbr_select = 0;
2222 } else if (!t1sz) {
2223 /* ttbr1 region is "everything not in the ttbr0 region" */
2224 ttbr_select = 1;
2225 } else {
2226 /* in the gap between the two regions, this is a Translation fault */
2227 fault_type = translation_fault;
2228 goto do_fault;
2229 }
2230
2231 /* Note that QEMU ignores shareability and cacheability attributes,
2232 * so we don't need to do anything with the SH, ORGN, IRGN fields
2233 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2234 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2235 * implement any ASID-like capability so we can ignore it (instead
2236 * we will always flush the TLB any time the ASID is changed).
2237 */
2238 if (ttbr_select == 0) {
2239 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2240 epd = extract32(env->cp15.c2_control, 7, 1);
2241 tsz = t0sz;
2242 } else {
2243 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2244 epd = extract32(env->cp15.c2_control, 23, 1);
2245 tsz = t1sz;
2246 }
2247
2248 if (epd) {
2249 /* Translation table walk disabled => Translation fault on TLB miss */
2250 goto do_fault;
2251 }
2252
2253 /* If the region is small enough we will skip straight to a 2nd level
2254 * lookup. This affects the number of bits of the address used in
2255 * combination with the TTBR to find the first descriptor. ('n' here
2256 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2257 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2258 */
2259 if (tsz > 1) {
2260 level = 2;
2261 n = 14 - tsz;
2262 } else {
2263 n = 5 - tsz;
2264 }
2265
2266 /* Clear the vaddr bits which aren't part of the within-region address,
2267 * so that we don't have to special case things when calculating the
2268 * first descriptor address.
2269 */
2270 address &= (0xffffffffU >> tsz);
2271
2272 /* Now we can extract the actual base address from the TTBR */
2273 descaddr = extract64(ttbr, 0, 40);
2274 descaddr &= ~((1ULL << n) - 1);
2275
2276 tableattrs = 0;
2277 for (;;) {
2278 uint64_t descriptor;
2279
2280 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2281 descriptor = ldq_phys(descaddr);
2282 if (!(descriptor & 1) ||
2283 (!(descriptor & 2) && (level == 3))) {
2284 /* Invalid, or the Reserved level 3 encoding */
2285 goto do_fault;
2286 }
2287 descaddr = descriptor & 0xfffffff000ULL;
2288
2289 if ((descriptor & 2) && (level < 3)) {
2290 /* Table entry. The top five bits are attributes which may
2291 * propagate down through lower levels of the table (and
2292 * which are all arranged so that 0 means "no effect", so
2293 * we can gather them up by ORing in the bits at each level).
2294 */
2295 tableattrs |= extract64(descriptor, 59, 5);
2296 level++;
2297 continue;
2298 }
2299 /* Block entry at level 1 or 2, or page entry at level 3.
2300 * These are basically the same thing, although the number
2301 * of bits we pull in from the vaddr varies.
2302 */
2303 page_size = (1 << (39 - (9 * level)));
2304 descaddr |= (address & (page_size - 1));
2305 /* Extract attributes from the descriptor and merge with table attrs */
2306 attrs = extract64(descriptor, 2, 10)
2307 | (extract64(descriptor, 52, 12) << 10);
2308 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2309 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2310 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2311 * means "force PL1 access only", which means forcing AP[1] to 0.
2312 */
2313 if (extract32(tableattrs, 2, 1)) {
2314 attrs &= ~(1 << 4);
2315 }
2316 /* Since we're always in the Non-secure state, NSTable is ignored. */
2317 break;
2318 }
2319 /* Here descaddr is the final physical address, and attributes
2320 * are all in attrs.
2321 */
2322 fault_type = access_fault;
2323 if ((attrs & (1 << 8)) == 0) {
2324 /* Access flag */
2325 goto do_fault;
2326 }
2327 fault_type = permission_fault;
2328 if (is_user && !(attrs & (1 << 4))) {
2329 /* Unprivileged access not enabled */
2330 goto do_fault;
2331 }
2332 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2333 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2334 /* XN or PXN */
2335 if (access_type == 2) {
2336 goto do_fault;
2337 }
2338 *prot &= ~PAGE_EXEC;
2339 }
2340 if (attrs & (1 << 5)) {
2341 /* Write access forbidden */
2342 if (access_type == 1) {
2343 goto do_fault;
2344 }
2345 *prot &= ~PAGE_WRITE;
2346 }
2347
2348 *phys_ptr = descaddr;
2349 *page_size_ptr = page_size;
2350 return 0;
2351
2352do_fault:
2353 /* Long-descriptor format IFSR/DFSR value */
2354 return (1 << 9) | (fault_type << 2) | level;
2355}
2356
77a71dd1
PM		 2357static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2358 int access_type, int is_user,
a8170e5e 2359 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 2360{
2361 int n;
2362 uint32_t mask;
2363 uint32_t base;
2364
2365 *phys_ptr = address;
2366 for (n = 7; n >= 0; n--) {
2367 base = env->cp15.c6_region[n];
2368 if ((base & 1) == 0)
2369 continue;
2370 mask = 1 << ((base >> 1) & 0x1f);
2371 /* Keep this shift separate from the above to avoid an
2372 (undefined) << 32. */
2373 mask = (mask << 1) - 1;
2374 if (((base ^ address) & ~mask) == 0)
2375 break;
2376 }
2377 if (n < 0)
2378 return 2;
2379
2380 if (access_type == 2) {
2381 mask = env->cp15.c5_insn;
2382 } else {
2383 mask = env->cp15.c5_data;
2384 }
2385 mask = (mask >> (n * 4)) & 0xf;
2386 switch (mask) {
2387 case 0:
2388 return 1;
2389 case 1:
2390 if (is_user)
2391 return 1;
2392 *prot = PAGE_READ | PAGE_WRITE;
2393 break;
2394 case 2:
2395 *prot = PAGE_READ;
2396 if (!is_user)
2397 *prot |= PAGE_WRITE;
2398 break;
2399 case 3:
2400 *prot = PAGE_READ | PAGE_WRITE;
2401 break;
2402 case 5:
2403 if (is_user)
2404 return 1;
2405 *prot = PAGE_READ;
2406 break;
2407 case 6:
2408 *prot = PAGE_READ;
2409 break;
2410 default:
2411 /* Bad permission. */
2412 return 1;
2413 }
3ad493fc 2414 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2415 return 0;
2416}
2417
702a9357
PM		 2418/* get_phys_addr - get the physical address for this virtual address
2419 *
2420 * Find the physical address corresponding to the given virtual address,
2421 * by doing a translation table walk on MMU based systems or using the
2422 * MPU state on MPU based systems.
2423 *
2424 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2425 * prot and page_size are not filled in, and the return value provides
2426 * information on why the translation aborted, in the format of a
2427 * DFSR/IFSR fault register, with the following caveats:
2428 * * we honour the short vs long DFSR format differences.
2429 * * the WnR bit is never set (the caller must do this).
2430 * * for MPU based systems we don't bother to return a full FSR format
2431 * value.
2432 *
2433 * @env: CPUARMState
2434 * @address: virtual address to get physical address for
2435 * @access_type: 0 for read, 1 for write, 2 for execute
2436 * @is_user: 0 for privileged access, 1 for user
2437 * @phys_ptr: set to the physical address corresponding to the virtual address
2438 * @prot: set to the permissions for the page containing phys_ptr
2439 * @page_size: set to the size of the page containing phys_ptr
2440 */
0ecb72a5 2441static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2442 int access_type, int is_user,
a8170e5e 2443 hwaddr *phys_ptr, int *prot,
d4c430a8 2444 target_ulong *page_size)
9ee6e8bb
PB		 2445{
2446 /* Fast Context Switch Extension. */
2447 if (address < 0x02000000)
2448 address += env->cp15.c13_fcse;
2449
2450 if ((env->cp15.c1_sys & 1) == 0) {
2451 /* MMU/MPU disabled. */
2452 *phys_ptr = address;
3ad493fc 2453 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2454 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2455 return 0;
2456 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2457 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2458 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2459 prot);
3dde962f
PM		 2460 } else if (extended_addresses_enabled(env)) {
2461 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2462 prot, page_size);
9ee6e8bb
PB		 2463 } else if (env->cp15.c1_sys & (1 << 23)) {
2464 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2465 prot, page_size);
9ee6e8bb
PB		 2466 } else {
2467 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2468 prot, page_size);
9ee6e8bb
PB		 2469 }
2470}
2471
0ecb72a5 2472int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2473 int access_type, int mmu_idx)
b5ff1b31 2474{
a8170e5e 2475 hwaddr phys_addr;
d4c430a8 2476 target_ulong page_size;
b5ff1b31 2477 int prot;
6ebbf390 2478 int ret, is_user;
b5ff1b31 2479
6ebbf390 2480 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2481 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2482 &page_size);
b5ff1b31
FB		 2483 if (ret == 0) {
2484 /* Map a single [sub]page. */
a8170e5e 2485 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 2486 address &= ~(uint32_t)0x3ff;
3ad493fc 2487 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2488 return 0;
b5ff1b31
FB		 2489 }
2490
2491 if (access_type == 2) {
2492 env->cp15.c5_insn = ret;
2493 env->cp15.c6_insn = address;
2494 env->exception_index = EXCP_PREFETCH_ABORT;
2495 } else {
2496 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2497 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2498 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2499 env->cp15.c6_data = address;
2500 env->exception_index = EXCP_DATA_ABORT;
2501 }
2502 return 1;
2503}
2504
a8170e5e 2505hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31 2506{
a8170e5e 2507 hwaddr phys_addr;
d4c430a8 2508 target_ulong page_size;
b5ff1b31
FB		 2509 int prot;
2510 int ret;
2511
d4c430a8 2512 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2513
2514 if (ret != 0)
2515 return -1;
2516
2517 return phys_addr;
2518}
2519
0ecb72a5 2520void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2521{
39ea3d4e
PM		 2522 if ((env->uncached_cpsr & CPSR_M) == mode) {
2523 env->regs[13] = val;
2524 } else {
1b9e01c1 2525 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2526 }
9ee6e8bb
PB		 2527}
2528
0ecb72a5 2529uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2530{
39ea3d4e
PM		 2531 if ((env->uncached_cpsr & CPSR_M) == mode) {
2532 return env->regs[13];
2533 } else {
1b9e01c1 2534 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2535 }
9ee6e8bb
PB		 2536}
2537
0ecb72a5 2538uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2539{
2540 switch (reg) {
2541 case 0: /* APSR */
2542 return xpsr_read(env) & 0xf8000000;
2543 case 1: /* IAPSR */
2544 return xpsr_read(env) & 0xf80001ff;
2545 case 2: /* EAPSR */
2546 return xpsr_read(env) & 0xff00fc00;
2547 case 3: /* xPSR */
2548 return xpsr_read(env) & 0xff00fdff;
2549 case 5: /* IPSR */
2550 return xpsr_read(env) & 0x000001ff;
2551 case 6: /* EPSR */
2552 return xpsr_read(env) & 0x0700fc00;
2553 case 7: /* IEPSR */
2554 return xpsr_read(env) & 0x0700edff;
2555 case 8: /* MSP */
2556 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2557 case 9: /* PSP */
2558 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2559 case 16: /* PRIMASK */
2560 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2561 case 17: /* BASEPRI */
2562 case 18: /* BASEPRI_MAX */
9ee6e8bb 2563 return env->v7m.basepri;
82845826
SH		 2564 case 19: /* FAULTMASK */
2565 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2566 case 20: /* CONTROL */
2567 return env->v7m.control;
2568 default:
2569 /* ??? For debugging only. */
2570 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2571 return 0;
2572 }
2573}
2574
0ecb72a5 2575void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2576{
2577 switch (reg) {
2578 case 0: /* APSR */
2579 xpsr_write(env, val, 0xf8000000);
2580 break;
2581 case 1: /* IAPSR */
2582 xpsr_write(env, val, 0xf8000000);
2583 break;
2584 case 2: /* EAPSR */
2585 xpsr_write(env, val, 0xfe00fc00);
2586 break;
2587 case 3: /* xPSR */
2588 xpsr_write(env, val, 0xfe00fc00);
2589 break;
2590 case 5: /* IPSR */
2591 /* IPSR bits are readonly. */
2592 break;
2593 case 6: /* EPSR */
2594 xpsr_write(env, val, 0x0600fc00);
2595 break;
2596 case 7: /* IEPSR */
2597 xpsr_write(env, val, 0x0600fc00);
2598 break;
2599 case 8: /* MSP */
2600 if (env->v7m.current_sp)
2601 env->v7m.other_sp = val;
2602 else
2603 env->regs[13] = val;
2604 break;
2605 case 9: /* PSP */
2606 if (env->v7m.current_sp)
2607 env->regs[13] = val;
2608 else
2609 env->v7m.other_sp = val;
2610 break;
2611 case 16: /* PRIMASK */
2612 if (val & 1)
2613 env->uncached_cpsr |= CPSR_I;
2614 else
2615 env->uncached_cpsr &= ~CPSR_I;
2616 break;
82845826 2617 case 17: /* BASEPRI */
9ee6e8bb
PB		 2618 env->v7m.basepri = val & 0xff;
2619 break;
82845826 2620 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2621 val &= 0xff;
2622 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2623 env->v7m.basepri = val;
2624 break;
82845826
SH		 2625 case 19: /* FAULTMASK */
2626 if (val & 1)
2627 env->uncached_cpsr |= CPSR_F;
2628 else
2629 env->uncached_cpsr &= ~CPSR_F;
2630 break;
9ee6e8bb
PB		 2631 case 20: /* CONTROL */
2632 env->v7m.control = val & 3;
2633 switch_v7m_sp(env, (val & 2) != 0);
2634 break;
2635 default:
2636 /* ??? For debugging only. */
2637 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2638 return;
2639 }
2640}
2641
b5ff1b31 2642#endif
6ddbc6e4
PB		 2643
2644/* Note that signed overflow is undefined in C. The following routines are
2645 careful to use unsigned types where modulo arithmetic is required.
2646 Failure to do so _will_ break on newer gcc. */
2647
2648/* Signed saturating arithmetic. */
2649
1654b2d6 2650/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2651static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2652{
2653 uint16_t res;
2654
2655 res = a + b;
2656 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2657 if (a & 0x8000)
2658 res = 0x8000;
2659 else
2660 res = 0x7fff;
2661 }
2662 return res;
2663}
2664
1654b2d6 2665/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2666static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2667{
2668 uint8_t res;
2669
2670 res = a + b;
2671 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2672 if (a & 0x80)
2673 res = 0x80;
2674 else
2675 res = 0x7f;
2676 }
2677 return res;
2678}
2679
1654b2d6 2680/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2681static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2682{
2683 uint16_t res;
2684
2685 res = a - b;
2686 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2687 if (a & 0x8000)
2688 res = 0x8000;
2689 else
2690 res = 0x7fff;
2691 }
2692 return res;
2693}
2694
1654b2d6 2695/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2696static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2697{
2698 uint8_t res;
2699
2700 res = a - b;
2701 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2702 if (a & 0x80)
2703 res = 0x80;
2704 else
2705 res = 0x7f;
2706 }
2707 return res;
2708}
2709
2710#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2711#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2712#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2713#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2714#define PFX q
2715
2716#include "op_addsub.h"
2717
2718/* Unsigned saturating arithmetic. */
460a09c1 2719static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2720{
2721 uint16_t res;
2722 res = a + b;
2723 if (res < a)
2724 res = 0xffff;
2725 return res;
2726}
2727
460a09c1 2728static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2729{
4c4fd3f8 2730 if (a > b)
6ddbc6e4
PB		 2731 return a - b;
2732 else
2733 return 0;
2734}
2735
2736static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2737{
2738 uint8_t res;
2739 res = a + b;
2740 if (res < a)
2741 res = 0xff;
2742 return res;
2743}
2744
2745static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2746{
4c4fd3f8 2747 if (a > b)
6ddbc6e4
PB		 2748 return a - b;
2749 else
2750 return 0;
2751}
2752
2753#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2754#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2755#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2756#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2757#define PFX uq
2758
2759#include "op_addsub.h"
2760
2761/* Signed modulo arithmetic. */
2762#define SARITH16(a, b, n, op) do { \
2763 int32_t sum; \
db6e2e65 2764 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2765 RESULT(sum, n, 16); \
2766 if (sum >= 0) \
2767 ge |= 3 << (n * 2); \
2768 } while(0)
2769
2770#define SARITH8(a, b, n, op) do { \
2771 int32_t sum; \
db6e2e65 2772 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2773 RESULT(sum, n, 8); \
2774 if (sum >= 0) \
2775 ge |= 1 << n; \
2776 } while(0)
2777
2778
2779#define ADD16(a, b, n) SARITH16(a, b, n, +)
2780#define SUB16(a, b, n) SARITH16(a, b, n, -)
2781#define ADD8(a, b, n) SARITH8(a, b, n, +)
2782#define SUB8(a, b, n) SARITH8(a, b, n, -)
2783#define PFX s
2784#define ARITH_GE
2785
2786#include "op_addsub.h"
2787
2788/* Unsigned modulo arithmetic. */
2789#define ADD16(a, b, n) do { \
2790 uint32_t sum; \
2791 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2792 RESULT(sum, n, 16); \
a87aa10b 2793 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2794 ge |= 3 << (n * 2); \
2795 } while(0)
2796
2797#define ADD8(a, b, n) do { \
2798 uint32_t sum; \
2799 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2800 RESULT(sum, n, 8); \
a87aa10b
AZ		 2801 if ((sum >> 8) == 1) \
2802 ge |= 1 << n; \
6ddbc6e4
PB		 2803 } while(0)
2804
2805#define SUB16(a, b, n) do { \
2806 uint32_t sum; \
2807 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2808 RESULT(sum, n, 16); \
2809 if ((sum >> 16) == 0) \
2810 ge |= 3 << (n * 2); \
2811 } while(0)
2812
2813#define SUB8(a, b, n) do { \
2814 uint32_t sum; \
2815 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2816 RESULT(sum, n, 8); \
2817 if ((sum >> 8) == 0) \
a87aa10b 2818 ge |= 1 << n; \
6ddbc6e4
PB		 2819 } while(0)
2820
2821#define PFX u
2822#define ARITH_GE
2823
2824#include "op_addsub.h"
2825
2826/* Halved signed arithmetic. */
2827#define ADD16(a, b, n) \
2828 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2829#define SUB16(a, b, n) \
2830 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2831#define ADD8(a, b, n) \
2832 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2833#define SUB8(a, b, n) \
2834 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2835#define PFX sh
2836
2837#include "op_addsub.h"
2838
2839/* Halved unsigned arithmetic. */
2840#define ADD16(a, b, n) \
2841 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2842#define SUB16(a, b, n) \
2843 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2844#define ADD8(a, b, n) \
2845 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2846#define SUB8(a, b, n) \
2847 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2848#define PFX uh
2849
2850#include "op_addsub.h"
2851
2852static inline uint8_t do_usad(uint8_t a, uint8_t b)
2853{
2854 if (a > b)
2855 return a - b;
2856 else
2857 return b - a;
2858}
2859
2860/* Unsigned sum of absolute byte differences. */
2861uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2862{
2863 uint32_t sum;
2864 sum = do_usad(a, b);
2865 sum += do_usad(a >> 8, b >> 8);
2866 sum += do_usad(a >> 16, b >>16);
2867 sum += do_usad(a >> 24, b >> 24);
2868 return sum;
2869}
2870
2871/* For ARMv6 SEL instruction. */
2872uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2873{
2874 uint32_t mask;
2875
2876 mask = 0;
2877 if (flags & 1)
2878 mask |= 0xff;
2879 if (flags & 2)
2880 mask |= 0xff00;
2881 if (flags & 4)
2882 mask |= 0xff0000;
2883 if (flags & 8)
2884 mask |= 0xff000000;
2885 return (a & mask) | (b & ~mask);
2886}
2887
5e3f878a
PB		 2888uint32_t HELPER(logicq_cc)(uint64_t val)
2889{
2890 return (val >> 32) | (val != 0);
2891}
4373f3ce 2892
b90372ad
PM		 2893/* VFP support. We follow the convention used for VFP instructions:
2894 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 2895 "d" suffix. */
2896
2897/* Convert host exception flags to vfp form. */
2898static inline int vfp_exceptbits_from_host(int host_bits)
2899{
2900 int target_bits = 0;
2901
2902 if (host_bits & float_flag_invalid)
2903 target_bits |= 1;
2904 if (host_bits & float_flag_divbyzero)
2905 target_bits |= 2;
2906 if (host_bits & float_flag_overflow)
2907 target_bits |= 4;
36802b6b 2908 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2909 target_bits |= 8;
2910 if (host_bits & float_flag_inexact)
2911 target_bits |= 0x10;
cecd8504
PM		 2912 if (host_bits & float_flag_input_denormal)
2913 target_bits |= 0x80;
4373f3ce
PB		 2914 return target_bits;
2915}
2916
0ecb72a5 2917uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2918{
2919 int i;
2920 uint32_t fpscr;
2921
2922 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2923 | (env->vfp.vec_len << 16)
2924 | (env->vfp.vec_stride << 20);
2925 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2926 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2927 fpscr |= vfp_exceptbits_from_host(i);
2928 return fpscr;
2929}
2930
0ecb72a5 2931uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2932{
2933 return HELPER(vfp_get_fpscr)(env);
2934}
2935
4373f3ce
PB		 2936/* Convert vfp exception flags to target form. */
2937static inline int vfp_exceptbits_to_host(int target_bits)
2938{
2939 int host_bits = 0;
2940
2941 if (target_bits & 1)
2942 host_bits |= float_flag_invalid;
2943 if (target_bits & 2)
2944 host_bits |= float_flag_divbyzero;
2945 if (target_bits & 4)
2946 host_bits |= float_flag_overflow;
2947 if (target_bits & 8)
2948 host_bits |= float_flag_underflow;
2949 if (target_bits & 0x10)
2950 host_bits |= float_flag_inexact;
cecd8504
PM		 2951 if (target_bits & 0x80)
2952 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2953 return host_bits;
2954}
2955
0ecb72a5 2956void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2957{
2958 int i;
2959 uint32_t changed;
2960
2961 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2962 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2963 env->vfp.vec_len = (val >> 16) & 7;
2964 env->vfp.vec_stride = (val >> 20) & 3;
2965
2966 changed ^= val;
2967 if (changed & (3 << 22)) {
2968 i = (val >> 22) & 3;
2969 switch (i) {
2970 case 0:
2971 i = float_round_nearest_even;
2972 break;
2973 case 1:
2974 i = float_round_up;
2975 break;
2976 case 2:
2977 i = float_round_down;
2978 break;
2979 case 3:
2980 i = float_round_to_zero;
2981 break;
2982 }
2983 set_float_rounding_mode(i, &env->vfp.fp_status);
2984 }
cecd8504 2985 if (changed & (1 << 24)) {
fe76d976 2986 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2987 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2988 }
5c7908ed
PB		 2989 if (changed & (1 << 25))
2990 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2991
b12c390b 2992 i = vfp_exceptbits_to_host(val);
4373f3ce 2993 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2994 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2995}
2996
0ecb72a5 2997void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2998{
2999 HELPER(vfp_set_fpscr)(env, val);
3000}
3001
4373f3ce
PB		 3002#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3003
3004#define VFP_BINOP(name) \
ae1857ec 3005float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3006{ \
ae1857ec
PM		 3007 float_status *fpst = fpstp; \
3008 return float32_ ## name(a, b, fpst); \
4373f3ce 3009} \
ae1857ec 3010float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3011{ \
ae1857ec
PM		 3012 float_status *fpst = fpstp; \
3013 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3014}
3015VFP_BINOP(add)
3016VFP_BINOP(sub)
3017VFP_BINOP(mul)
3018VFP_BINOP(div)
3019#undef VFP_BINOP
3020
3021float32 VFP_HELPER(neg, s)(float32 a)
3022{
3023 return float32_chs(a);
3024}
3025
3026float64 VFP_HELPER(neg, d)(float64 a)
3027{
66230e0d 3028 return float64_chs(a);
4373f3ce
PB		 3029}
3030
3031float32 VFP_HELPER(abs, s)(float32 a)
3032{
3033 return float32_abs(a);
3034}
3035
3036float64 VFP_HELPER(abs, d)(float64 a)
3037{
66230e0d 3038 return float64_abs(a);
4373f3ce
PB		 3039}
3040
0ecb72a5 3041float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3042{
3043 return float32_sqrt(a, &env->vfp.fp_status);
3044}
3045
0ecb72a5 3046float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3047{
3048 return float64_sqrt(a, &env->vfp.fp_status);
3049}
3050
3051/* XXX: check quiet/signaling case */
3052#define DO_VFP_cmp(p, type) \
0ecb72a5 3053void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3054{ \
3055 uint32_t flags; \
3056 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3057 case 0: flags = 0x6; break; \
3058 case -1: flags = 0x8; break; \
3059 case 1: flags = 0x2; break; \
3060 default: case 2: flags = 0x3; break; \
3061 } \
3062 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3063 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3064} \
0ecb72a5 3065void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3066{ \
3067 uint32_t flags; \
3068 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3069 case 0: flags = 0x6; break; \
3070 case -1: flags = 0x8; break; \
3071 case 1: flags = 0x2; break; \
3072 default: case 2: flags = 0x3; break; \
3073 } \
3074 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3075 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3076}
3077DO_VFP_cmp(s, float32)
3078DO_VFP_cmp(d, float64)
3079#undef DO_VFP_cmp
3080
5500b06c 3081/* Integer to float and float to integer conversions */
4373f3ce 3082
5500b06c
PM		 3083#define CONV_ITOF(name, fsz, sign) \
3084 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3085{ \
3086 float_status *fpst = fpstp; \
85836979 3087 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3088}
3089
5500b06c
PM		 3090#define CONV_FTOI(name, fsz, sign, round) \
3091uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3092{ \
3093 float_status *fpst = fpstp; \
3094 if (float##fsz##_is_any_nan(x)) { \
3095 float_raise(float_flag_invalid, fpst); \
3096 return 0; \
3097 } \
3098 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3099}
3100
5500b06c
PM		 3101#define FLOAT_CONVS(name, p, fsz, sign) \
3102CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3103CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3104CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3105
5500b06c
PM		 3106FLOAT_CONVS(si, s, 32, )
3107FLOAT_CONVS(si, d, 64, )
3108FLOAT_CONVS(ui, s, 32, u)
3109FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3110
5500b06c
PM		 3111#undef CONV_ITOF
3112#undef CONV_FTOI
3113#undef FLOAT_CONVS
4373f3ce
PB		 3114
3115/* floating point conversion */
0ecb72a5 3116float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3117{
2d627737
PM		 3118 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3119 /* ARM requires that S<->D conversion of any kind of NaN generates
3120 * a quiet NaN by forcing the most significant frac bit to 1.
3121 */
3122 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3123}
3124
0ecb72a5 3125float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3126{
2d627737
PM		 3127 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3128 /* ARM requires that S<->D conversion of any kind of NaN generates
3129 * a quiet NaN by forcing the most significant frac bit to 1.
3130 */
3131 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3132}
3133
3134/* VFP3 fixed point conversion. */
622465e1 3135#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 3136float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3137 void *fpstp) \
4373f3ce 3138{ \
5500b06c 3139 float_status *fpst = fpstp; \
622465e1 3140 float##fsz tmp; \
5500b06c
PM		 3141 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3142 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 3143} \
5500b06c
PM		 3144uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3145 void *fpstp) \
4373f3ce 3146{ \
5500b06c 3147 float_status *fpst = fpstp; \
622465e1
PM		 3148 float##fsz tmp; \
3149 if (float##fsz##_is_any_nan(x)) { \
5500b06c 3150 float_raise(float_flag_invalid, fpst); \
622465e1 3151 return 0; \
09d9487f 3152 } \
5500b06c
PM		 3153 tmp = float##fsz##_scalbn(x, shift, fpst); \
3154 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 3155}
3156
3157VFP_CONV_FIX(sh, d, 64, int16, )
3158VFP_CONV_FIX(sl, d, 64, int32, )
3159VFP_CONV_FIX(uh, d, 64, uint16, u)
3160VFP_CONV_FIX(ul, d, 64, uint32, u)
3161VFP_CONV_FIX(sh, s, 32, int16, )
3162VFP_CONV_FIX(sl, s, 32, int32, )
3163VFP_CONV_FIX(uh, s, 32, uint16, u)
3164VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 3165#undef VFP_CONV_FIX
3166
60011498 3167/* Half precision conversions. */
0ecb72a5 3168static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 3169{
60011498 3170 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3171 float32 r = float16_to_float32(make_float16(a), ieee, s);
3172 if (ieee) {
3173 return float32_maybe_silence_nan(r);
3174 }
3175 return r;
60011498
PB		 3176}
3177
0ecb72a5 3178static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 3179{
60011498 3180 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3181 float16 r = float32_to_float16(a, ieee, s);
3182 if (ieee) {
3183 r = float16_maybe_silence_nan(r);
3184 }
3185 return float16_val(r);
60011498
PB		 3186}
3187
0ecb72a5 3188float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3189{
3190 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3191}
3192
0ecb72a5 3193uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3194{
3195 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3196}
3197
0ecb72a5 3198float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3199{
3200 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3201}
3202
0ecb72a5 3203uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3204{
3205 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3206}
3207
dda3ec49 3208#define float32_two make_float32(0x40000000)
6aae3df1
PM		 3209#define float32_three make_float32(0x40400000)
3210#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 3211
0ecb72a5 3212float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3213{
dda3ec49
PM		 3214 float_status *s = &env->vfp.standard_fp_status;
3215 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3216 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3217 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3218 float_raise(float_flag_input_denormal, s);
3219 }
dda3ec49
PM		 3220 return float32_two;
3221 }
3222 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 3223}
3224
0ecb72a5 3225float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3226{
71826966 3227 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 3228 float32 product;
3229 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3230 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3231 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3232 float_raise(float_flag_input_denormal, s);
3233 }
6aae3df1 3234 return float32_one_point_five;
9ea62f57 3235 }
6aae3df1
PM		 3236 product = float32_mul(a, b, s);
3237 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 3238}
3239
8f8e3aa4
PB		 3240/* NEON helpers. */
3241
56bf4fe2
CL		 3242/* Constants 256 and 512 are used in some helpers; we avoid relying on
3243 * int->float conversions at run-time. */
3244#define float64_256 make_float64(0x4070000000000000LL)
3245#define float64_512 make_float64(0x4080000000000000LL)
3246
fe0e4872
CL		 3247/* The algorithm that must be used to calculate the estimate
3248 * is specified by the ARM ARM.
3249 */
0ecb72a5 3250static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 3251{
1146a817
PM		 3252 /* These calculations mustn't set any fp exception flags,
3253 * so we use a local copy of the fp_status.
3254 */
3255 float_status dummy_status = env->vfp.standard_fp_status;
3256 float_status *s = &dummy_status;
fe0e4872
CL		 3257 /* q = (int)(a * 512.0) */
3258 float64 q = float64_mul(float64_512, a, s);
3259 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3260
3261 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3262 q = int64_to_float64(q_int, s);
3263 q = float64_add(q, float64_half, s);
3264 q = float64_div(q, float64_512, s);
3265 q = float64_div(float64_one, q, s);
3266
3267 /* s = (int)(256.0 * r + 0.5) */
3268 q = float64_mul(q, float64_256, s);
3269 q = float64_add(q, float64_half, s);
3270 q_int = float64_to_int64_round_to_zero(q, s);
3271
3272 /* return (double)s / 256.0 */
3273 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3274}
3275
0ecb72a5 3276float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 3277{
fe0e4872
CL		 3278 float_status *s = &env->vfp.standard_fp_status;
3279 float64 f64;
3280 uint32_t val32 = float32_val(a);
3281
3282 int result_exp;
3283 int a_exp = (val32 & 0x7f800000) >> 23;
3284 int sign = val32 & 0x80000000;
3285
3286 if (float32_is_any_nan(a)) {
3287 if (float32_is_signaling_nan(a)) {
3288 float_raise(float_flag_invalid, s);
3289 }
3290 return float32_default_nan;
3291 } else if (float32_is_infinity(a)) {
3292 return float32_set_sign(float32_zero, float32_is_neg(a));
3293 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3294 if (!float32_is_zero(a)) {
3295 float_raise(float_flag_input_denormal, s);
3296 }
fe0e4872
CL		 3297 float_raise(float_flag_divbyzero, s);
3298 return float32_set_sign(float32_infinity, float32_is_neg(a));
3299 } else if (a_exp >= 253) {
3300 float_raise(float_flag_underflow, s);
3301 return float32_set_sign(float32_zero, float32_is_neg(a));
3302 }
3303
3304 f64 = make_float64((0x3feULL << 52)
3305 | ((int64_t)(val32 & 0x7fffff) << 29));
3306
3307 result_exp = 253 - a_exp;
3308
3309 f64 = recip_estimate(f64, env);
3310
3311 val32 = sign
3312 | ((result_exp & 0xff) << 23)
3313 | ((float64_val(f64) >> 29) & 0x7fffff);
3314 return make_float32(val32);
4373f3ce
PB		 3315}
3316
e07be5d2
CL		 3317/* The algorithm that must be used to calculate the estimate
3318 * is specified by the ARM ARM.
3319 */
0ecb72a5 3320static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3321{
1146a817
PM		 3322 /* These calculations mustn't set any fp exception flags,
3323 * so we use a local copy of the fp_status.
3324 */
3325 float_status dummy_status = env->vfp.standard_fp_status;
3326 float_status *s = &dummy_status;
e07be5d2
CL		 3327 float64 q;
3328 int64_t q_int;
3329
3330 if (float64_lt(a, float64_half, s)) {
3331 /* range 0.25 <= a < 0.5 */
3332
3333 /* a in units of 1/512 rounded down */
3334 /* q0 = (int)(a * 512.0); */
3335 q = float64_mul(float64_512, a, s);
3336 q_int = float64_to_int64_round_to_zero(q, s);
3337
3338 /* reciprocal root r */
3339 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3340 q = int64_to_float64(q_int, s);
3341 q = float64_add(q, float64_half, s);
3342 q = float64_div(q, float64_512, s);
3343 q = float64_sqrt(q, s);
3344 q = float64_div(float64_one, q, s);
3345 } else {
3346 /* range 0.5 <= a < 1.0 */
3347
3348 /* a in units of 1/256 rounded down */
3349 /* q1 = (int)(a * 256.0); */
3350 q = float64_mul(float64_256, a, s);
3351 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3352
3353 /* reciprocal root r */
3354 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3355 q = int64_to_float64(q_int, s);
3356 q = float64_add(q, float64_half, s);
3357 q = float64_div(q, float64_256, s);
3358 q = float64_sqrt(q, s);
3359 q = float64_div(float64_one, q, s);
3360 }
3361 /* r in units of 1/256 rounded to nearest */
3362 /* s = (int)(256.0 * r + 0.5); */
3363
3364 q = float64_mul(q, float64_256,s );
3365 q = float64_add(q, float64_half, s);
3366 q_int = float64_to_int64_round_to_zero(q, s);
3367
3368 /* return (double)s / 256.0;*/
3369 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3370}
3371
0ecb72a5 3372float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3373{
e07be5d2
CL		 3374 float_status *s = &env->vfp.standard_fp_status;
3375 int result_exp;
3376 float64 f64;
3377 uint32_t val;
3378 uint64_t val64;
3379
3380 val = float32_val(a);
3381
3382 if (float32_is_any_nan(a)) {
3383 if (float32_is_signaling_nan(a)) {
3384 float_raise(float_flag_invalid, s);
3385 }
3386 return float32_default_nan;
3387 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3388 if (!float32_is_zero(a)) {
3389 float_raise(float_flag_input_denormal, s);
3390 }
e07be5d2
CL		 3391 float_raise(float_flag_divbyzero, s);
3392 return float32_set_sign(float32_infinity, float32_is_neg(a));
3393 } else if (float32_is_neg(a)) {
3394 float_raise(float_flag_invalid, s);
3395 return float32_default_nan;
3396 } else if (float32_is_infinity(a)) {
3397 return float32_zero;
3398 }
3399
3400 /* Normalize to a double-precision value between 0.25 and 1.0,
3401 * preserving the parity of the exponent. */
3402 if ((val & 0x800000) == 0) {
3403 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3404 | (0x3feULL << 52)
3405 | ((uint64_t)(val & 0x7fffff) << 29));
3406 } else {
3407 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3408 | (0x3fdULL << 52)
3409 | ((uint64_t)(val & 0x7fffff) << 29));
3410 }
3411
3412 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3413
3414 f64 = recip_sqrt_estimate(f64, env);
3415
3416 val64 = float64_val(f64);
3417
26cc6abf 3418 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3419 | ((val64 >> 29) & 0x7fffff);
3420 return make_float32(val);
4373f3ce
PB		 3421}
3422
0ecb72a5 3423uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3424{
fe0e4872
CL		 3425 float64 f64;
3426
3427 if ((a & 0x80000000) == 0) {
3428 return 0xffffffff;
3429 }
3430
3431 f64 = make_float64((0x3feULL << 52)
3432 | ((int64_t)(a & 0x7fffffff) << 21));
3433
3434 f64 = recip_estimate (f64, env);
3435
3436 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3437}
3438
0ecb72a5 3439uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3440{
e07be5d2
CL		 3441 float64 f64;
3442
3443 if ((a & 0xc0000000) == 0) {
3444 return 0xffffffff;
3445 }
3446
3447 if (a & 0x80000000) {
3448 f64 = make_float64((0x3feULL << 52)
3449 | ((uint64_t)(a & 0x7fffffff) << 21));
3450 } else { /* bits 31-30 == '01' */
3451 f64 = make_float64((0x3fdULL << 52)
3452 | ((uint64_t)(a & 0x3fffffff) << 22));
3453 }
3454
3455 f64 = recip_sqrt_estimate(f64, env);
3456
3457 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3458}
fe1479c3 3459
da97f52c
PM		 3460/* VFPv4 fused multiply-accumulate */
3461float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3462{
3463 float_status *fpst = fpstp;
3464 return float32_muladd(a, b, c, 0, fpst);
3465}
3466
3467float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3468{
3469 float_status *fpst = fpstp;
3470 return float64_muladd(a, b, c, 0, fpst);
3471}
Qemu copy for testing