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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r |
1e57a462 | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef __ARM_LIB__\r | |
11 | #define __ARM_LIB__\r | |
12 | \r | |
13 | #include <Uefi/UefiBaseType.h>\r | |
14 | \r | |
25402f5d | 15 | #ifdef MDE_CPU_ARM\r |
70119d27 | 16 | #include <Chipset/ArmV7.h>\r |
25402f5d HL |
17 | #elif defined(MDE_CPU_AARCH64)\r |
18 | #include <Chipset/AArch64.h>\r | |
1e57a462 | 19 | #else\r |
25402f5d | 20 | #error "Unknown chipset."\r |
1e57a462 | 21 | #endif\r |
22 | \r | |
e0307a7d AB |
23 | #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r |
24 | EFI_MEMORY_WT | EFI_MEMORY_WB | \\r | |
25 | EFI_MEMORY_UCE)\r | |
26 | \r | |
1e57a462 | 27 | /**\r |
28 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r | |
29 | *\r | |
30 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r | |
31 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r | |
32 | */\r | |
33 | typedef enum {\r | |
34 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r | |
35 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r | |
36 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r | |
37 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r | |
829633e3 PL |
38 | \r |
39 | // On some platforms, memory mapped flash region is designed as not supporting\r | |
40 | // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r | |
41 | // need.\r | |
42 | // Do NOT use below two attributes if you are not sure.\r | |
43 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r | |
44 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r | |
45 | \r | |
1e57a462 | 46 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r |
47 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r | |
48 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r | |
49 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r | |
50 | } ARM_MEMORY_REGION_ATTRIBUTES;\r | |
51 | \r | |
52 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r | |
53 | \r | |
54 | typedef struct {\r | |
55 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r | |
56 | EFI_VIRTUAL_ADDRESS VirtualBase;\r | |
c357fd6a | 57 | UINT64 Length;\r |
1e57a462 | 58 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
59 | } ARM_MEMORY_REGION_DESCRIPTOR;\r | |
60 | \r | |
61 | typedef VOID (*CACHE_OPERATION)(VOID);\r | |
62 | typedef VOID (*LINE_OPERATION)(UINTN);\r | |
63 | \r | |
64 | //\r | |
65 | // ARM Processor Mode\r | |
66 | //\r | |
67 | typedef enum {\r | |
68 | ARM_PROCESSOR_MODE_USER = 0x10,\r | |
69 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r | |
70 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r | |
71 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r | |
72 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r | |
73 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r | |
74 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r | |
75 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r | |
76 | ARM_PROCESSOR_MODE_MASK = 0x1F\r | |
77 | } ARM_PROCESSOR_MODE;\r | |
78 | \r | |
79 | //\r | |
80 | // ARM Cpu IDs\r | |
81 | //\r | |
82 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r | |
83 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r | |
84 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r | |
85 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r | |
86 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r | |
87 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r | |
88 | \r | |
89 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r | |
90 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r | |
91 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r | |
92 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r | |
93 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r | |
94 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r | |
95 | \r | |
96 | //\r | |
97 | // ARM MP Core IDs\r | |
98 | //\r | |
90ed18ca OM |
99 | #define ARM_CORE_AFF0 0xFF\r |
100 | #define ARM_CORE_AFF1 (0xFF << 8)\r | |
101 | #define ARM_CORE_AFF2 (0xFF << 16)\r | |
102 | #define ARM_CORE_AFF3 (0xFFULL << 32)\r | |
103 | \r | |
104 | #define ARM_CORE_MASK ARM_CORE_AFF0\r | |
105 | #define ARM_CLUSTER_MASK ARM_CORE_AFF1\r | |
1e57a462 | 106 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r |
107 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r | |
e359565e | 108 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r |
1e57a462 | 109 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
110 | \r | |
1e57a462 | 111 | UINTN\r |
112 | EFIAPI\r | |
113 | ArmDataCacheLineLength (\r | |
114 | VOID\r | |
115 | );\r | |
3402aac7 | 116 | \r |
1e57a462 | 117 | UINTN\r |
118 | EFIAPI\r | |
119 | ArmInstructionCacheLineLength (\r | |
120 | VOID\r | |
121 | );\r | |
168d7245 | 122 | \r |
c653fc2a AB |
123 | UINTN\r |
124 | EFIAPI\r | |
125 | ArmCacheWritebackGranule (\r | |
126 | VOID\r | |
127 | );\r | |
128 | \r | |
168d7245 OM |
129 | UINTN\r |
130 | EFIAPI\r | |
131 | ArmIsArchTimerImplemented (\r | |
132 | VOID\r | |
133 | );\r | |
134 | \r | |
135 | UINTN\r | |
136 | EFIAPI\r | |
137 | ArmReadIdPfr0 (\r | |
138 | VOID\r | |
139 | );\r | |
140 | \r | |
141 | UINTN\r | |
142 | EFIAPI\r | |
143 | ArmReadIdPfr1 (\r | |
144 | VOID\r | |
145 | );\r | |
146 | \r | |
64751727 | 147 | UINTN\r |
1e57a462 | 148 | EFIAPI\r |
64751727 | 149 | ArmCacheInfo (\r |
1e57a462 | 150 | VOID\r |
151 | );\r | |
152 | \r | |
153 | BOOLEAN\r | |
154 | EFIAPI\r | |
155 | ArmIsMpCore (\r | |
156 | VOID\r | |
157 | );\r | |
158 | \r | |
159 | VOID\r | |
160 | EFIAPI\r | |
161 | ArmInvalidateDataCache (\r | |
162 | VOID\r | |
163 | );\r | |
164 | \r | |
165 | \r | |
166 | VOID\r | |
167 | EFIAPI\r | |
168 | ArmCleanInvalidateDataCache (\r | |
169 | VOID\r | |
170 | );\r | |
171 | \r | |
172 | VOID\r | |
173 | EFIAPI\r | |
174 | ArmCleanDataCache (\r | |
175 | VOID\r | |
176 | );\r | |
177 | \r | |
1e57a462 | 178 | VOID\r |
179 | EFIAPI\r | |
180 | ArmInvalidateInstructionCache (\r | |
181 | VOID\r | |
182 | );\r | |
183 | \r | |
184 | VOID\r | |
185 | EFIAPI\r | |
186 | ArmInvalidateDataCacheEntryByMVA (\r | |
187 | IN UINTN Address\r | |
188 | );\r | |
189 | \r | |
190 | VOID\r | |
191 | EFIAPI\r | |
cf580da1 | 192 | ArmCleanDataCacheEntryToPoUByMVA (\r |
1e57a462 | 193 | IN UINTN Address\r |
194 | );\r | |
195 | \r | |
b7de7e3c EC |
196 | VOID\r |
197 | EFIAPI\r | |
cf580da1 AB |
198 | ArmInvalidateInstructionCacheEntryToPoUByMVA (\r |
199 | IN UINTN Address\r | |
200 | );\r | |
201 | \r | |
202 | VOID\r | |
203 | EFIAPI\r | |
204 | ArmCleanDataCacheEntryByMVA (\r | |
b7de7e3c EC |
205 | IN UINTN Address\r |
206 | );\r | |
207 | \r | |
1e57a462 | 208 | VOID\r |
209 | EFIAPI\r | |
210 | ArmCleanInvalidateDataCacheEntryByMVA (\r | |
211 | IN UINTN Address\r | |
212 | );\r | |
213 | \r | |
214 | VOID\r | |
215 | EFIAPI\r | |
216 | ArmEnableDataCache (\r | |
217 | VOID\r | |
218 | );\r | |
219 | \r | |
220 | VOID\r | |
221 | EFIAPI\r | |
222 | ArmDisableDataCache (\r | |
223 | VOID\r | |
224 | );\r | |
225 | \r | |
226 | VOID\r | |
227 | EFIAPI\r | |
228 | ArmEnableInstructionCache (\r | |
229 | VOID\r | |
230 | );\r | |
231 | \r | |
232 | VOID\r | |
233 | EFIAPI\r | |
234 | ArmDisableInstructionCache (\r | |
235 | VOID\r | |
236 | );\r | |
3402aac7 | 237 | \r |
1e57a462 | 238 | VOID\r |
239 | EFIAPI\r | |
240 | ArmEnableMmu (\r | |
241 | VOID\r | |
242 | );\r | |
243 | \r | |
244 | VOID\r | |
245 | EFIAPI\r | |
246 | ArmDisableMmu (\r | |
247 | VOID\r | |
248 | );\r | |
249 | \r | |
0ff0e414 OM |
250 | VOID\r |
251 | EFIAPI\r | |
252 | ArmEnableCachesAndMmu (\r | |
253 | VOID\r | |
254 | );\r | |
255 | \r | |
1e57a462 | 256 | VOID\r |
257 | EFIAPI\r | |
258 | ArmDisableCachesAndMmu (\r | |
259 | VOID\r | |
260 | );\r | |
261 | \r | |
1e57a462 | 262 | VOID\r |
263 | EFIAPI\r | |
264 | ArmEnableInterrupts (\r | |
265 | VOID\r | |
266 | );\r | |
267 | \r | |
268 | UINTN\r | |
269 | EFIAPI\r | |
270 | ArmDisableInterrupts (\r | |
271 | VOID\r | |
272 | );\r | |
47585ed5 | 273 | \r |
1e57a462 | 274 | BOOLEAN\r |
275 | EFIAPI\r | |
276 | ArmGetInterruptState (\r | |
277 | VOID\r | |
278 | );\r | |
279 | \r | |
0ff0e414 OM |
280 | VOID\r |
281 | EFIAPI\r | |
282 | ArmEnableAsynchronousAbort (\r | |
283 | VOID\r | |
284 | );\r | |
285 | \r | |
47585ed5 | 286 | UINTN\r |
287 | EFIAPI\r | |
0ff0e414 | 288 | ArmDisableAsynchronousAbort (\r |
47585ed5 | 289 | VOID\r |
290 | );\r | |
291 | \r | |
292 | VOID\r | |
293 | EFIAPI\r | |
294 | ArmEnableIrq (\r | |
295 | VOID\r | |
296 | );\r | |
297 | \r | |
0ff0e414 OM |
298 | UINTN\r |
299 | EFIAPI\r | |
300 | ArmDisableIrq (\r | |
301 | VOID\r | |
302 | );\r | |
303 | \r | |
1e57a462 | 304 | VOID\r |
305 | EFIAPI\r | |
306 | ArmEnableFiq (\r | |
307 | VOID\r | |
308 | );\r | |
309 | \r | |
310 | UINTN\r | |
311 | EFIAPI\r | |
312 | ArmDisableFiq (\r | |
313 | VOID\r | |
314 | );\r | |
3402aac7 | 315 | \r |
1e57a462 | 316 | BOOLEAN\r |
317 | EFIAPI\r | |
318 | ArmGetFiqState (\r | |
319 | VOID\r | |
320 | );\r | |
321 | \r | |
8dd618d2 OM |
322 | /**\r |
323 | * Invalidate Data and Instruction TLBs\r | |
324 | */\r | |
1e57a462 | 325 | VOID\r |
326 | EFIAPI\r | |
327 | ArmInvalidateTlb (\r | |
328 | VOID\r | |
329 | );\r | |
3402aac7 | 330 | \r |
1e57a462 | 331 | VOID\r |
332 | EFIAPI\r | |
333 | ArmUpdateTranslationTableEntry (\r | |
334 | IN VOID *TranslationTableEntry,\r | |
335 | IN VOID *Mva\r | |
336 | );\r | |
3402aac7 | 337 | \r |
1e57a462 | 338 | VOID\r |
339 | EFIAPI\r | |
340 | ArmSetDomainAccessControl (\r | |
341 | IN UINT32 Domain\r | |
342 | );\r | |
343 | \r | |
344 | VOID\r | |
345 | EFIAPI\r | |
346 | ArmSetTTBR0 (\r | |
347 | IN VOID *TranslationTableBase\r | |
348 | );\r | |
349 | \r | |
ff1f27c0 EL |
350 | VOID\r |
351 | EFIAPI\r | |
352 | ArmSetTTBCR (\r | |
353 | IN UINT32 Bits\r | |
354 | );\r | |
355 | \r | |
1e57a462 | 356 | VOID *\r |
357 | EFIAPI\r | |
358 | ArmGetTTBR0BaseAddress (\r | |
359 | VOID\r | |
360 | );\r | |
361 | \r | |
1e57a462 | 362 | BOOLEAN\r |
363 | EFIAPI\r | |
364 | ArmMmuEnabled (\r | |
365 | VOID\r | |
366 | );\r | |
3402aac7 | 367 | \r |
1e57a462 | 368 | VOID\r |
369 | EFIAPI\r | |
370 | ArmEnableBranchPrediction (\r | |
371 | VOID\r | |
372 | );\r | |
373 | \r | |
374 | VOID\r | |
375 | EFIAPI\r | |
376 | ArmDisableBranchPrediction (\r | |
377 | VOID\r | |
378 | );\r | |
379 | \r | |
380 | VOID\r | |
381 | EFIAPI\r | |
382 | ArmSetLowVectors (\r | |
383 | VOID\r | |
384 | );\r | |
385 | \r | |
386 | VOID\r | |
387 | EFIAPI\r | |
388 | ArmSetHighVectors (\r | |
389 | VOID\r | |
390 | );\r | |
391 | \r | |
392 | VOID\r | |
393 | EFIAPI\r | |
394 | ArmDataMemoryBarrier (\r | |
395 | VOID\r | |
396 | );\r | |
3402aac7 | 397 | \r |
1e57a462 | 398 | VOID\r |
399 | EFIAPI\r | |
cf93a378 | 400 | ArmDataSynchronizationBarrier (\r |
1e57a462 | 401 | VOID\r |
402 | );\r | |
3402aac7 | 403 | \r |
1e57a462 | 404 | VOID\r |
405 | EFIAPI\r | |
406 | ArmInstructionSynchronizationBarrier (\r | |
407 | VOID\r | |
408 | );\r | |
409 | \r | |
410 | VOID\r | |
411 | EFIAPI\r | |
412 | ArmWriteVBar (\r | |
4e57d6d7 | 413 | IN UINTN VectorBase\r |
1e57a462 | 414 | );\r |
415 | \r | |
4e57d6d7 | 416 | UINTN\r |
1e57a462 | 417 | EFIAPI\r |
418 | ArmReadVBar (\r | |
419 | VOID\r | |
420 | );\r | |
421 | \r | |
422 | VOID\r | |
423 | EFIAPI\r | |
424 | ArmWriteAuxCr (\r | |
425 | IN UINT32 Bit\r | |
426 | );\r | |
427 | \r | |
428 | UINT32\r | |
429 | EFIAPI\r | |
430 | ArmReadAuxCr (\r | |
431 | VOID\r | |
432 | );\r | |
433 | \r | |
434 | VOID\r | |
435 | EFIAPI\r | |
436 | ArmSetAuxCrBit (\r | |
437 | IN UINT32 Bits\r | |
438 | );\r | |
439 | \r | |
440 | VOID\r | |
441 | EFIAPI\r | |
442 | ArmUnsetAuxCrBit (\r | |
443 | IN UINT32 Bits\r | |
444 | );\r | |
445 | \r | |
446 | VOID\r | |
447 | EFIAPI\r | |
448 | ArmCallSEV (\r | |
449 | VOID\r | |
450 | );\r | |
451 | \r | |
452 | VOID\r | |
453 | EFIAPI\r | |
454 | ArmCallWFE (\r | |
455 | VOID\r | |
456 | );\r | |
457 | \r | |
458 | VOID\r | |
459 | EFIAPI\r | |
460 | ArmCallWFI (\r | |
25402f5d | 461 | \r |
1e57a462 | 462 | VOID\r |
463 | );\r | |
464 | \r | |
465 | UINTN\r | |
466 | EFIAPI\r | |
467 | ArmReadMpidr (\r | |
468 | VOID\r | |
469 | );\r | |
470 | \r | |
9401d6f4 OM |
471 | UINTN\r |
472 | EFIAPI\r | |
473 | ArmReadMidr (\r | |
474 | VOID\r | |
475 | );\r | |
476 | \r | |
1e57a462 | 477 | UINT32\r |
478 | EFIAPI\r | |
479 | ArmReadCpacr (\r | |
480 | VOID\r | |
481 | );\r | |
482 | \r | |
483 | VOID\r | |
484 | EFIAPI\r | |
485 | ArmWriteCpacr (\r | |
486 | IN UINT32 Access\r | |
487 | );\r | |
488 | \r | |
489 | VOID\r | |
490 | EFIAPI\r | |
491 | ArmEnableVFP (\r | |
492 | VOID\r | |
493 | );\r | |
494 | \r | |
46d4d75c OM |
495 | /**\r |
496 | Get the Secure Configuration Register value\r | |
497 | \r | |
498 | @return Value read from the Secure Configuration Register\r | |
499 | \r | |
500 | **/\r | |
1e57a462 | 501 | UINT32\r |
502 | EFIAPI\r | |
503 | ArmReadScr (\r | |
504 | VOID\r | |
505 | );\r | |
506 | \r | |
46d4d75c OM |
507 | /**\r |
508 | Set the Secure Configuration Register\r | |
509 | \r | |
510 | @param Value Value to write to the Secure Configuration Register\r | |
511 | \r | |
512 | **/\r | |
1e57a462 | 513 | VOID\r |
514 | EFIAPI\r | |
515 | ArmWriteScr (\r | |
46d4d75c | 516 | IN UINT32 Value\r |
1e57a462 | 517 | );\r |
518 | \r | |
519 | UINT32\r | |
520 | EFIAPI\r | |
521 | ArmReadMVBar (\r | |
522 | VOID\r | |
523 | );\r | |
524 | \r | |
525 | VOID\r | |
526 | EFIAPI\r | |
527 | ArmWriteMVBar (\r | |
528 | IN UINT32 VectorMonitorBase\r | |
529 | );\r | |
530 | \r | |
531 | UINT32\r | |
532 | EFIAPI\r | |
533 | ArmReadSctlr (\r | |
534 | VOID\r | |
535 | );\r | |
536 | \r | |
1e1d1697 MZ |
537 | VOID\r |
538 | EFIAPI\r | |
539 | ArmWriteSctlr (\r | |
540 | IN UINT32 Value\r | |
541 | );\r | |
542 | \r | |
5ea2c2d3 | 543 | UINTN\r |
544 | EFIAPI\r | |
545 | ArmReadHVBar (\r | |
546 | VOID\r | |
547 | );\r | |
548 | \r | |
549 | VOID\r | |
550 | EFIAPI\r | |
551 | ArmWriteHVBar (\r | |
552 | IN UINTN HypModeVectorBase\r | |
553 | );\r | |
554 | \r | |
52d44f77 OM |
555 | \r |
556 | //\r | |
557 | // Helper functions for accessing CPU ACTLR\r | |
558 | //\r | |
559 | \r | |
560 | UINTN\r | |
561 | EFIAPI\r | |
562 | ArmReadCpuActlr (\r | |
563 | VOID\r | |
564 | );\r | |
565 | \r | |
566 | VOID\r | |
567 | EFIAPI\r | |
568 | ArmWriteCpuActlr (\r | |
569 | IN UINTN Val\r | |
570 | );\r | |
571 | \r | |
572 | VOID\r | |
573 | EFIAPI\r | |
574 | ArmSetCpuActlrBit (\r | |
575 | IN UINTN Bits\r | |
576 | );\r | |
577 | \r | |
578 | VOID\r | |
579 | EFIAPI\r | |
580 | ArmUnsetCpuActlrBit (\r | |
581 | IN UINTN Bits\r | |
582 | );\r | |
583 | \r | |
734bd6cc AB |
584 | //\r |
585 | // Accessors for the architected generic timer registers\r | |
586 | //\r | |
587 | \r | |
588 | #define ARM_ARCH_TIMER_ENABLE (1 << 0)\r | |
589 | #define ARM_ARCH_TIMER_IMASK (1 << 1)\r | |
590 | #define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r | |
591 | \r | |
592 | UINTN\r | |
593 | EFIAPI\r | |
594 | ArmReadCntFrq (\r | |
595 | VOID\r | |
596 | );\r | |
597 | \r | |
598 | VOID\r | |
599 | EFIAPI\r | |
600 | ArmWriteCntFrq (\r | |
601 | UINTN FreqInHz\r | |
602 | );\r | |
603 | \r | |
604 | UINT64\r | |
605 | EFIAPI\r | |
606 | ArmReadCntPct (\r | |
607 | VOID\r | |
608 | );\r | |
609 | \r | |
610 | UINTN\r | |
611 | EFIAPI\r | |
612 | ArmReadCntkCtl (\r | |
613 | VOID\r | |
614 | );\r | |
615 | \r | |
616 | VOID\r | |
617 | EFIAPI\r | |
618 | ArmWriteCntkCtl (\r | |
619 | UINTN Val\r | |
620 | );\r | |
621 | \r | |
622 | UINTN\r | |
623 | EFIAPI\r | |
624 | ArmReadCntpTval (\r | |
625 | VOID\r | |
626 | );\r | |
627 | \r | |
628 | VOID\r | |
629 | EFIAPI\r | |
630 | ArmWriteCntpTval (\r | |
631 | UINTN Val\r | |
632 | );\r | |
633 | \r | |
634 | UINTN\r | |
635 | EFIAPI\r | |
636 | ArmReadCntpCtl (\r | |
637 | VOID\r | |
638 | );\r | |
639 | \r | |
640 | VOID\r | |
641 | EFIAPI\r | |
642 | ArmWriteCntpCtl (\r | |
643 | UINTN Val\r | |
644 | );\r | |
645 | \r | |
646 | UINTN\r | |
647 | EFIAPI\r | |
648 | ArmReadCntvTval (\r | |
649 | VOID\r | |
650 | );\r | |
651 | \r | |
652 | VOID\r | |
653 | EFIAPI\r | |
654 | ArmWriteCntvTval (\r | |
655 | UINTN Val\r | |
656 | );\r | |
657 | \r | |
658 | UINTN\r | |
659 | EFIAPI\r | |
660 | ArmReadCntvCtl (\r | |
661 | VOID\r | |
662 | );\r | |
663 | \r | |
664 | VOID\r | |
665 | EFIAPI\r | |
666 | ArmWriteCntvCtl (\r | |
667 | UINTN Val\r | |
668 | );\r | |
669 | \r | |
670 | UINT64\r | |
671 | EFIAPI\r | |
672 | ArmReadCntvCt (\r | |
673 | VOID\r | |
674 | );\r | |
675 | \r | |
676 | UINT64\r | |
677 | EFIAPI\r | |
678 | ArmReadCntpCval (\r | |
679 | VOID\r | |
680 | );\r | |
681 | \r | |
682 | VOID\r | |
683 | EFIAPI\r | |
684 | ArmWriteCntpCval (\r | |
685 | UINT64 Val\r | |
686 | );\r | |
687 | \r | |
688 | UINT64\r | |
689 | EFIAPI\r | |
690 | ArmReadCntvCval (\r | |
691 | VOID\r | |
692 | );\r | |
693 | \r | |
694 | VOID\r | |
695 | EFIAPI\r | |
696 | ArmWriteCntvCval (\r | |
697 | UINT64 Val\r | |
698 | );\r | |
699 | \r | |
700 | UINT64\r | |
701 | EFIAPI\r | |
702 | ArmReadCntvOff (\r | |
703 | VOID\r | |
704 | );\r | |
705 | \r | |
706 | VOID\r | |
707 | EFIAPI\r | |
708 | ArmWriteCntvOff (\r | |
709 | UINT64 Val\r | |
710 | );\r | |
711 | \r | |
95d04ebc AB |
712 | UINTN\r |
713 | EFIAPI\r | |
714 | ArmGetPhysicalAddressBits (\r | |
715 | VOID\r | |
716 | );\r | |
717 | \r | |
1e57a462 | 718 | #endif // __ARM_LIB__\r |