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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
869b17cc | 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
56d7640a | 7 | This program and the accompanying materials\r |
49ba9447 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/HobLib.h>\r | |
27 | #include <Library/IoLib.h>\r | |
77ba993c | 28 | #include <Library/MemoryAllocationLib.h>\r |
29 | #include <Library/PcdLib.h>\r | |
49ba9447 | 30 | #include <Library/PciLib.h>\r |
31 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 32 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 33 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 34 | #include <Library/ResourcePublicationLib.h>\r |
35 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 36 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 37 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 38 | #include <OvmfPlatforms.h>\r |
49ba9447 | 39 | \r |
40 | #include "Platform.h"\r | |
3ca15914 | 41 | #include "Cmos.h"\r |
49ba9447 | 42 | \r |
43 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
44 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 45 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 46 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 47 | { EfiRuntimeServicesData, 0x024 },\r |
48 | { EfiRuntimeServicesCode, 0x030 },\r | |
49 | { EfiBootServicesCode, 0x180 },\r | |
50 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 51 | { EfiMaxMemoryType, 0x000 }\r |
52 | };\r | |
53 | \r | |
54 | \r | |
9ed65b10 | 55 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
56 | {\r | |
57 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
58 | &gEfiPeiMasterBootModePpiGuid,\r | |
59 | NULL\r | |
60 | }\r | |
61 | };\r | |
62 | \r | |
63 | \r | |
589756c7 PA |
64 | UINT16 mHostBridgeDevId;\r |
65 | \r | |
979420df JJ |
66 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
67 | \r | |
7cdba634 JJ |
68 | BOOLEAN mS3Supported = FALSE;\r |
69 | \r | |
979420df | 70 | \r |
49ba9447 | 71 | VOID\r |
72 | AddIoMemoryBaseSizeHob (\r | |
73 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
74 | UINT64 MemorySize\r | |
75 | )\r | |
76 | {\r | |
991d9563 | 77 | BuildResourceDescriptorHob (\r |
78 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 79 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
80 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
81 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 82 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 83 | MemoryBase,\r |
84 | MemorySize\r | |
85 | );\r | |
86 | }\r | |
87 | \r | |
eec7d420 | 88 | VOID\r |
89 | AddReservedMemoryBaseSizeHob (\r | |
90 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
91 | UINT64 MemorySize\r | |
92 | )\r | |
93 | {\r | |
94 | BuildResourceDescriptorHob (\r | |
95 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
96 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
97 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
98 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
100 | MemoryBase,\r | |
101 | MemorySize\r | |
102 | );\r | |
103 | }\r | |
49ba9447 | 104 | \r |
105 | VOID\r | |
106 | AddIoMemoryRangeHob (\r | |
107 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
108 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
109 | )\r | |
110 | {\r | |
111 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
112 | }\r | |
113 | \r | |
114 | \r | |
115 | VOID\r | |
116 | AddMemoryBaseSizeHob (\r | |
117 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
118 | UINT64 MemorySize\r | |
119 | )\r | |
120 | {\r | |
991d9563 | 121 | BuildResourceDescriptorHob (\r |
122 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 123 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
124 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
125 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
126 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
127 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
128 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 129 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 130 | MemoryBase,\r |
131 | MemorySize\r | |
132 | );\r | |
133 | }\r | |
134 | \r | |
135 | \r | |
136 | VOID\r | |
137 | AddMemoryRangeHob (\r | |
138 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
139 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
140 | )\r | |
141 | {\r | |
142 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
143 | }\r | |
144 | \r | |
c0e10976 | 145 | \r |
146 | VOID\r | |
147 | AddUntestedMemoryBaseSizeHob (\r | |
148 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
149 | UINT64 MemorySize\r | |
150 | )\r | |
151 | {\r | |
152 | BuildResourceDescriptorHob (\r | |
153 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
154 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
155 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
156 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
157 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
158 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
159 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r | |
160 | MemoryBase,\r | |
161 | MemorySize\r | |
162 | );\r | |
163 | }\r | |
164 | \r | |
165 | \r | |
166 | VOID\r | |
167 | AddUntestedMemoryRangeHob (\r | |
168 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
169 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
170 | )\r | |
171 | {\r | |
172 | AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
173 | }\r | |
174 | \r | |
bb6a9a93 | 175 | VOID\r |
4b455f7b | 176 | MemMapInitialization (\r |
bb6a9a93 WL |
177 | VOID\r |
178 | )\r | |
179 | {\r | |
bb6a9a93 WL |
180 | //\r |
181 | // Create Memory Type Information HOB\r | |
182 | //\r | |
183 | BuildGuidDataHob (\r | |
184 | &gEfiMemoryTypeInformationGuid,\r | |
185 | mDefaultMemoryTypeInformation,\r | |
186 | sizeof(mDefaultMemoryTypeInformation)\r | |
187 | );\r | |
188 | \r | |
189 | //\r | |
190 | // Add PCI IO Port space available for PCI resource allocations.\r | |
191 | //\r | |
192 | BuildResourceDescriptorHob (\r | |
193 | EFI_RESOURCE_IO,\r | |
194 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
195 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
196 | 0xC000,\r | |
197 | 0x4000\r | |
198 | );\r | |
199 | \r | |
200 | //\r | |
201 | // Video memory + Legacy BIOS region\r | |
202 | //\r | |
203 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
204 | \r | |
4b455f7b JJ |
205 | if (!mXen) {\r |
206 | UINT32 TopOfLowRam;\r | |
c68d3a69 LE |
207 | UINT32 PciBase;\r |
208 | \r | |
4b455f7b | 209 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
c68d3a69 LE |
210 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
211 | //\r | |
212 | // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r | |
213 | // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r | |
214 | // the RAM below 4 GB exceed it.\r | |
215 | //\r | |
216 | PciBase = BASE_2GB + BASE_1GB;\r | |
217 | ASSERT (TopOfLowRam <= PciBase);\r | |
218 | } else {\r | |
219 | PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r | |
220 | }\r | |
49ba9447 | 221 | \r |
4b455f7b JJ |
222 | //\r |
223 | // address purpose size\r | |
224 | // ------------ -------- -------------------------\r | |
225 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
226 | // 0xFC000000 gap 44 MB\r | |
227 | // 0xFEC00000 IO-APIC 4 KB\r | |
228 | // 0xFEC01000 gap 1020 KB\r | |
229 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
230 | // 0xFED00400 gap 111 KB\r |
231 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
232 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
233 | // 0xFEE00000 LAPIC 1 MB\r |
234 | //\r | |
c68d3a69 | 235 | AddIoMemoryRangeHob (PciBase, 0xFC000000);\r |
4b455f7b JJ |
236 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
237 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
238 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
239 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
240 | }\r | |
4b455f7b | 241 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
4b455f7b | 242 | }\r |
49ba9447 | 243 | }\r |
244 | \r | |
ab081a50 LE |
245 | EFI_STATUS\r |
246 | GetNamedFwCfgBoolean (\r | |
247 | IN CHAR8 *FwCfgFileName,\r | |
248 | OUT BOOLEAN *Setting\r | |
249 | )\r | |
250 | {\r | |
251 | EFI_STATUS Status;\r | |
252 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
253 | UINTN FwCfgSize;\r | |
254 | UINT8 Value[3];\r | |
255 | \r | |
256 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
257 | if (EFI_ERROR (Status)) {\r | |
258 | return Status;\r | |
259 | }\r | |
260 | if (FwCfgSize > sizeof Value) {\r | |
261 | return EFI_BAD_BUFFER_SIZE;\r | |
262 | }\r | |
263 | QemuFwCfgSelectItem (FwCfgItem);\r | |
264 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
265 | \r | |
266 | if ((FwCfgSize == 1) ||\r | |
267 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
268 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
269 | switch (Value[0]) {\r | |
270 | case '0':\r | |
271 | case 'n':\r | |
272 | case 'N':\r | |
273 | *Setting = FALSE;\r | |
274 | return EFI_SUCCESS;\r | |
275 | \r | |
276 | case '1':\r | |
277 | case 'y':\r | |
278 | case 'Y':\r | |
279 | *Setting = TRUE;\r | |
280 | return EFI_SUCCESS;\r | |
281 | \r | |
282 | default:\r | |
283 | break;\r | |
284 | }\r | |
285 | }\r | |
286 | return EFI_PROTOCOL_ERROR;\r | |
287 | }\r | |
288 | \r | |
289 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
290 | do { \\r | |
291 | BOOLEAN Setting; \\r | |
292 | \\r | |
293 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
294 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
295 | PcdSetBool (TokenName, Setting); \\r | |
296 | } \\r | |
297 | } while (0)\r | |
298 | \r | |
299 | VOID\r | |
300 | NoexecDxeInitialization (\r | |
301 | VOID\r | |
302 | )\r | |
303 | {\r | |
304 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
305 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
306 | }\r | |
49ba9447 | 307 | \r |
308 | VOID\r | |
309 | MiscInitialization (\r | |
0e20a186 | 310 | VOID\r |
49ba9447 | 311 | )\r |
312 | {\r | |
97380beb GS |
313 | UINTN PmCmd;\r |
314 | UINTN Pmba;\r | |
e2ab3f81 GS |
315 | UINTN AcpiCtlReg;\r |
316 | UINT8 AcpiEnBit;\r | |
97380beb | 317 | \r |
49ba9447 | 318 | //\r |
319 | // Disable A20 Mask\r | |
320 | //\r | |
55cdb67a | 321 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 322 | \r |
323 | //\r | |
86a14b0a LE |
324 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
325 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
326 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 327 | //\r |
86a14b0a | 328 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 329 | \r |
97380beb | 330 | //\r |
589756c7 | 331 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 332 | //\r |
589756c7 | 333 | switch (mHostBridgeDevId) {\r |
97380beb | 334 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 335 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 LE |
336 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
337 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
338 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
339 | break;\r |
340 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 341 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 LE |
342 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
343 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
344 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
345 | break;\r |
346 | default:\r | |
347 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 348 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
349 | ASSERT (FALSE);\r |
350 | return;\r | |
351 | }\r | |
589756c7 | 352 | PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
97380beb | 353 | \r |
0e20a186 | 354 | //\r |
e2ab3f81 GS |
355 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
356 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
357 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 358 | //\r |
e2ab3f81 | 359 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 360 | //\r |
e2ab3f81 | 361 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 362 | // 1. set PMBA\r |
eec7d420 | 363 | //\r |
97380beb | 364 | PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r |
931a0c74 | 365 | \r |
366 | //\r | |
367 | // 2. set PCICMD/IOSE\r | |
368 | //\r | |
97380beb | 369 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 370 | \r |
371 | //\r | |
e2ab3f81 | 372 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 373 | //\r |
e2ab3f81 | 374 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 375 | }\r |
90721ba5 PA |
376 | \r |
377 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
378 | //\r | |
379 | // Set Root Complex Register Block BAR\r | |
380 | //\r | |
381 | PciWrite32 (\r | |
382 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
383 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
384 | );\r | |
385 | }\r | |
49ba9447 | 386 | }\r |
387 | \r | |
388 | \r | |
9ed65b10 | 389 | VOID\r |
390 | BootModeInitialization (\r | |
8f5ca05b | 391 | VOID\r |
9ed65b10 | 392 | )\r |
393 | {\r | |
8f5ca05b LE |
394 | EFI_STATUS Status;\r |
395 | \r | |
396 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 397 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 398 | }\r |
9be75189 | 399 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 400 | \r |
979420df | 401 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 402 | ASSERT_EFI_ERROR (Status);\r |
403 | \r | |
404 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
405 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 406 | }\r |
407 | \r | |
408 | \r | |
77ba993c | 409 | VOID\r |
410 | ReserveEmuVariableNvStore (\r | |
411 | )\r | |
412 | {\r | |
413 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
414 | \r | |
415 | //\r | |
416 | // Allocate storage for NV variables early on so it will be\r | |
417 | // at a consistent address. Since VM memory is preserved\r | |
418 | // across reboots, this allows the NV variable storage to survive\r | |
419 | // a VM reboot.\r | |
420 | //\r | |
421 | VariableStore =\r | |
422 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
9edb2933 | 423 | AllocateAlignedRuntimePages (\r |
cce992ac WL |
424 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r |
425 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
27f58ea1 | 426 | );\r |
77ba993c | 427 | DEBUG ((EFI_D_INFO,\r |
428 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
429 | VariableStore,\r | |
29a3f139 | 430 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 431 | ));\r |
432 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
433 | }\r | |
434 | \r | |
435 | \r | |
3ca15914 | 436 | VOID\r |
437 | DebugDumpCmos (\r | |
438 | VOID\r | |
439 | )\r | |
440 | {\r | |
6394c35a | 441 | UINT32 Loop;\r |
3ca15914 | 442 | \r |
443 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
444 | \r | |
445 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
446 | if ((Loop % 0x10) == 0) {\r | |
447 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
448 | }\r | |
449 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
450 | if ((Loop % 0x10) == 0xf) {\r | |
451 | DEBUG ((EFI_D_INFO, "\n"));\r | |
452 | }\r | |
453 | }\r | |
454 | }\r | |
455 | \r | |
456 | \r | |
49ba9447 | 457 | /**\r |
458 | Perform Platform PEI initialization.\r | |
459 | \r | |
460 | @param FileHandle Handle of the file being invoked.\r | |
461 | @param PeiServices Describes the list of possible PEI Services.\r | |
462 | \r | |
463 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
464 | \r | |
465 | **/\r | |
466 | EFI_STATUS\r | |
467 | EFIAPI\r | |
468 | InitializePlatform (\r | |
469 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
470 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
471 | )\r | |
472 | {\r | |
473 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r | |
474 | \r | |
3ca15914 | 475 | DebugDumpCmos ();\r |
476 | \r | |
b98b4941 | 477 | XenDetect ();\r |
c7ea55b9 | 478 | \r |
7cdba634 JJ |
479 | if (QemuFwCfgS3Enabled ()) {\r |
480 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
481 | mS3Supported = TRUE;\r | |
482 | }\r | |
483 | \r | |
869b17cc | 484 | BootModeInitialization ();\r |
bc89fe48 | 485 | AddressWidthInitialization ();\r |
869b17cc | 486 | \r |
f76e9eba JJ |
487 | PublishPeiMemory ();\r |
488 | \r | |
2818c158 | 489 | InitializeRamRegions ();\r |
49ba9447 | 490 | \r |
b621bb0a | 491 | if (mXen) {\r |
c7ea55b9 | 492 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 493 | InitializeXen ();\r |
c7ea55b9 | 494 | }\r |
eec7d420 | 495 | \r |
589756c7 PA |
496 | //\r |
497 | // Query Host Bridge DID\r | |
498 | //\r | |
499 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
500 | \r | |
bd386eaf JJ |
501 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
502 | ReserveEmuVariableNvStore ();\r | |
bd386eaf | 503 | PeiFvInitialization ();\r |
bd386eaf | 504 | MemMapInitialization ();\r |
ab081a50 | 505 | NoexecDxeInitialization ();\r |
bd386eaf | 506 | }\r |
49ba9447 | 507 | \r |
0e20a186 | 508 | MiscInitialization ();\r |
49ba9447 | 509 | \r |
510 | return EFI_SUCCESS;\r | |
511 | }\r |