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MdePkg/Register: Add register definition header files for RISC-V
[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec
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7798fb83 1## @file UefiCpuPkg.dec\r
7798fb83
HT		 2# This Package provides UEFI compatible CPU modules and libraries.\r
3#\r
4a68176c 4# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>\r
7798fb83 5#\r
0acd8697 6# SPDX-License-Identifier: BSD-2-Clause-Patent\r
7798fb83
HT		 7#\r
8##\r
9\r
10[Defines]\r
11 DEC_SPECIFICATION = 0x00010005\r
12 PACKAGE_NAME = UefiCpuPkg\r
abae030a 13 PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
7798fb83 14 PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
30142a32 15 PACKAGE_VERSION = 0.90\r
7798fb83
HT		 16\r
17[Includes]\r
18 Include\r
19\r
20[LibraryClasses]\r
21 ## @libraryclass Defines some routines that are generic for IA32 family CPU\r
22 ## to be UEFI specification compliant.\r
23 ##\r
24 UefiCpuLib|Include/Library/UefiCpuLib.h\r
25\r
548013c0
JF		 26 ## @libraryclass Defines some routines that are used to register/manage/program\r
27 ## CPU features.\r
28 ##\r
245e98bf 29 RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
548013c0 30\r
7798fb83
HT		 31[LibraryClasses.IA32, LibraryClasses.X64]\r
32 ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
33 ##\r
34 MtrrLib|Include/Library/MtrrLib.h\r
35\r
36 ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
37 ##\r
38 LocalApicLib|Include/Library/LocalApicLib.h\r
d947a4cc
MK		 39\r
40 ## @libraryclass Provides platform specific initialization functions in the SEC phase.\r
41 ##\r
42 PlatformSecLib|Include/Library/PlatformSecLib.h\r
529a5a86 43\r
406c7200
MK		 44 ## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r
45 ##\r
46 SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r
529a5a86 47\r
406c7200
MK		 48 ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
49 ##\r
50 SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
51\r
87896d03
JF		 52 ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
53 ##\r
54 MpInitLib|Include/Library/MpInitLib.h\r
55\r
a89f558d
MX		 56 ## @libraryclass Provides function to support CcExit processing.\r
57 CcExitLib|Include/Library/CcExitLib.h\r
87149787 58\r
83facfd1
LY		 59 ## @libraryclass Provides function to get CPU cache information.\r
60 CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h\r
61\r
1a957f17
RN		 62 ## @libraryclass Provides function for loading microcode.\r
63 MicrocodeLib|Include/Library/MicrocodeLib.h\r
64\r
75e3c243
RN		 65 ## @libraryclass Provides function for manipulating x86 paging structures.\r
66 CpuPageTableLib|Include/Library/CpuPageTableLib.h\r
67\r
7798fb83
HT		 68[Guids]\r
69 gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
f7c11c53 70 gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
7798fb83 71\r
98f4a565
JF		 72 ## Include/Guid/CpuFeaturesSetDone.h\r
73 gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
74\r
e000e774
JF		 75 ## Include/Guid/CpuFeaturesInitDone.h\r
76 gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
77\r
25390997
HW		 78 ## Include/Guid/MicrocodePatchHob.h\r
79 gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
80\r
406c7200
MK		 81[Protocols]\r
82 ## Include/Protocol/SmmCpuService.h\r
4a68176c
LZ		 83 gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
84 gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}\r
529a5a86 85\r
f7c11c53
MK		 86 ## Include/Protocol/SmMonitorInit.h\r
87 gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
88\r
abae030a
LG		 89#\r
90# [Error.gUefiCpuPkgTokenSpaceGuid]\r
91# 0x80000001 | Invalid value provided.\r
92#\r
93\r
ebfbb701
ED		 94[Ppis]\r
95 gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
96\r
c788c2b1
SF		 97 ## Include/Ppi/ShadowMicrocode.h\r
98 gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r
99\r
479613bd
MK		 100 ## Include/Ppi/RepublishSecPpi.h\r
101 gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}\r
102\r
529a5a86
MK		 103[PcdsFeatureFlag]\r
104 ## Indicates if SMM Profile will be enabled.\r
105 # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
f64a597d
RN		 106 # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r
107 # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r
529a5a86
MK		 108 # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
109 # TRUE - SMM Profile will be enabled.<BR>\r
110 # FALSE - SMM Profile will be disabled.<BR>\r
111 # @Prompt Enable SMM Profile.\r
112 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r
113\r
114 ## Indicates if the SMM profile log buffer is a ring buffer.\r
115 # If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
116 # TRUE - the SMM profile log buffer is a ring buffer.<BR>\r
117 # FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
118 # @Prompt The SMM profile log buffer is a ring buffer.\r
119 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r
120\r
121 ## Indicates if SMM Startup AP in a blocking fashion.\r
122 # TRUE - SMM Startup AP in a blocking fashion.<BR>\r
123 # FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
124 # @Prompt SMM Startup AP in a blocking fashion.\r
125 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
126\r
127 ## Indicates if SMM Stack Guard will be enabled.\r
509f8425 128 # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
529a5a86
MK		 129 # TRUE - SMM Stack Guard will be enabled.<BR>\r
130 # FALSE - SMM Stack Guard will be disabled.<BR>\r
131 # @Prompt Enable SMM Stack Guard.\r
509f8425 132 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
529a5a86
MK		 133\r
134 ## Indicates if BSP election in SMM will be enabled.\r
135 # If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
136 # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
137 # TRUE - BSP election in SMM will be enabled.<BR>\r
138 # FALSE - BSP election in SMM will be disabled.<BR>\r
139 # @Prompt Enable BSP election in SMM.\r
140 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r
141\r
142 ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
143 # TRUE - SMM CPU hot-plug will be enabled.<BR>\r
144 # FALSE - SMM CPU hot-plug will be disabled.<BR>\r
145 # @Prompt SMM CPU hot-plug.\r
146 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r
147\r
148 ## Indicates if SMM Debug will be enabled.\r
149 # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
150 # TRUE - SMM Debug will be enabled.<BR>\r
151 # FALSE - SMM Debug will be disabled.<BR>\r
152 # @Prompt Enable SMM Debug.\r
153 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r
154\r
155 ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
156 # TRUE - SMM Feature Control MSR will be locked.<BR>\r
157 # FALSE - SMM Feature Control MSR will not be locked.<BR>\r
158 # @Prompt Lock SMM Feature Control MSR.\r
159 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
160\r
76ec1752
WJ		 161 ## Indicates if SMRR will be enabled.<BR><BR>\r
162 # TRUE - SMRR will be enabled.<BR>\r
163 # FALSE - SMRR will not be enabled.<BR>\r
164 # @Prompt Enable SMRR.\r
165 gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D\r
166\r
167 ## Indicates if SmmFeatureControl will be enabled.<BR><BR>\r
168 # TRUE - SmmFeatureControl will be enabled.<BR>\r
169 # FALSE - SmmFeatureControl will not be enabled.<BR>\r
170 # @Prompt Support SmmFeatureControl.\r
171 gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x32132110\r
172\r
adb9f50e
JW		 173[PcdsFixedAtBuild]\r
174 ## List of exception vectors which need switching stack.\r
175 # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
176 # By default exception #DD(8), #PF(14) are supported.\r
177 # @Prompt Specify exception vectors which need switching stack.\r
178 gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
179\r
180 ## Size of good stack for an exception.\r
181 # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
182 # @Prompt Specify size of good stack of exception which need switching stack.\r
183 gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
184\r
9caaa79d
ED		 185 ## Count of pre allocated SMM MP tokens per chunk.\r
186 # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
187 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
188\r
88a36300
TL		 189 ## Area of memory where the SEV-ES work area block lives.\r
190 # @Prompt Configure the SEV-ES work area base\r
191 gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005\r
192\r
193 ## Size of teh area of memory where the SEV-ES work area block lives.\r
194 # @Prompt Configure the SEV-ES work area base\r
195 gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006\r
196\r
7798fb83 197[PcdsFixedAtBuild, PcdsPatchableInModule]\r
529a5a86
MK		 198 ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
199 # @Prompt Configure base address of CPU Local APIC\r
abae030a 200 # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
7798fb83 201 gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r
529a5a86 202\r
abae030a
LG		 203 ## Specifies delay value in microseconds after sending out an INIT IPI.\r
204 # @Prompt Configure delay value after send an INIT IPI\r
cf1eb6e6 205 gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
529a5a86 206\r
6a26a597
CF		 207 ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
208 ## aligns the address on a 4-KByte boundary.\r
209 # @Prompt Configure stack size for Application Processor (AP)\r
210 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
7798fb83 211\r
d947a4cc
MK		 212 ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
213 # @Prompt Stack size in the temporary RAM.\r
214 gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
215\r
529a5a86
MK		 216 ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
217 # @Prompt SMM profile data buffer size.\r
218 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
219\r
220 ## Specifies stack size in bytes for each processor in SMM.\r
221 # @Prompt Processor stack size in SMM.\r
222 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
223\r
3eb69b08
JY		 224 ## Specifies shadow stack size in bytes for each processor in SMM.\r
225 # @Prompt Processor shadow stack size in SMM.\r
226 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r
227\r
529a5a86
MK		 228 ## Indicates if SMM Code Access Check is enabled.\r
229 # If enabled, the SMM handler cannot execute the code outside SMM regions.\r
230 # This PCD is suggested to TRUE in production image.<BR><BR>\r
231 # TRUE - SMM Code Access Check will be enabled.<BR>\r
232 # FALSE - SMM Code Access Check will be disabled.<BR>\r
233 # @Prompt SMM Code Access Check.\r
234 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
235\r
46309b11
JF		 236 ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
237 # MTRRs reserved for OS use is 2.\r
238 # @Prompt Number of reserved variable MTRRs.\r
239 gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
240\r
f7c11c53
MK		 241 ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
242 # @Prompt STM exception stack size.\r
243 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
244\r
245 ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
246 # @Prompt MSEG size.\r
247 gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
248\r
98eb0095
JF		 249 ## Specifies the supported CPU features bit in array.\r
250 # @Prompt Supported CPU features.\r
7eee4e1e
JF		 251 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
252\r
98eb0095
JF		 253 ## Specifies if CPU features will be initialized after SMM relocation.\r
254 # @Prompt If CPU features will be initialized after SMM relocation.\r
82e75ac6
JF		 255 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
256\r
98eb0095
JF		 257 ## Specifies if CPU features will be initialized during S3 resume.\r
258 # @Prompt If CPU features will be initialized during S3 resume.\r
82e75ac6
JF		 259 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
260\r
30781feb
DK		 261 ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
262 # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
263 # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
264 # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
265 # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
266 # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
267 gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
268\r
a1c35ff3
HW		 269 ## Specifies the periodic interval value in microseconds for the status check\r
270 # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking\r
271 # mode in DXE phase.\r
272 # @Prompt Periodic interval value in microseconds for AP status check in DXE.\r
273 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E\r
274\r
f79fcf45 275[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
b1e01bd4
JF		 276 ## Specifies max supported number of Logical Processors.\r
277 # @Prompt Configure max supported number of Logical Processors\r
278 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
f79fcf45
JF		 279 ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
280 # @Prompt Timeout for the BSP to detect all APs for the first time.\r
281 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
778832bc
LE		 282 ## Specifies the number of Logical Processors that are available in the\r
283 # preboot environment after platform reset, including BSP and APs. Possible\r
284 # values:<BR><BR>\r
285 # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and\r
286 # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP\r
287 # detection by the BSP.<BR>\r
288 # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial\r
289 # AP detection finishes only when the detected CPU count\r
290 # (BSP plus APs) reaches the value of\r
291 # PcdCpuBootLogicalProcessorNumber, regardless of how long\r
292 # that takes.<BR>\r
293 # @Prompt Number of Logical Processors available after platform reset.\r
294 gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008\r
30314463
JF		 295 ## Specifies the base address of the first microcode Patch in the microcode Region.\r
296 # @Prompt Microcode Region base address.\r
297 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
298 ## Specifies the size of the microcode Region.\r
299 # @Prompt Microcode Region size.\r
300 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
54a3e8c9
JF		 301 ## Specifies the AP wait loop state during POST phase.\r
302 # The value is defined as below.<BR><BR>\r
303 # 1: Place AP in the Hlt-Loop state.<BR>\r
304 # 2: Place AP in the Mwait-Loop state.<BR>\r
305 # 3: Place AP in the Run-Loop state.<BR>\r
306 # @Prompt The AP wait loop state.\r
307 # @ValidRange 0x80000001 | 1 - 3\r
308 gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
9d39ed93
JF		 309 ## Specifies the AP target C-state for Mwait during POST phase.\r
310 # The default value 0 means C1 state.\r
311 # The value is defined as below.<BR><BR>\r
312 # @Prompt The specified AP target C-state for Mwait.\r
313 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
f79fcf45 314\r
b43dd229
LE		 315 ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
316 # @Prompt AP synchronization timeout value in SMM.\r
317 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
318\r
319 ## Indicates the CPU synchronization method used when processing an SMI.\r
320 # 0x00 - Traditional CPU synchronization method.<BR>\r
321 # 0x01 - Relaxed CPU synchronization method.<BR>\r
322 # @Prompt SMM CPU Synchronization Method.\r
323 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
324\r
0a70d1c3
JF		 325 ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
326 # @Prompt The encoded values for target duty cycle modulation.\r
327 # @ValidRange 0x80000001 | 0 - 15\r
328 gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
329\r
330 ## Indicates if the current boot is a power-on reset.<BR><BR>\r
331 # TRUE - Current boot is a power-on reset.<BR>\r
332 # FALSE - Current boot is not a power-on reset.<BR>\r
333 # @Prompt Current boot is a power-on reset.\r
334 gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
335\r
87184487
RN		 336[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
337 ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
338 # MMIO access is always allowed regardless of the value of this PCD.\r
339 # Loose of such restriction is only required by RAS components in X64 platforms.\r
340 # The PCD value is considered as constantly TRUE in IA32 platforms.\r
341 # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
342 # and the memory occupied by page table is protected by page table itself as read-only.\r
f64a597d
RN		 343 # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
344 # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r
345 # (PcdHeapGuardPropertyMask in MdeModulePkg).\r
346 # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r
347 # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r
87184487
RN		 348 # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
349 # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
350 # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
351 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
352\r
529a5a86
MK		 353[PcdsDynamic, PcdsDynamicEx]\r
354 ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
355 # @Prompt The pointer to a CPU S3 data buffer.\r
356 # @ValidList 0x80000001 | 0\r
357 gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
358\r
359 ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
360 # @Prompt The pointer to CPU Hot Plug Data.\r
361 # @ValidList 0x80000001 | 0\r
362 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
363\r
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JF		 364 ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
365 # @Prompt Processor feature capabilities.\r
366 # @ValidList 0x80000001 | 0\r
367 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
368\r
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ED		 369 ## As input, specifies user's desired settings for enabling/disabling processor features.\r
370 ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r
371 # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r
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JF		 372 # @ValidList 0x80000001 | 0\r
373 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
374\r
234d4c5f 375 ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
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ED		 376 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
377 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
378 # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
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ED		 379 # 0x0 - 4K.<BR>\r
380 # 0x1 - 8K.<BR>\r
381 # 0x2 - 16K.<BR>\r
382 # 0x3 - 32K.<BR>\r
383 # 0x4 - 64K.<BR>\r
384 # 0x5 - 128K.<BR>\r
385 # 0x6 - 256K.<BR>\r
386 # 0x7 - 512K.<BR>\r
387 # 0x8 - 1M.<BR>\r
388 # 0x9 - 2M.<BR>\r
389 # 0xA - 4M.<BR>\r
390 # 0xB - 8M.<BR>\r
391 # 0xC - 16M.<BR>\r
392 # 0xD - 32M.<BR>\r
393 # 0xE - 64M.<BR>\r
394 # 0xF - 128M.<BR>\r
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ED		 395 # @Prompt The memory size used for processor trace if processor trace is enabled.\r
396 # @ValidRange 0x80000001 | 0 - 0xF\r
397 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
c7399a0c 398\r
234d4c5f 399 ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
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ED		 400 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
401 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
402 # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
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ED		 403 # 0 - Single Range output scheme.<BR>\r
404 # 1 - ToPA(Table of physical address) scheme.<BR>\r
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ED		 405 # @Prompt The processor trace output scheme used when processor trace is enabled.\r
406 # @ValidRange 0x80000001 | 0 - 1\r
407 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
c7399a0c 408\r
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TL		 409 ## This dynamic PCD indicates whether SEV-ES is enabled\r
410 # TRUE - SEV-ES is enabled\r
411 # FALSE - SEV-ES is not enabled\r
412 # @Prompt SEV-ES Status\r
413 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016\r
414\r
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BS		 415 ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR\r
416 # features VMGEXIT defined in the version 2 of GHCB spec.\r
417 # @Prompt GHCB Hypervisor Features\r
418 gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018\r
419\r
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LG		 420[UserExtensions.TianoCore."ExtraFiles"]\r
421 UefiCpuPkgExtra.uni\r
EFI Development Kit II mirror for PVE