--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+\r
+.set DAIF_RD_FIQ_BIT, (1 << 6)\r
+.set DAIF_RD_IRQ_BIT, (1 << 7)\r
+\r
+ASM_FUNC(ArmReadMidr)\r
+ mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
+ ret\r
+\r
+ASM_FUNC(ArmCacheInfo)\r
+ mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r
+ ret\r
+\r
+ASM_FUNC(ArmGetInterruptState)\r
+ mrs x0, daif\r
+ tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)\r
+ cset w0, eq // if Z=1 return 1, else 0\r
+ ret\r
+\r
+ASM_FUNC(ArmGetFiqState)\r
+ mrs x0, daif\r
+ tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)\r
+ cset w0, eq // if Z=1 return 1, else 0\r
+ ret\r
+\r
+ASM_FUNC(ArmWriteCpacr)\r
+ msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r
+ ret\r
+\r
+ASM_FUNC(ArmWriteAuxCr)\r
+ EL1_OR_EL2(x1)\r
+1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+ ret\r
+2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+ ret\r
+\r
+ASM_FUNC(ArmReadAuxCr)\r
+ EL1_OR_EL2(x1)\r
+1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+ ret\r
+2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
+ ret\r
+\r
+ASM_FUNC(ArmSetTTBR0)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r
+ b 4f\r
+2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)\r
+ b 4f\r
+3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)\r
+4:isb\r
+ ret\r
+\r
+ASM_FUNC(ArmGetTTBR0BaseAddress)\r
+ EL1_OR_EL2(x1)\r
+1:mrs x0, ttbr0_el1\r
+ b 3f\r
+2:mrs x0, ttbr0_el2\r
+3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */\r
+ isb\r
+ ret\r
+\r
+ASM_FUNC(ArmGetTCR)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:mrs x0, tcr_el1\r
+ b 4f\r
+2:mrs x0, tcr_el2\r
+ b 4f\r
+3:mrs x0, tcr_el3\r
+4:isb\r
+ ret\r
+\r
+ASM_FUNC(ArmSetTCR)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr tcr_el1, x0\r
+ b 4f\r
+2:msr tcr_el2, x0\r
+ b 4f\r
+3:msr tcr_el3, x0\r
+4:isb\r
+ ret\r
+\r
+ASM_FUNC(ArmGetMAIR)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:mrs x0, mair_el1\r
+ b 4f\r
+2:mrs x0, mair_el2\r
+ b 4f\r
+3:mrs x0, mair_el3\r
+4:isb\r
+ ret\r
+\r
+ASM_FUNC(ArmSetMAIR)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr mair_el1, x0\r
+ b 4f\r
+2:msr mair_el2, x0\r
+ b 4f\r
+3:msr mair_el3, x0\r
+4:isb\r
+ ret\r
+\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // X0\r
+// IN VOID *MVA // X1\r
+// );\r
+ASM_FUNC(ArmUpdateTranslationTableEntry)\r
+ dc civac, x0 // Clean and invalidate data line\r
+ dsb sy\r
+ EL1_OR_EL2_OR_EL3(x0)\r
+1: tlbi vaae1, x1 // TLB Invalidate VA , EL1\r
+ b 4f\r
+2: tlbi vae2, x1 // TLB Invalidate VA , EL2\r
+ b 4f\r
+3: tlbi vae3, x1 // TLB Invalidate VA , EL3\r
+4: dsb sy\r
+ isb\r
+ ret\r
+\r
+ASM_FUNC(ArmInvalidateTlb)\r
+ EL1_OR_EL2_OR_EL3(x0)\r
+1: tlbi vmalle1\r
+ b 4f\r
+2: tlbi alle2\r
+ b 4f\r
+3: tlbi alle3\r
+4: dsb sy\r
+ isb\r
+ ret\r
+\r
+ASM_FUNC(ArmWriteCptr)\r
+ msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r
+ ret\r
+\r
+ASM_FUNC(ArmWriteScr)\r
+ msr scr_el3, x0 // Secure configuration register EL3\r
+ isb\r
+ ret\r
+\r
+ASM_FUNC(ArmWriteMVBar)\r
+ msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3\r
+ ret\r
+\r
+ASM_FUNC(ArmCallWFE)\r
+ wfe\r
+ ret\r
+\r
+ASM_FUNC(ArmCallSEV)\r
+ sev\r
+ ret\r
+\r
+ASM_FUNC(ArmReadCpuActlr)\r
+ mrs x0, S3_1_c15_c2_0\r
+ ret\r
+\r
+ASM_FUNC(ArmWriteCpuActlr)\r
+ msr S3_1_c15_c2_0, x0\r
+ dsb sy\r
+ isb\r
+ ret\r
+\r
+ASM_FUNC(ArmReadSctlr)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:mrs x0, sctlr_el1\r
+ ret\r
+2:mrs x0, sctlr_el2\r
+ ret\r
+3:mrs x0, sctlr_el3\r
+4:ret\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+ASM_FUNC(ArmReadMidr)\r
+ mrc p15,0,R0,c0,c0,0\r
+ bx LR\r
+\r
+ASM_FUNC(ArmCacheInfo)\r
+ mrc p15,0,R0,c0,c0,1\r
+ bx LR\r
+\r
+ASM_FUNC(ArmGetInterruptState)\r
+ mrs R0,CPSR\r
+ tst R0,#0x80 @Check if IRQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ASM_FUNC(ArmGetFiqState)\r
+ mrs R0,CPSR\r
+ tst R0,#0x40 @Check if FIQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ASM_FUNC(ArmSetDomainAccessControl)\r
+ mcr p15,0,r0,c3,c0,0\r
+ bx lr\r
+\r
+ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert\r
+ stmfd sp!, {r4-r12, lr} @ save all the banked registers\r
+ mov r3, sp @ copy the stack pointer into a non-banked register\r
+ mrs r2, cpsr @ read the cpsr\r
+ bic r2, r2, r0 @ clear mask in the cpsr\r
+ and r1, r1, r0 @ clear bits outside the mask in the input\r
+ orr r2, r2, r1 @ set field\r
+ msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r
+ isb\r
+ mov sp, r3 @ restore stack pointer\r
+ ldmfd sp!, {r4-r12, lr} @ restore registers\r
+ bx lr @ return (hopefully thumb-safe!)\r
+\r
+ASM_FUNC(CPSRRead)\r
+ mrs r0, cpsr\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCpacr)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCpacr)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteAuxCr)\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadAuxCr)\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ASM_FUNC(ArmSetTTBR0)\r
+ mcr p15,0,r0,c2,c0,0\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmSetTTBCR)\r
+ mcr p15, 0, r0, c2, c0, 2\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmGetTTBR0BaseAddress)\r
+ mrc p15,0,r0,c2,c0,0\r
+ MOV32 (r1, 0xFFFFC000)\r
+ and r0, r0, r1\r
+ isb\r
+ bx lr\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // R0\r
+// IN VOID *MVA // R1\r
+// );\r
+ASM_FUNC(ArmUpdateTranslationTableEntry)\r
+ mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r
+ dsb\r
+ mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA\r
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmInvalidateTlb)\r
+ mov r0,#0\r
+ mcr p15,0,r0,c8,c7,0\r
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadScr)\r
+ mrc p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteScr)\r
+ mcr p15, 0, r0, c1, c1, 0\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadHVBar)\r
+ mrc p15, 4, r0, c12, c0, 0\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteHVBar)\r
+ mcr p15, 4, r0, c12, c0, 0\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadMVBar)\r
+ mrc p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteMVBar)\r
+ mcr p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ASM_FUNC(ArmCallWFE)\r
+ wfe\r
+ bx lr\r
+\r
+ASM_FUNC(ArmCallSEV)\r
+ sev\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadSctlr)\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCpuActlr)\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCpuActlr)\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+\r
+ INCLUDE AsmMacroExport.inc\r
+\r
+ RVCT_ASM_EXPORT ArmReadMidr\r
+ mrc p15,0,R0,c0,c0,0\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmCacheInfo\r
+ mrc p15,0,R0,c0,c0,1\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmGetInterruptState\r
+ mrs R0,CPSR\r
+ tst R0,#0x80 // Check if IRQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmGetFiqState\r
+ mrs R0,CPSR\r
+ tst R0,#0x40 // Check if FIQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
+ mcr p15,0,r0,c3,c0,0\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT CPSRMaskInsert\r
+ stmfd sp!, {r4-r12, lr} // save all the banked registers\r
+ mov r3, sp // copy the stack pointer into a non-banked register\r
+ mrs r2, cpsr // read the cpsr\r
+ bic r2, r2, r0 // clear mask in the cpsr\r
+ and r1, r1, r0 // clear bits outside the mask in the input\r
+ orr r2, r2, r1 // set field\r
+ msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r
+ isb\r
+ mov sp, r3 // restore stack pointer\r
+ ldmfd sp!, {r4-r12, lr} // restore registers\r
+ bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
+\r
+ RVCT_ASM_EXPORT CPSRRead\r
+ mrs r0, cpsr\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCpacr\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCpacr\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteAuxCr\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadAuxCr\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmSetTTBR0\r
+ mcr p15,0,r0,c2,c0,0\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmSetTTBCR\r
+ mcr p15, 0, r0, c2, c0, 2\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
+ mrc p15,0,r0,c2,c0,0\r
+ MOV32 r1, 0xFFFFC000\r
+ and r0, r0, r1\r
+ isb\r
+ bx lr\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // R0\r
+// IN VOID *MVA // R1\r
+// );\r
+ RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
+ mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
+ dsb\r
+ mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
+ mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmInvalidateTlb\r
+ mov r0,#0\r
+ mcr p15,0,r0,c8,c7,0\r
+ mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadScr\r
+ mrc p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteScr\r
+ mcr p15, 0, r0, c1, c1, 0\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadHVBar\r
+ mrc p15, 4, r0, c12, c0, 0\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteHVBar\r
+ mcr p15, 4, r0, c12, c0, 0\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadMVBar\r
+ mrc p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteMVBar\r
+ mcr p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmCallWFE\r
+ wfe\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmCallSEV\r
+ sev\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadSctlr\r
+ mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmReadCpuActlr\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCpuActlr\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+ASM_FUNC(ArmIsMpCore)\r
+ mrc p15,0,R0,c0,c0,5\r
+ // Get Multiprocessing extension (bit31) & U bit (bit30)\r
+ and R0, R0, #0xC0000000\r
+ // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
+ cmp R0, #0x80000000\r
+ moveq R0, #1\r
+ movne R0, #0\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableAsynchronousAbort)\r
+ cpsie a\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableAsynchronousAbort)\r
+ cpsid a\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableIrq)\r
+ cpsie i\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableIrq)\r
+ cpsid i\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableFiq)\r
+ cpsie f\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableFiq)\r
+ cpsid f\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableInterrupts)\r
+ cpsie if\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableInterrupts)\r
+ cpsid if\r
+ isb\r
+ bx LR\r
+\r
+// UINT32\r
+// ReadCCSIDR (\r
+// IN UINT32 CSSELR\r
+// )\r
+ASM_FUNC(ReadCCSIDR)\r
+ mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r
+ isb\r
+ mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r
+ bx lr\r
+\r
+// UINT32\r
+// ReadCLIDR (\r
+// IN UINT32 CSSELR\r
+// )\r
+ASM_FUNC(ReadCLIDR)\r
+ mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadNsacr)\r
+ mrc p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteNsacr)\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+\r
+ INCLUDE AsmMacroExport.inc\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+ RVCT_ASM_EXPORT ArmIsMpCore\r
+ mrc p15,0,R0,c0,c0,5\r
+ // Get Multiprocessing extension (bit31) & U bit (bit30)\r
+ and R0, R0, #0xC0000000\r
+ // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
+ cmp R0, #0x80000000\r
+ moveq R0, #1\r
+ movne R0, #0\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r
+ cpsie a\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r
+ cpsid a\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableIrq\r
+ cpsie i\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableIrq\r
+ cpsid i\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableFiq\r
+ cpsie f\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableFiq\r
+ cpsid f\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableInterrupts\r
+ cpsie if\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableInterrupts\r
+ cpsid if\r
+ isb\r
+ bx LR\r
+\r
+// UINT32\r
+// ReadCCSIDR (\r
+// IN UINT32 CSSELR\r
+// )\r
+ RVCT_ASM_EXPORT ReadCCSIDR\r
+ mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
+ isb\r
+ mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r
+ bx lr\r
+\r
+// UINT32\r
+// ReadCLIDR (\r
+// IN UINT32 CSSELR\r
+// )\r
+ RVCT_ASM_EXPORT ReadCLIDR\r
+ mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadNsacr\r
+ mrc p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteNsacr\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Chipset/ArmV7.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include "ArmV7Lib.h"\r
+#include "ArmLibPrivate.h"\r
+#include <Library/ArmArchTimer.h>\r
+\r
+VOID\r
+EFIAPI\r
+ArmArchTimerReadReg (\r
+ IN ARM_ARCH_TIMER_REGS Reg,\r
+ OUT VOID *DstBuf\r
+ )\r
+{\r
+ // Check if the Generic/Architecture timer is implemented\r
+ if (ArmIsArchTimerImplemented ()) {\r
+ switch (Reg) {\r
+ case CntFrq:\r
+ *((UINTN *)DstBuf) = ArmReadCntFrq ();\r
+ return;\r
+\r
+ case CntPct:\r
+ *((UINT64 *)DstBuf) = ArmReadCntPct ();\r
+ return;\r
+\r
+ case CntkCtl:\r
+ *((UINTN *)DstBuf) = ArmReadCntkCtl();\r
+ return;\r
+\r
+ case CntpTval:\r
+ *((UINTN *)DstBuf) = ArmReadCntpTval ();\r
+ return;\r
+\r
+ case CntpCtl:\r
+ *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r
+ return;\r
+\r
+ case CntvTval:\r
+ *((UINTN *)DstBuf) = ArmReadCntvTval ();\r
+ return;\r
+\r
+ case CntvCtl:\r
+ *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r
+ return;\r
+\r
+ case CntvCt:\r
+ *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r
+ return;\r
+\r
+ case CntpCval:\r
+ *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r
+ return;\r
+\r
+ case CntvCval:\r
+ *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r
+ return;\r
+\r
+ case CntvOff:\r
+ *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r
+ return;\r
+\r
+ case CnthCtl:\r
+ case CnthpTval:\r
+ case CnthpCtl:\r
+ case CnthpCval:\r
+ DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
+ break;\r
+\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
+ }\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
+ ASSERT (0);\r
+ }\r
+\r
+ *((UINT64 *)DstBuf) = 0;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmArchTimerWriteReg (\r
+ IN ARM_ARCH_TIMER_REGS Reg,\r
+ IN VOID *SrcBuf\r
+ )\r
+{\r
+ // Check if the Generic/Architecture timer is implemented\r
+ if (ArmIsArchTimerImplemented ()) {\r
+\r
+ switch (Reg) {\r
+\r
+ case CntFrq:\r
+ ArmWriteCntFrq (*((UINTN *)SrcBuf));\r
+ break;\r
+\r
+ case CntPct:\r
+ DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r
+ break;\r
+\r
+ case CntkCtl:\r
+ ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r
+ break;\r
+\r
+ case CntpTval:\r
+ ArmWriteCntpTval (*((UINTN *)SrcBuf));\r
+ break;\r
+\r
+ case CntpCtl:\r
+ ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r
+ break;\r
+\r
+ case CntvTval:\r
+ ArmWriteCntvTval (*((UINTN *)SrcBuf));\r
+ break;\r
+\r
+ case CntvCtl:\r
+ ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r
+ break;\r
+\r
+ case CntvCt:\r
+ DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r
+ break;\r
+\r
+ case CntpCval:\r
+ ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r
+ break;\r
+\r
+ case CntvCval:\r
+ ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r
+ break;\r
+\r
+ case CntvOff:\r
+ ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r
+ break;\r
+\r
+ case CnthCtl:\r
+ case CnthpTval:\r
+ case CnthpCtl:\r
+ case CnthpCval:\r
+ DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
+ break;\r
+\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
+ }\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
+ ASSERT (0);\r
+ }\r
+}\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+ASM_FUNC(ArmReadCntFrq)\r
+ mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntFrq)\r
+ mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntPct)\r
+ mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntkCtl)\r
+ mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntkCtl)\r
+ mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntpTval)\r
+ mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntpTval)\r
+ mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntpCtl)\r
+ mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntpCtl)\r
+ mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntvTval)\r
+ mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntvTval)\r
+ mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntvCtl)\r
+ mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntvCtl)\r
+ mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntvCt)\r
+ mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntpCval)\r
+ mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntpCval)\r
+ mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntvCval)\r
+ mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntvCval)\r
+ mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadCntvOff)\r
+ mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteCntvOff)\r
+ mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+ INCLUDE AsmMacroExport.inc\r
+ PRESERVE8\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntFrq\r
+ mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntFrq\r
+ mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntPct\r
+ mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntkCtl\r
+ mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntkCtl\r
+ mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntpTval\r
+ mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntpTval\r
+ mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntpCtl\r
+ mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntpCtl\r
+ mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntvTval\r
+ mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntvTval\r
+ mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntvCtl\r
+ mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntvCtl\r
+ mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntvCt\r
+ mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntpCval\r
+ mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntpCval\r
+ mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntvCval\r
+ mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntvCval\r
+ mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadCntvOff\r
+ mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteCntvOff\r
+ mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include <Uefi.h>\r
+#include <Chipset/ArmV7.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include "ArmV7Lib.h"\r
+#include "ArmLibPrivate.h"\r
+\r
+VOID\r
+ArmV7DataCacheOperation (\r
+ IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
+ )\r
+{\r
+ UINTN SavedInterruptState;\r
+\r
+ SavedInterruptState = ArmGetInterruptState ();\r
+ ArmDisableInterrupts ();\r
+\r
+ ArmV7AllDataCachesOperation (DataCacheOperation);\r
+\r
+ ArmDataSynchronizationBarrier ();\r
+\r
+ if (SavedInterruptState) {\r
+ ArmEnableInterrupts ();\r
+ }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ ArmDataSynchronizationBarrier ();\r
+ ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ ArmDataSynchronizationBarrier ();\r
+ ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCache (\r
+ VOID\r
+ )\r
+{\r
+ ArmDataSynchronizationBarrier ();\r
+ ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
+}\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_V7_LIB_H__\r
+#define __ARM_V7_LIB_H__\r
+\r
+#define ID_MMFR0_SHARELVL_SHIFT 12\r
+#define ID_MMFR0_SHARELVL_MASK 0xf\r
+#define ID_MMFR0_SHARELVL_ONE 0\r
+#define ID_MMFR0_SHARELVL_TWO 1\r
+\r
+#define ID_MMFR0_INNERSHR_SHIFT 28\r
+#define ID_MMFR0_INNERSHR_MASK 0xf\r
+#define ID_MMFR0_OUTERSHR_SHIFT 8\r
+#define ID_MMFR0_OUTERSHR_MASK 0xf\r
+\r
+#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
+#define ID_MMFR0_SHR_IGNORED 0xf\r
+\r
+typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);\r
+\r
+VOID\r
+ArmV7AllDataCachesOperation (\r
+ IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
+ );\r
+\r
+#endif // __ARM_V7_LIB_H__\r
+\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+.set DC_ON, (0x1<<2)\r
+.set IC_ON, (0x1<<12)\r
+.set CTRL_M_BIT, (1 << 0)\r
+.set CTRL_C_BIT, (1 << 2)\r
+.set CTRL_B_BIT, (1 << 7)\r
+.set CTRL_I_BIT, (1 << 12)\r
+\r
+\r
+ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
+ bx lr\r
+\r
+ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
+ bx lr\r
+\r
+\r
+ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r
+ mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU\r
+ bx lr\r
+\r
+ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
+ mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU\r
+ mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor\r
+ bx lr\r
+\r
+ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r
+ mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
+ bx lr\r
+\r
+\r
+ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\r
+ bx lr\r
+\r
+\r
+ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\r
+ bx lr\r
+\r
+\r
+ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line\r
+ bx lr\r
+\r
+ASM_FUNC(ArmInvalidateInstructionCache)\r
+ mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableMmu)\r
+ mrc p15,0,R0,c1,c0,0\r
+ orr R0,R0,#1\r
+ mcr p15,0,R0,c1,c0,0\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+\r
+ASM_FUNC(ArmDisableMmu)\r
+ mrc p15,0,R0,c1,c0,0\r
+ bic R0,R0,#1\r
+ mcr p15,0,R0,c1,c0,0 @Disable MMU\r
+\r
+ mcr p15,0,R0,c8,c7,0 @Invalidate TLB\r
+ mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableCachesAndMmu)\r
+ mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
+ bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
+ bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
+ bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write control register\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmMmuEnabled)\r
+ mrc p15,0,R0,c1,c0,0\r
+ and R0,R0,#1\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableDataCache)\r
+ ldr R1,=DC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ orr R0,R0,R1 @Set C bit\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableDataCache)\r
+ ldr R1,=DC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ bic R0,R0,R1 @Clear C bit\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableInstructionCache)\r
+ ldr R1,=IC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ orr R0,R0,R1 @Set I bit\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableInstructionCache)\r
+ ldr R1,=IC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ bic R0,R0,R1 @Clear I bit.\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableSWPInstruction)\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000400\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmEnableBranchPrediction)\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000800\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDisableBranchPrediction)\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ bic r0, r0, #0x00000800\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmSetLowVectors)\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 @ clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmSetHighVectors)\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00002000 @ Set V bit\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmV7AllDataCachesOperation)\r
+ stmfd SP!,{r4-r12, LR}\r
+ mov R1, R0 @ Save Function call in R1\r
+ mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
+ ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)\r
+ mov R3, R3, LSR #23 @ Cache level value (naturally aligned)\r
+ beq L_Finished\r
+ mov R10, #0\r
+\r
+Loop1:\r
+ add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
+ mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
+ and R12, R12, #7 @ get those 3 bits alone\r
+ cmp R12, #2\r
+ blt L_Skip @ no cache or only instruction cache at this level\r
+ mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
+ isb @ isb to sync the change to the CacheSizeID reg\r
+ mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
+ and R2, R12, #0x7 @ extract the line length field\r
+ add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
+@ ldr R4, =0x3FF\r
+ mov R4, #0x400\r
+ sub R4, R4, #1\r
+ ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r
+ clz R5, R4 @ R5 is the bit position of the way size increment\r
+@ ldr R7, =0x00007FFF\r
+ mov R7, #0x00008000\r
+ sub R7, R7, #1\r
+ ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
+\r
+Loop2:\r
+ mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
+\r
+Loop3:\r
+ orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
+ orr R0, R0, R7, LSL R2 @ factor in the index number\r
+\r
+ blx R1\r
+\r
+ subs R9, R9, #1 @ decrement the way number\r
+ bge Loop3\r
+ subs R7, R7, #1 @ decrement the index\r
+ bge Loop2\r
+L_Skip:\r
+ add R10, R10, #2 @ increment the cache number\r
+ cmp R3, R10\r
+ bgt Loop1\r
+\r
+L_Finished:\r
+ dsb\r
+ ldmfd SP!, {r4-r12, lr}\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDataMemoryBarrier)\r
+ dmb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmDataSynchronizationBarrier)\r
+ dsb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmInstructionSynchronizationBarrier)\r
+ isb\r
+ bx LR\r
+\r
+ASM_FUNC(ArmReadVBar)\r
+ # Set the Address of the Vector Table in the VBAR register\r
+ mrc p15, 0, r0, c12, c0, 0\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteVBar)\r
+ # Set the Address of the Vector Table in the VBAR register\r
+ mcr p15, 0, r0, c12, c0, 0\r
+ # Ensure the SCTLR.V bit is clear\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 @ clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx lr\r
+\r
+ASM_FUNC(ArmEnableVFP)\r
+ # Read CPACR (Coprocessor Access Control Register)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
+ orr r0, r0, #0x00f00000\r
+ # Write back CPACR (Coprocessor Access Control Register)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
+ # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
+ mov r0, #0x40000000\r
+#ifndef __clang__\r
+ mcr p10,#0x7,r0,c8,c0,#0\r
+#else\r
+ vmsr fpexc, r0\r
+#endif\r
+ bx lr\r
+\r
+ASM_FUNC(ArmCallWFI)\r
+ wfi\r
+ bx lr\r
+\r
+#Note: Return 0 in Uniprocessor implementation\r
+ASM_FUNC(ArmReadCbar)\r
+ mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadMpidr)\r
+ mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadTpidrurw)\r
+ mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
+ bx lr\r
+\r
+ASM_FUNC(ArmWriteTpidrurw)\r
+ mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW\r
+ bx lr\r
+\r
+ASM_FUNC(ArmIsArchTimerImplemented)\r
+ mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1\r
+ and r0, r0, #0x000F0000\r
+ bx lr\r
+\r
+ASM_FUNC(ArmReadIdPfr1)\r
+ mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+ INCLUDE AsmMacroExport.inc\r
+ PRESERVE8\r
+\r
+DC_ON EQU ( 0x1:SHL:2 )\r
+IC_ON EQU ( 0x1:SHL:12 )\r
+CTRL_M_BIT EQU (1 << 0)\r
+CTRL_C_BIT EQU (1 << 2)\r
+CTRL_B_BIT EQU (1 << 7)\r
+CTRL_I_BIT EQU (1 << 12)\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r
+ mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r
+ mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r
+ mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
+ bx lr\r
+\r
+\r
+ RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
+ mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableMmu\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableMmu\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+\r
+ mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
+ mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
+ mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
+ bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
+ bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
+ bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmMmuEnabled\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ and R0,R0,#1\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableDataCache\r
+ ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableDataCache\r
+ ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableInstructionCache\r
+ ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableInstructionCache\r
+ ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000400\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00000800 ;\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00000800 ;\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmSetLowVectors\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmSetHighVectors\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00002000 ; Set V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
+ stmfd SP!,{r4-r12, LR}\r
+ mov R1, R0 ; Save Function call in R1\r
+ mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
+ ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
+ mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
+ beq Finished\r
+ mov R10, #0\r
+\r
+Loop1\r
+ add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
+ mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
+ and R12, R12, #7 ; get those 3 bits alone\r
+ cmp R12, #2\r
+ blt Skip ; no cache or only instruction cache at this level\r
+ mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
+ isb ; isb to sync the change to the CacheSizeID reg\r
+ mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
+ and R2, R12, #&7 ; extract the line length field\r
+ add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
+ ldr R4, =0x3FF\r
+ ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
+ clz R5, R4 ; R5 is the bit position of the way size increment\r
+ ldr R7, =0x00007FFF\r
+ ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
+\r
+Loop2\r
+ mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
+\r
+Loop3\r
+ orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
+ orr R0, R0, R7, LSL R2 ; factor in the index number\r
+\r
+ blx R1\r
+\r
+ subs R9, R9, #1 ; decrement the way number\r
+ bge Loop3\r
+ subs R7, R7, #1 ; decrement the index\r
+ bge Loop2\r
+Skip\r
+ add R10, R10, #2 ; increment the cache number\r
+ cmp R3, R10\r
+ bgt Loop1\r
+\r
+Finished\r
+ dsb\r
+ ldmfd SP!, {r4-r12, lr}\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
+ dmb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
+ dsb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
+ isb\r
+ bx LR\r
+\r
+ RVCT_ASM_EXPORT ArmReadVBar\r
+ // Set the Address of the Vector Table in the VBAR register\r
+ mrc p15, 0, r0, c12, c0, 0\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteVBar\r
+ // Set the Address of the Vector Table in the VBAR register\r
+ mcr p15, 0, r0, c12, c0, 0\r
+ // Ensure the SCTLR.V bit is clear\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmEnableVFP\r
+ // Read CPACR (Coprocessor Access Control Register)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
+ orr r0, r0, #0x00f00000\r
+ // Write back CPACR (Coprocessor Access Control Register)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
+ // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
+ mov r0, #0x40000000\r
+ mcr p10,#0x7,r0,c8,c0,#0\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmCallWFI\r
+ wfi\r
+ bx lr\r
+\r
+//Note: Return 0 in Uniprocessor implementation\r
+ RVCT_ASM_EXPORT ArmReadCbar\r
+ mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadMpidr\r
+ mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadTpidrurw\r
+ mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmWriteTpidrurw\r
+ mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
+ mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
+ and r0, r0, #0x000F0000\r
+ bx lr\r
+\r
+ RVCT_ASM_EXPORT ArmReadIdPfr1\r
+ mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
+ bx lr\r
+\r
+ END\r
LIBRARY_CLASS = ArmLib\r
\r
[Sources]\r
- Common/ArmLib.c\r
+ ArmLib.c\r
\r
[Sources.ARM]\r
- ArmV7/ArmV7Lib.c\r
- ArmV7/ArmV7ArchTimer.c\r
+ Arm/ArmV7Lib.c\r
+ Arm/ArmV7ArchTimer.c\r
\r
- ArmV7/ArmLibSupportV7.S | GCC\r
- ArmV7/ArmV7Support.S | GCC\r
- ArmV7/ArmV7ArchTimerSupport.S | GCC\r
- Common/Arm/ArmLibSupport.S | GCC\r
+ Arm/ArmLibSupport.S | GCC\r
+ Arm/ArmLibSupportV7.S | GCC\r
+ Arm/ArmV7Support.S | GCC\r
+ Arm/ArmV7ArchTimerSupport.S | GCC\r
\r
- ArmV7/ArmLibSupportV7.asm | RVCT\r
- ArmV7/ArmV7Support.asm | RVCT\r
- ArmV7/ArmV7ArchTimerSupport.asm | RVCT\r
- Common/Arm/ArmLibSupport.asm | RVCT\r
+ Arm/ArmLibSupport.asm | RVCT\r
+ Arm/ArmLibSupportV7.asm | RVCT\r
+ Arm/ArmV7Support.asm | RVCT\r
+ Arm/ArmV7ArchTimerSupport.asm | RVCT\r
\r
[Sources.AARCH64]\r
AArch64/AArch64Lib.c\r
AArch64/AArch64ArchTimer.c\r
\r
+ AArch64/ArmLibSupport.S\r
AArch64/ArmLibSupportV8.S\r
AArch64/AArch64Support.S\r
AArch64/AArch64ArchTimerSupport.S\r
- Common/AArch64/ArmLibSupport.S\r
\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include "ArmLibPrivate.h"\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetAuxCrBit (\r
+ IN UINT32 Bits\r
+ )\r
+{\r
+ UINT32 val = ArmReadAuxCr();\r
+ val |= Bits;\r
+ ArmWriteAuxCr(val);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetAuxCrBit (\r
+ IN UINT32 Bits\r
+ )\r
+{\r
+ UINT32 val = ArmReadAuxCr();\r
+ val &= ~Bits;\r
+ ArmWriteAuxCr(val);\r
+}\r
+\r
+//\r
+// Helper functions for accessing CPUACTLR\r
+//\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+ IN UINTN Bits\r
+ )\r
+{\r
+ UINTN Value;\r
+ Value = ArmReadCpuActlr ();\r
+ Value |= Bits;\r
+ ArmWriteCpuActlr (Value);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuActlrBit (\r
+ IN UINTN Bits\r
+ )\r
+{\r
+ UINTN Value;\r
+ Value = ArmReadCpuActlr ();\r
+ Value &= ~Bits;\r
+ ArmWriteCpuActlr (Value);\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+ VOID\r
+ )\r
+{\r
+ return 4 << ((ArmCacheInfo () >> 16) & 0xf); // CTR_EL0.DminLine\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+ VOID\r
+ )\r
+{\r
+ return 4 << (ArmCacheInfo () & 0xf); // CTR_EL0.IminLine\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmCacheWritebackGranule (\r
+ VOID\r
+ )\r
+{\r
+ UINTN CWG;\r
+\r
+ CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG\r
+\r
+ if (CWG == 0) {\r
+ return SIZE_2KB;\r
+ }\r
+\r
+ return 4 << CWG;\r
+}\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_LIB_PRIVATE_H__\r
+#define __ARM_LIB_PRIVATE_H__\r
+\r
+#define CACHE_SIZE_4_KB (3UL)\r
+#define CACHE_SIZE_8_KB (4UL)\r
+#define CACHE_SIZE_16_KB (5UL)\r
+#define CACHE_SIZE_32_KB (6UL)\r
+#define CACHE_SIZE_64_KB (7UL)\r
+#define CACHE_SIZE_128_KB (8UL)\r
+\r
+#define CACHE_ASSOCIATIVITY_DIRECT (0UL)\r
+#define CACHE_ASSOCIATIVITY_4_WAY (2UL)\r
+#define CACHE_ASSOCIATIVITY_8_WAY (3UL)\r
+\r
+#define CACHE_PRESENT (0UL)\r
+#define CACHE_NOT_PRESENT (1UL)\r
+\r
+#define CACHE_LINE_LENGTH_32_BYTES (2UL)\r
+\r
+#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)\r
+#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)\r
+#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)\r
+#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)\r
+\r
+#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
+#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
+\r
+#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
+\r
+#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+\r
+#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
+#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
+\r
+#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
+#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
+#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
+\r
+VOID\r
+CPSRMaskInsert (\r
+ IN UINT32 Mask,\r
+ IN UINT32 Value\r
+ );\r
+\r
+UINT32\r
+CPSRRead (\r
+ VOID\r
+ );\r
+\r
+UINT32\r
+ReadCCSIDR (\r
+ IN UINT32 CSSELR\r
+ );\r
+\r
+UINT32\r
+ReadCLIDR (\r
+ VOID\r
+ );\r
+\r
+#endif // __ARM_LIB_PRIVATE_H__\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-ASM_FUNC(ArmIsMpCore)\r
- mrc p15,0,R0,c0,c0,5\r
- // Get Multiprocessing extension (bit31) & U bit (bit30)\r
- and R0, R0, #0xC0000000\r
- // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
- cmp R0, #0x80000000\r
- moveq R0, #1\r
- movne R0, #0\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableAsynchronousAbort)\r
- cpsie a\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableAsynchronousAbort)\r
- cpsid a\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableIrq)\r
- cpsie i\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableIrq)\r
- cpsid i\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableFiq)\r
- cpsie f\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableFiq)\r
- cpsid f\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableInterrupts)\r
- cpsie if\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableInterrupts)\r
- cpsid if\r
- isb\r
- bx LR\r
-\r
-// UINT32\r
-// ReadCCSIDR (\r
-// IN UINT32 CSSELR\r
-// )\r
-ASM_FUNC(ReadCCSIDR)\r
- mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r
- isb\r
- mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r
- bx lr\r
-\r
-// UINT32\r
-// ReadCLIDR (\r
-// IN UINT32 CSSELR\r
-// )\r
-ASM_FUNC(ReadCLIDR)\r
- mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadNsacr)\r
- mrc p15, 0, r0, c1, c1, 2\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteNsacr)\r
- mcr p15, 0, r0, c1, c1, 2\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-\r
- RVCT_ASM_EXPORT ArmIsMpCore\r
- mrc p15,0,R0,c0,c0,5\r
- // Get Multiprocessing extension (bit31) & U bit (bit30)\r
- and R0, R0, #0xC0000000\r
- // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
- cmp R0, #0x80000000\r
- moveq R0, #1\r
- movne R0, #0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r
- cpsie a\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r
- cpsid a\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableIrq\r
- cpsie i\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableIrq\r
- cpsid i\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableFiq\r
- cpsie f\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableFiq\r
- cpsid f\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableInterrupts\r
- cpsie if\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableInterrupts\r
- cpsid if\r
- isb\r
- bx LR\r
-\r
-// UINT32\r
-// ReadCCSIDR (\r
-// IN UINT32 CSSELR\r
-// )\r
- RVCT_ASM_EXPORT ReadCCSIDR\r
- mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
- isb\r
- mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r
- bx lr\r
-\r
-// UINT32\r
-// ReadCLIDR (\r
-// IN UINT32 CSSELR\r
-// )\r
- RVCT_ASM_EXPORT ReadCLIDR\r
- mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadNsacr\r
- mrc p15, 0, r0, c1, c1, 2\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteNsacr\r
- mcr p15, 0, r0, c1, c1, 2\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Chipset/ArmV7.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include "ArmV7Lib.h"\r
-#include "ArmLibPrivate.h"\r
-#include <Library/ArmArchTimer.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerReadReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- OUT VOID *DstBuf\r
- )\r
-{\r
- // Check if the Generic/Architecture timer is implemented\r
- if (ArmIsArchTimerImplemented ()) {\r
- switch (Reg) {\r
- case CntFrq:\r
- *((UINTN *)DstBuf) = ArmReadCntFrq ();\r
- return;\r
-\r
- case CntPct:\r
- *((UINT64 *)DstBuf) = ArmReadCntPct ();\r
- return;\r
-\r
- case CntkCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntkCtl();\r
- return;\r
-\r
- case CntpTval:\r
- *((UINTN *)DstBuf) = ArmReadCntpTval ();\r
- return;\r
-\r
- case CntpCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r
- return;\r
-\r
- case CntvTval:\r
- *((UINTN *)DstBuf) = ArmReadCntvTval ();\r
- return;\r
-\r
- case CntvCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r
- return;\r
-\r
- case CntvCt:\r
- *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r
- return;\r
-\r
- case CntpCval:\r
- *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r
- return;\r
-\r
- case CntvCval:\r
- *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r
- return;\r
-\r
- case CntvOff:\r
- *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r
- return;\r
-\r
- case CnthCtl:\r
- case CnthpTval:\r
- case CnthpCtl:\r
- case CnthpCval:\r
- DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
- }\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
- ASSERT (0);\r
- }\r
-\r
- *((UINT64 *)DstBuf) = 0;\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerWriteReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- IN VOID *SrcBuf\r
- )\r
-{\r
- // Check if the Generic/Architecture timer is implemented\r
- if (ArmIsArchTimerImplemented ()) {\r
-\r
- switch (Reg) {\r
-\r
- case CntFrq:\r
- ArmWriteCntFrq (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntPct:\r
- DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r
- break;\r
-\r
- case CntkCtl:\r
- ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntpTval:\r
- ArmWriteCntpTval (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntpCtl:\r
- ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvTval:\r
- ArmWriteCntvTval (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvCtl:\r
- ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvCt:\r
- DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r
- break;\r
-\r
- case CntpCval:\r
- ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r
- break;\r
-\r
- case CntvCval:\r
- ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r
- break;\r
-\r
- case CntvOff:\r
- ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r
- break;\r
-\r
- case CnthCtl:\r
- case CnthpTval:\r
- case CnthpCtl:\r
- case CnthpCval:\r
- DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
- }\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
- ASSERT (0);\r
- }\r
-}\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-ASM_FUNC(ArmReadCntFrq)\r
- mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntFrq)\r
- mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntPct)\r
- mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntkCtl)\r
- mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntkCtl)\r
- mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntpTval)\r
- mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntpTval)\r
- mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntpCtl)\r
- mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntpCtl)\r
- mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntvTval)\r
- mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntvTval)\r
- mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntvCtl)\r
- mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntvCtl)\r
- mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntvCt)\r
- mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntpCval)\r
- mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntpCval)\r
- mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntvCval)\r
- mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntvCval)\r
- mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCntvOff)\r
- mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCntvOff)\r
- mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
- PRESERVE8\r
-\r
- RVCT_ASM_EXPORT ArmReadCntFrq\r
- mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntFrq\r
- mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntPct\r
- mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntkCtl\r
- mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntkCtl\r
- mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntpTval\r
- mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntpTval\r
- mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntpCtl\r
- mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntpCtl\r
- mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvTval\r
- mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvTval\r
- mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvCtl\r
- mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvCtl\r
- mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvCt\r
- mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntpCval\r
- mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntpCval\r
- mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvCval\r
- mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvCval\r
- mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvOff\r
- mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvOff\r
- mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-#include <Uefi.h>\r
-#include <Chipset/ArmV7.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/IoLib.h>\r
-#include "ArmV7Lib.h"\r
-#include "ArmLibPrivate.h"\r
-\r
-VOID\r
-ArmV7DataCacheOperation (\r
- IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
- )\r
-{\r
- UINTN SavedInterruptState;\r
-\r
- SavedInterruptState = ArmGetInterruptState ();\r
- ArmDisableInterrupts ();\r
-\r
- ArmV7AllDataCachesOperation (DataCacheOperation);\r
-\r
- ArmDataSynchronizationBarrier ();\r
-\r
- if (SavedInterruptState) {\r
- ArmEnableInterrupts ();\r
- }\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidateDataCache (\r
- VOID\r
- )\r
-{\r
- ArmDataSynchronizationBarrier ();\r
- ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanInvalidateDataCache (\r
- VOID\r
- )\r
-{\r
- ArmDataSynchronizationBarrier ();\r
- ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCache (\r
- VOID\r
- )\r
-{\r
- ArmDataSynchronizationBarrier ();\r
- ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
-}\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __ARM_V7_LIB_H__\r
-#define __ARM_V7_LIB_H__\r
-\r
-#define ID_MMFR0_SHARELVL_SHIFT 12\r
-#define ID_MMFR0_SHARELVL_MASK 0xf\r
-#define ID_MMFR0_SHARELVL_ONE 0\r
-#define ID_MMFR0_SHARELVL_TWO 1\r
-\r
-#define ID_MMFR0_INNERSHR_SHIFT 28\r
-#define ID_MMFR0_INNERSHR_MASK 0xf\r
-#define ID_MMFR0_OUTERSHR_SHIFT 8\r
-#define ID_MMFR0_OUTERSHR_MASK 0xf\r
-\r
-#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
-#define ID_MMFR0_SHR_IGNORED 0xf\r
-\r
-typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);\r
-\r
-VOID\r
-ArmV7AllDataCachesOperation (\r
- IN ARM_V7_CACHE_OPERATION DataCacheOperation\r
- );\r
-\r
-#endif // __ARM_V7_LIB_H__\r
-\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-.set DC_ON, (0x1<<2)\r
-.set IC_ON, (0x1<<12)\r
-.set CTRL_M_BIT, (1 << 0)\r
-.set CTRL_C_BIT, (1 << 2)\r
-.set CTRL_B_BIT, (1 << 7)\r
-.set CTRL_I_BIT, (1 << 12)\r
-\r
-\r
-ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
- bx lr\r
-\r
-ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
- bx lr\r
-\r
-\r
-ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r
- mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU\r
- bx lr\r
-\r
-ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
- mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU\r
- mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor\r
- bx lr\r
-\r
-ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r
- mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\r
- bx lr\r
-\r
-\r
-ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\r
- bx lr\r
-\r
-\r
-ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line\r
- bx lr\r
-\r
-ASM_FUNC(ArmInvalidateInstructionCache)\r
- mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableMmu)\r
- mrc p15,0,R0,c1,c0,0\r
- orr R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- dsb\r
- isb\r
- bx LR\r
-\r
-\r
-ASM_FUNC(ArmDisableMmu)\r
- mrc p15,0,R0,c1,c0,0\r
- bic R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0 @Disable MMU\r
-\r
- mcr p15,0,R0,c8,c7,0 @Invalidate TLB\r
- mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableCachesAndMmu)\r
- mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
- bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
- bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
- bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r
- mcr p15, 0, r0, c1, c0, 0 @ Write control register\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmMmuEnabled)\r
- mrc p15,0,R0,c1,c0,0\r
- and R0,R0,#1\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableDataCache)\r
- ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableDataCache)\r
- ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableInstructionCache)\r
- ldr R1,=IC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set I bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableInstructionCache)\r
- ldr R1,=IC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear I bit.\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableSWPInstruction)\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000400\r
- mcr p15, 0, r0, c1, c0, 0\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmEnableBranchPrediction)\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDisableBranchPrediction)\r
- mrc p15, 0, r0, c1, c0, 0\r
- bic r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- dsb\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmSetLowVectors)\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 @ clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmSetHighVectors)\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 @ Set V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmV7AllDataCachesOperation)\r
- stmfd SP!,{r4-r12, LR}\r
- mov R1, R0 @ Save Function call in R1\r
- mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
- ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)\r
- mov R3, R3, LSR #23 @ Cache level value (naturally aligned)\r
- beq L_Finished\r
- mov R10, #0\r
-\r
-Loop1:\r
- add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
- mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 @ get those 3 bits alone\r
- cmp R12, #2\r
- blt L_Skip @ no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb @ isb to sync the change to the CacheSizeID reg\r
- mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #0x7 @ extract the line length field\r
- add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
-@ ldr R4, =0x3FF\r
- mov R4, #0x400\r
- sub R4, R4, #1\r
- ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r
- clz R5, R4 @ R5 is the bit position of the way size increment\r
-@ ldr R7, =0x00007FFF\r
- mov R7, #0x00008000\r
- sub R7, R7, #1\r
- ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
-\r
-Loop2:\r
- mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
-\r
-Loop3:\r
- orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 @ factor in the index number\r
-\r
- blx R1\r
-\r
- subs R9, R9, #1 @ decrement the way number\r
- bge Loop3\r
- subs R7, R7, #1 @ decrement the index\r
- bge Loop2\r
-L_Skip:\r
- add R10, R10, #2 @ increment the cache number\r
- cmp R3, R10\r
- bgt Loop1\r
-\r
-L_Finished:\r
- dsb\r
- ldmfd SP!, {r4-r12, lr}\r
- bx LR\r
-\r
-ASM_FUNC(ArmDataMemoryBarrier)\r
- dmb\r
- bx LR\r
-\r
-ASM_FUNC(ArmDataSynchronizationBarrier)\r
- dsb\r
- bx LR\r
-\r
-ASM_FUNC(ArmInstructionSynchronizationBarrier)\r
- isb\r
- bx LR\r
-\r
-ASM_FUNC(ArmReadVBar)\r
- # Set the Address of the Vector Table in the VBAR register\r
- mrc p15, 0, r0, c12, c0, 0\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteVBar)\r
- # Set the Address of the Vector Table in the VBAR register\r
- mcr p15, 0, r0, c12, c0, 0\r
- # Ensure the SCTLR.V bit is clear\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 @ clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmEnableVFP)\r
- # Read CPACR (Coprocessor Access Control Register)\r
- mrc p15, 0, r0, c1, c0, 2\r
- # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
- orr r0, r0, #0x00f00000\r
- # Write back CPACR (Coprocessor Access Control Register)\r
- mcr p15, 0, r0, c1, c0, 2\r
- isb\r
- # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
- mov r0, #0x40000000\r
-#ifndef __clang__\r
- mcr p10,#0x7,r0,c8,c0,#0\r
-#else\r
- vmsr fpexc, r0\r
-#endif\r
- bx lr\r
-\r
-ASM_FUNC(ArmCallWFI)\r
- wfi\r
- bx lr\r
-\r
-#Note: Return 0 in Uniprocessor implementation\r
-ASM_FUNC(ArmReadCbar)\r
- mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadMpidr)\r
- mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadTpidrurw)\r
- mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteTpidrurw)\r
- mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW\r
- bx lr\r
-\r
-ASM_FUNC(ArmIsArchTimerImplemented)\r
- mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1\r
- and r0, r0, #0x000F0000\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadIdPfr1)\r
- mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
- PRESERVE8\r
-\r
-DC_ON EQU ( 0x1:SHL:2 )\r
-IC_ON EQU ( 0x1:SHL:12 )\r
-CTRL_M_BIT EQU (1 << 0)\r
-CTRL_C_BIT EQU (1 << 2)\r
-CTRL_B_BIT EQU (1 << 7)\r
-CTRL_I_BIT EQU (1 << 12)\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r
- mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r
- mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r
- mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
- mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableMmu\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableMmu\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
-\r
- mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
- mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
- mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
- bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
- bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
- bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
- mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmMmuEnabled\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- and R0,R0,#1\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableDataCache\r
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableDataCache\r
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableInstructionCache\r
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableInstructionCache\r
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000400\r
- mcr p15, 0, r0, c1, c0, 0\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00000800 ;\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00000800 ;\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmSetLowVectors\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 ; clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmSetHighVectors\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 ; Set V bit\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
- stmfd SP!,{r4-r12, LR}\r
- mov R1, R0 ; Save Function call in R1\r
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
- ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
- mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
- beq Finished\r
- mov R10, #0\r
-\r
-Loop1\r
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 ; get those 3 bits alone\r
- cmp R12, #2\r
- blt Skip ; no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb ; isb to sync the change to the CacheSizeID reg\r
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #&7 ; extract the line length field\r
- add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
- ldr R4, =0x3FF\r
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
- clz R5, R4 ; R5 is the bit position of the way size increment\r
- ldr R7, =0x00007FFF\r
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
-\r
-Loop2\r
- mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
-\r
-Loop3\r
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 ; factor in the index number\r
-\r
- blx R1\r
-\r
- subs R9, R9, #1 ; decrement the way number\r
- bge Loop3\r
- subs R7, R7, #1 ; decrement the index\r
- bge Loop2\r
-Skip\r
- add R10, R10, #2 ; increment the cache number\r
- cmp R3, R10\r
- bgt Loop1\r
-\r
-Finished\r
- dsb\r
- ldmfd SP!, {r4-r12, lr}\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
- dmb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
- dsb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmReadVBar\r
- // Set the Address of the Vector Table in the VBAR register\r
- mrc p15, 0, r0, c12, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteVBar\r
- // Set the Address of the Vector Table in the VBAR register\r
- mcr p15, 0, r0, c12, c0, 0\r
- // Ensure the SCTLR.V bit is clear\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 ; clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmEnableVFP\r
- // Read CPACR (Coprocessor Access Control Register)\r
- mrc p15, 0, r0, c1, c0, 2\r
- // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
- orr r0, r0, #0x00f00000\r
- // Write back CPACR (Coprocessor Access Control Register)\r
- mcr p15, 0, r0, c1, c0, 2\r
- isb\r
- // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
- mov r0, #0x40000000\r
- mcr p10,#0x7,r0,c8,c0,#0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCallWFI\r
- wfi\r
- bx lr\r
-\r
-//Note: Return 0 in Uniprocessor implementation\r
- RVCT_ASM_EXPORT ArmReadCbar\r
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadMpidr\r
- mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadTpidrurw\r
- mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteTpidrurw\r
- mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
- mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
- and r0, r0, #0x000F0000\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadIdPfr1\r
- mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
-# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-\r
-.set DAIF_RD_FIQ_BIT, (1 << 6)\r
-.set DAIF_RD_IRQ_BIT, (1 << 7)\r
-\r
-ASM_FUNC(ArmReadMidr)\r
- mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
- ret\r
-\r
-ASM_FUNC(ArmCacheInfo)\r
- mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r
- ret\r
-\r
-ASM_FUNC(ArmGetInterruptState)\r
- mrs x0, daif\r
- tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)\r
- cset w0, eq // if Z=1 return 1, else 0\r
- ret\r
-\r
-ASM_FUNC(ArmGetFiqState)\r
- mrs x0, daif\r
- tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)\r
- cset w0, eq // if Z=1 return 1, else 0\r
- ret\r
-\r
-ASM_FUNC(ArmWriteCpacr)\r
- msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r
- ret\r
-\r
-ASM_FUNC(ArmWriteAuxCr)\r
- EL1_OR_EL2(x1)\r
-1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
- ret\r
-2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
- ret\r
-\r
-ASM_FUNC(ArmReadAuxCr)\r
- EL1_OR_EL2(x1)\r
-1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
- ret\r
-2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
- ret\r
-\r
-ASM_FUNC(ArmSetTTBR0)\r
- EL1_OR_EL2_OR_EL3(x1)\r
-1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r
- b 4f\r
-2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)\r
- b 4f\r
-3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)\r
-4:isb\r
- ret\r
-\r
-ASM_FUNC(ArmGetTTBR0BaseAddress)\r
- EL1_OR_EL2(x1)\r
-1:mrs x0, ttbr0_el1\r
- b 3f\r
-2:mrs x0, ttbr0_el2\r
-3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */\r
- isb\r
- ret\r
-\r
-ASM_FUNC(ArmGetTCR)\r
- EL1_OR_EL2_OR_EL3(x1)\r
-1:mrs x0, tcr_el1\r
- b 4f\r
-2:mrs x0, tcr_el2\r
- b 4f\r
-3:mrs x0, tcr_el3\r
-4:isb\r
- ret\r
-\r
-ASM_FUNC(ArmSetTCR)\r
- EL1_OR_EL2_OR_EL3(x1)\r
-1:msr tcr_el1, x0\r
- b 4f\r
-2:msr tcr_el2, x0\r
- b 4f\r
-3:msr tcr_el3, x0\r
-4:isb\r
- ret\r
-\r
-ASM_FUNC(ArmGetMAIR)\r
- EL1_OR_EL2_OR_EL3(x1)\r
-1:mrs x0, mair_el1\r
- b 4f\r
-2:mrs x0, mair_el2\r
- b 4f\r
-3:mrs x0, mair_el3\r
-4:isb\r
- ret\r
-\r
-ASM_FUNC(ArmSetMAIR)\r
- EL1_OR_EL2_OR_EL3(x1)\r
-1:msr mair_el1, x0\r
- b 4f\r
-2:msr mair_el2, x0\r
- b 4f\r
-3:msr mair_el3, x0\r
-4:isb\r
- ret\r
-\r
-\r
-//\r
-//VOID\r
-//ArmUpdateTranslationTableEntry (\r
-// IN VOID *TranslationTableEntry // X0\r
-// IN VOID *MVA // X1\r
-// );\r
-ASM_FUNC(ArmUpdateTranslationTableEntry)\r
- dc civac, x0 // Clean and invalidate data line\r
- dsb sy\r
- EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi vaae1, x1 // TLB Invalidate VA , EL1\r
- b 4f\r
-2: tlbi vae2, x1 // TLB Invalidate VA , EL2\r
- b 4f\r
-3: tlbi vae3, x1 // TLB Invalidate VA , EL3\r
-4: dsb sy\r
- isb\r
- ret\r
-\r
-ASM_FUNC(ArmInvalidateTlb)\r
- EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi vmalle1\r
- b 4f\r
-2: tlbi alle2\r
- b 4f\r
-3: tlbi alle3\r
-4: dsb sy\r
- isb\r
- ret\r
-\r
-ASM_FUNC(ArmWriteCptr)\r
- msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r
- ret\r
-\r
-ASM_FUNC(ArmWriteScr)\r
- msr scr_el3, x0 // Secure configuration register EL3\r
- isb\r
- ret\r
-\r
-ASM_FUNC(ArmWriteMVBar)\r
- msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3\r
- ret\r
-\r
-ASM_FUNC(ArmCallWFE)\r
- wfe\r
- ret\r
-\r
-ASM_FUNC(ArmCallSEV)\r
- sev\r
- ret\r
-\r
-ASM_FUNC(ArmReadCpuActlr)\r
- mrs x0, S3_1_c15_c2_0\r
- ret\r
-\r
-ASM_FUNC(ArmWriteCpuActlr)\r
- msr S3_1_c15_c2_0, x0\r
- dsb sy\r
- isb\r
- ret\r
-\r
-ASM_FUNC(ArmReadSctlr)\r
- EL1_OR_EL2_OR_EL3(x1)\r
-1:mrs x0, sctlr_el1\r
- ret\r
-2:mrs x0, sctlr_el2\r
- ret\r
-3:mrs x0, sctlr_el3\r
-4:ret\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
-# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-ASM_FUNC(ArmReadMidr)\r
- mrc p15,0,R0,c0,c0,0\r
- bx LR\r
-\r
-ASM_FUNC(ArmCacheInfo)\r
- mrc p15,0,R0,c0,c0,1\r
- bx LR\r
-\r
-ASM_FUNC(ArmGetInterruptState)\r
- mrs R0,CPSR\r
- tst R0,#0x80 @Check if IRQ is enabled.\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
-ASM_FUNC(ArmGetFiqState)\r
- mrs R0,CPSR\r
- tst R0,#0x40 @Check if FIQ is enabled.\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
-ASM_FUNC(ArmSetDomainAccessControl)\r
- mcr p15,0,r0,c3,c0,0\r
- bx lr\r
-\r
-ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert\r
- stmfd sp!, {r4-r12, lr} @ save all the banked registers\r
- mov r3, sp @ copy the stack pointer into a non-banked register\r
- mrs r2, cpsr @ read the cpsr\r
- bic r2, r2, r0 @ clear mask in the cpsr\r
- and r1, r1, r0 @ clear bits outside the mask in the input\r
- orr r2, r2, r1 @ set field\r
- msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r
- isb\r
- mov sp, r3 @ restore stack pointer\r
- ldmfd sp!, {r4-r12, lr} @ restore registers\r
- bx lr @ return (hopefully thumb-safe!)\r
-\r
-ASM_FUNC(CPSRRead)\r
- mrs r0, cpsr\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCpacr)\r
- mrc p15, 0, r0, c1, c0, 2\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCpacr)\r
- mcr p15, 0, r0, c1, c0, 2\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteAuxCr)\r
- mcr p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadAuxCr)\r
- mrc p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
-ASM_FUNC(ArmSetTTBR0)\r
- mcr p15,0,r0,c2,c0,0\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmSetTTBCR)\r
- mcr p15, 0, r0, c2, c0, 2\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmGetTTBR0BaseAddress)\r
- mrc p15,0,r0,c2,c0,0\r
- MOV32 (r1, 0xFFFFC000)\r
- and r0, r0, r1\r
- isb\r
- bx lr\r
-\r
-//\r
-//VOID\r
-//ArmUpdateTranslationTableEntry (\r
-// IN VOID *TranslationTableEntry // R0\r
-// IN VOID *MVA // R1\r
-// );\r
-ASM_FUNC(ArmUpdateTranslationTableEntry)\r
- mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r
- dsb\r
- mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA\r
- mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
- dsb\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmInvalidateTlb)\r
- mov r0,#0\r
- mcr p15,0,r0,c8,c7,0\r
- mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
- dsb\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadScr)\r
- mrc p15, 0, r0, c1, c1, 0\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteScr)\r
- mcr p15, 0, r0, c1, c1, 0\r
- isb\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadHVBar)\r
- mrc p15, 4, r0, c12, c0, 0\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteHVBar)\r
- mcr p15, 4, r0, c12, c0, 0\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadMVBar)\r
- mrc p15, 0, r0, c12, c0, 1\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteMVBar)\r
- mcr p15, 0, r0, c12, c0, 1\r
- bx lr\r
-\r
-ASM_FUNC(ArmCallWFE)\r
- wfe\r
- bx lr\r
-\r
-ASM_FUNC(ArmCallSEV)\r
- sev\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadSctlr)\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- bx lr\r
-\r
-ASM_FUNC(ArmReadCpuActlr)\r
- mrc p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
-ASM_FUNC(ArmWriteCpuActlr)\r
- mcr p15, 0, r0, c1, c0, 1\r
- dsb\r
- isb\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT ArmReadMidr\r
- mrc p15,0,R0,c0,c0,0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmCacheInfo\r
- mrc p15,0,R0,c0,c0,1\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmGetInterruptState\r
- mrs R0,CPSR\r
- tst R0,#0x80 // Check if IRQ is enabled.\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmGetFiqState\r
- mrs R0,CPSR\r
- tst R0,#0x40 // Check if FIQ is enabled.\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
- mcr p15,0,r0,c3,c0,0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT CPSRMaskInsert\r
- stmfd sp!, {r4-r12, lr} // save all the banked registers\r
- mov r3, sp // copy the stack pointer into a non-banked register\r
- mrs r2, cpsr // read the cpsr\r
- bic r2, r2, r0 // clear mask in the cpsr\r
- and r1, r1, r0 // clear bits outside the mask in the input\r
- orr r2, r2, r1 // set field\r
- msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r
- isb\r
- mov sp, r3 // restore stack pointer\r
- ldmfd sp!, {r4-r12, lr} // restore registers\r
- bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
-\r
- RVCT_ASM_EXPORT CPSRRead\r
- mrs r0, cpsr\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCpacr\r
- mrc p15, 0, r0, c1, c0, 2\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCpacr\r
- mcr p15, 0, r0, c1, c0, 2\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteAuxCr\r
- mcr p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadAuxCr\r
- mrc p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmSetTTBR0\r
- mcr p15,0,r0,c2,c0,0\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmSetTTBCR\r
- mcr p15, 0, r0, c2, c0, 2\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
- mrc p15,0,r0,c2,c0,0\r
- MOV32 r1, 0xFFFFC000\r
- and r0, r0, r1\r
- isb\r
- bx lr\r
-\r
-//\r
-//VOID\r
-//ArmUpdateTranslationTableEntry (\r
-// IN VOID *TranslationTableEntry // R0\r
-// IN VOID *MVA // R1\r
-// );\r
- RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
- mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
- dsb\r
- mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
- mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
- dsb\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateTlb\r
- mov r0,#0\r
- mcr p15,0,r0,c8,c7,0\r
- mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
- dsb\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadScr\r
- mrc p15, 0, r0, c1, c1, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteScr\r
- mcr p15, 0, r0, c1, c1, 0\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadHVBar\r
- mrc p15, 4, r0, c12, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteHVBar\r
- mcr p15, 4, r0, c12, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadMVBar\r
- mrc p15, 0, r0, c12, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteMVBar\r
- mcr p15, 0, r0, c12, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCallWFE\r
- wfe\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCallSEV\r
- sev\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadSctlr\r
- mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmReadCpuActlr\r
- mrc p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCpuActlr\r
- mcr p15, 0, r0, c1, c0, 1\r
- dsb\r
- isb\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-\r
-#include <Library/ArmLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include "ArmLibPrivate.h"\r
-\r
-VOID\r
-EFIAPI\r
-ArmSetAuxCrBit (\r
- IN UINT32 Bits\r
- )\r
-{\r
- UINT32 val = ArmReadAuxCr();\r
- val |= Bits;\r
- ArmWriteAuxCr(val);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmUnsetAuxCrBit (\r
- IN UINT32 Bits\r
- )\r
-{\r
- UINT32 val = ArmReadAuxCr();\r
- val &= ~Bits;\r
- ArmWriteAuxCr(val);\r
-}\r
-\r
-//\r
-// Helper functions for accessing CPUACTLR\r
-//\r
-\r
-VOID\r
-EFIAPI\r
-ArmSetCpuActlrBit (\r
- IN UINTN Bits\r
- )\r
-{\r
- UINTN Value;\r
- Value = ArmReadCpuActlr ();\r
- Value |= Bits;\r
- ArmWriteCpuActlr (Value);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmUnsetCpuActlrBit (\r
- IN UINTN Bits\r
- )\r
-{\r
- UINTN Value;\r
- Value = ArmReadCpuActlr ();\r
- Value &= ~Bits;\r
- ArmWriteCpuActlr (Value);\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheLineLength (\r
- VOID\r
- )\r
-{\r
- return 4 << ((ArmCacheInfo () >> 16) & 0xf); // CTR_EL0.DminLine\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheLineLength (\r
- VOID\r
- )\r
-{\r
- return 4 << (ArmCacheInfo () & 0xf); // CTR_EL0.IminLine\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmCacheWritebackGranule (\r
- VOID\r
- )\r
-{\r
- UINTN CWG;\r
-\r
- CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG\r
-\r
- if (CWG == 0) {\r
- return SIZE_2KB;\r
- }\r
-\r
- return 4 << CWG;\r
-}\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __ARM_LIB_PRIVATE_H__\r
-#define __ARM_LIB_PRIVATE_H__\r
-\r
-#define CACHE_SIZE_4_KB (3UL)\r
-#define CACHE_SIZE_8_KB (4UL)\r
-#define CACHE_SIZE_16_KB (5UL)\r
-#define CACHE_SIZE_32_KB (6UL)\r
-#define CACHE_SIZE_64_KB (7UL)\r
-#define CACHE_SIZE_128_KB (8UL)\r
-\r
-#define CACHE_ASSOCIATIVITY_DIRECT (0UL)\r
-#define CACHE_ASSOCIATIVITY_4_WAY (2UL)\r
-#define CACHE_ASSOCIATIVITY_8_WAY (3UL)\r
-\r
-#define CACHE_PRESENT (0UL)\r
-#define CACHE_NOT_PRESENT (1UL)\r
-\r
-#define CACHE_LINE_LENGTH_32_BYTES (2UL)\r
-\r
-#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)\r
-#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)\r
-#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)\r
-#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)\r
-\r
-#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
-#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
-\r
-#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
-#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
-\r
-#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
-\r
-#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
-#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
-\r
-#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
-#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
-#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
-\r
-VOID\r
-CPSRMaskInsert (\r
- IN UINT32 Mask,\r
- IN UINT32 Value\r
- );\r
-\r
-UINT32\r
-CPSRRead (\r
- VOID\r
- );\r
-\r
-UINT32\r
-ReadCCSIDR (\r
- IN UINT32 CSSELR\r
- );\r
-\r
-UINT32\r
-ReadCLIDR (\r
- VOID\r
- );\r
-\r
-#endif // __ARM_LIB_PRIVATE_H__\r
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