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hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
[mirror_qemu.git] / hw / arm / aspeed.c
CommitLineData
327d8e4e
AJ		 1/*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12#include "qemu/osdep.h"
da34e65c 13#include "qapi/error.h"
12ec8bd5 14#include "hw/arm/boot.h"
fca9ca1b 15#include "hw/arm/aspeed.h"
00442402 16#include "hw/arm/aspeed_soc.h"
3ec75e39 17#include "hw/i2c/i2c_mux_pca954x.h"
93198b6c 18#include "hw/i2c/smbus_eeprom.h"
044475f3 19#include "hw/misc/pca9552.h"
9618ebae 20#include "hw/nvram/eeprom_at24c.h"
5e9ae4b1 21#include "hw/sensor/tmp105.h"
7cfbde5e 22#include "hw/misc/led.h"
a27bd6c7 23#include "hw/qdev-properties.h"
e1ad9bc4 24#include "sysemu/block-backend.h"
fa699e80 25#include "sysemu/reset.h"
d769a1da
CLG		 26#include "hw/loader.h"
27#include "qemu/error-report.h"
a9df9622 28#include "qemu/units.h"
66c895b8 29#include "hw/qdev-clock.h"
d2b3eaef 30#include "sysemu/sysemu.h"
327d8e4e 31
74fb1f38 32static struct arm_boot_info aspeed_board_binfo = {
b033271f 33 .board_id = -1, /* device-tree-only board */
327d8e4e
AJ		 34};
35
612b219a 36struct AspeedMachineState {
888b2b03
PMD		 37 /* Private */
38 MachineState parent_obj;
39 /* Public */
40
ff90606f 41 AspeedSoCState soc;
888b2b03 42 bool mmio_exec;
9820e52f
CLG		 43 char *fmc_model;
44 char *spi_model;
ea066d39 45};
327d8e4e 46
ef17f836 47/* Palmetto hardware value: 0x120CE416 */
8da33ef7
CLG		 48#define PALMETTO_BMC_HW_STRAP1 ( \
49 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
50 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
51 SCU_AST2400_HW_STRAP_ACPI_DIS | \
52 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
53 SCU_HW_STRAP_VGA_CLASS_CODE | \
54 SCU_HW_STRAP_LPC_RESET_PIN | \
55 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
56 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
57 SCU_HW_STRAP_SPI_WIDTH | \
58 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
59 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
60
40a38df5
ES		 61/* TODO: Find the actual hardware value */
62#define SUPERMICROX11_BMC_HW_STRAP1 ( \
63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
65 SCU_AST2400_HW_STRAP_ACPI_DIS | \
66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
67 SCU_HW_STRAP_VGA_CLASS_CODE | \
68 SCU_HW_STRAP_LPC_RESET_PIN | \
69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
71 SCU_HW_STRAP_SPI_WIDTH | \
72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
74
47936597
GR		 75/* TODO: Find the actual hardware value */
76#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
77 AST2500_HW_STRAP1_DEFAULTS | \
78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
80 SCU_AST2500_HW_STRAP_UART_DEBUG | \
81 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
82 SCU_HW_STRAP_SPI_WIDTH | \
83 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
84
ef17f836 85/* AST2500 evb hardware value: 0xF100C2E6 */
9a7c1750
CLG		 86#define AST2500_EVB_HW_STRAP1 (( \
87 AST2500_HW_STRAP1_DEFAULTS | \
88 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
89 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
90 SCU_AST2500_HW_STRAP_UART_DEBUG | \
91 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
92 SCU_HW_STRAP_MAC1_RGMII | \
93 SCU_HW_STRAP_MAC0_RGMII) & \
94 ~SCU_HW_STRAP_2ND_BOOT_WDT)
95
ef17f836
CLG		 96/* Romulus hardware value: 0xF10AD206 */
97#define ROMULUS_BMC_HW_STRAP1 ( \
98 AST2500_HW_STRAP1_DEFAULTS | \
99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
101 SCU_AST2500_HW_STRAP_UART_DEBUG | \
102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
103 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
104 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
105
143b040f
PW		 106/* Sonorapass hardware value: 0xF100D216 */
107#define SONORAPASS_BMC_HW_STRAP1 ( \
108 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
109 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
110 SCU_AST2500_HW_STRAP_UART_DEBUG | \
111 SCU_AST2500_HW_STRAP_RESERVED28 | \
112 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
113 SCU_HW_STRAP_VGA_CLASS_CODE | \
114 SCU_HW_STRAP_LPC_RESET_PIN | \
115 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
116 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
117 SCU_HW_STRAP_VGA_BIOS_ROM | \
118 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
119 SCU_AST2500_HW_STRAP_RESERVED1)
120
95f068c8
JW		 121#define G220A_BMC_HW_STRAP1 ( \
122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
124 SCU_AST2500_HW_STRAP_UART_DEBUG | \
125 SCU_AST2500_HW_STRAP_RESERVED28 | \
126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
127 SCU_HW_STRAP_2ND_BOOT_WDT | \
128 SCU_HW_STRAP_VGA_CLASS_CODE | \
129 SCU_HW_STRAP_LPC_RESET_PIN | \
130 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
131 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
133 SCU_AST2500_HW_STRAP_RESERVED1)
134
82b6a3f6
JW		 135/* FP5280G2 hardware value: 0XF100D286 */
136#define FP5280G2_BMC_HW_STRAP1 ( \
137 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
138 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
139 SCU_AST2500_HW_STRAP_UART_DEBUG | \
140 SCU_AST2500_HW_STRAP_RESERVED28 | \
141 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
142 SCU_HW_STRAP_VGA_CLASS_CODE | \
143 SCU_HW_STRAP_LPC_RESET_PIN | \
144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
145 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
146 SCU_HW_STRAP_MAC1_RGMII | \
147 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
148 SCU_AST2500_HW_STRAP_RESERVED1)
149
62c2c2eb
CLG		 150/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
151#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
152
9cccb912
PV		 153/* Quanta-Q71l hardware value */
154#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
155 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
156 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
157 SCU_AST2400_HW_STRAP_ACPI_DIS | \
158 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
159 SCU_HW_STRAP_VGA_CLASS_CODE | \
160 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
161 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
162 SCU_HW_STRAP_SPI_WIDTH | \
163 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
164 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
165
ccc2c418
CLG		 166/* AST2600 evb hardware value */
167#define AST2600_EVB_HW_STRAP1 0x000000C0
168#define AST2600_EVB_HW_STRAP2 0x00000003
169
63ceb818
CLG		 170/* Tacoma hardware value */
171#define TACOMA_BMC_HW_STRAP1 0x00000000
7582591a 172#define TACOMA_BMC_HW_STRAP2 0x00000040
63ceb818 173
58e52bdb 174/* Rainier hardware value: (QEMU prototype) */
b6d1df64
JS		 175#define RAINIER_BMC_HW_STRAP1 0x00422016
176#define RAINIER_BMC_HW_STRAP2 0x80000848
58e52bdb 177
febbe308
PD		 178/* Fuji hardware value */
179#define FUJI_BMC_HW_STRAP1 0x00000000
180#define FUJI_BMC_HW_STRAP2 0x00000000
181
a20c54b1
PW		 182/* Bletchley hardware value */
183/* TODO: Leave same as EVB for now. */
184#define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
185#define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
186
fb6b3c8d
JHY		 187/* Qualcomm DC-SCM hardware value */
188#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
189#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
190
9bb6d140
JS		 191#define AST_SMP_MAILBOX_BASE 0x1e6e2180
192#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
193#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
194#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
195#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
196#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
197#define AST_SMP_MBOX_GOSIGN 0xabbaab00
198
199static void aspeed_write_smpboot(ARMCPU *cpu,
200 const struct arm_boot_info *info)
201{
202 static const uint32_t poll_mailbox_ready[] = {
203 /*
204 * r2 = per-cpu go sign value
205 * r1 = AST_SMP_MBOX_FIELD_ENTRY
206 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
207 */
208 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
209 0xe21000ff, /* ands r0, r0, #255 */
210 0xe59f201c, /* ldr r2, [pc, #28] */
211 0xe1822000, /* orr r2, r2, r0 */
212
213 0xe59f1018, /* ldr r1, [pc, #24] */
214 0xe59f0018, /* ldr r0, [pc, #24] */
215
216 0xe320f002, /* wfe */
217 0xe5904000, /* ldr r4, [r0] */
218 0xe1520004, /* cmp r2, r4 */
219 0x1afffffb, /* bne <wfe> */
220 0xe591f000, /* ldr pc, [r1] */
221 AST_SMP_MBOX_GOSIGN,
222 AST_SMP_MBOX_FIELD_ENTRY,
223 AST_SMP_MBOX_FIELD_GOSIGN,
224 };
225
226 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
227 sizeof(poll_mailbox_ready),
228 info->smp_loader_start);
229}
230
231static void aspeed_reset_secondary(ARMCPU *cpu,
232 const struct arm_boot_info *info)
233{
234 AddressSpace *as = arm_boot_address_space(cpu, info);
235 CPUState *cs = CPU(cpu);
236
237 /* info->smp_bootreg_addr */
238 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
239 MEMTXATTRS_UNSPECIFIED, NULL);
240 cpu_set_pc(cs, info->smp_loader_start);
241}
242
d769a1da
CLG		 243#define FIRMWARE_ADDR 0x0
244
245static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
246 Error **errp)
247{
248 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
05e6e40a 249 g_autofree void *storage = NULL;
0c7209be
CLG		 250 int64_t size;
251
252 /* The block backend size should have already been 'validated' by
253 * the creation of the m25p80 object.
254 */
255 size = blk_getlength(blk);
256 if (size <= 0) {
257 error_setg(errp, "failed to get flash size");
258 return;
259 }
d769a1da 260
0c7209be
CLG		 261 if (rom_size > size) {
262 rom_size = size;
d769a1da
CLG		 263 }
264
05e6e40a 265 storage = g_malloc0(rom_size);
a9262f55 266 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
d769a1da
CLG		 267 error_setg(errp, "failed to read the initial flash content");
268 return;
269 }
270
271 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
d769a1da
CLG		 272}
273
1099ad10 274void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
9bd4ac61 275 unsigned int count, int unit0)
e1ad9bc4 276{
179b2058
PW		 277 int i;
278
279 if (!flashtype) {
280 return;
281 }
e1ad9bc4 282
9bd4ac61 283 for (i = 0; i < count; ++i) {
8ec239f2 284 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
e1ad9bc4 285 qemu_irq cs_line;
a7d78bef 286 DeviceState *dev;
e1ad9bc4 287
a7d78bef 288 dev = qdev_new(flashtype);
e1ad9bc4 289 if (dinfo) {
a7d78bef 290 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
e1ad9bc4 291 }
a7d78bef 292 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
e1ad9bc4 293
a7d78bef 294 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
e1ad9bc4
CLG		 295 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
296 }
297}
298
a29e3e12
AJ		 299static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
300{
301 DeviceState *card;
302
756f739b
PMD		 303 if (!dinfo) {
304 return;
a29e3e12 305 }
756f739b
PMD		 306 card = qdev_new(TYPE_SD_CARD);
307 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
308 &error_fatal);
3e80f690
MA		 309 qdev_realize_and_unref(card,
310 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
311 &error_fatal);
a29e3e12
AJ		 312}
313
d2b3eaef
PD		 314static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
315{
316 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
317 AspeedSoCState *s = &bmc->soc;
318 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
319
320 aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
321 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
322 if (uart == amc->uart_default) {
323 continue;
324 }
325 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
326 }
327}
328
baa4732b 329static void aspeed_machine_init(MachineState *machine)
327d8e4e 330{
888b2b03 331 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
baa4732b 332 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
b033271f 333 AspeedSoCClass *sc;
d769a1da 334 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
2bea128c 335 int i;
d3bad7e7 336 NICInfo *nd = &nd_table[0];
327d8e4e 337
9fc7fc4d 338 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
327d8e4e 339
b033271f
CLG		 340 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
341
533eb415 342 /*
346160cb
CLG		 343 * This will error out if the RAM size is not supported by the
344 * memory controller of the SoC.
533eb415 345 */
6e504a98 346 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
533eb415
IM		 347 &error_fatal);
348
d3bad7e7
CLG		 349 for (i = 0; i < sc->macs_num; i++) {
350 if ((amc->macs_mask & (1 << i)) && nd->used) {
351 qemu_check_nic_model(nd, TYPE_FTGMAC100);
352 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
353 nd++;
354 }
355 }
356
5325cc34 357 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
87e79af0 358 &error_abort);
5325cc34 359 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
ccc2c418 360 &error_abort);
4dd9d554
PD		 361 object_property_set_link(OBJECT(&bmc->soc), "memory",
362 OBJECT(get_system_memory()), &error_abort);
5325cc34 363 object_property_set_link(OBJECT(&bmc->soc), "dram",
0df2d9a6 364 OBJECT(machine->ram), &error_abort);
b6e70d1d
JS		 365 if (machine->kernel_filename) {
366 /*
367 * When booting with a -kernel command line there is no u-boot
368 * that runs to unlock the SCU. In this case set the default to
369 * be unlocked as the kernel expects
370 */
5325cc34
MA		 371 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
372 ASPEED_SCU_PROT_KEY, &error_abort);
b6e70d1d 373 }
d2b3eaef 374 connect_serial_hds_to_uarts(bmc);
ce189ab2 375 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
327d8e4e 376
8ec239f2
MA		 377 aspeed_board_init_flashes(&bmc->soc.fmc,
378 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
9bd4ac61 379 amc->num_cs, 0);
8ec239f2
MA		 380 aspeed_board_init_flashes(&bmc->soc.spi[0],
381 bmc->spi_model ? bmc->spi_model : amc->spi_model,
9bd4ac61 382 1, amc->num_cs);
74fb1f38 383
d769a1da
CLG		 384 /* Install first FMC flash content as a boot rom. */
385 if (drive0) {
386 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
387 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
6bb55e79 388 uint64_t size = memory_region_size(&fl->mmio);
d769a1da
CLG		 389
390 /*
391 * create a ROM region using the default mapping window size of
93bf276d
CLG		 392 * the flash module. The window size is 64MB for the AST2400
393 * SoC and 128MB for the AST2500 SoC, which is twice as big as
394 * needed by the flash modules of the Aspeed machines.
d769a1da 395 */
1a15311a 396 if (ASPEED_MACHINE(machine)->mmio_exec) {
f489960d 397 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
6bb55e79 398 &fl->mmio, 0, size);
1a15311a
CLG		 399 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
400 boot_rom);
401 } else {
f489960d 402 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
6bb55e79 403 size, &error_abort);
1a15311a
CLG		 404 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
405 boot_rom);
6bb55e79 406 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
1a15311a 407 }
d769a1da
CLG		 408 }
409
b7f1a0cb 410 if (machine->kernel_filename && sc->num_cpus > 1) {
9bb6d140
JS		 411 /* With no u-boot we must set up a boot stub for the secondary CPU */
412 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
f489960d 413 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
9bb6d140
JS		 414 0x80, &error_abort);
415 memory_region_add_subregion(get_system_memory(),
416 AST_SMP_MAILBOX_BASE, smpboot);
417
418 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
419 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
420 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
421 }
422
6e504a98 423 aspeed_board_binfo.ram_size = machine->ram_size;
347df6f8 424 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
e1ad9bc4 425
baa4732b
CLG		 426 if (amc->i2c_init) {
427 amc->i2c_init(bmc);
2cf6cb50
CLG		 428 }
429
0e2c24c6 430 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
8ec239f2
MA		 431 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
432 drive_get(IF_SD, 0, i));
a29e3e12 433 }
2bea128c 434
a29e3e12 435 if (bmc->soc.emmc.num_slots) {
8ec239f2
MA		 436 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
437 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
2bea128c
EJ		 438 }
439
2744ece8 440 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
74fb1f38 441}
b033271f 442
612b219a 443static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
2cf6cb50
CLG		 444{
445 AspeedSoCState *soc = &bmc->soc;
a87e81b9 446 DeviceState *dev;
3d165f12 447 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
2cf6cb50
CLG		 448
449 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
450 * enough to provide basic RTC features. Alarms will be missing */
1373b15b 451 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
a87e81b9 452
7a204cbd 453 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
3d165f12
CLG		 454 eeprom_buf);
455
a87e81b9 456 /* add a TMP423 temperature sensor */
1373b15b
PMD		 457 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
458 "tmp423", 0x4c));
5325cc34
MA		 459 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
460 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
461 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
462 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
2cf6cb50
CLG		 463}
464
9cccb912
PV		 465static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
466{
467 AspeedSoCState *soc = &bmc->soc;
468
469 /*
470 * The quanta-q71l platform expects tmp75s which are compatible with
471 * tmp105s.
472 */
473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
475 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
476
477 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
478 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
479 /* TODO: Add Memory Riser i2c mux and eeproms. */
480
3ec75e39
PV		 481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
483
9cccb912 484 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
3ec75e39
PV		 485
486 /* i2c-7 */
487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
9cccb912
PV		 488 /* - i2c@0: pmbus@59 */
489 /* - i2c@1: pmbus@58 */
490 /* - i2c@2: pmbus@58 */
491 /* - i2c@3: pmbus@59 */
3ec75e39 492
9cccb912
PV		 493 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
494 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
495}
496
612b219a 497static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
2cf6cb50
CLG		 498{
499 AspeedSoCState *soc = &bmc->soc;
3d165f12
CLG		 500 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
501
7a204cbd 502 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
3d165f12 503 eeprom_buf);
2cf6cb50
CLG		 504
505 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
1373b15b 506 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
044475f3 507 TYPE_TMP105, 0x4d);
2cf6cb50
CLG		 508}
509
612b219a 510static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
ccc2c418 511{
52bcd997
HC		 512 AspeedSoCState *soc = &bmc->soc;
513 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
514
515 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
516 eeprom_buf);
517
518 /* LM75 is compatible with TMP105 driver */
519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
520 TYPE_TMP105, 0x4d);
ccc2c418
CLG		 521}
522
612b219a 523static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
6c4567c7
CLG		 524{
525 AspeedSoCState *soc = &bmc->soc;
526
527 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
528 * good enough */
1373b15b 529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
6c4567c7
CLG		 530}
531
f4aec252
CLG		 532static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
533{
534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
535 TYPE_PCA9552, addr);
536}
537
612b219a 538static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
143b040f
PW		 539{
540 AspeedSoCState *soc = &bmc->soc;
541
542 /* bus 2 : */
1373b15b
PMD		 543 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
143b040f
PW		 545 /* bus 2 : pca9546 @ 0x73 */
546
547 /* bus 3 : pca9548 @ 0x70 */
548
549 /* bus 4 : */
550 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
7a204cbd 551 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
143b040f
PW		 552 eeprom4_54);
553 /* PCA9539 @ 0x76, but PCA9552 is compatible */
f4aec252 554 create_pca9552(soc, 4, 0x76);
143b040f 555 /* PCA9539 @ 0x77, but PCA9552 is compatible */
f4aec252 556 create_pca9552(soc, 4, 0x77);
143b040f
PW		 557
558 /* bus 6 : */
1373b15b
PMD		 559 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
143b040f
PW		 561 /* bus 6 : pca9546 @ 0x73 */
562
563 /* bus 8 : */
564 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
7a204cbd 565 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
143b040f 566 eeprom8_56);
f4aec252
CLG		 567 create_pca9552(soc, 8, 0x60);
568 create_pca9552(soc, 8, 0x61);
143b040f
PW		 569 /* bus 8 : adc128d818 @ 0x1d */
570 /* bus 8 : adc128d818 @ 0x1f */
571
572 /*
573 * bus 13 : pca9548 @ 0x71
574 * - channel 3:
575 * - tmm421 @ 0x4c
576 * - tmp421 @ 0x4e
577 * - tmp421 @ 0x4f
578 */
579
580}
581
612b219a 582static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
62c2c2eb 583{
7cfbde5e
PMD		 584 static const struct {
585 unsigned gpio_id;
586 LEDColor color;
587 const char *description;
588 bool gpio_polarity;
589 } pca1_leds[] = {
590 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
591 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
592 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
593 };
62c2c2eb 594 AspeedSoCState *soc = &bmc->soc;
3d165f12 595 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
15ce12cf 596 DeviceState *dev;
7cfbde5e 597 LEDState *led;
62c2c2eb 598
63ceb818 599 /* Bus 3: TODO bmp280@77 */
db437ca6 600 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
15ce12cf 601 qdev_prop_set_string(dev, "description", "pca1");
2616f572
PMD		 602 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
603 aspeed_i2c_get_bus(&soc->i2c, 3),
604 &error_fatal);
8c9a61d7 605
7cfbde5e
PMD		 606 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
607 led = led_create_simple(OBJECT(bmc),
608 pca1_leds[i].gpio_polarity,
609 pca1_leds[i].color,
610 pca1_leds[i].description);
611 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
612 qdev_get_gpio_in(DEVICE(led), 0));
613 }
b61ea6e7 614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
2a75e8c3 615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
1373b15b
PMD		 616 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
617 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
62c2c2eb
CLG		 618
619 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
1373b15b 620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
044475f3 621 0x4a);
6c4567c7
CLG		 622
623 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
624 * good enough */
1373b15b 625 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
3d165f12 626
7a204cbd 627 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
3d165f12 628 eeprom_buf);
db437ca6 629 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
15ce12cf 630 qdev_prop_set_string(dev, "description", "pca0");
2616f572
PMD		 631 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
632 aspeed_i2c_get_bus(&soc->i2c, 11),
633 &error_fatal);
63ceb818 634 /* Bus 11: TODO ucd90160@64 */
62c2c2eb
CLG		 635}
636
95f068c8
JW		 637static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
638{
639 AspeedSoCState *soc = &bmc->soc;
640 DeviceState *dev;
641
642 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
643 "emc1413", 0x4c));
644 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
645 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
646 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
647
648 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
649 "emc1413", 0x4c));
650 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
651 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
652 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
653
654 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
655 "emc1413", 0x4c));
656 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
657 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
658 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
6f5f6507
JW		 659
660 static uint8_t eeprom_buf[2 * 1024] = {
661 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
662 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
663 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
664 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
665 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
666 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
667 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
668 };
669 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
670 eeprom_buf);
95f068c8
JW		 671}
672
fa6d98c0
JS		 673static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
674{
675 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
676 DeviceState *dev = DEVICE(i2c_dev);
677
678 qdev_prop_set_uint32(dev, "rom-size", rsize);
679 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
680}
681
82b6a3f6
JW		 682static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
683{
684 AspeedSoCState *soc = &bmc->soc;
685 I2CSlave *i2c_mux;
686
687 /* The at24c256 */
688 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
689
690 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
692 0x48);
693 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
694 0x49);
695
696 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
697 "pca9546", 0x70);
698 /* It expects a TMP112 but a TMP105 is compatible */
699 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
700 0x4a);
701
702 /* It expects a ds3232 but a ds1338 is good enough */
703 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
704
705 /* It expects a pca9555 but a pca9552 is compatible */
f4aec252 706 create_pca9552(soc, 8, 0x30);
82b6a3f6
JW		 707}
708
58e52bdb
CLG		 709static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
710{
711 AspeedSoCState *soc = &bmc->soc;
fa6d98c0
JS		 712 I2CSlave *i2c_mux;
713
714 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
58e52bdb 715
f4aec252 716 create_pca9552(soc, 3, 0x61);
bcb122f8 717
58e52bdb
CLG		 718 /* The rainier expects a TMP275 but a TMP105 is compatible */
719 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
720 0x48);
721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
722 0x49);
723 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
724 0x4a);
fa6d98c0
JS		 725 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
726 "pca9546", 0x70);
727 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
728 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
729 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
f4aec252 730 create_pca9552(soc, 4, 0x60);
58e52bdb
CLG		 731
732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
733 0x48);
734 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
735 0x49);
f4aec252
CLG		 736 create_pca9552(soc, 5, 0x60);
737 create_pca9552(soc, 5, 0x61);
fa6d98c0
JS		 738 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
739 "pca9546", 0x70);
740 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
741 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
58e52bdb
CLG		 742
743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
744 0x48);
745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
746 0x4a);
747 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
748 0x4b);
fa6d98c0
JS		 749 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
750 "pca9546", 0x70);
751 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
752 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
753 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
754 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
58e52bdb 755
f4aec252
CLG		 756 create_pca9552(soc, 7, 0x30);
757 create_pca9552(soc, 7, 0x31);
758 create_pca9552(soc, 7, 0x32);
759 create_pca9552(soc, 7, 0x33);
f4aec252
CLG		 760 create_pca9552(soc, 7, 0x60);
761 create_pca9552(soc, 7, 0x61);
b61ea6e7 762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
58e52bdb
CLG		 763 /* Bus 7: TODO si7021-a20@20 */
764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
765 0x48);
2a75e8c3 766 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
fa6d98c0
JS		 767 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
768 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
58e52bdb
CLG		 769
770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
771 0x48);
772 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
773 0x4a);
fa6d98c0
JS		 774 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
775 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
f4aec252
CLG		 776 create_pca9552(soc, 8, 0x60);
777 create_pca9552(soc, 8, 0x61);
58e52bdb
CLG		 778 /* Bus 8: ucd90320@11 */
779 /* Bus 8: ucd90320@b */
780 /* Bus 8: ucd90320@c */
781
782 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
fa6d98c0 784 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
58e52bdb
CLG		 785
786 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
fa6d98c0 788 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
58e52bdb
CLG		 789
790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
791 0x48);
792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
793 0x49);
fa6d98c0
JS		 794 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
795 "pca9546", 0x70);
796 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
797 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
f4aec252 798 create_pca9552(soc, 11, 0x60);
fa6d98c0
JS		 799
800
801 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
f4aec252 802 create_pca9552(soc, 13, 0x60);
fa6d98c0
JS		 803
804 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
f4aec252 805 create_pca9552(soc, 14, 0x60);
fa6d98c0
JS		 806
807 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
f4aec252 808 create_pca9552(soc, 15, 0x60);
58e52bdb
CLG		 809}
810
febbe308
PD		 811static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
812 I2CBus **channels)
813{
814 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
815 for (int i = 0; i < 8; i++) {
816 channels[i] = pca954x_i2c_get_bus(mux, i);
817 }
818}
819
820#define TYPE_LM75 TYPE_TMP105
821#define TYPE_TMP75 TYPE_TMP105
822#define TYPE_TMP422 "tmp422"
823
824static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
825{
826 AspeedSoCState *soc = &bmc->soc;
827 I2CBus *i2c[144] = {};
828
829 for (int i = 0; i < 16; i++) {
830 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
831 }
832 I2CBus *i2c180 = i2c[2];
833 I2CBus *i2c480 = i2c[8];
834 I2CBus *i2c600 = i2c[11];
835
836 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
837 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
838 /* NOTE: The device tree skips [32, 40) in the alias numbering */
839 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
840 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
841 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
842 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
843 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
844 for (int i = 0; i < 8; i++) {
845 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
846 }
847
848 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
849 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
850
851 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
852 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
853 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
854
855 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
856 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
857 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
858 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
859
860 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
861 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
862
863 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
864 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
865 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
866 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
867
868 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
869 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
870
871 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
872 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
873 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
874 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
875 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
876 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
877 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
878
879 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
880 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
881 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
882 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
883 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
884 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
885 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
886 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
887
888 for (int i = 0; i < 8; i++) {
889 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
890 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
891 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
892 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
893 }
894}
895
a20c54b1
PW		 896#define TYPE_TMP421 "tmp421"
897
898static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
899{
900 AspeedSoCState *soc = &bmc->soc;
901 I2CBus *i2c[13] = {};
902 for (int i = 0; i < 13; i++) {
903 if ((i == 8) || (i == 11)) {
904 continue;
905 }
906 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
907 }
908
909 /* Bus 0 - 5 all have the same config. */
910 for (int i = 0; i < 6; i++) {
911 /* Missing model: ti,ina230 @ 0x45 */
912 /* Missing model: mps,mp5023 @ 0x40 */
913 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
914 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
915 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
916 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
917 /* Missing model: fsc,fusb302 @ 0x22 */
918 }
919
920 /* Bus 6 */
921 at24c_eeprom_init(i2c[6], 0x56, 65536);
922 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
923 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
924
925
926 /* Bus 7 */
927 at24c_eeprom_init(i2c[7], 0x54, 65536);
928
929 /* Bus 9 */
930 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
931
932 /* Bus 10 */
933 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
934 /* Missing model: ti,hdc1080 @ 0x40 */
935 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
936
937 /* Bus 12 */
938 /* Missing model: adi,adm1278 @ 0x11 */
939 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
940 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
941 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
942}
943
fa699e80
PD		 944static void fby35_i2c_init(AspeedMachineState *bmc)
945{
946 AspeedSoCState *soc = &bmc->soc;
947 I2CBus *i2c[16];
948
949 for (int i = 0; i < 16; i++) {
950 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
951 }
952
953 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
954 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
955 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
956 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
957 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
958 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
959
960 aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
961 aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
962 aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
963 aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
964 aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
965
966 /*
967 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
968 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
969 * each.
970 */
971}
972
fb6b3c8d
JHY		 973static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
974{
975 AspeedSoCState *soc = &bmc->soc;
976
977 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
978}
979
ece4cccd
GG		 980static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
981{
982 AspeedSoCState *soc = &bmc->soc;
2a7a5d5c 983 I2CSlave *therm_mux, *cpuvr_mux;
ece4cccd
GG		 984
985 /* Create the generic DC-SCM hardware */
986 qcom_dc_scm_bmc_i2c_init(bmc);
987
988 /* Now create the Firework specific hardware */
2a75e8c3 989
2a7a5d5c
JHY		 990 /* I2C7 CPUVR MUX */
991 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
992 "pca9546", 0x70);
993 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
994 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
995 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
996 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
997
cfc68f16
MK		 998 /* I2C8 Thermal Diodes*/
999 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1000 "pca9548", 0x70);
1001 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1002 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1003 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1004 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1005 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1006
2a75e8c3
MK		 1007 /* I2C9 Fan Controller (MAX31785) */
1008 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1009 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
ece4cccd
GG		 1010}
1011
1a15311a
CLG		 1012static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1013{
1014 return ASPEED_MACHINE(obj)->mmio_exec;
1015}
1016
1017static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1018{
1019 ASPEED_MACHINE(obj)->mmio_exec = value;
1020}
1021
1022static void aspeed_machine_instance_init(Object *obj)
1023{
1024 ASPEED_MACHINE(obj)->mmio_exec = false;
1025}
1026
9820e52f
CLG		 1027static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1028{
1029 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1030 return g_strdup(bmc->fmc_model);
1031}
1032
1033static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1034{
1035 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1036
1037 g_free(bmc->fmc_model);
1038 bmc->fmc_model = g_strdup(value);
1039}
1040
1041static char *aspeed_get_spi_model(Object *obj, Error **errp)
1042{
1043 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1044 return g_strdup(bmc->spi_model);
1045}
1046
1047static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1048{
1049 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1050
1051 g_free(bmc->spi_model);
1052 bmc->spi_model = g_strdup(value);
1053}
1054
1a15311a
CLG		 1055static void aspeed_machine_class_props_init(ObjectClass *oc)
1056{
1057 object_class_property_add_bool(oc, "execute-in-place",
1058 aspeed_get_mmio_exec,
d2623129 1059 aspeed_set_mmio_exec);
1a15311a 1060 object_class_property_set_description(oc, "execute-in-place",
7eecec7d 1061 "boot directly from CE0 flash device");
9820e52f
CLG		 1062
1063 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1064 aspeed_set_fmc_model);
1065 object_class_property_set_description(oc, "fmc-model",
1066 "Change the FMC Flash model");
1067 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1068 aspeed_set_spi_model);
1069 object_class_property_set_description(oc, "spi-model",
1070 "Change the SPI Flash model");
1a15311a
CLG		 1071}
1072
b7f1a0cb
CLG		 1073static int aspeed_soc_num_cpus(const char *soc_name)
1074{
1075 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1076 return sc->num_cpus;
1077}
1078
fca9ca1b 1079static void aspeed_machine_class_init(ObjectClass *oc, void *data)
62c2c2eb
CLG		 1080{
1081 MachineClass *mc = MACHINE_CLASS(oc);
d3bad7e7 1082 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
62c2c2eb 1083
fca9ca1b 1084 mc->init = aspeed_machine_init;
62c2c2eb
CLG		 1085 mc->no_floppy = 1;
1086 mc->no_cdrom = 1;
1087 mc->no_parallel = 1;
afcbaed6 1088 mc->default_ram_id = "ram";
d3bad7e7 1089 amc->macs_mask = ASPEED_MAC0_ON;
5d63d0c7 1090 amc->uart_default = ASPEED_DEV_UART5;
1a15311a
CLG		 1091
1092 aspeed_machine_class_props_init(oc);
62c2c2eb
CLG		 1093}
1094
baa4732b
CLG		 1095static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1096{
1097 MachineClass *mc = MACHINE_CLASS(oc);
1098 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1099
1100 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1101 amc->soc_name = "ast2400-a1";
1102 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1103 amc->fmc_model = "n25q256a";
70322913 1104 amc->spi_model = "mx25l25635f";
baa4732b
CLG		 1105 amc->num_cs = 1;
1106 amc->i2c_init = palmetto_bmc_i2c_init;
1107 mc->default_ram_size = 256 * MiB;
b7f1a0cb
CLG		 1108 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1109 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1110};
1111
9cccb912
PV		 1112static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1113{
1114 MachineClass *mc = MACHINE_CLASS(oc);
1115 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1116
1117 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1118 amc->soc_name = "ast2400-a1";
1119 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1120 amc->fmc_model = "n25q256a";
1121 amc->spi_model = "mx25l25635e";
1122 amc->num_cs = 1;
1123 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1124 mc->default_ram_size = 128 * MiB;
1125 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1126 aspeed_soc_num_cpus(amc->soc_name);
1127}
1128
40a38df5
ES		 1129static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1130 void *data)
1131{
1132 MachineClass *mc = MACHINE_CLASS(oc);
1133 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1134
1135 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1136 amc->soc_name = "ast2400-a1";
1137 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1138 amc->fmc_model = "mx25l25635e";
1139 amc->spi_model = "mx25l25635e";
1140 amc->num_cs = 1;
1141 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1142 amc->i2c_init = palmetto_bmc_i2c_init;
1143 mc->default_ram_size = 256 * MiB;
1144}
1145
47936597
GR		 1146static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1147 void *data)
1148{
1149 MachineClass *mc = MACHINE_CLASS(oc);
1150 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1151
1152 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1153 amc->soc_name = "ast2500-a1";
1154 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1155 amc->fmc_model = "mx25l25635e";
1156 amc->spi_model = "mx25l25635e";
1157 amc->num_cs = 1;
1158 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1159 amc->i2c_init = palmetto_bmc_i2c_init;
1160 mc->default_ram_size = 512 * MiB;
1161 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1162 aspeed_soc_num_cpus(amc->soc_name);
1163}
1164
baa4732b
CLG		 1165static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1166{
1167 MachineClass *mc = MACHINE_CLASS(oc);
1168 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1169
1170 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1171 amc->soc_name = "ast2500-a1";
1172 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
753abfc4 1173 amc->fmc_model = "mx25l25635e";
70322913 1174 amc->spi_model = "mx25l25635f";
baa4732b
CLG		 1175 amc->num_cs = 1;
1176 amc->i2c_init = ast2500_evb_i2c_init;
1177 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1178 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1179 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1180};
1181
1182static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1183{
1184 MachineClass *mc = MACHINE_CLASS(oc);
1185 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1186
1187 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1188 amc->soc_name = "ast2500-a1";
1189 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1190 amc->fmc_model = "n25q256a";
1191 amc->spi_model = "mx66l1g45g";
1192 amc->num_cs = 2;
1193 amc->i2c_init = romulus_bmc_i2c_init;
1194 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1195 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1196 aspeed_soc_num_cpus(amc->soc_name);
fca9ca1b
CLG		 1197};
1198
143b040f
PW		 1199static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1200{
1201 MachineClass *mc = MACHINE_CLASS(oc);
1202 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1203
1204 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1205 amc->soc_name = "ast2500-a1";
1206 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1207 amc->fmc_model = "mx66l1g45g";
1208 amc->spi_model = "mx66l1g45g";
1209 amc->num_cs = 2;
1210 amc->i2c_init = sonorapass_bmc_i2c_init;
1211 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1212 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1213 aspeed_soc_num_cpus(amc->soc_name);
143b040f
PW		 1214};
1215
baa4732b
CLG		 1216static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1217{
1218 MachineClass *mc = MACHINE_CLASS(oc);
1219 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1220
1221 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1222 amc->soc_name = "ast2500-a1";
1223 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
70322913 1224 amc->fmc_model = "mx25l25635f";
baa4732b
CLG		 1225 amc->spi_model = "mx66l1g45g";
1226 amc->num_cs = 2;
1227 amc->i2c_init = witherspoon_bmc_i2c_init;
1228 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1229 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1230 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1231};
1232
1233static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1234{
1235 MachineClass *mc = MACHINE_CLASS(oc);
1236 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1237
f548f201 1238 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
c5811bb3 1239 amc->soc_name = "ast2600-a3";
baa4732b
CLG		 1240 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1241 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
753abfc4 1242 amc->fmc_model = "mx66u51235f";
baa4732b
CLG		 1243 amc->spi_model = "mx66u51235f";
1244 amc->num_cs = 1;
29193286
GR		 1245 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1246 ASPEED_MAC3_ON;
baa4732b
CLG		 1247 amc->i2c_init = ast2600_evb_i2c_init;
1248 mc->default_ram_size = 1 * GiB;
b7f1a0cb
CLG		 1249 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1250 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1251};
1252
63ceb818
CLG		 1253static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1254{
1255 MachineClass *mc = MACHINE_CLASS(oc);
1256 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1257
f548f201 1258 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
c5811bb3 1259 amc->soc_name = "ast2600-a3";
63ceb818
CLG		 1260 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1261 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1262 amc->fmc_model = "mx66l1g45g";
1263 amc->spi_model = "mx66l1g45g";
1264 amc->num_cs = 2;
d3bad7e7 1265 amc->macs_mask = ASPEED_MAC2_ON;
63ceb818
CLG		 1266 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1267 mc->default_ram_size = 1 * GiB;
b7f1a0cb
CLG		 1268 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1269 aspeed_soc_num_cpus(amc->soc_name);
63ceb818
CLG		 1270};
1271
95f068c8
JW		 1272static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1273{
1274 MachineClass *mc = MACHINE_CLASS(oc);
1275 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1276
1277 mc->desc = "Bytedance G220A BMC (ARM1176)";
1278 amc->soc_name = "ast2500-a1";
1279 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1280 amc->fmc_model = "n25q512a";
1281 amc->spi_model = "mx25l25635e";
1282 amc->num_cs = 2;
5bb825c8 1283 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
95f068c8
JW		 1284 amc->i2c_init = g220a_bmc_i2c_init;
1285 mc->default_ram_size = 1024 * MiB;
1286 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1287 aspeed_soc_num_cpus(amc->soc_name);
1288};
1289
82b6a3f6
JW		 1290static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1291{
1292 MachineClass *mc = MACHINE_CLASS(oc);
1293 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1294
1295 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1296 amc->soc_name = "ast2500-a1";
1297 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1298 amc->fmc_model = "n25q512a";
1299 amc->spi_model = "mx25l25635e";
1300 amc->num_cs = 2;
1301 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1302 amc->i2c_init = fp5280g2_bmc_i2c_init;
1303 mc->default_ram_size = 512 * MiB;
1304 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1305 aspeed_soc_num_cpus(amc->soc_name);
1306};
1307
58e52bdb
CLG		 1308static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1309{
1310 MachineClass *mc = MACHINE_CLASS(oc);
1311 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1312
f548f201 1313 mc->desc = "IBM Rainier BMC (Cortex-A7)";
c5811bb3 1314 amc->soc_name = "ast2600-a3";
58e52bdb
CLG		 1315 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1316 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1317 amc->fmc_model = "mx66l1g45g";
1318 amc->spi_model = "mx66l1g45g";
1319 amc->num_cs = 2;
1320 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1321 amc->i2c_init = rainier_bmc_i2c_init;
1322 mc->default_ram_size = 1 * GiB;
1323 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1324 aspeed_soc_num_cpus(amc->soc_name);
1325};
1326
febbe308
PD		 1327/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1328#if HOST_LONG_BITS == 32
1329#define FUJI_BMC_RAM_SIZE (1 * GiB)
1330#else
1331#define FUJI_BMC_RAM_SIZE (2 * GiB)
1332#endif
1333
1334static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1335{
1336 MachineClass *mc = MACHINE_CLASS(oc);
1337 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1338
1339 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1340 amc->soc_name = "ast2600-a3";
1341 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1342 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1343 amc->fmc_model = "mx66l1g45g";
1344 amc->spi_model = "mx66l1g45g";
1345 amc->num_cs = 2;
1346 amc->macs_mask = ASPEED_MAC3_ON;
1347 amc->i2c_init = fuji_bmc_i2c_init;
1348 amc->uart_default = ASPEED_DEV_UART1;
1349 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1350 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1351 aspeed_soc_num_cpus(amc->soc_name);
1352};
1353
104bdaff
PW		 1354/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1355#if HOST_LONG_BITS == 32
1356#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1357#else
1358#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1359#endif
1360
a20c54b1
PW		 1361static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1362{
1363 MachineClass *mc = MACHINE_CLASS(oc);
1364 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1365
1366 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1367 amc->soc_name = "ast2600-a3";
1368 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1369 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1370 amc->fmc_model = "w25q01jvq";
1371 amc->spi_model = NULL;
1372 amc->num_cs = 2;
1373 amc->macs_mask = ASPEED_MAC2_ON;
1374 amc->i2c_init = bletchley_bmc_i2c_init;
104bdaff 1375 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
a20c54b1
PW		 1376 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1377 aspeed_soc_num_cpus(amc->soc_name);
1378}
1379
7966d70f 1380static void fby35_reset(MachineState *state, ShutdownCause reason)
fa699e80
PD		 1381{
1382 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1383 AspeedGPIOState *gpio = &bmc->soc.gpio;
1384
7966d70f 1385 qemu_devices_reset(reason);
fa699e80 1386
f0418558 1387 /* Board ID: 7 (Class-1, 4 slots) */
fa699e80
PD		 1388 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1389 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1390 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1391 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
f0418558
PD		 1392
1393 /* Slot presence pins, inverse polarity. (False means present) */
1394 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1395 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1396 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1397 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1398
1399 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1400 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1401 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1402 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1403 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
fa699e80
PD		 1404}
1405
1406static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1407{
1408 MachineClass *mc = MACHINE_CLASS(oc);
1409 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1410
1411 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1412 mc->reset = fby35_reset;
1413 amc->fmc_model = "mx66l1g45g";
1414 amc->num_cs = 2;
1415 amc->macs_mask = ASPEED_MAC3_ON;
1416 amc->i2c_init = fby35_i2c_init;
1417 /* FIXME: Replace this macro with something more general */
1418 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1419}
1420
66c895b8
JL		 1421#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1422/* Main SYSCLK frequency in Hz (200MHz) */
1423#define SYSCLK_FRQ 200000000ULL
1424
1425static void aspeed_minibmc_machine_init(MachineState *machine)
1426{
1427 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1428 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1429 Clock *sysclk;
1430
1431 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1432 clock_set_hz(sysclk, SYSCLK_FRQ);
1433
1434 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1435 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1436
4dd9d554
PD		 1437 object_property_set_link(OBJECT(&bmc->soc), "memory",
1438 OBJECT(get_system_memory()), &error_abort);
d2b3eaef 1439 connect_serial_hds_to_uarts(bmc);
66c895b8
JL		 1440 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1441
1442 aspeed_board_init_flashes(&bmc->soc.fmc,
1443 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1444 amc->num_cs,
1445 0);
1446
1447 aspeed_board_init_flashes(&bmc->soc.spi[0],
1448 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1449 amc->num_cs, amc->num_cs);
1450
1451 aspeed_board_init_flashes(&bmc->soc.spi[1],
1452 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1453 amc->num_cs, (amc->num_cs * 2));
1454
1455 if (amc->i2c_init) {
1456 amc->i2c_init(bmc);
1457 }
1458
1459 armv7m_load_kernel(ARM_CPU(first_cpu),
1460 machine->kernel_filename,
761c532a 1461 0,
66c895b8
JL		 1462 AST1030_INTERNAL_FLASH_SIZE);
1463}
1464
4c70ab16
TL		 1465static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1466{
1467 AspeedSoCState *soc = &bmc->soc;
1468
1469 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1470 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1471 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1472
1473 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1475}
1476
66c895b8
JL		 1477static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1478 void *data)
1479{
1480 MachineClass *mc = MACHINE_CLASS(oc);
1481 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1482
1483 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1484 amc->soc_name = "ast1030-a1";
1485 amc->hw_strap1 = 0;
1486 amc->hw_strap2 = 0;
1487 mc->init = aspeed_minibmc_machine_init;
4c70ab16 1488 amc->i2c_init = ast1030_evb_i2c_init;
66c895b8
JL		 1489 mc->default_ram_size = 0;
1490 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1491 amc->fmc_model = "sst25vf032b";
1492 amc->spi_model = "sst25vf032b";
1493 amc->num_cs = 2;
1494 amc->macs_mask = 0;
1495}
1496
fb6b3c8d
JHY		 1497static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1498 void *data)
1499{
1500 MachineClass *mc = MACHINE_CLASS(oc);
1501 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1502
1503 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1504 amc->soc_name = "ast2600-a3";
1505 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1506 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1507 amc->fmc_model = "n25q512a";
1508 amc->spi_model = "n25q512a";
1509 amc->num_cs = 2;
1510 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1511 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1512 mc->default_ram_size = 1 * GiB;
1513 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1514 aspeed_soc_num_cpus(amc->soc_name);
1515};
1516
ece4cccd
GG		 1517static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1518 void *data)
1519{
1520 MachineClass *mc = MACHINE_CLASS(oc);
1521 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1522
1523 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1524 amc->soc_name = "ast2600-a3";
1525 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1526 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1527 amc->fmc_model = "n25q512a";
1528 amc->spi_model = "n25q512a";
1529 amc->num_cs = 2;
1530 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1531 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1532 mc->default_ram_size = 1 * GiB;
1533 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1534 aspeed_soc_num_cpus(amc->soc_name);
1535};
1536
baa4732b 1537static const TypeInfo aspeed_machine_types[] = {
fca9ca1b 1538 {
baa4732b
CLG		 1539 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1540 .parent = TYPE_ASPEED_MACHINE,
1541 .class_init = aspeed_machine_palmetto_class_init,
40a38df5
ES		 1542 }, {
1543 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1544 .parent = TYPE_ASPEED_MACHINE,
1545 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
47936597
GR		 1546 }, {
1547 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1548 .parent = TYPE_ASPEED_MACHINE,
1549 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
fca9ca1b 1550 }, {
baa4732b
CLG		 1551 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1552 .parent = TYPE_ASPEED_MACHINE,
1553 .class_init = aspeed_machine_ast2500_evb_class_init,
fca9ca1b 1554 }, {
baa4732b
CLG		 1555 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1556 .parent = TYPE_ASPEED_MACHINE,
1557 .class_init = aspeed_machine_romulus_class_init,
143b040f
PW		 1558 }, {
1559 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1560 .parent = TYPE_ASPEED_MACHINE,
1561 .class_init = aspeed_machine_sonorapass_class_init,
fca9ca1b 1562 }, {
baa4732b
CLG		 1563 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1564 .parent = TYPE_ASPEED_MACHINE,
1565 .class_init = aspeed_machine_witherspoon_class_init,
ccc2c418 1566 }, {
baa4732b
CLG		 1567 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1568 .parent = TYPE_ASPEED_MACHINE,
1569 .class_init = aspeed_machine_ast2600_evb_class_init,
63ceb818
CLG		 1570 }, {
1571 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1572 .parent = TYPE_ASPEED_MACHINE,
1573 .class_init = aspeed_machine_tacoma_class_init,
95f068c8
JW		 1574 }, {
1575 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1576 .parent = TYPE_ASPEED_MACHINE,
1577 .class_init = aspeed_machine_g220a_class_init,
fb6b3c8d
JHY		 1578 }, {
1579 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1580 .parent = TYPE_ASPEED_MACHINE,
1581 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
ece4cccd
GG		 1582 }, {
1583 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1584 .parent = TYPE_ASPEED_MACHINE,
1585 .class_init = aspeed_machine_qcom_firework_class_init,
82b6a3f6
JW		 1586 }, {
1587 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1588 .parent = TYPE_ASPEED_MACHINE,
1589 .class_init = aspeed_machine_fp5280g2_class_init,
9cccb912
PV		 1590 }, {
1591 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1592 .parent = TYPE_ASPEED_MACHINE,
1593 .class_init = aspeed_machine_quanta_q71l_class_init,
58e52bdb
CLG		 1594 }, {
1595 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1596 .parent = TYPE_ASPEED_MACHINE,
1597 .class_init = aspeed_machine_rainier_class_init,
febbe308
PD		 1598 }, {
1599 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1600 .parent = TYPE_ASPEED_MACHINE,
1601 .class_init = aspeed_machine_fuji_class_init,
a20c54b1
PW		 1602 }, {
1603 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1604 .parent = TYPE_ASPEED_MACHINE,
1605 .class_init = aspeed_machine_bletchley_class_init,
fa699e80
PD		 1606 }, {
1607 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1608 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1609 .class_init = aspeed_machine_fby35_class_init,
66c895b8
JL		 1610 }, {
1611 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1612 .parent = TYPE_ASPEED_MACHINE,
1613 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
baa4732b
CLG		 1614 }, {
1615 .name = TYPE_ASPEED_MACHINE,
1616 .parent = TYPE_MACHINE,
888b2b03 1617 .instance_size = sizeof(AspeedMachineState),
1a15311a 1618 .instance_init = aspeed_machine_instance_init,
baa4732b
CLG		 1619 .class_size = sizeof(AspeedMachineClass),
1620 .class_init = aspeed_machine_class_init,
1621 .abstract = true,
fca9ca1b 1622 }
baa4732b 1623};
74fb1f38 1624
baa4732b 1625DEFINE_TYPES(aspeed_machine_types)
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