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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
4771d756 PB |
26 | #include "qemu-common.h" |
27 | #include "cpu.h" | |
83c9f4ca PB |
28 | #include "hw/hw.h" |
29 | #include "hw/pci/pci.h" | |
6864fa38 | 30 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
31 | #include "hw/pci-host/apb.h" |
32 | #include "hw/i386/pc.h" | |
33 | #include "hw/char/serial.h" | |
34 | #include "hw/timer/m48t59.h" | |
35 | #include "hw/block/fdc.h" | |
1422e32d | 36 | #include "net/net.h" |
1de7afc9 | 37 | #include "qemu/timer.h" |
9c17d615 | 38 | #include "sysemu/sysemu.h" |
83c9f4ca | 39 | #include "hw/boards.h" |
c6363bae | 40 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 41 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 42 | #include "hw/sparc/sparc64.h" |
0d09e41a | 43 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca PB |
44 | #include "hw/sysbus.h" |
45 | #include "hw/ide.h" | |
6864fa38 | 46 | #include "hw/ide/pci.h" |
83c9f4ca | 47 | #include "hw/loader.h" |
ca20cf32 | 48 | #include "elf.h" |
f348b6d1 | 49 | #include "qemu/cutils.h" |
3475187d | 50 | |
b430a225 | 51 | //#define DEBUG_EBUS |
b430a225 BS |
52 | |
53 | #ifdef DEBUG_EBUS | |
54 | #define EBUS_DPRINTF(fmt, ...) \ | |
55 | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) | |
56 | #else | |
57 | #define EBUS_DPRINTF(fmt, ...) | |
9d926598 BS |
58 | #endif |
59 | ||
83469015 FB |
60 | #define KERNEL_LOAD_ADDR 0x00404000 |
61 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 62 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 63 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 64 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e | 65 | #define APB_MEM_BASE 0x1ff00000000ULL |
d63baf92 | 66 | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
f930d07e | 67 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 68 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 69 | #define MAX_IDE_BUS 2 |
3cce6243 | 70 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
71 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
72 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
73 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 74 | |
852e82f3 | 75 | #define IVEC_MAX 0x40 |
9d926598 | 76 | |
c7ba218d BS |
77 | struct hwdef { |
78 | const char * const default_cpu_model; | |
905fdcb5 | 79 | uint16_t machine_id; |
e87231d4 BS |
80 | uint64_t prom_addr; |
81 | uint64_t console_serial_base; | |
c7ba218d BS |
82 | }; |
83 | ||
c5e6fb7e AK |
84 | typedef struct EbusState { |
85 | PCIDevice pci_dev; | |
86 | MemoryRegion bar0; | |
87 | MemoryRegion bar1; | |
88 | } EbusState; | |
89 | ||
57146941 | 90 | void DMA_init(ISABus *bus, int high_page_enable) |
4556bd8b BS |
91 | { |
92 | } | |
93 | ||
ddcd5531 GA |
94 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
95 | Error **errp) | |
81864572 | 96 | { |
48779e50 | 97 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
98 | } |
99 | ||
31688246 | 100 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
101 | const char *arch, ram_addr_t RAM_size, |
102 | const char *boot_devices, | |
103 | uint32_t kernel_image, uint32_t kernel_size, | |
104 | const char *cmdline, | |
105 | uint32_t initrd_image, uint32_t initrd_size, | |
106 | uint32_t NVRAM_image, | |
107 | int width, int height, int depth, | |
108 | const uint8_t *macaddr) | |
83469015 | 109 | { |
66508601 | 110 | unsigned int i; |
2024c014 | 111 | int sysp_end; |
d2c63fc1 | 112 | uint8_t image[0x1ff0]; |
31688246 | 113 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
114 | |
115 | memset(image, '\0', sizeof(image)); | |
116 | ||
2024c014 TH |
117 | /* OpenBIOS nvram variables partition */ |
118 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
83469015 | 119 | |
2024c014 TH |
120 | /* Free space partition */ |
121 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 122 | |
0d31cb99 BS |
123 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
124 | ||
31688246 HP |
125 | for (i = 0; i < sizeof(image); i++) { |
126 | (k->write)(nvram, i, image[i]); | |
127 | } | |
66508601 | 128 | |
83469015 | 129 | return 0; |
3475187d | 130 | } |
5f2bf0fe BS |
131 | |
132 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
133 | const char *initrd_filename, | |
134 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
135 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
136 | uint64_t *kernel_entry) | |
636aa70a BS |
137 | { |
138 | int linux_boot; | |
139 | unsigned int i; | |
140 | long kernel_size; | |
6908d9ce | 141 | uint8_t *ptr; |
5f2bf0fe | 142 | uint64_t kernel_top; |
636aa70a BS |
143 | |
144 | linux_boot = (kernel_filename != NULL); | |
145 | ||
146 | kernel_size = 0; | |
147 | if (linux_boot) { | |
ca20cf32 BS |
148 | int bswap_needed; |
149 | ||
150 | #ifdef BSWAP_NEEDED | |
151 | bswap_needed = 1; | |
152 | #else | |
153 | bswap_needed = 0; | |
154 | #endif | |
5f2bf0fe | 155 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
7ef295ea | 156 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); |
5f2bf0fe BS |
157 | if (kernel_size < 0) { |
158 | *kernel_addr = KERNEL_LOAD_ADDR; | |
159 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 160 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
161 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
162 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
163 | } |
164 | if (kernel_size < 0) { | |
636aa70a BS |
165 | kernel_size = load_image_targphys(kernel_filename, |
166 | KERNEL_LOAD_ADDR, | |
167 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 168 | } |
636aa70a BS |
169 | if (kernel_size < 0) { |
170 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
171 | kernel_filename); | |
172 | exit(1); | |
173 | } | |
5f2bf0fe | 174 | /* load initrd above kernel */ |
636aa70a BS |
175 | *initrd_size = 0; |
176 | if (initrd_filename) { | |
5f2bf0fe BS |
177 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
178 | ||
636aa70a | 179 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
180 | *initrd_addr, |
181 | RAM_size - *initrd_addr); | |
182 | if ((int)*initrd_size < 0) { | |
636aa70a BS |
183 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
184 | initrd_filename); | |
185 | exit(1); | |
186 | } | |
187 | } | |
188 | if (*initrd_size > 0) { | |
189 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 190 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 191 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 192 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 193 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
194 | break; |
195 | } | |
196 | } | |
197 | } | |
198 | } | |
199 | return kernel_size; | |
200 | } | |
3475187d | 201 | |
e87231d4 | 202 | typedef struct ResetData { |
403d7a2d | 203 | SPARCCPU *cpu; |
44a99354 | 204 | uint64_t prom_addr; |
e87231d4 BS |
205 | } ResetData; |
206 | ||
361dea40 | 207 | static void isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 208 | { |
361dea40 BS |
209 | static const int isa_irq_to_ivec[16] = { |
210 | [1] = 0x29, /* keyboard */ | |
211 | [4] = 0x2b, /* serial */ | |
212 | [6] = 0x27, /* floppy */ | |
213 | [7] = 0x22, /* parallel */ | |
214 | [12] = 0x2a, /* mouse */ | |
215 | }; | |
216 | qemu_irq *irqs = opaque; | |
217 | int ivec; | |
218 | ||
1f6fb58d | 219 | assert(n < ARRAY_SIZE(isa_irq_to_ivec)); |
361dea40 BS |
220 | ivec = isa_irq_to_ivec[n]; |
221 | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); | |
222 | if (ivec) { | |
223 | qemu_set_irq(irqs[ivec], level); | |
224 | } | |
1387fe4a BS |
225 | } |
226 | ||
c190ea07 | 227 | /* EBUS (Eight bit bus) bridge */ |
48a18b3c | 228 | static ISABus * |
e1030ca5 | 229 | pci_ebus_init(PCIDevice *pci_dev, qemu_irq *irqs) |
c190ea07 | 230 | { |
1387fe4a | 231 | qemu_irq *isa_irq; |
48a18b3c | 232 | ISABus *isa_bus; |
1387fe4a | 233 | |
2ae0e48d | 234 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); |
361dea40 | 235 | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); |
48a18b3c HP |
236 | isa_bus_irqs(isa_bus, isa_irq); |
237 | return isa_bus; | |
53e3c4f9 | 238 | } |
c190ea07 | 239 | |
3a80cead | 240 | static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 241 | { |
c5e6fb7e AK |
242 | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
243 | ||
d10e5432 MA |
244 | if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
245 | pci_address_space_io(pci_dev), errp)) { | |
246 | return; | |
247 | } | |
c5e6fb7e AK |
248 | |
249 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem | |
250 | pci_dev->config[0x05] = 0x00; | |
251 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
252 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
253 | pci_dev->config[0x09] = 0x00; // programming i/f | |
254 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
255 | ||
0a70e094 PB |
256 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
257 | 0, 0x1000000); | |
e824b2cc | 258 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 259 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
f3b18f35 | 260 | 0, 0x4000); |
a1cf8be5 | 261 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
262 | } |
263 | ||
40021f08 AL |
264 | static void ebus_class_init(ObjectClass *klass, void *data) |
265 | { | |
266 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
267 | ||
3a80cead | 268 | k->realize = pci_ebus_realize; |
40021f08 AL |
269 | k->vendor_id = PCI_VENDOR_ID_SUN; |
270 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
271 | k->revision = 0x01; | |
272 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
273 | } | |
274 | ||
8c43a6f0 | 275 | static const TypeInfo ebus_info = { |
39bffca2 AL |
276 | .name = "ebus", |
277 | .parent = TYPE_PCI_DEVICE, | |
278 | .instance_size = sizeof(EbusState), | |
279 | .class_init = ebus_class_init, | |
fd3b02c8 EH |
280 | .interfaces = (InterfaceInfo[]) { |
281 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
282 | { }, | |
283 | }, | |
53e3c4f9 BS |
284 | }; |
285 | ||
13575cf6 AF |
286 | #define TYPE_OPENPROM "openprom" |
287 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
288 | ||
d4edce38 | 289 | typedef struct PROMState { |
13575cf6 AF |
290 | SysBusDevice parent_obj; |
291 | ||
d4edce38 AK |
292 | MemoryRegion prom; |
293 | } PROMState; | |
294 | ||
409dbce5 AJ |
295 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
296 | { | |
a8170e5e | 297 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
298 | return addr + *base_addr - PROM_VADDR; |
299 | } | |
300 | ||
1baffa46 | 301 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 302 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
303 | { |
304 | DeviceState *dev; | |
305 | SysBusDevice *s; | |
306 | char *filename; | |
307 | int ret; | |
308 | ||
13575cf6 | 309 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 310 | qdev_init_nofail(dev); |
1356b98d | 311 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
312 | |
313 | sysbus_mmio_map(s, 0, addr); | |
314 | ||
315 | /* load boot prom */ | |
316 | if (bios_name == NULL) { | |
317 | bios_name = PROM_FILENAME; | |
318 | } | |
319 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
320 | if (filename) { | |
409dbce5 | 321 | ret = load_elf(filename, translate_prom_address, &addr, |
7ef295ea | 322 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
323 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
324 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
325 | } | |
7267c094 | 326 | g_free(filename); |
1baffa46 BS |
327 | } else { |
328 | ret = -1; | |
329 | } | |
330 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
331 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
332 | exit(1); | |
333 | } | |
334 | } | |
335 | ||
78fb261d | 336 | static void prom_init1(Object *obj) |
1baffa46 | 337 | { |
78fb261d XZ |
338 | PROMState *s = OPENPROM(obj); |
339 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
1baffa46 | 340 | |
1cfe48c1 | 341 | memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, |
f8ed85ac | 342 | &error_fatal); |
c5705a77 | 343 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 344 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 345 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
346 | } |
347 | ||
999e12bb AL |
348 | static Property prom_properties[] = { |
349 | {/* end of property list */}, | |
350 | }; | |
351 | ||
352 | static void prom_class_init(ObjectClass *klass, void *data) | |
353 | { | |
39bffca2 | 354 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 355 | |
39bffca2 | 356 | dc->props = prom_properties; |
999e12bb AL |
357 | } |
358 | ||
8c43a6f0 | 359 | static const TypeInfo prom_info = { |
13575cf6 | 360 | .name = TYPE_OPENPROM, |
39bffca2 AL |
361 | .parent = TYPE_SYS_BUS_DEVICE, |
362 | .instance_size = sizeof(PROMState), | |
363 | .class_init = prom_class_init, | |
78fb261d | 364 | .instance_init = prom_init1, |
1baffa46 BS |
365 | }; |
366 | ||
bda42033 | 367 | |
88c034d5 AF |
368 | #define TYPE_SUN4U_MEMORY "memory" |
369 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
370 | ||
371 | typedef struct RamDevice { | |
372 | SysBusDevice parent_obj; | |
373 | ||
d4edce38 | 374 | MemoryRegion ram; |
04843626 | 375 | uint64_t size; |
bda42033 BS |
376 | } RamDevice; |
377 | ||
378 | /* System RAM */ | |
78fb261d | 379 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 380 | { |
88c034d5 | 381 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 382 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 383 | |
1cfe48c1 | 384 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 385 | &error_fatal); |
c5705a77 | 386 | vmstate_register_ram_global(&d->ram); |
78fb261d | 387 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
388 | } |
389 | ||
a8170e5e | 390 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
391 | { |
392 | DeviceState *dev; | |
393 | SysBusDevice *s; | |
394 | RamDevice *d; | |
395 | ||
396 | /* allocate RAM */ | |
88c034d5 | 397 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 398 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 399 | |
88c034d5 | 400 | d = SUN4U_RAM(dev); |
bda42033 | 401 | d->size = RAM_size; |
e23a1b33 | 402 | qdev_init_nofail(dev); |
bda42033 BS |
403 | |
404 | sysbus_mmio_map(s, 0, addr); | |
405 | } | |
406 | ||
999e12bb AL |
407 | static Property ram_properties[] = { |
408 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
409 | DEFINE_PROP_END_OF_LIST(), | |
410 | }; | |
411 | ||
412 | static void ram_class_init(ObjectClass *klass, void *data) | |
413 | { | |
39bffca2 | 414 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 415 | |
78fb261d | 416 | dc->realize = ram_realize; |
39bffca2 | 417 | dc->props = ram_properties; |
999e12bb AL |
418 | } |
419 | ||
8c43a6f0 | 420 | static const TypeInfo ram_info = { |
88c034d5 | 421 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
422 | .parent = TYPE_SYS_BUS_DEVICE, |
423 | .instance_size = sizeof(RamDevice), | |
424 | .class_init = ram_class_init, | |
bda42033 BS |
425 | }; |
426 | ||
38bc50f7 | 427 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 428 | MachineState *machine, |
7b833f5b BS |
429 | const struct hwdef *hwdef) |
430 | { | |
f9d1465f | 431 | SPARCCPU *cpu; |
31688246 | 432 | Nvram *nvram; |
7b833f5b | 433 | unsigned int i; |
5f2bf0fe | 434 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
311f2b7a | 435 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 436 | PCIDevice *ebus, *pci_dev; |
48a18b3c | 437 | ISABus *isa_bus; |
f3b18f35 | 438 | SysBusDevice *s; |
361dea40 | 439 | qemu_irq *ivec_irqs, *pbm_irqs; |
f455e98c | 440 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 441 | DriveInfo *fd[MAX_FD]; |
c3ae40e1 | 442 | DeviceState *dev; |
a88b362c | 443 | FWCfgState *fw_cfg; |
8d932971 | 444 | NICInfo *nd; |
6864fa38 MCA |
445 | MACAddr macaddr; |
446 | bool onboard_nic; | |
7b833f5b | 447 | |
7b833f5b | 448 | /* init CPUs */ |
fff54d22 AT |
449 | cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model, |
450 | hwdef->prom_addr); | |
7b833f5b | 451 | |
bda42033 | 452 | /* set up devices */ |
3ef96221 | 453 | ram_init(0, machine->ram_size); |
3475187d | 454 | |
1baffa46 | 455 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 456 | |
fff54d22 | 457 | ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); |
311f2b7a MCA |
458 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, |
459 | &pci_busB, &pbm_irqs); | |
83469015 | 460 | |
6864fa38 MCA |
461 | /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is |
462 | reserved (leaving no slots free after on-board devices) however slots | |
463 | 0-3 are free on busB */ | |
464 | pci_bus->slot_reserved_mask = 0xfffffffc; | |
465 | pci_busA->slot_reserved_mask = 0xfffffff1; | |
466 | pci_busB->slot_reserved_mask = 0xfffffff0; | |
467 | ||
468 | ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, "ebus"); | |
469 | qdev_init_nofail(DEVICE(ebus)); | |
470 | ||
e1030ca5 | 471 | isa_bus = pci_ebus_init(ebus, pbm_irqs); |
c190ea07 | 472 | |
e87231d4 BS |
473 | i = 0; |
474 | if (hwdef->console_serial_base) { | |
38bc50f7 | 475 | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, |
39186d8a | 476 | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
e87231d4 BS |
477 | i++; |
478 | } | |
83469015 | 479 | |
4496dc49 | 480 | serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); |
07dc7880 | 481 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
83469015 | 482 | |
6864fa38 MCA |
483 | pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); |
484 | ||
485 | memset(&macaddr, 0, sizeof(MACAddr)); | |
486 | onboard_nic = false; | |
8d932971 MCA |
487 | for (i = 0; i < nb_nics; i++) { |
488 | nd = &nd_table[i]; | |
489 | ||
6864fa38 MCA |
490 | if (!nd->model || strcmp(nd->model, "sunhme") == 0) { |
491 | if (!onboard_nic) { | |
492 | pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), | |
493 | true, "sunhme"); | |
494 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); | |
495 | onboard_nic = true; | |
496 | } else { | |
497 | pci_dev = pci_create_simple(pci_busB, -1, "sunhme"); | |
498 | } | |
8d932971 | 499 | } else { |
6864fa38 | 500 | pci_dev = pci_create_simple(pci_busB, -1, nd->model); |
8d932971 | 501 | } |
6864fa38 MCA |
502 | |
503 | dev = &pci_dev->qdev; | |
504 | qdev_set_nic_properties(dev, nd); | |
505 | qdev_init_nofail(dev); | |
506 | } | |
507 | ||
508 | /* If we don't have an onboard NIC, grab a default MAC address so that | |
509 | * we have a valid machine id */ | |
510 | if (!onboard_nic) { | |
511 | qemu_macaddr_default_if_unset(&macaddr); | |
8d932971 | 512 | } |
83469015 | 513 | |
d8f94e1b | 514 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
e4bcb14c | 515 | |
6864fa38 MCA |
516 | pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); |
517 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); | |
518 | qdev_init_nofail(&pci_dev->qdev); | |
519 | pci_ide_create_devs(pci_dev, hd); | |
3b898dda | 520 | |
48a18b3c | 521 | isa_create_simple(isa_bus, "i8042"); |
c3ae40e1 HP |
522 | |
523 | /* Floppy */ | |
e4bcb14c | 524 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 525 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 526 | } |
c3ae40e1 HP |
527 | dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); |
528 | if (fd[0]) { | |
529 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
530 | &error_abort); | |
531 | } | |
532 | if (fd[1]) { | |
533 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
534 | &error_abort); | |
535 | } | |
536 | qdev_prop_set_uint32(dev, "dma", -1); | |
537 | qdev_init_nofail(dev); | |
636aa70a | 538 | |
f3b18f35 MCA |
539 | /* Map NVRAM into I/O (ebus) space */ |
540 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
541 | s = SYS_BUS_DEVICE(nvram); | |
07c84741 | 542 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 MCA |
543 | sysbus_mmio_get_region(s, 0)); |
544 | ||
636aa70a | 545 | initrd_size = 0; |
5f2bf0fe | 546 | initrd_addr = 0; |
3ef96221 MA |
547 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
548 | machine->initrd_filename, | |
5f2bf0fe BS |
549 | ram_size, &initrd_size, &initrd_addr, |
550 | &kernel_addr, &kernel_entry); | |
636aa70a | 551 | |
3ef96221 MA |
552 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
553 | machine->boot_order, | |
5f2bf0fe | 554 | kernel_addr, kernel_size, |
3ef96221 | 555 | machine->kernel_cmdline, |
5f2bf0fe | 556 | initrd_addr, initrd_size, |
0d31cb99 BS |
557 | /* XXX: need an option to load a NVRAM image */ |
558 | 0, | |
559 | graphic_width, graphic_height, graphic_depth, | |
6864fa38 | 560 | (uint8_t *)&macaddr); |
83469015 | 561 | |
d6acc8a5 MCA |
562 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
563 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
07c84741 | 564 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); |
d6acc8a5 | 565 | qdev_init_nofail(dev); |
07c84741 | 566 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
567 | &FW_CFG_IO(dev)->comb_iomem); |
568 | ||
569 | fw_cfg = FW_CFG(dev); | |
5836d168 | 570 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 571 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
572 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
573 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
574 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
575 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 576 | if (machine->kernel_cmdline) { |
9c9b0512 | 577 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
578 | strlen(machine->kernel_cmdline) + 1); |
579 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 580 | } else { |
9c9b0512 | 581 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 582 | } |
5f2bf0fe BS |
583 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
584 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 585 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
586 | |
587 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
588 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
589 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
590 | ||
513f789f | 591 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
592 | } |
593 | ||
905fdcb5 BS |
594 | enum { |
595 | sun4u_id = 0, | |
596 | sun4v_id = 64, | |
597 | }; | |
598 | ||
c7ba218d BS |
599 | static const struct hwdef hwdefs[] = { |
600 | /* Sun4u generic PC-like machine */ | |
601 | { | |
5910b047 | 602 | .default_cpu_model = "TI UltraSparc IIi", |
905fdcb5 | 603 | .machine_id = sun4u_id, |
e87231d4 BS |
604 | .prom_addr = 0x1fff0000000ULL, |
605 | .console_serial_base = 0, | |
c7ba218d BS |
606 | }, |
607 | /* Sun4v generic PC-like machine */ | |
608 | { | |
609 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 610 | .machine_id = sun4v_id, |
e87231d4 BS |
611 | .prom_addr = 0x1fff0000000ULL, |
612 | .console_serial_base = 0, | |
613 | }, | |
c7ba218d BS |
614 | }; |
615 | ||
616 | /* Sun4u hardware initialisation */ | |
3ef96221 | 617 | static void sun4u_init(MachineState *machine) |
5f072e1f | 618 | { |
3ef96221 | 619 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
620 | } |
621 | ||
622 | /* Sun4v hardware initialisation */ | |
3ef96221 | 623 | static void sun4v_init(MachineState *machine) |
5f072e1f | 624 | { |
3ef96221 | 625 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
626 | } |
627 | ||
8a661aea | 628 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 629 | { |
8a661aea AF |
630 | MachineClass *mc = MACHINE_CLASS(oc); |
631 | ||
e264d29d EH |
632 | mc->desc = "Sun4u platform"; |
633 | mc->init = sun4u_init; | |
2059839b | 634 | mc->block_default_type = IF_IDE; |
e264d29d EH |
635 | mc->max_cpus = 1; /* XXX for now */ |
636 | mc->is_default = 1; | |
637 | mc->default_boot_order = "c"; | |
638 | } | |
c7ba218d | 639 | |
8a661aea AF |
640 | static const TypeInfo sun4u_type = { |
641 | .name = MACHINE_TYPE_NAME("sun4u"), | |
642 | .parent = TYPE_MACHINE, | |
643 | .class_init = sun4u_class_init, | |
644 | }; | |
e87231d4 | 645 | |
8a661aea | 646 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 647 | { |
8a661aea AF |
648 | MachineClass *mc = MACHINE_CLASS(oc); |
649 | ||
e264d29d EH |
650 | mc->desc = "Sun4v platform"; |
651 | mc->init = sun4v_init; | |
2059839b | 652 | mc->block_default_type = IF_IDE; |
e264d29d EH |
653 | mc->max_cpus = 1; /* XXX for now */ |
654 | mc->default_boot_order = "c"; | |
655 | } | |
656 | ||
8a661aea AF |
657 | static const TypeInfo sun4v_type = { |
658 | .name = MACHINE_TYPE_NAME("sun4v"), | |
659 | .parent = TYPE_MACHINE, | |
660 | .class_init = sun4v_class_init, | |
661 | }; | |
e264d29d | 662 | |
83f7d43a AF |
663 | static void sun4u_register_types(void) |
664 | { | |
665 | type_register_static(&ebus_info); | |
666 | type_register_static(&prom_info); | |
667 | type_register_static(&ram_info); | |
83f7d43a | 668 | |
8a661aea AF |
669 | type_register_static(&sun4u_type); |
670 | type_register_static(&sun4v_type); | |
8a661aea AF |
671 | } |
672 | ||
83f7d43a | 673 | type_init(sun4u_register_types) |