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target-i386: Introduce "xlevel" property for X86CPU
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3
AF		 30#include "qapi/qapi-visit-core.h"
31
28f52cc0
VR		 32#include "hyperv.h"
33
c6dc6f63
AP		 34/* feature flags taken from "Intel Processor Identification and the CPUID
35 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
36 * between feature naming conventions, aliases may be added.
37 */
38static const char *feature_name[] = {
39 "fpu", "vme", "de", "pse",
40 "tsc", "msr", "pae", "mce",
41 "cx8", "apic", NULL, "sep",
42 "mtrr", "pge", "mca", "cmov",
43 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
44 NULL, "ds" /* Intel dts */, "acpi", "mmx",
45 "fxsr", "sse", "sse2", "ss",
46 "ht" /* Intel htt */, "tm", "ia64", "pbe",
47};
48static const char *ext_feature_name[] = {
f370be3c 49 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 50 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 51 "tm2", "ssse3", "cid", NULL,
e117f772 52 "fma", "cx16", "xtpr", "pdcm",
c6dc6f63 53 NULL, NULL, "dca", "sse4.1|sse4_1",
e117f772 54 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 55 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 56 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 57};
58static const char *ext2_feature_name[] = {
59 "fpu", "vme", "de", "pse",
60 "tsc", "msr", "pae", "mce",
61 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
62 "mtrr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 64 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 65 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 66 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 67};
68static const char *ext3_feature_name[] = {
69 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
70 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 71 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 72 "skinit", "wdt", NULL, NULL,
e117f772 73 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 74 NULL, NULL, NULL, NULL,
75 NULL, NULL, NULL, NULL,
76 NULL, NULL, NULL, NULL,
77};
78
79static const char *kvm_feature_name[] = {
642258c6 80 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
c6dc6f63
AP		 81 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
83 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
84};
85
296acb64
JR		 86static const char *svm_feature_name[] = {
87 "npt", "lbrv", "svm_lock", "nrip_save",
88 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
89 NULL, NULL, "pause_filter", NULL,
90 "pfthreshold", NULL, NULL, NULL,
91 NULL, NULL, NULL, NULL,
92 NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95};
96
c6dc6f63
AP		 97/* collects per-function cpuid data
98 */
99typedef struct model_features_t {
100 uint32_t *guest_feat;
101 uint32_t *host_feat;
102 uint32_t check_feat;
103 const char **flag_names;
104 uint32_t cpuid;
105 } model_features_t;
106
107int check_cpuid = 0;
108int enforce_cpuid = 0;
109
bb44e0d1
JK		 110void host_cpuid(uint32_t function, uint32_t count,
111 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 112{
113#if defined(CONFIG_KVM)
a1fd24af
AL		 114 uint32_t vec[4];
115
116#ifdef __x86_64__
117 asm volatile("cpuid"
118 : "=a"(vec[0]), "=b"(vec[1]),
119 "=c"(vec[2]), "=d"(vec[3])
120 : "0"(function), "c"(count) : "cc");
121#else
122 asm volatile("pusha \n\t"
123 "cpuid \n\t"
124 "mov %%eax, 0(%2) \n\t"
125 "mov %%ebx, 4(%2) \n\t"
126 "mov %%ecx, 8(%2) \n\t"
127 "mov %%edx, 12(%2) \n\t"
128 "popa"
129 : : "a"(function), "c"(count), "S"(vec)
130 : "memory", "cc");
131#endif
132
bdde476a 133 if (eax)
a1fd24af 134 *eax = vec[0];
bdde476a 135 if (ebx)
a1fd24af 136 *ebx = vec[1];
bdde476a 137 if (ecx)
a1fd24af 138 *ecx = vec[2];
bdde476a 139 if (edx)
a1fd24af 140 *edx = vec[3];
bdde476a
AP		 141#endif
142}
c6dc6f63
AP		 143
144#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
145
146/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
147 * a substring. ex if !NULL points to the first char after a substring,
148 * otherwise the string is assumed to sized by a terminating nul.
149 * Return lexical ordering of *s1:*s2.
150 */
151static int sstrcmp(const char *s1, const char *e1, const char *s2,
152 const char *e2)
153{
154 for (;;) {
155 if (!*s1 || !*s2 || *s1 != *s2)
156 return (*s1 - *s2);
157 ++s1, ++s2;
158 if (s1 == e1 && s2 == e2)
159 return (0);
160 else if (s1 == e1)
161 return (*s2);
162 else if (s2 == e2)
163 return (*s1);
164 }
165}
166
167/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
168 * '|' delimited (possibly empty) strings in which case search for a match
169 * within the alternatives proceeds left to right. Return 0 for success,
170 * non-zero otherwise.
171 */
172static int altcmp(const char *s, const char *e, const char *altstr)
173{
174 const char *p, *q;
175
176 for (q = p = altstr; ; ) {
177 while (*p && *p != '|')
178 ++p;
179 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
180 return (0);
181 if (!*p)
182 return (1);
183 else
184 q = ++p;
185 }
186}
187
188/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 189 * *pval and return true, otherwise return false
c6dc6f63 190 */
e41e0fc6
JK		 191static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
192 const char **featureset)
c6dc6f63
AP		 193{
194 uint32_t mask;
195 const char **ppc;
e41e0fc6 196 bool found = false;
c6dc6f63 197
e41e0fc6 198 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 199 if (*ppc && !altcmp(s, e, *ppc)) {
200 *pval |= mask;
e41e0fc6 201 found = true;
c6dc6f63 202 }
e41e0fc6
JK		 203 }
204 return found;
c6dc6f63
AP		 205}
206
207static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
208 uint32_t *ext_features,
209 uint32_t *ext2_features,
210 uint32_t *ext3_features,
296acb64
JR		 211 uint32_t *kvm_features,
212 uint32_t *svm_features)
c6dc6f63
AP		 213{
214 if (!lookup_feature(features, flagname, NULL, feature_name) &&
215 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
216 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
217 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 218 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
219 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 220 fprintf(stderr, "CPU feature %s not found\n", flagname);
221}
222
223typedef struct x86_def_t {
224 struct x86_def_t *next;
225 const char *name;
226 uint32_t level;
227 uint32_t vendor1, vendor2, vendor3;
228 int family;
229 int model;
230 int stepping;
b862d1fe 231 int tsc_khz;
296acb64
JR		 232 uint32_t features, ext_features, ext2_features, ext3_features;
233 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 234 uint32_t xlevel;
235 char model_id[48];
236 int vendor_override;
237 uint32_t flags;
b3baa152
BW		 238 /* Store the results of Centaur's CPUID instructions */
239 uint32_t ext4_features;
240 uint32_t xlevel2;
c6dc6f63
AP		 241} x86_def_t;
242
243#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
244#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
245 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
246#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
247 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
248 CPUID_PSE36 | CPUID_FXSR)
249#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
250#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
251 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
252 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
253 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 254#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 255
551a2dec
AP		 256#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
257 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
258 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
259 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
260 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 261 /* partly implemented:
262 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
263 CPUID_PSE36 (needed for Solaris) */
264 /* missing:
265 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 266#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 267 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 268 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 269 /* missing:
270 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 271 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 272#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
273 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
274 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 275 /* missing:
276 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 277#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
278 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 279#define TCG_SVM_FEATURES 0
551a2dec 280
c6dc6f63
AP		 281/* maintains list of cpu model definitions
282 */
283static x86_def_t *x86_defs = {NULL};
284
285/* built-in cpu model definitions (deprecated)
286 */
287static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 288 {
289 .name = "qemu64",
290 .level = 4,
291 .vendor1 = CPUID_VENDOR_AMD_1,
292 .vendor2 = CPUID_VENDOR_AMD_2,
293 .vendor3 = CPUID_VENDOR_AMD_3,
294 .family = 6,
295 .model = 2,
296 .stepping = 3,
297 .features = PPRO_FEATURES |
c6dc6f63 298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 299 CPUID_PSE36,
300 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 301 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 302 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
303 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
304 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
305 .xlevel = 0x8000000A,
306 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
307 },
308 {
309 .name = "phenom",
310 .level = 5,
311 .vendor1 = CPUID_VENDOR_AMD_1,
312 .vendor2 = CPUID_VENDOR_AMD_2,
313 .vendor3 = CPUID_VENDOR_AMD_3,
314 .family = 16,
315 .model = 2,
316 .stepping = 3,
c6dc6f63
AP		 317 .features = PPRO_FEATURES |
318 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 319 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 320 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
321 CPUID_EXT_POPCNT,
42673936 322 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 323 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
324 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 325 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 326 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
327 CPUID_EXT3_CR8LEG,
328 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
329 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
330 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
331 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 332 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 333 .xlevel = 0x8000001A,
334 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
335 },
336 {
337 .name = "core2duo",
338 .level = 10,
339 .family = 6,
340 .model = 15,
341 .stepping = 11,
c6dc6f63
AP		 342 .features = PPRO_FEATURES |
343 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 344 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
345 CPUID_HT | CPUID_TM | CPUID_PBE,
346 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
347 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
348 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 349 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
350 .ext3_features = CPUID_EXT3_LAHF_LM,
351 .xlevel = 0x80000008,
352 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
353 },
354 {
355 .name = "kvm64",
356 .level = 5,
357 .vendor1 = CPUID_VENDOR_INTEL_1,
358 .vendor2 = CPUID_VENDOR_INTEL_2,
359 .vendor3 = CPUID_VENDOR_INTEL_3,
360 .family = 15,
361 .model = 6,
362 .stepping = 1,
363 /* Missing: CPUID_VME, CPUID_HT */
364 .features = PPRO_FEATURES |
365 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
366 CPUID_PSE36,
367 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
368 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
369 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 370 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 371 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
372 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
373 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
374 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
375 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
376 .ext3_features = 0,
377 .xlevel = 0x80000008,
378 .model_id = "Common KVM processor"
379 },
c6dc6f63
AP		 380 {
381 .name = "qemu32",
382 .level = 4,
383 .family = 6,
384 .model = 3,
385 .stepping = 3,
386 .features = PPRO_FEATURES,
387 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 388 .xlevel = 0x80000004,
c6dc6f63
AP		 389 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
390 },
eafaf1e5
AP		 391 {
392 .name = "kvm32",
393 .level = 5,
394 .family = 15,
395 .model = 6,
396 .stepping = 1,
397 .features = PPRO_FEATURES |
398 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
399 .ext_features = CPUID_EXT_SSE3,
400 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
401 .ext3_features = 0,
402 .xlevel = 0x80000008,
403 .model_id = "Common 32-bit KVM processor"
404 },
c6dc6f63
AP		 405 {
406 .name = "coreduo",
407 .level = 10,
408 .family = 6,
409 .model = 14,
410 .stepping = 8,
c6dc6f63 411 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 412 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
413 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
414 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
415 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 416 .ext2_features = CPUID_EXT2_NX,
417 .xlevel = 0x80000008,
418 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
419 },
420 {
421 .name = "486",
58012d66 422 .level = 1,
c6dc6f63
AP		 423 .family = 4,
424 .model = 0,
425 .stepping = 0,
426 .features = I486_FEATURES,
427 .xlevel = 0,
428 },
429 {
430 .name = "pentium",
431 .level = 1,
432 .family = 5,
433 .model = 4,
434 .stepping = 3,
435 .features = PENTIUM_FEATURES,
436 .xlevel = 0,
437 },
438 {
439 .name = "pentium2",
440 .level = 2,
441 .family = 6,
442 .model = 5,
443 .stepping = 2,
444 .features = PENTIUM2_FEATURES,
445 .xlevel = 0,
446 },
447 {
448 .name = "pentium3",
449 .level = 2,
450 .family = 6,
451 .model = 7,
452 .stepping = 3,
453 .features = PENTIUM3_FEATURES,
454 .xlevel = 0,
455 },
456 {
457 .name = "athlon",
458 .level = 2,
459 .vendor1 = CPUID_VENDOR_AMD_1,
460 .vendor2 = CPUID_VENDOR_AMD_2,
461 .vendor3 = CPUID_VENDOR_AMD_3,
462 .family = 6,
463 .model = 2,
464 .stepping = 3,
465 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 466 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63
AP		 467 .xlevel = 0x80000008,
468 /* XXX: put another string ? */
469 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
470 },
471 {
472 .name = "n270",
473 /* original is on level 10 */
474 .level = 5,
475 .family = 6,
476 .model = 28,
477 .stepping = 2,
478 .features = PPRO_FEATURES |
8560efed
AJ		 479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
480 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 481 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 482 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
483 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 484 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 485 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 486 .xlevel = 0x8000000A,
487 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
488 },
489};
490
491static int cpu_x86_fill_model_id(char *str)
492{
493 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
494 int i;
495
496 for (i = 0; i < 3; i++) {
497 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
498 memcpy(str + i * 16 + 0, &eax, 4);
499 memcpy(str + i * 16 + 4, &ebx, 4);
500 memcpy(str + i * 16 + 8, &ecx, 4);
501 memcpy(str + i * 16 + 12, &edx, 4);
502 }
503 return 0;
504}
505
506static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
507{
508 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
509
510 x86_cpu_def->name = "host";
511 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
512 x86_cpu_def->level = eax;
513 x86_cpu_def->vendor1 = ebx;
514 x86_cpu_def->vendor2 = edx;
515 x86_cpu_def->vendor3 = ecx;
516
517 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
518 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
519 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
520 x86_cpu_def->stepping = eax & 0x0F;
521 x86_cpu_def->ext_features = ecx;
522 x86_cpu_def->features = edx;
523
524 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
525 x86_cpu_def->xlevel = eax;
526
527 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
528 x86_cpu_def->ext2_features = edx;
529 x86_cpu_def->ext3_features = ecx;
530 cpu_x86_fill_model_id(x86_cpu_def->model_id);
531 x86_cpu_def->vendor_override = 0;
532
b3baa152
BW		 533 /* Call Centaur's CPUID instruction. */
534 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
535 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
536 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
537 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
538 if (eax >= 0xC0000001) {
539 /* Support VIA max extended level */
540 x86_cpu_def->xlevel2 = eax;
541 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
542 x86_cpu_def->ext4_features = edx;
543 }
544 }
296acb64
JR		 545
546 /*
547 * Every SVM feature requires emulation support in KVM - so we can't just
548 * read the host features here. KVM might even support SVM features not
549 * available on the host hardware. Just set all bits and mask out the
550 * unsupported ones later.
551 */
552 x86_cpu_def->svm_features = -1;
553
c6dc6f63
AP		 554 return 0;
555}
556
557static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
558{
559 int i;
560
561 for (i = 0; i < 32; ++i)
562 if (1 << i & mask) {
563 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
564 " flag '%s' [0x%08x]\n",
565 f->cpuid >> 16, f->cpuid & 0xffff,
566 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
567 break;
568 }
569 return 0;
570}
571
572/* best effort attempt to inform user requested cpu flags aren't making
573 * their way to the guest. Note: ft[].check_feat ideally should be
574 * specified via a guest_def field to suppress report of extraneous flags.
575 */
576static int check_features_against_host(x86_def_t *guest_def)
577{
578 x86_def_t host_def;
579 uint32_t mask;
580 int rv, i;
581 struct model_features_t ft[] = {
582 {&guest_def->features, &host_def.features,
583 ~0, feature_name, 0x00000000},
584 {&guest_def->ext_features, &host_def.ext_features,
585 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
586 {&guest_def->ext2_features, &host_def.ext2_features,
587 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
588 {&guest_def->ext3_features, &host_def.ext3_features,
589 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
590
591 cpu_x86_fill_host(&host_def);
66fe09ee 592 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 593 for (mask = 1; mask; mask <<= 1)
594 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
595 !(*ft[i].host_feat & mask)) {
596 unavailable_host_feature(&ft[i], mask);
597 rv = 1;
598 }
599 return rv;
600}
601
95b8519d
AF		 602static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
603 const char *name, Error **errp)
604{
605 X86CPU *cpu = X86_CPU(obj);
606 CPUX86State *env = &cpu->env;
607 int64_t value;
608
609 value = (env->cpuid_version >> 8) & 0xf;
610 if (value == 0xf) {
611 value += (env->cpuid_version >> 20) & 0xff;
612 }
613 visit_type_int(v, &value, name, errp);
614}
615
71ad61d3
AF		 616static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
617 const char *name, Error **errp)
ed5e1ec3 618{
71ad61d3
AF		 619 X86CPU *cpu = X86_CPU(obj);
620 CPUX86State *env = &cpu->env;
621 const int64_t min = 0;
622 const int64_t max = 0xff + 0xf;
623 int64_t value;
624
625 visit_type_int(v, &value, name, errp);
626 if (error_is_set(errp)) {
627 return;
628 }
629 if (value < min || value > max) {
630 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
631 name ? name : "null", value, min, max);
632 return;
633 }
634
ed5e1ec3 635 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 636 if (value > 0x0f) {
637 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 638 } else {
71ad61d3 639 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 640 }
641}
642
67e30c83
AF		 643static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
644 const char *name, Error **errp)
645{
646 X86CPU *cpu = X86_CPU(obj);
647 CPUX86State *env = &cpu->env;
648 int64_t value;
649
650 value = (env->cpuid_version >> 4) & 0xf;
651 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
652 visit_type_int(v, &value, name, errp);
653}
654
c5291a4f
AF		 655static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
656 const char *name, Error **errp)
b0704cbd 657{
c5291a4f
AF		 658 X86CPU *cpu = X86_CPU(obj);
659 CPUX86State *env = &cpu->env;
660 const int64_t min = 0;
661 const int64_t max = 0xff;
662 int64_t value;
663
664 visit_type_int(v, &value, name, errp);
665 if (error_is_set(errp)) {
666 return;
667 }
668 if (value < min || value > max) {
669 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
670 name ? name : "null", value, min, max);
671 return;
672 }
673
b0704cbd 674 env->cpuid_version &= ~0xf00f0;
c5291a4f 675 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 676}
677
35112e41
AF		 678static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
679 void *opaque, const char *name,
680 Error **errp)
681{
682 X86CPU *cpu = X86_CPU(obj);
683 CPUX86State *env = &cpu->env;
684 int64_t value;
685
686 value = env->cpuid_version & 0xf;
687 visit_type_int(v, &value, name, errp);
688}
689
036e2222
AF		 690static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
691 void *opaque, const char *name,
692 Error **errp)
38c3dc46 693{
036e2222
AF		 694 X86CPU *cpu = X86_CPU(obj);
695 CPUX86State *env = &cpu->env;
696 const int64_t min = 0;
697 const int64_t max = 0xf;
698 int64_t value;
699
700 visit_type_int(v, &value, name, errp);
701 if (error_is_set(errp)) {
702 return;
703 }
704 if (value < min || value > max) {
705 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
706 name ? name : "null", value, min, max);
707 return;
708 }
709
38c3dc46 710 env->cpuid_version &= ~0xf;
036e2222 711 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 712}
713
8e1898bf
AF		 714static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
715 const char *name, Error **errp)
716{
717 X86CPU *cpu = X86_CPU(obj);
718 int64_t value;
719
720 value = cpu->env.cpuid_level;
721 /* TODO Use visit_type_uint32() once available */
722 visit_type_int(v, &value, name, errp);
723}
724
725static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
726 const char *name, Error **errp)
727{
728 X86CPU *cpu = X86_CPU(obj);
729 const int64_t min = 0;
730 const int64_t max = UINT32_MAX;
731 int64_t value;
732
733 /* TODO Use visit_type_uint32() once available */
734 visit_type_int(v, &value, name, errp);
735 if (error_is_set(errp)) {
736 return;
737 }
738 if (value < min || value > max) {
739 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
740 name ? name : "null", value, min, max);
741 return;
742 }
743
744 cpu->env.cpuid_level = value;
745}
746
16b93aa8
AF		 747static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
748 const char *name, Error **errp)
749{
750 X86CPU *cpu = X86_CPU(obj);
751 int64_t value;
752
753 value = cpu->env.cpuid_xlevel;
754 /* TODO Use visit_type_uint32() once available */
755 visit_type_int(v, &value, name, errp);
756}
757
758static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
759 const char *name, Error **errp)
760{
761 X86CPU *cpu = X86_CPU(obj);
762 const int64_t min = 0;
763 const int64_t max = UINT32_MAX;
764 int64_t value;
765
766 /* TODO Use visit_type_uint32() once available */
767 visit_type_int(v, &value, name, errp);
768 if (error_is_set(errp)) {
769 return;
770 }
771 if (value < min || value > max) {
772 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
773 name ? name : "null", value, min, max);
774 return;
775 }
776
777 cpu->env.cpuid_xlevel = value;
778}
779
63e886eb
AF		 780static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
781{
782 X86CPU *cpu = X86_CPU(obj);
783 CPUX86State *env = &cpu->env;
784 char *value;
785 int i;
786
787 value = g_malloc(48 + 1);
788 for (i = 0; i < 48; i++) {
789 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
790 }
791 value[48] = '\0';
792 return value;
793}
794
938d4c25
AF		 795static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
796 Error **errp)
dcce6675 797{
938d4c25
AF		 798 X86CPU *cpu = X86_CPU(obj);
799 CPUX86State *env = &cpu->env;
dcce6675
AF		 800 int c, len, i;
801
802 if (model_id == NULL) {
803 model_id = "";
804 }
805 len = strlen(model_id);
d0a6acf4 806 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 807 for (i = 0; i < 48; i++) {
808 if (i >= len) {
809 c = '\0';
810 } else {
811 c = (uint8_t)model_id[i];
812 }
813 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
814 }
815}
816
c6dc6f63
AP		 817static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
818{
819 unsigned int i;
820 x86_def_t *def;
821
d3c481b3 822 char *s = g_strdup(cpu_model);
c6dc6f63 823 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 824 /* Features to be added*/
825 uint32_t plus_features = 0, plus_ext_features = 0;
826 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
827 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
828 /* Features to be removed */
829 uint32_t minus_features = 0, minus_ext_features = 0;
830 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
831 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 832 uint32_t numvalue;
833
834 for (def = x86_defs; def; def = def->next)
04c5b17a 835 if (name && !strcmp(name, def->name))
c6dc6f63 836 break;
04c5b17a 837 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 838 cpu_x86_fill_host(x86_cpu_def);
839 } else if (!def) {
840 goto error;
841 } else {
842 memcpy(x86_cpu_def, def, sizeof(*def));
843 }
844
845 plus_kvm_features = ~0; /* not supported bits will be filtered out later */
846
847 add_flagname_to_bitmaps("hypervisor", &plus_features,
848 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 849 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 850
851 featurestr = strtok(NULL, ",");
852
853 while (featurestr) {
854 char *val;
855 if (featurestr[0] == '+') {
296acb64
JR		 856 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
857 &plus_ext_features, &plus_ext2_features,
858 &plus_ext3_features, &plus_kvm_features,
859 &plus_svm_features);
c6dc6f63 860 } else if (featurestr[0] == '-') {
296acb64
JR		 861 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
862 &minus_ext_features, &minus_ext2_features,
863 &minus_ext3_features, &minus_kvm_features,
864 &minus_svm_features);
c6dc6f63
AP		 865 } else if ((val = strchr(featurestr, '='))) {
866 *val = 0; val++;
867 if (!strcmp(featurestr, "family")) {
868 char *err;
869 numvalue = strtoul(val, &err, 0);
a88a677f 870 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 871 fprintf(stderr, "bad numerical value %s\n", val);
872 goto error;
873 }
874 x86_cpu_def->family = numvalue;
875 } else if (!strcmp(featurestr, "model")) {
876 char *err;
877 numvalue = strtoul(val, &err, 0);
878 if (!*val || *err || numvalue > 0xff) {
879 fprintf(stderr, "bad numerical value %s\n", val);
880 goto error;
881 }
882 x86_cpu_def->model = numvalue;
883 } else if (!strcmp(featurestr, "stepping")) {
884 char *err;
885 numvalue = strtoul(val, &err, 0);
886 if (!*val || *err || numvalue > 0xf) {
887 fprintf(stderr, "bad numerical value %s\n", val);
888 goto error;
889 }
890 x86_cpu_def->stepping = numvalue ;
891 } else if (!strcmp(featurestr, "level")) {
892 char *err;
893 numvalue = strtoul(val, &err, 0);
894 if (!*val || *err) {
895 fprintf(stderr, "bad numerical value %s\n", val);
896 goto error;
897 }
898 x86_cpu_def->level = numvalue;
899 } else if (!strcmp(featurestr, "xlevel")) {
900 char *err;
901 numvalue = strtoul(val, &err, 0);
902 if (!*val || *err) {
903 fprintf(stderr, "bad numerical value %s\n", val);
904 goto error;
905 }
906 if (numvalue < 0x80000000) {
2f7a21c4 907 numvalue += 0x80000000;
c6dc6f63
AP		 908 }
909 x86_cpu_def->xlevel = numvalue;
910 } else if (!strcmp(featurestr, "vendor")) {
911 if (strlen(val) != 12) {
912 fprintf(stderr, "vendor string must be 12 chars long\n");
913 goto error;
914 }
915 x86_cpu_def->vendor1 = 0;
916 x86_cpu_def->vendor2 = 0;
917 x86_cpu_def->vendor3 = 0;
918 for(i = 0; i < 4; i++) {
919 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
920 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
921 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
922 }
923 x86_cpu_def->vendor_override = 1;
924 } else if (!strcmp(featurestr, "model_id")) {
925 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
926 val);
b862d1fe
JR		 927 } else if (!strcmp(featurestr, "tsc_freq")) {
928 int64_t tsc_freq;
929 char *err;
930
931 tsc_freq = strtosz_suffix_unit(val, &err,
932 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 933 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 934 fprintf(stderr, "bad numerical value %s\n", val);
935 goto error;
936 }
937 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 938 } else if (!strcmp(featurestr, "hv_spinlocks")) {
939 char *err;
940 numvalue = strtoul(val, &err, 0);
941 if (!*val || *err) {
942 fprintf(stderr, "bad numerical value %s\n", val);
943 goto error;
944 }
945 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 946 } else {
947 fprintf(stderr, "unrecognized feature %s\n", featurestr);
948 goto error;
949 }
950 } else if (!strcmp(featurestr, "check")) {
951 check_cpuid = 1;
952 } else if (!strcmp(featurestr, "enforce")) {
953 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 954 } else if (!strcmp(featurestr, "hv_relaxed")) {
955 hyperv_enable_relaxed_timing(true);
956 } else if (!strcmp(featurestr, "hv_vapic")) {
957 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 958 } else {
959 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
960 goto error;
961 }
962 featurestr = strtok(NULL, ",");
963 }
964 x86_cpu_def->features |= plus_features;
965 x86_cpu_def->ext_features |= plus_ext_features;
966 x86_cpu_def->ext2_features |= plus_ext2_features;
967 x86_cpu_def->ext3_features |= plus_ext3_features;
968 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 969 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 970 x86_cpu_def->features &= ~minus_features;
971 x86_cpu_def->ext_features &= ~minus_ext_features;
972 x86_cpu_def->ext2_features &= ~minus_ext2_features;
973 x86_cpu_def->ext3_features &= ~minus_ext3_features;
974 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 975 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 976 if (check_cpuid) {
977 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
978 goto error;
979 }
d3c481b3 980 g_free(s);
c6dc6f63
AP		 981 return 0;
982
983error:
d3c481b3 984 g_free(s);
c6dc6f63
AP		 985 return -1;
986}
987
988/* generate a composite string into buf of all cpuid names in featureset
989 * selected by fbits. indicate truncation at bufsize in the event of overflow.
990 * if flags, suppress names undefined in featureset.
991 */
992static void listflags(char *buf, int bufsize, uint32_t fbits,
993 const char **featureset, uint32_t flags)
994{
995 const char **p = &featureset[31];
996 char *q, *b, bit;
997 int nc;
998
999 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1000 *buf = '\0';
1001 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1002 if (fbits & 1 << bit && (*p || !flags)) {
1003 if (*p)
1004 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1005 else
1006 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1007 if (bufsize <= nc) {
1008 if (b) {
1009 memcpy(b, "...", sizeof("..."));
1010 }
1011 return;
1012 }
1013 q += nc;
1014 bufsize -= nc;
1015 }
1016}
1017
1018/* generate CPU information:
1019 * -? list model names
1020 * -?model list model names/IDs
1021 * -?dump output all model (x86_def_t) data
1022 * -?cpuid list all recognized cpuid flag names
1023 */
9a78eead 1024void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 1025{
1026 unsigned char model = !strcmp("?model", optarg);
1027 unsigned char dump = !strcmp("?dump", optarg);
1028 unsigned char cpuid = !strcmp("?cpuid", optarg);
1029 x86_def_t *def;
1030 char buf[256];
1031
1032 if (cpuid) {
1033 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
1034 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
1035 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1036 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
1037 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1038 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
1039 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1040 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
1041 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
1042 return;
1043 }
1044 for (def = x86_defs; def; def = def->next) {
1045 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
1046 if (model || dump) {
1047 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1048 } else {
1049 (*cpu_fprintf)(f, "x86 %16s\n", buf);
1050 }
1051 if (dump) {
1052 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
1053 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
1054 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
1055 buf[12] = '\0';
1056 (*cpu_fprintf)(f,
1057 " family %d model %d stepping %d level %d xlevel 0x%x"
1058 " vendor \"%s\"\n",
1059 def->family, def->model, def->stepping, def->level,
1060 def->xlevel, buf);
1061 listflags(buf, sizeof (buf), def->features, feature_name, 0);
1062 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
1063 buf);
1064 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
1065 0);
1066 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
1067 buf);
1068 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
1069 0);
1070 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
1071 def->ext2_features, buf);
1072 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
1073 0);
1074 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
1075 def->ext3_features, buf);
1076 (*cpu_fprintf)(f, "\n");
1077 }
1078 }
ed2c54d4
AP		 1079 if (kvm_enabled()) {
1080 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1081 }
c6dc6f63
AP		 1082}
1083
61dcd775 1084int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1085{
61dcd775 1086 CPUX86State *env = &cpu->env;
c6dc6f63 1087 x86_def_t def1, *def = &def1;
71ad61d3 1088 Error *error = NULL;
c6dc6f63 1089
db0ad1ba
JR		 1090 memset(def, 0, sizeof(*def));
1091
c6dc6f63
AP		 1092 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1093 return -1;
1094 if (def->vendor1) {
1095 env->cpuid_vendor1 = def->vendor1;
1096 env->cpuid_vendor2 = def->vendor2;
1097 env->cpuid_vendor3 = def->vendor3;
1098 } else {
1099 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1100 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1101 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1102 }
1103 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1104 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1105 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1106 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1107 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1108 env->cpuid_features = def->features;
c6dc6f63
AP		 1109 env->cpuid_ext_features = def->ext_features;
1110 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1111 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1112 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1113 env->cpuid_kvm_features = def->kvm_features;
296acb64 1114 env->cpuid_svm_features = def->svm_features;
b3baa152
BW		 1115 env->cpuid_ext4_features = def->ext4_features;
1116 env->cpuid_xlevel2 = def->xlevel2;
b862d1fe 1117 env->tsc_khz = def->tsc_khz;
551a2dec
AP		 1118 if (!kvm_enabled()) {
1119 env->cpuid_features &= TCG_FEATURES;
1120 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1121 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1122#ifdef TARGET_X86_64
1123 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1124#endif
1125 );
1126 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1127 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1128 }
938d4c25 1129 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1130 if (error_is_set(&error)) {
1131 error_free(error);
1132 return -1;
1133 }
c6dc6f63
AP		 1134 return 0;
1135}
1136
1137#if !defined(CONFIG_USER_ONLY)
1138/* copy vendor id string to 32 bit register, nul pad as needed
1139 */
1140static void cpyid(const char *s, uint32_t *id)
1141{
1142 char *d = (char *)id;
1143 char i;
1144
1145 for (i = sizeof (*id); i--; )
1146 *d++ = *s ? *s++ : '\0';
1147}
1148
1149/* interpret radix and convert from string to arbitrary scalar,
1150 * otherwise flag failure
1151 */
1152#define setscalar(pval, str, perr) \
1153{ \
1154 char *pend; \
1155 unsigned long ul; \
1156 \
1157 ul = strtoul(str, &pend, 0); \
1158 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1159}
1160
1161/* map cpuid options to feature bits, otherwise return failure
1162 * (option tags in *str are delimited by whitespace)
1163 */
1164static void setfeatures(uint32_t *pval, const char *str,
1165 const char **featureset, int *perr)
1166{
1167 const char *p, *q;
1168
1169 for (q = p = str; *p || *q; q = p) {
1170 while (iswhite(*p))
1171 q = ++p;
1172 while (*p && !iswhite(*p))
1173 ++p;
1174 if (!*q && !*p)
1175 return;
1176 if (!lookup_feature(pval, q, p, featureset)) {
1177 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1178 (int)(p - q), q);
1179 *perr = 1;
1180 return;
1181 }
1182 }
1183}
1184
1185/* map config file options to x86_def_t form
1186 */
1187static int cpudef_setfield(const char *name, const char *str, void *opaque)
1188{
1189 x86_def_t *def = opaque;
1190 int err = 0;
1191
1192 if (!strcmp(name, "name")) {
99e1dec0 1193 g_free((void *)def->name);
d3c481b3 1194 def->name = g_strdup(str);
c6dc6f63
AP		 1195 } else if (!strcmp(name, "model_id")) {
1196 strncpy(def->model_id, str, sizeof (def->model_id));
1197 } else if (!strcmp(name, "level")) {
1198 setscalar(&def->level, str, &err)
1199 } else if (!strcmp(name, "vendor")) {
1200 cpyid(&str[0], &def->vendor1);
1201 cpyid(&str[4], &def->vendor2);
1202 cpyid(&str[8], &def->vendor3);
1203 } else if (!strcmp(name, "family")) {
1204 setscalar(&def->family, str, &err)
1205 } else if (!strcmp(name, "model")) {
1206 setscalar(&def->model, str, &err)
1207 } else if (!strcmp(name, "stepping")) {
1208 setscalar(&def->stepping, str, &err)
1209 } else if (!strcmp(name, "feature_edx")) {
1210 setfeatures(&def->features, str, feature_name, &err);
1211 } else if (!strcmp(name, "feature_ecx")) {
1212 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1213 } else if (!strcmp(name, "extfeature_edx")) {
1214 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1215 } else if (!strcmp(name, "extfeature_ecx")) {
1216 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1217 } else if (!strcmp(name, "xlevel")) {
1218 setscalar(&def->xlevel, str, &err)
1219 } else {
1220 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1221 return (1);
1222 }
1223 if (err) {
1224 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1225 return (1);
1226 }
1227 return (0);
1228}
1229
1230/* register config file entry as x86_def_t
1231 */
1232static int cpudef_register(QemuOpts *opts, void *opaque)
1233{
7267c094 1234 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1235
1236 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1237 def->next = x86_defs;
1238 x86_defs = def;
1239 return (0);
1240}
0e26b7b8
BS		 1241
1242void cpu_clear_apic_feature(CPUX86State *env)
1243{
1244 env->cpuid_features &= ~CPUID_APIC;
1245}
1246
c6dc6f63
AP		 1247#endif /* !CONFIG_USER_ONLY */
1248
1249/* register "cpudef" models defined in configuration file. Here we first
1250 * preload any built-in definitions
1251 */
1252void x86_cpudef_setup(void)
1253{
1254 int i;
1255
1256 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1257 builtin_x86_defs[i].next = x86_defs;
1258 builtin_x86_defs[i].flags = 1;
1259 x86_defs = &builtin_x86_defs[i];
1260 }
1261#if !defined(CONFIG_USER_ONLY)
3329f07b 1262 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1263#endif
1264}
1265
c6dc6f63
AP		 1266static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1267 uint32_t *ecx, uint32_t *edx)
1268{
1269 *ebx = env->cpuid_vendor1;
1270 *edx = env->cpuid_vendor2;
1271 *ecx = env->cpuid_vendor3;
1272
1273 /* sysenter isn't supported on compatibility mode on AMD, syscall
1274 * isn't supported in compatibility mode on Intel.
1275 * Normally we advertise the actual cpu vendor, but you can override
1276 * this if you want to use KVM's sysenter/syscall emulation
1277 * in compatibility mode and when doing cross vendor migration
1278 */
89354998 1279 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1280 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1281 }
1282}
1283
1284void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1285 uint32_t *eax, uint32_t *ebx,
1286 uint32_t *ecx, uint32_t *edx)
1287{
1288 /* test if maximum index reached */
1289 if (index & 0x80000000) {
b3baa152
BW		 1290 if (index > env->cpuid_xlevel) {
1291 if (env->cpuid_xlevel2 > 0) {
1292 /* Handle the Centaur's CPUID instruction. */
1293 if (index > env->cpuid_xlevel2) {
1294 index = env->cpuid_xlevel2;
1295 } else if (index < 0xC0000000) {
1296 index = env->cpuid_xlevel;
1297 }
1298 } else {
1299 index = env->cpuid_xlevel;
1300 }
1301 }
c6dc6f63
AP		 1302 } else {
1303 if (index > env->cpuid_level)
1304 index = env->cpuid_level;
1305 }
1306
1307 switch(index) {
1308 case 0:
1309 *eax = env->cpuid_level;
1310 get_cpuid_vendor(env, ebx, ecx, edx);
1311 break;
1312 case 1:
1313 *eax = env->cpuid_version;
1314 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1315 *ecx = env->cpuid_ext_features;
1316 *edx = env->cpuid_features;
1317 if (env->nr_cores * env->nr_threads > 1) {
1318 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1319 *edx |= 1 << 28; /* HTT bit */
1320 }
1321 break;
1322 case 2:
1323 /* cache info: needed for Pentium Pro compatibility */
1324 *eax = 1;
1325 *ebx = 0;
1326 *ecx = 0;
1327 *edx = 0x2c307d;
1328 break;
1329 case 4:
1330 /* cache info: needed for Core compatibility */
1331 if (env->nr_cores > 1) {
2f7a21c4 1332 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1333 } else {
2f7a21c4 1334 *eax = 0;
c6dc6f63
AP		 1335 }
1336 switch (count) {
1337 case 0: /* L1 dcache info */
1338 *eax |= 0x0000121;
1339 *ebx = 0x1c0003f;
1340 *ecx = 0x000003f;
1341 *edx = 0x0000001;
1342 break;
1343 case 1: /* L1 icache info */
1344 *eax |= 0x0000122;
1345 *ebx = 0x1c0003f;
1346 *ecx = 0x000003f;
1347 *edx = 0x0000001;
1348 break;
1349 case 2: /* L2 cache info */
1350 *eax |= 0x0000143;
1351 if (env->nr_threads > 1) {
1352 *eax |= (env->nr_threads - 1) << 14;
1353 }
1354 *ebx = 0x3c0003f;
1355 *ecx = 0x0000fff;
1356 *edx = 0x0000001;
1357 break;
1358 default: /* end of info */
1359 *eax = 0;
1360 *ebx = 0;
1361 *ecx = 0;
1362 *edx = 0;
1363 break;
1364 }
1365 break;
1366 case 5:
1367 /* mwait info: needed for Core compatibility */
1368 *eax = 0; /* Smallest monitor-line size in bytes */
1369 *ebx = 0; /* Largest monitor-line size in bytes */
1370 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1371 *edx = 0;
1372 break;
1373 case 6:
1374 /* Thermal and Power Leaf */
1375 *eax = 0;
1376 *ebx = 0;
1377 *ecx = 0;
1378 *edx = 0;
1379 break;
f7911686
YW		 1380 case 7:
1381 if (kvm_enabled()) {
ba9bc59e
JK		 1382 KVMState *s = env->kvm_state;
1383
1384 *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
1385 *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
1386 *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
1387 *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
f7911686
YW		 1388 } else {
1389 *eax = 0;
1390 *ebx = 0;
1391 *ecx = 0;
1392 *edx = 0;
1393 }
1394 break;
c6dc6f63
AP		 1395 case 9:
1396 /* Direct Cache Access Information Leaf */
1397 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1398 *ebx = 0;
1399 *ecx = 0;
1400 *edx = 0;
1401 break;
1402 case 0xA:
1403 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1404 if (kvm_enabled()) {
1405 KVMState *s = env->kvm_state;
1406
1407 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1408 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1409 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1410 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1411 } else {
1412 *eax = 0;
1413 *ebx = 0;
1414 *ecx = 0;
1415 *edx = 0;
1416 }
c6dc6f63 1417 break;
51e49430
SY		 1418 case 0xD:
1419 /* Processor Extended State */
1420 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1421 *eax = 0;
1422 *ebx = 0;
1423 *ecx = 0;
1424 *edx = 0;
1425 break;
1426 }
1427 if (kvm_enabled()) {
ba9bc59e
JK		 1428 KVMState *s = env->kvm_state;
1429
1430 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1431 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1432 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1433 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1434 } else {
1435 *eax = 0;
1436 *ebx = 0;
1437 *ecx = 0;
1438 *edx = 0;
1439 }
1440 break;
c6dc6f63
AP		 1441 case 0x80000000:
1442 *eax = env->cpuid_xlevel;
1443 *ebx = env->cpuid_vendor1;
1444 *edx = env->cpuid_vendor2;
1445 *ecx = env->cpuid_vendor3;
1446 break;
1447 case 0x80000001:
1448 *eax = env->cpuid_version;
1449 *ebx = 0;
1450 *ecx = env->cpuid_ext3_features;
1451 *edx = env->cpuid_ext2_features;
1452
1453 /* The Linux kernel checks for the CMPLegacy bit and
1454 * discards multiple thread information if it is set.
1455 * So dont set it here for Intel to make Linux guests happy.
1456 */
1457 if (env->nr_cores * env->nr_threads > 1) {
1458 uint32_t tebx, tecx, tedx;
1459 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1460 if (tebx != CPUID_VENDOR_INTEL_1 ||
1461 tedx != CPUID_VENDOR_INTEL_2 ||
1462 tecx != CPUID_VENDOR_INTEL_3) {
1463 *ecx |= 1 << 1; /* CmpLegacy bit */
1464 }
1465 }
c6dc6f63
AP		 1466 break;
1467 case 0x80000002:
1468 case 0x80000003:
1469 case 0x80000004:
1470 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1471 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1472 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1473 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1474 break;
1475 case 0x80000005:
1476 /* cache info (L1 cache) */
1477 *eax = 0x01ff01ff;
1478 *ebx = 0x01ff01ff;
1479 *ecx = 0x40020140;
1480 *edx = 0x40020140;
1481 break;
1482 case 0x80000006:
1483 /* cache info (L2 cache) */
1484 *eax = 0;
1485 *ebx = 0x42004200;
1486 *ecx = 0x02008140;
1487 *edx = 0;
1488 break;
1489 case 0x80000008:
1490 /* virtual & phys address size in low 2 bytes. */
1491/* XXX: This value must match the one used in the MMU code. */
1492 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1493 /* 64 bit processor */
1494/* XXX: The physical address space is limited to 42 bits in exec.c. */
1495 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1496 } else {
1497 if (env->cpuid_features & CPUID_PSE36)
1498 *eax = 0x00000024; /* 36 bits physical */
1499 else
1500 *eax = 0x00000020; /* 32 bits physical */
1501 }
1502 *ebx = 0;
1503 *ecx = 0;
1504 *edx = 0;
1505 if (env->nr_cores * env->nr_threads > 1) {
1506 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1507 }
1508 break;
1509 case 0x8000000A:
296acb64
JR		 1510 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1511 *eax = 0x00000001; /* SVM Revision */
1512 *ebx = 0x00000010; /* nr of ASIDs */
1513 *ecx = 0;
1514 *edx = env->cpuid_svm_features; /* optional features */
1515 } else {
1516 *eax = 0;
1517 *ebx = 0;
1518 *ecx = 0;
1519 *edx = 0;
1520 }
c6dc6f63 1521 break;
b3baa152
BW		 1522 case 0xC0000000:
1523 *eax = env->cpuid_xlevel2;
1524 *ebx = 0;
1525 *ecx = 0;
1526 *edx = 0;
1527 break;
1528 case 0xC0000001:
1529 /* Support for VIA CPU's CPUID instruction */
1530 *eax = env->cpuid_version;
1531 *ebx = 0;
1532 *ecx = 0;
1533 *edx = env->cpuid_ext4_features;
1534 break;
1535 case 0xC0000002:
1536 case 0xC0000003:
1537 case 0xC0000004:
1538 /* Reserved for the future, and now filled with zero */
1539 *eax = 0;
1540 *ebx = 0;
1541 *ecx = 0;
1542 *edx = 0;
1543 break;
c6dc6f63
AP		 1544 default:
1545 /* reserved values: zero */
1546 *eax = 0;
1547 *ebx = 0;
1548 *ecx = 0;
1549 *edx = 0;
1550 break;
1551 }
1552}
5fd2087a
AF		 1553
1554/* CPUClass::reset() */
1555static void x86_cpu_reset(CPUState *s)
1556{
1557 X86CPU *cpu = X86_CPU(s);
1558 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1559 CPUX86State *env = &cpu->env;
c1958aea
AF		 1560 int i;
1561
1562 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1563 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1564 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1565 }
5fd2087a
AF		 1566
1567 xcc->parent_reset(s);
1568
c1958aea
AF		 1569
1570 memset(env, 0, offsetof(CPUX86State, breakpoints));
1571
1572 tlb_flush(env, 1);
1573
1574 env->old_exception = -1;
1575
1576 /* init to reset state */
1577
1578#ifdef CONFIG_SOFTMMU
1579 env->hflags |= HF_SOFTMMU_MASK;
1580#endif
1581 env->hflags2 |= HF2_GIF_MASK;
1582
1583 cpu_x86_update_cr0(env, 0x60000010);
1584 env->a20_mask = ~0x0;
1585 env->smbase = 0x30000;
1586
1587 env->idt.limit = 0xffff;
1588 env->gdt.limit = 0xffff;
1589 env->ldt.limit = 0xffff;
1590 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1591 env->tr.limit = 0xffff;
1592 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1593
1594 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1595 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1596 DESC_R_MASK | DESC_A_MASK);
1597 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1598 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1599 DESC_A_MASK);
1600 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1601 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1602 DESC_A_MASK);
1603 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1604 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1605 DESC_A_MASK);
1606 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1607 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1608 DESC_A_MASK);
1609 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1610 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1611 DESC_A_MASK);
1612
1613 env->eip = 0xfff0;
1614 env->regs[R_EDX] = env->cpuid_version;
1615
1616 env->eflags = 0x2;
1617
1618 /* FPU init */
1619 for (i = 0; i < 8; i++) {
1620 env->fptags[i] = 1;
1621 }
1622 env->fpuc = 0x37f;
1623
1624 env->mxcsr = 0x1f80;
1625
1626 env->pat = 0x0007040600070406ULL;
1627 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1628
1629 memset(env->dr, 0, sizeof(env->dr));
1630 env->dr[6] = DR6_FIXED_1;
1631 env->dr[7] = DR7_FIXED_1;
1632 cpu_breakpoint_remove_all(env, BP_CPU);
1633 cpu_watchpoint_remove_all(env, BP_CPU);
5fd2087a
AF		 1634}
1635
de024815
AF		 1636static void mce_init(X86CPU *cpu)
1637{
1638 CPUX86State *cenv = &cpu->env;
1639 unsigned int bank;
1640
1641 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1642 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1643 (CPUID_MCE | CPUID_MCA)) {
1644 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1645 cenv->mcg_ctl = ~(uint64_t)0;
1646 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1647 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1648 }
1649 }
1650}
1651
1652static void x86_cpu_initfn(Object *obj)
1653{
1654 X86CPU *cpu = X86_CPU(obj);
1655 CPUX86State *env = &cpu->env;
1656
1657 cpu_exec_init(env);
71ad61d3
AF		 1658
1659 object_property_add(obj, "family", "int",
95b8519d 1660 x86_cpuid_version_get_family,
71ad61d3 1661 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1662 object_property_add(obj, "model", "int",
67e30c83 1663 x86_cpuid_version_get_model,
c5291a4f 1664 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1665 object_property_add(obj, "stepping", "int",
35112e41 1666 x86_cpuid_version_get_stepping,
036e2222 1667 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1668 object_property_add(obj, "level", "int",
1669 x86_cpuid_get_level,
1670 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1671 object_property_add(obj, "xlevel", "int",
1672 x86_cpuid_get_xlevel,
1673 x86_cpuid_set_xlevel, NULL, NULL, NULL);
938d4c25 1674 object_property_add_str(obj, "model-id",
63e886eb 1675 x86_cpuid_get_model_id,
938d4c25 1676 x86_cpuid_set_model_id, NULL);
71ad61d3 1677
de024815
AF		 1678 env->cpuid_apic_id = env->cpu_index;
1679 mce_init(cpu);
1680}
1681
5fd2087a
AF		 1682static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1683{
1684 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1685 CPUClass *cc = CPU_CLASS(oc);
1686
1687 xcc->parent_reset = cc->reset;
1688 cc->reset = x86_cpu_reset;
1689}
1690
1691static const TypeInfo x86_cpu_type_info = {
1692 .name = TYPE_X86_CPU,
1693 .parent = TYPE_CPU,
1694 .instance_size = sizeof(X86CPU),
de024815 1695 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1696 .abstract = false,
1697 .class_size = sizeof(X86CPUClass),
1698 .class_init = x86_cpu_common_class_init,
1699};
1700
1701static void x86_cpu_register_types(void)
1702{
1703 type_register_static(&x86_cpu_type_info);
1704}
1705
1706type_init(x86_cpu_register_types)
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