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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
4c822698 | 10 | #include <linux/sched/idle.h> |
b17b0153 | 11 | #include <linux/sched/debug.h> |
29930025 | 12 | #include <linux/sched/task.h> |
68db0cf1 | 13 | #include <linux/sched/task_stack.h> |
186f4360 PG |
14 | #include <linux/init.h> |
15 | #include <linux/export.h> | |
7f424a8b | 16 | #include <linux/pm.h> |
162a688e | 17 | #include <linux/tick.h> |
9d62dcdf | 18 | #include <linux/random.h> |
7c68af6e | 19 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
20 | #include <linux/dmi.h> |
21 | #include <linux/utsname.h> | |
90e24014 RW |
22 | #include <linux/stackprotector.h> |
23 | #include <linux/tick.h> | |
24 | #include <linux/cpuidle.h> | |
61613521 | 25 | #include <trace/events/power.h> |
24f1e32c | 26 | #include <linux/hw_breakpoint.h> |
93789b32 | 27 | #include <asm/cpu.h> |
d3ec5cae | 28 | #include <asm/apic.h> |
2c1b284e | 29 | #include <asm/syscalls.h> |
7c0f6ba6 | 30 | #include <linux/uaccess.h> |
b253149b | 31 | #include <asm/mwait.h> |
78f7f1e5 | 32 | #include <asm/fpu/internal.h> |
66cb5917 | 33 | #include <asm/debugreg.h> |
90e24014 | 34 | #include <asm/nmi.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
8838eb6c | 36 | #include <asm/mce.h> |
9fda6a06 | 37 | #include <asm/vm86.h> |
7b32aead | 38 | #include <asm/switch_to.h> |
b7ffc44d | 39 | #include <asm/desc.h> |
90e24014 | 40 | |
45046892 TG |
41 | /* |
42 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
43 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
44 | * so they are allowed to end up in the .data..cacheline_aligned | |
45 | * section. Since TSS's are completely CPU-local, we want them | |
46 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
47 | */ | |
d0a0de21 AL |
48 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
49 | .x86_tss = { | |
d9e05cc5 | 50 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
51 | #ifdef CONFIG_X86_32 |
52 | .ss0 = __KERNEL_DS, | |
53 | .ss1 = __KERNEL_CS, | |
54 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
55 | #endif | |
56 | }, | |
57 | #ifdef CONFIG_X86_32 | |
58 | /* | |
59 | * Note that the .io_bitmap member must be extra-big. This is because | |
60 | * the CPU will access an additional byte beyond the end of the IO | |
61 | * permission bitmap. The extra byte must be all 1 bits, and must | |
62 | * be within the limit. | |
63 | */ | |
64 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
65 | #endif | |
2a41aa4f AL |
66 | #ifdef CONFIG_X86_32 |
67 | .SYSENTER_stack_canary = STACK_END_MAGIC, | |
68 | #endif | |
d0a0de21 | 69 | }; |
de71ad2c | 70 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 71 | |
b7ceaec1 AL |
72 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
73 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 74 | |
55ccf3fe SS |
75 | /* |
76 | * this gets called so that we can store lazy state into memory and copy the | |
77 | * current task into the new thread. | |
78 | */ | |
61c4628b SS |
79 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
80 | { | |
5aaeb5c0 | 81 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
82 | #ifdef CONFIG_VM86 |
83 | dst->thread.vm86 = NULL; | |
84 | #endif | |
f1853505 | 85 | |
c69e098b | 86 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 87 | } |
7f424a8b | 88 | |
389d1fb1 JF |
89 | /* |
90 | * Free current thread data structures etc.. | |
91 | */ | |
e6464694 | 92 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 93 | { |
e6464694 | 94 | struct thread_struct *t = &tsk->thread; |
250981e6 | 95 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 96 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 97 | |
250981e6 | 98 | if (bp) { |
24933b82 | 99 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 100 | |
389d1fb1 JF |
101 | t->io_bitmap_ptr = NULL; |
102 | clear_thread_flag(TIF_IO_BITMAP); | |
103 | /* | |
104 | * Careful, clear this in the TSS too: | |
105 | */ | |
106 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
107 | t->io_bitmap_max = 0; | |
108 | put_cpu(); | |
250981e6 | 109 | kfree(bp); |
389d1fb1 | 110 | } |
1dcc8d7b | 111 | |
9fda6a06 BG |
112 | free_vm86(t); |
113 | ||
50338615 | 114 | fpu__drop(fpu); |
389d1fb1 JF |
115 | } |
116 | ||
117 | void flush_thread(void) | |
118 | { | |
119 | struct task_struct *tsk = current; | |
120 | ||
24f1e32c | 121 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 122 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 123 | |
04c8e01d | 124 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
125 | } |
126 | ||
127 | static void hard_disable_TSC(void) | |
128 | { | |
375074cc | 129 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
130 | } |
131 | ||
132 | void disable_TSC(void) | |
133 | { | |
134 | preempt_disable(); | |
135 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
136 | /* | |
137 | * Must flip the CPU state synchronously with | |
138 | * TIF_NOTSC in the current running context. | |
139 | */ | |
140 | hard_disable_TSC(); | |
141 | preempt_enable(); | |
142 | } | |
143 | ||
144 | static void hard_enable_TSC(void) | |
145 | { | |
375074cc | 146 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
147 | } |
148 | ||
149 | static void enable_TSC(void) | |
150 | { | |
151 | preempt_disable(); | |
152 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
153 | /* | |
154 | * Must flip the CPU state synchronously with | |
155 | * TIF_NOTSC in the current running context. | |
156 | */ | |
157 | hard_enable_TSC(); | |
158 | preempt_enable(); | |
159 | } | |
160 | ||
161 | int get_tsc_mode(unsigned long adr) | |
162 | { | |
163 | unsigned int val; | |
164 | ||
165 | if (test_thread_flag(TIF_NOTSC)) | |
166 | val = PR_TSC_SIGSEGV; | |
167 | else | |
168 | val = PR_TSC_ENABLE; | |
169 | ||
170 | return put_user(val, (unsigned int __user *)adr); | |
171 | } | |
172 | ||
173 | int set_tsc_mode(unsigned int val) | |
174 | { | |
175 | if (val == PR_TSC_SIGSEGV) | |
176 | disable_TSC(); | |
177 | else if (val == PR_TSC_ENABLE) | |
178 | enable_TSC(); | |
179 | else | |
180 | return -EINVAL; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
186 | struct tss_struct *tss) | |
187 | { | |
188 | struct thread_struct *prev, *next; | |
189 | ||
190 | prev = &prev_p->thread; | |
191 | next = &next_p->thread; | |
192 | ||
ea8e61b7 PZ |
193 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
194 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
195 | unsigned long debugctl = get_debugctlmsr(); | |
196 | ||
197 | debugctl &= ~DEBUGCTLMSR_BTF; | |
198 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
199 | debugctl |= DEBUGCTLMSR_BTF; | |
200 | ||
201 | update_debugctlmsr(debugctl); | |
202 | } | |
389d1fb1 | 203 | |
389d1fb1 JF |
204 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
205 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
206 | /* prev and next are different */ | |
207 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
208 | hard_disable_TSC(); | |
209 | else | |
210 | hard_enable_TSC(); | |
211 | } | |
212 | ||
213 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
214 | /* | |
215 | * Copy the relevant range of the IO bitmap. | |
216 | * Normally this is 128 bytes or less: | |
217 | */ | |
218 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
219 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
b7ffc44d AL |
220 | |
221 | /* | |
222 | * Make sure that the TSS limit is correct for the CPU | |
223 | * to notice the IO bitmap. | |
224 | */ | |
b7ceaec1 | 225 | refresh_tss_limit(); |
389d1fb1 JF |
226 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { |
227 | /* | |
228 | * Clear any possible leftover bits: | |
229 | */ | |
230 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
231 | } | |
7c68af6e | 232 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
233 | } |
234 | ||
00dba564 TG |
235 | /* |
236 | * Idle related variables and functions | |
237 | */ | |
d1896049 | 238 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
239 | EXPORT_SYMBOL(boot_option_idle_override); |
240 | ||
a476bda3 | 241 | static void (*x86_idle)(void); |
00dba564 | 242 | |
90e24014 RW |
243 | #ifndef CONFIG_SMP |
244 | static inline void play_dead(void) | |
245 | { | |
246 | BUG(); | |
247 | } | |
248 | #endif | |
249 | ||
7d1a9417 TG |
250 | void arch_cpu_idle_enter(void) |
251 | { | |
6a369583 | 252 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 253 | local_touch_nmi(); |
7d1a9417 | 254 | } |
90e24014 | 255 | |
7d1a9417 TG |
256 | void arch_cpu_idle_dead(void) |
257 | { | |
258 | play_dead(); | |
259 | } | |
90e24014 | 260 | |
7d1a9417 TG |
261 | /* |
262 | * Called from the generic idle code. | |
263 | */ | |
264 | void arch_cpu_idle(void) | |
265 | { | |
16f8b05a | 266 | x86_idle(); |
90e24014 RW |
267 | } |
268 | ||
00dba564 | 269 | /* |
7d1a9417 | 270 | * We use this if we don't have any better idle routine.. |
00dba564 | 271 | */ |
6727ad9e | 272 | void __cpuidle default_idle(void) |
00dba564 | 273 | { |
4d0e42cc | 274 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 275 | safe_halt(); |
4d0e42cc | 276 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 277 | } |
60b8b1de | 278 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
279 | EXPORT_SYMBOL(default_idle); |
280 | #endif | |
281 | ||
6a377ddc LB |
282 | #ifdef CONFIG_XEN |
283 | bool xen_set_default_idle(void) | |
e5fd47bf | 284 | { |
a476bda3 | 285 | bool ret = !!x86_idle; |
e5fd47bf | 286 | |
a476bda3 | 287 | x86_idle = default_idle; |
e5fd47bf KRW |
288 | |
289 | return ret; | |
290 | } | |
6a377ddc | 291 | #endif |
d3ec5cae IV |
292 | void stop_this_cpu(void *dummy) |
293 | { | |
294 | local_irq_disable(); | |
295 | /* | |
296 | * Remove this CPU: | |
297 | */ | |
4f062896 | 298 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 299 | disable_local_APIC(); |
8838eb6c | 300 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 301 | |
27be4570 LB |
302 | for (;;) |
303 | halt(); | |
7f424a8b PZ |
304 | } |
305 | ||
aa276e1c | 306 | /* |
07c94a38 BP |
307 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
308 | * states (local apic timer and TSC stop). | |
aa276e1c | 309 | */ |
02c68a02 | 310 | static void amd_e400_idle(void) |
aa276e1c | 311 | { |
07c94a38 BP |
312 | /* |
313 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
314 | * gets set after static_cpu_has() places have been converted via | |
315 | * alternatives. | |
316 | */ | |
317 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
318 | default_idle(); | |
319 | return; | |
aa276e1c TG |
320 | } |
321 | ||
07c94a38 | 322 | tick_broadcast_enter(); |
aa276e1c | 323 | |
07c94a38 | 324 | default_idle(); |
0beefa20 | 325 | |
07c94a38 BP |
326 | /* |
327 | * The switch back from broadcast mode needs to be called with | |
328 | * interrupts disabled. | |
329 | */ | |
330 | local_irq_disable(); | |
331 | tick_broadcast_exit(); | |
332 | local_irq_enable(); | |
aa276e1c TG |
333 | } |
334 | ||
b253149b LB |
335 | /* |
336 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
337 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
338 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
339 | * | |
340 | * Some AMD machines are the opposite, they depend on using HALT. | |
341 | * | |
342 | * So for default C1, which is used during boot until cpuidle loads, | |
343 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
344 | */ | |
345 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
346 | { | |
347 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
348 | return 0; | |
349 | ||
08e237fa | 350 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
351 | return 0; |
352 | ||
353 | return 1; | |
354 | } | |
355 | ||
356 | /* | |
0fb0328d HR |
357 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
358 | * with interrupts enabled and no flags, which is backwards compatible with the | |
359 | * original MWAIT implementation. | |
b253149b | 360 | */ |
6727ad9e | 361 | static __cpuidle void mwait_idle(void) |
b253149b | 362 | { |
f8e617f4 | 363 | if (!current_set_polling_and_test()) { |
e43d0189 | 364 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 365 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 366 | mb(); /* quirk */ |
b253149b | 367 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 368 | mb(); /* quirk */ |
f8e617f4 | 369 | } |
b253149b LB |
370 | |
371 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
372 | if (!need_resched()) |
373 | __sti_mwait(0, 0); | |
374 | else | |
375 | local_irq_enable(); | |
e43d0189 | 376 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 377 | } else { |
b253149b | 378 | local_irq_enable(); |
f8e617f4 MG |
379 | } |
380 | __current_clr_polling(); | |
b253149b LB |
381 | } |
382 | ||
148f9bb8 | 383 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 384 | { |
3e5095d1 | 385 | #ifdef CONFIG_SMP |
7d1a9417 | 386 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 387 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 388 | #endif |
7d1a9417 | 389 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
390 | return; |
391 | ||
3344ed30 | 392 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 393 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 394 | x86_idle = amd_e400_idle; |
b253149b LB |
395 | } else if (prefer_mwait_c1_over_halt(c)) { |
396 | pr_info("using mwait in idle threads\n"); | |
397 | x86_idle = mwait_idle; | |
6ddd2a27 | 398 | } else |
a476bda3 | 399 | x86_idle = default_idle; |
7f424a8b PZ |
400 | } |
401 | ||
07c94a38 | 402 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 403 | { |
07c94a38 BP |
404 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
405 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
406 | local_irq_disable(); | |
407 | tick_broadcast_force(); | |
408 | local_irq_enable(); | |
409 | } | |
30e1e6d1 RR |
410 | } |
411 | ||
e7ff3a47 TG |
412 | void __init arch_post_acpi_subsys_init(void) |
413 | { | |
414 | u32 lo, hi; | |
415 | ||
416 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
417 | return; | |
418 | ||
419 | /* | |
420 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
421 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
422 | * MSR_K8_INT_PENDING_MSG. | |
423 | */ | |
424 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
425 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
426 | return; | |
427 | ||
428 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
429 | ||
430 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
431 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
432 | pr_info("System has AMD C1E enabled\n"); | |
433 | } | |
434 | ||
7f424a8b PZ |
435 | static int __init idle_setup(char *str) |
436 | { | |
ab6bc3e3 CG |
437 | if (!str) |
438 | return -EINVAL; | |
439 | ||
7f424a8b | 440 | if (!strcmp(str, "poll")) { |
c767a54b | 441 | pr_info("using polling idle threads\n"); |
d1896049 | 442 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 443 | cpu_idle_poll_ctrl(true); |
d1896049 | 444 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
445 | /* |
446 | * When the boot option of idle=halt is added, halt is | |
447 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
448 | * won't be used again. | |
449 | * To continue to load the CPU idle driver, don't touch | |
450 | * the boot_option_idle_override. | |
451 | */ | |
a476bda3 | 452 | x86_idle = default_idle; |
d1896049 | 453 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
454 | } else if (!strcmp(str, "nomwait")) { |
455 | /* | |
456 | * If the boot option of "idle=nomwait" is added, | |
457 | * it means that mwait will be disabled for CPU C2/C3 | |
458 | * states. In such case it won't touch the variable | |
459 | * of boot_option_idle_override. | |
460 | */ | |
d1896049 | 461 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 462 | } else |
7f424a8b PZ |
463 | return -1; |
464 | ||
7f424a8b PZ |
465 | return 0; |
466 | } | |
467 | early_param("idle", idle_setup); | |
468 | ||
9d62dcdf AW |
469 | unsigned long arch_align_stack(unsigned long sp) |
470 | { | |
471 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
472 | sp -= get_random_int() % 8192; | |
473 | return sp & ~0xf; | |
474 | } | |
475 | ||
476 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
477 | { | |
9c6f0902 | 478 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
479 | } |
480 | ||
ffcb043b BG |
481 | /* |
482 | * Return saved PC of a blocked thread. | |
483 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
484 | */ | |
485 | unsigned long thread_saved_pc(struct task_struct *tsk) | |
486 | { | |
487 | struct inactive_task_frame *frame = | |
488 | (struct inactive_task_frame *) READ_ONCE(tsk->thread.sp); | |
489 | return READ_ONCE_NOCHECK(frame->ret_addr); | |
490 | } | |
491 | ||
7ba78053 TG |
492 | /* |
493 | * Called from fs/proc with a reference on @p to find the function | |
494 | * which called into schedule(). This needs to be done carefully | |
495 | * because the task might wake up and we might look at a stack | |
496 | * changing under us. | |
497 | */ | |
498 | unsigned long get_wchan(struct task_struct *p) | |
499 | { | |
74327a3e | 500 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
501 | int count = 0; |
502 | ||
503 | if (!p || p == current || p->state == TASK_RUNNING) | |
504 | return 0; | |
505 | ||
74327a3e AL |
506 | if (!try_get_task_stack(p)) |
507 | return 0; | |
508 | ||
7ba78053 TG |
509 | start = (unsigned long)task_stack_page(p); |
510 | if (!start) | |
74327a3e | 511 | goto out; |
7ba78053 TG |
512 | |
513 | /* | |
514 | * Layout of the stack page: | |
515 | * | |
516 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
517 | * PADDING | |
518 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
519 | * stack | |
15f4eae7 | 520 | * ----------- bottom = start |
7ba78053 TG |
521 | * |
522 | * The tasks stack pointer points at the location where the | |
523 | * framepointer is stored. The data on the stack is: | |
524 | * ... IP FP ... IP FP | |
525 | * | |
526 | * We need to read FP and IP, so we need to adjust the upper | |
527 | * bound by another unsigned long. | |
528 | */ | |
529 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
530 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 531 | bottom = start; |
7ba78053 TG |
532 | |
533 | sp = READ_ONCE(p->thread.sp); | |
534 | if (sp < bottom || sp > top) | |
74327a3e | 535 | goto out; |
7ba78053 | 536 | |
7b32aead | 537 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
538 | do { |
539 | if (fp < bottom || fp > top) | |
74327a3e | 540 | goto out; |
f7d27c35 | 541 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
542 | if (!in_sched_functions(ip)) { |
543 | ret = ip; | |
544 | goto out; | |
545 | } | |
f7d27c35 | 546 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 547 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
548 | |
549 | out: | |
550 | put_task_stack(p); | |
551 | return ret; | |
7ba78053 | 552 | } |