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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda | 21 | /* |
57f26649 NP |
22 | * There are a few constraints to be concerned with. |
23 | * - Real mode exceptions code/data must be located at their physical location. | |
24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
25 | * - Fixed location code must not call directly beyond the __end_interrupts | |
26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
27 | * must be used. | |
28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
29 | * virtual 0xc00... | |
30 | * - Conditional branch targets must be within +/-32K of caller. | |
31 | * | |
32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
33 | * therefore don't have to run in physically located code or rfid to | |
34 | * virtual mode kernel code. However on relocatable kernels they do have | |
35 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
36 | * the exception vectors) may be located elsewhere. | |
37 | * | |
38 | * Virtual exceptions correspond with physical, except their entry points | |
39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
40 | * offset applied. Virtual exceptions are enabled with the Alternate | |
41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
43 | * cause exceptions to be delivered in real mode. | |
44 | * | |
45 | * It's impossible to receive interrupts below 0x300 via AIL. | |
46 | * | |
47 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
49 | * | |
50 | * | |
0ebc4cda BH |
51 | * We layout physical memory as follows: |
52 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
54 | * 0x1900 - 0x3fff : Real mode trampolines | |
55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
56 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 57 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
59 | * setup code, rest of kernel. | |
e0319829 NP |
60 | * |
61 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
62 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
63 | * vectors there. | |
57f26649 NP |
64 | */ |
65 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
66 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
67 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
68 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
69 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
70 | /* | |
71 | * Data area reserved for FWNMI option. | |
72 | * This address (0x7000) is fixed by the RPA. | |
73 | * pseries and powernv need to keep the whole page from | |
74 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 75 | */ |
57f26649 NP |
76 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
77 | OPEN_TEXT_SECTION(0x8000) | |
78 | #else | |
79 | OPEN_TEXT_SECTION(0x7000) | |
80 | #endif | |
81 | ||
82 | USE_FIXED_SECTION(real_vectors) | |
83 | ||
0ebc4cda BH |
84 | /* |
85 | * This is the start of the interrupt handlers for pSeries | |
86 | * This code runs with relocation off. | |
87 | * Code from here to __end_interrupts gets copied down to real | |
88 | * address 0x100 when we are running a relocatable kernel. | |
89 | * Therefore any relative branches in this section must only | |
90 | * branch to labels in this section. | |
91 | */ | |
0ebc4cda BH |
92 | .globl __start_interrupts |
93 | __start_interrupts: | |
94 | ||
e0319829 NP |
95 | /* No virt vectors corresponding with 0x0..0x100 */ |
96 | EXC_VIRT_NONE(0x4000, 0x4100) | |
97 | ||
fb479e44 | 98 | |
948cf67c | 99 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
100 | /* |
101 | * If running native on arch 2.06 or later, check if we are waking up | |
a37c15c3 BH |
102 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
103 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
104 | * saving state. The idle wakeup handler initially runs in real mode, | |
105 | * but we branch to the 0xc000... address so we can turn on relocation | |
106 | * with mtmsr. | |
948cf67c | 107 | */ |
fb479e44 NP |
108 | #define IDLETEST(n) \ |
109 | BEGIN_FTR_SECTION ; \ | |
110 | mfspr r10,SPRN_SRR1 ; \ | |
111 | rlwinm. r10,r10,47-31,30,31 ; \ | |
112 | beq- 1f ; \ | |
113 | cmpwi cr3,r10,2 ; \ | |
114 | BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ | |
115 | 1: \ | |
116 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) | |
117 | #else | |
118 | #define IDLETEST NOTEST | |
119 | #endif | |
371fefd6 | 120 | |
fb479e44 NP |
121 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
122 | SET_SCRATCH0(r13) | |
f23ed166 NP |
123 | GET_PACA(r13) |
124 | clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */ | |
125 | EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD, | |
fb479e44 NP |
126 | IDLETEST, 0x100) |
127 | ||
128 | EXC_REAL_END(system_reset, 0x100, 0x200) | |
129 | EXC_VIRT_NONE(0x4100, 0x4200) | |
130 | ||
131 | #ifdef CONFIG_PPC_P7_NAP | |
132 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
f23ed166 NP |
133 | BEGIN_FTR_SECTION |
134 | GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */ | |
135 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
5fa6b6bd | 136 | bl pnv_restore_hyp_resource |
77b54e9f | 137 | |
7cba160a SP |
138 | li r0,PNV_THREAD_RUNNING |
139 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
371fefd6 | 140 | |
3a167bea | 141 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
142 | li r0,KVM_HWTHREAD_IN_KERNEL |
143 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
144 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
145 | sync | |
146 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
147 | cmpwi r0,0 | |
148 | beq 1f | |
f148cf06 | 149 | BRANCH_TO_KVM(r10, kvm_start_guest) |
371fefd6 PM |
150 | 1: |
151 | #endif | |
152 | ||
56548fc0 PM |
153 | /* Return SRR1 from power7_nap() */ |
154 | mfspr r3,SPRN_SRR1 | |
17065671 | 155 | blt cr3,2f |
5fa6b6bd SP |
156 | b pnv_wakeup_loss |
157 | 2: b pnv_wakeup_noloss | |
fb479e44 | 158 | #endif |
aca79d2b | 159 | |
582baf44 NP |
160 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) |
161 | ||
162 | #ifdef CONFIG_PPC_PSERIES | |
163 | /* | |
164 | * Vectors for the FWNMI option. Share common code. | |
165 | */ | |
166 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
167 | SET_SCRATCH0(r13) /* save r13 */ | |
168 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, | |
169 | NOTEST, 0x100) | |
170 | #endif /* CONFIG_PPC_PSERIES */ | |
171 | ||
0ebc4cda | 172 | |
da2bc464 | 173 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
b01c8b54 PM |
174 | /* This is moved out of line as it can be patched by FW, but |
175 | * some code path might still want to branch into the original | |
176 | * vector | |
177 | */ | |
1707dd16 | 178 | SET_SCRATCH0(r13) /* save r13 */ |
bc14c491 MS |
179 | /* |
180 | * Running native on arch 2.06 or later, we may wakeup from winkle | |
f23ed166 | 181 | * inside machine check. If yes, then last bit of HSPRG0 would be set |
bc14c491 | 182 | * to 1. Hence clear it unconditionally. |
1c51089f | 183 | */ |
bc14c491 MS |
184 | GET_PACA(r13) |
185 | clrrdi r13,r13,1 | |
186 | SET_PACA(r13) | |
1707dd16 | 187 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 | 188 | BEGIN_FTR_SECTION |
2513767d | 189 | b machine_check_powernv_early |
1e9b4507 | 190 | FTR_SECTION_ELSE |
1707dd16 | 191 | b machine_check_pSeries_0 |
1e9b4507 | 192 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 | 193 | EXC_REAL_END(machine_check, 0x200, 0x300) |
afcf0095 NP |
194 | EXC_VIRT_NONE(0x4200, 0x4300) |
195 | TRAMP_REAL_BEGIN(machine_check_powernv_early) | |
196 | BEGIN_FTR_SECTION | |
197 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
198 | /* | |
199 | * Register contents: | |
200 | * R13 = PACA | |
201 | * R9 = CR | |
202 | * Original R9 to R13 is saved on PACA_EXMC | |
203 | * | |
204 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
205 | * the nested MCE upto level 4 to avoid stack overflow). | |
206 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
207 | * | |
208 | * We use paca->in_mce to check whether this is the first entry or | |
209 | * nested machine check. We increment paca->in_mce to track nested | |
210 | * machine checks. | |
211 | * | |
212 | * If this is the first entry then set stack pointer to | |
213 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
214 | * stack frame on mc_emergency stack. | |
215 | * | |
216 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
217 | * checkstop if we get another machine check exception before we do | |
218 | * rfid with MSR_ME=1. | |
219 | */ | |
220 | mr r11,r1 /* Save r1 */ | |
221 | lhz r10,PACA_IN_MCE(r13) | |
222 | cmpwi r10,0 /* Are we in nested machine check */ | |
223 | bne 0f /* Yes, we are. */ | |
224 | /* First machine check entry */ | |
225 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
226 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
227 | addi r10,r10,1 /* increment paca->in_mce */ | |
228 | sth r10,PACA_IN_MCE(r13) | |
229 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
230 | cmpwi r10,4 | |
231 | bgt 2f /* Check if we hit limit of 4 */ | |
232 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
233 | std r11,0(r1) /* make stack chain pointer */ | |
234 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
235 | std r11,_NIP(r1) | |
236 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
237 | std r11,_MSR(r1) | |
238 | mfspr r11,SPRN_DAR /* Save DAR */ | |
239 | std r11,_DAR(r1) | |
240 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
241 | std r11,_DSISR(r1) | |
242 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
243 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
244 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
245 | mfmsr r11 /* get MSR value */ | |
246 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
247 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
248 | LOAD_HANDLER(r12, machine_check_handle_early) | |
249 | 1: mtspr SPRN_SRR0,r12 | |
250 | mtspr SPRN_SRR1,r11 | |
251 | rfid | |
252 | b . /* prevent speculative execution */ | |
253 | 2: | |
254 | /* Stack overflow. Stay on emergency stack and panic. | |
255 | * Keep the ME bit off while panic-ing, so that if we hit | |
256 | * another machine check we checkstop. | |
257 | */ | |
258 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
259 | ld r11,PACAKMSR(r13) | |
260 | LOAD_HANDLER(r12, unrecover_mce) | |
261 | li r10,MSR_ME | |
262 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
263 | b 1b | |
264 | b . /* prevent speculative execution */ | |
265 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
266 | ||
267 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
268 | .globl machine_check_fwnmi | |
269 | machine_check_fwnmi: | |
270 | SET_SCRATCH0(r13) /* save r13 */ | |
271 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
272 | machine_check_pSeries_0: | |
273 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
274 | /* | |
275 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
276 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
277 | * used, so nested machine check corrupts it. machine_check_common | |
278 | * enables MSR_RI. | |
279 | */ | |
280 | ld r10,PACAKMSR(r13) | |
281 | xori r10,r10,MSR_RI | |
282 | mfspr r11,SPRN_SRR0 | |
283 | LOAD_HANDLER(r12, machine_check_common) | |
284 | mtspr SPRN_SRR0,r12 | |
285 | mfspr r12,SPRN_SRR1 | |
286 | mtspr SPRN_SRR1,r10 | |
287 | rfid | |
288 | b . /* prevent speculative execution */ | |
289 | ||
290 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
291 | ||
292 | EXC_COMMON_BEGIN(machine_check_common) | |
293 | /* | |
294 | * Machine check is different because we use a different | |
295 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
296 | */ | |
297 | mfspr r10,SPRN_DAR | |
298 | std r10,PACA_EXMC+EX_DAR(r13) | |
299 | mfspr r10,SPRN_DSISR | |
300 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
301 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
302 | FINISH_NAP | |
303 | RECONCILE_IRQ_STATE(r10, r11) | |
304 | ld r3,PACA_EXMC+EX_DAR(r13) | |
305 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
306 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
307 | li r10,MSR_RI | |
308 | mtmsrd r10,1 | |
309 | std r3,_DAR(r1) | |
310 | std r4,_DSISR(r1) | |
311 | bl save_nvgprs | |
312 | addi r3,r1,STACK_FRAME_OVERHEAD | |
313 | bl machine_check_exception | |
314 | b ret_from_except | |
315 | ||
316 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
317 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
318 | li r0,MSR_RI; \ | |
319 | mfmsr r9; /* get MSR value */ \ | |
320 | andc r9,r9,r0; \ | |
321 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
322 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
323 | ld r9,_MSR(r1); \ | |
324 | mtspr SPRN_SRR1,r9; \ | |
325 | ld r3,_NIP(r1); \ | |
326 | mtspr SPRN_SRR0,r3; \ | |
327 | ld r9,_CTR(r1); \ | |
328 | mtctr r9; \ | |
329 | ld r9,_XER(r1); \ | |
330 | mtxer r9; \ | |
331 | ld r9,_LINK(r1); \ | |
332 | mtlr r9; \ | |
333 | REST_GPR(0, r1); \ | |
334 | REST_8GPRS(2, r1); \ | |
335 | REST_GPR(10, r1); \ | |
336 | ld r11,_CCR(r1); \ | |
337 | mtcr r11; \ | |
338 | /* Decrement paca->in_mce. */ \ | |
339 | lhz r12,PACA_IN_MCE(r13); \ | |
340 | subi r12,r12,1; \ | |
341 | sth r12,PACA_IN_MCE(r13); \ | |
342 | REST_GPR(11, r1); \ | |
343 | REST_2GPRS(12, r1); \ | |
344 | /* restore original r1. */ \ | |
345 | ld r1,GPR1(r1) | |
346 | ||
347 | /* | |
348 | * Handle machine check early in real mode. We come here with | |
349 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
350 | */ | |
351 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
352 | std r0,GPR0(r1) /* Save r0 */ | |
353 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
354 | bl save_nvgprs | |
355 | addi r3,r1,STACK_FRAME_OVERHEAD | |
356 | bl machine_check_early | |
357 | std r3,RESULT(r1) /* Save result */ | |
358 | ld r12,_MSR(r1) | |
359 | #ifdef CONFIG_PPC_P7_NAP | |
360 | /* | |
361 | * Check if thread was in power saving mode. We come here when any | |
362 | * of the following is true: | |
363 | * a. thread wasn't in power saving mode | |
364 | * b. thread was in power saving mode with no state loss, | |
365 | * supervisor state loss or hypervisor state loss. | |
366 | * | |
367 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
368 | */ | |
369 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
370 | beq 4f /* No, it wasn;t */ | |
371 | /* Thread was in power saving mode. Go back to nap again. */ | |
372 | cmpwi r11,2 | |
373 | blt 3f | |
374 | /* Supervisor/Hypervisor state loss */ | |
375 | li r0,1 | |
376 | stb r0,PACA_NAPSTATELOST(r13) | |
377 | 3: bl machine_check_queue_event | |
378 | MACHINE_CHECK_HANDLER_WINDUP | |
379 | GET_PACA(r13) | |
380 | ld r1,PACAR1(r13) | |
381 | /* | |
382 | * Check what idle state this CPU was in and go back to same mode | |
383 | * again. | |
384 | */ | |
385 | lbz r3,PACA_THREAD_IDLE_STATE(r13) | |
386 | cmpwi r3,PNV_THREAD_NAP | |
387 | bgt 10f | |
407ac19b | 388 | IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) |
afcf0095 NP |
389 | /* No return */ |
390 | 10: | |
391 | cmpwi r3,PNV_THREAD_SLEEP | |
392 | bgt 2f | |
407ac19b | 393 | IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) |
afcf0095 NP |
394 | /* No return */ |
395 | ||
396 | 2: | |
397 | /* | |
398 | * Go back to winkle. Please note that this thread was woken up in | |
399 | * machine check from winkle and have not restored the per-subcore | |
f23ed166 | 400 | * state. Hence before going back to winkle, set last bit of HSPRG0 |
afcf0095 NP |
401 | * to 1. This will make sure that if this thread gets woken up |
402 | * again at reset vector 0x100 then it will get chance to restore | |
403 | * the subcore state. | |
404 | */ | |
405 | ori r13,r13,1 | |
406 | SET_PACA(r13) | |
407ac19b | 407 | IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) |
afcf0095 NP |
408 | /* No return */ |
409 | 4: | |
410 | #endif | |
411 | /* | |
412 | * Check if we are coming from hypervisor userspace. If yes then we | |
413 | * continue in host kernel in V mode to deliver the MC event. | |
414 | */ | |
415 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
416 | beq 5f | |
417 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
418 | bne 9f /* continue in V mode if we are. */ | |
419 | ||
420 | 5: | |
421 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
422 | /* | |
423 | * We are coming from kernel context. Check if we are coming from | |
424 | * guest. if yes, then we can continue. We will fall through | |
425 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
426 | */ | |
427 | lbz r11,HSTATE_IN_GUEST(r13) | |
428 | cmpwi r11,0 /* Check if coming from guest */ | |
429 | bne 9f /* continue if we are. */ | |
430 | #endif | |
431 | /* | |
432 | * At this point we are not sure about what context we come from. | |
433 | * Queue up the MCE event and return from the interrupt. | |
434 | * But before that, check if this is an un-recoverable exception. | |
435 | * If yes, then stay on emergency stack and panic. | |
436 | */ | |
437 | andi. r11,r12,MSR_RI | |
438 | bne 2f | |
439 | 1: mfspr r11,SPRN_SRR0 | |
440 | LOAD_HANDLER(r10,unrecover_mce) | |
441 | mtspr SPRN_SRR0,r10 | |
442 | ld r10,PACAKMSR(r13) | |
443 | /* | |
444 | * We are going down. But there are chances that we might get hit by | |
445 | * another MCE during panic path and we may run into unstable state | |
446 | * with no way out. Hence, turn ME bit off while going down, so that | |
447 | * when another MCE is hit during panic path, system will checkstop | |
448 | * and hypervisor will get restarted cleanly by SP. | |
449 | */ | |
450 | li r3,MSR_ME | |
451 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
452 | mtspr SPRN_SRR1,r10 | |
453 | rfid | |
454 | b . | |
455 | 2: | |
456 | /* | |
457 | * Check if we have successfully handled/recovered from error, if not | |
458 | * then stay on emergency stack and panic. | |
459 | */ | |
460 | ld r3,RESULT(r1) /* Load result */ | |
461 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
462 | ||
463 | beq 1b /* if !handled then panic */ | |
464 | /* | |
465 | * Return from MC interrupt. | |
466 | * Queue up the MCE event so that we can log it later, while | |
467 | * returning from kernel or opal call. | |
468 | */ | |
469 | bl machine_check_queue_event | |
470 | MACHINE_CHECK_HANDLER_WINDUP | |
471 | rfid | |
472 | 9: | |
473 | /* Deliver the machine check to host kernel in V mode. */ | |
474 | MACHINE_CHECK_HANDLER_WINDUP | |
475 | b machine_check_pSeries | |
476 | ||
477 | EXC_COMMON_BEGIN(unrecover_mce) | |
478 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
479 | addi r3,r1,STACK_FRAME_OVERHEAD | |
480 | bl machine_check_exception | |
481 | /* | |
482 | * We will not reach here. Even if we did, there is no way out. Call | |
483 | * unrecoverable_exception and die. | |
484 | */ | |
485 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
486 | bl unrecoverable_exception | |
487 | b 1b | |
488 | ||
0ebc4cda | 489 | |
da2bc464 | 490 | EXC_REAL(data_access, 0x300, 0x380) |
80795e6c NP |
491 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) |
492 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) | |
493 | ||
494 | EXC_COMMON_BEGIN(data_access_common) | |
495 | /* | |
496 | * Here r13 points to the paca, r9 contains the saved CR, | |
497 | * SRR0 and SRR1 are saved in r11 and r12, | |
498 | * r9 - r13 are saved in paca->exgen. | |
499 | */ | |
500 | mfspr r10,SPRN_DAR | |
501 | std r10,PACA_EXGEN+EX_DAR(r13) | |
502 | mfspr r10,SPRN_DSISR | |
503 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
504 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
505 | RECONCILE_IRQ_STATE(r10, r11) | |
506 | ld r12,_MSR(r1) | |
507 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
508 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
509 | li r5,0x300 | |
510 | std r3,_DAR(r1) | |
511 | std r4,_DSISR(r1) | |
512 | BEGIN_MMU_FTR_SECTION | |
513 | b do_hash_page /* Try to handle as hpte fault */ | |
514 | MMU_FTR_SECTION_ELSE | |
515 | b handle_page_fault | |
516 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
517 | ||
0ebc4cda | 518 | |
da2bc464 | 519 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
673b189a | 520 | SET_SCRATCH0(r13) |
1707dd16 | 521 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 522 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
523 | std r3,PACA_EXSLB+EX_R3(r13) |
524 | mfspr r3,SPRN_DAR | |
b01c8b54 | 525 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 526 | crset 4*cr6+eq |
0ebc4cda | 527 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 528 | b slb_miss_realmode |
0ebc4cda BH |
529 | #else |
530 | /* | |
ad0289e4 | 531 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
532 | * because the distance from here to there depends on where |
533 | * the kernel ends up being put. | |
534 | */ | |
535 | mfctr r11 | |
ad0289e4 | 536 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
537 | mtctr r10 |
538 | bctr | |
539 | #endif | |
da2bc464 | 540 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
0ebc4cda | 541 | |
2b9af6e4 NP |
542 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) |
543 | SET_SCRATCH0(r13) | |
544 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
545 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
546 | std r3,PACA_EXSLB+EX_R3(r13) | |
547 | mfspr r3,SPRN_DAR | |
548 | mfspr r12,SPRN_SRR1 | |
549 | crset 4*cr6+eq | |
550 | #ifndef CONFIG_RELOCATABLE | |
551 | b slb_miss_realmode | |
552 | #else | |
553 | /* | |
554 | * We can't just use a direct branch to slb_miss_realmode | |
555 | * because the distance from here to there depends on where | |
556 | * the kernel ends up being put. | |
557 | */ | |
558 | mfctr r11 | |
559 | LOAD_HANDLER(r10, slb_miss_realmode) | |
560 | mtctr r10 | |
561 | bctr | |
562 | #endif | |
563 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) | |
564 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) | |
565 | ||
566 | ||
da2bc464 | 567 | EXC_REAL(instruction_access, 0x400, 0x480) |
27ce77df NP |
568 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
569 | TRAMP_KVM(PACA_EXGEN, 0x400) | |
570 | ||
571 | EXC_COMMON_BEGIN(instruction_access_common) | |
572 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
573 | RECONCILE_IRQ_STATE(r10, r11) | |
574 | ld r12,_MSR(r1) | |
575 | ld r3,_NIP(r1) | |
576 | andis. r4,r12,0x5820 | |
577 | li r5,0x400 | |
578 | std r3,_DAR(r1) | |
579 | std r4,_DSISR(r1) | |
580 | BEGIN_MMU_FTR_SECTION | |
581 | b do_hash_page /* Try to handle as hpte fault */ | |
582 | MMU_FTR_SECTION_ELSE | |
583 | b handle_page_fault | |
584 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
585 | ||
0ebc4cda | 586 | |
da2bc464 | 587 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
673b189a | 588 | SET_SCRATCH0(r13) |
1707dd16 | 589 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 590 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
591 | std r3,PACA_EXSLB+EX_R3(r13) |
592 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 593 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 594 | crclr 4*cr6+eq |
0ebc4cda | 595 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 596 | b slb_miss_realmode |
0ebc4cda BH |
597 | #else |
598 | mfctr r11 | |
ad0289e4 | 599 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
600 | mtctr r10 |
601 | bctr | |
602 | #endif | |
da2bc464 | 603 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
0ebc4cda | 604 | |
8d04631a NP |
605 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) |
606 | SET_SCRATCH0(r13) | |
607 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
608 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
609 | std r3,PACA_EXSLB+EX_R3(r13) | |
610 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
611 | mfspr r12,SPRN_SRR1 | |
612 | crclr 4*cr6+eq | |
613 | #ifndef CONFIG_RELOCATABLE | |
614 | b slb_miss_realmode | |
615 | #else | |
616 | mfctr r11 | |
617 | LOAD_HANDLER(r10, slb_miss_realmode) | |
618 | mtctr r10 | |
619 | bctr | |
620 | #endif | |
621 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) | |
622 | TRAMP_KVM(PACA_EXSLB, 0x480) | |
623 | ||
624 | ||
625 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ | |
626 | EXC_COMMON_BEGIN(slb_miss_realmode) | |
627 | /* | |
628 | * r13 points to the PACA, r9 contains the saved CR, | |
629 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
630 | * r3 has the faulting address | |
631 | * r9 - r13 are saved in paca->exslb. | |
632 | * r3 is saved in paca->slb_r3 | |
633 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss | |
634 | * We assume we aren't going to take any exceptions during this | |
635 | * procedure. | |
636 | */ | |
637 | mflr r10 | |
638 | #ifdef CONFIG_RELOCATABLE | |
639 | mtctr r11 | |
640 | #endif | |
641 | ||
642 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
643 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
644 | std r3,PACA_EXSLB+EX_DAR(r13) | |
645 | ||
646 | crset 4*cr0+eq | |
647 | #ifdef CONFIG_PPC_STD_MMU_64 | |
648 | BEGIN_MMU_FTR_SECTION | |
649 | bl slb_allocate_realmode | |
650 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) | |
651 | #endif | |
652 | ||
653 | ld r10,PACA_EXSLB+EX_LR(r13) | |
654 | ld r3,PACA_EXSLB+EX_R3(r13) | |
655 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
656 | mtlr r10 | |
657 | ||
658 | beq 8f /* if bad address, make full stack frame */ | |
659 | ||
660 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
661 | beq- 2f | |
662 | ||
663 | /* All done -- return from exception. */ | |
664 | ||
665 | .machine push | |
666 | .machine "power4" | |
667 | mtcrf 0x80,r9 | |
668 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
669 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
670 | .machine pop | |
671 | ||
672 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
673 | ld r9,PACA_EXSLB+EX_R9(r13) | |
674 | ld r10,PACA_EXSLB+EX_R10(r13) | |
675 | ld r11,PACA_EXSLB+EX_R11(r13) | |
676 | ld r12,PACA_EXSLB+EX_R12(r13) | |
677 | ld r13,PACA_EXSLB+EX_R13(r13) | |
678 | rfid | |
679 | b . /* prevent speculative execution */ | |
680 | ||
681 | 2: mfspr r11,SPRN_SRR0 | |
682 | LOAD_HANDLER(r10,unrecov_slb) | |
683 | mtspr SPRN_SRR0,r10 | |
684 | ld r10,PACAKMSR(r13) | |
685 | mtspr SPRN_SRR1,r10 | |
686 | rfid | |
687 | b . | |
688 | ||
689 | 8: mfspr r11,SPRN_SRR0 | |
690 | LOAD_HANDLER(r10,bad_addr_slb) | |
691 | mtspr SPRN_SRR0,r10 | |
692 | ld r10,PACAKMSR(r13) | |
693 | mtspr SPRN_SRR1,r10 | |
694 | rfid | |
695 | b . | |
696 | ||
697 | EXC_COMMON_BEGIN(unrecov_slb) | |
698 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
699 | RECONCILE_IRQ_STATE(r10, r11) | |
700 | bl save_nvgprs | |
701 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
702 | bl unrecoverable_exception | |
703 | b 1b | |
704 | ||
705 | EXC_COMMON_BEGIN(bad_addr_slb) | |
706 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
707 | RECONCILE_IRQ_STATE(r10, r11) | |
708 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
709 | std r3, _DAR(r1) | |
710 | beq cr6, 2f | |
711 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
712 | std r10, _TRAP(r1) | |
713 | 2: bl save_nvgprs | |
714 | addi r3, r1, STACK_FRAME_OVERHEAD | |
715 | bl slb_miss_bad_addr | |
716 | b ret_from_except | |
717 | ||
da2bc464 | 718 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
b3e6b5df | 719 | .globl hardware_interrupt_hv; |
b3e6b5df | 720 | hardware_interrupt_hv: |
a5d4f3ad | 721 | BEGIN_FTR_SECTION |
da2bc464 | 722 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 723 | EXC_HV, SOFTEN_TEST_HV) |
de56a948 | 724 | FTR_SECTION_ELSE |
da2bc464 | 725 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 726 | EXC_STD, SOFTEN_TEST_PR) |
969391c5 | 727 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
da2bc464 ME |
728 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
729 | ||
c138e588 NP |
730 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
731 | .globl hardware_interrupt_relon_hv; | |
732 | hardware_interrupt_relon_hv: | |
733 | BEGIN_FTR_SECTION | |
734 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) | |
735 | FTR_SECTION_ELSE | |
736 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) | |
737 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
738 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) | |
739 | ||
13ed73eb NP |
740 | TRAMP_KVM(PACA_EXGEN, 0x500) |
741 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
742 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
743 | ||
744 | ||
da2bc464 | 745 | EXC_REAL(alignment, 0x600, 0x700) |
f9aa6714 | 746 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) |
da2bc464 | 747 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
748 | EXC_COMMON_BEGIN(alignment_common) |
749 | mfspr r10,SPRN_DAR | |
750 | std r10,PACA_EXGEN+EX_DAR(r13) | |
751 | mfspr r10,SPRN_DSISR | |
752 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
753 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
754 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
755 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
756 | std r3,_DAR(r1) | |
757 | std r4,_DSISR(r1) | |
758 | bl save_nvgprs | |
759 | RECONCILE_IRQ_STATE(r10, r11) | |
760 | addi r3,r1,STACK_FRAME_OVERHEAD | |
761 | bl alignment_exception | |
762 | b ret_from_except | |
763 | ||
da2bc464 ME |
764 | |
765 | EXC_REAL(program_check, 0x700, 0x800) | |
11e87346 | 766 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) |
da2bc464 | 767 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 768 | EXC_COMMON_BEGIN(program_check_common) |
8b1a7b06 CB |
769 | /* |
770 | * It's possible to receive a TM Bad Thing type program check with | |
771 | * userspace register values (in particular r1), but with SRR1 reporting | |
772 | * that we came from the kernel. Normally that would confuse the bad | |
773 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
774 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
775 | * the kernel. | |
776 | */ | |
777 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ | |
778 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ | |
779 | and r10,r10,r12 /* Mask SRR1 with that. */ | |
780 | srdi r10,r10,8 /* Shift it so we can compare */ | |
781 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ | |
782 | bne 1f /* If != go to normal path. */ | |
783 | ||
784 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ | |
785 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ | |
786 | /* 3 in EXCEPTION_PROLOG_COMMON */ | |
787 | mr r10,r1 /* Save r1 */ | |
788 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
789 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
790 | b 3f /* Jump into the macro !! */ | |
791 | 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
11e87346 NP |
792 | bl save_nvgprs |
793 | RECONCILE_IRQ_STATE(r10, r11) | |
794 | addi r3,r1,STACK_FRAME_OVERHEAD | |
795 | bl program_check_exception | |
796 | b ret_from_except | |
797 | ||
b01c8b54 | 798 | |
da2bc464 | 799 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
c78d9b97 | 800 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) |
da2bc464 | 801 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
802 | EXC_COMMON_BEGIN(fp_unavailable_common) |
803 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
804 | bne 1f /* if from user, just load it up */ | |
805 | bl save_nvgprs | |
806 | RECONCILE_IRQ_STATE(r10, r11) | |
807 | addi r3,r1,STACK_FRAME_OVERHEAD | |
808 | bl kernel_fp_unavailable_exception | |
809 | BUG_OPCODE | |
810 | 1: | |
811 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
812 | BEGIN_FTR_SECTION | |
813 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
814 | * transaction), go do TM stuff | |
815 | */ | |
816 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
817 | bne- 2f | |
818 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
819 | #endif | |
820 | bl load_up_fpu | |
821 | b fast_exception_return | |
822 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
823 | 2: /* User process was in a transaction */ | |
824 | bl save_nvgprs | |
825 | RECONCILE_IRQ_STATE(r10, r11) | |
826 | addi r3,r1,STACK_FRAME_OVERHEAD | |
827 | bl fp_unavailable_tm | |
828 | b ret_from_except | |
829 | #endif | |
830 | ||
a5d4f3ad | 831 | |
da2bc464 | 832 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
39c0da57 NP |
833 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) |
834 | TRAMP_KVM(PACA_EXGEN, 0x900) | |
835 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
836 | ||
a485c709 | 837 | |
da2bc464 | 838 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
facc6d74 NP |
839 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) |
840 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) | |
841 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
842 | ||
a5d4f3ad | 843 | |
da2bc464 | 844 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
ca243163 | 845 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) |
da2bc464 | 846 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
847 | #ifdef CONFIG_PPC_DOORBELL |
848 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
849 | #else | |
850 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
851 | #endif | |
852 | ||
0ebc4cda | 853 | |
da2bc464 | 854 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
341215dc | 855 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) |
da2bc464 | 856 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
857 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
858 | ||
40a6d878 PM |
859 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
860 | /* | |
861 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
862 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
863 | * code to save that value into the guest state (it is the guest's PPR | |
864 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
865 | * already saved the PPR. | |
866 | */ | |
867 | #define SYSCALL_KVMTEST \ | |
868 | SET_SCRATCH0(r13); \ | |
869 | GET_PACA(r13); \ | |
870 | std r9,PACA_EXGEN+EX_R9(r13); \ | |
871 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ | |
872 | HMT_MEDIUM; \ | |
873 | std r10,PACA_EXGEN+EX_R10(r13); \ | |
874 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); \ | |
875 | mfcr r9; \ | |
876 | KVMTEST_PR(0xc00); \ | |
877 | GET_SCRATCH0(r13) | |
878 | ||
879 | #else | |
880 | #define SYSCALL_KVMTEST \ | |
881 | HMT_MEDIUM | |
882 | #endif | |
883 | ||
fb479e44 NP |
884 | #define LOAD_SYSCALL_HANDLER(reg) \ |
885 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 NP |
886 | |
887 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ | |
888 | #define SYSCALL_PSERIES_1 \ | |
889 | BEGIN_FTR_SECTION \ | |
890 | cmpdi r0,0x1ebe ; \ | |
891 | beq- 1f ; \ | |
892 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
893 | mr r9,r13 ; \ | |
894 | GET_PACA(r13) ; \ | |
895 | mfspr r11,SPRN_SRR0 ; \ | |
896 | 0: | |
897 | ||
898 | #define SYSCALL_PSERIES_2_RFID \ | |
899 | mfspr r12,SPRN_SRR1 ; \ | |
900 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
901 | mtspr SPRN_SRR0,r10 ; \ | |
902 | ld r10,PACAKMSR(r13) ; \ | |
903 | mtspr SPRN_SRR1,r10 ; \ | |
904 | rfid ; \ | |
905 | b . ; /* prevent speculative execution */ | |
906 | ||
907 | #define SYSCALL_PSERIES_3 \ | |
908 | /* Fast LE/BE switch system call */ \ | |
909 | 1: mfspr r12,SPRN_SRR1 ; \ | |
910 | xori r12,r12,MSR_LE ; \ | |
911 | mtspr SPRN_SRR1,r12 ; \ | |
912 | rfid ; /* return to userspace */ \ | |
913 | b . ; /* prevent speculative execution */ | |
914 | ||
915 | #if defined(CONFIG_RELOCATABLE) | |
916 | /* | |
917 | * We can't branch directly so we do it via the CTR which | |
918 | * is volatile across system calls. | |
919 | */ | |
920 | #define SYSCALL_PSERIES_2_DIRECT \ | |
921 | LOAD_SYSCALL_HANDLER(r12) ; \ | |
922 | mtctr r12 ; \ | |
923 | mfspr r12,SPRN_SRR1 ; \ | |
924 | li r10,MSR_RI ; \ | |
925 | mtmsrd r10,1 ; \ | |
926 | bctr ; | |
927 | #else | |
928 | /* We can branch directly */ | |
929 | #define SYSCALL_PSERIES_2_DIRECT \ | |
930 | mfspr r12,SPRN_SRR1 ; \ | |
931 | li r10,MSR_RI ; \ | |
932 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
933 | b system_call_common ; | |
934 | #endif | |
935 | ||
da2bc464 | 936 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) |
40a6d878 | 937 | SYSCALL_KVMTEST |
742415d6 MN |
938 | SYSCALL_PSERIES_1 |
939 | SYSCALL_PSERIES_2_RFID | |
940 | SYSCALL_PSERIES_3 | |
da2bc464 ME |
941 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
942 | ||
d807ad37 | 943 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) |
40a6d878 | 944 | SYSCALL_KVMTEST |
d807ad37 NP |
945 | SYSCALL_PSERIES_1 |
946 | SYSCALL_PSERIES_2_DIRECT | |
947 | SYSCALL_PSERIES_3 | |
948 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) | |
949 | ||
da2bc464 ME |
950 | TRAMP_KVM(PACA_EXGEN, 0xc00) |
951 | ||
d807ad37 | 952 | |
da2bc464 | 953 | EXC_REAL(single_step, 0xd00, 0xe00) |
bc6675c6 | 954 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
da2bc464 | 955 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 956 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 957 | |
a33532af | 958 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
40a6d878 | 959 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x4e20, 0xe00) |
f5c32c1d NP |
960 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
961 | EXC_COMMON_BEGIN(h_data_storage_common) | |
962 | mfspr r10,SPRN_HDAR | |
963 | std r10,PACA_EXGEN+EX_DAR(r13) | |
964 | mfspr r10,SPRN_HDSISR | |
965 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
966 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
967 | bl save_nvgprs | |
968 | RECONCILE_IRQ_STATE(r10, r11) | |
969 | addi r3,r1,STACK_FRAME_OVERHEAD | |
970 | bl unknown_exception | |
971 | b ret_from_except | |
f5c32c1d | 972 | |
1707dd16 | 973 | |
a33532af | 974 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
40a6d878 | 975 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x4e40, 0xe20) |
82517cab NP |
976 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
977 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
978 | ||
1707dd16 | 979 | |
a33532af NP |
980 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
981 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60, 0xe40) | |
031b4026 NP |
982 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
983 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
984 | ||
1707dd16 | 985 | |
e0319829 NP |
986 | /* |
987 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
988 | * first, and then eventaully from there to the trampoline to get into virtual | |
989 | * mode. | |
990 | */ | |
da2bc464 | 991 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
62f9b03b | 992 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
e0319829 | 993 | EXC_VIRT_NONE(0x4e60, 0x4e80) |
62f9b03b NP |
994 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
995 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
996 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
997 | mr r10,r1 /* Save r1 */ | |
998 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
999 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1000 | std r9,_CCR(r1) /* save CR in stackframe */ | |
1001 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
1002 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
1003 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
1004 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
1005 | std r10,0(r1) /* make stack chain pointer */ | |
1006 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
1007 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
1008 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
1009 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1010 | addi r3,r1,STACK_FRAME_OVERHEAD | |
9d4892ae | 1011 | BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ |
62f9b03b NP |
1012 | /* Windup the stack. */ |
1013 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
1014 | ld r9,_MSR(r1) | |
1015 | mtspr SPRN_HSRR1,r9 | |
1016 | ld r3,_NIP(r1) | |
1017 | mtspr SPRN_HSRR0,r3 | |
1018 | ld r9,_CTR(r1) | |
1019 | mtctr r9 | |
1020 | ld r9,_XER(r1) | |
1021 | mtxer r9 | |
1022 | ld r9,_LINK(r1) | |
1023 | mtlr r9 | |
1024 | REST_GPR(0, r1) | |
1025 | REST_8GPRS(2, r1) | |
1026 | REST_GPR(10, r1) | |
1027 | ld r11,_CCR(r1) | |
1028 | mtcr r11 | |
1029 | REST_GPR(11, r1) | |
1030 | REST_2GPRS(12, r1) | |
1031 | /* restore original r1. */ | |
1032 | ld r1,GPR1(r1) | |
1033 | ||
1034 | /* | |
1035 | * Go to virtual mode and pull the HMI event information from | |
1036 | * firmware. | |
1037 | */ | |
1038 | .globl hmi_exception_after_realmode | |
1039 | hmi_exception_after_realmode: | |
1040 | SET_SCRATCH0(r13) | |
1041 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
1042 | b tramp_real_hmi_exception | |
1043 | ||
1044 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) | |
1045 | ||
1707dd16 | 1046 | |
a33532af NP |
1047 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
1048 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0, 0xe80) | |
9bcb81bf NP |
1049 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1050 | #ifdef CONFIG_PPC_DOORBELL | |
1051 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1052 | #else | |
1053 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1054 | #endif | |
1055 | ||
0ebc4cda | 1056 | |
a33532af NP |
1057 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
1058 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0, 0xea0) | |
74408776 NP |
1059 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1060 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1061 | ||
9baaef0a | 1062 | |
da2bc464 | 1063 | EXC_REAL_NONE(0xec0, 0xf00) |
bda7fea2 NP |
1064 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
1065 | ||
0ebc4cda | 1066 | |
a33532af NP |
1067 | EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
1068 | EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20, 0xf00) | |
b1c7f150 NP |
1069 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1070 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1071 | ||
0ebc4cda | 1072 | |
a33532af NP |
1073 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
1074 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40, 0xf20) | |
d1a0ca9c NP |
1075 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1076 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1077 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1078 | #ifdef CONFIG_ALTIVEC | |
1079 | BEGIN_FTR_SECTION | |
1080 | beq 1f | |
1081 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1082 | BEGIN_FTR_SECTION_NESTED(69) | |
1083 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1084 | * transaction), go do TM stuff | |
1085 | */ | |
1086 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1087 | bne- 2f | |
1088 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1089 | #endif | |
1090 | bl load_up_altivec | |
1091 | b fast_exception_return | |
1092 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1093 | 2: /* User process was in a transaction */ | |
1094 | bl save_nvgprs | |
1095 | RECONCILE_IRQ_STATE(r10, r11) | |
1096 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1097 | bl altivec_unavailable_tm | |
1098 | b ret_from_except | |
1099 | #endif | |
1100 | 1: | |
1101 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1102 | #endif | |
1103 | bl save_nvgprs | |
1104 | RECONCILE_IRQ_STATE(r10, r11) | |
1105 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1106 | bl altivec_unavailable_exception | |
1107 | b ret_from_except | |
1108 | ||
0ebc4cda | 1109 | |
a33532af NP |
1110 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
1111 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60, 0xf40) | |
792cbddd NP |
1112 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1113 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1114 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1115 | #ifdef CONFIG_VSX | |
1116 | BEGIN_FTR_SECTION | |
1117 | beq 1f | |
1118 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1119 | BEGIN_FTR_SECTION_NESTED(69) | |
1120 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1121 | * transaction), go do TM stuff | |
1122 | */ | |
1123 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1124 | bne- 2f | |
1125 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1126 | #endif | |
1127 | b load_up_vsx | |
1128 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1129 | 2: /* User process was in a transaction */ | |
1130 | bl save_nvgprs | |
1131 | RECONCILE_IRQ_STATE(r10, r11) | |
1132 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1133 | bl vsx_unavailable_tm | |
1134 | b ret_from_except | |
1135 | #endif | |
1136 | 1: | |
1137 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1138 | #endif | |
1139 | bl save_nvgprs | |
1140 | RECONCILE_IRQ_STATE(r10, r11) | |
1141 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1142 | bl vsx_unavailable_exception | |
1143 | b ret_from_except | |
1144 | ||
da2bc464 | 1145 | |
a33532af NP |
1146 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) |
1147 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80, 0xf60) | |
1134713c NP |
1148 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1149 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1150 | ||
da2bc464 | 1151 | |
a33532af NP |
1152 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) |
1153 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0, 0xf80) | |
14b0072c NP |
1154 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1155 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1156 | ||
da2bc464 ME |
1157 | |
1158 | EXC_REAL_NONE(0xfa0, 0x1200) | |
e46b964c | 1159 | EXC_VIRT_NONE(0x4fa0, 0x5200) |
d0c0c9a1 | 1160 | |
0ebc4cda | 1161 | #ifdef CONFIG_CBE_RAS |
da2bc464 | 1162 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
ff1b3206 | 1163 | EXC_VIRT_NONE(0x5200, 0x5300) |
da2bc464 | 1164 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1165 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 ME |
1166 | #else /* CONFIG_CBE_RAS */ |
1167 | EXC_REAL_NONE(0x1200, 0x1300) | |
e0319829 | 1168 | EXC_VIRT_NONE(0x5200, 0x5300) |
da2bc464 | 1169 | #endif |
b01c8b54 | 1170 | |
ff1b3206 | 1171 | |
da2bc464 | 1172 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
4e96dbbf | 1173 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) |
da2bc464 | 1174 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1175 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1176 | ||
e0319829 NP |
1177 | EXC_REAL_NONE(0x1400, 0x1500) |
1178 | EXC_VIRT_NONE(0x5400, 0x5500) | |
da2bc464 ME |
1179 | |
1180 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) | |
b92a66a6 | 1181 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1182 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1183 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1184 | |
1185 | #ifdef CONFIG_PPC_DENORMALISATION | |
1186 | mfspr r10,SPRN_HSRR1 | |
1187 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
afcf0095 NP |
1188 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
1189 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
1190 | bne+ denorm_assist | |
1191 | #endif | |
1e9b4507 | 1192 | |
afcf0095 NP |
1193 | KVMTEST_PR(0x1500) |
1194 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
1195 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) | |
a74599a5 | 1196 | |
d7e89849 NP |
1197 | #ifdef CONFIG_PPC_DENORMALISATION |
1198 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) | |
1199 | b exc_real_0x1500_denorm_exception_hv | |
1200 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) | |
1201 | #else | |
1202 | EXC_VIRT_NONE(0x5500, 0x5600) | |
afcf0095 NP |
1203 | #endif |
1204 | ||
d7e89849 | 1205 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
b01c8b54 | 1206 | |
b92a66a6 | 1207 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1208 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1209 | BEGIN_FTR_SECTION |
1210 | /* | |
1211 | * To denormalise we need to move a copy of the register to itself. | |
1212 | * For POWER6 do that here for all FP regs. | |
1213 | */ | |
1214 | mfmsr r10 | |
1215 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1216 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1217 | mtmsrd r10 | |
1218 | sync | |
d7c67fb1 MN |
1219 | |
1220 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1221 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1222 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1223 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1224 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1225 | FMR32(0) | |
1226 | ||
b92a66a6 MN |
1227 | FTR_SECTION_ELSE |
1228 | /* | |
1229 | * To denormalise we need to move a copy of the register to itself. | |
1230 | * For POWER7 do that here for the first 32 VSX registers only. | |
1231 | */ | |
1232 | mfmsr r10 | |
1233 | oris r10,r10,MSR_VSX@h | |
1234 | mtmsrd r10 | |
1235 | sync | |
d7c67fb1 MN |
1236 | |
1237 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1238 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1239 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1240 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1241 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1242 | XVCPSGNDP32(0) | |
1243 | ||
b92a66a6 | 1244 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1245 | |
1246 | BEGIN_FTR_SECTION | |
1247 | b denorm_done | |
1248 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1249 | /* | |
1250 | * To denormalise we need to move a copy of the register to itself. | |
1251 | * For POWER8 we need to do that for all 64 VSX registers | |
1252 | */ | |
1253 | XVCPSGNDP32(32) | |
1254 | denorm_done: | |
b92a66a6 MN |
1255 | mtspr SPRN_HSRR0,r11 |
1256 | mtcrf 0x80,r9 | |
1257 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1258 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1259 | BEGIN_FTR_SECTION |
1260 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1261 | mtspr SPRN_CFAR,r10 | |
1262 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1263 | ld r10,PACA_EXGEN+EX_R10(r13) |
1264 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1265 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1266 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1267 | HRFID | |
1268 | b . | |
1269 | #endif | |
1270 | ||
d7e89849 NP |
1271 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
1272 | ||
1273 | ||
1274 | #ifdef CONFIG_CBE_RAS | |
1275 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) | |
69a79344 | 1276 | EXC_VIRT_NONE(0x5600, 0x5700) |
d7e89849 | 1277 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1278 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 NP |
1279 | #else /* CONFIG_CBE_RAS */ |
1280 | EXC_REAL_NONE(0x1600, 0x1700) | |
e0319829 | 1281 | EXC_VIRT_NONE(0x5600, 0x5700) |
d7e89849 NP |
1282 | #endif |
1283 | ||
69a79344 | 1284 | |
d7e89849 | 1285 | EXC_REAL(altivec_assist, 0x1700, 0x1800) |
b51c079e | 1286 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) |
d7e89849 | 1287 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1288 | #ifdef CONFIG_ALTIVEC |
1289 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1290 | #else | |
1291 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1292 | #endif | |
1293 | ||
d7e89849 NP |
1294 | |
1295 | #ifdef CONFIG_CBE_RAS | |
1296 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) | |
3965f8ab | 1297 | EXC_VIRT_NONE(0x5800, 0x5900) |
d7e89849 | 1298 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1299 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 NP |
1300 | #else /* CONFIG_CBE_RAS */ |
1301 | EXC_REAL_NONE(0x1800, 0x1900) | |
e0319829 | 1302 | EXC_VIRT_NONE(0x5800, 0x5900) |
d7e89849 NP |
1303 | #endif |
1304 | ||
1305 | ||
0ebc4cda | 1306 | /* |
fe9e1d54 IM |
1307 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1308 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1309 | * - If it was a doorbell we return immediately since doorbells are edge | |
1310 | * triggered and won't automatically refire. | |
0869b6fd MS |
1311 | * - If it was a HMI we return immediately since we handled it in realmode |
1312 | * and it won't refire. | |
fe9e1d54 IM |
1313 | * - else we hard disable and return. |
1314 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 1315 | */ |
7230c564 BH |
1316 | #define MASKED_INTERRUPT(_H) \ |
1317 | masked_##_H##interrupt: \ | |
1318 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1319 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1320 | or r11,r11,r10; \ | |
1321 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1322 | cmpwi r10,PACA_IRQ_DEC; \ |
1323 | bne 1f; \ | |
7230c564 BH |
1324 | lis r10,0x7fff; \ |
1325 | ori r10,r10,0xffff; \ | |
1326 | mtspr SPRN_DEC,r10; \ | |
1327 | b 2f; \ | |
fe9e1d54 | 1328 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
1329 | beq 2f; \ |
1330 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
1331 | beq 2f; \ |
1332 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
1333 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
1334 | rotldi r10,r10,16; \ | |
1335 | mtspr SPRN_##_H##SRR1,r10; \ | |
1336 | 2: mtcrf 0x80,r9; \ | |
1337 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
1338 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1339 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
1340 | GET_SCRATCH0(r13); \ | |
1341 | ##_H##rfid; \ | |
0ebc4cda | 1342 | b . |
57f26649 NP |
1343 | |
1344 | /* | |
1345 | * Real mode exceptions actually use this too, but alternate | |
1346 | * instruction code patches (which end up in the common .text area) | |
1347 | * cannot reach these if they are put there. | |
1348 | */ | |
1349 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1350 | MASKED_INTERRUPT() |
1351 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1352 | |
4f6c11db | 1353 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1354 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1355 | /* |
1356 | * Here all GPRs are unchanged from when the interrupt happened | |
1357 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1358 | */ | |
1359 | mfspr r13, SPRN_SRR0 | |
1360 | addi r13, r13, 4 | |
1361 | mtspr SPRN_SRR0, r13 | |
1362 | GET_SCRATCH0(r13) | |
1363 | rfid | |
1364 | b . | |
1365 | ||
da2bc464 | 1366 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1367 | /* |
1368 | * Here all GPRs are unchanged from when the interrupt happened | |
1369 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1370 | */ | |
1371 | mfspr r13, SPRN_HSRR0 | |
1372 | addi r13, r13, 4 | |
1373 | mtspr SPRN_HSRR0, r13 | |
1374 | GET_SCRATCH0(r13) | |
1375 | hrfid | |
1376 | b . | |
1377 | #endif | |
1378 | ||
0ebc4cda | 1379 | /* |
057b6d7e HB |
1380 | * Ensure that any handlers that get invoked from the exception prologs |
1381 | * above are below the first 64KB (0x10000) of the kernel image because | |
1382 | * the prologs assemble the addresses of these handlers using the | |
1383 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1384 | */ |
1385 | ||
1386 | /*** Common interrupt handlers ***/ | |
1387 | ||
0ebc4cda | 1388 | |
c1fb6816 MN |
1389 | /* |
1390 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1391 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1392 | * it. Addresses are the same as the original interrupt addresses, but | |
1393 | * offset by 0xc000000000004000. | |
1394 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1395 | * KVM: None of these traps are from the guest ; anything that escalated | |
1396 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1397 | */ | |
1398 | ||
1399 | /* | |
1400 | * This uses the standard macro, since the original 0x300 vector | |
1401 | * only has extra guff for STAB-based processors -- which never | |
1402 | * come here. | |
1403 | */ | |
da2bc464 | 1404 | |
57f26649 | 1405 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1406 | b __ppc64_runlatch_on |
fe1952fc | 1407 | |
57f26649 | 1408 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1409 | /* |
1410 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1411 | * handlers, so that they are copied to real address 0x100 when running | |
1412 | * a relocatable kernel. This ensures they can be reached from the short | |
1413 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1414 | * directly, without using LOAD_HANDLER(). | |
1415 | */ | |
1416 | .align 7 | |
1417 | .globl __end_interrupts | |
1418 | __end_interrupts: | |
57f26649 | 1419 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1420 | |
087aa036 | 1421 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1422 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1423 | andc r9,r9,r10 |
1424 | std r9,TI_LOCAL_FLAGS(r11) | |
1425 | ld r10,_LINK(r1) /* make idle task do the */ | |
1426 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1427 | blr | |
1428 | #endif | |
1429 | ||
57f26649 NP |
1430 | CLOSE_FIXED_SECTION(real_vectors); |
1431 | CLOSE_FIXED_SECTION(real_trampolines); | |
1432 | CLOSE_FIXED_SECTION(virt_vectors); | |
1433 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1434 | ||
1435 | USE_TEXT_SECTION() | |
1436 | ||
0ebc4cda BH |
1437 | /* |
1438 | * Hash table stuff | |
1439 | */ | |
f4329f2e | 1440 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1441 | do_hash_page: |
caca285e | 1442 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1443 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1444 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1445 | andis. r0,r4,DSISR_DABRMATCH@h |
1446 | bne- handle_dabr_fault | |
9778b696 | 1447 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1448 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1449 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1450 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1451 | |
1452 | /* | |
1453 | * r3 contains the faulting address | |
106713a1 | 1454 | * r4 msr |
0ebc4cda | 1455 | * r5 contains the trap number |
aefa5688 | 1456 | * r6 contains dsisr |
0ebc4cda | 1457 | * |
7230c564 | 1458 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1459 | */ |
106713a1 | 1460 | mr r4,r12 |
aefa5688 | 1461 | ld r6,_DSISR(r1) |
106713a1 AK |
1462 | bl __hash_page /* build HPTE if possible */ |
1463 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1464 | |
7230c564 | 1465 | /* Success */ |
0ebc4cda | 1466 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1467 | |
7230c564 BH |
1468 | /* Error */ |
1469 | blt- 13f | |
caca285e | 1470 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1471 | |
0ebc4cda BH |
1472 | /* Here we have a page fault that hash_page can't handle. */ |
1473 | handle_page_fault: | |
0ebc4cda BH |
1474 | 11: ld r4,_DAR(r1) |
1475 | ld r5,_DSISR(r1) | |
1476 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1477 | bl do_page_fault |
0ebc4cda | 1478 | cmpdi r3,0 |
a546498f | 1479 | beq+ 12f |
b1576fec | 1480 | bl save_nvgprs |
0ebc4cda BH |
1481 | mr r5,r3 |
1482 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1483 | lwz r4,_DAR(r1) | |
b1576fec AB |
1484 | bl bad_page_fault |
1485 | b ret_from_except | |
0ebc4cda | 1486 | |
a546498f BH |
1487 | /* We have a data breakpoint exception - handle it */ |
1488 | handle_dabr_fault: | |
b1576fec | 1489 | bl save_nvgprs |
a546498f BH |
1490 | ld r4,_DAR(r1) |
1491 | ld r5,_DSISR(r1) | |
1492 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1493 | bl do_break |
1494 | 12: b ret_from_except_lite | |
a546498f | 1495 | |
0ebc4cda | 1496 | |
caca285e | 1497 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1498 | /* We have a page fault that hash_page could handle but HV refused |
1499 | * the PTE insertion | |
1500 | */ | |
b1576fec | 1501 | 13: bl save_nvgprs |
0ebc4cda BH |
1502 | mr r5,r3 |
1503 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1504 | ld r4,_DAR(r1) | |
b1576fec AB |
1505 | bl low_hash_fault |
1506 | b ret_from_except | |
caca285e | 1507 | #endif |
0ebc4cda | 1508 | |
9c1e1052 PM |
1509 | /* |
1510 | * We come here as a result of a DSI at a point where we don't want | |
1511 | * to call hash_page, such as when we are accessing memory (possibly | |
1512 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1513 | * were soft-disabled. We want to invoke the exception handler for | |
1514 | * the access, or panic if there isn't a handler. | |
1515 | */ | |
b1576fec | 1516 | 77: bl save_nvgprs |
9c1e1052 PM |
1517 | mr r4,r3 |
1518 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1519 | li r5,SIGSEGV | |
b1576fec AB |
1520 | bl bad_page_fault |
1521 | b ret_from_except | |
4e2bf01b ME |
1522 | |
1523 | /* | |
1524 | * Here we have detected that the kernel stack pointer is bad. | |
1525 | * R9 contains the saved CR, r13 points to the paca, | |
1526 | * r10 contains the (bad) kernel stack pointer, | |
1527 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1528 | * We switch to using an emergency stack, save the registers there, | |
1529 | * and call kernel_bad_stack(), which panics. | |
1530 | */ | |
1531 | bad_stack: | |
1532 | ld r1,PACAEMERGSP(r13) | |
1533 | subi r1,r1,64+INT_FRAME_SIZE | |
1534 | std r9,_CCR(r1) | |
1535 | std r10,GPR1(r1) | |
1536 | std r11,_NIP(r1) | |
1537 | std r12,_MSR(r1) | |
1538 | mfspr r11,SPRN_DAR | |
1539 | mfspr r12,SPRN_DSISR | |
1540 | std r11,_DAR(r1) | |
1541 | std r12,_DSISR(r1) | |
1542 | mflr r10 | |
1543 | mfctr r11 | |
1544 | mfxer r12 | |
1545 | std r10,_LINK(r1) | |
1546 | std r11,_CTR(r1) | |
1547 | std r12,_XER(r1) | |
1548 | SAVE_GPR(0,r1) | |
1549 | SAVE_GPR(2,r1) | |
1550 | ld r10,EX_R3(r3) | |
1551 | std r10,GPR3(r1) | |
1552 | SAVE_GPR(4,r1) | |
1553 | SAVE_4GPRS(5,r1) | |
1554 | ld r9,EX_R9(r3) | |
1555 | ld r10,EX_R10(r3) | |
1556 | SAVE_2GPRS(9,r1) | |
1557 | ld r9,EX_R11(r3) | |
1558 | ld r10,EX_R12(r3) | |
1559 | ld r11,EX_R13(r3) | |
1560 | std r9,GPR11(r1) | |
1561 | std r10,GPR12(r1) | |
1562 | std r11,GPR13(r1) | |
1563 | BEGIN_FTR_SECTION | |
1564 | ld r10,EX_CFAR(r3) | |
1565 | std r10,ORIG_GPR3(r1) | |
1566 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1567 | SAVE_8GPRS(14,r1) | |
1568 | SAVE_10GPRS(22,r1) | |
1569 | lhz r12,PACA_TRAP_SAVE(r13) | |
1570 | std r12,_TRAP(r1) | |
1571 | addi r11,r1,INT_FRAME_SIZE | |
1572 | std r11,0(r1) | |
1573 | li r12,0 | |
1574 | std r12,0(r11) | |
1575 | ld r2,PACATOC(r13) | |
1576 | ld r11,exception_marker@toc(r2) | |
1577 | std r12,RESULT(r1) | |
1578 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1579 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1580 | bl kernel_bad_stack | |
1581 | b 1b | |
0f0c6ca1 NP |
1582 | |
1583 | /* | |
1584 | * Called from arch_local_irq_enable when an interrupt needs | |
1585 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1586 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1587 | * stackframe like if a real interrupt had happened. | |
1588 | * | |
1589 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1590 | * in the generated frame has EE set to 1 or the exception | |
1591 | * handler will not properly re-enable them. | |
1592 | */ | |
1593 | _GLOBAL(__replay_interrupt) | |
1594 | /* We are going to jump to the exception common code which | |
1595 | * will retrieve various register values from the PACA which | |
1596 | * we don't give a damn about, so we don't bother storing them. | |
1597 | */ | |
1598 | mfmsr r12 | |
1599 | mflr r11 | |
1600 | mfcr r9 | |
1601 | ori r12,r12,MSR_EE | |
1602 | cmpwi r3,0x900 | |
1603 | beq decrementer_common | |
1604 | cmpwi r3,0x500 | |
1605 | beq hardware_interrupt_common | |
1606 | BEGIN_FTR_SECTION | |
1607 | cmpwi r3,0xe80 | |
1608 | beq h_doorbell_common | |
1609 | cmpwi r3,0xea0 | |
1610 | beq h_virt_irq_common | |
1611 | cmpwi r3,0xe60 | |
1612 | beq hmi_exception_common | |
1613 | FTR_SECTION_ELSE | |
1614 | cmpwi r3,0xa00 | |
1615 | beq doorbell_super_common | |
1616 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1617 | blr |