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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
e495606d | 20 | |
edf88417 | 21 | #include <linux/kvm_host.h> |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/mm.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
c7addb90 | 27 | #include <linux/moduleparam.h> |
5fdbf976 | 28 | #include "kvm_cache_regs.h" |
35920a35 | 29 | #include "x86.h" |
e495606d | 30 | |
6aa8b732 | 31 | #include <asm/io.h> |
3b3be0d1 | 32 | #include <asm/desc.h> |
13673a90 | 33 | #include <asm/vmx.h> |
6210e37b | 34 | #include <asm/virtext.h> |
6aa8b732 | 35 | |
4ecac3fd AK |
36 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
37 | ||
6aa8b732 AK |
38 | MODULE_AUTHOR("Qumranet"); |
39 | MODULE_LICENSE("GPL"); | |
40 | ||
c7addb90 AK |
41 | static int bypass_guest_pf = 1; |
42 | module_param(bypass_guest_pf, bool, 0); | |
43 | ||
2384d2b3 SY |
44 | static int enable_vpid = 1; |
45 | module_param(enable_vpid, bool, 0); | |
46 | ||
4c9fc8ef AK |
47 | static int flexpriority_enabled = 1; |
48 | module_param(flexpriority_enabled, bool, 0); | |
49 | ||
1439442c | 50 | static int enable_ept = 1; |
d56f546d SY |
51 | module_param(enable_ept, bool, 0); |
52 | ||
04fa4d32 MG |
53 | static int emulate_invalid_guest_state = 0; |
54 | module_param(emulate_invalid_guest_state, bool, 0); | |
55 | ||
a2fa3e9f GH |
56 | struct vmcs { |
57 | u32 revision_id; | |
58 | u32 abort; | |
59 | char data[0]; | |
60 | }; | |
61 | ||
62 | struct vcpu_vmx { | |
fb3f0f51 | 63 | struct kvm_vcpu vcpu; |
543e4243 | 64 | struct list_head local_vcpus_link; |
313dbd49 | 65 | unsigned long host_rsp; |
a2fa3e9f | 66 | int launched; |
29bd8a78 | 67 | u8 fail; |
1155f76a | 68 | u32 idt_vectoring_info; |
a2fa3e9f GH |
69 | struct kvm_msr_entry *guest_msrs; |
70 | struct kvm_msr_entry *host_msrs; | |
71 | int nmsrs; | |
72 | int save_nmsrs; | |
73 | int msr_offset_efer; | |
74 | #ifdef CONFIG_X86_64 | |
75 | int msr_offset_kernel_gs_base; | |
76 | #endif | |
77 | struct vmcs *vmcs; | |
78 | struct { | |
79 | int loaded; | |
80 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
81 | int gs_ldt_reload_needed; |
82 | int fs_reload_needed; | |
51c6cf66 | 83 | int guest_efer_loaded; |
d77c26fc | 84 | } host_state; |
9c8cba37 AK |
85 | struct { |
86 | struct { | |
87 | bool pending; | |
88 | u8 vector; | |
89 | unsigned rip; | |
90 | } irq; | |
91 | } rmode; | |
2384d2b3 | 92 | int vpid; |
04fa4d32 | 93 | bool emulation_required; |
3b86cd99 JK |
94 | |
95 | /* Support for vnmi-less CPUs */ | |
96 | int soft_vnmi_blocked; | |
97 | ktime_t entry_time; | |
98 | s64 vnmi_blocked_time; | |
a2fa3e9f GH |
99 | }; |
100 | ||
101 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
102 | { | |
fb3f0f51 | 103 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
104 | } |
105 | ||
b7ebfb05 | 106 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 107 | static u64 construct_eptp(unsigned long root_hpa); |
75880a01 | 108 | |
6aa8b732 AK |
109 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
110 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 111 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
6aa8b732 | 112 | |
fdef3ad1 HQ |
113 | static struct page *vmx_io_bitmap_a; |
114 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 115 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 116 | |
2384d2b3 SY |
117 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
118 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
119 | ||
1c3d14fe | 120 | static struct vmcs_config { |
6aa8b732 AK |
121 | int size; |
122 | int order; | |
123 | u32 revision_id; | |
1c3d14fe YS |
124 | u32 pin_based_exec_ctrl; |
125 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 126 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
127 | u32 vmexit_ctrl; |
128 | u32 vmentry_ctrl; | |
129 | } vmcs_config; | |
6aa8b732 | 130 | |
efff9e53 | 131 | static struct vmx_capability { |
d56f546d SY |
132 | u32 ept; |
133 | u32 vpid; | |
134 | } vmx_capability; | |
135 | ||
6aa8b732 AK |
136 | #define VMX_SEGMENT_FIELD(seg) \ |
137 | [VCPU_SREG_##seg] = { \ | |
138 | .selector = GUEST_##seg##_SELECTOR, \ | |
139 | .base = GUEST_##seg##_BASE, \ | |
140 | .limit = GUEST_##seg##_LIMIT, \ | |
141 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
142 | } | |
143 | ||
144 | static struct kvm_vmx_segment_field { | |
145 | unsigned selector; | |
146 | unsigned base; | |
147 | unsigned limit; | |
148 | unsigned ar_bytes; | |
149 | } kvm_vmx_segment_fields[] = { | |
150 | VMX_SEGMENT_FIELD(CS), | |
151 | VMX_SEGMENT_FIELD(DS), | |
152 | VMX_SEGMENT_FIELD(ES), | |
153 | VMX_SEGMENT_FIELD(FS), | |
154 | VMX_SEGMENT_FIELD(GS), | |
155 | VMX_SEGMENT_FIELD(SS), | |
156 | VMX_SEGMENT_FIELD(TR), | |
157 | VMX_SEGMENT_FIELD(LDTR), | |
158 | }; | |
159 | ||
4d56c8a7 AK |
160 | /* |
161 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
162 | * away by decrementing the array size. | |
163 | */ | |
6aa8b732 | 164 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 165 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
166 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
167 | #endif | |
168 | MSR_EFER, MSR_K6_STAR, | |
169 | }; | |
9d8f549d | 170 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 171 | |
a2fa3e9f GH |
172 | static void load_msrs(struct kvm_msr_entry *e, int n) |
173 | { | |
174 | int i; | |
175 | ||
176 | for (i = 0; i < n; ++i) | |
177 | wrmsrl(e[i].index, e[i].data); | |
178 | } | |
179 | ||
180 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
181 | { | |
182 | int i; | |
183 | ||
184 | for (i = 0; i < n; ++i) | |
185 | rdmsrl(e[i].index, e[i].data); | |
186 | } | |
187 | ||
6aa8b732 AK |
188 | static inline int is_page_fault(u32 intr_info) |
189 | { | |
190 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
191 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 192 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
193 | } |
194 | ||
2ab455cc AL |
195 | static inline int is_no_device(u32 intr_info) |
196 | { | |
197 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
198 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 199 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
200 | } |
201 | ||
7aa81cc0 AL |
202 | static inline int is_invalid_opcode(u32 intr_info) |
203 | { | |
204 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
205 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 206 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
207 | } |
208 | ||
6aa8b732 AK |
209 | static inline int is_external_interrupt(u32 intr_info) |
210 | { | |
211 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
212 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
213 | } | |
214 | ||
25c5f225 SY |
215 | static inline int cpu_has_vmx_msr_bitmap(void) |
216 | { | |
217 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
218 | } | |
219 | ||
6e5d865c YS |
220 | static inline int cpu_has_vmx_tpr_shadow(void) |
221 | { | |
222 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
223 | } | |
224 | ||
225 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
226 | { | |
227 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
228 | } | |
229 | ||
f78e0e2e SY |
230 | static inline int cpu_has_secondary_exec_ctrls(void) |
231 | { | |
232 | return (vmcs_config.cpu_based_exec_ctrl & | |
233 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
234 | } | |
235 | ||
774ead3a | 236 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 237 | { |
4c9fc8ef AK |
238 | return flexpriority_enabled |
239 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
240 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
241 | } |
242 | ||
d56f546d SY |
243 | static inline int cpu_has_vmx_invept_individual_addr(void) |
244 | { | |
245 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
246 | } | |
247 | ||
248 | static inline int cpu_has_vmx_invept_context(void) | |
249 | { | |
250 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
251 | } | |
252 | ||
253 | static inline int cpu_has_vmx_invept_global(void) | |
254 | { | |
255 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
256 | } | |
257 | ||
258 | static inline int cpu_has_vmx_ept(void) | |
259 | { | |
260 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
261 | SECONDARY_EXEC_ENABLE_EPT); | |
262 | } | |
263 | ||
264 | static inline int vm_need_ept(void) | |
265 | { | |
266 | return (cpu_has_vmx_ept() && enable_ept); | |
267 | } | |
268 | ||
f78e0e2e SY |
269 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
270 | { | |
271 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
272 | (irqchip_in_kernel(kvm))); | |
273 | } | |
274 | ||
2384d2b3 SY |
275 | static inline int cpu_has_vmx_vpid(void) |
276 | { | |
277 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
278 | SECONDARY_EXEC_ENABLE_VPID); | |
279 | } | |
280 | ||
f08864b4 SY |
281 | static inline int cpu_has_virtual_nmis(void) |
282 | { | |
283 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
284 | } | |
285 | ||
8b9cf98c | 286 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
287 | { |
288 | int i; | |
289 | ||
a2fa3e9f GH |
290 | for (i = 0; i < vmx->nmsrs; ++i) |
291 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
292 | return i; |
293 | return -1; | |
294 | } | |
295 | ||
2384d2b3 SY |
296 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
297 | { | |
298 | struct { | |
299 | u64 vpid : 16; | |
300 | u64 rsvd : 48; | |
301 | u64 gva; | |
302 | } operand = { vpid, 0, gva }; | |
303 | ||
4ecac3fd | 304 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
305 | /* CF==1 or ZF==1 --> rc = -1 */ |
306 | "; ja 1f ; ud2 ; 1:" | |
307 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
308 | } | |
309 | ||
1439442c SY |
310 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
311 | { | |
312 | struct { | |
313 | u64 eptp, gpa; | |
314 | } operand = {eptp, gpa}; | |
315 | ||
4ecac3fd | 316 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
317 | /* CF==1 or ZF==1 --> rc = -1 */ |
318 | "; ja 1f ; ud2 ; 1:\n" | |
319 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
320 | } | |
321 | ||
8b9cf98c | 322 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
323 | { |
324 | int i; | |
325 | ||
8b9cf98c | 326 | i = __find_msr_index(vmx, msr); |
a75beee6 | 327 | if (i >= 0) |
a2fa3e9f | 328 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 329 | return NULL; |
7725f0ba AK |
330 | } |
331 | ||
6aa8b732 AK |
332 | static void vmcs_clear(struct vmcs *vmcs) |
333 | { | |
334 | u64 phys_addr = __pa(vmcs); | |
335 | u8 error; | |
336 | ||
4ecac3fd | 337 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
338 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
339 | : "cc", "memory"); | |
340 | if (error) | |
341 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
342 | vmcs, phys_addr); | |
343 | } | |
344 | ||
345 | static void __vcpu_clear(void *arg) | |
346 | { | |
8b9cf98c | 347 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 348 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 349 | |
8b9cf98c | 350 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
351 | vmcs_clear(vmx->vmcs); |
352 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 353 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 354 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
355 | list_del(&vmx->local_vcpus_link); |
356 | vmx->vcpu.cpu = -1; | |
357 | vmx->launched = 0; | |
6aa8b732 AK |
358 | } |
359 | ||
8b9cf98c | 360 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 361 | { |
eae5ecb5 AK |
362 | if (vmx->vcpu.cpu == -1) |
363 | return; | |
8691e5a8 | 364 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
365 | } |
366 | ||
2384d2b3 SY |
367 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
368 | { | |
369 | if (vmx->vpid == 0) | |
370 | return; | |
371 | ||
372 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
373 | } | |
374 | ||
1439442c SY |
375 | static inline void ept_sync_global(void) |
376 | { | |
377 | if (cpu_has_vmx_invept_global()) | |
378 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
379 | } | |
380 | ||
381 | static inline void ept_sync_context(u64 eptp) | |
382 | { | |
383 | if (vm_need_ept()) { | |
384 | if (cpu_has_vmx_invept_context()) | |
385 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
386 | else | |
387 | ept_sync_global(); | |
388 | } | |
389 | } | |
390 | ||
391 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
392 | { | |
393 | if (vm_need_ept()) { | |
394 | if (cpu_has_vmx_invept_individual_addr()) | |
395 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
396 | eptp, gpa); | |
397 | else | |
398 | ept_sync_context(eptp); | |
399 | } | |
400 | } | |
401 | ||
6aa8b732 AK |
402 | static unsigned long vmcs_readl(unsigned long field) |
403 | { | |
404 | unsigned long value; | |
405 | ||
4ecac3fd | 406 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
407 | : "=a"(value) : "d"(field) : "cc"); |
408 | return value; | |
409 | } | |
410 | ||
411 | static u16 vmcs_read16(unsigned long field) | |
412 | { | |
413 | return vmcs_readl(field); | |
414 | } | |
415 | ||
416 | static u32 vmcs_read32(unsigned long field) | |
417 | { | |
418 | return vmcs_readl(field); | |
419 | } | |
420 | ||
421 | static u64 vmcs_read64(unsigned long field) | |
422 | { | |
05b3e0c2 | 423 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
424 | return vmcs_readl(field); |
425 | #else | |
426 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
427 | #endif | |
428 | } | |
429 | ||
e52de1b8 AK |
430 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
431 | { | |
432 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
433 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
434 | dump_stack(); | |
435 | } | |
436 | ||
6aa8b732 AK |
437 | static void vmcs_writel(unsigned long field, unsigned long value) |
438 | { | |
439 | u8 error; | |
440 | ||
4ecac3fd | 441 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 442 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
443 | if (unlikely(error)) |
444 | vmwrite_error(field, value); | |
6aa8b732 AK |
445 | } |
446 | ||
447 | static void vmcs_write16(unsigned long field, u16 value) | |
448 | { | |
449 | vmcs_writel(field, value); | |
450 | } | |
451 | ||
452 | static void vmcs_write32(unsigned long field, u32 value) | |
453 | { | |
454 | vmcs_writel(field, value); | |
455 | } | |
456 | ||
457 | static void vmcs_write64(unsigned long field, u64 value) | |
458 | { | |
6aa8b732 | 459 | vmcs_writel(field, value); |
7682f2d0 | 460 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
461 | asm volatile (""); |
462 | vmcs_writel(field+1, value >> 32); | |
463 | #endif | |
464 | } | |
465 | ||
2ab455cc AL |
466 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
467 | { | |
468 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
469 | } | |
470 | ||
471 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
472 | { | |
473 | vmcs_writel(field, vmcs_readl(field) | mask); | |
474 | } | |
475 | ||
abd3f2d6 AK |
476 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
477 | { | |
478 | u32 eb; | |
479 | ||
7aa81cc0 | 480 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
481 | if (!vcpu->fpu_active) |
482 | eb |= 1u << NM_VECTOR; | |
d0bfb940 JK |
483 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
484 | if (vcpu->guest_debug & | |
485 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
486 | eb |= 1u << DB_VECTOR; | |
487 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
488 | eb |= 1u << BP_VECTOR; | |
489 | } | |
ad312c7c | 490 | if (vcpu->arch.rmode.active) |
abd3f2d6 | 491 | eb = ~0; |
1439442c SY |
492 | if (vm_need_ept()) |
493 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | |
abd3f2d6 AK |
494 | vmcs_write32(EXCEPTION_BITMAP, eb); |
495 | } | |
496 | ||
33ed6329 AK |
497 | static void reload_tss(void) |
498 | { | |
33ed6329 AK |
499 | /* |
500 | * VT restores TR but not its size. Useless. | |
501 | */ | |
502 | struct descriptor_table gdt; | |
a5f61300 | 503 | struct desc_struct *descs; |
33ed6329 | 504 | |
d6e88aec | 505 | kvm_get_gdt(&gdt); |
33ed6329 AK |
506 | descs = (void *)gdt.base; |
507 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
508 | load_TR_desc(); | |
33ed6329 AK |
509 | } |
510 | ||
8b9cf98c | 511 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 512 | { |
a2fa3e9f | 513 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
514 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
515 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
516 | u64 ignore_bits; | |
517 | ||
518 | if (efer_offset < 0) | |
519 | return; | |
520 | /* | |
521 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
522 | * outside long mode | |
523 | */ | |
524 | ignore_bits = EFER_NX | EFER_SCE; | |
525 | #ifdef CONFIG_X86_64 | |
526 | ignore_bits |= EFER_LMA | EFER_LME; | |
527 | /* SCE is meaningful only in long mode on Intel */ | |
528 | if (guest_efer & EFER_LMA) | |
529 | ignore_bits &= ~(u64)EFER_SCE; | |
530 | #endif | |
531 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
532 | return; | |
2cc51560 | 533 | |
51c6cf66 AK |
534 | vmx->host_state.guest_efer_loaded = 1; |
535 | guest_efer &= ~ignore_bits; | |
536 | guest_efer |= host_efer & ignore_bits; | |
537 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 538 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
539 | } |
540 | ||
51c6cf66 AK |
541 | static void reload_host_efer(struct vcpu_vmx *vmx) |
542 | { | |
543 | if (vmx->host_state.guest_efer_loaded) { | |
544 | vmx->host_state.guest_efer_loaded = 0; | |
545 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
546 | } | |
547 | } | |
548 | ||
04d2cc77 | 549 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 550 | { |
04d2cc77 AK |
551 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
552 | ||
a2fa3e9f | 553 | if (vmx->host_state.loaded) |
33ed6329 AK |
554 | return; |
555 | ||
a2fa3e9f | 556 | vmx->host_state.loaded = 1; |
33ed6329 AK |
557 | /* |
558 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
559 | * allow segment selectors with cpl > 0 or ti == 1. | |
560 | */ | |
d6e88aec | 561 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 562 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
d6e88aec | 563 | vmx->host_state.fs_sel = kvm_read_fs(); |
152d3f2f | 564 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 565 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
566 | vmx->host_state.fs_reload_needed = 0; |
567 | } else { | |
33ed6329 | 568 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 569 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 570 | } |
d6e88aec | 571 | vmx->host_state.gs_sel = kvm_read_gs(); |
a2fa3e9f GH |
572 | if (!(vmx->host_state.gs_sel & 7)) |
573 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
574 | else { |
575 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 576 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
577 | } |
578 | ||
579 | #ifdef CONFIG_X86_64 | |
580 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
581 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
582 | #else | |
a2fa3e9f GH |
583 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
584 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 585 | #endif |
707c0874 AK |
586 | |
587 | #ifdef CONFIG_X86_64 | |
d77c26fc | 588 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
589 | save_msrs(vmx->host_msrs + |
590 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 591 | |
707c0874 | 592 | #endif |
a2fa3e9f | 593 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 594 | load_transition_efer(vmx); |
33ed6329 AK |
595 | } |
596 | ||
a9b21b62 | 597 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 598 | { |
15ad7146 | 599 | unsigned long flags; |
33ed6329 | 600 | |
a2fa3e9f | 601 | if (!vmx->host_state.loaded) |
33ed6329 AK |
602 | return; |
603 | ||
e1beb1d3 | 604 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 605 | vmx->host_state.loaded = 0; |
152d3f2f | 606 | if (vmx->host_state.fs_reload_needed) |
d6e88aec | 607 | kvm_load_fs(vmx->host_state.fs_sel); |
152d3f2f | 608 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 609 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 AK |
610 | /* |
611 | * If we have to reload gs, we must take care to | |
612 | * preserve our gs base. | |
613 | */ | |
15ad7146 | 614 | local_irq_save(flags); |
d6e88aec | 615 | kvm_load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
616 | #ifdef CONFIG_X86_64 |
617 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
618 | #endif | |
15ad7146 | 619 | local_irq_restore(flags); |
33ed6329 | 620 | } |
152d3f2f | 621 | reload_tss(); |
a2fa3e9f GH |
622 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
623 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 624 | reload_host_efer(vmx); |
33ed6329 AK |
625 | } |
626 | ||
a9b21b62 AK |
627 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
628 | { | |
629 | preempt_disable(); | |
630 | __vmx_load_host_state(vmx); | |
631 | preempt_enable(); | |
632 | } | |
633 | ||
6aa8b732 AK |
634 | /* |
635 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
636 | * vcpu mutex is already taken. | |
637 | */ | |
15ad7146 | 638 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 639 | { |
a2fa3e9f GH |
640 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
641 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 642 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 643 | |
a3d7f85f | 644 | if (vcpu->cpu != cpu) { |
8b9cf98c | 645 | vcpu_clear(vmx); |
2f599714 | 646 | kvm_migrate_timers(vcpu); |
2384d2b3 | 647 | vpid_sync_vcpu_all(vmx); |
543e4243 AK |
648 | local_irq_disable(); |
649 | list_add(&vmx->local_vcpus_link, | |
650 | &per_cpu(vcpus_on_cpu, cpu)); | |
651 | local_irq_enable(); | |
a3d7f85f | 652 | } |
6aa8b732 | 653 | |
a2fa3e9f | 654 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
655 | u8 error; |
656 | ||
a2fa3e9f | 657 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
4ecac3fd | 658 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
6aa8b732 AK |
659 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
660 | : "cc"); | |
661 | if (error) | |
662 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 663 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
664 | } |
665 | ||
666 | if (vcpu->cpu != cpu) { | |
667 | struct descriptor_table dt; | |
668 | unsigned long sysenter_esp; | |
669 | ||
670 | vcpu->cpu = cpu; | |
671 | /* | |
672 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
673 | * processors. | |
674 | */ | |
d6e88aec AK |
675 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
676 | kvm_get_gdt(&dt); | |
6aa8b732 AK |
677 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ |
678 | ||
679 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
680 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
681 | |
682 | /* | |
683 | * Make sure the time stamp counter is monotonous. | |
684 | */ | |
685 | rdtscll(tsc_this); | |
019960ae AK |
686 | if (tsc_this < vcpu->arch.host_tsc) { |
687 | delta = vcpu->arch.host_tsc - tsc_this; | |
688 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
689 | vmcs_write64(TSC_OFFSET, new_offset); | |
690 | } | |
6aa8b732 | 691 | } |
6aa8b732 AK |
692 | } |
693 | ||
694 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
695 | { | |
a9b21b62 | 696 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
697 | } |
698 | ||
5fd86fcf AK |
699 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
700 | { | |
701 | if (vcpu->fpu_active) | |
702 | return; | |
703 | vcpu->fpu_active = 1; | |
707d92fa | 704 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 705 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 706 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
707 | update_exception_bitmap(vcpu); |
708 | } | |
709 | ||
710 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
711 | { | |
712 | if (!vcpu->fpu_active) | |
713 | return; | |
714 | vcpu->fpu_active = 0; | |
707d92fa | 715 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
716 | update_exception_bitmap(vcpu); |
717 | } | |
718 | ||
6aa8b732 AK |
719 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
720 | { | |
721 | return vmcs_readl(GUEST_RFLAGS); | |
722 | } | |
723 | ||
724 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
725 | { | |
ad312c7c | 726 | if (vcpu->arch.rmode.active) |
053de044 | 727 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
728 | vmcs_writel(GUEST_RFLAGS, rflags); |
729 | } | |
730 | ||
731 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
732 | { | |
733 | unsigned long rip; | |
734 | u32 interruptibility; | |
735 | ||
5fdbf976 | 736 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 737 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 738 | kvm_rip_write(vcpu, rip); |
6aa8b732 AK |
739 | |
740 | /* | |
741 | * We emulated an instruction, so temporary interrupt blocking | |
742 | * should be removed, if set. | |
743 | */ | |
744 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
745 | if (interruptibility & 3) | |
746 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
747 | interruptibility & ~3); | |
ad312c7c | 748 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
749 | } |
750 | ||
298101da AK |
751 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
752 | bool has_error_code, u32 error_code) | |
753 | { | |
77ab6db0 | 754 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 755 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 756 | |
8ab2d2e2 | 757 | if (has_error_code) { |
77ab6db0 | 758 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
759 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
760 | } | |
77ab6db0 JK |
761 | |
762 | if (vcpu->arch.rmode.active) { | |
763 | vmx->rmode.irq.pending = true; | |
764 | vmx->rmode.irq.vector = nr; | |
765 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
8ab2d2e2 | 766 | if (nr == BP_VECTOR || nr == OF_VECTOR) |
77ab6db0 | 767 | vmx->rmode.irq.rip++; |
8ab2d2e2 JK |
768 | intr_info |= INTR_TYPE_SOFT_INTR; |
769 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
77ab6db0 JK |
770 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); |
771 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
772 | return; | |
773 | } | |
774 | ||
8ab2d2e2 JK |
775 | if (nr == BP_VECTOR || nr == OF_VECTOR) { |
776 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
777 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
778 | } else | |
779 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
780 | ||
781 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
782 | } |
783 | ||
784 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
785 | { | |
35920a35 | 786 | return false; |
298101da AK |
787 | } |
788 | ||
a75beee6 ED |
789 | /* |
790 | * Swap MSR entry in host/guest MSR entry array. | |
791 | */ | |
54e11fa1 | 792 | #ifdef CONFIG_X86_64 |
8b9cf98c | 793 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 794 | { |
a2fa3e9f GH |
795 | struct kvm_msr_entry tmp; |
796 | ||
797 | tmp = vmx->guest_msrs[to]; | |
798 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
799 | vmx->guest_msrs[from] = tmp; | |
800 | tmp = vmx->host_msrs[to]; | |
801 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
802 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 803 | } |
54e11fa1 | 804 | #endif |
a75beee6 | 805 | |
e38aea3e AK |
806 | /* |
807 | * Set up the vmcs to automatically save and restore system | |
808 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
809 | * mode, as fiddling with msrs is very expensive. | |
810 | */ | |
8b9cf98c | 811 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 812 | { |
2cc51560 | 813 | int save_nmsrs; |
e38aea3e | 814 | |
33f9c505 | 815 | vmx_load_host_state(vmx); |
a75beee6 ED |
816 | save_nmsrs = 0; |
817 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 818 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
819 | int index; |
820 | ||
8b9cf98c | 821 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 822 | if (index >= 0) |
8b9cf98c RR |
823 | move_msr_up(vmx, index, save_nmsrs++); |
824 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 825 | if (index >= 0) |
8b9cf98c RR |
826 | move_msr_up(vmx, index, save_nmsrs++); |
827 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 828 | if (index >= 0) |
8b9cf98c RR |
829 | move_msr_up(vmx, index, save_nmsrs++); |
830 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 831 | if (index >= 0) |
8b9cf98c | 832 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
833 | /* |
834 | * MSR_K6_STAR is only needed on long mode guests, and only | |
835 | * if efer.sce is enabled. | |
836 | */ | |
8b9cf98c | 837 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 838 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 839 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
840 | } |
841 | #endif | |
a2fa3e9f | 842 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 843 | |
4d56c8a7 | 844 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 845 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 846 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 847 | #endif |
8b9cf98c | 848 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
849 | } |
850 | ||
6aa8b732 AK |
851 | /* |
852 | * reads and returns guest's timestamp counter "register" | |
853 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
854 | */ | |
855 | static u64 guest_read_tsc(void) | |
856 | { | |
857 | u64 host_tsc, tsc_offset; | |
858 | ||
859 | rdtscll(host_tsc); | |
860 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
861 | return host_tsc + tsc_offset; | |
862 | } | |
863 | ||
864 | /* | |
865 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
866 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
867 | */ | |
53f658b3 | 868 | static void guest_write_tsc(u64 guest_tsc, u64 host_tsc) |
6aa8b732 | 869 | { |
6aa8b732 AK |
870 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); |
871 | } | |
872 | ||
6aa8b732 AK |
873 | /* |
874 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
875 | * Returns 0 on success, non-0 otherwise. | |
876 | * Assumes vcpu_load() was already called. | |
877 | */ | |
878 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
879 | { | |
880 | u64 data; | |
a2fa3e9f | 881 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
882 | |
883 | if (!pdata) { | |
884 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
885 | return -EINVAL; | |
886 | } | |
887 | ||
888 | switch (msr_index) { | |
05b3e0c2 | 889 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
890 | case MSR_FS_BASE: |
891 | data = vmcs_readl(GUEST_FS_BASE); | |
892 | break; | |
893 | case MSR_GS_BASE: | |
894 | data = vmcs_readl(GUEST_GS_BASE); | |
895 | break; | |
896 | case MSR_EFER: | |
3bab1f5d | 897 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
898 | #endif |
899 | case MSR_IA32_TIME_STAMP_COUNTER: | |
900 | data = guest_read_tsc(); | |
901 | break; | |
902 | case MSR_IA32_SYSENTER_CS: | |
903 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
904 | break; | |
905 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 906 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
907 | break; |
908 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 909 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 910 | break; |
6aa8b732 | 911 | default: |
516a1a7e | 912 | vmx_load_host_state(to_vmx(vcpu)); |
8b9cf98c | 913 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
914 | if (msr) { |
915 | data = msr->data; | |
916 | break; | |
6aa8b732 | 917 | } |
3bab1f5d | 918 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
919 | } |
920 | ||
921 | *pdata = data; | |
922 | return 0; | |
923 | } | |
924 | ||
925 | /* | |
926 | * Writes msr value into into the appropriate "register". | |
927 | * Returns 0 on success, non-0 otherwise. | |
928 | * Assumes vcpu_load() was already called. | |
929 | */ | |
930 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
931 | { | |
a2fa3e9f GH |
932 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
933 | struct kvm_msr_entry *msr; | |
53f658b3 | 934 | u64 host_tsc; |
2cc51560 ED |
935 | int ret = 0; |
936 | ||
6aa8b732 | 937 | switch (msr_index) { |
05b3e0c2 | 938 | #ifdef CONFIG_X86_64 |
3bab1f5d | 939 | case MSR_EFER: |
a9b21b62 | 940 | vmx_load_host_state(vmx); |
2cc51560 | 941 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 942 | break; |
6aa8b732 AK |
943 | case MSR_FS_BASE: |
944 | vmcs_writel(GUEST_FS_BASE, data); | |
945 | break; | |
946 | case MSR_GS_BASE: | |
947 | vmcs_writel(GUEST_GS_BASE, data); | |
948 | break; | |
949 | #endif | |
950 | case MSR_IA32_SYSENTER_CS: | |
951 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
952 | break; | |
953 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 954 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
955 | break; |
956 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 957 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 958 | break; |
d27d4aca | 959 | case MSR_IA32_TIME_STAMP_COUNTER: |
53f658b3 MT |
960 | rdtscll(host_tsc); |
961 | guest_write_tsc(data, host_tsc); | |
efa67e0d CL |
962 | break; |
963 | case MSR_P6_PERFCTR0: | |
964 | case MSR_P6_PERFCTR1: | |
965 | case MSR_P6_EVNTSEL0: | |
966 | case MSR_P6_EVNTSEL1: | |
967 | /* | |
968 | * Just discard all writes to the performance counters; this | |
969 | * should keep both older linux and windows 64-bit guests | |
970 | * happy | |
971 | */ | |
972 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data); | |
973 | ||
6aa8b732 | 974 | break; |
468d472f SY |
975 | case MSR_IA32_CR_PAT: |
976 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
977 | vmcs_write64(GUEST_IA32_PAT, data); | |
978 | vcpu->arch.pat = data; | |
979 | break; | |
980 | } | |
981 | /* Otherwise falls through to kvm_set_msr_common */ | |
6aa8b732 | 982 | default: |
a9b21b62 | 983 | vmx_load_host_state(vmx); |
8b9cf98c | 984 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
985 | if (msr) { |
986 | msr->data = data; | |
987 | break; | |
6aa8b732 | 988 | } |
2cc51560 | 989 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
990 | } |
991 | ||
2cc51560 | 992 | return ret; |
6aa8b732 AK |
993 | } |
994 | ||
5fdbf976 | 995 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 996 | { |
5fdbf976 MT |
997 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
998 | switch (reg) { | |
999 | case VCPU_REGS_RSP: | |
1000 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
1001 | break; | |
1002 | case VCPU_REGS_RIP: | |
1003 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
1004 | break; | |
1005 | default: | |
1006 | break; | |
1007 | } | |
6aa8b732 AK |
1008 | } |
1009 | ||
d0bfb940 | 1010 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
6aa8b732 | 1011 | { |
d0bfb940 JK |
1012 | int old_debug = vcpu->guest_debug; |
1013 | unsigned long flags; | |
6aa8b732 | 1014 | |
d0bfb940 JK |
1015 | vcpu->guest_debug = dbg->control; |
1016 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
1017 | vcpu->guest_debug = 0; | |
6aa8b732 | 1018 | |
ae675ef0 JK |
1019 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1020 | vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); | |
1021 | else | |
1022 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
1023 | ||
d0bfb940 JK |
1024 | flags = vmcs_readl(GUEST_RFLAGS); |
1025 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
1026 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1027 | else if (old_debug & KVM_GUESTDBG_SINGLESTEP) | |
6aa8b732 | 1028 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); |
d0bfb940 | 1029 | vmcs_writel(GUEST_RFLAGS, flags); |
6aa8b732 | 1030 | |
abd3f2d6 | 1031 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1032 | |
1033 | return 0; | |
1034 | } | |
1035 | ||
2a8067f1 ED |
1036 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
1037 | { | |
f7d9238f AK |
1038 | if (!vcpu->arch.interrupt.pending) |
1039 | return -1; | |
1040 | return vcpu->arch.interrupt.nr; | |
2a8067f1 ED |
1041 | } |
1042 | ||
6aa8b732 AK |
1043 | static __init int cpu_has_kvm_support(void) |
1044 | { | |
6210e37b | 1045 | return cpu_has_vmx(); |
6aa8b732 AK |
1046 | } |
1047 | ||
1048 | static __init int vmx_disabled_by_bios(void) | |
1049 | { | |
1050 | u64 msr; | |
1051 | ||
1052 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
9ea542fa SY |
1053 | return (msr & (FEATURE_CONTROL_LOCKED | |
1054 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1055 | == FEATURE_CONTROL_LOCKED; | |
62b3ffb8 | 1056 | /* locked but not enabled */ |
6aa8b732 AK |
1057 | } |
1058 | ||
774c47f1 | 1059 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
1060 | { |
1061 | int cpu = raw_smp_processor_id(); | |
1062 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1063 | u64 old; | |
1064 | ||
543e4243 | 1065 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1066 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
9ea542fa SY |
1067 | if ((old & (FEATURE_CONTROL_LOCKED | |
1068 | FEATURE_CONTROL_VMXON_ENABLED)) | |
1069 | != (FEATURE_CONTROL_LOCKED | | |
1070 | FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 1071 | /* enable and lock */ |
62b3ffb8 | 1072 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
9ea542fa SY |
1073 | FEATURE_CONTROL_LOCKED | |
1074 | FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 1075 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
4ecac3fd AK |
1076 | asm volatile (ASM_VMX_VMXON_RAX |
1077 | : : "a"(&phys_addr), "m"(phys_addr) | |
6aa8b732 AK |
1078 | : "memory", "cc"); |
1079 | } | |
1080 | ||
543e4243 AK |
1081 | static void vmclear_local_vcpus(void) |
1082 | { | |
1083 | int cpu = raw_smp_processor_id(); | |
1084 | struct vcpu_vmx *vmx, *n; | |
1085 | ||
1086 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1087 | local_vcpus_link) | |
1088 | __vcpu_clear(vmx); | |
1089 | } | |
1090 | ||
710ff4a8 EH |
1091 | |
1092 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
1093 | * tricks. | |
1094 | */ | |
1095 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 1096 | { |
4ecac3fd | 1097 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
e693d71b | 1098 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1099 | } |
1100 | ||
710ff4a8 EH |
1101 | static void hardware_disable(void *garbage) |
1102 | { | |
1103 | vmclear_local_vcpus(); | |
1104 | kvm_cpu_vmxoff(); | |
1105 | } | |
1106 | ||
1c3d14fe | 1107 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1108 | u32 msr, u32 *result) |
1c3d14fe YS |
1109 | { |
1110 | u32 vmx_msr_low, vmx_msr_high; | |
1111 | u32 ctl = ctl_min | ctl_opt; | |
1112 | ||
1113 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1114 | ||
1115 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1116 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1117 | ||
1118 | /* Ensure minimum (required) set of control bits are supported. */ | |
1119 | if (ctl_min & ~ctl) | |
002c7f7c | 1120 | return -EIO; |
1c3d14fe YS |
1121 | |
1122 | *result = ctl; | |
1123 | return 0; | |
1124 | } | |
1125 | ||
002c7f7c | 1126 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1127 | { |
1128 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1129 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1130 | u32 _pin_based_exec_control = 0; |
1131 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1132 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1133 | u32 _vmexit_control = 0; |
1134 | u32 _vmentry_control = 0; | |
1135 | ||
1136 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1137 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1138 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1139 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1140 | return -EIO; |
1c3d14fe YS |
1141 | |
1142 | min = CPU_BASED_HLT_EXITING | | |
1143 | #ifdef CONFIG_X86_64 | |
1144 | CPU_BASED_CR8_LOAD_EXITING | | |
1145 | CPU_BASED_CR8_STORE_EXITING | | |
1146 | #endif | |
d56f546d SY |
1147 | CPU_BASED_CR3_LOAD_EXITING | |
1148 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1149 | CPU_BASED_USE_IO_BITMAPS | |
1150 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 MT |
1151 | CPU_BASED_USE_TSC_OFFSETING | |
1152 | CPU_BASED_INVLPG_EXITING; | |
f78e0e2e | 1153 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1154 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1155 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1156 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1157 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1158 | return -EIO; |
6e5d865c YS |
1159 | #ifdef CONFIG_X86_64 |
1160 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1161 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1162 | ~CPU_BASED_CR8_STORE_EXITING; | |
1163 | #endif | |
f78e0e2e | 1164 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1165 | min2 = 0; |
1166 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1167 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1168 | SECONDARY_EXEC_ENABLE_VPID | |
1169 | SECONDARY_EXEC_ENABLE_EPT; | |
1170 | if (adjust_vmx_controls(min2, opt2, | |
1171 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1172 | &_cpu_based_2nd_exec_control) < 0) |
1173 | return -EIO; | |
1174 | } | |
1175 | #ifndef CONFIG_X86_64 | |
1176 | if (!(_cpu_based_2nd_exec_control & | |
1177 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1178 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1179 | #endif | |
d56f546d | 1180 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1181 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1182 | enabled */ | |
d56f546d | 1183 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | |
a7052897 MT |
1184 | CPU_BASED_CR3_STORE_EXITING | |
1185 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1186 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1187 | &_cpu_based_exec_control) < 0) | |
1188 | return -EIO; | |
1189 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1190 | vmx_capability.ept, vmx_capability.vpid); | |
1191 | } | |
1c3d14fe YS |
1192 | |
1193 | min = 0; | |
1194 | #ifdef CONFIG_X86_64 | |
1195 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1196 | #endif | |
468d472f | 1197 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
1198 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
1199 | &_vmexit_control) < 0) | |
002c7f7c | 1200 | return -EIO; |
1c3d14fe | 1201 | |
468d472f SY |
1202 | min = 0; |
1203 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
1204 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
1205 | &_vmentry_control) < 0) | |
002c7f7c | 1206 | return -EIO; |
6aa8b732 | 1207 | |
c68876fd | 1208 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1209 | |
1210 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1211 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1212 | return -EIO; |
1c3d14fe YS |
1213 | |
1214 | #ifdef CONFIG_X86_64 | |
1215 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1216 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1217 | return -EIO; |
1c3d14fe YS |
1218 | #endif |
1219 | ||
1220 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1221 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1222 | return -EIO; |
1c3d14fe | 1223 | |
002c7f7c YS |
1224 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1225 | vmcs_conf->order = get_order(vmcs_config.size); | |
1226 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1227 | |
002c7f7c YS |
1228 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1229 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1230 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1231 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1232 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1233 | |
1234 | return 0; | |
c68876fd | 1235 | } |
6aa8b732 AK |
1236 | |
1237 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1238 | { | |
1239 | int node = cpu_to_node(cpu); | |
1240 | struct page *pages; | |
1241 | struct vmcs *vmcs; | |
1242 | ||
1c3d14fe | 1243 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1244 | if (!pages) |
1245 | return NULL; | |
1246 | vmcs = page_address(pages); | |
1c3d14fe YS |
1247 | memset(vmcs, 0, vmcs_config.size); |
1248 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1249 | return vmcs; |
1250 | } | |
1251 | ||
1252 | static struct vmcs *alloc_vmcs(void) | |
1253 | { | |
d3b2c338 | 1254 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1255 | } |
1256 | ||
1257 | static void free_vmcs(struct vmcs *vmcs) | |
1258 | { | |
1c3d14fe | 1259 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1260 | } |
1261 | ||
39959588 | 1262 | static void free_kvm_area(void) |
6aa8b732 AK |
1263 | { |
1264 | int cpu; | |
1265 | ||
1266 | for_each_online_cpu(cpu) | |
1267 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1268 | } | |
1269 | ||
6aa8b732 AK |
1270 | static __init int alloc_kvm_area(void) |
1271 | { | |
1272 | int cpu; | |
1273 | ||
1274 | for_each_online_cpu(cpu) { | |
1275 | struct vmcs *vmcs; | |
1276 | ||
1277 | vmcs = alloc_vmcs_cpu(cpu); | |
1278 | if (!vmcs) { | |
1279 | free_kvm_area(); | |
1280 | return -ENOMEM; | |
1281 | } | |
1282 | ||
1283 | per_cpu(vmxarea, cpu) = vmcs; | |
1284 | } | |
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | static __init int hardware_setup(void) | |
1289 | { | |
002c7f7c YS |
1290 | if (setup_vmcs_config(&vmcs_config) < 0) |
1291 | return -EIO; | |
50a37eb4 JR |
1292 | |
1293 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1294 | kvm_enable_efer_bits(EFER_NX); | |
1295 | ||
6aa8b732 AK |
1296 | return alloc_kvm_area(); |
1297 | } | |
1298 | ||
1299 | static __exit void hardware_unsetup(void) | |
1300 | { | |
1301 | free_kvm_area(); | |
1302 | } | |
1303 | ||
6aa8b732 AK |
1304 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1305 | { | |
1306 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1307 | ||
6af11b9e | 1308 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1309 | vmcs_write16(sf->selector, save->selector); |
1310 | vmcs_writel(sf->base, save->base); | |
1311 | vmcs_write32(sf->limit, save->limit); | |
1312 | vmcs_write32(sf->ar_bytes, save->ar); | |
1313 | } else { | |
1314 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1315 | << AR_DPL_SHIFT; | |
1316 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1317 | } | |
1318 | } | |
1319 | ||
1320 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1321 | { | |
1322 | unsigned long flags; | |
a89a8fb9 | 1323 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1324 | |
a89a8fb9 | 1325 | vmx->emulation_required = 1; |
ad312c7c | 1326 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1327 | |
ad312c7c ZX |
1328 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1329 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1330 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1331 | |
1332 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1333 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1334 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1335 | vmcs_writel(GUEST_RFLAGS, flags); |
1336 | ||
66aee91a RR |
1337 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1338 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1339 | |
1340 | update_exception_bitmap(vcpu); | |
1341 | ||
a89a8fb9 MG |
1342 | if (emulate_invalid_guest_state) |
1343 | return; | |
1344 | ||
ad312c7c ZX |
1345 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1346 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1347 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1348 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1349 | |
1350 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1351 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1352 | ||
1353 | vmcs_write16(GUEST_CS_SELECTOR, | |
1354 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1355 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1356 | } | |
1357 | ||
d77c26fc | 1358 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1359 | { |
bfc6d222 | 1360 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1361 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1362 | kvm->memslots[0].npages - 3; | |
1363 | return base_gfn << PAGE_SHIFT; | |
1364 | } | |
bfc6d222 | 1365 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1366 | } |
1367 | ||
1368 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1369 | { | |
1370 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1371 | ||
1372 | save->selector = vmcs_read16(sf->selector); | |
1373 | save->base = vmcs_readl(sf->base); | |
1374 | save->limit = vmcs_read32(sf->limit); | |
1375 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1376 | vmcs_write16(sf->selector, save->base >> 4); |
1377 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1378 | vmcs_write32(sf->limit, 0xffff); |
1379 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1380 | } | |
1381 | ||
1382 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1383 | { | |
1384 | unsigned long flags; | |
a89a8fb9 | 1385 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1386 | |
a89a8fb9 | 1387 | vmx->emulation_required = 1; |
ad312c7c | 1388 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1389 | |
ad312c7c | 1390 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1391 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1392 | ||
ad312c7c | 1393 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1394 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1395 | ||
ad312c7c | 1396 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1397 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1398 | ||
1399 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1400 | vcpu->arch.rmode.save_iopl |
1401 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1402 | |
053de044 | 1403 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1404 | |
1405 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1406 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1407 | update_exception_bitmap(vcpu); |
1408 | ||
a89a8fb9 MG |
1409 | if (emulate_invalid_guest_state) |
1410 | goto continue_rmode; | |
1411 | ||
6aa8b732 AK |
1412 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
1413 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1414 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1415 | ||
1416 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1417 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1418 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1419 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1420 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1421 | ||
ad312c7c ZX |
1422 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1423 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1424 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1425 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1426 | |
a89a8fb9 | 1427 | continue_rmode: |
8668a3c4 | 1428 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1429 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1430 | } |
1431 | ||
05b3e0c2 | 1432 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1433 | |
1434 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1435 | { | |
1436 | u32 guest_tr_ar; | |
1437 | ||
1438 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1439 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1440 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1441 | __func__); |
6aa8b732 AK |
1442 | vmcs_write32(GUEST_TR_AR_BYTES, |
1443 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1444 | | AR_TYPE_BUSY_64_TSS); | |
1445 | } | |
1446 | ||
ad312c7c | 1447 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1448 | |
8b9cf98c | 1449 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1450 | vmcs_write32(VM_ENTRY_CONTROLS, |
1451 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1452 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1453 | } |
1454 | ||
1455 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1456 | { | |
ad312c7c | 1457 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1458 | |
1459 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1460 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1461 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1462 | } |
1463 | ||
1464 | #endif | |
1465 | ||
2384d2b3 SY |
1466 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1467 | { | |
1468 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
4e1096d2 SY |
1469 | if (vm_need_ept()) |
1470 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); | |
2384d2b3 SY |
1471 | } |
1472 | ||
25c4c276 | 1473 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1474 | { |
ad312c7c ZX |
1475 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1476 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1477 | } |
1478 | ||
1439442c SY |
1479 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1480 | { | |
1481 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1482 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1483 | printk(KERN_ERR "EPT: Fail to load pdptrs!\n"); | |
1484 | return; | |
1485 | } | |
1486 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); | |
1487 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1488 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1489 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1494 | ||
1495 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1496 | unsigned long cr0, | |
1497 | struct kvm_vcpu *vcpu) | |
1498 | { | |
1499 | if (!(cr0 & X86_CR0_PG)) { | |
1500 | /* From paging/starting to nonpaging */ | |
1501 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1502 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1503 | (CPU_BASED_CR3_LOAD_EXITING | |
1504 | CPU_BASED_CR3_STORE_EXITING)); | |
1505 | vcpu->arch.cr0 = cr0; | |
1506 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1507 | *hw_cr0 |= X86_CR0_PE | X86_CR0_PG; | |
1508 | *hw_cr0 &= ~X86_CR0_WP; | |
1509 | } else if (!is_paging(vcpu)) { | |
1510 | /* From nonpaging to paging */ | |
1511 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1512 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1513 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1514 | CPU_BASED_CR3_STORE_EXITING)); | |
1515 | vcpu->arch.cr0 = cr0; | |
1516 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1517 | if (!(vcpu->arch.cr0 & X86_CR0_WP)) | |
1518 | *hw_cr0 &= ~X86_CR0_WP; | |
1519 | } | |
1520 | } | |
1521 | ||
1522 | static void ept_update_paging_mode_cr4(unsigned long *hw_cr4, | |
1523 | struct kvm_vcpu *vcpu) | |
1524 | { | |
1525 | if (!is_paging(vcpu)) { | |
1526 | *hw_cr4 &= ~X86_CR4_PAE; | |
1527 | *hw_cr4 |= X86_CR4_PSE; | |
1528 | } else if (!(vcpu->arch.cr4 & X86_CR4_PAE)) | |
1529 | *hw_cr4 &= ~X86_CR4_PAE; | |
1530 | } | |
1531 | ||
6aa8b732 AK |
1532 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1533 | { | |
1439442c SY |
1534 | unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | |
1535 | KVM_VM_CR0_ALWAYS_ON; | |
1536 | ||
5fd86fcf AK |
1537 | vmx_fpu_deactivate(vcpu); |
1538 | ||
ad312c7c | 1539 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1540 | enter_pmode(vcpu); |
1541 | ||
ad312c7c | 1542 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1543 | enter_rmode(vcpu); |
1544 | ||
05b3e0c2 | 1545 | #ifdef CONFIG_X86_64 |
ad312c7c | 1546 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1547 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1548 | enter_lmode(vcpu); |
707d92fa | 1549 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1550 | exit_lmode(vcpu); |
1551 | } | |
1552 | #endif | |
1553 | ||
1439442c SY |
1554 | if (vm_need_ept()) |
1555 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | |
1556 | ||
6aa8b732 | 1557 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1558 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1559 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1560 | |
707d92fa | 1561 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1562 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1563 | } |
1564 | ||
1439442c SY |
1565 | static u64 construct_eptp(unsigned long root_hpa) |
1566 | { | |
1567 | u64 eptp; | |
1568 | ||
1569 | /* TODO write the value reading from MSR */ | |
1570 | eptp = VMX_EPT_DEFAULT_MT | | |
1571 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1572 | eptp |= (root_hpa & PAGE_MASK); | |
1573 | ||
1574 | return eptp; | |
1575 | } | |
1576 | ||
6aa8b732 AK |
1577 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1578 | { | |
1439442c SY |
1579 | unsigned long guest_cr3; |
1580 | u64 eptp; | |
1581 | ||
1582 | guest_cr3 = cr3; | |
1583 | if (vm_need_ept()) { | |
1584 | eptp = construct_eptp(cr3); | |
1585 | vmcs_write64(EPT_POINTER, eptp); | |
1586 | ept_sync_context(eptp); | |
1587 | ept_load_pdptrs(vcpu); | |
1588 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : | |
1589 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1590 | } | |
1591 | ||
2384d2b3 | 1592 | vmx_flush_tlb(vcpu); |
1439442c | 1593 | vmcs_writel(GUEST_CR3, guest_cr3); |
ad312c7c | 1594 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1595 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1596 | } |
1597 | ||
1598 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1599 | { | |
1439442c SY |
1600 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? |
1601 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1602 | ||
ad312c7c | 1603 | vcpu->arch.cr4 = cr4; |
1439442c SY |
1604 | if (vm_need_ept()) |
1605 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | |
1606 | ||
1607 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1608 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1609 | } |
1610 | ||
6aa8b732 AK |
1611 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1612 | { | |
8b9cf98c RR |
1613 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1614 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1615 | |
ad312c7c | 1616 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1617 | if (!msr) |
1618 | return; | |
6aa8b732 AK |
1619 | if (efer & EFER_LMA) { |
1620 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1621 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1622 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1623 | msr->data = efer; |
1624 | ||
1625 | } else { | |
1626 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1627 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1628 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1629 | |
1630 | msr->data = efer & ~EFER_LME; | |
1631 | } | |
8b9cf98c | 1632 | setup_msrs(vmx); |
6aa8b732 AK |
1633 | } |
1634 | ||
6aa8b732 AK |
1635 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1636 | { | |
1637 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1638 | ||
1639 | return vmcs_readl(sf->base); | |
1640 | } | |
1641 | ||
1642 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1643 | struct kvm_segment *var, int seg) | |
1644 | { | |
1645 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1646 | u32 ar; | |
1647 | ||
1648 | var->base = vmcs_readl(sf->base); | |
1649 | var->limit = vmcs_read32(sf->limit); | |
1650 | var->selector = vmcs_read16(sf->selector); | |
1651 | ar = vmcs_read32(sf->ar_bytes); | |
9fd4a3b7 | 1652 | if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
6aa8b732 AK |
1653 | ar = 0; |
1654 | var->type = ar & 15; | |
1655 | var->s = (ar >> 4) & 1; | |
1656 | var->dpl = (ar >> 5) & 3; | |
1657 | var->present = (ar >> 7) & 1; | |
1658 | var->avl = (ar >> 12) & 1; | |
1659 | var->l = (ar >> 13) & 1; | |
1660 | var->db = (ar >> 14) & 1; | |
1661 | var->g = (ar >> 15) & 1; | |
1662 | var->unusable = (ar >> 16) & 1; | |
1663 | } | |
1664 | ||
2e4d2653 IE |
1665 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1666 | { | |
1667 | struct kvm_segment kvm_seg; | |
1668 | ||
1669 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1670 | return 0; | |
1671 | ||
1672 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1673 | return 3; | |
1674 | ||
1675 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1676 | return kvm_seg.selector & 3; | |
1677 | } | |
1678 | ||
653e3108 | 1679 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1680 | { |
6aa8b732 AK |
1681 | u32 ar; |
1682 | ||
653e3108 | 1683 | if (var->unusable) |
6aa8b732 AK |
1684 | ar = 1 << 16; |
1685 | else { | |
1686 | ar = var->type & 15; | |
1687 | ar |= (var->s & 1) << 4; | |
1688 | ar |= (var->dpl & 3) << 5; | |
1689 | ar |= (var->present & 1) << 7; | |
1690 | ar |= (var->avl & 1) << 12; | |
1691 | ar |= (var->l & 1) << 13; | |
1692 | ar |= (var->db & 1) << 14; | |
1693 | ar |= (var->g & 1) << 15; | |
1694 | } | |
f7fbf1fd UL |
1695 | if (ar == 0) /* a 0 value means unusable */ |
1696 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1697 | |
1698 | return ar; | |
1699 | } | |
1700 | ||
1701 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1702 | struct kvm_segment *var, int seg) | |
1703 | { | |
1704 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1705 | u32 ar; | |
1706 | ||
ad312c7c ZX |
1707 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1708 | vcpu->arch.rmode.tr.selector = var->selector; | |
1709 | vcpu->arch.rmode.tr.base = var->base; | |
1710 | vcpu->arch.rmode.tr.limit = var->limit; | |
1711 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1712 | return; |
1713 | } | |
1714 | vmcs_writel(sf->base, var->base); | |
1715 | vmcs_write32(sf->limit, var->limit); | |
1716 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1717 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1718 | /* |
1719 | * Hack real-mode segments into vm86 compatibility. | |
1720 | */ | |
1721 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1722 | vmcs_writel(sf->base, 0xf0000); | |
1723 | ar = 0xf3; | |
1724 | } else | |
1725 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1726 | vmcs_write32(sf->ar_bytes, ar); |
1727 | } | |
1728 | ||
6aa8b732 AK |
1729 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1730 | { | |
1731 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1732 | ||
1733 | *db = (ar >> 14) & 1; | |
1734 | *l = (ar >> 13) & 1; | |
1735 | } | |
1736 | ||
1737 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1738 | { | |
1739 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1740 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1741 | } | |
1742 | ||
1743 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1744 | { | |
1745 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1746 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1747 | } | |
1748 | ||
1749 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1750 | { | |
1751 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1752 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1753 | } | |
1754 | ||
1755 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1756 | { | |
1757 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1758 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1759 | } | |
1760 | ||
648dfaa7 MG |
1761 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
1762 | { | |
1763 | struct kvm_segment var; | |
1764 | u32 ar; | |
1765 | ||
1766 | vmx_get_segment(vcpu, &var, seg); | |
1767 | ar = vmx_segment_access_rights(&var); | |
1768 | ||
1769 | if (var.base != (var.selector << 4)) | |
1770 | return false; | |
1771 | if (var.limit != 0xffff) | |
1772 | return false; | |
1773 | if (ar != 0xf3) | |
1774 | return false; | |
1775 | ||
1776 | return true; | |
1777 | } | |
1778 | ||
1779 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
1780 | { | |
1781 | struct kvm_segment cs; | |
1782 | unsigned int cs_rpl; | |
1783 | ||
1784 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1785 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
1786 | ||
1872a3f4 AK |
1787 | if (cs.unusable) |
1788 | return false; | |
648dfaa7 MG |
1789 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
1790 | return false; | |
1791 | if (!cs.s) | |
1792 | return false; | |
1872a3f4 | 1793 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
1794 | if (cs.dpl > cs_rpl) |
1795 | return false; | |
1872a3f4 | 1796 | } else { |
648dfaa7 MG |
1797 | if (cs.dpl != cs_rpl) |
1798 | return false; | |
1799 | } | |
1800 | if (!cs.present) | |
1801 | return false; | |
1802 | ||
1803 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
1804 | return true; | |
1805 | } | |
1806 | ||
1807 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
1808 | { | |
1809 | struct kvm_segment ss; | |
1810 | unsigned int ss_rpl; | |
1811 | ||
1812 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
1813 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
1814 | ||
1872a3f4 AK |
1815 | if (ss.unusable) |
1816 | return true; | |
1817 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
1818 | return false; |
1819 | if (!ss.s) | |
1820 | return false; | |
1821 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
1822 | return false; | |
1823 | if (!ss.present) | |
1824 | return false; | |
1825 | ||
1826 | return true; | |
1827 | } | |
1828 | ||
1829 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
1830 | { | |
1831 | struct kvm_segment var; | |
1832 | unsigned int rpl; | |
1833 | ||
1834 | vmx_get_segment(vcpu, &var, seg); | |
1835 | rpl = var.selector & SELECTOR_RPL_MASK; | |
1836 | ||
1872a3f4 AK |
1837 | if (var.unusable) |
1838 | return true; | |
648dfaa7 MG |
1839 | if (!var.s) |
1840 | return false; | |
1841 | if (!var.present) | |
1842 | return false; | |
1843 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
1844 | if (var.dpl < rpl) /* DPL < RPL */ | |
1845 | return false; | |
1846 | } | |
1847 | ||
1848 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
1849 | * rights flags | |
1850 | */ | |
1851 | return true; | |
1852 | } | |
1853 | ||
1854 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
1855 | { | |
1856 | struct kvm_segment tr; | |
1857 | ||
1858 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
1859 | ||
1872a3f4 AK |
1860 | if (tr.unusable) |
1861 | return false; | |
648dfaa7 MG |
1862 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
1863 | return false; | |
1872a3f4 | 1864 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
1865 | return false; |
1866 | if (!tr.present) | |
1867 | return false; | |
1868 | ||
1869 | return true; | |
1870 | } | |
1871 | ||
1872 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
1873 | { | |
1874 | struct kvm_segment ldtr; | |
1875 | ||
1876 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
1877 | ||
1872a3f4 AK |
1878 | if (ldtr.unusable) |
1879 | return true; | |
648dfaa7 MG |
1880 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
1881 | return false; | |
1882 | if (ldtr.type != 2) | |
1883 | return false; | |
1884 | if (!ldtr.present) | |
1885 | return false; | |
1886 | ||
1887 | return true; | |
1888 | } | |
1889 | ||
1890 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
1891 | { | |
1892 | struct kvm_segment cs, ss; | |
1893 | ||
1894 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
1895 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
1896 | ||
1897 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
1898 | (ss.selector & SELECTOR_RPL_MASK)); | |
1899 | } | |
1900 | ||
1901 | /* | |
1902 | * Check if guest state is valid. Returns true if valid, false if | |
1903 | * not. | |
1904 | * We assume that registers are always usable | |
1905 | */ | |
1906 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
1907 | { | |
1908 | /* real mode guest state checks */ | |
1909 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) { | |
1910 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) | |
1911 | return false; | |
1912 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
1913 | return false; | |
1914 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
1915 | return false; | |
1916 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
1917 | return false; | |
1918 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
1919 | return false; | |
1920 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
1921 | return false; | |
1922 | } else { | |
1923 | /* protected mode guest state checks */ | |
1924 | if (!cs_ss_rpl_check(vcpu)) | |
1925 | return false; | |
1926 | if (!code_segment_valid(vcpu)) | |
1927 | return false; | |
1928 | if (!stack_segment_valid(vcpu)) | |
1929 | return false; | |
1930 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
1931 | return false; | |
1932 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
1933 | return false; | |
1934 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
1935 | return false; | |
1936 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
1937 | return false; | |
1938 | if (!tr_valid(vcpu)) | |
1939 | return false; | |
1940 | if (!ldtr_valid(vcpu)) | |
1941 | return false; | |
1942 | } | |
1943 | /* TODO: | |
1944 | * - Add checks on RIP | |
1945 | * - Add checks on RFLAGS | |
1946 | */ | |
1947 | ||
1948 | return true; | |
1949 | } | |
1950 | ||
d77c26fc | 1951 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1952 | { |
6aa8b732 | 1953 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1954 | u16 data = 0; |
10589a46 | 1955 | int ret = 0; |
195aefde | 1956 | int r; |
6aa8b732 | 1957 | |
195aefde IE |
1958 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1959 | if (r < 0) | |
10589a46 | 1960 | goto out; |
195aefde | 1961 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
1962 | r = kvm_write_guest_page(kvm, fn++, &data, |
1963 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 1964 | if (r < 0) |
10589a46 | 1965 | goto out; |
195aefde IE |
1966 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1967 | if (r < 0) | |
10589a46 | 1968 | goto out; |
195aefde IE |
1969 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1970 | if (r < 0) | |
10589a46 | 1971 | goto out; |
195aefde | 1972 | data = ~0; |
10589a46 MT |
1973 | r = kvm_write_guest_page(kvm, fn, &data, |
1974 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1975 | sizeof(u8)); | |
195aefde | 1976 | if (r < 0) |
10589a46 MT |
1977 | goto out; |
1978 | ||
1979 | ret = 1; | |
1980 | out: | |
10589a46 | 1981 | return ret; |
6aa8b732 AK |
1982 | } |
1983 | ||
b7ebfb05 SY |
1984 | static int init_rmode_identity_map(struct kvm *kvm) |
1985 | { | |
1986 | int i, r, ret; | |
1987 | pfn_t identity_map_pfn; | |
1988 | u32 tmp; | |
1989 | ||
1990 | if (!vm_need_ept()) | |
1991 | return 1; | |
1992 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
1993 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
1994 | "haven't been allocated!\n"); | |
1995 | return 0; | |
1996 | } | |
1997 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
1998 | return 1; | |
1999 | ret = 0; | |
2000 | identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT; | |
2001 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); | |
2002 | if (r < 0) | |
2003 | goto out; | |
2004 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
2005 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
2006 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
2007 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
2008 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
2009 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
2010 | if (r < 0) | |
2011 | goto out; | |
2012 | } | |
2013 | kvm->arch.ept_identity_pagetable_done = true; | |
2014 | ret = 1; | |
2015 | out: | |
2016 | return ret; | |
2017 | } | |
2018 | ||
6aa8b732 AK |
2019 | static void seg_setup(int seg) |
2020 | { | |
2021 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2022 | ||
2023 | vmcs_write16(sf->selector, 0); | |
2024 | vmcs_writel(sf->base, 0); | |
2025 | vmcs_write32(sf->limit, 0xffff); | |
a16b20da | 2026 | vmcs_write32(sf->ar_bytes, 0xf3); |
6aa8b732 AK |
2027 | } |
2028 | ||
f78e0e2e SY |
2029 | static int alloc_apic_access_page(struct kvm *kvm) |
2030 | { | |
2031 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2032 | int r = 0; | |
2033 | ||
72dc67a6 | 2034 | down_write(&kvm->slots_lock); |
bfc6d222 | 2035 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
2036 | goto out; |
2037 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
2038 | kvm_userspace_mem.flags = 0; | |
2039 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
2040 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2041 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2042 | if (r) | |
2043 | goto out; | |
72dc67a6 | 2044 | |
bfc6d222 | 2045 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 2046 | out: |
72dc67a6 | 2047 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
2048 | return r; |
2049 | } | |
2050 | ||
b7ebfb05 SY |
2051 | static int alloc_identity_pagetable(struct kvm *kvm) |
2052 | { | |
2053 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2054 | int r = 0; | |
2055 | ||
2056 | down_write(&kvm->slots_lock); | |
2057 | if (kvm->arch.ept_identity_pagetable) | |
2058 | goto out; | |
2059 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
2060 | kvm_userspace_mem.flags = 0; | |
2061 | kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
2062 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2063 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2064 | if (r) | |
2065 | goto out; | |
2066 | ||
b7ebfb05 SY |
2067 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
2068 | VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT); | |
b7ebfb05 SY |
2069 | out: |
2070 | up_write(&kvm->slots_lock); | |
2071 | return r; | |
2072 | } | |
2073 | ||
2384d2b3 SY |
2074 | static void allocate_vpid(struct vcpu_vmx *vmx) |
2075 | { | |
2076 | int vpid; | |
2077 | ||
2078 | vmx->vpid = 0; | |
2079 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
2080 | return; | |
2081 | spin_lock(&vmx_vpid_lock); | |
2082 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
2083 | if (vpid < VMX_NR_VPIDS) { | |
2084 | vmx->vpid = vpid; | |
2085 | __set_bit(vpid, vmx_vpid_bitmap); | |
2086 | } | |
2087 | spin_unlock(&vmx_vpid_lock); | |
2088 | } | |
2089 | ||
8b2cf73c | 2090 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
25c5f225 SY |
2091 | { |
2092 | void *va; | |
2093 | ||
2094 | if (!cpu_has_vmx_msr_bitmap()) | |
2095 | return; | |
2096 | ||
2097 | /* | |
2098 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
2099 | * have the write-low and read-high bitmap offsets the wrong way round. | |
2100 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
2101 | */ | |
2102 | va = kmap(msr_bitmap); | |
2103 | if (msr <= 0x1fff) { | |
2104 | __clear_bit(msr, va + 0x000); /* read-low */ | |
2105 | __clear_bit(msr, va + 0x800); /* write-low */ | |
2106 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2107 | msr &= 0x1fff; | |
2108 | __clear_bit(msr, va + 0x400); /* read-high */ | |
2109 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
2110 | } | |
2111 | kunmap(msr_bitmap); | |
2112 | } | |
2113 | ||
6aa8b732 AK |
2114 | /* |
2115 | * Sets up the vmcs for emulated real mode. | |
2116 | */ | |
8b9cf98c | 2117 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 2118 | { |
468d472f | 2119 | u32 host_sysenter_cs, msr_low, msr_high; |
6aa8b732 | 2120 | u32 junk; |
53f658b3 | 2121 | u64 host_pat, tsc_this, tsc_base; |
6aa8b732 AK |
2122 | unsigned long a; |
2123 | struct descriptor_table dt; | |
2124 | int i; | |
cd2276a7 | 2125 | unsigned long kvm_vmx_return; |
6e5d865c | 2126 | u32 exec_control; |
6aa8b732 | 2127 | |
6aa8b732 | 2128 | /* I/O */ |
fdef3ad1 HQ |
2129 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
2130 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 2131 | |
25c5f225 SY |
2132 | if (cpu_has_vmx_msr_bitmap()) |
2133 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
2134 | ||
6aa8b732 AK |
2135 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2136 | ||
6aa8b732 | 2137 | /* Control */ |
1c3d14fe YS |
2138 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
2139 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
2140 | |
2141 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
2142 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
2143 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2144 | #ifdef CONFIG_X86_64 | |
2145 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
2146 | CPU_BASED_CR8_LOAD_EXITING; | |
2147 | #endif | |
2148 | } | |
d56f546d SY |
2149 | if (!vm_need_ept()) |
2150 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
83dbc83a MT |
2151 | CPU_BASED_CR3_LOAD_EXITING | |
2152 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 2153 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 2154 | |
83ff3b9d SY |
2155 | if (cpu_has_secondary_exec_ctrls()) { |
2156 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
2157 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2158 | exec_control &= | |
2159 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
2160 | if (vmx->vpid == 0) |
2161 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
2162 | if (!vm_need_ept()) |
2163 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
2164 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2165 | } | |
f78e0e2e | 2166 | |
c7addb90 AK |
2167 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
2168 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
2169 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
2170 | ||
2171 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
2172 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
2173 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
2174 | ||
2175 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
2176 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
2177 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
d6e88aec AK |
2178 | vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */ |
2179 | vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */ | |
6aa8b732 | 2180 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 2181 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2182 | rdmsrl(MSR_FS_BASE, a); |
2183 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
2184 | rdmsrl(MSR_GS_BASE, a); | |
2185 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
2186 | #else | |
2187 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
2188 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
2189 | #endif | |
2190 | ||
2191 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
2192 | ||
d6e88aec | 2193 | kvm_get_idt(&dt); |
6aa8b732 AK |
2194 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ |
2195 | ||
d77c26fc | 2196 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 2197 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
2198 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
2199 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
2200 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
2201 | |
2202 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
2203 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
2204 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
2205 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
2206 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
2207 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
2208 | ||
468d472f SY |
2209 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { |
2210 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2211 | host_pat = msr_low | ((u64) msr_high << 32); | |
2212 | vmcs_write64(HOST_IA32_PAT, host_pat); | |
2213 | } | |
2214 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
2215 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2216 | host_pat = msr_low | ((u64) msr_high << 32); | |
2217 | /* Write the default value follow host pat */ | |
2218 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
2219 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
2220 | vmx->vcpu.arch.pat = host_pat; | |
2221 | } | |
2222 | ||
6aa8b732 AK |
2223 | for (i = 0; i < NR_VMX_MSR; ++i) { |
2224 | u32 index = vmx_msr_index[i]; | |
2225 | u32 data_low, data_high; | |
2226 | u64 data; | |
a2fa3e9f | 2227 | int j = vmx->nmsrs; |
6aa8b732 AK |
2228 | |
2229 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
2230 | continue; | |
432bd6cb AK |
2231 | if (wrmsr_safe(index, data_low, data_high) < 0) |
2232 | continue; | |
6aa8b732 | 2233 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
2234 | vmx->host_msrs[j].index = index; |
2235 | vmx->host_msrs[j].reserved = 0; | |
2236 | vmx->host_msrs[j].data = data; | |
2237 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
2238 | ++vmx->nmsrs; | |
6aa8b732 | 2239 | } |
6aa8b732 | 2240 | |
1c3d14fe | 2241 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2242 | |
2243 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2244 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2245 | ||
e00c8cf2 AK |
2246 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
2247 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
2248 | ||
53f658b3 MT |
2249 | tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc; |
2250 | rdtscll(tsc_this); | |
2251 | if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc) | |
2252 | tsc_base = tsc_this; | |
2253 | ||
2254 | guest_write_tsc(0, tsc_base); | |
f78e0e2e | 2255 | |
e00c8cf2 AK |
2256 | return 0; |
2257 | } | |
2258 | ||
b7ebfb05 SY |
2259 | static int init_rmode(struct kvm *kvm) |
2260 | { | |
2261 | if (!init_rmode_tss(kvm)) | |
2262 | return 0; | |
2263 | if (!init_rmode_identity_map(kvm)) | |
2264 | return 0; | |
2265 | return 1; | |
2266 | } | |
2267 | ||
e00c8cf2 AK |
2268 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2269 | { | |
2270 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2271 | u64 msr; | |
2272 | int ret; | |
2273 | ||
5fdbf976 | 2274 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3200f405 | 2275 | down_read(&vcpu->kvm->slots_lock); |
b7ebfb05 | 2276 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2277 | ret = -ENOMEM; |
2278 | goto out; | |
2279 | } | |
2280 | ||
ad312c7c | 2281 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 2282 | |
3b86cd99 JK |
2283 | vmx->soft_vnmi_blocked = 0; |
2284 | ||
ad312c7c | 2285 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2286 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
2287 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
2288 | if (vmx->vcpu.vcpu_id == 0) | |
2289 | msr |= MSR_IA32_APICBASE_BSP; | |
2290 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2291 | ||
2292 | fx_init(&vmx->vcpu); | |
2293 | ||
5706be0d | 2294 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
2295 | /* |
2296 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2297 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2298 | */ | |
2299 | if (vmx->vcpu.vcpu_id == 0) { | |
2300 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
2301 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2302 | } else { | |
ad312c7c ZX |
2303 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2304 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 2305 | } |
e00c8cf2 AK |
2306 | |
2307 | seg_setup(VCPU_SREG_DS); | |
2308 | seg_setup(VCPU_SREG_ES); | |
2309 | seg_setup(VCPU_SREG_FS); | |
2310 | seg_setup(VCPU_SREG_GS); | |
2311 | seg_setup(VCPU_SREG_SS); | |
2312 | ||
2313 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2314 | vmcs_writel(GUEST_TR_BASE, 0); | |
2315 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2316 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2317 | ||
2318 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2319 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2320 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2321 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2322 | ||
2323 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2324 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2325 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2326 | ||
2327 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
2328 | if (vmx->vcpu.vcpu_id == 0) | |
5fdbf976 | 2329 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2330 | else |
5fdbf976 MT |
2331 | kvm_rip_write(vcpu, 0); |
2332 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 | 2333 | |
e00c8cf2 AK |
2334 | vmcs_writel(GUEST_DR7, 0x400); |
2335 | ||
2336 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2337 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2338 | ||
2339 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2340 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2341 | ||
2342 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2343 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2344 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2345 | ||
e00c8cf2 AK |
2346 | /* Special registers */ |
2347 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2348 | ||
2349 | setup_msrs(vmx); | |
2350 | ||
6aa8b732 AK |
2351 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2352 | ||
f78e0e2e SY |
2353 | if (cpu_has_vmx_tpr_shadow()) { |
2354 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2355 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2356 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2357 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2358 | vmcs_write32(TPR_THRESHOLD, 0); |
2359 | } | |
2360 | ||
2361 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2362 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2363 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2364 | |
2384d2b3 SY |
2365 | if (vmx->vpid != 0) |
2366 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2367 | ||
ad312c7c ZX |
2368 | vmx->vcpu.arch.cr0 = 0x60000010; |
2369 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 2370 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2371 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2372 | vmx_fpu_activate(&vmx->vcpu); |
2373 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2374 | |
2384d2b3 SY |
2375 | vpid_sync_vcpu_all(vmx); |
2376 | ||
3200f405 | 2377 | ret = 0; |
6aa8b732 | 2378 | |
a89a8fb9 MG |
2379 | /* HACK: Don't enable emulation on guest boot/reset */ |
2380 | vmx->emulation_required = 0; | |
2381 | ||
6aa8b732 | 2382 | out: |
3200f405 | 2383 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
2384 | return ret; |
2385 | } | |
2386 | ||
3b86cd99 JK |
2387 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2388 | { | |
2389 | u32 cpu_based_vm_exec_control; | |
2390 | ||
2391 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2392 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2393 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2394 | } | |
2395 | ||
2396 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
2397 | { | |
2398 | u32 cpu_based_vm_exec_control; | |
2399 | ||
2400 | if (!cpu_has_virtual_nmis()) { | |
2401 | enable_irq_window(vcpu); | |
2402 | return; | |
2403 | } | |
2404 | ||
2405 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2406 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2407 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2408 | } | |
2409 | ||
85f455f7 ED |
2410 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
2411 | { | |
9c8cba37 AK |
2412 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2413 | ||
2714d1d3 FEL |
2414 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2415 | ||
fa89a817 | 2416 | ++vcpu->stat.irq_injections; |
ad312c7c | 2417 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
2418 | vmx->rmode.irq.pending = true; |
2419 | vmx->rmode.irq.vector = irq; | |
5fdbf976 | 2420 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
9c5623e3 AK |
2421 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2422 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2423 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
5fdbf976 | 2424 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2425 | return; |
2426 | } | |
2427 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2428 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
2429 | } | |
2430 | ||
f08864b4 SY |
2431 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2432 | { | |
66a5a347 JK |
2433 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2434 | ||
3b86cd99 JK |
2435 | if (!cpu_has_virtual_nmis()) { |
2436 | /* | |
2437 | * Tracking the NMI-blocked state in software is built upon | |
2438 | * finding the next open IRQ window. This, in turn, depends on | |
2439 | * well-behaving guests: They have to keep IRQs disabled at | |
2440 | * least as long as the NMI handler runs. Otherwise we may | |
2441 | * cause NMI nesting, maybe breaking the guest. But as this is | |
2442 | * highly unlikely, we can live with the residual risk. | |
2443 | */ | |
2444 | vmx->soft_vnmi_blocked = 1; | |
2445 | vmx->vnmi_blocked_time = 0; | |
2446 | } | |
2447 | ||
487b391d | 2448 | ++vcpu->stat.nmi_injections; |
66a5a347 JK |
2449 | if (vcpu->arch.rmode.active) { |
2450 | vmx->rmode.irq.pending = true; | |
2451 | vmx->rmode.irq.vector = NMI_VECTOR; | |
2452 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
2453 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2454 | NMI_VECTOR | INTR_TYPE_SOFT_INTR | | |
2455 | INTR_INFO_VALID_MASK); | |
2456 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
2457 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
2458 | return; | |
2459 | } | |
f08864b4 SY |
2460 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2461 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
2462 | } |
2463 | ||
33f089ca JK |
2464 | static void vmx_update_window_states(struct kvm_vcpu *vcpu) |
2465 | { | |
2466 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2467 | ||
2468 | vcpu->arch.nmi_window_open = | |
2469 | !(guest_intr & (GUEST_INTR_STATE_STI | | |
2470 | GUEST_INTR_STATE_MOV_SS | | |
2471 | GUEST_INTR_STATE_NMI)); | |
3b86cd99 JK |
2472 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
2473 | vcpu->arch.nmi_window_open = 0; | |
33f089ca JK |
2474 | |
2475 | vcpu->arch.interrupt_window_open = | |
2476 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2477 | !(guest_intr & (GUEST_INTR_STATE_STI | | |
2478 | GUEST_INTR_STATE_MOV_SS))); | |
2479 | } | |
2480 | ||
6aa8b732 AK |
2481 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
2482 | { | |
ad312c7c ZX |
2483 | int word_index = __ffs(vcpu->arch.irq_summary); |
2484 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
2485 | int irq = word_index * BITS_PER_LONG + bit_index; |
2486 | ||
ad312c7c ZX |
2487 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2488 | if (!vcpu->arch.irq_pending[word_index]) | |
2489 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
ecfc79c7 | 2490 | kvm_queue_interrupt(vcpu, irq); |
6aa8b732 AK |
2491 | } |
2492 | ||
f460ee43 JK |
2493 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
2494 | struct kvm_run *kvm_run) | |
2495 | { | |
2496 | vmx_update_window_states(vcpu); | |
2497 | ||
55934c0b JK |
2498 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
2499 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2500 | GUEST_INTR_STATE_STI | | |
2501 | GUEST_INTR_STATE_MOV_SS); | |
2502 | ||
3b86cd99 | 2503 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { |
264ff01d JK |
2504 | if (vcpu->arch.interrupt.pending) { |
2505 | enable_nmi_window(vcpu); | |
2506 | } else if (vcpu->arch.nmi_window_open) { | |
3b86cd99 JK |
2507 | vcpu->arch.nmi_pending = false; |
2508 | vcpu->arch.nmi_injected = true; | |
2509 | } else { | |
2510 | enable_nmi_window(vcpu); | |
487b391d JK |
2511 | return; |
2512 | } | |
3b86cd99 JK |
2513 | } |
2514 | if (vcpu->arch.nmi_injected) { | |
2515 | vmx_inject_nmi(vcpu); | |
4531220b | 2516 | if (vcpu->arch.nmi_pending) |
487b391d | 2517 | enable_nmi_window(vcpu); |
3b86cd99 JK |
2518 | else if (vcpu->arch.irq_summary |
2519 | || kvm_run->request_interrupt_window) | |
2520 | enable_irq_window(vcpu); | |
2521 | return; | |
487b391d JK |
2522 | } |
2523 | ||
f460ee43 JK |
2524 | if (vcpu->arch.interrupt_window_open) { |
2525 | if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending) | |
2526 | kvm_do_inject_irq(vcpu); | |
2527 | ||
2528 | if (vcpu->arch.interrupt.pending) | |
2529 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
2530 | } | |
ad312c7c ZX |
2531 | if (!vcpu->arch.interrupt_window_open && |
2532 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
f460ee43 | 2533 | enable_irq_window(vcpu); |
6aa8b732 AK |
2534 | } |
2535 | ||
cbc94022 IE |
2536 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2537 | { | |
2538 | int ret; | |
2539 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 2540 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
2541 | .guest_phys_addr = addr, |
2542 | .memory_size = PAGE_SIZE * 3, | |
2543 | .flags = 0, | |
2544 | }; | |
2545 | ||
2546 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2547 | if (ret) | |
2548 | return ret; | |
bfc6d222 | 2549 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2550 | return 0; |
2551 | } | |
2552 | ||
6aa8b732 AK |
2553 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, |
2554 | int vec, u32 err_code) | |
2555 | { | |
b3f37707 NK |
2556 | /* |
2557 | * Instruction with address size override prefix opcode 0x67 | |
2558 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2559 | */ | |
2560 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2561 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 | 2562 | return 1; |
77ab6db0 JK |
2563 | /* |
2564 | * Forward all other exceptions that are valid in real mode. | |
2565 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
2566 | * the required debugging infrastructure rework. | |
2567 | */ | |
2568 | switch (vec) { | |
77ab6db0 | 2569 | case DB_VECTOR: |
d0bfb940 JK |
2570 | if (vcpu->guest_debug & |
2571 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
2572 | return 0; | |
2573 | kvm_queue_exception(vcpu, vec); | |
2574 | return 1; | |
77ab6db0 | 2575 | case BP_VECTOR: |
d0bfb940 JK |
2576 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
2577 | return 0; | |
2578 | /* fall through */ | |
2579 | case DE_VECTOR: | |
77ab6db0 JK |
2580 | case OF_VECTOR: |
2581 | case BR_VECTOR: | |
2582 | case UD_VECTOR: | |
2583 | case DF_VECTOR: | |
2584 | case SS_VECTOR: | |
2585 | case GP_VECTOR: | |
2586 | case MF_VECTOR: | |
2587 | kvm_queue_exception(vcpu, vec); | |
2588 | return 1; | |
2589 | } | |
6aa8b732 AK |
2590 | return 0; |
2591 | } | |
2592 | ||
2593 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2594 | { | |
1155f76a | 2595 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d0bfb940 | 2596 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 2597 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
2598 | u32 vect_info; |
2599 | enum emulation_result er; | |
2600 | ||
1155f76a | 2601 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2602 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2603 | ||
2604 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2605 | !is_page_fault(intr_info)) |
6aa8b732 | 2606 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2607 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2608 | |
85f455f7 | 2609 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2610 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2611 | set_bit(irq, vcpu->arch.irq_pending); |
2612 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2613 | } |
2614 | ||
e4a41889 | 2615 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 2616 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
2617 | |
2618 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2619 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2620 | return 1; |
2621 | } | |
2622 | ||
7aa81cc0 | 2623 | if (is_invalid_opcode(intr_info)) { |
571008da | 2624 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2625 | if (er != EMULATE_DONE) |
7ee5d940 | 2626 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2627 | return 1; |
2628 | } | |
2629 | ||
6aa8b732 | 2630 | error_code = 0; |
5fdbf976 | 2631 | rip = kvm_rip_read(vcpu); |
2e11384c | 2632 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2633 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2634 | if (is_page_fault(intr_info)) { | |
1439442c SY |
2635 | /* EPT won't cause page fault directly */ |
2636 | if (vm_need_ept()) | |
2637 | BUG(); | |
6aa8b732 | 2638 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2714d1d3 FEL |
2639 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2640 | (u32)((u64)cr2 >> 32), handler); | |
f7d9238f | 2641 | if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending) |
577bdc49 | 2642 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
3067714c | 2643 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2644 | } |
2645 | ||
ad312c7c | 2646 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2647 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2648 | error_code)) { |
ad312c7c ZX |
2649 | if (vcpu->arch.halt_request) { |
2650 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2651 | return kvm_emulate_halt(vcpu); |
2652 | } | |
6aa8b732 | 2653 | return 1; |
72d6e5a0 | 2654 | } |
6aa8b732 | 2655 | |
d0bfb940 | 2656 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
42dbaa5a JK |
2657 | switch (ex_no) { |
2658 | case DB_VECTOR: | |
2659 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
2660 | if (!(vcpu->guest_debug & | |
2661 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
2662 | vcpu->arch.dr6 = dr6 | DR6_FIXED_1; | |
2663 | kvm_queue_exception(vcpu, DB_VECTOR); | |
2664 | return 1; | |
2665 | } | |
2666 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
2667 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
2668 | /* fall through */ | |
2669 | case BP_VECTOR: | |
6aa8b732 | 2670 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
d0bfb940 JK |
2671 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
2672 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
2673 | break; |
2674 | default: | |
d0bfb940 JK |
2675 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
2676 | kvm_run->ex.exception = ex_no; | |
2677 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 2678 | break; |
6aa8b732 | 2679 | } |
6aa8b732 AK |
2680 | return 0; |
2681 | } | |
2682 | ||
2683 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2684 | struct kvm_run *kvm_run) | |
2685 | { | |
1165f5fe | 2686 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2687 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2688 | return 1; |
2689 | } | |
2690 | ||
988ad74f AK |
2691 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2692 | { | |
2693 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2694 | return 0; | |
2695 | } | |
6aa8b732 | 2696 | |
6aa8b732 AK |
2697 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2698 | { | |
bfdaab09 | 2699 | unsigned long exit_qualification; |
039576c0 AK |
2700 | int size, down, in, string, rep; |
2701 | unsigned port; | |
6aa8b732 | 2702 | |
1165f5fe | 2703 | ++vcpu->stat.io_exits; |
bfdaab09 | 2704 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2705 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2706 | |
2707 | if (string) { | |
3427318f LV |
2708 | if (emulate_instruction(vcpu, |
2709 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2710 | return 0; |
2711 | return 1; | |
2712 | } | |
2713 | ||
2714 | size = (exit_qualification & 7) + 1; | |
2715 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2716 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2717 | rep = (exit_qualification & 32) != 0; |
2718 | port = exit_qualification >> 16; | |
e70669ab | 2719 | |
e93f36bc | 2720 | skip_emulated_instruction(vcpu); |
3090dd73 | 2721 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2722 | } |
2723 | ||
102d8325 IM |
2724 | static void |
2725 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2726 | { | |
2727 | /* | |
2728 | * Patch in the VMCALL instruction: | |
2729 | */ | |
2730 | hypercall[0] = 0x0f; | |
2731 | hypercall[1] = 0x01; | |
2732 | hypercall[2] = 0xc1; | |
102d8325 IM |
2733 | } |
2734 | ||
6aa8b732 AK |
2735 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2736 | { | |
bfdaab09 | 2737 | unsigned long exit_qualification; |
6aa8b732 AK |
2738 | int cr; |
2739 | int reg; | |
2740 | ||
bfdaab09 | 2741 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2742 | cr = exit_qualification & 15; |
2743 | reg = (exit_qualification >> 8) & 15; | |
2744 | switch ((exit_qualification >> 4) & 3) { | |
2745 | case 0: /* mov to cr */ | |
5fdbf976 MT |
2746 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, |
2747 | (u32)kvm_register_read(vcpu, reg), | |
2748 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2749 | handler); | |
6aa8b732 AK |
2750 | switch (cr) { |
2751 | case 0: | |
5fdbf976 | 2752 | kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2753 | skip_emulated_instruction(vcpu); |
2754 | return 1; | |
2755 | case 3: | |
5fdbf976 | 2756 | kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2757 | skip_emulated_instruction(vcpu); |
2758 | return 1; | |
2759 | case 4: | |
5fdbf976 | 2760 | kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2761 | skip_emulated_instruction(vcpu); |
2762 | return 1; | |
2763 | case 8: | |
5fdbf976 | 2764 | kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 | 2765 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2766 | if (irqchip_in_kernel(vcpu->kvm)) |
2767 | return 1; | |
253abdee YS |
2768 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2769 | return 0; | |
6aa8b732 AK |
2770 | }; |
2771 | break; | |
25c4c276 | 2772 | case 2: /* clts */ |
5fd86fcf | 2773 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2774 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2775 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2776 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2777 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2778 | skip_emulated_instruction(vcpu); |
2779 | return 1; | |
6aa8b732 AK |
2780 | case 1: /*mov from cr*/ |
2781 | switch (cr) { | |
2782 | case 3: | |
5fdbf976 | 2783 | kvm_register_write(vcpu, reg, vcpu->arch.cr3); |
2714d1d3 | 2784 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
5fdbf976 MT |
2785 | (u32)kvm_register_read(vcpu, reg), |
2786 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2714d1d3 | 2787 | handler); |
6aa8b732 AK |
2788 | skip_emulated_instruction(vcpu); |
2789 | return 1; | |
2790 | case 8: | |
5fdbf976 | 2791 | kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu)); |
2714d1d3 | 2792 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
5fdbf976 | 2793 | (u32)kvm_register_read(vcpu, reg), handler); |
6aa8b732 AK |
2794 | skip_emulated_instruction(vcpu); |
2795 | return 1; | |
2796 | } | |
2797 | break; | |
2798 | case 3: /* lmsw */ | |
2d3ad1f4 | 2799 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2800 | |
2801 | skip_emulated_instruction(vcpu); | |
2802 | return 1; | |
2803 | default: | |
2804 | break; | |
2805 | } | |
2806 | kvm_run->exit_reason = 0; | |
f0242478 | 2807 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2808 | (int)(exit_qualification >> 4) & 3, cr); |
2809 | return 0; | |
2810 | } | |
2811 | ||
2812 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2813 | { | |
bfdaab09 | 2814 | unsigned long exit_qualification; |
6aa8b732 AK |
2815 | unsigned long val; |
2816 | int dr, reg; | |
2817 | ||
42dbaa5a JK |
2818 | dr = vmcs_readl(GUEST_DR7); |
2819 | if (dr & DR7_GD) { | |
2820 | /* | |
2821 | * As the vm-exit takes precedence over the debug trap, we | |
2822 | * need to emulate the latter, either for the host or the | |
2823 | * guest debugging itself. | |
2824 | */ | |
2825 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
2826 | kvm_run->debug.arch.dr6 = vcpu->arch.dr6; | |
2827 | kvm_run->debug.arch.dr7 = dr; | |
2828 | kvm_run->debug.arch.pc = | |
2829 | vmcs_readl(GUEST_CS_BASE) + | |
2830 | vmcs_readl(GUEST_RIP); | |
2831 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2832 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
2833 | return 0; | |
2834 | } else { | |
2835 | vcpu->arch.dr7 &= ~DR7_GD; | |
2836 | vcpu->arch.dr6 |= DR6_BD; | |
2837 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
2838 | kvm_queue_exception(vcpu, DB_VECTOR); | |
2839 | return 1; | |
2840 | } | |
2841 | } | |
2842 | ||
bfdaab09 | 2843 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
42dbaa5a JK |
2844 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
2845 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); | |
2846 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
6aa8b732 | 2847 | switch (dr) { |
42dbaa5a JK |
2848 | case 0 ... 3: |
2849 | val = vcpu->arch.db[dr]; | |
2850 | break; | |
6aa8b732 | 2851 | case 6: |
42dbaa5a | 2852 | val = vcpu->arch.dr6; |
6aa8b732 AK |
2853 | break; |
2854 | case 7: | |
42dbaa5a | 2855 | val = vcpu->arch.dr7; |
6aa8b732 AK |
2856 | break; |
2857 | default: | |
2858 | val = 0; | |
2859 | } | |
5fdbf976 | 2860 | kvm_register_write(vcpu, reg, val); |
2714d1d3 | 2861 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 | 2862 | } else { |
42dbaa5a JK |
2863 | val = vcpu->arch.regs[reg]; |
2864 | switch (dr) { | |
2865 | case 0 ... 3: | |
2866 | vcpu->arch.db[dr] = val; | |
2867 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
2868 | vcpu->arch.eff_db[dr] = val; | |
2869 | break; | |
2870 | case 4 ... 5: | |
2871 | if (vcpu->arch.cr4 & X86_CR4_DE) | |
2872 | kvm_queue_exception(vcpu, UD_VECTOR); | |
2873 | break; | |
2874 | case 6: | |
2875 | if (val & 0xffffffff00000000ULL) { | |
2876 | kvm_queue_exception(vcpu, GP_VECTOR); | |
2877 | break; | |
2878 | } | |
2879 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; | |
2880 | break; | |
2881 | case 7: | |
2882 | if (val & 0xffffffff00000000ULL) { | |
2883 | kvm_queue_exception(vcpu, GP_VECTOR); | |
2884 | break; | |
2885 | } | |
2886 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; | |
2887 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
2888 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
2889 | vcpu->arch.switch_db_regs = | |
2890 | (val & DR7_BP_EN_MASK); | |
2891 | } | |
2892 | break; | |
2893 | } | |
2894 | KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler); | |
6aa8b732 | 2895 | } |
6aa8b732 AK |
2896 | skip_emulated_instruction(vcpu); |
2897 | return 1; | |
2898 | } | |
2899 | ||
2900 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2901 | { | |
06465c5a AK |
2902 | kvm_emulate_cpuid(vcpu); |
2903 | return 1; | |
6aa8b732 AK |
2904 | } |
2905 | ||
2906 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2907 | { | |
ad312c7c | 2908 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2909 | u64 data; |
2910 | ||
2911 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2912 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2913 | return 1; |
2914 | } | |
2915 | ||
2714d1d3 FEL |
2916 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2917 | handler); | |
2918 | ||
6aa8b732 | 2919 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2920 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2921 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2922 | skip_emulated_instruction(vcpu); |
2923 | return 1; | |
2924 | } | |
2925 | ||
2926 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2927 | { | |
ad312c7c ZX |
2928 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2929 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2930 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2931 | |
2714d1d3 FEL |
2932 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2933 | handler); | |
2934 | ||
6aa8b732 | 2935 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2936 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2937 | return 1; |
2938 | } | |
2939 | ||
2940 | skip_emulated_instruction(vcpu); | |
2941 | return 1; | |
2942 | } | |
2943 | ||
6e5d865c YS |
2944 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2945 | struct kvm_run *kvm_run) | |
2946 | { | |
2947 | return 1; | |
2948 | } | |
2949 | ||
6aa8b732 AK |
2950 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2951 | struct kvm_run *kvm_run) | |
2952 | { | |
85f455f7 ED |
2953 | u32 cpu_based_vm_exec_control; |
2954 | ||
2955 | /* clear pending irq */ | |
2956 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2957 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2958 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2959 | |
2960 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
a26bf12a | 2961 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 2962 | |
c1150d8c DL |
2963 | /* |
2964 | * If the user space waits to inject interrupts, exit as soon as | |
2965 | * possible | |
2966 | */ | |
2967 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2968 | !vcpu->arch.irq_summary) { |
c1150d8c | 2969 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
2970 | return 0; |
2971 | } | |
6aa8b732 AK |
2972 | return 1; |
2973 | } | |
2974 | ||
2975 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2976 | { | |
2977 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2978 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2979 | } |
2980 | ||
c21415e8 IM |
2981 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2982 | { | |
510043da | 2983 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2984 | kvm_emulate_hypercall(vcpu); |
2985 | return 1; | |
c21415e8 IM |
2986 | } |
2987 | ||
a7052897 MT |
2988 | static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2989 | { | |
2990 | u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2991 | ||
2992 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
2993 | skip_emulated_instruction(vcpu); | |
2994 | return 1; | |
2995 | } | |
2996 | ||
e5edaa01 ED |
2997 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2998 | { | |
2999 | skip_emulated_instruction(vcpu); | |
3000 | /* TODO: Add support for VT-d/pass-through device */ | |
3001 | return 1; | |
3002 | } | |
3003 | ||
f78e0e2e SY |
3004 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3005 | { | |
3006 | u64 exit_qualification; | |
3007 | enum emulation_result er; | |
3008 | unsigned long offset; | |
3009 | ||
3010 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
3011 | offset = exit_qualification & 0xffful; | |
3012 | ||
3013 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
3014 | ||
3015 | if (er != EMULATE_DONE) { | |
3016 | printk(KERN_ERR | |
3017 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
3018 | offset); | |
3019 | return -ENOTSUPP; | |
3020 | } | |
3021 | return 1; | |
3022 | } | |
3023 | ||
37817f29 IE |
3024 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3025 | { | |
60637aac | 3026 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 IE |
3027 | unsigned long exit_qualification; |
3028 | u16 tss_selector; | |
3029 | int reason; | |
3030 | ||
3031 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
3032 | ||
3033 | reason = (u32)exit_qualification >> 30; | |
60637aac JK |
3034 | if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected && |
3035 | (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
3036 | (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK) | |
3037 | == INTR_TYPE_NMI_INTR) { | |
3038 | vcpu->arch.nmi_injected = false; | |
3039 | if (cpu_has_virtual_nmis()) | |
3040 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3041 | GUEST_INTR_STATE_NMI); | |
3042 | } | |
37817f29 IE |
3043 | tss_selector = exit_qualification; |
3044 | ||
42dbaa5a JK |
3045 | if (!kvm_task_switch(vcpu, tss_selector, reason)) |
3046 | return 0; | |
3047 | ||
3048 | /* clear all local breakpoint enable flags */ | |
3049 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); | |
3050 | ||
3051 | /* | |
3052 | * TODO: What about debug traps on tss switch? | |
3053 | * Are we supposed to inject them and update dr6? | |
3054 | */ | |
3055 | ||
3056 | return 1; | |
37817f29 IE |
3057 | } |
3058 | ||
1439442c SY |
3059 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3060 | { | |
3061 | u64 exit_qualification; | |
3062 | enum emulation_result er; | |
3063 | gpa_t gpa; | |
3064 | unsigned long hva; | |
3065 | int gla_validity; | |
3066 | int r; | |
3067 | ||
3068 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
3069 | ||
3070 | if (exit_qualification & (1 << 6)) { | |
3071 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
3072 | return -ENOTSUPP; | |
3073 | } | |
3074 | ||
3075 | gla_validity = (exit_qualification >> 7) & 0x3; | |
3076 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
3077 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
3078 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
3079 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
3080 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
3081 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
3082 | (long unsigned int)exit_qualification); | |
3083 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
3084 | kvm_run->hw.hardware_exit_reason = 0; | |
3085 | return -ENOTSUPP; | |
3086 | } | |
3087 | ||
3088 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
3089 | hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT); | |
3090 | if (!kvm_is_error_hva(hva)) { | |
3091 | r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); | |
3092 | if (r < 0) { | |
3093 | printk(KERN_ERR "EPT: Not enough memory!\n"); | |
3094 | return -ENOMEM; | |
3095 | } | |
3096 | return 1; | |
3097 | } else { | |
3098 | /* must be MMIO */ | |
3099 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
3100 | ||
3101 | if (er == EMULATE_FAIL) { | |
3102 | printk(KERN_ERR | |
3103 | "EPT: Fail to handle EPT violation vmexit!er is %d\n", | |
3104 | er); | |
3105 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
3106 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
3107 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
3108 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
3109 | (long unsigned int)exit_qualification); | |
3110 | return -ENOTSUPP; | |
3111 | } else if (er == EMULATE_DO_MMIO) | |
3112 | return 0; | |
3113 | } | |
3114 | return 1; | |
3115 | } | |
3116 | ||
f08864b4 SY |
3117 | static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3118 | { | |
3119 | u32 cpu_based_vm_exec_control; | |
3120 | ||
3121 | /* clear pending NMI */ | |
3122 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3123 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
3124 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3125 | ++vcpu->stat.nmi_window_exits; | |
3126 | ||
3127 | return 1; | |
3128 | } | |
3129 | ||
ea953ef0 MG |
3130 | static void handle_invalid_guest_state(struct kvm_vcpu *vcpu, |
3131 | struct kvm_run *kvm_run) | |
3132 | { | |
ea953ef0 MG |
3133 | int err; |
3134 | ||
3135 | preempt_enable(); | |
3136 | local_irq_enable(); | |
3137 | ||
3138 | while (!guest_state_valid(vcpu)) { | |
3139 | err = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
3140 | ||
1d5a4d9b GT |
3141 | if (err == EMULATE_DO_MMIO) |
3142 | break; | |
3143 | ||
3144 | if (err != EMULATE_DONE) { | |
3145 | kvm_report_emulation_failure(vcpu, "emulation failure"); | |
3146 | return; | |
ea953ef0 MG |
3147 | } |
3148 | ||
3149 | if (signal_pending(current)) | |
3150 | break; | |
3151 | if (need_resched()) | |
3152 | schedule(); | |
3153 | } | |
3154 | ||
3155 | local_irq_disable(); | |
3156 | preempt_disable(); | |
ea953ef0 MG |
3157 | } |
3158 | ||
6aa8b732 AK |
3159 | /* |
3160 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
3161 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
3162 | * to be done to userspace and return 0. | |
3163 | */ | |
3164 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
3165 | struct kvm_run *kvm_run) = { | |
3166 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
3167 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 3168 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 3169 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 3170 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
3171 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
3172 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
3173 | [EXIT_REASON_CPUID] = handle_cpuid, | |
3174 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
3175 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
3176 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
3177 | [EXIT_REASON_HLT] = handle_halt, | |
a7052897 | 3178 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 3179 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
3180 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
3181 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 3182 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 3183 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
1439442c | 3184 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
6aa8b732 AK |
3185 | }; |
3186 | ||
3187 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 3188 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
3189 | |
3190 | /* | |
3191 | * The guest has exited. See if we can fix it or if we need userspace | |
3192 | * assistance. | |
3193 | */ | |
3194 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
3195 | { | |
6aa8b732 | 3196 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 3197 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 3198 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 3199 | |
5fdbf976 MT |
3200 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu), |
3201 | (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit); | |
2714d1d3 | 3202 | |
1d5a4d9b GT |
3203 | /* If we need to emulate an MMIO from handle_invalid_guest_state |
3204 | * we just return 0 */ | |
10f32d84 AK |
3205 | if (vmx->emulation_required && emulate_invalid_guest_state) { |
3206 | if (guest_state_valid(vcpu)) | |
3207 | vmx->emulation_required = 0; | |
1d5a4d9b | 3208 | return 0; |
10f32d84 | 3209 | } |
1d5a4d9b | 3210 | |
1439442c SY |
3211 | /* Access CR3 don't cause VMExit in paging mode, so we need |
3212 | * to sync with guest real CR3. */ | |
3213 | if (vm_need_ept() && is_paging(vcpu)) { | |
3214 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3215 | ept_load_pdptrs(vcpu); | |
3216 | } | |
3217 | ||
29bd8a78 AK |
3218 | if (unlikely(vmx->fail)) { |
3219 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3220 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3221 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
3222 | return 0; | |
3223 | } | |
6aa8b732 | 3224 | |
d77c26fc | 3225 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 3226 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
3227 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
3228 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
3229 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
3230 | "(0x%x) and exit reason is 0x%x\n", | |
3231 | __func__, vectoring_info, exit_reason); | |
3b86cd99 JK |
3232 | |
3233 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | |
3234 | if (vcpu->arch.interrupt_window_open) { | |
3235 | vmx->soft_vnmi_blocked = 0; | |
3236 | vcpu->arch.nmi_window_open = 1; | |
3237 | } else if (vmx->vnmi_blocked_time > 1000000000LL && | |
4531220b | 3238 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
3239 | /* |
3240 | * This CPU don't support us in finding the end of an | |
3241 | * NMI-blocked window if the guest runs with IRQs | |
3242 | * disabled. So we pull the trigger after 1 s of | |
3243 | * futile waiting, but inform the user about this. | |
3244 | */ | |
3245 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
3246 | "state on VCPU %d after 1 s timeout\n", | |
3247 | __func__, vcpu->vcpu_id); | |
3248 | vmx->soft_vnmi_blocked = 0; | |
3249 | vmx->vcpu.arch.nmi_window_open = 1; | |
3250 | } | |
3b86cd99 JK |
3251 | } |
3252 | ||
6aa8b732 AK |
3253 | if (exit_reason < kvm_vmx_max_exit_handlers |
3254 | && kvm_vmx_exit_handlers[exit_reason]) | |
3255 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
3256 | else { | |
3257 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
3258 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
3259 | } | |
3260 | return 0; | |
3261 | } | |
3262 | ||
6e5d865c YS |
3263 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
3264 | { | |
3265 | int max_irr, tpr; | |
3266 | ||
3267 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
3268 | return; | |
3269 | ||
3270 | if (!kvm_lapic_enabled(vcpu) || | |
3271 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
3272 | vmcs_write32(TPR_THRESHOLD, 0); | |
3273 | return; | |
3274 | } | |
3275 | ||
3276 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
3277 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
3278 | } | |
3279 | ||
cf393f75 AK |
3280 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3281 | { | |
3282 | u32 exit_intr_info; | |
668f612f | 3283 | u32 idt_vectoring_info; |
cf393f75 AK |
3284 | bool unblock_nmi; |
3285 | u8 vector; | |
668f612f AK |
3286 | int type; |
3287 | bool idtv_info_valid; | |
35920a35 | 3288 | u32 error; |
cf393f75 AK |
3289 | |
3290 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3291 | if (cpu_has_virtual_nmis()) { | |
3292 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
3293 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
3294 | /* | |
3295 | * SDM 3: 25.7.1.2 | |
3296 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
3297 | * a guest IRET fault. | |
3298 | */ | |
3299 | if (unblock_nmi && vector != DF_VECTOR) | |
3300 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3301 | GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
3302 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
3303 | vmx->vnmi_blocked_time += | |
3304 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
668f612f AK |
3305 | |
3306 | idt_vectoring_info = vmx->idt_vectoring_info; | |
3307 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
3308 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; | |
3309 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
3310 | if (vmx->vcpu.arch.nmi_injected) { | |
3311 | /* | |
3312 | * SDM 3: 25.7.1.2 | |
3313 | * Clear bit "block by NMI" before VM entry if a NMI delivery | |
3314 | * faulted. | |
3315 | */ | |
3316 | if (idtv_info_valid && type == INTR_TYPE_NMI_INTR) | |
3317 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3318 | GUEST_INTR_STATE_NMI); | |
3319 | else | |
3320 | vmx->vcpu.arch.nmi_injected = false; | |
3321 | } | |
35920a35 | 3322 | kvm_clear_exception_queue(&vmx->vcpu); |
8ab2d2e2 JK |
3323 | if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION || |
3324 | type == INTR_TYPE_SOFT_EXCEPTION)) { | |
35920a35 AK |
3325 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
3326 | error = vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
3327 | kvm_queue_exception_e(&vmx->vcpu, vector, error); | |
3328 | } else | |
3329 | kvm_queue_exception(&vmx->vcpu, vector); | |
3330 | vmx->idt_vectoring_info = 0; | |
3331 | } | |
f7d9238f AK |
3332 | kvm_clear_interrupt_queue(&vmx->vcpu); |
3333 | if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) { | |
3334 | kvm_queue_interrupt(&vmx->vcpu, vector); | |
3335 | vmx->idt_vectoring_info = 0; | |
3336 | } | |
cf393f75 AK |
3337 | } |
3338 | ||
85f455f7 ED |
3339 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) |
3340 | { | |
6e5d865c YS |
3341 | update_tpr_threshold(vcpu); |
3342 | ||
33f089ca JK |
3343 | vmx_update_window_states(vcpu); |
3344 | ||
55934c0b JK |
3345 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
3346 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3347 | GUEST_INTR_STATE_STI | | |
3348 | GUEST_INTR_STATE_MOV_SS); | |
3349 | ||
3b86cd99 JK |
3350 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { |
3351 | if (vcpu->arch.interrupt.pending) { | |
3352 | enable_nmi_window(vcpu); | |
3353 | } else if (vcpu->arch.nmi_window_open) { | |
3354 | vcpu->arch.nmi_pending = false; | |
3355 | vcpu->arch.nmi_injected = true; | |
3356 | } else { | |
3357 | enable_nmi_window(vcpu); | |
f08864b4 SY |
3358 | return; |
3359 | } | |
f08864b4 | 3360 | } |
3b86cd99 JK |
3361 | if (vcpu->arch.nmi_injected) { |
3362 | vmx_inject_nmi(vcpu); | |
3363 | if (vcpu->arch.nmi_pending) | |
3364 | enable_nmi_window(vcpu); | |
3365 | else if (kvm_cpu_has_interrupt(vcpu)) | |
3366 | enable_irq_window(vcpu); | |
3367 | return; | |
3368 | } | |
f7d9238f | 3369 | if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) { |
33f089ca | 3370 | if (vcpu->arch.interrupt_window_open) |
f7d9238f AK |
3371 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu)); |
3372 | else | |
3373 | enable_irq_window(vcpu); | |
3374 | } | |
3375 | if (vcpu->arch.interrupt.pending) { | |
3376 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
df203ec9 AK |
3377 | if (kvm_cpu_has_interrupt(vcpu)) |
3378 | enable_irq_window(vcpu); | |
f7d9238f | 3379 | } |
85f455f7 ED |
3380 | } |
3381 | ||
9c8cba37 AK |
3382 | /* |
3383 | * Failure to inject an interrupt should give us the information | |
3384 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
3385 | * when fetching the interrupt redirection bitmap in the real-mode | |
3386 | * tss, this doesn't happen. So we do it ourselves. | |
3387 | */ | |
3388 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
3389 | { | |
3390 | vmx->rmode.irq.pending = 0; | |
5fdbf976 | 3391 | if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip) |
9c8cba37 | 3392 | return; |
5fdbf976 | 3393 | kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip); |
9c8cba37 AK |
3394 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { |
3395 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
3396 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
3397 | return; | |
3398 | } | |
3399 | vmx->idt_vectoring_info = | |
3400 | VECTORING_INFO_VALID_MASK | |
3401 | | INTR_TYPE_EXT_INTR | |
3402 | | vmx->rmode.irq.vector; | |
3403 | } | |
3404 | ||
c801949d AK |
3405 | #ifdef CONFIG_X86_64 |
3406 | #define R "r" | |
3407 | #define Q "q" | |
3408 | #else | |
3409 | #define R "e" | |
3410 | #define Q "l" | |
3411 | #endif | |
3412 | ||
04d2cc77 | 3413 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 3414 | { |
a2fa3e9f | 3415 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 3416 | u32 intr_info; |
e6adf283 | 3417 | |
3b86cd99 JK |
3418 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
3419 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
3420 | vmx->entry_time = ktime_get(); | |
3421 | ||
a89a8fb9 MG |
3422 | /* Handle invalid guest state instead of entering VMX */ |
3423 | if (vmx->emulation_required && emulate_invalid_guest_state) { | |
3424 | handle_invalid_guest_state(vcpu, kvm_run); | |
3425 | return; | |
3426 | } | |
3427 | ||
5fdbf976 MT |
3428 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
3429 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
3430 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
3431 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
3432 | ||
e6adf283 AK |
3433 | /* |
3434 | * Loading guest fpu may have cleared host cr0.ts | |
3435 | */ | |
3436 | vmcs_writel(HOST_CR0, read_cr0()); | |
3437 | ||
42dbaa5a JK |
3438 | set_debugreg(vcpu->arch.dr6, 6); |
3439 | ||
d77c26fc | 3440 | asm( |
6aa8b732 | 3441 | /* Store host registers */ |
c801949d AK |
3442 | "push %%"R"dx; push %%"R"bp;" |
3443 | "push %%"R"cx \n\t" | |
313dbd49 AK |
3444 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
3445 | "je 1f \n\t" | |
3446 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 3447 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 3448 | "1: \n\t" |
6aa8b732 | 3449 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 3450 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 3451 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
3452 | "mov %c[cr2](%0), %%"R"ax \n\t" |
3453 | "mov %%"R"ax, %%cr2 \n\t" | |
3454 | "mov %c[rax](%0), %%"R"ax \n\t" | |
3455 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
3456 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
3457 | "mov %c[rsi](%0), %%"R"si \n\t" | |
3458 | "mov %c[rdi](%0), %%"R"di \n\t" | |
3459 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 3460 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3461 | "mov %c[r8](%0), %%r8 \n\t" |
3462 | "mov %c[r9](%0), %%r9 \n\t" | |
3463 | "mov %c[r10](%0), %%r10 \n\t" | |
3464 | "mov %c[r11](%0), %%r11 \n\t" | |
3465 | "mov %c[r12](%0), %%r12 \n\t" | |
3466 | "mov %c[r13](%0), %%r13 \n\t" | |
3467 | "mov %c[r14](%0), %%r14 \n\t" | |
3468 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 3469 | #endif |
c801949d AK |
3470 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
3471 | ||
6aa8b732 | 3472 | /* Enter guest mode */ |
cd2276a7 | 3473 | "jne .Llaunched \n\t" |
4ecac3fd | 3474 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 3475 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 3476 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 3477 | ".Lkvm_vmx_return: " |
6aa8b732 | 3478 | /* Save guest registers, load host registers, keep flags */ |
c801949d AK |
3479 | "xchg %0, (%%"R"sp) \n\t" |
3480 | "mov %%"R"ax, %c[rax](%0) \n\t" | |
3481 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
3482 | "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t" | |
3483 | "mov %%"R"dx, %c[rdx](%0) \n\t" | |
3484 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
3485 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
3486 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 3487 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3488 | "mov %%r8, %c[r8](%0) \n\t" |
3489 | "mov %%r9, %c[r9](%0) \n\t" | |
3490 | "mov %%r10, %c[r10](%0) \n\t" | |
3491 | "mov %%r11, %c[r11](%0) \n\t" | |
3492 | "mov %%r12, %c[r12](%0) \n\t" | |
3493 | "mov %%r13, %c[r13](%0) \n\t" | |
3494 | "mov %%r14, %c[r14](%0) \n\t" | |
3495 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 3496 | #endif |
c801949d AK |
3497 | "mov %%cr2, %%"R"ax \n\t" |
3498 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
3499 | ||
3500 | "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t" | |
e08aa78a AK |
3501 | "setbe %c[fail](%0) \n\t" |
3502 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
3503 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
3504 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 3505 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
3506 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
3507 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3508 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3509 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3510 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3511 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3512 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 3513 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3514 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
3515 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
3516 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
3517 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
3518 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
3519 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
3520 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
3521 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 3522 | #endif |
ad312c7c | 3523 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 | 3524 | : "cc", "memory" |
c801949d | 3525 | , R"bx", R"di", R"si" |
c2036300 | 3526 | #ifdef CONFIG_X86_64 |
c2036300 LV |
3527 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
3528 | #endif | |
3529 | ); | |
6aa8b732 | 3530 | |
5fdbf976 MT |
3531 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3532 | vcpu->arch.regs_dirty = 0; | |
3533 | ||
42dbaa5a JK |
3534 | get_debugreg(vcpu->arch.dr6, 6); |
3535 | ||
1155f76a | 3536 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
3537 | if (vmx->rmode.irq.pending) |
3538 | fixup_rmode_irq(vmx); | |
1155f76a | 3539 | |
33f089ca | 3540 | vmx_update_window_states(vcpu); |
6aa8b732 | 3541 | |
d77c26fc | 3542 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 3543 | vmx->launched = 1; |
1b6269db AK |
3544 | |
3545 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3546 | ||
3547 | /* We need to handle NMIs before interrupts are enabled */ | |
e4a41889 | 3548 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
f08864b4 | 3549 | (intr_info & INTR_INFO_VALID_MASK)) { |
2714d1d3 | 3550 | KVMTRACE_0D(NMI, vcpu, handler); |
1b6269db | 3551 | asm("int $2"); |
2714d1d3 | 3552 | } |
cf393f75 AK |
3553 | |
3554 | vmx_complete_interrupts(vmx); | |
6aa8b732 AK |
3555 | } |
3556 | ||
c801949d AK |
3557 | #undef R |
3558 | #undef Q | |
3559 | ||
6aa8b732 AK |
3560 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
3561 | { | |
a2fa3e9f GH |
3562 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3563 | ||
3564 | if (vmx->vmcs) { | |
543e4243 | 3565 | vcpu_clear(vmx); |
a2fa3e9f GH |
3566 | free_vmcs(vmx->vmcs); |
3567 | vmx->vmcs = NULL; | |
6aa8b732 AK |
3568 | } |
3569 | } | |
3570 | ||
3571 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
3572 | { | |
fb3f0f51 RR |
3573 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3574 | ||
2384d2b3 SY |
3575 | spin_lock(&vmx_vpid_lock); |
3576 | if (vmx->vpid != 0) | |
3577 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3578 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 3579 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
3580 | kfree(vmx->host_msrs); |
3581 | kfree(vmx->guest_msrs); | |
3582 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 3583 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
3584 | } |
3585 | ||
fb3f0f51 | 3586 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 3587 | { |
fb3f0f51 | 3588 | int err; |
c16f862d | 3589 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 3590 | int cpu; |
6aa8b732 | 3591 | |
a2fa3e9f | 3592 | if (!vmx) |
fb3f0f51 RR |
3593 | return ERR_PTR(-ENOMEM); |
3594 | ||
2384d2b3 SY |
3595 | allocate_vpid(vmx); |
3596 | ||
fb3f0f51 RR |
3597 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3598 | if (err) | |
3599 | goto free_vcpu; | |
965b58a5 | 3600 | |
a2fa3e9f | 3601 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3602 | if (!vmx->guest_msrs) { |
3603 | err = -ENOMEM; | |
3604 | goto uninit_vcpu; | |
3605 | } | |
965b58a5 | 3606 | |
a2fa3e9f GH |
3607 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
3608 | if (!vmx->host_msrs) | |
fb3f0f51 | 3609 | goto free_guest_msrs; |
965b58a5 | 3610 | |
a2fa3e9f GH |
3611 | vmx->vmcs = alloc_vmcs(); |
3612 | if (!vmx->vmcs) | |
fb3f0f51 | 3613 | goto free_msrs; |
a2fa3e9f GH |
3614 | |
3615 | vmcs_clear(vmx->vmcs); | |
3616 | ||
15ad7146 AK |
3617 | cpu = get_cpu(); |
3618 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3619 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3620 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3621 | put_cpu(); |
fb3f0f51 RR |
3622 | if (err) |
3623 | goto free_vmcs; | |
5e4a0b3c MT |
3624 | if (vm_need_virtualize_apic_accesses(kvm)) |
3625 | if (alloc_apic_access_page(kvm) != 0) | |
3626 | goto free_vmcs; | |
fb3f0f51 | 3627 | |
b7ebfb05 SY |
3628 | if (vm_need_ept()) |
3629 | if (alloc_identity_pagetable(kvm) != 0) | |
3630 | goto free_vmcs; | |
3631 | ||
fb3f0f51 RR |
3632 | return &vmx->vcpu; |
3633 | ||
3634 | free_vmcs: | |
3635 | free_vmcs(vmx->vmcs); | |
3636 | free_msrs: | |
3637 | kfree(vmx->host_msrs); | |
3638 | free_guest_msrs: | |
3639 | kfree(vmx->guest_msrs); | |
3640 | uninit_vcpu: | |
3641 | kvm_vcpu_uninit(&vmx->vcpu); | |
3642 | free_vcpu: | |
a4770347 | 3643 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3644 | return ERR_PTR(err); |
6aa8b732 AK |
3645 | } |
3646 | ||
002c7f7c YS |
3647 | static void __init vmx_check_processor_compat(void *rtn) |
3648 | { | |
3649 | struct vmcs_config vmcs_conf; | |
3650 | ||
3651 | *(int *)rtn = 0; | |
3652 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3653 | *(int *)rtn = -EIO; | |
3654 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3655 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3656 | smp_processor_id()); | |
3657 | *(int *)rtn = -EIO; | |
3658 | } | |
3659 | } | |
3660 | ||
67253af5 SY |
3661 | static int get_ept_level(void) |
3662 | { | |
3663 | return VMX_EPT_DEFAULT_GAW + 1; | |
3664 | } | |
3665 | ||
64d4d521 SY |
3666 | static int vmx_get_mt_mask_shift(void) |
3667 | { | |
3668 | return VMX_EPT_MT_EPTE_SHIFT; | |
3669 | } | |
3670 | ||
cbdd1bea | 3671 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
3672 | .cpu_has_kvm_support = cpu_has_kvm_support, |
3673 | .disabled_by_bios = vmx_disabled_by_bios, | |
3674 | .hardware_setup = hardware_setup, | |
3675 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 3676 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
3677 | .hardware_enable = hardware_enable, |
3678 | .hardware_disable = hardware_disable, | |
774ead3a | 3679 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
3680 | |
3681 | .vcpu_create = vmx_create_vcpu, | |
3682 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 3683 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 3684 | |
04d2cc77 | 3685 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
3686 | .vcpu_load = vmx_vcpu_load, |
3687 | .vcpu_put = vmx_vcpu_put, | |
3688 | ||
3689 | .set_guest_debug = set_guest_debug, | |
3690 | .get_msr = vmx_get_msr, | |
3691 | .set_msr = vmx_set_msr, | |
3692 | .get_segment_base = vmx_get_segment_base, | |
3693 | .get_segment = vmx_get_segment, | |
3694 | .set_segment = vmx_set_segment, | |
2e4d2653 | 3695 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 3696 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 3697 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 3698 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
3699 | .set_cr3 = vmx_set_cr3, |
3700 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 3701 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
3702 | .get_idt = vmx_get_idt, |
3703 | .set_idt = vmx_set_idt, | |
3704 | .get_gdt = vmx_get_gdt, | |
3705 | .set_gdt = vmx_set_gdt, | |
5fdbf976 | 3706 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
3707 | .get_rflags = vmx_get_rflags, |
3708 | .set_rflags = vmx_set_rflags, | |
3709 | ||
3710 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 3711 | |
6aa8b732 | 3712 | .run = vmx_vcpu_run, |
04d2cc77 | 3713 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 3714 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 3715 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
3716 | .get_irq = vmx_get_irq, |
3717 | .set_irq = vmx_inject_irq, | |
298101da AK |
3718 | .queue_exception = vmx_queue_exception, |
3719 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
3720 | .inject_pending_irq = vmx_intr_assist, |
3721 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
3722 | |
3723 | .set_tss_addr = vmx_set_tss_addr, | |
67253af5 | 3724 | .get_tdp_level = get_ept_level, |
64d4d521 | 3725 | .get_mt_mask_shift = vmx_get_mt_mask_shift, |
6aa8b732 AK |
3726 | }; |
3727 | ||
3728 | static int __init vmx_init(void) | |
3729 | { | |
25c5f225 | 3730 | void *va; |
fdef3ad1 HQ |
3731 | int r; |
3732 | ||
3733 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3734 | if (!vmx_io_bitmap_a) | |
3735 | return -ENOMEM; | |
3736 | ||
3737 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3738 | if (!vmx_io_bitmap_b) { | |
3739 | r = -ENOMEM; | |
3740 | goto out; | |
3741 | } | |
3742 | ||
25c5f225 SY |
3743 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
3744 | if (!vmx_msr_bitmap) { | |
3745 | r = -ENOMEM; | |
3746 | goto out1; | |
3747 | } | |
3748 | ||
fdef3ad1 HQ |
3749 | /* |
3750 | * Allow direct access to the PC debug port (it is often used for I/O | |
3751 | * delays, but the vmexits simply slow things down). | |
3752 | */ | |
25c5f225 SY |
3753 | va = kmap(vmx_io_bitmap_a); |
3754 | memset(va, 0xff, PAGE_SIZE); | |
3755 | clear_bit(0x80, va); | |
cd0536d7 | 3756 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 3757 | |
25c5f225 SY |
3758 | va = kmap(vmx_io_bitmap_b); |
3759 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 3760 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 3761 | |
25c5f225 SY |
3762 | va = kmap(vmx_msr_bitmap); |
3763 | memset(va, 0xff, PAGE_SIZE); | |
3764 | kunmap(vmx_msr_bitmap); | |
3765 | ||
2384d2b3 SY |
3766 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3767 | ||
cb498ea2 | 3768 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 3769 | if (r) |
25c5f225 SY |
3770 | goto out2; |
3771 | ||
3772 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
3773 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
3774 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
3775 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
3776 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 3777 | |
5fdbcb9d | 3778 | if (vm_need_ept()) { |
1439442c | 3779 | bypass_guest_pf = 0; |
5fdbcb9d | 3780 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
2aaf69dc | 3781 | VMX_EPT_WRITABLE_MASK); |
534e38b4 | 3782 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
64d4d521 SY |
3783 | VMX_EPT_EXECUTABLE_MASK, |
3784 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); | |
5fdbcb9d SY |
3785 | kvm_enable_tdp(); |
3786 | } else | |
3787 | kvm_disable_tdp(); | |
1439442c | 3788 | |
c7addb90 AK |
3789 | if (bypass_guest_pf) |
3790 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
3791 | ||
1439442c SY |
3792 | ept_sync_global(); |
3793 | ||
fdef3ad1 HQ |
3794 | return 0; |
3795 | ||
25c5f225 SY |
3796 | out2: |
3797 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
3798 | out1: |
3799 | __free_page(vmx_io_bitmap_b); | |
3800 | out: | |
3801 | __free_page(vmx_io_bitmap_a); | |
3802 | return r; | |
6aa8b732 AK |
3803 | } |
3804 | ||
3805 | static void __exit vmx_exit(void) | |
3806 | { | |
25c5f225 | 3807 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
3808 | __free_page(vmx_io_bitmap_b); |
3809 | __free_page(vmx_io_bitmap_a); | |
3810 | ||
cb498ea2 | 3811 | kvm_exit(); |
6aa8b732 AK |
3812 | } |
3813 | ||
3814 | module_init(vmx_init) | |
3815 | module_exit(vmx_exit) |