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KVM: Wake up waitqueue before calling get_cpu()
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
6aa8b732 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
4462d21a 41static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 42module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 43
4462d21a 44static int __read_mostly enable_vpid = 1;
736caefe 45module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 46
4462d21a 47static int __read_mostly flexpriority_enabled = 1;
736caefe 48module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 49
4462d21a 50static int __read_mostly enable_ept = 1;
736caefe 51module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 52
4462d21a 53static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 54module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 55
a2fa3e9f
GH		 56struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60};
61
62struct vcpu_vmx {
fb3f0f51 63 struct kvm_vcpu vcpu;
543e4243 64 struct list_head local_vcpus_link;
313dbd49 65 unsigned long host_rsp;
a2fa3e9f 66 int launched;
29bd8a78 67 u8 fail;
1155f76a 68 u32 idt_vectoring_info;
a2fa3e9f
GH		 69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74#ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76#endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
51c6cf66 83 int guest_efer_loaded;
d77c26fc 84 } host_state;
9c8cba37
AK		 85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
2384d2b3 92 int vpid;
04fa4d32 93 bool emulation_required;
8b3079a5 94 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 95
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked;
98 ktime_t entry_time;
99 s64 vnmi_blocked_time;
a2fa3e9f
GH		 100};
101
102static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103{
fb3f0f51 104 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 105}
106
b7ebfb05 107static int init_rmode(struct kvm *kvm);
4e1096d2 108static u64 construct_eptp(unsigned long root_hpa);
75880a01 109
6aa8b732
AK		 110static DEFINE_PER_CPU(struct vmcs *, vmxarea);
111static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 112static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 113
3e7c73e9
AK		 114static unsigned long *vmx_io_bitmap_a;
115static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 116static unsigned long *vmx_msr_bitmap_legacy;
117static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 118
2384d2b3
SY		 119static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
120static DEFINE_SPINLOCK(vmx_vpid_lock);
121
1c3d14fe 122static struct vmcs_config {
6aa8b732
AK		 123 int size;
124 int order;
125 u32 revision_id;
1c3d14fe
YS		 126 u32 pin_based_exec_ctrl;
127 u32 cpu_based_exec_ctrl;
f78e0e2e 128 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 129 u32 vmexit_ctrl;
130 u32 vmentry_ctrl;
131} vmcs_config;
6aa8b732 132
efff9e53 133static struct vmx_capability {
d56f546d
SY		 134 u32 ept;
135 u32 vpid;
136} vmx_capability;
137
6aa8b732
AK		 138#define VMX_SEGMENT_FIELD(seg) \
139 [VCPU_SREG_##seg] = { \
140 .selector = GUEST_##seg##_SELECTOR, \
141 .base = GUEST_##seg##_BASE, \
142 .limit = GUEST_##seg##_LIMIT, \
143 .ar_bytes = GUEST_##seg##_AR_BYTES, \
144 }
145
146static struct kvm_vmx_segment_field {
147 unsigned selector;
148 unsigned base;
149 unsigned limit;
150 unsigned ar_bytes;
151} kvm_vmx_segment_fields[] = {
152 VMX_SEGMENT_FIELD(CS),
153 VMX_SEGMENT_FIELD(DS),
154 VMX_SEGMENT_FIELD(ES),
155 VMX_SEGMENT_FIELD(FS),
156 VMX_SEGMENT_FIELD(GS),
157 VMX_SEGMENT_FIELD(SS),
158 VMX_SEGMENT_FIELD(TR),
159 VMX_SEGMENT_FIELD(LDTR),
160};
161
4d56c8a7
AK		 162/*
163 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
164 * away by decrementing the array size.
165 */
6aa8b732 166static const u32 vmx_msr_index[] = {
05b3e0c2 167#ifdef CONFIG_X86_64
6aa8b732
AK		 168 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
169#endif
170 MSR_EFER, MSR_K6_STAR,
171};
9d8f549d 172#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 173
a2fa3e9f
GH		 174static void load_msrs(struct kvm_msr_entry *e, int n)
175{
176 int i;
177
178 for (i = 0; i < n; ++i)
179 wrmsrl(e[i].index, e[i].data);
180}
181
182static void save_msrs(struct kvm_msr_entry *e, int n)
183{
184 int i;
185
186 for (i = 0; i < n; ++i)
187 rdmsrl(e[i].index, e[i].data);
188}
189
6aa8b732
AK		 190static inline int is_page_fault(u32 intr_info)
191{
192 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
193 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 194 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 195}
196
2ab455cc
AL		 197static inline int is_no_device(u32 intr_info)
198{
199 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
200 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 201 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 202}
203
7aa81cc0
AL		 204static inline int is_invalid_opcode(u32 intr_info)
205{
206 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
207 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 208 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 209}
210
6aa8b732
AK		 211static inline int is_external_interrupt(u32 intr_info)
212{
213 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
214 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
215}
216
25c5f225
SY		 217static inline int cpu_has_vmx_msr_bitmap(void)
218{
04547156 219 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 220}
221
6e5d865c
YS		 222static inline int cpu_has_vmx_tpr_shadow(void)
223{
04547156 224 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 225}
226
227static inline int vm_need_tpr_shadow(struct kvm *kvm)
228{
04547156 229 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 230}
231
f78e0e2e
SY		 232static inline int cpu_has_secondary_exec_ctrls(void)
233{
04547156
SY		 234 return vmcs_config.cpu_based_exec_ctrl &
235 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 236}
237
774ead3a 238static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 239{
04547156
SY		 240 return vmcs_config.cpu_based_2nd_exec_ctrl &
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
242}
243
244static inline bool cpu_has_vmx_flexpriority(void)
245{
246 return cpu_has_vmx_tpr_shadow() &&
247 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 248}
249
d56f546d
SY		 250static inline int cpu_has_vmx_invept_individual_addr(void)
251{
04547156 252 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 253}
254
255static inline int cpu_has_vmx_invept_context(void)
256{
04547156 257 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 258}
259
260static inline int cpu_has_vmx_invept_global(void)
261{
04547156 262 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 263}
264
265static inline int cpu_has_vmx_ept(void)
266{
04547156
SY		 267 return vmcs_config.cpu_based_2nd_exec_ctrl &
268 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 269}
270
f78e0e2e
SY		 271static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
272{
04547156
SY		 273 return flexpriority_enabled &&
274 (cpu_has_vmx_virtualize_apic_accesses()) &&
275 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 276}
277
2384d2b3
SY		 278static inline int cpu_has_vmx_vpid(void)
279{
04547156
SY		 280 return vmcs_config.cpu_based_2nd_exec_ctrl &
281 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 282}
283
f08864b4
SY		 284static inline int cpu_has_virtual_nmis(void)
285{
286 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
287}
288
04547156
SY		 289static inline bool report_flexpriority(void)
290{
291 return flexpriority_enabled;
292}
293
8b9cf98c 294static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 295{
296 int i;
297
a2fa3e9f
GH		 298 for (i = 0; i < vmx->nmsrs; ++i)
299 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 300 return i;
301 return -1;
302}
303
2384d2b3
SY		 304static inline void __invvpid(int ext, u16 vpid, gva_t gva)
305{
306 struct {
307 u64 vpid : 16;
308 u64 rsvd : 48;
309 u64 gva;
310 } operand = { vpid, 0, gva };
311
4ecac3fd 312 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 313 /* CF==1 or ZF==1 --> rc = -1 */
314 "; ja 1f ; ud2 ; 1:"
315 : : "a"(&operand), "c"(ext) : "cc", "memory");
316}
317
1439442c
SY		 318static inline void __invept(int ext, u64 eptp, gpa_t gpa)
319{
320 struct {
321 u64 eptp, gpa;
322 } operand = {eptp, gpa};
323
4ecac3fd 324 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 325 /* CF==1 or ZF==1 --> rc = -1 */
326 "; ja 1f ; ud2 ; 1:\n"
327 : : "a" (&operand), "c" (ext) : "cc", "memory");
328}
329
8b9cf98c 330static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 331{
332 int i;
333
8b9cf98c 334 i = __find_msr_index(vmx, msr);
a75beee6 335 if (i >= 0)
a2fa3e9f 336 return &vmx->guest_msrs[i];
8b6d44c7 337 return NULL;
7725f0ba
AK		 338}
339
6aa8b732
AK		 340static void vmcs_clear(struct vmcs *vmcs)
341{
342 u64 phys_addr = __pa(vmcs);
343 u8 error;
344
4ecac3fd 345 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 346 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
347 : "cc", "memory");
348 if (error)
349 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
350 vmcs, phys_addr);
351}
352
353static void __vcpu_clear(void *arg)
354{
8b9cf98c 355 struct vcpu_vmx *vmx = arg;
d3b2c338 356 int cpu = raw_smp_processor_id();
6aa8b732 357
8b9cf98c 358 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 359 vmcs_clear(vmx->vmcs);
360 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 361 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 362 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 363 list_del(&vmx->local_vcpus_link);
364 vmx->vcpu.cpu = -1;
365 vmx->launched = 0;
6aa8b732
AK		 366}
367
8b9cf98c 368static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 369{
eae5ecb5
AK		 370 if (vmx->vcpu.cpu == -1)
371 return;
8691e5a8 372 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 373}
374
2384d2b3
SY		 375static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
376{
377 if (vmx->vpid == 0)
378 return;
379
380 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
381}
382
1439442c
SY		 383static inline void ept_sync_global(void)
384{
385 if (cpu_has_vmx_invept_global())
386 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
387}
388
389static inline void ept_sync_context(u64 eptp)
390{
089d034e 391 if (enable_ept) {
1439442c
SY		 392 if (cpu_has_vmx_invept_context())
393 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
394 else
395 ept_sync_global();
396 }
397}
398
399static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
400{
089d034e 401 if (enable_ept) {
1439442c
SY		 402 if (cpu_has_vmx_invept_individual_addr())
403 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
404 eptp, gpa);
405 else
406 ept_sync_context(eptp);
407 }
408}
409
6aa8b732
AK		 410static unsigned long vmcs_readl(unsigned long field)
411{
412 unsigned long value;
413
4ecac3fd 414 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 415 : "=a"(value) : "d"(field) : "cc");
416 return value;
417}
418
419static u16 vmcs_read16(unsigned long field)
420{
421 return vmcs_readl(field);
422}
423
424static u32 vmcs_read32(unsigned long field)
425{
426 return vmcs_readl(field);
427}
428
429static u64 vmcs_read64(unsigned long field)
430{
05b3e0c2 431#ifdef CONFIG_X86_64
6aa8b732
AK		 432 return vmcs_readl(field);
433#else
434 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
435#endif
436}
437
e52de1b8
AK		 438static noinline void vmwrite_error(unsigned long field, unsigned long value)
439{
440 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
441 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
442 dump_stack();
443}
444
6aa8b732
AK		 445static void vmcs_writel(unsigned long field, unsigned long value)
446{
447 u8 error;
448
4ecac3fd 449 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 450 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 451 if (unlikely(error))
452 vmwrite_error(field, value);
6aa8b732
AK		 453}
454
455static void vmcs_write16(unsigned long field, u16 value)
456{
457 vmcs_writel(field, value);
458}
459
460static void vmcs_write32(unsigned long field, u32 value)
461{
462 vmcs_writel(field, value);
463}
464
465static void vmcs_write64(unsigned long field, u64 value)
466{
6aa8b732 467 vmcs_writel(field, value);
7682f2d0 468#ifndef CONFIG_X86_64
6aa8b732
AK		 469 asm volatile ("");
470 vmcs_writel(field+1, value >> 32);
471#endif
472}
473
2ab455cc
AL		 474static void vmcs_clear_bits(unsigned long field, u32 mask)
475{
476 vmcs_writel(field, vmcs_readl(field) & ~mask);
477}
478
479static void vmcs_set_bits(unsigned long field, u32 mask)
480{
481 vmcs_writel(field, vmcs_readl(field) | mask);
482}
483
abd3f2d6
AK		 484static void update_exception_bitmap(struct kvm_vcpu *vcpu)
485{
486 u32 eb;
487
7aa81cc0 488 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 489 if (!vcpu->fpu_active)
490 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 491 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
492 if (vcpu->guest_debug &
493 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
494 eb |= 1u << DB_VECTOR;
495 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
496 eb |= 1u << BP_VECTOR;
497 }
ad312c7c 498 if (vcpu->arch.rmode.active)
abd3f2d6 499 eb = ~0;
089d034e 500 if (enable_ept)
1439442c 501 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 502 vmcs_write32(EXCEPTION_BITMAP, eb);
503}
504
33ed6329
AK		 505static void reload_tss(void)
506{
33ed6329
AK		 507 /*
508 * VT restores TR but not its size. Useless.
509 */
510 struct descriptor_table gdt;
a5f61300 511 struct desc_struct *descs;
33ed6329 512
d6e88aec 513 kvm_get_gdt(&gdt);
33ed6329
AK		 514 descs = (void *)gdt.base;
515 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
516 load_TR_desc();
33ed6329
AK		 517}
518
8b9cf98c 519static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 520{
a2fa3e9f 521 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 522 u64 host_efer = vmx->host_msrs[efer_offset].data;
523 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
524 u64 ignore_bits;
525
526 if (efer_offset < 0)
527 return;
528 /*
529 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
530 * outside long mode
531 */
532 ignore_bits = EFER_NX | EFER_SCE;
533#ifdef CONFIG_X86_64
534 ignore_bits |= EFER_LMA | EFER_LME;
535 /* SCE is meaningful only in long mode on Intel */
536 if (guest_efer & EFER_LMA)
537 ignore_bits &= ~(u64)EFER_SCE;
538#endif
539 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
540 return;
2cc51560 541
51c6cf66
AK		 542 vmx->host_state.guest_efer_loaded = 1;
543 guest_efer &= ~ignore_bits;
544 guest_efer |= host_efer & ignore_bits;
545 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 546 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 547}
548
51c6cf66
AK		 549static void reload_host_efer(struct vcpu_vmx *vmx)
550{
551 if (vmx->host_state.guest_efer_loaded) {
552 vmx->host_state.guest_efer_loaded = 0;
553 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
554 }
555}
556
04d2cc77 557static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 558{
04d2cc77
AK		 559 struct vcpu_vmx *vmx = to_vmx(vcpu);
560
a2fa3e9f 561 if (vmx->host_state.loaded)
33ed6329
AK		 562 return;
563
a2fa3e9f 564 vmx->host_state.loaded = 1;
33ed6329
AK		 565 /*
566 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
567 * allow segment selectors with cpl > 0 or ti == 1.
568 */
d6e88aec 569 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 570 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 571 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 572 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 573 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 574 vmx->host_state.fs_reload_needed = 0;
575 } else {
33ed6329 576 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 577 vmx->host_state.fs_reload_needed = 1;
33ed6329 578 }
d6e88aec 579 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 580 if (!(vmx->host_state.gs_sel & 7))
581 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 582 else {
583 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 584 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 585 }
586
587#ifdef CONFIG_X86_64
588 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
589 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
590#else
a2fa3e9f
GH		 591 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
592 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 593#endif
707c0874
AK		 594
595#ifdef CONFIG_X86_64
d77c26fc 596 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 597 save_msrs(vmx->host_msrs +
598 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 599
707c0874 600#endif
a2fa3e9f 601 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 602 load_transition_efer(vmx);
33ed6329
AK		 603}
604
a9b21b62 605static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 606{
15ad7146 607 unsigned long flags;
33ed6329 608
a2fa3e9f 609 if (!vmx->host_state.loaded)
33ed6329
AK		 610 return;
611
e1beb1d3 612 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 613 vmx->host_state.loaded = 0;
152d3f2f 614 if (vmx->host_state.fs_reload_needed)
d6e88aec 615 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 616 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 617 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 618 /*
619 * If we have to reload gs, we must take care to
620 * preserve our gs base.
621 */
15ad7146 622 local_irq_save(flags);
d6e88aec 623 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 624#ifdef CONFIG_X86_64
625 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
626#endif
15ad7146 627 local_irq_restore(flags);
33ed6329 628 }
152d3f2f 629 reload_tss();
a2fa3e9f
GH		 630 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
631 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 632 reload_host_efer(vmx);
33ed6329
AK		 633}
634
a9b21b62
AK		 635static void vmx_load_host_state(struct vcpu_vmx *vmx)
636{
637 preempt_disable();
638 __vmx_load_host_state(vmx);
639 preempt_enable();
640}
641
6aa8b732
AK		 642/*
643 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
644 * vcpu mutex is already taken.
645 */
15ad7146 646static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 647{
a2fa3e9f
GH		 648 struct vcpu_vmx *vmx = to_vmx(vcpu);
649 u64 phys_addr = __pa(vmx->vmcs);
019960ae 650 u64 tsc_this, delta, new_offset;
6aa8b732 651
a3d7f85f 652 if (vcpu->cpu != cpu) {
8b9cf98c 653 vcpu_clear(vmx);
2f599714 654 kvm_migrate_timers(vcpu);
2384d2b3 655 vpid_sync_vcpu_all(vmx);
543e4243
AK		 656 local_irq_disable();
657 list_add(&vmx->local_vcpus_link,
658 &per_cpu(vcpus_on_cpu, cpu));
659 local_irq_enable();
a3d7f85f 660 }
6aa8b732 661
a2fa3e9f 662 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 663 u8 error;
664
a2fa3e9f 665 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 666 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 667 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
668 : "cc");
669 if (error)
670 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 671 vmx->vmcs, phys_addr);
6aa8b732
AK		 672 }
673
674 if (vcpu->cpu != cpu) {
675 struct descriptor_table dt;
676 unsigned long sysenter_esp;
677
678 vcpu->cpu = cpu;
679 /*
680 * Linux uses per-cpu TSS and GDT, so set these when switching
681 * processors.
682 */
d6e88aec
AK		 683 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
684 kvm_get_gdt(&dt);
6aa8b732
AK		 685 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
686
687 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
688 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 689
690 /*
691 * Make sure the time stamp counter is monotonous.
692 */
693 rdtscll(tsc_this);
019960ae
AK		 694 if (tsc_this < vcpu->arch.host_tsc) {
695 delta = vcpu->arch.host_tsc - tsc_this;
696 new_offset = vmcs_read64(TSC_OFFSET) + delta;
697 vmcs_write64(TSC_OFFSET, new_offset);
698 }
6aa8b732 699 }
6aa8b732
AK		 700}
701
702static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
703{
a9b21b62 704 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 705}
706
5fd86fcf
AK		 707static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->fpu_active)
710 return;
711 vcpu->fpu_active = 1;
707d92fa 712 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 713 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 714 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 715 update_exception_bitmap(vcpu);
716}
717
718static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
719{
720 if (!vcpu->fpu_active)
721 return;
722 vcpu->fpu_active = 0;
707d92fa 723 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 724 update_exception_bitmap(vcpu);
725}
726
6aa8b732
AK		 727static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
728{
729 return vmcs_readl(GUEST_RFLAGS);
730}
731
732static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
733{
ad312c7c 734 if (vcpu->arch.rmode.active)
053de044 735 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 736 vmcs_writel(GUEST_RFLAGS, rflags);
737}
738
739static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
740{
741 unsigned long rip;
742 u32 interruptibility;
743
5fdbf976 744 rip = kvm_rip_read(vcpu);
6aa8b732 745 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 746 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 747
748 /*
749 * We emulated an instruction, so temporary interrupt blocking
750 * should be removed, if set.
751 */
752 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
753 if (interruptibility & 3)
754 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
755 interruptibility & ~3);
756}
757
298101da
AK		 758static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
759 bool has_error_code, u32 error_code)
760{
77ab6db0 761 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 762 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 763
8ab2d2e2 764 if (has_error_code) {
77ab6db0 765 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 766 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
767 }
77ab6db0
JK		 768
769 if (vcpu->arch.rmode.active) {
770 vmx->rmode.irq.pending = true;
771 vmx->rmode.irq.vector = nr;
772 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
8ab2d2e2 773 if (nr == BP_VECTOR || nr == OF_VECTOR)
77ab6db0 774 vmx->rmode.irq.rip++;
8ab2d2e2
JK		 775 intr_info |= INTR_TYPE_SOFT_INTR;
776 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 777 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
778 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
779 return;
780 }
781
8ab2d2e2
JK		 782 if (nr == BP_VECTOR || nr == OF_VECTOR) {
783 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
784 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
785 } else
786 intr_info |= INTR_TYPE_HARD_EXCEPTION;
787
788 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 789}
790
a75beee6
ED		 791/*
792 * Swap MSR entry in host/guest MSR entry array.
793 */
54e11fa1 794#ifdef CONFIG_X86_64
8b9cf98c 795static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 796{
a2fa3e9f
GH		 797 struct kvm_msr_entry tmp;
798
799 tmp = vmx->guest_msrs[to];
800 vmx->guest_msrs[to] = vmx->guest_msrs[from];
801 vmx->guest_msrs[from] = tmp;
802 tmp = vmx->host_msrs[to];
803 vmx->host_msrs[to] = vmx->host_msrs[from];
804 vmx->host_msrs[from] = tmp;
a75beee6 805}
54e11fa1 806#endif
a75beee6 807
e38aea3e
AK		 808/*
809 * Set up the vmcs to automatically save and restore system
810 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
811 * mode, as fiddling with msrs is very expensive.
812 */
8b9cf98c 813static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 814{
2cc51560 815 int save_nmsrs;
5897297b 816 unsigned long *msr_bitmap;
e38aea3e 817
33f9c505 818 vmx_load_host_state(vmx);
a75beee6
ED		 819 save_nmsrs = 0;
820#ifdef CONFIG_X86_64
8b9cf98c 821 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 822 int index;
823
8b9cf98c 824 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 825 if (index >= 0)
8b9cf98c
RR		 826 move_msr_up(vmx, index, save_nmsrs++);
827 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 828 if (index >= 0)
8b9cf98c
RR		 829 move_msr_up(vmx, index, save_nmsrs++);
830 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 831 if (index >= 0)
8b9cf98c
RR		 832 move_msr_up(vmx, index, save_nmsrs++);
833 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 834 if (index >= 0)
8b9cf98c 835 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 836 /*
837 * MSR_K6_STAR is only needed on long mode guests, and only
838 * if efer.sce is enabled.
839 */
8b9cf98c 840 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 841 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 842 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 843 }
844#endif
a2fa3e9f 845 vmx->save_nmsrs = save_nmsrs;
e38aea3e 846
4d56c8a7 847#ifdef CONFIG_X86_64
a2fa3e9f 848 vmx->msr_offset_kernel_gs_base =
8b9cf98c 849 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 850#endif
8b9cf98c 851 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 852
853 if (cpu_has_vmx_msr_bitmap()) {
854 if (is_long_mode(&vmx->vcpu))
855 msr_bitmap = vmx_msr_bitmap_longmode;
856 else
857 msr_bitmap = vmx_msr_bitmap_legacy;
858
859 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
860 }
e38aea3e
AK		 861}
862
6aa8b732
AK		 863/*
864 * reads and returns guest's timestamp counter "register"
865 * guest_tsc = host_tsc + tsc_offset -- 21.3
866 */
867static u64 guest_read_tsc(void)
868{
869 u64 host_tsc, tsc_offset;
870
871 rdtscll(host_tsc);
872 tsc_offset = vmcs_read64(TSC_OFFSET);
873 return host_tsc + tsc_offset;
874}
875
876/*
877 * writes 'guest_tsc' into guest's timestamp counter "register"
878 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
879 */
53f658b3 880static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 881{
6aa8b732
AK		 882 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
883}
884
6aa8b732
AK		 885/*
886 * Reads an msr value (of 'msr_index') into 'pdata'.
887 * Returns 0 on success, non-0 otherwise.
888 * Assumes vcpu_load() was already called.
889 */
890static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
891{
892 u64 data;
a2fa3e9f 893 struct kvm_msr_entry *msr;
6aa8b732
AK		 894
895 if (!pdata) {
896 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
897 return -EINVAL;
898 }
899
900 switch (msr_index) {
05b3e0c2 901#ifdef CONFIG_X86_64
6aa8b732
AK		 902 case MSR_FS_BASE:
903 data = vmcs_readl(GUEST_FS_BASE);
904 break;
905 case MSR_GS_BASE:
906 data = vmcs_readl(GUEST_GS_BASE);
907 break;
908 case MSR_EFER:
3bab1f5d 909 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 910#endif
911 case MSR_IA32_TIME_STAMP_COUNTER:
912 data = guest_read_tsc();
913 break;
914 case MSR_IA32_SYSENTER_CS:
915 data = vmcs_read32(GUEST_SYSENTER_CS);
916 break;
917 case MSR_IA32_SYSENTER_EIP:
f5b42c33 918 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 919 break;
920 case MSR_IA32_SYSENTER_ESP:
f5b42c33 921 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 922 break;
6aa8b732 923 default:
516a1a7e 924 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 925 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 926 if (msr) {
927 data = msr->data;
928 break;
6aa8b732 929 }
3bab1f5d 930 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 931 }
932
933 *pdata = data;
934 return 0;
935}
936
937/*
938 * Writes msr value into into the appropriate "register".
939 * Returns 0 on success, non-0 otherwise.
940 * Assumes vcpu_load() was already called.
941 */
942static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
943{
a2fa3e9f
GH		 944 struct vcpu_vmx *vmx = to_vmx(vcpu);
945 struct kvm_msr_entry *msr;
53f658b3 946 u64 host_tsc;
2cc51560
ED		 947 int ret = 0;
948
6aa8b732 949 switch (msr_index) {
3bab1f5d 950 case MSR_EFER:
a9b21b62 951 vmx_load_host_state(vmx);
2cc51560 952 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 953 break;
16175a79 954#ifdef CONFIG_X86_64
6aa8b732
AK		 955 case MSR_FS_BASE:
956 vmcs_writel(GUEST_FS_BASE, data);
957 break;
958 case MSR_GS_BASE:
959 vmcs_writel(GUEST_GS_BASE, data);
960 break;
961#endif
962 case MSR_IA32_SYSENTER_CS:
963 vmcs_write32(GUEST_SYSENTER_CS, data);
964 break;
965 case MSR_IA32_SYSENTER_EIP:
f5b42c33 966 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 967 break;
968 case MSR_IA32_SYSENTER_ESP:
f5b42c33 969 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 970 break;
d27d4aca 971 case MSR_IA32_TIME_STAMP_COUNTER:
53f658b3
MT		 972 rdtscll(host_tsc);
973 guest_write_tsc(data, host_tsc);
efa67e0d
CL		 974 break;
975 case MSR_P6_PERFCTR0:
976 case MSR_P6_PERFCTR1:
977 case MSR_P6_EVNTSEL0:
978 case MSR_P6_EVNTSEL1:
979 /*
980 * Just discard all writes to the performance counters; this
981 * should keep both older linux and windows 64-bit guests
982 * happy
983 */
984 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
985
6aa8b732 986 break;
468d472f
SY		 987 case MSR_IA32_CR_PAT:
988 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
989 vmcs_write64(GUEST_IA32_PAT, data);
990 vcpu->arch.pat = data;
991 break;
992 }
993 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 994 default:
a9b21b62 995 vmx_load_host_state(vmx);
8b9cf98c 996 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 997 if (msr) {
998 msr->data = data;
999 break;
6aa8b732 1000 }
2cc51560 1001 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1002 }
1003
2cc51560 1004 return ret;
6aa8b732
AK		 1005}
1006
5fdbf976 1007static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1008{
5fdbf976
MT		 1009 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1010 switch (reg) {
1011 case VCPU_REGS_RSP:
1012 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1013 break;
1014 case VCPU_REGS_RIP:
1015 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1016 break;
1017 default:
1018 break;
1019 }
6aa8b732
AK		 1020}
1021
d0bfb940 1022static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1023{
d0bfb940
JK		 1024 int old_debug = vcpu->guest_debug;
1025 unsigned long flags;
6aa8b732 1026
d0bfb940
JK		 1027 vcpu->guest_debug = dbg->control;
1028 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1029 vcpu->guest_debug = 0;
6aa8b732 1030
ae675ef0
JK		 1031 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1032 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1033 else
1034 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1035
d0bfb940
JK		 1036 flags = vmcs_readl(GUEST_RFLAGS);
1037 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1038 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1039 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1040 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1041 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1042
abd3f2d6 1043 update_exception_bitmap(vcpu);
6aa8b732
AK		 1044
1045 return 0;
1046}
1047
1048static __init int cpu_has_kvm_support(void)
1049{
6210e37b 1050 return cpu_has_vmx();
6aa8b732
AK		 1051}
1052
1053static __init int vmx_disabled_by_bios(void)
1054{
1055 u64 msr;
1056
1057 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1058 return (msr & (FEATURE_CONTROL_LOCKED |
1059 FEATURE_CONTROL_VMXON_ENABLED))
1060 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1061 /* locked but not enabled */
6aa8b732
AK		 1062}
1063
774c47f1 1064static void hardware_enable(void *garbage)
6aa8b732
AK		 1065{
1066 int cpu = raw_smp_processor_id();
1067 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1068 u64 old;
1069
543e4243 1070 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1071 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1072 if ((old & (FEATURE_CONTROL_LOCKED |
1073 FEATURE_CONTROL_VMXON_ENABLED))
1074 != (FEATURE_CONTROL_LOCKED |
1075 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1076 /* enable and lock */
62b3ffb8 1077 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1078 FEATURE_CONTROL_LOCKED |
1079 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1080 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1081 asm volatile (ASM_VMX_VMXON_RAX
1082 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1083 : "memory", "cc");
1084}
1085
543e4243
AK		 1086static void vmclear_local_vcpus(void)
1087{
1088 int cpu = raw_smp_processor_id();
1089 struct vcpu_vmx *vmx, *n;
1090
1091 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1092 local_vcpus_link)
1093 __vcpu_clear(vmx);
1094}
1095
710ff4a8
EH		 1096
1097/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1098 * tricks.
1099 */
1100static void kvm_cpu_vmxoff(void)
6aa8b732 1101{
4ecac3fd 1102 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1103 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1104}
1105
710ff4a8
EH		 1106static void hardware_disable(void *garbage)
1107{
1108 vmclear_local_vcpus();
1109 kvm_cpu_vmxoff();
1110}
1111
1c3d14fe 1112static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1113 u32 msr, u32 *result)
1c3d14fe
YS		 1114{
1115 u32 vmx_msr_low, vmx_msr_high;
1116 u32 ctl = ctl_min | ctl_opt;
1117
1118 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1119
1120 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1121 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1122
1123 /* Ensure minimum (required) set of control bits are supported. */
1124 if (ctl_min & ~ctl)
002c7f7c 1125 return -EIO;
1c3d14fe
YS		 1126
1127 *result = ctl;
1128 return 0;
1129}
1130
002c7f7c 1131static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1132{
1133 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1134 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1135 u32 _pin_based_exec_control = 0;
1136 u32 _cpu_based_exec_control = 0;
f78e0e2e 1137 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1138 u32 _vmexit_control = 0;
1139 u32 _vmentry_control = 0;
1140
1141 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1142 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1143 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1144 &_pin_based_exec_control) < 0)
002c7f7c 1145 return -EIO;
1c3d14fe
YS		 1146
1147 min = CPU_BASED_HLT_EXITING |
1148#ifdef CONFIG_X86_64
1149 CPU_BASED_CR8_LOAD_EXITING |
1150 CPU_BASED_CR8_STORE_EXITING |
1151#endif
d56f546d
SY		 1152 CPU_BASED_CR3_LOAD_EXITING |
1153 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1154 CPU_BASED_USE_IO_BITMAPS |
1155 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1156 CPU_BASED_USE_TSC_OFFSETING |
1157 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1158 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1159 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1160 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1161 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1162 &_cpu_based_exec_control) < 0)
002c7f7c 1163 return -EIO;
6e5d865c
YS		 1164#ifdef CONFIG_X86_64
1165 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1166 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1167 ~CPU_BASED_CR8_STORE_EXITING;
1168#endif
f78e0e2e 1169 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1170 min2 = 0;
1171 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1172 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1173 SECONDARY_EXEC_ENABLE_VPID |
1174 SECONDARY_EXEC_ENABLE_EPT;
1175 if (adjust_vmx_controls(min2, opt2,
1176 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1177 &_cpu_based_2nd_exec_control) < 0)
1178 return -EIO;
1179 }
1180#ifndef CONFIG_X86_64
1181 if (!(_cpu_based_2nd_exec_control &
1182 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1183 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1184#endif
d56f546d 1185 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1186 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1187 enabled */
d56f546d 1188 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1189 CPU_BASED_CR3_STORE_EXITING |
1190 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1191 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1192 &_cpu_based_exec_control) < 0)
1193 return -EIO;
1194 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1195 vmx_capability.ept, vmx_capability.vpid);
1196 }
1c3d14fe
YS		 1197
1198 min = 0;
1199#ifdef CONFIG_X86_64
1200 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1201#endif
468d472f 1202 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1203 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1204 &_vmexit_control) < 0)
002c7f7c 1205 return -EIO;
1c3d14fe 1206
468d472f
SY		 1207 min = 0;
1208 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1209 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1210 &_vmentry_control) < 0)
002c7f7c 1211 return -EIO;
6aa8b732 1212
c68876fd 1213 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1214
1215 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1216 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1217 return -EIO;
1c3d14fe
YS		 1218
1219#ifdef CONFIG_X86_64
1220 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1221 if (vmx_msr_high & (1u<<16))
002c7f7c 1222 return -EIO;
1c3d14fe
YS		 1223#endif
1224
1225 /* Require Write-Back (WB) memory type for VMCS accesses. */
1226 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1227 return -EIO;
1c3d14fe 1228
002c7f7c
YS		 1229 vmcs_conf->size = vmx_msr_high & 0x1fff;
1230 vmcs_conf->order = get_order(vmcs_config.size);
1231 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1232
002c7f7c
YS		 1233 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1234 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1235 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1236 vmcs_conf->vmexit_ctrl = _vmexit_control;
1237 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1238
1239 return 0;
c68876fd 1240}
6aa8b732
AK		 1241
1242static struct vmcs *alloc_vmcs_cpu(int cpu)
1243{
1244 int node = cpu_to_node(cpu);
1245 struct page *pages;
1246 struct vmcs *vmcs;
1247
1c3d14fe 1248 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1249 if (!pages)
1250 return NULL;
1251 vmcs = page_address(pages);
1c3d14fe
YS		 1252 memset(vmcs, 0, vmcs_config.size);
1253 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1254 return vmcs;
1255}
1256
1257static struct vmcs *alloc_vmcs(void)
1258{
d3b2c338 1259 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1260}
1261
1262static void free_vmcs(struct vmcs *vmcs)
1263{
1c3d14fe 1264 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1265}
1266
39959588 1267static void free_kvm_area(void)
6aa8b732
AK		 1268{
1269 int cpu;
1270
1271 for_each_online_cpu(cpu)
1272 free_vmcs(per_cpu(vmxarea, cpu));
1273}
1274
6aa8b732
AK		 1275static __init int alloc_kvm_area(void)
1276{
1277 int cpu;
1278
1279 for_each_online_cpu(cpu) {
1280 struct vmcs *vmcs;
1281
1282 vmcs = alloc_vmcs_cpu(cpu);
1283 if (!vmcs) {
1284 free_kvm_area();
1285 return -ENOMEM;
1286 }
1287
1288 per_cpu(vmxarea, cpu) = vmcs;
1289 }
1290 return 0;
1291}
1292
1293static __init int hardware_setup(void)
1294{
002c7f7c
YS		 1295 if (setup_vmcs_config(&vmcs_config) < 0)
1296 return -EIO;
50a37eb4
JR		 1297
1298 if (boot_cpu_has(X86_FEATURE_NX))
1299 kvm_enable_efer_bits(EFER_NX);
1300
93ba03c2
SY		 1301 if (!cpu_has_vmx_vpid())
1302 enable_vpid = 0;
1303
1304 if (!cpu_has_vmx_ept())
1305 enable_ept = 0;
1306
1307 if (!cpu_has_vmx_flexpriority())
1308 flexpriority_enabled = 0;
1309
95ba8273
GN		 1310 if (!cpu_has_vmx_tpr_shadow())
1311 kvm_x86_ops->update_cr8_intercept = NULL;
1312
6aa8b732
AK		 1313 return alloc_kvm_area();
1314}
1315
1316static __exit void hardware_unsetup(void)
1317{
1318 free_kvm_area();
1319}
1320
6aa8b732
AK		 1321static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1322{
1323 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1324
6af11b9e 1325 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1326 vmcs_write16(sf->selector, save->selector);
1327 vmcs_writel(sf->base, save->base);
1328 vmcs_write32(sf->limit, save->limit);
1329 vmcs_write32(sf->ar_bytes, save->ar);
1330 } else {
1331 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1332 << AR_DPL_SHIFT;
1333 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1334 }
1335}
1336
1337static void enter_pmode(struct kvm_vcpu *vcpu)
1338{
1339 unsigned long flags;
a89a8fb9 1340 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1341
a89a8fb9 1342 vmx->emulation_required = 1;
ad312c7c 1343 vcpu->arch.rmode.active = 0;
6aa8b732 1344
ad312c7c
ZX		 1345 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1346 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1347 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1348
1349 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1350 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1351 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1352 vmcs_writel(GUEST_RFLAGS, flags);
1353
66aee91a
RR		 1354 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1355 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1356
1357 update_exception_bitmap(vcpu);
1358
a89a8fb9
MG		 1359 if (emulate_invalid_guest_state)
1360 return;
1361
ad312c7c
ZX		 1362 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1363 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1364 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1365 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1366
1367 vmcs_write16(GUEST_SS_SELECTOR, 0);
1368 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1369
1370 vmcs_write16(GUEST_CS_SELECTOR,
1371 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1372 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1373}
1374
d77c26fc 1375static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1376{
bfc6d222 1377 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1378 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1379 kvm->memslots[0].npages - 3;
1380 return base_gfn << PAGE_SHIFT;
1381 }
bfc6d222 1382 return kvm->arch.tss_addr;
6aa8b732
AK		 1383}
1384
1385static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1386{
1387 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1388
1389 save->selector = vmcs_read16(sf->selector);
1390 save->base = vmcs_readl(sf->base);
1391 save->limit = vmcs_read32(sf->limit);
1392 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1393 vmcs_write16(sf->selector, save->base >> 4);
1394 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1395 vmcs_write32(sf->limit, 0xffff);
1396 vmcs_write32(sf->ar_bytes, 0xf3);
1397}
1398
1399static void enter_rmode(struct kvm_vcpu *vcpu)
1400{
1401 unsigned long flags;
a89a8fb9 1402 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1403
a89a8fb9 1404 vmx->emulation_required = 1;
ad312c7c 1405 vcpu->arch.rmode.active = 1;
6aa8b732 1406
ad312c7c 1407 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1408 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1409
ad312c7c 1410 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1411 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1412
ad312c7c 1413 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1414 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1415
1416 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1417 vcpu->arch.rmode.save_iopl
1418 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1419
053de044 1420 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1421
1422 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1423 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1424 update_exception_bitmap(vcpu);
1425
a89a8fb9
MG		 1426 if (emulate_invalid_guest_state)
1427 goto continue_rmode;
1428
6aa8b732
AK		 1429 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1430 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1431 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1432
1433 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1434 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1435 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1436 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1437 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1438
ad312c7c
ZX		 1439 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1440 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1441 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1442 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1443
a89a8fb9 1444continue_rmode:
8668a3c4 1445 kvm_mmu_reset_context(vcpu);
b7ebfb05 1446 init_rmode(vcpu->kvm);
6aa8b732
AK		 1447}
1448
401d10de
AS		 1449static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1450{
1451 struct vcpu_vmx *vmx = to_vmx(vcpu);
1452 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1453
1454 vcpu->arch.shadow_efer = efer;
1455 if (!msr)
1456 return;
1457 if (efer & EFER_LMA) {
1458 vmcs_write32(VM_ENTRY_CONTROLS,
1459 vmcs_read32(VM_ENTRY_CONTROLS) |
1460 VM_ENTRY_IA32E_MODE);
1461 msr->data = efer;
1462 } else {
1463 vmcs_write32(VM_ENTRY_CONTROLS,
1464 vmcs_read32(VM_ENTRY_CONTROLS) &
1465 ~VM_ENTRY_IA32E_MODE);
1466
1467 msr->data = efer & ~EFER_LME;
1468 }
1469 setup_msrs(vmx);
1470}
1471
05b3e0c2 1472#ifdef CONFIG_X86_64
6aa8b732
AK		 1473
1474static void enter_lmode(struct kvm_vcpu *vcpu)
1475{
1476 u32 guest_tr_ar;
1477
1478 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1479 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1480 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1481 __func__);
6aa8b732
AK		 1482 vmcs_write32(GUEST_TR_AR_BYTES,
1483 (guest_tr_ar & ~AR_TYPE_MASK)
1484 | AR_TYPE_BUSY_64_TSS);
1485 }
ad312c7c 1486 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1487 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1488}
1489
1490static void exit_lmode(struct kvm_vcpu *vcpu)
1491{
ad312c7c 1492 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1493
1494 vmcs_write32(VM_ENTRY_CONTROLS,
1495 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1496 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1497}
1498
1499#endif
1500
2384d2b3
SY		 1501static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1502{
1503 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1504 if (enable_ept)
4e1096d2 1505 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1506}
1507
25c4c276 1508static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1509{
ad312c7c
ZX		 1510 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1511 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1512}
1513
1439442c
SY		 1514static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1515{
1516 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1517 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1518 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1519 return;
1520 }
1521 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1522 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1523 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1524 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1525 }
1526}
1527
1528static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1529
1530static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1531 unsigned long cr0,
1532 struct kvm_vcpu *vcpu)
1533{
1534 if (!(cr0 & X86_CR0_PG)) {
1535 /* From paging/starting to nonpaging */
1536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1537 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1538 (CPU_BASED_CR3_LOAD_EXITING |
1539 CPU_BASED_CR3_STORE_EXITING));
1540 vcpu->arch.cr0 = cr0;
1541 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1542 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1543 *hw_cr0 &= ~X86_CR0_WP;
1544 } else if (!is_paging(vcpu)) {
1545 /* From nonpaging to paging */
1546 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1547 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1548 ~(CPU_BASED_CR3_LOAD_EXITING |
1549 CPU_BASED_CR3_STORE_EXITING));
1550 vcpu->arch.cr0 = cr0;
1551 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1552 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1553 *hw_cr0 &= ~X86_CR0_WP;
1554 }
1555}
1556
1557static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1558 struct kvm_vcpu *vcpu)
1559{
1560 if (!is_paging(vcpu)) {
1561 *hw_cr4 &= ~X86_CR4_PAE;
1562 *hw_cr4 |= X86_CR4_PSE;
1563 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1564 *hw_cr4 &= ~X86_CR4_PAE;
1565}
1566
6aa8b732
AK		 1567static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1568{
1439442c
SY		 1569 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1570 KVM_VM_CR0_ALWAYS_ON;
1571
5fd86fcf
AK		 1572 vmx_fpu_deactivate(vcpu);
1573
ad312c7c 1574 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1575 enter_pmode(vcpu);
1576
ad312c7c 1577 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1578 enter_rmode(vcpu);
1579
05b3e0c2 1580#ifdef CONFIG_X86_64
ad312c7c 1581 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1582 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1583 enter_lmode(vcpu);
707d92fa 1584 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1585 exit_lmode(vcpu);
1586 }
1587#endif
1588
089d034e 1589 if (enable_ept)
1439442c
SY		 1590 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1591
6aa8b732 1592 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1593 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1594 vcpu->arch.cr0 = cr0;
5fd86fcf 1595
707d92fa 1596 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1597 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1598}
1599
1439442c
SY		 1600static u64 construct_eptp(unsigned long root_hpa)
1601{
1602 u64 eptp;
1603
1604 /* TODO write the value reading from MSR */
1605 eptp = VMX_EPT_DEFAULT_MT |
1606 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1607 eptp |= (root_hpa & PAGE_MASK);
1608
1609 return eptp;
1610}
1611
6aa8b732
AK		 1612static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1613{
1439442c
SY		 1614 unsigned long guest_cr3;
1615 u64 eptp;
1616
1617 guest_cr3 = cr3;
089d034e 1618 if (enable_ept) {
1439442c
SY		 1619 eptp = construct_eptp(cr3);
1620 vmcs_write64(EPT_POINTER, eptp);
1621 ept_sync_context(eptp);
1622 ept_load_pdptrs(vcpu);
1623 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1624 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1625 }
1626
2384d2b3 1627 vmx_flush_tlb(vcpu);
1439442c 1628 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1629 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1630 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1631}
1632
1633static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1634{
1439442c
SY		 1635 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1636 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1637
ad312c7c 1638 vcpu->arch.cr4 = cr4;
089d034e 1639 if (enable_ept)
1439442c
SY		 1640 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1641
1642 vmcs_writel(CR4_READ_SHADOW, cr4);
1643 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1644}
1645
6aa8b732
AK		 1646static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1647{
1648 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649
1650 return vmcs_readl(sf->base);
1651}
1652
1653static void vmx_get_segment(struct kvm_vcpu *vcpu,
1654 struct kvm_segment *var, int seg)
1655{
1656 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1657 u32 ar;
1658
1659 var->base = vmcs_readl(sf->base);
1660 var->limit = vmcs_read32(sf->limit);
1661 var->selector = vmcs_read16(sf->selector);
1662 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1663 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1664 ar = 0;
1665 var->type = ar & 15;
1666 var->s = (ar >> 4) & 1;
1667 var->dpl = (ar >> 5) & 3;
1668 var->present = (ar >> 7) & 1;
1669 var->avl = (ar >> 12) & 1;
1670 var->l = (ar >> 13) & 1;
1671 var->db = (ar >> 14) & 1;
1672 var->g = (ar >> 15) & 1;
1673 var->unusable = (ar >> 16) & 1;
1674}
1675
2e4d2653
IE		 1676static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1677{
1678 struct kvm_segment kvm_seg;
1679
1680 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1681 return 0;
1682
1683 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1684 return 3;
1685
1686 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1687 return kvm_seg.selector & 3;
1688}
1689
653e3108 1690static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1691{
6aa8b732
AK		 1692 u32 ar;
1693
653e3108 1694 if (var->unusable)
6aa8b732
AK		 1695 ar = 1 << 16;
1696 else {
1697 ar = var->type & 15;
1698 ar |= (var->s & 1) << 4;
1699 ar |= (var->dpl & 3) << 5;
1700 ar |= (var->present & 1) << 7;
1701 ar |= (var->avl & 1) << 12;
1702 ar |= (var->l & 1) << 13;
1703 ar |= (var->db & 1) << 14;
1704 ar |= (var->g & 1) << 15;
1705 }
f7fbf1fd
UL		 1706 if (ar == 0) /* a 0 value means unusable */
1707 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1708
1709 return ar;
1710}
1711
1712static void vmx_set_segment(struct kvm_vcpu *vcpu,
1713 struct kvm_segment *var, int seg)
1714{
1715 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1716 u32 ar;
1717
ad312c7c
ZX		 1718 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1719 vcpu->arch.rmode.tr.selector = var->selector;
1720 vcpu->arch.rmode.tr.base = var->base;
1721 vcpu->arch.rmode.tr.limit = var->limit;
1722 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1723 return;
1724 }
1725 vmcs_writel(sf->base, var->base);
1726 vmcs_write32(sf->limit, var->limit);
1727 vmcs_write16(sf->selector, var->selector);
ad312c7c 1728 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1729 /*
1730 * Hack real-mode segments into vm86 compatibility.
1731 */
1732 if (var->base == 0xffff0000 && var->selector == 0xf000)
1733 vmcs_writel(sf->base, 0xf0000);
1734 ar = 0xf3;
1735 } else
1736 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1737 vmcs_write32(sf->ar_bytes, ar);
1738}
1739
6aa8b732
AK		 1740static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1741{
1742 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1743
1744 *db = (ar >> 14) & 1;
1745 *l = (ar >> 13) & 1;
1746}
1747
1748static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1749{
1750 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1751 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1752}
1753
1754static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1755{
1756 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1757 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1758}
1759
1760static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1761{
1762 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1763 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1764}
1765
1766static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1767{
1768 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1769 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1770}
1771
648dfaa7
MG		 1772static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1773{
1774 struct kvm_segment var;
1775 u32 ar;
1776
1777 vmx_get_segment(vcpu, &var, seg);
1778 ar = vmx_segment_access_rights(&var);
1779
1780 if (var.base != (var.selector << 4))
1781 return false;
1782 if (var.limit != 0xffff)
1783 return false;
1784 if (ar != 0xf3)
1785 return false;
1786
1787 return true;
1788}
1789
1790static bool code_segment_valid(struct kvm_vcpu *vcpu)
1791{
1792 struct kvm_segment cs;
1793 unsigned int cs_rpl;
1794
1795 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1796 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1797
1872a3f4
AK		 1798 if (cs.unusable)
1799 return false;
648dfaa7
MG		 1800 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1801 return false;
1802 if (!cs.s)
1803 return false;
1872a3f4 1804 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1805 if (cs.dpl > cs_rpl)
1806 return false;
1872a3f4 1807 } else {
648dfaa7
MG		 1808 if (cs.dpl != cs_rpl)
1809 return false;
1810 }
1811 if (!cs.present)
1812 return false;
1813
1814 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1815 return true;
1816}
1817
1818static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1819{
1820 struct kvm_segment ss;
1821 unsigned int ss_rpl;
1822
1823 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1824 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1825
1872a3f4
AK		 1826 if (ss.unusable)
1827 return true;
1828 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1829 return false;
1830 if (!ss.s)
1831 return false;
1832 if (ss.dpl != ss_rpl) /* DPL != RPL */
1833 return false;
1834 if (!ss.present)
1835 return false;
1836
1837 return true;
1838}
1839
1840static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1841{
1842 struct kvm_segment var;
1843 unsigned int rpl;
1844
1845 vmx_get_segment(vcpu, &var, seg);
1846 rpl = var.selector & SELECTOR_RPL_MASK;
1847
1872a3f4
AK		 1848 if (var.unusable)
1849 return true;
648dfaa7
MG		 1850 if (!var.s)
1851 return false;
1852 if (!var.present)
1853 return false;
1854 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1855 if (var.dpl < rpl) /* DPL < RPL */
1856 return false;
1857 }
1858
1859 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1860 * rights flags
1861 */
1862 return true;
1863}
1864
1865static bool tr_valid(struct kvm_vcpu *vcpu)
1866{
1867 struct kvm_segment tr;
1868
1869 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1870
1872a3f4
AK		 1871 if (tr.unusable)
1872 return false;
648dfaa7
MG		 1873 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1874 return false;
1872a3f4 1875 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1876 return false;
1877 if (!tr.present)
1878 return false;
1879
1880 return true;
1881}
1882
1883static bool ldtr_valid(struct kvm_vcpu *vcpu)
1884{
1885 struct kvm_segment ldtr;
1886
1887 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1888
1872a3f4
AK		 1889 if (ldtr.unusable)
1890 return true;
648dfaa7
MG		 1891 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1892 return false;
1893 if (ldtr.type != 2)
1894 return false;
1895 if (!ldtr.present)
1896 return false;
1897
1898 return true;
1899}
1900
1901static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1902{
1903 struct kvm_segment cs, ss;
1904
1905 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1906 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1907
1908 return ((cs.selector & SELECTOR_RPL_MASK) ==
1909 (ss.selector & SELECTOR_RPL_MASK));
1910}
1911
1912/*
1913 * Check if guest state is valid. Returns true if valid, false if
1914 * not.
1915 * We assume that registers are always usable
1916 */
1917static bool guest_state_valid(struct kvm_vcpu *vcpu)
1918{
1919 /* real mode guest state checks */
1920 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1921 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1922 return false;
1923 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1924 return false;
1925 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1926 return false;
1927 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1928 return false;
1929 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1930 return false;
1931 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1932 return false;
1933 } else {
1934 /* protected mode guest state checks */
1935 if (!cs_ss_rpl_check(vcpu))
1936 return false;
1937 if (!code_segment_valid(vcpu))
1938 return false;
1939 if (!stack_segment_valid(vcpu))
1940 return false;
1941 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1942 return false;
1943 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1944 return false;
1945 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1946 return false;
1947 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1948 return false;
1949 if (!tr_valid(vcpu))
1950 return false;
1951 if (!ldtr_valid(vcpu))
1952 return false;
1953 }
1954 /* TODO:
1955 * - Add checks on RIP
1956 * - Add checks on RFLAGS
1957 */
1958
1959 return true;
1960}
1961
d77c26fc 1962static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1963{
6aa8b732 1964 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1965 u16 data = 0;
10589a46 1966 int ret = 0;
195aefde 1967 int r;
6aa8b732 1968
195aefde
IE		 1969 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1970 if (r < 0)
10589a46 1971 goto out;
195aefde 1972 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1973 r = kvm_write_guest_page(kvm, fn++, &data,
1974 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1975 if (r < 0)
10589a46 1976 goto out;
195aefde
IE		 1977 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1978 if (r < 0)
10589a46 1979 goto out;
195aefde
IE		 1980 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1981 if (r < 0)
10589a46 1982 goto out;
195aefde 1983 data = ~0;
10589a46
MT		 1984 r = kvm_write_guest_page(kvm, fn, &data,
1985 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1986 sizeof(u8));
195aefde 1987 if (r < 0)
10589a46
MT		 1988 goto out;
1989
1990 ret = 1;
1991out:
10589a46 1992 return ret;
6aa8b732
AK		 1993}
1994
b7ebfb05
SY		 1995static int init_rmode_identity_map(struct kvm *kvm)
1996{
1997 int i, r, ret;
1998 pfn_t identity_map_pfn;
1999 u32 tmp;
2000
089d034e 2001 if (!enable_ept)
b7ebfb05
SY		 2002 return 1;
2003 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2004 printk(KERN_ERR "EPT: identity-mapping pagetable "
2005 "haven't been allocated!\n");
2006 return 0;
2007 }
2008 if (likely(kvm->arch.ept_identity_pagetable_done))
2009 return 1;
2010 ret = 0;
2011 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2012 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2013 if (r < 0)
2014 goto out;
2015 /* Set up identity-mapping pagetable for EPT in real mode */
2016 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2017 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2018 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2019 r = kvm_write_guest_page(kvm, identity_map_pfn,
2020 &tmp, i * sizeof(tmp), sizeof(tmp));
2021 if (r < 0)
2022 goto out;
2023 }
2024 kvm->arch.ept_identity_pagetable_done = true;
2025 ret = 1;
2026out:
2027 return ret;
2028}
2029
6aa8b732
AK		 2030static void seg_setup(int seg)
2031{
2032 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2033
2034 vmcs_write16(sf->selector, 0);
2035 vmcs_writel(sf->base, 0);
2036 vmcs_write32(sf->limit, 0xffff);
a16b20da 2037 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2038}
2039
f78e0e2e
SY		 2040static int alloc_apic_access_page(struct kvm *kvm)
2041{
2042 struct kvm_userspace_memory_region kvm_userspace_mem;
2043 int r = 0;
2044
72dc67a6 2045 down_write(&kvm->slots_lock);
bfc6d222 2046 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2047 goto out;
2048 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2049 kvm_userspace_mem.flags = 0;
2050 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2051 kvm_userspace_mem.memory_size = PAGE_SIZE;
2052 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2053 if (r)
2054 goto out;
72dc67a6 2055
bfc6d222 2056 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2057out:
72dc67a6 2058 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2059 return r;
2060}
2061
b7ebfb05
SY		 2062static int alloc_identity_pagetable(struct kvm *kvm)
2063{
2064 struct kvm_userspace_memory_region kvm_userspace_mem;
2065 int r = 0;
2066
2067 down_write(&kvm->slots_lock);
2068 if (kvm->arch.ept_identity_pagetable)
2069 goto out;
2070 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2071 kvm_userspace_mem.flags = 0;
2072 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2073 kvm_userspace_mem.memory_size = PAGE_SIZE;
2074 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2075 if (r)
2076 goto out;
2077
b7ebfb05
SY		 2078 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2079 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2080out:
2081 up_write(&kvm->slots_lock);
2082 return r;
2083}
2084
2384d2b3
SY		 2085static void allocate_vpid(struct vcpu_vmx *vmx)
2086{
2087 int vpid;
2088
2089 vmx->vpid = 0;
919818ab 2090 if (!enable_vpid)
2384d2b3
SY		 2091 return;
2092 spin_lock(&vmx_vpid_lock);
2093 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2094 if (vpid < VMX_NR_VPIDS) {
2095 vmx->vpid = vpid;
2096 __set_bit(vpid, vmx_vpid_bitmap);
2097 }
2098 spin_unlock(&vmx_vpid_lock);
2099}
2100
5897297b 2101static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2102{
3e7c73e9 2103 int f = sizeof(unsigned long);
25c5f225
SY		 2104
2105 if (!cpu_has_vmx_msr_bitmap())
2106 return;
2107
2108 /*
2109 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2110 * have the write-low and read-high bitmap offsets the wrong way round.
2111 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2112 */
25c5f225 2113 if (msr <= 0x1fff) {
3e7c73e9
AK		 2114 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2115 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2116 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2117 msr &= 0x1fff;
3e7c73e9
AK		 2118 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2119 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2120 }
25c5f225
SY		 2121}
2122
5897297b
AK		 2123static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2124{
2125 if (!longmode_only)
2126 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2127 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2128}
2129
6aa8b732
AK		 2130/*
2131 * Sets up the vmcs for emulated real mode.
2132 */
8b9cf98c 2133static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2134{
468d472f 2135 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2136 u32 junk;
53f658b3 2137 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2138 unsigned long a;
2139 struct descriptor_table dt;
2140 int i;
cd2276a7 2141 unsigned long kvm_vmx_return;
6e5d865c 2142 u32 exec_control;
6aa8b732 2143
6aa8b732 2144 /* I/O */
3e7c73e9
AK		 2145 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2146 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2147
25c5f225 2148 if (cpu_has_vmx_msr_bitmap())
5897297b 2149 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2150
6aa8b732
AK		 2151 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2152
6aa8b732 2153 /* Control */
1c3d14fe
YS		 2154 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2155 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2156
2157 exec_control = vmcs_config.cpu_based_exec_ctrl;
2158 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2159 exec_control &= ~CPU_BASED_TPR_SHADOW;
2160#ifdef CONFIG_X86_64
2161 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2162 CPU_BASED_CR8_LOAD_EXITING;
2163#endif
2164 }
089d034e 2165 if (!enable_ept)
d56f546d 2166 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2167 CPU_BASED_CR3_LOAD_EXITING |
2168 CPU_BASED_INVLPG_EXITING;
6e5d865c 2169 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2170
83ff3b9d
SY		 2171 if (cpu_has_secondary_exec_ctrls()) {
2172 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2173 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2174 exec_control &=
2175 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2176 if (vmx->vpid == 0)
2177 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2178 if (!enable_ept)
d56f546d 2179 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2180 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2181 }
f78e0e2e 2182
c7addb90
AK		 2183 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2184 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2185 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2186
2187 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2188 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2189 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2190
2191 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2192 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2193 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2194 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2195 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2196 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2197#ifdef CONFIG_X86_64
6aa8b732
AK		 2198 rdmsrl(MSR_FS_BASE, a);
2199 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2200 rdmsrl(MSR_GS_BASE, a);
2201 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2202#else
2203 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2204 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2205#endif
2206
2207 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2208
d6e88aec 2209 kvm_get_idt(&dt);
6aa8b732
AK		 2210 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2211
d77c26fc 2212 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2213 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2214 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2216 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2217
2218 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2219 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2220 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2221 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2222 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2223 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2224
468d472f
SY		 2225 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2226 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2227 host_pat = msr_low | ((u64) msr_high << 32);
2228 vmcs_write64(HOST_IA32_PAT, host_pat);
2229 }
2230 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2231 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2232 host_pat = msr_low | ((u64) msr_high << 32);
2233 /* Write the default value follow host pat */
2234 vmcs_write64(GUEST_IA32_PAT, host_pat);
2235 /* Keep arch.pat sync with GUEST_IA32_PAT */
2236 vmx->vcpu.arch.pat = host_pat;
2237 }
2238
6aa8b732
AK		 2239 for (i = 0; i < NR_VMX_MSR; ++i) {
2240 u32 index = vmx_msr_index[i];
2241 u32 data_low, data_high;
2242 u64 data;
a2fa3e9f 2243 int j = vmx->nmsrs;
6aa8b732
AK		 2244
2245 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2246 continue;
432bd6cb
AK		 2247 if (wrmsr_safe(index, data_low, data_high) < 0)
2248 continue;
6aa8b732 2249 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2250 vmx->host_msrs[j].index = index;
2251 vmx->host_msrs[j].reserved = 0;
2252 vmx->host_msrs[j].data = data;
2253 vmx->guest_msrs[j] = vmx->host_msrs[j];
2254 ++vmx->nmsrs;
6aa8b732 2255 }
6aa8b732 2256
1c3d14fe 2257 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2258
2259 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2260 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2261
e00c8cf2
AK		 2262 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2263 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2264
53f658b3
MT		 2265 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2266 rdtscll(tsc_this);
2267 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2268 tsc_base = tsc_this;
2269
2270 guest_write_tsc(0, tsc_base);
f78e0e2e 2271
e00c8cf2
AK		 2272 return 0;
2273}
2274
b7ebfb05
SY		 2275static int init_rmode(struct kvm *kvm)
2276{
2277 if (!init_rmode_tss(kvm))
2278 return 0;
2279 if (!init_rmode_identity_map(kvm))
2280 return 0;
2281 return 1;
2282}
2283
e00c8cf2
AK		 2284static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2285{
2286 struct vcpu_vmx *vmx = to_vmx(vcpu);
2287 u64 msr;
2288 int ret;
2289
5fdbf976 2290 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2291 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2292 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2293 ret = -ENOMEM;
2294 goto out;
2295 }
2296
ad312c7c 2297 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2298
3b86cd99
JK		 2299 vmx->soft_vnmi_blocked = 0;
2300
ad312c7c 2301 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2302 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2303 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2304 if (vmx->vcpu.vcpu_id == 0)
2305 msr |= MSR_IA32_APICBASE_BSP;
2306 kvm_set_apic_base(&vmx->vcpu, msr);
2307
2308 fx_init(&vmx->vcpu);
2309
5706be0d 2310 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2311 /*
2312 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2313 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2314 */
2315 if (vmx->vcpu.vcpu_id == 0) {
2316 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2317 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2318 } else {
ad312c7c
ZX		 2319 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2320 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2321 }
e00c8cf2
AK		 2322
2323 seg_setup(VCPU_SREG_DS);
2324 seg_setup(VCPU_SREG_ES);
2325 seg_setup(VCPU_SREG_FS);
2326 seg_setup(VCPU_SREG_GS);
2327 seg_setup(VCPU_SREG_SS);
2328
2329 vmcs_write16(GUEST_TR_SELECTOR, 0);
2330 vmcs_writel(GUEST_TR_BASE, 0);
2331 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2332 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2333
2334 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2335 vmcs_writel(GUEST_LDTR_BASE, 0);
2336 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2337 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2338
2339 vmcs_write32(GUEST_SYSENTER_CS, 0);
2340 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2341 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2342
2343 vmcs_writel(GUEST_RFLAGS, 0x02);
2344 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2345 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2346 else
5fdbf976
MT		 2347 kvm_rip_write(vcpu, 0);
2348 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2349
e00c8cf2
AK		 2350 vmcs_writel(GUEST_DR7, 0x400);
2351
2352 vmcs_writel(GUEST_GDTR_BASE, 0);
2353 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2354
2355 vmcs_writel(GUEST_IDTR_BASE, 0);
2356 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2357
2358 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2359 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2360 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2361
e00c8cf2
AK		 2362 /* Special registers */
2363 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2364
2365 setup_msrs(vmx);
2366
6aa8b732
AK		 2367 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2368
f78e0e2e
SY		 2369 if (cpu_has_vmx_tpr_shadow()) {
2370 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2371 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2372 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2373 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2374 vmcs_write32(TPR_THRESHOLD, 0);
2375 }
2376
2377 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2378 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2379 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2380
2384d2b3
SY		 2381 if (vmx->vpid != 0)
2382 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2383
ad312c7c
ZX		 2384 vmx->vcpu.arch.cr0 = 0x60000010;
2385 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2386 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2387 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2388 vmx_fpu_activate(&vmx->vcpu);
2389 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2390
2384d2b3
SY		 2391 vpid_sync_vcpu_all(vmx);
2392
3200f405 2393 ret = 0;
6aa8b732 2394
a89a8fb9
MG		 2395 /* HACK: Don't enable emulation on guest boot/reset */
2396 vmx->emulation_required = 0;
2397
6aa8b732 2398out:
3200f405 2399 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2400 return ret;
2401}
2402
95ba8273
GN		 2403void vmx_drop_interrupt_shadow(struct kvm_vcpu *vcpu)
2404{
2405 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2406 GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2407}
2408
3b86cd99
JK		 2409static void enable_irq_window(struct kvm_vcpu *vcpu)
2410{
2411 u32 cpu_based_vm_exec_control;
2412
2413 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2414 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2415 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2416}
2417
2418static void enable_nmi_window(struct kvm_vcpu *vcpu)
2419{
2420 u32 cpu_based_vm_exec_control;
2421
2422 if (!cpu_has_virtual_nmis()) {
2423 enable_irq_window(vcpu);
2424 return;
2425 }
2426
2427 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2428 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2429 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2430}
2431
85f455f7
ED		 2432static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2433{
9c8cba37
AK		 2434 struct vcpu_vmx *vmx = to_vmx(vcpu);
2435
2714d1d3
FEL		 2436 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2437
fa89a817 2438 ++vcpu->stat.irq_injections;
ad312c7c 2439 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2440 vmx->rmode.irq.pending = true;
2441 vmx->rmode.irq.vector = irq;
5fdbf976 2442 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2445 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2446 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2447 return;
2448 }
2449 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2450 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2451}
2452
f08864b4
SY		 2453static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2454{
66a5a347
JK		 2455 struct vcpu_vmx *vmx = to_vmx(vcpu);
2456
3b86cd99
JK		 2457 if (!cpu_has_virtual_nmis()) {
2458 /*
2459 * Tracking the NMI-blocked state in software is built upon
2460 * finding the next open IRQ window. This, in turn, depends on
2461 * well-behaving guests: They have to keep IRQs disabled at
2462 * least as long as the NMI handler runs. Otherwise we may
2463 * cause NMI nesting, maybe breaking the guest. But as this is
2464 * highly unlikely, we can live with the residual risk.
2465 */
2466 vmx->soft_vnmi_blocked = 1;
2467 vmx->vnmi_blocked_time = 0;
2468 }
2469
487b391d 2470 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2471 if (vcpu->arch.rmode.active) {
2472 vmx->rmode.irq.pending = true;
2473 vmx->rmode.irq.vector = NMI_VECTOR;
2474 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2475 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2476 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2477 INTR_INFO_VALID_MASK);
2478 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2479 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2480 return;
2481 }
f08864b4
SY		 2482 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2483 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2484}
2485
c4282df9 2486static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2487{
3b86cd99 2488 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2489 return 0;
33f089ca 2490
c4282df9
GN		 2491 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2492 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2493 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2494}
2495
78646121
GN		 2496static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2497{
c4282df9
GN		 2498 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2499 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2500 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2501}
2502
cbc94022
IE		 2503static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2504{
2505 int ret;
2506 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2507 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2508 .guest_phys_addr = addr,
2509 .memory_size = PAGE_SIZE * 3,
2510 .flags = 0,
2511 };
2512
2513 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2514 if (ret)
2515 return ret;
bfc6d222 2516 kvm->arch.tss_addr = addr;
cbc94022
IE		 2517 return 0;
2518}
2519
6aa8b732
AK		 2520static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2521 int vec, u32 err_code)
2522{
b3f37707
NK		 2523 /*
2524 * Instruction with address size override prefix opcode 0x67
2525 * Cause the #SS fault with 0 error code in VM86 mode.
2526 */
2527 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2528 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2529 return 1;
77ab6db0
JK		 2530 /*
2531 * Forward all other exceptions that are valid in real mode.
2532 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2533 * the required debugging infrastructure rework.
2534 */
2535 switch (vec) {
77ab6db0 2536 case DB_VECTOR:
d0bfb940
JK		 2537 if (vcpu->guest_debug &
2538 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2539 return 0;
2540 kvm_queue_exception(vcpu, vec);
2541 return 1;
77ab6db0 2542 case BP_VECTOR:
d0bfb940
JK		 2543 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2544 return 0;
2545 /* fall through */
2546 case DE_VECTOR:
77ab6db0
JK		 2547 case OF_VECTOR:
2548 case BR_VECTOR:
2549 case UD_VECTOR:
2550 case DF_VECTOR:
2551 case SS_VECTOR:
2552 case GP_VECTOR:
2553 case MF_VECTOR:
2554 kvm_queue_exception(vcpu, vec);
2555 return 1;
2556 }
6aa8b732
AK		 2557 return 0;
2558}
2559
2560static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2561{
1155f76a 2562 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2563 u32 intr_info, ex_no, error_code;
42dbaa5a 2564 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2565 u32 vect_info;
2566 enum emulation_result er;
2567
1155f76a 2568 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2569 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2570
2571 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2572 !is_page_fault(intr_info))
6aa8b732 2573 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2574 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2575
e4a41889 2576 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2577 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2578
2579 if (is_no_device(intr_info)) {
5fd86fcf 2580 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2581 return 1;
2582 }
2583
7aa81cc0 2584 if (is_invalid_opcode(intr_info)) {
571008da 2585 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2586 if (er != EMULATE_DONE)
7ee5d940 2587 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2588 return 1;
2589 }
2590
6aa8b732 2591 error_code = 0;
5fdbf976 2592 rip = kvm_rip_read(vcpu);
2e11384c 2593 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2594 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2595 if (is_page_fault(intr_info)) {
1439442c 2596 /* EPT won't cause page fault directly */
089d034e 2597 if (enable_ept)
1439442c 2598 BUG();
6aa8b732 2599 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2600 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2601 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2602 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2603 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2604 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2605 }
2606
ad312c7c 2607 if (vcpu->arch.rmode.active &&
6aa8b732 2608 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2609 error_code)) {
ad312c7c
ZX		 2610 if (vcpu->arch.halt_request) {
2611 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2612 return kvm_emulate_halt(vcpu);
2613 }
6aa8b732 2614 return 1;
72d6e5a0 2615 }
6aa8b732 2616
d0bfb940 2617 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2618 switch (ex_no) {
2619 case DB_VECTOR:
2620 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2621 if (!(vcpu->guest_debug &
2622 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2623 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2624 kvm_queue_exception(vcpu, DB_VECTOR);
2625 return 1;
2626 }
2627 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2628 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2629 /* fall through */
2630 case BP_VECTOR:
6aa8b732 2631 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2632 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2633 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2634 break;
2635 default:
d0bfb940
JK		 2636 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2637 kvm_run->ex.exception = ex_no;
2638 kvm_run->ex.error_code = error_code;
42dbaa5a 2639 break;
6aa8b732 2640 }
6aa8b732
AK		 2641 return 0;
2642}
2643
2644static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2645 struct kvm_run *kvm_run)
2646{
1165f5fe 2647 ++vcpu->stat.irq_exits;
2714d1d3 2648 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2649 return 1;
2650}
2651
988ad74f
AK		 2652static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2653{
2654 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2655 return 0;
2656}
6aa8b732 2657
6aa8b732
AK		 2658static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2659{
bfdaab09 2660 unsigned long exit_qualification;
34c33d16 2661 int size, in, string;
039576c0 2662 unsigned port;
6aa8b732 2663
1165f5fe 2664 ++vcpu->stat.io_exits;
bfdaab09 2665 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2666 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2667
2668 if (string) {
3427318f
LV		 2669 if (emulate_instruction(vcpu,
2670 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2671 return 0;
2672 return 1;
2673 }
2674
2675 size = (exit_qualification & 7) + 1;
2676 in = (exit_qualification & 8) != 0;
039576c0 2677 port = exit_qualification >> 16;
e70669ab 2678
e93f36bc 2679 skip_emulated_instruction(vcpu);
3090dd73 2680 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2681}
2682
102d8325
IM		 2683static void
2684vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2685{
2686 /*
2687 * Patch in the VMCALL instruction:
2688 */
2689 hypercall[0] = 0x0f;
2690 hypercall[1] = 0x01;
2691 hypercall[2] = 0xc1;
102d8325
IM		 2692}
2693
6aa8b732
AK		 2694static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2695{
bfdaab09 2696 unsigned long exit_qualification;
6aa8b732
AK		 2697 int cr;
2698 int reg;
2699
bfdaab09 2700 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2701 cr = exit_qualification & 15;
2702 reg = (exit_qualification >> 8) & 15;
2703 switch ((exit_qualification >> 4) & 3) {
2704 case 0: /* mov to cr */
5fdbf976
MT		 2705 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2706 (u32)kvm_register_read(vcpu, reg),
2707 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2708 handler);
6aa8b732
AK		 2709 switch (cr) {
2710 case 0:
5fdbf976 2711 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2712 skip_emulated_instruction(vcpu);
2713 return 1;
2714 case 3:
5fdbf976 2715 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2716 skip_emulated_instruction(vcpu);
2717 return 1;
2718 case 4:
5fdbf976 2719 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2720 skip_emulated_instruction(vcpu);
2721 return 1;
0a5fff19
GN		 2722 case 8: {
2723 u8 cr8_prev = kvm_get_cr8(vcpu);
2724 u8 cr8 = kvm_register_read(vcpu, reg);
2725 kvm_set_cr8(vcpu, cr8);
2726 skip_emulated_instruction(vcpu);
2727 if (irqchip_in_kernel(vcpu->kvm))
2728 return 1;
2729 if (cr8_prev <= cr8)
2730 return 1;
2731 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2732 return 0;
2733 }
6aa8b732
AK		 2734 };
2735 break;
25c4c276 2736 case 2: /* clts */
5fd86fcf 2737 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2738 vcpu->arch.cr0 &= ~X86_CR0_TS;
2739 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2740 vmx_fpu_activate(vcpu);
2714d1d3 2741 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2742 skip_emulated_instruction(vcpu);
2743 return 1;
6aa8b732
AK		 2744 case 1: /*mov from cr*/
2745 switch (cr) {
2746 case 3:
5fdbf976 2747 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2748 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2749 (u32)kvm_register_read(vcpu, reg),
2750 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2751 handler);
6aa8b732
AK		 2752 skip_emulated_instruction(vcpu);
2753 return 1;
2754 case 8:
5fdbf976 2755 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2756 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2757 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2758 skip_emulated_instruction(vcpu);
2759 return 1;
2760 }
2761 break;
2762 case 3: /* lmsw */
2d3ad1f4 2763 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2764
2765 skip_emulated_instruction(vcpu);
2766 return 1;
2767 default:
2768 break;
2769 }
2770 kvm_run->exit_reason = 0;
f0242478 2771 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2772 (int)(exit_qualification >> 4) & 3, cr);
2773 return 0;
2774}
2775
2776static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2777{
bfdaab09 2778 unsigned long exit_qualification;
6aa8b732
AK		 2779 unsigned long val;
2780 int dr, reg;
2781
42dbaa5a
JK		 2782 dr = vmcs_readl(GUEST_DR7);
2783 if (dr & DR7_GD) {
2784 /*
2785 * As the vm-exit takes precedence over the debug trap, we
2786 * need to emulate the latter, either for the host or the
2787 * guest debugging itself.
2788 */
2789 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2790 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2791 kvm_run->debug.arch.dr7 = dr;
2792 kvm_run->debug.arch.pc =
2793 vmcs_readl(GUEST_CS_BASE) +
2794 vmcs_readl(GUEST_RIP);
2795 kvm_run->debug.arch.exception = DB_VECTOR;
2796 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2797 return 0;
2798 } else {
2799 vcpu->arch.dr7 &= ~DR7_GD;
2800 vcpu->arch.dr6 |= DR6_BD;
2801 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2802 kvm_queue_exception(vcpu, DB_VECTOR);
2803 return 1;
2804 }
2805 }
2806
bfdaab09 2807 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2808 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2809 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2810 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2811 switch (dr) {
42dbaa5a
JK		 2812 case 0 ... 3:
2813 val = vcpu->arch.db[dr];
2814 break;
6aa8b732 2815 case 6:
42dbaa5a 2816 val = vcpu->arch.dr6;
6aa8b732
AK		 2817 break;
2818 case 7:
42dbaa5a 2819 val = vcpu->arch.dr7;
6aa8b732
AK		 2820 break;
2821 default:
2822 val = 0;
2823 }
5fdbf976 2824 kvm_register_write(vcpu, reg, val);
2714d1d3 2825 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2826 } else {
42dbaa5a
JK		 2827 val = vcpu->arch.regs[reg];
2828 switch (dr) {
2829 case 0 ... 3:
2830 vcpu->arch.db[dr] = val;
2831 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2832 vcpu->arch.eff_db[dr] = val;
2833 break;
2834 case 4 ... 5:
2835 if (vcpu->arch.cr4 & X86_CR4_DE)
2836 kvm_queue_exception(vcpu, UD_VECTOR);
2837 break;
2838 case 6:
2839 if (val & 0xffffffff00000000ULL) {
2840 kvm_queue_exception(vcpu, GP_VECTOR);
2841 break;
2842 }
2843 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2844 break;
2845 case 7:
2846 if (val & 0xffffffff00000000ULL) {
2847 kvm_queue_exception(vcpu, GP_VECTOR);
2848 break;
2849 }
2850 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2851 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2852 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2853 vcpu->arch.switch_db_regs =
2854 (val & DR7_BP_EN_MASK);
2855 }
2856 break;
2857 }
2858 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2859 }
6aa8b732
AK		 2860 skip_emulated_instruction(vcpu);
2861 return 1;
2862}
2863
2864static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2865{
06465c5a
AK		 2866 kvm_emulate_cpuid(vcpu);
2867 return 1;
6aa8b732
AK		 2868}
2869
2870static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2871{
ad312c7c 2872 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2873 u64 data;
2874
2875 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2876 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2877 return 1;
2878 }
2879
2714d1d3
FEL		 2880 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2881 handler);
2882
6aa8b732 2883 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2884 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2885 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2886 skip_emulated_instruction(vcpu);
2887 return 1;
2888}
2889
2890static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2891{
ad312c7c
ZX		 2892 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2893 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2894 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2895
2714d1d3
FEL		 2896 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2897 handler);
2898
6aa8b732 2899 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2900 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2901 return 1;
2902 }
2903
2904 skip_emulated_instruction(vcpu);
2905 return 1;
2906}
2907
6e5d865c
YS		 2908static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2909 struct kvm_run *kvm_run)
2910{
2911 return 1;
2912}
2913
6aa8b732
AK		 2914static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2915 struct kvm_run *kvm_run)
2916{
85f455f7
ED		 2917 u32 cpu_based_vm_exec_control;
2918
2919 /* clear pending irq */
2920 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2921 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2922 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2923
2924 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2925 ++vcpu->stat.irq_window_exits;
2714d1d3 2926
c1150d8c
DL		 2927 /*
2928 * If the user space waits to inject interrupts, exit as soon as
2929 * possible
2930 */
8061823a
GN		 2931 if (!irqchip_in_kernel(vcpu->kvm) &&
2932 kvm_run->request_interrupt_window &&
2933 !kvm_cpu_has_interrupt(vcpu)) {
c1150d8c 2934 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2935 return 0;
2936 }
6aa8b732
AK		 2937 return 1;
2938}
2939
2940static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2941{
2942 skip_emulated_instruction(vcpu);
d3bef15f 2943 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2944}
2945
c21415e8
IM		 2946static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2947{
510043da 2948 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2949 kvm_emulate_hypercall(vcpu);
2950 return 1;
c21415e8
IM		 2951}
2952
a7052897
MT		 2953static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2954{
f9c617f6 2955 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 2956
2957 kvm_mmu_invlpg(vcpu, exit_qualification);
2958 skip_emulated_instruction(vcpu);
2959 return 1;
2960}
2961
e5edaa01
ED		 2962static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2963{
2964 skip_emulated_instruction(vcpu);
2965 /* TODO: Add support for VT-d/pass-through device */
2966 return 1;
2967}
2968
f78e0e2e
SY		 2969static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2970{
f9c617f6 2971 unsigned long exit_qualification;
f78e0e2e
SY		 2972 enum emulation_result er;
2973 unsigned long offset;
2974
f9c617f6 2975 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 2976 offset = exit_qualification & 0xffful;
2977
2978 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2979
2980 if (er != EMULATE_DONE) {
2981 printk(KERN_ERR
2982 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2983 offset);
2984 return -ENOTSUPP;
2985 }
2986 return 1;
2987}
2988
37817f29
IE		 2989static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2990{
60637aac 2991 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 2992 unsigned long exit_qualification;
2993 u16 tss_selector;
64a7ec06
GN		 2994 int reason, type, idt_v;
2995
2996 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
2997 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 2998
2999 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3000
3001 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3002 if (reason == TASK_SWITCH_GATE && idt_v) {
3003 switch (type) {
3004 case INTR_TYPE_NMI_INTR:
3005 vcpu->arch.nmi_injected = false;
3006 if (cpu_has_virtual_nmis())
3007 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3008 GUEST_INTR_STATE_NMI);
3009 break;
3010 case INTR_TYPE_EXT_INTR:
3011 kvm_clear_interrupt_queue(vcpu);
3012 break;
3013 case INTR_TYPE_HARD_EXCEPTION:
3014 case INTR_TYPE_SOFT_EXCEPTION:
3015 kvm_clear_exception_queue(vcpu);
3016 break;
3017 default:
3018 break;
3019 }
60637aac 3020 }
37817f29
IE		 3021 tss_selector = exit_qualification;
3022
64a7ec06
GN		 3023 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3024 type != INTR_TYPE_EXT_INTR &&
3025 type != INTR_TYPE_NMI_INTR))
3026 skip_emulated_instruction(vcpu);
3027
42dbaa5a
JK		 3028 if (!kvm_task_switch(vcpu, tss_selector, reason))
3029 return 0;
3030
3031 /* clear all local breakpoint enable flags */
3032 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3033
3034 /*
3035 * TODO: What about debug traps on tss switch?
3036 * Are we supposed to inject them and update dr6?
3037 */
3038
3039 return 1;
37817f29
IE		 3040}
3041
1439442c
SY		 3042static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3043{
f9c617f6 3044 unsigned long exit_qualification;
1439442c 3045 gpa_t gpa;
1439442c 3046 int gla_validity;
1439442c 3047
f9c617f6 3048 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3049
3050 if (exit_qualification & (1 << 6)) {
3051 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3052 return -ENOTSUPP;
3053 }
3054
3055 gla_validity = (exit_qualification >> 7) & 0x3;
3056 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3057 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3058 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3059 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3060 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3061 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3062 (long unsigned int)exit_qualification);
3063 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3064 kvm_run->hw.hardware_exit_reason = 0;
3065 return -ENOTSUPP;
3066 }
3067
3068 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
49cd7d22 3069 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3070}
3071
f08864b4
SY		 3072static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3073{
3074 u32 cpu_based_vm_exec_control;
3075
3076 /* clear pending NMI */
3077 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3078 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3079 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3080 ++vcpu->stat.nmi_window_exits;
3081
3082 return 1;
3083}
3084
ea953ef0
MG		 3085static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3086 struct kvm_run *kvm_run)
3087{
8b3079a5
AK		 3088 struct vcpu_vmx *vmx = to_vmx(vcpu);
3089 enum emulation_result err = EMULATE_DONE;
ea953ef0
MG		 3090
3091 preempt_enable();
3092 local_irq_enable();
3093
3094 while (!guest_state_valid(vcpu)) {
3095 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3096
1d5a4d9b
GT		 3097 if (err == EMULATE_DO_MMIO)
3098 break;
3099
3100 if (err != EMULATE_DONE) {
3101 kvm_report_emulation_failure(vcpu, "emulation failure");
3102 return;
ea953ef0
MG		 3103 }
3104
3105 if (signal_pending(current))
3106 break;
3107 if (need_resched())
3108 schedule();
3109 }
3110
3111 local_irq_disable();
3112 preempt_disable();
8b3079a5
AK		 3113
3114 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3115}
3116
6aa8b732
AK		 3117/*
3118 * The exit handlers return 1 if the exit was handled fully and guest execution
3119 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3120 * to be done to userspace and return 0.
3121 */
3122static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3123 struct kvm_run *kvm_run) = {
3124 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3125 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3126 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3127 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3128 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3129 [EXIT_REASON_CR_ACCESS] = handle_cr,
3130 [EXIT_REASON_DR_ACCESS] = handle_dr,
3131 [EXIT_REASON_CPUID] = handle_cpuid,
3132 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3133 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3134 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3135 [EXIT_REASON_HLT] = handle_halt,
a7052897 3136 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3137 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3138 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3139 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3140 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3141 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3142 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3143};
3144
3145static const int kvm_vmx_max_exit_handlers =
50a3485c 3146 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3147
3148/*
3149 * The guest has exited. See if we can fix it or if we need userspace
3150 * assistance.
3151 */
6062d012 3152static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 3153{
6aa8b732 3154 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3155 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3156 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3157
5fdbf976
MT		 3158 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3159 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3160
1d5a4d9b
GT		 3161 /* If we need to emulate an MMIO from handle_invalid_guest_state
3162 * we just return 0 */
10f32d84
AK		 3163 if (vmx->emulation_required && emulate_invalid_guest_state) {
3164 if (guest_state_valid(vcpu))
3165 vmx->emulation_required = 0;
8b3079a5 3166 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3167 }
1d5a4d9b 3168
1439442c
SY		 3169 /* Access CR3 don't cause VMExit in paging mode, so we need
3170 * to sync with guest real CR3. */
089d034e 3171 if (enable_ept && is_paging(vcpu)) {
1439442c
SY		 3172 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3173 ept_load_pdptrs(vcpu);
3174 }
3175
29bd8a78
AK		 3176 if (unlikely(vmx->fail)) {
3177 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3178 kvm_run->fail_entry.hardware_entry_failure_reason
3179 = vmcs_read32(VM_INSTRUCTION_ERROR);
3180 return 0;
3181 }
6aa8b732 3182
d77c26fc 3183 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3184 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3185 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3186 exit_reason != EXIT_REASON_TASK_SWITCH))
3187 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3188 "(0x%x) and exit reason is 0x%x\n",
3189 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3190
3191 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3192 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3193 vmx->soft_vnmi_blocked = 0;
3b86cd99 3194 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3195 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3196 /*
3197 * This CPU don't support us in finding the end of an
3198 * NMI-blocked window if the guest runs with IRQs
3199 * disabled. So we pull the trigger after 1 s of
3200 * futile waiting, but inform the user about this.
3201 */
3202 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3203 "state on VCPU %d after 1 s timeout\n",
3204 __func__, vcpu->vcpu_id);
3205 vmx->soft_vnmi_blocked = 0;
3b86cd99 3206 }
3b86cd99
JK		 3207 }
3208
6aa8b732
AK		 3209 if (exit_reason < kvm_vmx_max_exit_handlers
3210 && kvm_vmx_exit_handlers[exit_reason])
3211 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3212 else {
3213 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3214 kvm_run->hw.hardware_exit_reason = exit_reason;
3215 }
3216 return 0;
3217}
3218
95ba8273 3219static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3220{
95ba8273 3221 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3222 vmcs_write32(TPR_THRESHOLD, 0);
3223 return;
3224 }
3225
95ba8273 3226 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3227}
3228
cf393f75
AK		 3229static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3230{
3231 u32 exit_intr_info;
7b4a25cb 3232 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3233 bool unblock_nmi;
3234 u8 vector;
668f612f
AK		 3235 int type;
3236 bool idtv_info_valid;
cf393f75 3237
7b4a25cb 3238 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
cf393f75
AK		 3239 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3240 if (cpu_has_virtual_nmis()) {
3241 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3242 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3243 /*
7b4a25cb 3244 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3245 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3246 * a guest IRET fault.
7b4a25cb
GN		 3247 * SDM 3: 23.2.2 (September 2008)
3248 * Bit 12 is undefined in any of the following cases:
3249 * If the VM exit sets the valid bit in the IDT-vectoring
3250 * information field.
3251 * If the VM exit is due to a double fault.
cf393f75 3252 */
7b4a25cb
GN		 3253 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3254 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3255 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3256 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3257 } else if (unlikely(vmx->soft_vnmi_blocked))
3258 vmx->vnmi_blocked_time +=
3259 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3260
37b96e98
GN		 3261 vmx->vcpu.arch.nmi_injected = false;
3262 kvm_clear_exception_queue(&vmx->vcpu);
3263 kvm_clear_interrupt_queue(&vmx->vcpu);
3264
3265 if (!idtv_info_valid)
3266 return;
3267
668f612f
AK		 3268 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3269 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3270
64a7ec06 3271 switch (type) {
37b96e98
GN		 3272 case INTR_TYPE_NMI_INTR:
3273 vmx->vcpu.arch.nmi_injected = true;
668f612f 3274 /*
7b4a25cb 3275 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3276 * Clear bit "block by NMI" before VM entry if a NMI
3277 * delivery faulted.
668f612f 3278 */
37b96e98
GN		 3279 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3280 GUEST_INTR_STATE_NMI);
3281 break;
3282 case INTR_TYPE_HARD_EXCEPTION:
3283 case INTR_TYPE_SOFT_EXCEPTION:
35920a35 3284 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3285 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3286 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3287 } else
3288 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98
GN		 3289 break;
3290 case INTR_TYPE_EXT_INTR:
f7d9238f 3291 kvm_queue_interrupt(&vmx->vcpu, vector);
37b96e98
GN		 3292 break;
3293 default:
3294 break;
f7d9238f 3295 }
cf393f75
AK		 3296}
3297
9c8cba37
AK		 3298/*
3299 * Failure to inject an interrupt should give us the information
3300 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3301 * when fetching the interrupt redirection bitmap in the real-mode
3302 * tss, this doesn't happen. So we do it ourselves.
3303 */
3304static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3305{
3306 vmx->rmode.irq.pending = 0;
5fdbf976 3307 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3308 return;
5fdbf976 3309 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3310 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3311 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3312 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3313 return;
3314 }
3315 vmx->idt_vectoring_info =
3316 VECTORING_INFO_VALID_MASK
3317 | INTR_TYPE_EXT_INTR
3318 | vmx->rmode.irq.vector;
3319}
3320
c801949d
AK		 3321#ifdef CONFIG_X86_64
3322#define R "r"
3323#define Q "q"
3324#else
3325#define R "e"
3326#define Q "l"
3327#endif
3328
04d2cc77 3329static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3330{
a2fa3e9f 3331 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3332 u32 intr_info;
e6adf283 3333
3b86cd99
JK		 3334 /* Record the guest's net vcpu time for enforced NMI injections. */
3335 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3336 vmx->entry_time = ktime_get();
3337
a89a8fb9
MG		 3338 /* Handle invalid guest state instead of entering VMX */
3339 if (vmx->emulation_required && emulate_invalid_guest_state) {
3340 handle_invalid_guest_state(vcpu, kvm_run);
3341 return;
3342 }
3343
5fdbf976
MT		 3344 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3345 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3346 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3347 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3348
e6adf283
AK		 3349 /*
3350 * Loading guest fpu may have cleared host cr0.ts
3351 */
3352 vmcs_writel(HOST_CR0, read_cr0());
3353
42dbaa5a
JK		 3354 set_debugreg(vcpu->arch.dr6, 6);
3355
d77c26fc 3356 asm(
6aa8b732 3357 /* Store host registers */
c801949d
AK		 3358 "push %%"R"dx; push %%"R"bp;"
3359 "push %%"R"cx \n\t"
313dbd49
AK		 3360 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3361 "je 1f \n\t"
3362 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3363 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3364 "1: \n\t"
6aa8b732 3365 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3366 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3367 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3368 "mov %c[cr2](%0), %%"R"ax \n\t"
3369 "mov %%"R"ax, %%cr2 \n\t"
3370 "mov %c[rax](%0), %%"R"ax \n\t"
3371 "mov %c[rbx](%0), %%"R"bx \n\t"
3372 "mov %c[rdx](%0), %%"R"dx \n\t"
3373 "mov %c[rsi](%0), %%"R"si \n\t"
3374 "mov %c[rdi](%0), %%"R"di \n\t"
3375 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3376#ifdef CONFIG_X86_64
e08aa78a
AK		 3377 "mov %c[r8](%0), %%r8 \n\t"
3378 "mov %c[r9](%0), %%r9 \n\t"
3379 "mov %c[r10](%0), %%r10 \n\t"
3380 "mov %c[r11](%0), %%r11 \n\t"
3381 "mov %c[r12](%0), %%r12 \n\t"
3382 "mov %c[r13](%0), %%r13 \n\t"
3383 "mov %c[r14](%0), %%r14 \n\t"
3384 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3385#endif
c801949d
AK		 3386 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3387
6aa8b732 3388 /* Enter guest mode */
cd2276a7 3389 "jne .Llaunched \n\t"
4ecac3fd 3390 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3391 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3392 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3393 ".Lkvm_vmx_return: "
6aa8b732 3394 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3395 "xchg %0, (%%"R"sp) \n\t"
3396 "mov %%"R"ax, %c[rax](%0) \n\t"
3397 "mov %%"R"bx, %c[rbx](%0) \n\t"
3398 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3399 "mov %%"R"dx, %c[rdx](%0) \n\t"
3400 "mov %%"R"si, %c[rsi](%0) \n\t"
3401 "mov %%"R"di, %c[rdi](%0) \n\t"
3402 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3403#ifdef CONFIG_X86_64
e08aa78a
AK		 3404 "mov %%r8, %c[r8](%0) \n\t"
3405 "mov %%r9, %c[r9](%0) \n\t"
3406 "mov %%r10, %c[r10](%0) \n\t"
3407 "mov %%r11, %c[r11](%0) \n\t"
3408 "mov %%r12, %c[r12](%0) \n\t"
3409 "mov %%r13, %c[r13](%0) \n\t"
3410 "mov %%r14, %c[r14](%0) \n\t"
3411 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3412#endif
c801949d
AK		 3413 "mov %%cr2, %%"R"ax \n\t"
3414 "mov %%"R"ax, %c[cr2](%0) \n\t"
3415
3416 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3417 "setbe %c[fail](%0) \n\t"
3418 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3419 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3420 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3421 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3422 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3423 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3424 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3425 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3426 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3427 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3428 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3429#ifdef CONFIG_X86_64
ad312c7c
ZX		 3430 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3431 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3432 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3433 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3434 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3435 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3436 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3437 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3438#endif
ad312c7c 3439 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3440 : "cc", "memory"
c801949d 3441 , R"bx", R"di", R"si"
c2036300 3442#ifdef CONFIG_X86_64
c2036300
LV		 3443 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3444#endif
3445 );
6aa8b732 3446
5fdbf976
MT		 3447 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3448 vcpu->arch.regs_dirty = 0;
3449
42dbaa5a
JK		 3450 get_debugreg(vcpu->arch.dr6, 6);
3451
1155f76a 3452 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3453 if (vmx->rmode.irq.pending)
3454 fixup_rmode_irq(vmx);
1155f76a 3455
d77c26fc 3456 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3457 vmx->launched = 1;
1b6269db
AK		 3458
3459 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3460
3461 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3462 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3463 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3464 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3465 asm("int $2");
2714d1d3 3466 }
cf393f75
AK		 3467
3468 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3469}
3470
c801949d
AK		 3471#undef R
3472#undef Q
3473
6aa8b732
AK		 3474static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3475{
a2fa3e9f
GH		 3476 struct vcpu_vmx *vmx = to_vmx(vcpu);
3477
3478 if (vmx->vmcs) {
543e4243 3479 vcpu_clear(vmx);
a2fa3e9f
GH		 3480 free_vmcs(vmx->vmcs);
3481 vmx->vmcs = NULL;
6aa8b732
AK		 3482 }
3483}
3484
3485static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3486{
fb3f0f51
RR		 3487 struct vcpu_vmx *vmx = to_vmx(vcpu);
3488
2384d2b3
SY		 3489 spin_lock(&vmx_vpid_lock);
3490 if (vmx->vpid != 0)
3491 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3492 spin_unlock(&vmx_vpid_lock);
6aa8b732 3493 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3494 kfree(vmx->host_msrs);
3495 kfree(vmx->guest_msrs);
3496 kvm_vcpu_uninit(vcpu);
a4770347 3497 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3498}
3499
fb3f0f51 3500static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3501{
fb3f0f51 3502 int err;
c16f862d 3503 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3504 int cpu;
6aa8b732 3505
a2fa3e9f 3506 if (!vmx)
fb3f0f51
RR		 3507 return ERR_PTR(-ENOMEM);
3508
2384d2b3
SY		 3509 allocate_vpid(vmx);
3510
fb3f0f51
RR		 3511 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3512 if (err)
3513 goto free_vcpu;
965b58a5 3514
a2fa3e9f 3515 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3516 if (!vmx->guest_msrs) {
3517 err = -ENOMEM;
3518 goto uninit_vcpu;
3519 }
965b58a5 3520
a2fa3e9f
GH		 3521 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3522 if (!vmx->host_msrs)
fb3f0f51 3523 goto free_guest_msrs;
965b58a5 3524
a2fa3e9f
GH		 3525 vmx->vmcs = alloc_vmcs();
3526 if (!vmx->vmcs)
fb3f0f51 3527 goto free_msrs;
a2fa3e9f
GH		 3528
3529 vmcs_clear(vmx->vmcs);
3530
15ad7146
AK		 3531 cpu = get_cpu();
3532 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3533 err = vmx_vcpu_setup(vmx);
fb3f0f51 3534 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3535 put_cpu();
fb3f0f51
RR		 3536 if (err)
3537 goto free_vmcs;
5e4a0b3c
MT		 3538 if (vm_need_virtualize_apic_accesses(kvm))
3539 if (alloc_apic_access_page(kvm) != 0)
3540 goto free_vmcs;
fb3f0f51 3541
089d034e 3542 if (enable_ept)
b7ebfb05
SY		 3543 if (alloc_identity_pagetable(kvm) != 0)
3544 goto free_vmcs;
3545
fb3f0f51
RR		 3546 return &vmx->vcpu;
3547
3548free_vmcs:
3549 free_vmcs(vmx->vmcs);
3550free_msrs:
3551 kfree(vmx->host_msrs);
3552free_guest_msrs:
3553 kfree(vmx->guest_msrs);
3554uninit_vcpu:
3555 kvm_vcpu_uninit(&vmx->vcpu);
3556free_vcpu:
a4770347 3557 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3558 return ERR_PTR(err);
6aa8b732
AK		 3559}
3560
002c7f7c
YS		 3561static void __init vmx_check_processor_compat(void *rtn)
3562{
3563 struct vmcs_config vmcs_conf;
3564
3565 *(int *)rtn = 0;
3566 if (setup_vmcs_config(&vmcs_conf) < 0)
3567 *(int *)rtn = -EIO;
3568 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3569 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3570 smp_processor_id());
3571 *(int *)rtn = -EIO;
3572 }
3573}
3574
67253af5
SY		 3575static int get_ept_level(void)
3576{
3577 return VMX_EPT_DEFAULT_GAW + 1;
3578}
3579
64d4d521
SY		 3580static int vmx_get_mt_mask_shift(void)
3581{
3582 return VMX_EPT_MT_EPTE_SHIFT;
3583}
3584
cbdd1bea 3585static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3586 .cpu_has_kvm_support = cpu_has_kvm_support,
3587 .disabled_by_bios = vmx_disabled_by_bios,
3588 .hardware_setup = hardware_setup,
3589 .hardware_unsetup = hardware_unsetup,
002c7f7c 3590 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3591 .hardware_enable = hardware_enable,
3592 .hardware_disable = hardware_disable,
04547156 3593 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3594
3595 .vcpu_create = vmx_create_vcpu,
3596 .vcpu_free = vmx_free_vcpu,
04d2cc77 3597 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3598
04d2cc77 3599 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3600 .vcpu_load = vmx_vcpu_load,
3601 .vcpu_put = vmx_vcpu_put,
3602
3603 .set_guest_debug = set_guest_debug,
3604 .get_msr = vmx_get_msr,
3605 .set_msr = vmx_set_msr,
3606 .get_segment_base = vmx_get_segment_base,
3607 .get_segment = vmx_get_segment,
3608 .set_segment = vmx_set_segment,
2e4d2653 3609 .get_cpl = vmx_get_cpl,
6aa8b732 3610 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3611 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3612 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3613 .set_cr3 = vmx_set_cr3,
3614 .set_cr4 = vmx_set_cr4,
6aa8b732 3615 .set_efer = vmx_set_efer,
6aa8b732
AK		 3616 .get_idt = vmx_get_idt,
3617 .set_idt = vmx_set_idt,
3618 .get_gdt = vmx_get_gdt,
3619 .set_gdt = vmx_set_gdt,
5fdbf976 3620 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3621 .get_rflags = vmx_get_rflags,
3622 .set_rflags = vmx_set_rflags,
3623
3624 .tlb_flush = vmx_flush_tlb,
6aa8b732 3625
6aa8b732 3626 .run = vmx_vcpu_run,
6062d012 3627 .handle_exit = vmx_handle_exit,
6aa8b732 3628 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3629 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3630 .set_irq = vmx_inject_irq,
95ba8273 3631 .set_nmi = vmx_inject_nmi,
298101da 3632 .queue_exception = vmx_queue_exception,
78646121 3633 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3634 .nmi_allowed = vmx_nmi_allowed,
3635 .enable_nmi_window = enable_nmi_window,
3636 .enable_irq_window = enable_irq_window,
3637 .update_cr8_intercept = update_cr8_intercept,
3638 .drop_interrupt_shadow = vmx_drop_interrupt_shadow,
3639
cbc94022 3640 .set_tss_addr = vmx_set_tss_addr,
67253af5 3641 .get_tdp_level = get_ept_level,
64d4d521 3642 .get_mt_mask_shift = vmx_get_mt_mask_shift,
6aa8b732
AK		 3643};
3644
3645static int __init vmx_init(void)
3646{
fdef3ad1
HQ		 3647 int r;
3648
3e7c73e9 3649 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3650 if (!vmx_io_bitmap_a)
3651 return -ENOMEM;
3652
3e7c73e9 3653 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3654 if (!vmx_io_bitmap_b) {
3655 r = -ENOMEM;
3656 goto out;
3657 }
3658
5897297b
AK		 3659 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3660 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 3661 r = -ENOMEM;
3662 goto out1;
3663 }
3664
5897297b
AK		 3665 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3666 if (!vmx_msr_bitmap_longmode) {
3667 r = -ENOMEM;
3668 goto out2;
3669 }
3670
fdef3ad1
HQ		 3671 /*
3672 * Allow direct access to the PC debug port (it is often used for I/O
3673 * delays, but the vmexits simply slow things down).
3674 */
3e7c73e9
AK		 3675 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3676 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 3677
3e7c73e9 3678 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 3679
5897297b
AK		 3680 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3681 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 3682
2384d2b3
SY		 3683 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3684
cb498ea2 3685 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3686 if (r)
5897297b 3687 goto out3;
25c5f225 3688
5897297b
AK		 3689 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3690 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3691 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3692 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3693 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3694 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 3695
089d034e 3696 if (enable_ept) {
1439442c 3697 bypass_guest_pf = 0;
5fdbcb9d 3698 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 3699 VMX_EPT_WRITABLE_MASK);
534e38b4 3700 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
64d4d521
SY		 3701 VMX_EPT_EXECUTABLE_MASK,
3702 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
5fdbcb9d
SY		 3703 kvm_enable_tdp();
3704 } else
3705 kvm_disable_tdp();
1439442c 3706
c7addb90
AK		 3707 if (bypass_guest_pf)
3708 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3709
1439442c
SY		 3710 ept_sync_global();
3711
fdef3ad1
HQ		 3712 return 0;
3713
5897297b
AK		 3714out3:
3715 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 3716out2:
5897297b 3717 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 3718out1:
3e7c73e9 3719 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 3720out:
3e7c73e9 3721 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3722 return r;
6aa8b732
AK		 3723}
3724
3725static void __exit vmx_exit(void)
3726{
5897297b
AK		 3727 free_page((unsigned long)vmx_msr_bitmap_legacy);
3728 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 3729 free_page((unsigned long)vmx_io_bitmap_b);
3730 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3731
cb498ea2 3732 kvm_exit();
6aa8b732
AK		 3733}
3734
3735module_init(vmx_init)
3736module_exit(vmx_exit)
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