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x86: kvmclock: drop rdtsc_barrier()
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
6aa8b732 49
229456fc
MT		 50#include "trace.h"
51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
789 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
705699a1 812static int vmx_vm_has_apicv(struct kvm *kvm);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
31299944 949static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 950{
04547156 951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987}
988
989static inline bool cpu_has_vmx_apicv(void)
990{
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
994}
995
04547156
SY		 996static inline bool cpu_has_vmx_flexpriority(void)
997{
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1000}
1001
e799794e
MT		 1002static inline bool cpu_has_vmx_ept_execute_only(void)
1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1005}
1006
e799794e
MT		 1007static inline bool cpu_has_vmx_ept_2m_page(void)
1008{
31299944 1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1010}
1011
878403b7
SY		 1012static inline bool cpu_has_vmx_ept_1g_page(void)
1013{
31299944 1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1015}
1016
4bc9b982
SY		 1017static inline bool cpu_has_vmx_ept_4levels(void)
1018{
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020}
1021
83c3a331
XH		 1022static inline bool cpu_has_vmx_ept_ad_bits(void)
1023{
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1025}
1026
31299944 1027static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1028{
31299944 1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1033{
31299944 1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1035}
1036
518c8aee
GJ		 1037static inline bool cpu_has_vmx_invvpid_single(void)
1038{
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040}
1041
b9d762fa
GJ		 1042static inline bool cpu_has_vmx_invvpid_global(void)
1043{
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045}
1046
31299944 1047static inline bool cpu_has_vmx_ept(void)
d56f546d 1048{
04547156
SY		 1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1051}
1052
31299944 1053static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057}
1058
31299944 1059static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1060{
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063}
1064
31299944 1065static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1066{
6d3e435e 1067 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1068}
1069
31299944 1070static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1071{
04547156
SY		 1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1074}
1075
31299944 1076static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1077{
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1080}
1081
ad756a16
MJ		 1082static inline bool cpu_has_vmx_invpcid(void)
1083{
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1086}
1087
31299944 1088static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1089{
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f5f48ee1
SY		 1093static inline bool cpu_has_vmx_wbinvd_exit(void)
1094{
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1097}
1098
abc4fc58
AG		 1099static inline bool cpu_has_vmx_shadow_vmcs(void)
1100{
1101 u64 vmx_msr;
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105 return false;
1106
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1109}
1110
843e4330
KH		 1111static inline bool cpu_has_vmx_pml(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114}
1115
04547156
SY		 1116static inline bool report_flexpriority(void)
1117{
1118 return flexpriority_enabled;
1119}
1120
fe3ef05c
NHE		 1121static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122{
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1124}
1125
1126static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127{
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1131}
1132
f5c4368f 1133static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1134{
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136}
1137
f4124500
JK		 1138static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139{
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1142}
1143
155a97a3
NHE		 1144static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145{
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147}
1148
81dc01f7
WL		 1149static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150{
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1153}
1154
f2b93280
WV		 1155static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156{
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158}
1159
82f0dd4b
WV		 1160static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161{
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163}
1164
608406e2
WV		 1165static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166{
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168}
1169
705699a1
WV		 1170static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171{
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173}
1174
644d711a
NHE		 1175static inline bool is_exception(u32 intr_info)
1176{
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179}
1180
533558bc
JK		 1181static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182 u32 exit_intr_info,
1183 unsigned long exit_qualification);
7c177938
NHE		 1184static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1187
8b9cf98c 1188static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1189{
1190 int i;
1191
a2fa3e9f 1192 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1194 return i;
1195 return -1;
1196}
1197
2384d2b3
SY		 1198static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199{
1200 struct {
1201 u64 vpid : 16;
1202 u64 rsvd : 48;
1203 u64 gva;
1204 } operand = { vpid, 0, gva };
1205
4ecac3fd 1206 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1210}
1211
1439442c
SY		 1212static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213{
1214 struct {
1215 u64 eptp, gpa;
1216 } operand = {eptp, gpa};
1217
4ecac3fd 1218 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1222}
1223
26bb0981 1224static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1225{
1226 int i;
1227
8b9cf98c 1228 i = __find_msr_index(vmx, msr);
a75beee6 1229 if (i >= 0)
a2fa3e9f 1230 return &vmx->guest_msrs[i];
8b6d44c7 1231 return NULL;
7725f0ba
AK		 1232}
1233
6aa8b732
AK		 1234static void vmcs_clear(struct vmcs *vmcs)
1235{
1236 u64 phys_addr = __pa(vmcs);
1237 u8 error;
1238
4ecac3fd 1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1241 : "cc", "memory");
1242 if (error)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244 vmcs, phys_addr);
1245}
1246
d462b819
NHE		 1247static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248{
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1252}
1253
7725b894
DX		 1254static void vmcs_load(struct vmcs *vmcs)
1255{
1256 u64 phys_addr = __pa(vmcs);
1257 u8 error;
1258
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1261 : "cc", "memory");
1262 if (error)
2844d849 1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1264 vmcs, phys_addr);
1265}
1266
8f536b76
ZY		 1267#ifdef CONFIG_KEXEC
1268/*
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1271 * default.
1272 */
1273static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275static inline void crash_enable_local_vmclear(int cpu)
1276{
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278}
1279
1280static inline void crash_disable_local_vmclear(int cpu)
1281{
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283}
1284
1285static inline int crash_local_vmclear_enabled(int cpu)
1286{
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288}
1289
1290static void crash_vmclear_local_loaded_vmcss(void)
1291{
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1294
1295 if (!crash_local_vmclear_enabled(cpu))
1296 return;
1297
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1301}
1302#else
1303static inline void crash_enable_local_vmclear(int cpu) { }
1304static inline void crash_disable_local_vmclear(int cpu) { }
1305#endif /* CONFIG_KEXEC */
1306
d462b819 1307static void __loaded_vmcs_clear(void *arg)
6aa8b732 1308{
d462b819 1309 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1310 int cpu = raw_smp_processor_id();
6aa8b732 1311
d462b819
NHE		 1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1315 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1316 crash_disable_local_vmclear(cpu);
d462b819 1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1318
1319 /*
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1324 */
1325 smp_wmb();
1326
d462b819 1327 loaded_vmcs_init(loaded_vmcs);
8f536b76 1328 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1329}
1330
d462b819 1331static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1332{
e6c7d321
XG		 1333 int cpu = loaded_vmcs->cpu;
1334
1335 if (cpu != -1)
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1338}
1339
1760dd49 1340static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1341{
1342 if (vmx->vpid == 0)
1343 return;
1344
518c8aee
GJ		 1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1347}
1348
b9d762fa
GJ		 1349static inline void vpid_sync_vcpu_global(void)
1350{
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353}
1354
1355static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356{
1357 if (cpu_has_vmx_invvpid_single())
1760dd49 1358 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1359 else
1360 vpid_sync_vcpu_global();
1361}
1362
1439442c
SY		 1363static inline void ept_sync_global(void)
1364{
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367}
1368
1369static inline void ept_sync_context(u64 eptp)
1370{
089d034e 1371 if (enable_ept) {
1439442c
SY		 1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374 else
1375 ept_sync_global();
1376 }
1377}
1378
96304217 1379static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1380{
5e520e62 1381 unsigned long value;
6aa8b732 1382
5e520e62
AK		 1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1385 return value;
1386}
1387
96304217 1388static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1389{
1390 return vmcs_readl(field);
1391}
1392
96304217 1393static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1394{
1395 return vmcs_readl(field);
1396}
1397
96304217 1398static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1399{
05b3e0c2 1400#ifdef CONFIG_X86_64
6aa8b732
AK		 1401 return vmcs_readl(field);
1402#else
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404#endif
1405}
1406
e52de1b8
AK		 1407static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408{
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411 dump_stack();
1412}
1413
6aa8b732
AK		 1414static void vmcs_writel(unsigned long field, unsigned long value)
1415{
1416 u8 error;
1417
4ecac3fd 1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1420 if (unlikely(error))
1421 vmwrite_error(field, value);
6aa8b732
AK		 1422}
1423
1424static void vmcs_write16(unsigned long field, u16 value)
1425{
1426 vmcs_writel(field, value);
1427}
1428
1429static void vmcs_write32(unsigned long field, u32 value)
1430{
1431 vmcs_writel(field, value);
1432}
1433
1434static void vmcs_write64(unsigned long field, u64 value)
1435{
6aa8b732 1436 vmcs_writel(field, value);
7682f2d0 1437#ifndef CONFIG_X86_64
6aa8b732
AK		 1438 asm volatile ("");
1439 vmcs_writel(field+1, value >> 32);
1440#endif
1441}
1442
2ab455cc
AL		 1443static void vmcs_clear_bits(unsigned long field, u32 mask)
1444{
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1446}
1447
1448static void vmcs_set_bits(unsigned long field, u32 mask)
1449{
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1451}
1452
2961e876
GN		 1453static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454{
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1457}
1458
1459static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460{
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1463}
1464
1465static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466{
1467 return vmx->vm_entry_controls_shadow;
1468}
1469
1470
1471static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472{
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474}
1475
1476static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477{
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479}
1480
1481static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482{
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1485}
1486
1487static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488{
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1491}
1492
1493static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494{
1495 return vmx->vm_exit_controls_shadow;
1496}
1497
1498
1499static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500{
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502}
1503
1504static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505{
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507}
1508
2fb92db1
AK		 1509static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510{
1511 vmx->segment_cache.bitmask = 0;
1512}
1513
1514static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515 unsigned field)
1516{
1517 bool ret;
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1523 }
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1526 return ret;
1527}
1528
1529static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530{
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535 return *p;
1536}
1537
1538static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539{
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544 return *p;
1545}
1546
1547static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548{
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553 return *p;
1554}
1555
1556static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557{
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562 return *p;
1563}
1564
abd3f2d6
AK		 1565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566{
1567 u32 eb;
1568
fd7373cc
JK		 1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
7ffd92c5 1575 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1576 eb = ~0;
089d034e 1577 if (enable_ept)
1439442c 1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1581
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1586 */
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
abd3f2d6
AK		 1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1591}
1592
2961e876
GN		 1593static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
8bf00a52 1595{
2961e876
GN		 1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1598}
1599
61d2ef2c
AK		 1600static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601{
1602 unsigned i;
1603 struct msr_autoload *m = &vmx->msr_autoload;
1604
8bf00a52
GN		 1605 switch (msr) {
1606 case MSR_EFER:
1607 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1610 VM_EXIT_LOAD_IA32_EFER);
1611 return;
1612 }
1613 break;
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
2961e876 1616 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619 return;
1620 }
1621 break;
110312c8
AK		 1622 }
1623
61d2ef2c
AK		 1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1626 break;
1627
1628 if (i == m->nr)
1629 return;
1630 --m->nr;
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635}
1636
2961e876
GN		 1637static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
8bf00a52
GN		 1641{
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1646}
1647
61d2ef2c
AK		 1648static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1650{
1651 unsigned i;
1652 struct msr_autoload *m = &vmx->msr_autoload;
1653
8bf00a52
GN		 1654 switch (msr) {
1655 case MSR_EFER:
1656 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1659 VM_EXIT_LOAD_IA32_EFER,
1660 GUEST_IA32_EFER,
1661 HOST_IA32_EFER,
1662 guest_val, host_val);
1663 return;
1664 }
1665 break;
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
2961e876 1668 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1674 return;
1675 }
1676 break;
110312c8
AK		 1677 }
1678
61d2ef2c
AK		 1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1681 break;
1682
e7fc6f93 1683 if (i == NR_AUTOLOAD_MSRS) {
60266204 1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1685 "Can't add msr %x\n", msr);
1686 return;
1687 } else if (i == m->nr) {
61d2ef2c
AK		 1688 ++m->nr;
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691 }
1692
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1697}
1698
33ed6329
AK		 1699static void reload_tss(void)
1700{
33ed6329
AK		 1701 /*
1702 * VT restores TR but not its size. Useless.
1703 */
89cbc767 1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1705 struct desc_struct *descs;
33ed6329 1706
d359192f 1707 descs = (void *)gdt->address;
33ed6329
AK		 1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709 load_TR_desc();
33ed6329
AK		 1710}
1711
92c0d900 1712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1713{
3a34a881 1714 u64 guest_efer;
51c6cf66
AK		 1715 u64 ignore_bits;
1716
f6801dff 1717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1718
51c6cf66 1719 /*
0fa06071 1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1721 * outside long mode
1722 */
1723 ignore_bits = EFER_NX | EFER_SCE;
1724#ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1729#endif
51c6cf66
AK		 1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
26bb0981 1732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1734
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1736
1737 /*
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1741 */
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
54b98bff
AL		 1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
84ad33ef
AK		 1750 return false;
1751 }
1752
26bb0981 1753 return true;
51c6cf66
AK		 1754}
1755
2d49ec72
GN		 1756static unsigned long segment_base(u16 selector)
1757{
89cbc767 1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1759 struct desc_struct *d;
1760 unsigned long table_base;
1761 unsigned long v;
1762
1763 if (!(selector & ~3))
1764 return 0;
1765
d359192f 1766 table_base = gdt->address;
2d49ec72
GN		 1767
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1770
1771 if (!(ldt_selector & ~3))
1772 return 0;
1773
1774 table_base = segment_base(ldt_selector);
1775 }
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778#ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781#endif
1782 return v;
1783}
1784
1785static inline unsigned long kvm_read_tr_base(void)
1786{
1787 u16 tr;
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1790}
1791
04d2cc77 1792static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1793{
04d2cc77 1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1795 int i;
04d2cc77 1796
a2fa3e9f 1797 if (vmx->host_state.loaded)
33ed6329
AK		 1798 return;
1799
a2fa3e9f 1800 vmx->host_state.loaded = 1;
33ed6329
AK		 1801 /*
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1804 */
d6e88aec 1805 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1807 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1808 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1810 vmx->host_state.fs_reload_needed = 0;
1811 } else {
33ed6329 1812 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1813 vmx->host_state.fs_reload_needed = 1;
33ed6329 1814 }
9581d442 1815 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1818 else {
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1820 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1821 }
1822
b2da15ac
AK		 1823#ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1826#endif
1827
33ed6329
AK		 1828#ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831#else
a2fa3e9f
GH		 1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1834#endif
707c0874
AK		 1835
1836#ifdef CONFIG_X86_64
c8770e7b
AK		 1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
44ea2b17 1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1840#endif
da8999d3
LJ		 1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
33ed6329
AK		 1847}
1848
a9b21b62 1849static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1850{
a2fa3e9f 1851 if (!vmx->host_state.loaded)
33ed6329
AK		 1852 return;
1853
e1beb1d3 1854 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1855 vmx->host_state.loaded = 0;
c8770e7b
AK		 1856#ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859#endif
152d3f2f 1860 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1861 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1862#ifdef CONFIG_X86_64
9581d442 1863 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1864#else
1865 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1866#endif
33ed6329 1867 }
0a77fe4c
AK		 1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1870#ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1874 }
b2da15ac 1875#endif
152d3f2f 1876 reload_tss();
44ea2b17 1877#ifdef CONFIG_X86_64
c8770e7b 1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1879#endif
da8999d3
LJ		 1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1882 /*
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1885 */
1886 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887 stts();
89cbc767 1888 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1889}
1890
a9b21b62
AK		 1891static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892{
1893 preempt_disable();
1894 __vmx_load_host_state(vmx);
1895 preempt_enable();
1896}
1897
6aa8b732
AK		 1898/*
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1901 */
15ad7146 1902static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1903{
a2fa3e9f 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1906
4610c9cc
DX		 1907 if (!vmm_exclusive)
1908 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1911
d462b819
NHE		 1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1915 }
1916
d462b819 1917 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1919 unsigned long sysenter_esp;
1920
a8eeb04a 1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1922 local_irq_disable();
8f536b76 1923 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1924
1925 /*
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1929 */
1930 smp_rmb();
1931
d462b819
NHE		 1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1934 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1935 local_irq_enable();
1936
6aa8b732
AK		 1937 /*
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1939 * processors.
1940 */
d6e88aec 1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1943
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1946 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1947 }
6aa8b732
AK		 1948}
1949
1950static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951{
a9b21b62 1952 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1953 if (!vmm_exclusive) {
d462b819
NHE		 1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955 vcpu->cpu = -1;
4610c9cc
DX		 1956 kvm_cpu_vmxoff();
1957 }
6aa8b732
AK		 1958}
1959
5fd86fcf
AK		 1960static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961{
81231c69
AK		 1962 ulong cr0;
1963
5fd86fcf
AK		 1964 if (vcpu->fpu_active)
1965 return;
1966 vcpu->fpu_active = 1;
81231c69
AK		 1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1971 update_exception_bitmap(vcpu);
edcafe3c 1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1977}
1978
edcafe3c
AK		 1979static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
fe3ef05c
NHE		 1981/*
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1985 */
1986static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987{
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990}
1991static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992{
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995}
1996
5fd86fcf
AK		 1997static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998{
36cf24e0
NHE		 1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2001 */
edcafe3c 2002 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2004 update_exception_bitmap(vcpu);
edcafe3c
AK		 2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2007 if (is_guest_mode(vcpu)) {
2008 /*
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2015 */
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020 } else
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2022}
2023
6aa8b732
AK		 2024static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025{
78ac8b47 2026 unsigned long rflags, save_rflags;
345dcaa8 2027
6de12732
AK		 2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035 }
2036 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2037 }
6de12732 2038 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2039}
2040
2041static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042{
6de12732
AK		 2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2048 }
6aa8b732
AK		 2049 vmcs_writel(GUEST_RFLAGS, rflags);
2050}
2051
37ccdcbe 2052static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2053{
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055 int ret = 0;
2056
2057 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2058 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2061
37ccdcbe 2062 return ret;
2809f5d2
GC		 2063}
2064
2065static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066{
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2069
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
48005f64 2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2075 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079}
2080
6aa8b732
AK		 2081static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082{
2083 unsigned long rip;
6aa8b732 2084
5fdbf976 2085 rip = kvm_rip_read(vcpu);
6aa8b732 2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2087 kvm_rip_write(vcpu, rip);
6aa8b732 2088
2809f5d2
GC		 2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2091}
2092
0b6ac343
NHE		 2093/*
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2096 */
e011c663 2097static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2098{
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
e011c663 2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2102 return 0;
2103
533558bc
JK		 2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2107 return 1;
2108}
2109
298101da 2110static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2111 bool has_error_code, u32 error_code,
2112 bool reinject)
298101da 2113{
77ab6db0 2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2116
e011c663
GN		 2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2119 return;
2120
8ab2d2e2 2121 if (has_error_code) {
77ab6db0 2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124 }
77ab6db0 2125
7ffd92c5 2126 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2127 int inc_eip = 0;
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2132 return;
2133 }
2134
66fd3f7f
GN		 2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139 } else
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2143}
2144
4e47c7a6
SY		 2145static bool vmx_rdtscp_supported(void)
2146{
2147 return cpu_has_vmx_rdtscp();
2148}
2149
ad756a16
MJ		 2150static bool vmx_invpcid_supported(void)
2151{
2152 return cpu_has_vmx_invpcid() && enable_ept;
2153}
2154
a75beee6
ED		 2155/*
2156 * Swap MSR entry in host/guest MSR entry array.
2157 */
8b9cf98c 2158static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2159{
26bb0981 2160 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2161
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2165}
2166
8d14695f
YZ		 2167static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168{
2169 unsigned long *msr_bitmap;
2170
670125bd
WV		 2171 if (is_guest_mode(vcpu))
2172 msr_bitmap = vmx_msr_bitmap_nested;
2173 else if (irqchip_in_kernel(vcpu->kvm) &&
2174 apic_x2apic_mode(vcpu->arch.apic)) {
8d14695f
YZ		 2175 if (is_long_mode(vcpu))
2176 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177 else
2178 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179 } else {
2180 if (is_long_mode(vcpu))
2181 msr_bitmap = vmx_msr_bitmap_longmode;
2182 else
2183 msr_bitmap = vmx_msr_bitmap_legacy;
2184 }
2185
2186 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187}
2188
e38aea3e
AK		 2189/*
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2193 */
8b9cf98c 2194static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2195{
26bb0981 2196 int save_nmsrs, index;
e38aea3e 2197
a75beee6
ED		 2198 save_nmsrs = 0;
2199#ifdef CONFIG_X86_64
8b9cf98c 2200 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2201 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2202 if (index >= 0)
8b9cf98c
RR		 2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2205 if (index >= 0)
8b9cf98c
RR		 2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2208 if (index >= 0)
8b9cf98c 2209 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2210 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211 if (index >= 0 && vmx->rdtscp_enabled)
2212 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2213 /*
8c06585d 2214 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2215 * if efer.sce is enabled.
2216 */
8c06585d 2217 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2218 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2219 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2220 }
2221#endif
92c0d900
AK		 2222 index = __find_msr_index(vmx, MSR_EFER);
2223 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2224 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2225
26bb0981 2226 vmx->save_nmsrs = save_nmsrs;
5897297b 2227
8d14695f
YZ		 2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2230}
2231
6aa8b732
AK		 2232/*
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2235 */
2236static u64 guest_read_tsc(void)
2237{
2238 u64 host_tsc, tsc_offset;
2239
2240 rdtscll(host_tsc);
2241 tsc_offset = vmcs_read64(TSC_OFFSET);
2242 return host_tsc + tsc_offset;
2243}
2244
d5c1785d
NHE		 2245/*
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2248 */
48d89b92 2249static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2250{
886b470c 2251 u64 tsc_offset;
d5c1785d 2252
d5c1785d
NHE		 2253 tsc_offset = is_guest_mode(vcpu) ?
2254 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255 vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2257}
2258
4051b188 2259/*
cc578287
ZA		 2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
4051b188 2262 */
cc578287 2263static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2264{
cc578287
ZA		 2265 if (!scale)
2266 return;
2267
2268 if (user_tsc_khz > tsc_khz) {
2269 vcpu->arch.tsc_catchup = 1;
2270 vcpu->arch.tsc_always_catchup = 1;
2271 } else
2272 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2273}
2274
ba904635
WA		 2275static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276{
2277 return vmcs_read64(TSC_OFFSET);
2278}
2279
6aa8b732 2280/*
99e3e30a 2281 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2282 */
99e3e30a 2283static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2284{
27fc51b2 2285 if (is_guest_mode(vcpu)) {
7991825b 2286 /*
27fc51b2
NHE		 2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
7991825b 2291 */
27fc51b2
NHE		 2292 struct vmcs12 *vmcs12;
2293 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12 = get_vmcs12(vcpu);
2296 vmcs_write64(TSC_OFFSET, offset +
2297 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298 vmcs12->tsc_offset : 0));
2299 } else {
489223ed
YY		 2300 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2302 vmcs_write64(TSC_OFFSET, offset);
2303 }
6aa8b732
AK		 2304}
2305
f1e2b260 2306static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2307{
2308 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2309
e48672fa 2310 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2311 if (is_guest_mode(vcpu)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2314 } else
2315 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316 offset + adjustment);
e48672fa
ZA		 2317}
2318
857e4099
JR		 2319static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320{
2321 return target_tsc - native_read_tsc();
2322}
2323
801d3424
NHE		 2324static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325{
2326 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328}
2329
2330/*
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2335 */
2336static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337{
2338 return nested && guest_cpuid_has_vmx(vcpu);
2339}
2340
b87a51ae
NHE		 2341/*
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
b87a51ae 2350 */
b9c237bb 2351static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2352{
2353 /*
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2366 */
2367
2368 /* pin-based controls */
eabeaacc 2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2370 vmx->nested.nested_vmx_pinbased_ctls_low,
2371 vmx->nested.nested_vmx_pinbased_ctls_high);
2372 vmx->nested.nested_vmx_pinbased_ctls_low |=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374 vmx->nested.nested_vmx_pinbased_ctls_high &=
2375 PIN_BASED_EXT_INTR_MASK |
2376 PIN_BASED_NMI_EXITING |
2377 PIN_BASED_VIRTUAL_NMIS;
2378 vmx->nested.nested_vmx_pinbased_ctls_high |=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2380 PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1
WV		 2381 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383 PIN_BASED_POSTED_INTR;
b87a51ae 2384
3dbcd8da 2385 /* exit controls */
c0dfee58 2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2387 vmx->nested.nested_vmx_exit_ctls_low,
2388 vmx->nested.nested_vmx_exit_ctls_high);
2389 vmx->nested.nested_vmx_exit_ctls_low =
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2391
b9c237bb 2392 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2393#ifdef CONFIG_X86_64
c0dfee58 2394 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2395#endif
f4124500 2396 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2397 vmx->nested.nested_vmx_exit_ctls_high |=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2399 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
36be0b9d 2402 if (vmx_mpx_supported())
b9c237bb 2403 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2404
2996fca0 2405 /* We support free control of debug control saving. */
b9c237bb
WV		 2406 vmx->nested.nested_vmx_true_exit_ctls_low =
2407 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
b87a51ae
NHE		 2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2412 vmx->nested.nested_vmx_entry_ctls_low,
2413 vmx->nested.nested_vmx_entry_ctls_high);
2414 vmx->nested.nested_vmx_entry_ctls_low =
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2417#ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE |
2419#endif
2420 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2421 vmx->nested.nested_vmx_entry_ctls_high |=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2423 if (vmx_mpx_supported())
b9c237bb 2424 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2425
2996fca0 2426 /* We support free control of debug control loading. */
b9c237bb
WV		 2427 vmx->nested.nested_vmx_true_entry_ctls_low =
2428 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
b87a51ae
NHE		 2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2433 vmx->nested.nested_vmx_procbased_ctls_low,
2434 vmx->nested.nested_vmx_procbased_ctls_high);
2435 vmx->nested.nested_vmx_procbased_ctls_low =
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2438 CPU_BASED_VIRTUAL_INTR_PENDING |
2439 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2440 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442 CPU_BASED_CR3_STORE_EXITING |
2443#ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445#endif
2446 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2448 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2449 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2450 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451 /*
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2456 */
b9c237bb
WV		 2457 vmx->nested.nested_vmx_procbased_ctls_high |=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2459 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2460
3dcdf3ec 2461 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2462 vmx->nested.nested_vmx_true_procbased_ctls_low =
2463 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2464 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
b87a51ae
NHE		 2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2468 vmx->nested.nested_vmx_secondary_ctls_low,
2469 vmx->nested.nested_vmx_secondary_ctls_high);
2470 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2473 SECONDARY_EXEC_RDTSCP |
f2b93280 2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2475 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2477 SECONDARY_EXEC_WBINVD_EXITING |
2478 SECONDARY_EXEC_XSAVES;
c18911a2 2479
afa61f75
NHE		 2480 if (enable_ept) {
2481 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2482 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2483 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2484 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2485 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486 VMX_EPT_INVEPT_BIT;
b9c237bb 2487 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2488 /*
4b855078
BD		 2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
afa61f75 2492 */
b9c237bb 2493 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2494 } else
b9c237bb 2495 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2496
0790ec17
RK		 2497 if (enable_unrestricted_guest)
2498 vmx->nested.nested_vmx_secondary_ctls_high |=
2499 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500
c18911a2 2501 /* miscellaneous data */
b9c237bb
WV		 2502 rdmsr(MSR_IA32_VMX_MISC,
2503 vmx->nested.nested_vmx_misc_low,
2504 vmx->nested.nested_vmx_misc_high);
2505 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506 vmx->nested.nested_vmx_misc_low |=
2507 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2508 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2509 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2510}
2511
2512static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2513{
2514 /*
2515 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516 */
2517 return ((control & high) | low) == control;
2518}
2519
2520static inline u64 vmx_control_msr(u32 low, u32 high)
2521{
2522 return low | ((u64)high << 32);
2523}
2524
cae50139 2525/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2526static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527{
b9c237bb
WV		 2528 struct vcpu_vmx *vmx = to_vmx(vcpu);
2529
b87a51ae 2530 switch (msr_index) {
b87a51ae
NHE		 2531 case MSR_IA32_VMX_BASIC:
2532 /*
2533 * This MSR reports some information about VMX support. We
2534 * should return information about the VMX we emulate for the
2535 * guest, and the VMCS structure we give it - not about the
2536 * VMX support of the underlying hardware.
2537 */
3dbcd8da 2538 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2539 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541 break;
2542 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2544 *pdata = vmx_control_msr(
2545 vmx->nested.nested_vmx_pinbased_ctls_low,
2546 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2547 break;
2548 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2549 *pdata = vmx_control_msr(
2550 vmx->nested.nested_vmx_true_procbased_ctls_low,
2551 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2552 break;
b87a51ae 2553 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2554 *pdata = vmx_control_msr(
2555 vmx->nested.nested_vmx_procbased_ctls_low,
2556 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2557 break;
2558 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2559 *pdata = vmx_control_msr(
2560 vmx->nested.nested_vmx_true_exit_ctls_low,
2561 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2562 break;
b87a51ae 2563 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2564 *pdata = vmx_control_msr(
2565 vmx->nested.nested_vmx_exit_ctls_low,
2566 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2567 break;
2568 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2569 *pdata = vmx_control_msr(
2570 vmx->nested.nested_vmx_true_entry_ctls_low,
2571 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2572 break;
b87a51ae 2573 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2574 *pdata = vmx_control_msr(
2575 vmx->nested.nested_vmx_entry_ctls_low,
2576 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2577 break;
2578 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2579 *pdata = vmx_control_msr(
2580 vmx->nested.nested_vmx_misc_low,
2581 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2582 break;
2583 /*
2584 * These MSRs specify bits which the guest must keep fixed (on or off)
2585 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586 * We picked the standard core2 setting.
2587 */
2588#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2590 case MSR_IA32_VMX_CR0_FIXED0:
2591 *pdata = VMXON_CR0_ALWAYSON;
2592 break;
2593 case MSR_IA32_VMX_CR0_FIXED1:
2594 *pdata = -1ULL;
2595 break;
2596 case MSR_IA32_VMX_CR4_FIXED0:
2597 *pdata = VMXON_CR4_ALWAYSON;
2598 break;
2599 case MSR_IA32_VMX_CR4_FIXED1:
2600 *pdata = -1ULL;
2601 break;
2602 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2603 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2604 break;
2605 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2606 *pdata = vmx_control_msr(
2607 vmx->nested.nested_vmx_secondary_ctls_low,
2608 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2609 break;
2610 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2611 /* Currently, no nested vpid support */
b9c237bb 2612 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2613 break;
2614 default:
b87a51ae 2615 return 1;
b3897a49
NHE		 2616 }
2617
b87a51ae
NHE		 2618 return 0;
2619}
2620
6aa8b732
AK		 2621/*
2622 * Reads an msr value (of 'msr_index') into 'pdata'.
2623 * Returns 0 on success, non-0 otherwise.
2624 * Assumes vcpu_load() was already called.
2625 */
2626static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2627{
2628 u64 data;
26bb0981 2629 struct shared_msr_entry *msr;
6aa8b732
AK		 2630
2631 if (!pdata) {
2632 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2633 return -EINVAL;
2634 }
2635
2636 switch (msr_index) {
05b3e0c2 2637#ifdef CONFIG_X86_64
6aa8b732
AK		 2638 case MSR_FS_BASE:
2639 data = vmcs_readl(GUEST_FS_BASE);
2640 break;
2641 case MSR_GS_BASE:
2642 data = vmcs_readl(GUEST_GS_BASE);
2643 break;
44ea2b17
AK		 2644 case MSR_KERNEL_GS_BASE:
2645 vmx_load_host_state(to_vmx(vcpu));
2646 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2647 break;
26bb0981 2648#endif
6aa8b732 2649 case MSR_EFER:
3bab1f5d 2650 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2651 case MSR_IA32_TSC:
6aa8b732
AK		 2652 data = guest_read_tsc();
2653 break;
2654 case MSR_IA32_SYSENTER_CS:
2655 data = vmcs_read32(GUEST_SYSENTER_CS);
2656 break;
2657 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2658 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2659 break;
2660 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2661 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2662 break;
0dd376e7 2663 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2664 if (!vmx_mpx_supported())
2665 return 1;
0dd376e7
LJ		 2666 data = vmcs_read64(GUEST_BNDCFGS);
2667 break;
cae50139
JK		 2668 case MSR_IA32_FEATURE_CONTROL:
2669 if (!nested_vmx_allowed(vcpu))
2670 return 1;
2671 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2672 break;
2673 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2674 if (!nested_vmx_allowed(vcpu))
2675 return 1;
2676 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2677 case MSR_IA32_XSS:
2678 if (!vmx_xsaves_supported())
2679 return 1;
2680 data = vcpu->arch.ia32_xss;
2681 break;
4e47c7a6
SY		 2682 case MSR_TSC_AUX:
2683 if (!to_vmx(vcpu)->rdtscp_enabled)
2684 return 1;
2685 /* Otherwise falls through */
6aa8b732 2686 default:
8b9cf98c 2687 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2688 if (msr) {
2689 data = msr->data;
2690 break;
6aa8b732 2691 }
3bab1f5d 2692 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2693 }
2694
2695 *pdata = data;
2696 return 0;
2697}
2698
cae50139
JK		 2699static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2700
6aa8b732
AK		 2701/*
2702 * Writes msr value into into the appropriate "register".
2703 * Returns 0 on success, non-0 otherwise.
2704 * Assumes vcpu_load() was already called.
2705 */
8fe8ab46 2706static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2707{
a2fa3e9f 2708 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2709 struct shared_msr_entry *msr;
2cc51560 2710 int ret = 0;
8fe8ab46
WA		 2711 u32 msr_index = msr_info->index;
2712 u64 data = msr_info->data;
2cc51560 2713
6aa8b732 2714 switch (msr_index) {
3bab1f5d 2715 case MSR_EFER:
8fe8ab46 2716 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2717 break;
16175a79 2718#ifdef CONFIG_X86_64
6aa8b732 2719 case MSR_FS_BASE:
2fb92db1 2720 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2721 vmcs_writel(GUEST_FS_BASE, data);
2722 break;
2723 case MSR_GS_BASE:
2fb92db1 2724 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2725 vmcs_writel(GUEST_GS_BASE, data);
2726 break;
44ea2b17
AK		 2727 case MSR_KERNEL_GS_BASE:
2728 vmx_load_host_state(vmx);
2729 vmx->msr_guest_kernel_gs_base = data;
2730 break;
6aa8b732
AK		 2731#endif
2732 case MSR_IA32_SYSENTER_CS:
2733 vmcs_write32(GUEST_SYSENTER_CS, data);
2734 break;
2735 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2736 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2737 break;
2738 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2739 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2740 break;
0dd376e7 2741 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2742 if (!vmx_mpx_supported())
2743 return 1;
0dd376e7
LJ		 2744 vmcs_write64(GUEST_BNDCFGS, data);
2745 break;
af24a4e4 2746 case MSR_IA32_TSC:
8fe8ab46 2747 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2748 break;
468d472f
SY		 2749 case MSR_IA32_CR_PAT:
2750 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2751 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2752 return 1;
468d472f
SY		 2753 vmcs_write64(GUEST_IA32_PAT, data);
2754 vcpu->arch.pat = data;
2755 break;
2756 }
8fe8ab46 2757 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2758 break;
ba904635
WA		 2759 case MSR_IA32_TSC_ADJUST:
2760 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2761 break;
cae50139
JK		 2762 case MSR_IA32_FEATURE_CONTROL:
2763 if (!nested_vmx_allowed(vcpu) ||
2764 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2765 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2766 return 1;
2767 vmx->nested.msr_ia32_feature_control = data;
2768 if (msr_info->host_initiated && data == 0)
2769 vmx_leave_nested(vcpu);
2770 break;
2771 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2772 return 1; /* they are read-only */
20300099
WL		 2773 case MSR_IA32_XSS:
2774 if (!vmx_xsaves_supported())
2775 return 1;
2776 /*
2777 * The only supported bit as of Skylake is bit 8, but
2778 * it is not supported on KVM.
2779 */
2780 if (data != 0)
2781 return 1;
2782 vcpu->arch.ia32_xss = data;
2783 if (vcpu->arch.ia32_xss != host_xss)
2784 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2785 vcpu->arch.ia32_xss, host_xss);
2786 else
2787 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2788 break;
4e47c7a6
SY		 2789 case MSR_TSC_AUX:
2790 if (!vmx->rdtscp_enabled)
2791 return 1;
2792 /* Check reserved bit, higher 32 bits should be zero */
2793 if ((data >> 32) != 0)
2794 return 1;
2795 /* Otherwise falls through */
6aa8b732 2796 default:
8b9cf98c 2797 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2798 if (msr) {
8b3c3104 2799 u64 old_msr_data = msr->data;
3bab1f5d 2800 msr->data = data;
2225fd56
AK		 2801 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2802 preempt_disable();
8b3c3104
AH		 2803 ret = kvm_set_shared_msr(msr->index, msr->data,
2804 msr->mask);
2225fd56 2805 preempt_enable();
8b3c3104
AH		 2806 if (ret)
2807 msr->data = old_msr_data;
2225fd56 2808 }
3bab1f5d 2809 break;
6aa8b732 2810 }
8fe8ab46 2811 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2812 }
2813
2cc51560 2814 return ret;
6aa8b732
AK		 2815}
2816
5fdbf976 2817static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2818{
5fdbf976
MT		 2819 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2820 switch (reg) {
2821 case VCPU_REGS_RSP:
2822 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2823 break;
2824 case VCPU_REGS_RIP:
2825 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2826 break;
6de4f3ad
AK		 2827 case VCPU_EXREG_PDPTR:
2828 if (enable_ept)
2829 ept_save_pdptrs(vcpu);
2830 break;
5fdbf976
MT		 2831 default:
2832 break;
2833 }
6aa8b732
AK		 2834}
2835
6aa8b732
AK		 2836static __init int cpu_has_kvm_support(void)
2837{
6210e37b 2838 return cpu_has_vmx();
6aa8b732
AK		 2839}
2840
2841static __init int vmx_disabled_by_bios(void)
2842{
2843 u64 msr;
2844
2845 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2846 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2847 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2848 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2849 && tboot_enabled())
2850 return 1;
23f3e991 2851 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2852 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2853 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2854 && !tboot_enabled()) {
2855 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2856 "activate TXT before enabling KVM\n");
cafd6659 2857 return 1;
f9335afe 2858 }
23f3e991
JC		 2859 /* launched w/o TXT and VMX disabled */
2860 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2861 && !tboot_enabled())
2862 return 1;
cafd6659
SW		 2863 }
2864
2865 return 0;
6aa8b732
AK		 2866}
2867
7725b894
DX		 2868static void kvm_cpu_vmxon(u64 addr)
2869{
2870 asm volatile (ASM_VMX_VMXON_RAX
2871 : : "a"(&addr), "m"(addr)
2872 : "memory", "cc");
2873}
2874
13a34e06 2875static int hardware_enable(void)
6aa8b732
AK		 2876{
2877 int cpu = raw_smp_processor_id();
2878 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2879 u64 old, test_bits;
6aa8b732 2880
1e02ce4c 2881 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2882 return -EBUSY;
2883
d462b819 2884 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2885
2886 /*
2887 * Now we can enable the vmclear operation in kdump
2888 * since the loaded_vmcss_on_cpu list on this cpu
2889 * has been initialized.
2890 *
2891 * Though the cpu is not in VMX operation now, there
2892 * is no problem to enable the vmclear operation
2893 * for the loaded_vmcss_on_cpu list is empty!
2894 */
2895 crash_enable_local_vmclear(cpu);
2896
6aa8b732 2897 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2898
2899 test_bits = FEATURE_CONTROL_LOCKED;
2900 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2901 if (tboot_enabled())
2902 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2903
2904 if ((old & test_bits) != test_bits) {
6aa8b732 2905 /* enable and lock */
cafd6659
SW		 2906 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2907 }
375074cc 2908 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2909
4610c9cc
DX		 2910 if (vmm_exclusive) {
2911 kvm_cpu_vmxon(phys_addr);
2912 ept_sync_global();
2913 }
10474ae8 2914
89cbc767 2915 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2916
10474ae8 2917 return 0;
6aa8b732
AK		 2918}
2919
d462b819 2920static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2921{
2922 int cpu = raw_smp_processor_id();
d462b819 2923 struct loaded_vmcs *v, *n;
543e4243 2924
d462b819
NHE		 2925 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2926 loaded_vmcss_on_cpu_link)
2927 __loaded_vmcs_clear(v);
543e4243
AK		 2928}
2929
710ff4a8
EH		 2930
2931/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2932 * tricks.
2933 */
2934static void kvm_cpu_vmxoff(void)
6aa8b732 2935{
4ecac3fd 2936 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2937}
2938
13a34e06 2939static void hardware_disable(void)
710ff4a8 2940{
4610c9cc 2941 if (vmm_exclusive) {
d462b819 2942 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2943 kvm_cpu_vmxoff();
2944 }
375074cc 2945 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2946}
2947
1c3d14fe 2948static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2949 u32 msr, u32 *result)
1c3d14fe
YS		 2950{
2951 u32 vmx_msr_low, vmx_msr_high;
2952 u32 ctl = ctl_min | ctl_opt;
2953
2954 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2955
2956 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2957 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2958
2959 /* Ensure minimum (required) set of control bits are supported. */
2960 if (ctl_min & ~ctl)
002c7f7c 2961 return -EIO;
1c3d14fe
YS		 2962
2963 *result = ctl;
2964 return 0;
2965}
2966
110312c8
AK		 2967static __init bool allow_1_setting(u32 msr, u32 ctl)
2968{
2969 u32 vmx_msr_low, vmx_msr_high;
2970
2971 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2972 return vmx_msr_high & ctl;
2973}
2974
002c7f7c 2975static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2976{
2977 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2978 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2979 u32 _pin_based_exec_control = 0;
2980 u32 _cpu_based_exec_control = 0;
f78e0e2e 2981 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2982 u32 _vmexit_control = 0;
2983 u32 _vmentry_control = 0;
2984
10166744 2985 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2986#ifdef CONFIG_X86_64
2987 CPU_BASED_CR8_LOAD_EXITING |
2988 CPU_BASED_CR8_STORE_EXITING |
2989#endif
d56f546d
SY		 2990 CPU_BASED_CR3_LOAD_EXITING |
2991 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2992 CPU_BASED_USE_IO_BITMAPS |
2993 CPU_BASED_MOV_DR_EXITING |
a7052897 2994 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2995 CPU_BASED_MWAIT_EXITING |
2996 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2997 CPU_BASED_INVLPG_EXITING |
2998 CPU_BASED_RDPMC_EXITING;
443381a8 2999
f78e0e2e 3000 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3001 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3002 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3003 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3004 &_cpu_based_exec_control) < 0)
002c7f7c 3005 return -EIO;
6e5d865c
YS		 3006#ifdef CONFIG_X86_64
3007 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3008 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3009 ~CPU_BASED_CR8_STORE_EXITING;
3010#endif
f78e0e2e 3011 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3012 min2 = 0;
3013 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3014 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3015 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3016 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3017 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3018 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3019 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3020 SECONDARY_EXEC_RDTSCP |
83d4c286 3021 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3022 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3023 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3024 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3025 SECONDARY_EXEC_XSAVES |
3026 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3027 if (adjust_vmx_controls(min2, opt2,
3028 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3029 &_cpu_based_2nd_exec_control) < 0)
3030 return -EIO;
3031 }
3032#ifndef CONFIG_X86_64
3033 if (!(_cpu_based_2nd_exec_control &
3034 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3035 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3036#endif
83d4c286
YZ		 3037
3038 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3039 _cpu_based_2nd_exec_control &= ~(
8d14695f 3040 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3041 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3042 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3043
d56f546d 3044 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3045 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3046 enabled */
5fff7d27
GN		 3047 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3048 CPU_BASED_CR3_STORE_EXITING |
3049 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3050 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3051 vmx_capability.ept, vmx_capability.vpid);
3052 }
1c3d14fe 3053
81908bf4 3054 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3055#ifdef CONFIG_X86_64
3056 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3057#endif
a547c6db 3058 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3059 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3060 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3061 &_vmexit_control) < 0)
002c7f7c 3062 return -EIO;
1c3d14fe 3063
01e439be
YZ		 3064 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3065 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3066 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3067 &_pin_based_exec_control) < 0)
3068 return -EIO;
3069
3070 if (!(_cpu_based_2nd_exec_control &
3071 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3072 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3073 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3074
c845f9c6 3075 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3076 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3077 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3078 &_vmentry_control) < 0)
002c7f7c 3079 return -EIO;
6aa8b732 3080
c68876fd 3081 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3082
3083 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3085 return -EIO;
1c3d14fe
YS		 3086
3087#ifdef CONFIG_X86_64
3088 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089 if (vmx_msr_high & (1u<<16))
002c7f7c 3090 return -EIO;
1c3d14fe
YS		 3091#endif
3092
3093 /* Require Write-Back (WB) memory type for VMCS accesses. */
3094 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3095 return -EIO;
1c3d14fe 3096
002c7f7c
YS		 3097 vmcs_conf->size = vmx_msr_high & 0x1fff;
3098 vmcs_conf->order = get_order(vmcs_config.size);
3099 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3100
002c7f7c
YS		 3101 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3102 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3103 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3104 vmcs_conf->vmexit_ctrl = _vmexit_control;
3105 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3106
110312c8
AK		 3107 cpu_has_load_ia32_efer =
3108 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109 VM_ENTRY_LOAD_IA32_EFER)
3110 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111 VM_EXIT_LOAD_IA32_EFER);
3112
8bf00a52
GN		 3113 cpu_has_load_perf_global_ctrl =
3114 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3115 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3116 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3117 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3118
3119 /*
3120 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121 * but due to arrata below it can't be used. Workaround is to use
3122 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3123 *
3124 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3125 *
3126 * AAK155 (model 26)
3127 * AAP115 (model 30)
3128 * AAT100 (model 37)
3129 * BC86,AAY89,BD102 (model 44)
3130 * BA97 (model 46)
3131 *
3132 */
3133 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3134 switch (boot_cpu_data.x86_model) {
3135 case 26:
3136 case 30:
3137 case 37:
3138 case 44:
3139 case 46:
3140 cpu_has_load_perf_global_ctrl = false;
3141 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142 "does not work properly. Using workaround\n");
3143 break;
3144 default:
3145 break;
3146 }
3147 }
3148
20300099
WL		 3149 if (cpu_has_xsaves)
3150 rdmsrl(MSR_IA32_XSS, host_xss);
3151
1c3d14fe 3152 return 0;
c68876fd 3153}
6aa8b732
AK		 3154
3155static struct vmcs *alloc_vmcs_cpu(int cpu)
3156{
3157 int node = cpu_to_node(cpu);
3158 struct page *pages;
3159 struct vmcs *vmcs;
3160
6484eb3e 3161 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3162 if (!pages)
3163 return NULL;
3164 vmcs = page_address(pages);
1c3d14fe
YS		 3165 memset(vmcs, 0, vmcs_config.size);
3166 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3167 return vmcs;
3168}
3169
3170static struct vmcs *alloc_vmcs(void)
3171{
d3b2c338 3172 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3173}
3174
3175static void free_vmcs(struct vmcs *vmcs)
3176{
1c3d14fe 3177 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3178}
3179
d462b819
NHE		 3180/*
3181 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3182 */
3183static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3184{
3185 if (!loaded_vmcs->vmcs)
3186 return;
3187 loaded_vmcs_clear(loaded_vmcs);
3188 free_vmcs(loaded_vmcs->vmcs);
3189 loaded_vmcs->vmcs = NULL;
3190}
3191
39959588 3192static void free_kvm_area(void)
6aa8b732
AK		 3193{
3194 int cpu;
3195
3230bb47 3196 for_each_possible_cpu(cpu) {
6aa8b732 3197 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3198 per_cpu(vmxarea, cpu) = NULL;
3199 }
6aa8b732
AK		 3200}
3201
fe2b201b
BD		 3202static void init_vmcs_shadow_fields(void)
3203{
3204 int i, j;
3205
3206 /* No checks for read only fields yet */
3207
3208 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3209 switch (shadow_read_write_fields[i]) {
3210 case GUEST_BNDCFGS:
3211 if (!vmx_mpx_supported())
3212 continue;
3213 break;
3214 default:
3215 break;
3216 }
3217
3218 if (j < i)
3219 shadow_read_write_fields[j] =
3220 shadow_read_write_fields[i];
3221 j++;
3222 }
3223 max_shadow_read_write_fields = j;
3224
3225 /* shadowed fields guest access without vmexit */
3226 for (i = 0; i < max_shadow_read_write_fields; i++) {
3227 clear_bit(shadow_read_write_fields[i],
3228 vmx_vmwrite_bitmap);
3229 clear_bit(shadow_read_write_fields[i],
3230 vmx_vmread_bitmap);
3231 }
3232 for (i = 0; i < max_shadow_read_only_fields; i++)
3233 clear_bit(shadow_read_only_fields[i],
3234 vmx_vmread_bitmap);
3235}
3236
6aa8b732
AK		 3237static __init int alloc_kvm_area(void)
3238{
3239 int cpu;
3240
3230bb47 3241 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3242 struct vmcs *vmcs;
3243
3244 vmcs = alloc_vmcs_cpu(cpu);
3245 if (!vmcs) {
3246 free_kvm_area();
3247 return -ENOMEM;
3248 }
3249
3250 per_cpu(vmxarea, cpu) = vmcs;
3251 }
3252 return 0;
3253}
3254
14168786
GN		 3255static bool emulation_required(struct kvm_vcpu *vcpu)
3256{
3257 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3258}
3259
91b0aa2c 3260static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3261 struct kvm_segment *save)
6aa8b732 3262{
d99e4152
GN		 3263 if (!emulate_invalid_guest_state) {
3264 /*
3265 * CS and SS RPL should be equal during guest entry according
3266 * to VMX spec, but in reality it is not always so. Since vcpu
3267 * is in the middle of the transition from real mode to
3268 * protected mode it is safe to assume that RPL 0 is a good
3269 * default value.
3270 */
3271 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3272 save->selector &= ~SEGMENT_RPL_MASK;
3273 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3274 save->s = 1;
6aa8b732 3275 }
d99e4152 3276 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3277}
3278
3279static void enter_pmode(struct kvm_vcpu *vcpu)
3280{
3281 unsigned long flags;
a89a8fb9 3282 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3283
d99e4152
GN		 3284 /*
3285 * Update real mode segment cache. It may be not up-to-date if sement
3286 * register was written while vcpu was in a guest mode.
3287 */
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3289 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3290 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3291 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3292 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3293 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3294
7ffd92c5 3295 vmx->rmode.vm86_active = 0;
6aa8b732 3296
2fb92db1
AK		 3297 vmx_segment_cache_clear(vmx);
3298
f5f7b2fe 3299 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3300
3301 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3302 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3303 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3304 vmcs_writel(GUEST_RFLAGS, flags);
3305
66aee91a
RR		 3306 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3307 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3308
3309 update_exception_bitmap(vcpu);
3310
91b0aa2c
GN		 3311 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3312 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3313 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3314 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3315 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3316 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3317}
3318
f5f7b2fe 3319static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3320{
772e0318 3321 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3322 struct kvm_segment var = *save;
3323
3324 var.dpl = 0x3;
3325 if (seg == VCPU_SREG_CS)
3326 var.type = 0x3;
3327
3328 if (!emulate_invalid_guest_state) {
3329 var.selector = var.base >> 4;
3330 var.base = var.base & 0xffff0;
3331 var.limit = 0xffff;
3332 var.g = 0;
3333 var.db = 0;
3334 var.present = 1;
3335 var.s = 1;
3336 var.l = 0;
3337 var.unusable = 0;
3338 var.type = 0x3;
3339 var.avl = 0;
3340 if (save->base & 0xf)
3341 printk_once(KERN_WARNING "kvm: segment base is not "
3342 "paragraph aligned when entering "
3343 "protected mode (seg=%d)", seg);
3344 }
6aa8b732 3345
d99e4152
GN		 3346 vmcs_write16(sf->selector, var.selector);
3347 vmcs_write32(sf->base, var.base);
3348 vmcs_write32(sf->limit, var.limit);
3349 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3350}
3351
3352static void enter_rmode(struct kvm_vcpu *vcpu)
3353{
3354 unsigned long flags;
a89a8fb9 3355 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3356
f5f7b2fe
AK		 3357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3359 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3360 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3361 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3362 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3363 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3364
7ffd92c5 3365 vmx->rmode.vm86_active = 1;
6aa8b732 3366
776e58ea
GN		 3367 /*
3368 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3369 * vcpu. Warn the user that an update is overdue.
776e58ea 3370 */
4918c6ca 3371 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3372 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3373 "called before entering vcpu\n");
776e58ea 3374
2fb92db1
AK		 3375 vmx_segment_cache_clear(vmx);
3376
4918c6ca 3377 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3378 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3379 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3380
3381 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3382 vmx->rmode.save_rflags = flags;
6aa8b732 3383
053de044 3384 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3385
3386 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3387 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3388 update_exception_bitmap(vcpu);
3389
d99e4152
GN		 3390 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3391 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3392 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3393 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3394 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3395 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3396
8668a3c4 3397 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3398}
3399
401d10de
AS		 3400static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3401{
3402 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3403 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3404
3405 if (!msr)
3406 return;
401d10de 3407
44ea2b17
AK		 3408 /*
3409 * Force kernel_gs_base reloading before EFER changes, as control
3410 * of this msr depends on is_long_mode().
3411 */
3412 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3413 vcpu->arch.efer = efer;
401d10de 3414 if (efer & EFER_LMA) {
2961e876 3415 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3416 msr->data = efer;
3417 } else {
2961e876 3418 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3419
3420 msr->data = efer & ~EFER_LME;
3421 }
3422 setup_msrs(vmx);
3423}
3424
05b3e0c2 3425#ifdef CONFIG_X86_64
6aa8b732
AK		 3426
3427static void enter_lmode(struct kvm_vcpu *vcpu)
3428{
3429 u32 guest_tr_ar;
3430
2fb92db1
AK		 3431 vmx_segment_cache_clear(to_vmx(vcpu));
3432
6aa8b732
AK		 3433 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3434 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3435 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3436 __func__);
6aa8b732
AK		 3437 vmcs_write32(GUEST_TR_AR_BYTES,
3438 (guest_tr_ar & ~AR_TYPE_MASK)
3439 | AR_TYPE_BUSY_64_TSS);
3440 }
da38f438 3441 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3442}
3443
3444static void exit_lmode(struct kvm_vcpu *vcpu)
3445{
2961e876 3446 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3447 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3448}
3449
3450#endif
3451
2384d2b3
SY		 3452static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3453{
b9d762fa 3454 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3455 if (enable_ept) {
3456 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3457 return;
4e1096d2 3458 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3459 }
2384d2b3
SY		 3460}
3461
e8467fda
AK		 3462static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3463{
3464 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3465
3466 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3467 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3468}
3469
aff48baa
AK		 3470static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3471{
3472 if (enable_ept && is_paging(vcpu))
3473 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3474 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3475}
3476
25c4c276 3477static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3478{
fc78f519
AK		 3479 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3480
3481 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3482 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3483}
3484
1439442c
SY		 3485static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3486{
d0d538b9
GN		 3487 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3488
6de4f3ad
AK		 3489 if (!test_bit(VCPU_EXREG_PDPTR,
3490 (unsigned long *)&vcpu->arch.regs_dirty))
3491 return;
3492
1439442c 3493 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3494 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3495 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3496 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3497 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3498 }
3499}
3500
8f5d549f
AK		 3501static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3502{
d0d538b9
GN		 3503 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3504
8f5d549f 3505 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3506 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3507 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3508 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3509 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3510 }
6de4f3ad
AK		 3511
3512 __set_bit(VCPU_EXREG_PDPTR,
3513 (unsigned long *)&vcpu->arch.regs_avail);
3514 __set_bit(VCPU_EXREG_PDPTR,
3515 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3516}
3517
5e1746d6 3518static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3519
3520static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3521 unsigned long cr0,
3522 struct kvm_vcpu *vcpu)
3523{
5233dd51
MT		 3524 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3525 vmx_decache_cr3(vcpu);
1439442c
SY		 3526 if (!(cr0 & X86_CR0_PG)) {
3527 /* From paging/starting to nonpaging */
3528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3529 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3530 (CPU_BASED_CR3_LOAD_EXITING |
3531 CPU_BASED_CR3_STORE_EXITING));
3532 vcpu->arch.cr0 = cr0;
fc78f519 3533 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3534 } else if (!is_paging(vcpu)) {
3535 /* From nonpaging to paging */
3536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3537 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3538 ~(CPU_BASED_CR3_LOAD_EXITING |
3539 CPU_BASED_CR3_STORE_EXITING));
3540 vcpu->arch.cr0 = cr0;
fc78f519 3541 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3542 }
95eb84a7
SY		 3543
3544 if (!(cr0 & X86_CR0_WP))
3545 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3546}
3547
6aa8b732
AK		 3548static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3549{
7ffd92c5 3550 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3551 unsigned long hw_cr0;
3552
5037878e 3553 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3554 if (enable_unrestricted_guest)
5037878e 3555 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3556 else {
5037878e 3557 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3558
218e763f
GN		 3559 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3560 enter_pmode(vcpu);
6aa8b732 3561
218e763f
GN		 3562 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3563 enter_rmode(vcpu);
3564 }
6aa8b732 3565
05b3e0c2 3566#ifdef CONFIG_X86_64
f6801dff 3567 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3568 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3569 enter_lmode(vcpu);
707d92fa 3570 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3571 exit_lmode(vcpu);
3572 }
3573#endif
3574
089d034e 3575 if (enable_ept)
1439442c
SY		 3576 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3577
02daab21 3578 if (!vcpu->fpu_active)
81231c69 3579 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3580
6aa8b732 3581 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3582 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3583 vcpu->arch.cr0 = cr0;
14168786
GN		 3584
3585 /* depends on vcpu->arch.cr0 to be set to a new value */
3586 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3587}
3588
1439442c
SY		 3589static u64 construct_eptp(unsigned long root_hpa)
3590{
3591 u64 eptp;
3592
3593 /* TODO write the value reading from MSR */
3594 eptp = VMX_EPT_DEFAULT_MT |
3595 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3596 if (enable_ept_ad_bits)
3597 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3598 eptp |= (root_hpa & PAGE_MASK);
3599
3600 return eptp;
3601}
3602
6aa8b732
AK		 3603static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3604{
1439442c
SY		 3605 unsigned long guest_cr3;
3606 u64 eptp;
3607
3608 guest_cr3 = cr3;
089d034e 3609 if (enable_ept) {
1439442c
SY		 3610 eptp = construct_eptp(cr3);
3611 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3612 if (is_paging(vcpu) || is_guest_mode(vcpu))
3613 guest_cr3 = kvm_read_cr3(vcpu);
3614 else
3615 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3616 ept_load_pdptrs(vcpu);
1439442c
SY		 3617 }
3618
2384d2b3 3619 vmx_flush_tlb(vcpu);
1439442c 3620 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3621}
3622
5e1746d6 3623static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3624{
085e68ee
BS		 3625 /*
3626 * Pass through host's Machine Check Enable value to hw_cr4, which
3627 * is in force while we are in guest mode. Do not let guests control
3628 * this bit, even if host CR4.MCE == 0.
3629 */
3630 unsigned long hw_cr4 =
3631 (cr4_read_shadow() & X86_CR4_MCE) |
3632 (cr4 & ~X86_CR4_MCE) |
3633 (to_vmx(vcpu)->rmode.vm86_active ?
3634 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3635
5e1746d6
NHE		 3636 if (cr4 & X86_CR4_VMXE) {
3637 /*
3638 * To use VMXON (and later other VMX instructions), a guest
3639 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3640 * So basically the check on whether to allow nested VMX
3641 * is here.
3642 */
3643 if (!nested_vmx_allowed(vcpu))
3644 return 1;
1a0d74e6
JK		 3645 }
3646 if (to_vmx(vcpu)->nested.vmxon &&
3647 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3648 return 1;
3649
ad312c7c 3650 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3651 if (enable_ept) {
3652 if (!is_paging(vcpu)) {
3653 hw_cr4 &= ~X86_CR4_PAE;
3654 hw_cr4 |= X86_CR4_PSE;
c08800a5 3655 /*
e1e746b3
FW		 3656 * SMEP/SMAP is disabled if CPU is in non-paging mode
3657 * in hardware. However KVM always uses paging mode to
c08800a5 3658 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3659 * To emulate this behavior, SMEP/SMAP needs to be
3660 * manually disabled when guest switches to non-paging
3661 * mode.
c08800a5 3662 */
e1e746b3 3663 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3664 } else if (!(cr4 & X86_CR4_PAE)) {
3665 hw_cr4 &= ~X86_CR4_PAE;
3666 }
3667 }
1439442c
SY		 3668
3669 vmcs_writel(CR4_READ_SHADOW, cr4);
3670 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3671 return 0;
6aa8b732
AK		 3672}
3673
6aa8b732
AK		 3674static void vmx_get_segment(struct kvm_vcpu *vcpu,
3675 struct kvm_segment *var, int seg)
3676{
a9179499 3677 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3678 u32 ar;
3679
c6ad1153 3680 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3681 *var = vmx->rmode.segs[seg];
a9179499 3682 if (seg == VCPU_SREG_TR
2fb92db1 3683 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3684 return;
1390a28b
AK		 3685 var->base = vmx_read_guest_seg_base(vmx, seg);
3686 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3687 return;
a9179499 3688 }
2fb92db1
AK		 3689 var->base = vmx_read_guest_seg_base(vmx, seg);
3690 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3691 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3692 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3693 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3694 var->type = ar & 15;
3695 var->s = (ar >> 4) & 1;
3696 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3697 /*
3698 * Some userspaces do not preserve unusable property. Since usable
3699 * segment has to be present according to VMX spec we can use present
3700 * property to amend userspace bug by making unusable segment always
3701 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3702 * segment as unusable.
3703 */
3704 var->present = !var->unusable;
6aa8b732
AK		 3705 var->avl = (ar >> 12) & 1;
3706 var->l = (ar >> 13) & 1;
3707 var->db = (ar >> 14) & 1;
3708 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3709}
3710
a9179499
AK		 3711static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3712{
a9179499
AK		 3713 struct kvm_segment s;
3714
3715 if (to_vmx(vcpu)->rmode.vm86_active) {
3716 vmx_get_segment(vcpu, &s, seg);
3717 return s.base;
3718 }
2fb92db1 3719 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3720}
3721
b09408d0 3722static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3723{
b09408d0
MT		 3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725
ae9fedc7 3726 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3727 return 0;
ae9fedc7
PB		 3728 else {
3729 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3730 return AR_DPL(ar);
69c73028 3731 }
69c73028
AK		 3732}
3733
653e3108 3734static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3735{
6aa8b732
AK		 3736 u32 ar;
3737
f0495f9b 3738 if (var->unusable || !var->present)
6aa8b732
AK		 3739 ar = 1 << 16;
3740 else {
3741 ar = var->type & 15;
3742 ar |= (var->s & 1) << 4;
3743 ar |= (var->dpl & 3) << 5;
3744 ar |= (var->present & 1) << 7;
3745 ar |= (var->avl & 1) << 12;
3746 ar |= (var->l & 1) << 13;
3747 ar |= (var->db & 1) << 14;
3748 ar |= (var->g & 1) << 15;
3749 }
653e3108
AK		 3750
3751 return ar;
3752}
3753
3754static void vmx_set_segment(struct kvm_vcpu *vcpu,
3755 struct kvm_segment *var, int seg)
3756{
7ffd92c5 3757 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3758 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3759
2fb92db1
AK		 3760 vmx_segment_cache_clear(vmx);
3761
1ecd50a9
GN		 3762 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3763 vmx->rmode.segs[seg] = *var;
3764 if (seg == VCPU_SREG_TR)
3765 vmcs_write16(sf->selector, var->selector);
3766 else if (var->s)
3767 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3768 goto out;
653e3108 3769 }
1ecd50a9 3770
653e3108
AK		 3771 vmcs_writel(sf->base, var->base);
3772 vmcs_write32(sf->limit, var->limit);
3773 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3774
3775 /*
3776 * Fix the "Accessed" bit in AR field of segment registers for older
3777 * qemu binaries.
3778 * IA32 arch specifies that at the time of processor reset the
3779 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3780 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3781 * state vmexit when "unrestricted guest" mode is turned on.
3782 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3783 * tree. Newer qemu binaries with that qemu fix would not need this
3784 * kvm hack.
3785 */
3786 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3787 var->type |= 0x1; /* Accessed */
3a624e29 3788
f924d66d 3789 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3790
3791out:
98eb2f8b 3792 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3793}
3794
6aa8b732
AK		 3795static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3796{
2fb92db1 3797 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3798
3799 *db = (ar >> 14) & 1;
3800 *l = (ar >> 13) & 1;
3801}
3802
89a27f4d 3803static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3804{
89a27f4d
GN		 3805 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3806 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3807}
3808
89a27f4d 3809static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3810{
89a27f4d
GN		 3811 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3812 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3813}
3814
89a27f4d 3815static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3816{
89a27f4d
GN		 3817 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3818 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3819}
3820
89a27f4d 3821static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3822{
89a27f4d
GN		 3823 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3824 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3825}
3826
648dfaa7
MG		 3827static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3828{
3829 struct kvm_segment var;
3830 u32 ar;
3831
3832 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3833 var.dpl = 0x3;
0647f4aa
GN		 3834 if (seg == VCPU_SREG_CS)
3835 var.type = 0x3;
648dfaa7
MG		 3836 ar = vmx_segment_access_rights(&var);
3837
3838 if (var.base != (var.selector << 4))
3839 return false;
89efbed0 3840 if (var.limit != 0xffff)
648dfaa7 3841 return false;
07f42f5f 3842 if (ar != 0xf3)
648dfaa7
MG		 3843 return false;
3844
3845 return true;
3846}
3847
3848static bool code_segment_valid(struct kvm_vcpu *vcpu)
3849{
3850 struct kvm_segment cs;
3851 unsigned int cs_rpl;
3852
3853 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3854 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3855
1872a3f4
AK		 3856 if (cs.unusable)
3857 return false;
648dfaa7
MG		 3858 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3859 return false;
3860 if (!cs.s)
3861 return false;
1872a3f4 3862 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3863 if (cs.dpl > cs_rpl)
3864 return false;
1872a3f4 3865 } else {
648dfaa7
MG		 3866 if (cs.dpl != cs_rpl)
3867 return false;
3868 }
3869 if (!cs.present)
3870 return false;
3871
3872 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3873 return true;
3874}
3875
3876static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3877{
3878 struct kvm_segment ss;
3879 unsigned int ss_rpl;
3880
3881 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3882 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3883
1872a3f4
AK		 3884 if (ss.unusable)
3885 return true;
3886 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3887 return false;
3888 if (!ss.s)
3889 return false;
3890 if (ss.dpl != ss_rpl) /* DPL != RPL */
3891 return false;
3892 if (!ss.present)
3893 return false;
3894
3895 return true;
3896}
3897
3898static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3899{
3900 struct kvm_segment var;
3901 unsigned int rpl;
3902
3903 vmx_get_segment(vcpu, &var, seg);
b32a9918 3904 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3905
1872a3f4
AK		 3906 if (var.unusable)
3907 return true;
648dfaa7
MG		 3908 if (!var.s)
3909 return false;
3910 if (!var.present)
3911 return false;
3912 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3913 if (var.dpl < rpl) /* DPL < RPL */
3914 return false;
3915 }
3916
3917 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3918 * rights flags
3919 */
3920 return true;
3921}
3922
3923static bool tr_valid(struct kvm_vcpu *vcpu)
3924{
3925 struct kvm_segment tr;
3926
3927 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3928
1872a3f4
AK		 3929 if (tr.unusable)
3930 return false;
b32a9918 3931 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3932 return false;
1872a3f4 3933 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3934 return false;
3935 if (!tr.present)
3936 return false;
3937
3938 return true;
3939}
3940
3941static bool ldtr_valid(struct kvm_vcpu *vcpu)
3942{
3943 struct kvm_segment ldtr;
3944
3945 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3946
1872a3f4
AK		 3947 if (ldtr.unusable)
3948 return true;
b32a9918 3949 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3950 return false;
3951 if (ldtr.type != 2)
3952 return false;
3953 if (!ldtr.present)
3954 return false;
3955
3956 return true;
3957}
3958
3959static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3960{
3961 struct kvm_segment cs, ss;
3962
3963 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3964 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3965
b32a9918
NA		 3966 return ((cs.selector & SEGMENT_RPL_MASK) ==
3967 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3968}
3969
3970/*
3971 * Check if guest state is valid. Returns true if valid, false if
3972 * not.
3973 * We assume that registers are always usable
3974 */
3975static bool guest_state_valid(struct kvm_vcpu *vcpu)
3976{
c5e97c80
GN		 3977 if (enable_unrestricted_guest)
3978 return true;
3979
648dfaa7 3980 /* real mode guest state checks */
f13882d8 3981 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3982 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3983 return false;
3984 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3985 return false;
3986 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3987 return false;
3988 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3989 return false;
3990 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3991 return false;
3992 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3993 return false;
3994 } else {
3995 /* protected mode guest state checks */
3996 if (!cs_ss_rpl_check(vcpu))
3997 return false;
3998 if (!code_segment_valid(vcpu))
3999 return false;
4000 if (!stack_segment_valid(vcpu))
4001 return false;
4002 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4003 return false;
4004 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4005 return false;
4006 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4007 return false;
4008 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4009 return false;
4010 if (!tr_valid(vcpu))
4011 return false;
4012 if (!ldtr_valid(vcpu))
4013 return false;
4014 }
4015 /* TODO:
4016 * - Add checks on RIP
4017 * - Add checks on RFLAGS
4018 */
4019
4020 return true;
4021}
4022
d77c26fc 4023static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4024{
40dcaa9f 4025 gfn_t fn;
195aefde 4026 u16 data = 0;
1f755a82 4027 int idx, r;
6aa8b732 4028
40dcaa9f 4029 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4030 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4031 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4032 if (r < 0)
10589a46 4033 goto out;
195aefde 4034 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4035 r = kvm_write_guest_page(kvm, fn++, &data,
4036 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4037 if (r < 0)
10589a46 4038 goto out;
195aefde
IE		 4039 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4040 if (r < 0)
10589a46 4041 goto out;
195aefde
IE		 4042 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4043 if (r < 0)
10589a46 4044 goto out;
195aefde 4045 data = ~0;
10589a46
MT		 4046 r = kvm_write_guest_page(kvm, fn, &data,
4047 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4048 sizeof(u8));
10589a46 4049out:
40dcaa9f 4050 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4051 return r;
6aa8b732
AK		 4052}
4053
b7ebfb05
SY		 4054static int init_rmode_identity_map(struct kvm *kvm)
4055{
f51770ed 4056 int i, idx, r = 0;
b7ebfb05
SY		 4057 pfn_t identity_map_pfn;
4058 u32 tmp;
4059
089d034e 4060 if (!enable_ept)
f51770ed 4061 return 0;
a255d479
TC		 4062
4063 /* Protect kvm->arch.ept_identity_pagetable_done. */
4064 mutex_lock(&kvm->slots_lock);
4065
f51770ed 4066 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4067 goto out2;
a255d479 4068
b927a3ce 4069 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4070
4071 r = alloc_identity_pagetable(kvm);
f51770ed 4072 if (r < 0)
a255d479
TC		 4073 goto out2;
4074
40dcaa9f 4075 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4076 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4077 if (r < 0)
4078 goto out;
4079 /* Set up identity-mapping pagetable for EPT in real mode */
4080 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4081 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4082 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4083 r = kvm_write_guest_page(kvm, identity_map_pfn,
4084 &tmp, i * sizeof(tmp), sizeof(tmp));
4085 if (r < 0)
4086 goto out;
4087 }
4088 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4089
b7ebfb05 4090out:
40dcaa9f 4091 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4092
4093out2:
4094 mutex_unlock(&kvm->slots_lock);
f51770ed 4095 return r;
b7ebfb05
SY		 4096}
4097
6aa8b732
AK		 4098static void seg_setup(int seg)
4099{
772e0318 4100 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4101 unsigned int ar;
6aa8b732
AK		 4102
4103 vmcs_write16(sf->selector, 0);
4104 vmcs_writel(sf->base, 0);
4105 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4106 ar = 0x93;
4107 if (seg == VCPU_SREG_CS)
4108 ar |= 0x08; /* code segment */
3a624e29
NK		 4109
4110 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4111}
4112
f78e0e2e
SY		 4113static int alloc_apic_access_page(struct kvm *kvm)
4114{
4484141a 4115 struct page *page;
f78e0e2e
SY		 4116 struct kvm_userspace_memory_region kvm_userspace_mem;
4117 int r = 0;
4118
79fac95e 4119 mutex_lock(&kvm->slots_lock);
c24ae0dc 4120 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4121 goto out;
4122 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4123 kvm_userspace_mem.flags = 0;
73a6d941 4124 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4125 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4126 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4127 if (r)
4128 goto out;
72dc67a6 4129
73a6d941 4130 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4131 if (is_error_page(page)) {
4132 r = -EFAULT;
4133 goto out;
4134 }
4135
c24ae0dc
TC		 4136 /*
4137 * Do not pin the page in memory, so that memory hot-unplug
4138 * is able to migrate it.
4139 */
4140 put_page(page);
4141 kvm->arch.apic_access_page_done = true;
f78e0e2e 4142out:
79fac95e 4143 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4144 return r;
4145}
4146
b7ebfb05
SY		 4147static int alloc_identity_pagetable(struct kvm *kvm)
4148{
a255d479
TC		 4149 /* Called with kvm->slots_lock held. */
4150
b7ebfb05
SY		 4151 struct kvm_userspace_memory_region kvm_userspace_mem;
4152 int r = 0;
4153
a255d479
TC		 4154 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4155
b7ebfb05
SY		 4156 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4157 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4158 kvm_userspace_mem.guest_phys_addr =
4159 kvm->arch.ept_identity_map_addr;
b7ebfb05 4160 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4161 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4162
b7ebfb05
SY		 4163 return r;
4164}
4165
2384d2b3
SY		 4166static void allocate_vpid(struct vcpu_vmx *vmx)
4167{
4168 int vpid;
4169
4170 vmx->vpid = 0;
919818ab 4171 if (!enable_vpid)
2384d2b3
SY		 4172 return;
4173 spin_lock(&vmx_vpid_lock);
4174 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4175 if (vpid < VMX_NR_VPIDS) {
4176 vmx->vpid = vpid;
4177 __set_bit(vpid, vmx_vpid_bitmap);
4178 }
4179 spin_unlock(&vmx_vpid_lock);
4180}
4181
cdbecfc3
LJ		 4182static void free_vpid(struct vcpu_vmx *vmx)
4183{
4184 if (!enable_vpid)
4185 return;
4186 spin_lock(&vmx_vpid_lock);
4187 if (vmx->vpid != 0)
4188 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4189 spin_unlock(&vmx_vpid_lock);
4190}
4191
8d14695f
YZ		 4192#define MSR_TYPE_R 1
4193#define MSR_TYPE_W 2
4194static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4195 u32 msr, int type)
25c5f225 4196{
3e7c73e9 4197 int f = sizeof(unsigned long);
25c5f225
SY		 4198
4199 if (!cpu_has_vmx_msr_bitmap())
4200 return;
4201
4202 /*
4203 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4204 * have the write-low and read-high bitmap offsets the wrong way round.
4205 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4206 */
25c5f225 4207 if (msr <= 0x1fff) {
8d14695f
YZ		 4208 if (type & MSR_TYPE_R)
4209 /* read-low */
4210 __clear_bit(msr, msr_bitmap + 0x000 / f);
4211
4212 if (type & MSR_TYPE_W)
4213 /* write-low */
4214 __clear_bit(msr, msr_bitmap + 0x800 / f);
4215
25c5f225
SY		 4216 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4217 msr &= 0x1fff;
8d14695f
YZ		 4218 if (type & MSR_TYPE_R)
4219 /* read-high */
4220 __clear_bit(msr, msr_bitmap + 0x400 / f);
4221
4222 if (type & MSR_TYPE_W)
4223 /* write-high */
4224 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4225
4226 }
4227}
4228
4229static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4230 u32 msr, int type)
4231{
4232 int f = sizeof(unsigned long);
4233
4234 if (!cpu_has_vmx_msr_bitmap())
4235 return;
4236
4237 /*
4238 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4239 * have the write-low and read-high bitmap offsets the wrong way round.
4240 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4241 */
4242 if (msr <= 0x1fff) {
4243 if (type & MSR_TYPE_R)
4244 /* read-low */
4245 __set_bit(msr, msr_bitmap + 0x000 / f);
4246
4247 if (type & MSR_TYPE_W)
4248 /* write-low */
4249 __set_bit(msr, msr_bitmap + 0x800 / f);
4250
4251 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4252 msr &= 0x1fff;
4253 if (type & MSR_TYPE_R)
4254 /* read-high */
4255 __set_bit(msr, msr_bitmap + 0x400 / f);
4256
4257 if (type & MSR_TYPE_W)
4258 /* write-high */
4259 __set_bit(msr, msr_bitmap + 0xc00 / f);
4260
25c5f225 4261 }
25c5f225
SY		 4262}
4263
f2b93280
WV		 4264/*
4265 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4266 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4267 */
4268static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4269 unsigned long *msr_bitmap_nested,
4270 u32 msr, int type)
4271{
4272 int f = sizeof(unsigned long);
4273
4274 if (!cpu_has_vmx_msr_bitmap()) {
4275 WARN_ON(1);
4276 return;
4277 }
4278
4279 /*
4280 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4281 * have the write-low and read-high bitmap offsets the wrong way round.
4282 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4283 */
4284 if (msr <= 0x1fff) {
4285 if (type & MSR_TYPE_R &&
4286 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4287 /* read-low */
4288 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4289
4290 if (type & MSR_TYPE_W &&
4291 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4292 /* write-low */
4293 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4294
4295 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4296 msr &= 0x1fff;
4297 if (type & MSR_TYPE_R &&
4298 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4299 /* read-high */
4300 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4301
4302 if (type & MSR_TYPE_W &&
4303 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4304 /* write-high */
4305 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4306
4307 }
4308}
4309
5897297b
AK		 4310static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4311{
4312 if (!longmode_only)
8d14695f
YZ		 4313 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4314 msr, MSR_TYPE_R | MSR_TYPE_W);
4315 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4316 msr, MSR_TYPE_R | MSR_TYPE_W);
4317}
4318
4319static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4320{
4321 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4322 msr, MSR_TYPE_R);
4323 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4324 msr, MSR_TYPE_R);
4325}
4326
4327static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4328{
4329 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4330 msr, MSR_TYPE_R);
4331 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4332 msr, MSR_TYPE_R);
4333}
4334
4335static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4336{
4337 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4338 msr, MSR_TYPE_W);
4339 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4340 msr, MSR_TYPE_W);
5897297b
AK		 4341}
4342
01e439be
YZ		 4343static int vmx_vm_has_apicv(struct kvm *kvm)
4344{
4345 return enable_apicv && irqchip_in_kernel(kvm);
4346}
4347
705699a1
WV		 4348static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4349{
4350 struct vcpu_vmx *vmx = to_vmx(vcpu);
4351 int max_irr;
4352 void *vapic_page;
4353 u16 status;
4354
4355 if (vmx->nested.pi_desc &&
4356 vmx->nested.pi_pending) {
4357 vmx->nested.pi_pending = false;
4358 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4359 return 0;
4360
4361 max_irr = find_last_bit(
4362 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4363
4364 if (max_irr == 256)
4365 return 0;
4366
4367 vapic_page = kmap(vmx->nested.virtual_apic_page);
4368 if (!vapic_page) {
4369 WARN_ON(1);
4370 return -ENOMEM;
4371 }
4372 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4373 kunmap(vmx->nested.virtual_apic_page);
4374
4375 status = vmcs_read16(GUEST_INTR_STATUS);
4376 if ((u8)max_irr > ((u8)status & 0xff)) {
4377 status &= ~0xff;
4378 status |= (u8)max_irr;
4379 vmcs_write16(GUEST_INTR_STATUS, status);
4380 }
4381 }
4382 return 0;
4383}
4384
21bc8dc5
RK		 4385static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4386{
4387#ifdef CONFIG_SMP
4388 if (vcpu->mode == IN_GUEST_MODE) {
4389 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4390 POSTED_INTR_VECTOR);
4391 return true;
4392 }
4393#endif
4394 return false;
4395}
4396
705699a1
WV		 4397static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4398 int vector)
4399{
4400 struct vcpu_vmx *vmx = to_vmx(vcpu);
4401
4402 if (is_guest_mode(vcpu) &&
4403 vector == vmx->nested.posted_intr_nv) {
4404 /* the PIR and ON have been set by L1. */
21bc8dc5 4405 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4406 /*
4407 * If a posted intr is not recognized by hardware,
4408 * we will accomplish it in the next vmentry.
4409 */
4410 vmx->nested.pi_pending = true;
4411 kvm_make_request(KVM_REQ_EVENT, vcpu);
4412 return 0;
4413 }
4414 return -1;
4415}
a20ed54d
YZ		 4416/*
4417 * Send interrupt to vcpu via posted interrupt way.
4418 * 1. If target vcpu is running(non-root mode), send posted interrupt
4419 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4420 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4421 * interrupt from PIR in next vmentry.
4422 */
4423static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4424{
4425 struct vcpu_vmx *vmx = to_vmx(vcpu);
4426 int r;
4427
705699a1
WV		 4428 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4429 if (!r)
4430 return;
4431
a20ed54d
YZ		 4432 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4433 return;
4434
4435 r = pi_test_and_set_on(&vmx->pi_desc);
4436 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4437 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4438 kvm_vcpu_kick(vcpu);
4439}
4440
4441static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4442{
4443 struct vcpu_vmx *vmx = to_vmx(vcpu);
4444
4445 if (!pi_test_and_clear_on(&vmx->pi_desc))
4446 return;
4447
4448 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4449}
4450
4451static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4452{
4453 return;
4454}
4455
a3a8ff8e
NHE		 4456/*
4457 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4458 * will not change in the lifetime of the guest.
4459 * Note that host-state that does change is set elsewhere. E.g., host-state
4460 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4461 */
a547c6db 4462static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4463{
4464 u32 low32, high32;
4465 unsigned long tmpl;
4466 struct desc_ptr dt;
d974baa3 4467 unsigned long cr4;
a3a8ff8e 4468
b1a74bf8 4469 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4470 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4471
d974baa3 4472 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4473 cr4 = cr4_read_shadow();
d974baa3
AL		 4474 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4475 vmx->host_state.vmcs_host_cr4 = cr4;
4476
a3a8ff8e 4477 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4478#ifdef CONFIG_X86_64
4479 /*
4480 * Load null selectors, so we can avoid reloading them in
4481 * __vmx_load_host_state(), in case userspace uses the null selectors
4482 * too (the expected case).
4483 */
4484 vmcs_write16(HOST_DS_SELECTOR, 0);
4485 vmcs_write16(HOST_ES_SELECTOR, 0);
4486#else
a3a8ff8e
NHE		 4487 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4488 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4489#endif
a3a8ff8e
NHE		 4490 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4491 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4492
4493 native_store_idt(&dt);
4494 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4495 vmx->host_idt_base = dt.address;
a3a8ff8e 4496
83287ea4 4497 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4498
4499 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4500 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4501 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4502 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4503
4504 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4505 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4506 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4507 }
4508}
4509
bf8179a0
NHE		 4510static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4511{
4512 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4513 if (enable_ept)
4514 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4515 if (is_guest_mode(&vmx->vcpu))
4516 vmx->vcpu.arch.cr4_guest_owned_bits &=
4517 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4518 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4519}
4520
01e439be
YZ		 4521static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4522{
4523 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4524
4525 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4526 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4527 return pin_based_exec_ctrl;
4528}
4529
bf8179a0
NHE		 4530static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4531{
4532 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4533
4534 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4535 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4536
bf8179a0
NHE		 4537 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4538 exec_control &= ~CPU_BASED_TPR_SHADOW;
4539#ifdef CONFIG_X86_64
4540 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4541 CPU_BASED_CR8_LOAD_EXITING;
4542#endif
4543 }
4544 if (!enable_ept)
4545 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4546 CPU_BASED_CR3_LOAD_EXITING |
4547 CPU_BASED_INVLPG_EXITING;
4548 return exec_control;
4549}
4550
4551static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4552{
4553 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4554 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4555 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4556 if (vmx->vpid == 0)
4557 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4558 if (!enable_ept) {
4559 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4560 enable_unrestricted_guest = 0;
ad756a16
MJ		 4561 /* Enable INVPCID for non-ept guests may cause performance regression. */
4562 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4563 }
4564 if (!enable_unrestricted_guest)
4565 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4566 if (!ple_gap)
4567 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4568 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4569 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4570 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4571 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4572 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4573 (handle_vmptrld).
4574 We can NOT enable shadow_vmcs here because we don't have yet
4575 a current VMCS12
4576 */
4577 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4578 /* PML is enabled/disabled in creating/destorying vcpu */
4579 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4580
bf8179a0
NHE		 4581 return exec_control;
4582}
4583
ce88decf
XG		 4584static void ept_set_mmio_spte_mask(void)
4585{
4586 /*
4587 * EPT Misconfigurations can be generated if the value of bits 2:0
4588 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4589 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4590 * spte.
4591 */
885032b9 4592 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4593}
4594
f53cd63c 4595#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4596/*
4597 * Sets up the vmcs for emulated real mode.
4598 */
8b9cf98c 4599static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4600{
2e4ce7f5 4601#ifdef CONFIG_X86_64
6aa8b732 4602 unsigned long a;
2e4ce7f5 4603#endif
6aa8b732 4604 int i;
6aa8b732 4605
6aa8b732 4606 /* I/O */
3e7c73e9
AK		 4607 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4608 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4609
4607c2d7
AG		 4610 if (enable_shadow_vmcs) {
4611 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4612 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4613 }
25c5f225 4614 if (cpu_has_vmx_msr_bitmap())
5897297b 4615 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4616
6aa8b732
AK		 4617 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4618
6aa8b732 4619 /* Control */
01e439be 4620 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4621
bf8179a0 4622 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4623
83ff3b9d 4624 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4625 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4626 vmx_secondary_exec_control(vmx));
83ff3b9d 4627 }
f78e0e2e 4628
01e439be 4629 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4630 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4631 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4632 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4633 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4634
4635 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4636
4637 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4638 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4639 }
4640
4b8d54f9
ZE		 4641 if (ple_gap) {
4642 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4643 vmx->ple_window = ple_window;
4644 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4645 }
4646
c3707958
XG		 4647 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4648 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4649 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4650
9581d442
AK		 4651 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4652 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4653 vmx_set_constant_host_state(vmx);
05b3e0c2 4654#ifdef CONFIG_X86_64
6aa8b732
AK		 4655 rdmsrl(MSR_FS_BASE, a);
4656 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4657 rdmsrl(MSR_GS_BASE, a);
4658 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4659#else
4660 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4661 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4662#endif
4663
2cc51560
ED		 4664 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4665 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4666 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4667 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4668 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4669
74545705
RK		 4670 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4671 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4672
03916db9 4673 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4674 u32 index = vmx_msr_index[i];
4675 u32 data_low, data_high;
a2fa3e9f 4676 int j = vmx->nmsrs;
6aa8b732
AK		 4677
4678 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4679 continue;
432bd6cb
AK		 4680 if (wrmsr_safe(index, data_low, data_high) < 0)
4681 continue;
26bb0981
AK		 4682 vmx->guest_msrs[j].index = i;
4683 vmx->guest_msrs[j].data = 0;
d5696725 4684 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4685 ++vmx->nmsrs;
6aa8b732 4686 }
6aa8b732 4687
2961e876
GN		 4688
4689 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4690
4691 /* 22.2.1, 20.8.1 */
2961e876 4692 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4693
e00c8cf2 4694 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4695 set_cr4_guest_host_mask(vmx);
e00c8cf2 4696
f53cd63c
WL		 4697 if (vmx_xsaves_supported())
4698 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4699
e00c8cf2
AK		 4700 return 0;
4701}
4702
d28bc9dd 4703static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4704{
4705 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4706 struct msr_data apic_base_msr;
d28bc9dd 4707 u64 cr0;
e00c8cf2 4708
7ffd92c5 4709 vmx->rmode.vm86_active = 0;
e00c8cf2 4710
3b86cd99
JK		 4711 vmx->soft_vnmi_blocked = 0;
4712
ad312c7c 4713 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4714 kvm_set_cr8(vcpu, 0);
4715
4716 if (!init_event) {
4717 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4718 MSR_IA32_APICBASE_ENABLE;
4719 if (kvm_vcpu_is_reset_bsp(vcpu))
4720 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4721 apic_base_msr.host_initiated = true;
4722 kvm_set_apic_base(vcpu, &apic_base_msr);
4723 }
e00c8cf2 4724
2fb92db1
AK		 4725 vmx_segment_cache_clear(vmx);
4726
5706be0d 4727 seg_setup(VCPU_SREG_CS);
66450a21 4728 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4729 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4730
4731 seg_setup(VCPU_SREG_DS);
4732 seg_setup(VCPU_SREG_ES);
4733 seg_setup(VCPU_SREG_FS);
4734 seg_setup(VCPU_SREG_GS);
4735 seg_setup(VCPU_SREG_SS);
4736
4737 vmcs_write16(GUEST_TR_SELECTOR, 0);
4738 vmcs_writel(GUEST_TR_BASE, 0);
4739 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4740 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4741
4742 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4743 vmcs_writel(GUEST_LDTR_BASE, 0);
4744 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4745 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4746
d28bc9dd
NA		 4747 if (!init_event) {
4748 vmcs_write32(GUEST_SYSENTER_CS, 0);
4749 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4750 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4751 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4752 }
e00c8cf2
AK		 4753
4754 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4755 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4756
e00c8cf2
AK		 4757 vmcs_writel(GUEST_GDTR_BASE, 0);
4758 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4759
4760 vmcs_writel(GUEST_IDTR_BASE, 0);
4761 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4762
443381a8 4763 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4764 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4765 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4766
e00c8cf2
AK		 4767 setup_msrs(vmx);
4768
6aa8b732
AK		 4769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4770
d28bc9dd 4771 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4772 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
d28bc9dd 4773 if (vm_need_tpr_shadow(vcpu->kvm))
f78e0e2e 4774 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4775 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4776 vmcs_write32(TPR_THRESHOLD, 0);
4777 }
4778
a73896cb 4779 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4780
01e439be
YZ		 4781 if (vmx_vm_has_apicv(vcpu->kvm))
4782 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4783
2384d2b3
SY		 4784 if (vmx->vpid != 0)
4785 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4786
d28bc9dd
NA		 4787 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4788 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4789 vmx->vcpu.arch.cr0 = cr0;
4790 vmx_set_cr4(vcpu, 0);
4791 if (!init_event)
4792 vmx_set_efer(vcpu, 0);
4793 vmx_fpu_activate(vcpu);
4794 update_exception_bitmap(vcpu);
6aa8b732 4795
b9d762fa 4796 vpid_sync_context(vmx);
6aa8b732
AK		 4797}
4798
b6f1250e
NHE		 4799/*
4800 * In nested virtualization, check if L1 asked to exit on external interrupts.
4801 * For most existing hypervisors, this will always return true.
4802 */
4803static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4804{
4805 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4806 PIN_BASED_EXT_INTR_MASK;
4807}
4808
77b0f5d6
BD		 4809/*
4810 * In nested virtualization, check if L1 has set
4811 * VM_EXIT_ACK_INTR_ON_EXIT
4812 */
4813static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4814{
4815 return get_vmcs12(vcpu)->vm_exit_controls &
4816 VM_EXIT_ACK_INTR_ON_EXIT;
4817}
4818
ea8ceb83
JK		 4819static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4820{
4821 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4822 PIN_BASED_NMI_EXITING;
4823}
4824
c9a7953f 4825static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4826{
4827 u32 cpu_based_vm_exec_control;
730dca42 4828
3b86cd99
JK		 4829 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4830 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4831 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4832}
4833
c9a7953f 4834static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4835{
4836 u32 cpu_based_vm_exec_control;
4837
c9a7953f
JK		 4838 if (!cpu_has_virtual_nmis() ||
4839 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4840 enable_irq_window(vcpu);
4841 return;
4842 }
3b86cd99
JK		 4843
4844 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4845 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4846 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4847}
4848
66fd3f7f 4849static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4850{
9c8cba37 4851 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4852 uint32_t intr;
4853 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4854
229456fc 4855 trace_kvm_inj_virq(irq);
2714d1d3 4856
fa89a817 4857 ++vcpu->stat.irq_injections;
7ffd92c5 4858 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4859 int inc_eip = 0;
4860 if (vcpu->arch.interrupt.soft)
4861 inc_eip = vcpu->arch.event_exit_inst_len;
4862 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4863 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4864 return;
4865 }
66fd3f7f
GN		 4866 intr = irq | INTR_INFO_VALID_MASK;
4867 if (vcpu->arch.interrupt.soft) {
4868 intr |= INTR_TYPE_SOFT_INTR;
4869 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4870 vmx->vcpu.arch.event_exit_inst_len);
4871 } else
4872 intr |= INTR_TYPE_EXT_INTR;
4873 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4874}
4875
f08864b4
SY		 4876static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4877{
66a5a347
JK		 4878 struct vcpu_vmx *vmx = to_vmx(vcpu);
4879
0b6ac343
NHE		 4880 if (is_guest_mode(vcpu))
4881 return;
4882
3b86cd99
JK		 4883 if (!cpu_has_virtual_nmis()) {
4884 /*
4885 * Tracking the NMI-blocked state in software is built upon
4886 * finding the next open IRQ window. This, in turn, depends on
4887 * well-behaving guests: They have to keep IRQs disabled at
4888 * least as long as the NMI handler runs. Otherwise we may
4889 * cause NMI nesting, maybe breaking the guest. But as this is
4890 * highly unlikely, we can live with the residual risk.
4891 */
4892 vmx->soft_vnmi_blocked = 1;
4893 vmx->vnmi_blocked_time = 0;
4894 }
4895
487b391d 4896 ++vcpu->stat.nmi_injections;
9d58b931 4897 vmx->nmi_known_unmasked = false;
7ffd92c5 4898 if (vmx->rmode.vm86_active) {
71f9833b 4899 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4900 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4901 return;
4902 }
f08864b4
SY		 4903 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4904 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4905}
4906
3cfc3092
JK		 4907static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4908{
4909 if (!cpu_has_virtual_nmis())
4910 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4911 if (to_vmx(vcpu)->nmi_known_unmasked)
4912 return false;
c332c83a 4913 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4914}
4915
4916static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4917{
4918 struct vcpu_vmx *vmx = to_vmx(vcpu);
4919
4920 if (!cpu_has_virtual_nmis()) {
4921 if (vmx->soft_vnmi_blocked != masked) {
4922 vmx->soft_vnmi_blocked = masked;
4923 vmx->vnmi_blocked_time = 0;
4924 }
4925 } else {
9d58b931 4926 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4927 if (masked)
4928 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4929 GUEST_INTR_STATE_NMI);
4930 else
4931 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4932 GUEST_INTR_STATE_NMI);
4933 }
4934}
4935
2505dc9f
JK		 4936static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4937{
b6b8a145
JK		 4938 if (to_vmx(vcpu)->nested.nested_run_pending)
4939 return 0;
ea8ceb83 4940
2505dc9f
JK		 4941 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4942 return 0;
4943
4944 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4945 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4946 | GUEST_INTR_STATE_NMI));
4947}
4948
78646121
GN		 4949static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4950{
b6b8a145
JK		 4951 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4952 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4953 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4954 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4955}
4956
cbc94022
IE		 4957static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4958{
4959 int ret;
4960 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4961 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4962 .guest_phys_addr = addr,
4963 .memory_size = PAGE_SIZE * 3,
4964 .flags = 0,
4965 };
4966
47ae31e2 4967 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4968 if (ret)
4969 return ret;
bfc6d222 4970 kvm->arch.tss_addr = addr;
1f755a82 4971 return init_rmode_tss(kvm);
cbc94022
IE		 4972}
4973
0ca1b4f4 4974static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4975{
77ab6db0 4976 switch (vec) {
77ab6db0 4977 case BP_VECTOR:
c573cd22
JK		 4978 /*
4979 * Update instruction length as we may reinject the exception
4980 * from user space while in guest debugging mode.
4981 */
4982 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4983 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4984 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4985 return false;
4986 /* fall through */
4987 case DB_VECTOR:
4988 if (vcpu->guest_debug &
4989 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4990 return false;
d0bfb940
JK		 4991 /* fall through */
4992 case DE_VECTOR:
77ab6db0
JK		 4993 case OF_VECTOR:
4994 case BR_VECTOR:
4995 case UD_VECTOR:
4996 case DF_VECTOR:
4997 case SS_VECTOR:
4998 case GP_VECTOR:
4999 case MF_VECTOR:
0ca1b4f4
GN		 5000 return true;
5001 break;
77ab6db0 5002 }
0ca1b4f4
GN		 5003 return false;
5004}
5005
5006static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5007 int vec, u32 err_code)
5008{
5009 /*
5010 * Instruction with address size override prefix opcode 0x67
5011 * Cause the #SS fault with 0 error code in VM86 mode.
5012 */
5013 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5014 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5015 if (vcpu->arch.halt_request) {
5016 vcpu->arch.halt_request = 0;
5cb56059 5017 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5018 }
5019 return 1;
5020 }
5021 return 0;
5022 }
5023
5024 /*
5025 * Forward all other exceptions that are valid in real mode.
5026 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5027 * the required debugging infrastructure rework.
5028 */
5029 kvm_queue_exception(vcpu, vec);
5030 return 1;
6aa8b732
AK		 5031}
5032
a0861c02
AK		 5033/*
5034 * Trigger machine check on the host. We assume all the MSRs are already set up
5035 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5036 * We pass a fake environment to the machine check handler because we want
5037 * the guest to be always treated like user space, no matter what context
5038 * it used internally.
5039 */
5040static void kvm_machine_check(void)
5041{
5042#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5043 struct pt_regs regs = {
5044 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5045 .flags = X86_EFLAGS_IF,
5046 };
5047
5048 do_machine_check(&regs, 0);
5049#endif
5050}
5051
851ba692 5052static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5053{
5054 /* already handled by vcpu_run */
5055 return 1;
5056}
5057
851ba692 5058static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5059{
1155f76a 5060 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5061 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5062 u32 intr_info, ex_no, error_code;
42dbaa5a 5063 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5064 u32 vect_info;
5065 enum emulation_result er;
5066
1155f76a 5067 vect_info = vmx->idt_vectoring_info;
88786475 5068 intr_info = vmx->exit_intr_info;
6aa8b732 5069
a0861c02 5070 if (is_machine_check(intr_info))
851ba692 5071 return handle_machine_check(vcpu);
a0861c02 5072
e4a41889 5073 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5074 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5075
5076 if (is_no_device(intr_info)) {
5fd86fcf 5077 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5078 return 1;
5079 }
5080
7aa81cc0 5081 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5082 if (is_guest_mode(vcpu)) {
5083 kvm_queue_exception(vcpu, UD_VECTOR);
5084 return 1;
5085 }
51d8b661 5086 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5087 if (er != EMULATE_DONE)
7ee5d940 5088 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5089 return 1;
5090 }
5091
6aa8b732 5092 error_code = 0;
2e11384c 5093 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5094 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5095
5096 /*
5097 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5098 * MMIO, it is better to report an internal error.
5099 * See the comments in vmx_handle_exit.
5100 */
5101 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5102 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5103 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5104 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5105 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5106 vcpu->run->internal.data[0] = vect_info;
5107 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5108 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5109 return 0;
5110 }
5111
6aa8b732 5112 if (is_page_fault(intr_info)) {
1439442c 5113 /* EPT won't cause page fault directly */
cf3ace79 5114 BUG_ON(enable_ept);
6aa8b732 5115 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5116 trace_kvm_page_fault(cr2, error_code);
5117
3298b75c 5118 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5119 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5120 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5121 }
5122
d0bfb940 5123 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5124
5125 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5126 return handle_rmode_exception(vcpu, ex_no, error_code);
5127
42dbaa5a
JK		 5128 switch (ex_no) {
5129 case DB_VECTOR:
5130 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5131 if (!(vcpu->guest_debug &
5132 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5133 vcpu->arch.dr6 &= ~15;
6f43ed01 5134 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5135 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5136 skip_emulated_instruction(vcpu);
5137
42dbaa5a
JK		 5138 kvm_queue_exception(vcpu, DB_VECTOR);
5139 return 1;
5140 }
5141 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5142 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5143 /* fall through */
5144 case BP_VECTOR:
c573cd22
JK		 5145 /*
5146 * Update instruction length as we may reinject #BP from
5147 * user space while in guest debugging mode. Reading it for
5148 * #DB as well causes no harm, it is not used in that case.
5149 */
5150 vmx->vcpu.arch.event_exit_inst_len =
5151 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5152 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5153 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5154 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5155 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5156 break;
5157 default:
d0bfb940
JK		 5158 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5159 kvm_run->ex.exception = ex_no;
5160 kvm_run->ex.error_code = error_code;
42dbaa5a 5161 break;
6aa8b732 5162 }
6aa8b732
AK		 5163 return 0;
5164}
5165
851ba692 5166static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5167{
1165f5fe 5168 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5169 return 1;
5170}
5171
851ba692 5172static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5173{
851ba692 5174 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5175 return 0;
5176}
6aa8b732 5177
851ba692 5178static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5179{
bfdaab09 5180 unsigned long exit_qualification;
34c33d16 5181 int size, in, string;
039576c0 5182 unsigned port;
6aa8b732 5183
bfdaab09 5184 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5185 string = (exit_qualification & 16) != 0;
cf8f70bf 5186 in = (exit_qualification & 8) != 0;
e70669ab 5187
cf8f70bf 5188 ++vcpu->stat.io_exits;
e70669ab 5189
cf8f70bf 5190 if (string || in)
51d8b661 5191 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5192
cf8f70bf
GN		 5193 port = exit_qualification >> 16;
5194 size = (exit_qualification & 7) + 1;
e93f36bc 5195 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5196
5197 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5198}
5199
102d8325
IM		 5200static void
5201vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5202{
5203 /*
5204 * Patch in the VMCALL instruction:
5205 */
5206 hypercall[0] = 0x0f;
5207 hypercall[1] = 0x01;
5208 hypercall[2] = 0xc1;
102d8325
IM		 5209}
5210
b9c237bb 5211static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5212{
5213 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5214 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5215
b9c237bb 5216 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5217 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5218 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5219 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5220 return (val & always_on) == always_on;
5221}
5222
0fa06071 5223/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5224static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5225{
eeadf9e7 5226 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5227 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5228 unsigned long orig_val = val;
5229
eeadf9e7
NHE		 5230 /*
5231 * We get here when L2 changed cr0 in a way that did not change
5232 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5233 * but did change L0 shadowed bits. So we first calculate the
5234 * effective cr0 value that L1 would like to write into the
5235 * hardware. It consists of the L2-owned bits from the new
5236 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5237 */
1a0d74e6
JK		 5238 val = (val & ~vmcs12->cr0_guest_host_mask) |
5239 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5240
b9c237bb 5241 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5242 return 1;
1a0d74e6
JK		 5243
5244 if (kvm_set_cr0(vcpu, val))
5245 return 1;
5246 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5247 return 0;
1a0d74e6
JK		 5248 } else {
5249 if (to_vmx(vcpu)->nested.vmxon &&
5250 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5251 return 1;
eeadf9e7 5252 return kvm_set_cr0(vcpu, val);
1a0d74e6 5253 }
eeadf9e7
NHE		 5254}
5255
5256static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5257{
5258 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5259 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5260 unsigned long orig_val = val;
5261
5262 /* analogously to handle_set_cr0 */
5263 val = (val & ~vmcs12->cr4_guest_host_mask) |
5264 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5265 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5266 return 1;
1a0d74e6 5267 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5268 return 0;
5269 } else
5270 return kvm_set_cr4(vcpu, val);
5271}
5272
5273/* called to set cr0 as approriate for clts instruction exit. */
5274static void handle_clts(struct kvm_vcpu *vcpu)
5275{
5276 if (is_guest_mode(vcpu)) {
5277 /*
5278 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5279 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5280 * just pretend it's off (also in arch.cr0 for fpu_activate).
5281 */
5282 vmcs_writel(CR0_READ_SHADOW,
5283 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5284 vcpu->arch.cr0 &= ~X86_CR0_TS;
5285 } else
5286 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5287}
5288
851ba692 5289static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5290{
229456fc 5291 unsigned long exit_qualification, val;
6aa8b732
AK		 5292 int cr;
5293 int reg;
49a9b07e 5294 int err;
6aa8b732 5295
bfdaab09 5296 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5297 cr = exit_qualification & 15;
5298 reg = (exit_qualification >> 8) & 15;
5299 switch ((exit_qualification >> 4) & 3) {
5300 case 0: /* mov to cr */
1e32c079 5301 val = kvm_register_readl(vcpu, reg);
229456fc 5302 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5303 switch (cr) {
5304 case 0:
eeadf9e7 5305 err = handle_set_cr0(vcpu, val);
db8fcefa 5306 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5307 return 1;
5308 case 3:
2390218b 5309 err = kvm_set_cr3(vcpu, val);
db8fcefa 5310 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5311 return 1;
5312 case 4:
eeadf9e7 5313 err = handle_set_cr4(vcpu, val);
db8fcefa 5314 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5315 return 1;
0a5fff19
GN		 5316 case 8: {
5317 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5318 u8 cr8 = (u8)val;
eea1cff9 5319 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5320 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5321 if (irqchip_in_kernel(vcpu->kvm))
5322 return 1;
5323 if (cr8_prev <= cr8)
5324 return 1;
851ba692 5325 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5326 return 0;
5327 }
4b8073e4 5328 }
6aa8b732 5329 break;
25c4c276 5330 case 2: /* clts */
eeadf9e7 5331 handle_clts(vcpu);
4d4ec087 5332 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5333 skip_emulated_instruction(vcpu);
6b52d186 5334 vmx_fpu_activate(vcpu);
25c4c276 5335 return 1;
6aa8b732
AK		 5336 case 1: /*mov from cr*/
5337 switch (cr) {
5338 case 3:
9f8fe504
AK		 5339 val = kvm_read_cr3(vcpu);
5340 kvm_register_write(vcpu, reg, val);
5341 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5342 skip_emulated_instruction(vcpu);
5343 return 1;
5344 case 8:
229456fc
MT		 5345 val = kvm_get_cr8(vcpu);
5346 kvm_register_write(vcpu, reg, val);
5347 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5348 skip_emulated_instruction(vcpu);
5349 return 1;
5350 }
5351 break;
5352 case 3: /* lmsw */
a1f83a74 5353 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5354 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5355 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5356
5357 skip_emulated_instruction(vcpu);
5358 return 1;
5359 default:
5360 break;
5361 }
851ba692 5362 vcpu->run->exit_reason = 0;
a737f256 5363 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5364 (int)(exit_qualification >> 4) & 3, cr);
5365 return 0;
5366}
5367
851ba692 5368static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5369{
bfdaab09 5370 unsigned long exit_qualification;
16f8a6f9
NA		 5371 int dr, dr7, reg;
5372
5373 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5374 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5375
5376 /* First, if DR does not exist, trigger UD */
5377 if (!kvm_require_dr(vcpu, dr))
5378 return 1;
6aa8b732 5379
f2483415 5380 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5381 if (!kvm_require_cpl(vcpu, 0))
5382 return 1;
16f8a6f9
NA		 5383 dr7 = vmcs_readl(GUEST_DR7);
5384 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5385 /*
5386 * As the vm-exit takes precedence over the debug trap, we
5387 * need to emulate the latter, either for the host or the
5388 * guest debugging itself.
5389 */
5390 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5391 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5392 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5393 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5394 vcpu->run->debug.arch.exception = DB_VECTOR;
5395 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5396 return 0;
5397 } else {
7305eb5d 5398 vcpu->arch.dr6 &= ~15;
6f43ed01 5399 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5400 kvm_queue_exception(vcpu, DB_VECTOR);
5401 return 1;
5402 }
5403 }
5404
81908bf4
PB		 5405 if (vcpu->guest_debug == 0) {
5406 u32 cpu_based_vm_exec_control;
5407
5408 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5409 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5410 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5411
5412 /*
5413 * No more DR vmexits; force a reload of the debug registers
5414 * and reenter on this instruction. The next vmexit will
5415 * retrieve the full state of the debug registers.
5416 */
5417 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5418 return 1;
5419 }
5420
42dbaa5a
JK		 5421 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5422 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5423 unsigned long val;
4c4d563b
JK		 5424
5425 if (kvm_get_dr(vcpu, dr, &val))
5426 return 1;
5427 kvm_register_write(vcpu, reg, val);
020df079 5428 } else
5777392e 5429 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5430 return 1;
5431
6aa8b732
AK		 5432 skip_emulated_instruction(vcpu);
5433 return 1;
5434}
5435
73aaf249
JK		 5436static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5437{
5438 return vcpu->arch.dr6;
5439}
5440
5441static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5442{
5443}
5444
81908bf4
PB		 5445static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5446{
5447 u32 cpu_based_vm_exec_control;
5448
5449 get_debugreg(vcpu->arch.db[0], 0);
5450 get_debugreg(vcpu->arch.db[1], 1);
5451 get_debugreg(vcpu->arch.db[2], 2);
5452 get_debugreg(vcpu->arch.db[3], 3);
5453 get_debugreg(vcpu->arch.dr6, 6);
5454 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5455
5456 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5457
5458 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5459 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5461}
5462
020df079
GN		 5463static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5464{
5465 vmcs_writel(GUEST_DR7, val);
5466}
5467
851ba692 5468static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5469{
06465c5a
AK		 5470 kvm_emulate_cpuid(vcpu);
5471 return 1;
6aa8b732
AK		 5472}
5473
851ba692 5474static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5475{
ad312c7c 5476 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5477 u64 data;
5478
5479 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5480 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5481 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5482 return 1;
5483 }
5484
229456fc 5485 trace_kvm_msr_read(ecx, data);
2714d1d3 5486
6aa8b732 5487 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5488 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5489 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5490 skip_emulated_instruction(vcpu);
5491 return 1;
5492}
5493
851ba692 5494static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5495{
8fe8ab46 5496 struct msr_data msr;
ad312c7c
ZX		 5497 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5498 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5499 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5500
8fe8ab46
WA		 5501 msr.data = data;
5502 msr.index = ecx;
5503 msr.host_initiated = false;
854e8bb1 5504 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5505 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5506 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5507 return 1;
5508 }
5509
59200273 5510 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5511 skip_emulated_instruction(vcpu);
5512 return 1;
5513}
5514
851ba692 5515static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5516{
3842d135 5517 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5518 return 1;
5519}
5520
851ba692 5521static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5522{
85f455f7
ED		 5523 u32 cpu_based_vm_exec_control;
5524
5525 /* clear pending irq */
5526 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5527 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5529
3842d135
AK		 5530 kvm_make_request(KVM_REQ_EVENT, vcpu);
5531
a26bf12a 5532 ++vcpu->stat.irq_window_exits;
2714d1d3 5533
c1150d8c
DL		 5534 /*
5535 * If the user space waits to inject interrupts, exit as soon as
5536 * possible
5537 */
8061823a 5538 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5539 vcpu->run->request_interrupt_window &&
8061823a 5540 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5541 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5542 return 0;
5543 }
6aa8b732
AK		 5544 return 1;
5545}
5546
851ba692 5547static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5548{
d3bef15f 5549 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5550}
5551
851ba692 5552static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5553{
7aa81cc0
AL		 5554 kvm_emulate_hypercall(vcpu);
5555 return 1;
c21415e8
IM		 5556}
5557
ec25d5e6
GN		 5558static int handle_invd(struct kvm_vcpu *vcpu)
5559{
51d8b661 5560 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5561}
5562
851ba692 5563static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5564{
f9c617f6 5565 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5566
5567 kvm_mmu_invlpg(vcpu, exit_qualification);
5568 skip_emulated_instruction(vcpu);
5569 return 1;
5570}
5571
fee84b07
AK		 5572static int handle_rdpmc(struct kvm_vcpu *vcpu)
5573{
5574 int err;
5575
5576 err = kvm_rdpmc(vcpu);
5577 kvm_complete_insn_gp(vcpu, err);
5578
5579 return 1;
5580}
5581
851ba692 5582static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5583{
f5f48ee1 5584 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5585 return 1;
5586}
5587
2acf923e
DC		 5588static int handle_xsetbv(struct kvm_vcpu *vcpu)
5589{
5590 u64 new_bv = kvm_read_edx_eax(vcpu);
5591 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5592
5593 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5594 skip_emulated_instruction(vcpu);
5595 return 1;
5596}
5597
f53cd63c
WL		 5598static int handle_xsaves(struct kvm_vcpu *vcpu)
5599{
5600 skip_emulated_instruction(vcpu);
5601 WARN(1, "this should never happen\n");
5602 return 1;
5603}
5604
5605static int handle_xrstors(struct kvm_vcpu *vcpu)
5606{
5607 skip_emulated_instruction(vcpu);
5608 WARN(1, "this should never happen\n");
5609 return 1;
5610}
5611
851ba692 5612static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5613{
58fbbf26
KT		 5614 if (likely(fasteoi)) {
5615 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5616 int access_type, offset;
5617
5618 access_type = exit_qualification & APIC_ACCESS_TYPE;
5619 offset = exit_qualification & APIC_ACCESS_OFFSET;
5620 /*
5621 * Sane guest uses MOV to write EOI, with written value
5622 * not cared. So make a short-circuit here by avoiding
5623 * heavy instruction emulation.
5624 */
5625 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5626 (offset == APIC_EOI)) {
5627 kvm_lapic_set_eoi(vcpu);
5628 skip_emulated_instruction(vcpu);
5629 return 1;
5630 }
5631 }
51d8b661 5632 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5633}
5634
c7c9c56c
YZ		 5635static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5636{
5637 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5638 int vector = exit_qualification & 0xff;
5639
5640 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5641 kvm_apic_set_eoi_accelerated(vcpu, vector);
5642 return 1;
5643}
5644
83d4c286
YZ		 5645static int handle_apic_write(struct kvm_vcpu *vcpu)
5646{
5647 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5648 u32 offset = exit_qualification & 0xfff;
5649
5650 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5651 kvm_apic_write_nodecode(vcpu, offset);
5652 return 1;
5653}
5654
851ba692 5655static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5656{
60637aac 5657 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5658 unsigned long exit_qualification;
e269fb21
JK		 5659 bool has_error_code = false;
5660 u32 error_code = 0;
37817f29 5661 u16 tss_selector;
7f3d35fd 5662 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5663
5664 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5665 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5666 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5667
5668 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5669
5670 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5671 if (reason == TASK_SWITCH_GATE && idt_v) {
5672 switch (type) {
5673 case INTR_TYPE_NMI_INTR:
5674 vcpu->arch.nmi_injected = false;
654f06fc 5675 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5676 break;
5677 case INTR_TYPE_EXT_INTR:
66fd3f7f 5678 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5679 kvm_clear_interrupt_queue(vcpu);
5680 break;
5681 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5682 if (vmx->idt_vectoring_info &
5683 VECTORING_INFO_DELIVER_CODE_MASK) {
5684 has_error_code = true;
5685 error_code =
5686 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5687 }
5688 /* fall through */
64a7ec06
GN		 5689 case INTR_TYPE_SOFT_EXCEPTION:
5690 kvm_clear_exception_queue(vcpu);
5691 break;
5692 default:
5693 break;
5694 }
60637aac 5695 }
37817f29
IE		 5696 tss_selector = exit_qualification;
5697
64a7ec06
GN		 5698 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5699 type != INTR_TYPE_EXT_INTR &&
5700 type != INTR_TYPE_NMI_INTR))
5701 skip_emulated_instruction(vcpu);
5702
7f3d35fd
KW		 5703 if (kvm_task_switch(vcpu, tss_selector,
5704 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5705 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5706 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5707 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5708 vcpu->run->internal.ndata = 0;
42dbaa5a 5709 return 0;
acb54517 5710 }
42dbaa5a
JK		 5711
5712 /* clear all local breakpoint enable flags */
0e8a0996 5713 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5714
5715 /*
5716 * TODO: What about debug traps on tss switch?
5717 * Are we supposed to inject them and update dr6?
5718 */
5719
5720 return 1;
37817f29
IE		 5721}
5722
851ba692 5723static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5724{
f9c617f6 5725 unsigned long exit_qualification;
1439442c 5726 gpa_t gpa;
4f5982a5 5727 u32 error_code;
1439442c 5728 int gla_validity;
1439442c 5729
f9c617f6 5730 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5731
1439442c
SY		 5732 gla_validity = (exit_qualification >> 7) & 0x3;
5733 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5734 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5735 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5736 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5737 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5738 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5739 (long unsigned int)exit_qualification);
851ba692
AK		 5740 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5741 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5742 return 0;
1439442c
SY		 5743 }
5744
0be9c7a8
GN		 5745 /*
5746 * EPT violation happened while executing iret from NMI,
5747 * "blocked by NMI" bit has to be set before next VM entry.
5748 * There are errata that may cause this bit to not be set:
5749 * AAK134, BY25.
5750 */
bcd1c294
GN		 5751 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5752 cpu_has_virtual_nmis() &&
5753 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5754 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5755
1439442c 5756 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5757 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5758
5759 /* It is a write fault? */
81ed33e4 5760 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5761 /* It is a fetch fault? */
81ed33e4 5762 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5763 /* ept page table is present? */
81ed33e4 5764 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5765
25d92081
YZ		 5766 vcpu->arch.exit_qualification = exit_qualification;
5767
4f5982a5 5768 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5769}
5770
68f89400
MT		 5771static u64 ept_rsvd_mask(u64 spte, int level)
5772{
5773 int i;
5774 u64 mask = 0;
5775
5776 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5777 mask |= (1ULL << i);
5778
a32e8459 5779 if (level == 4)
68f89400
MT		 5780 /* bits 7:3 reserved */
5781 mask |= 0xf8;
a32e8459
WL		 5782 else if (spte & (1ULL << 7))
5783 /*
5784 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5785 * level == 1 if the hypervisor is using the ignored bit 7.
5786 */
5787 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5788 else if (level > 1)
5789 /* bits 6:3 reserved */
5790 mask |= 0x78;
68f89400
MT		 5791
5792 return mask;
5793}
5794
5795static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5796 int level)
5797{
5798 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5799
5800 /* 010b (write-only) */
5801 WARN_ON((spte & 0x7) == 0x2);
5802
5803 /* 110b (write/execute) */
5804 WARN_ON((spte & 0x7) == 0x6);
5805
5806 /* 100b (execute-only) and value not supported by logical processor */
5807 if (!cpu_has_vmx_ept_execute_only())
5808 WARN_ON((spte & 0x7) == 0x4);
5809
5810 /* not 000b */
5811 if ((spte & 0x7)) {
5812 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5813
5814 if (rsvd_bits != 0) {
5815 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5816 __func__, rsvd_bits);
5817 WARN_ON(1);
5818 }
5819
a32e8459
WL		 5820 /* bits 5:3 are _not_ reserved for large page or leaf page */
5821 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5822 u64 ept_mem_type = (spte & 0x38) >> 3;
5823
5824 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5825 ept_mem_type == 7) {
5826 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5827 __func__, ept_mem_type);
5828 WARN_ON(1);
5829 }
5830 }
5831 }
5832}
5833
851ba692 5834static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5835{
5836 u64 sptes[4];
ce88decf 5837 int nr_sptes, i, ret;
68f89400
MT		 5838 gpa_t gpa;
5839
5840 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5841 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1
MT		 5842 skip_emulated_instruction(vcpu);
5843 return 1;
5844 }
68f89400 5845
ce88decf 5846 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5847 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5848 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5849 EMULATE_DONE;
f8f55942
XG		 5850
5851 if (unlikely(ret == RET_MMIO_PF_INVALID))
5852 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5853
b37fbea6 5854 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5855 return 1;
5856
5857 /* It is the real ept misconfig */
68f89400
MT		 5858 printk(KERN_ERR "EPT: Misconfiguration.\n");
5859 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5860
5861 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5862
5863 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5864 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5865
851ba692
AK		 5866 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5867 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5868
5869 return 0;
5870}
5871
851ba692 5872static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5873{
5874 u32 cpu_based_vm_exec_control;
5875
5876 /* clear pending NMI */
5877 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5878 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5879 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5880 ++vcpu->stat.nmi_window_exits;
3842d135 5881 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5882
5883 return 1;
5884}
5885
80ced186 5886static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5887{
8b3079a5
AK		 5888 struct vcpu_vmx *vmx = to_vmx(vcpu);
5889 enum emulation_result err = EMULATE_DONE;
80ced186 5890 int ret = 1;
49e9d557
AK		 5891 u32 cpu_exec_ctrl;
5892 bool intr_window_requested;
b8405c18 5893 unsigned count = 130;
49e9d557
AK		 5894
5895 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5896 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5897
98eb2f8b 5898 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5899 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5900 return handle_interrupt_window(&vmx->vcpu);
5901
de87dcdd
AK		 5902 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5903 return 1;
5904
991eebf9 5905 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5906
ac0a48c3 5907 if (err == EMULATE_USER_EXIT) {
94452b9e 5908 ++vcpu->stat.mmio_exits;
80ced186
MG		 5909 ret = 0;
5910 goto out;
5911 }
1d5a4d9b 5912
de5f70e0
AK		 5913 if (err != EMULATE_DONE) {
5914 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5915 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5916 vcpu->run->internal.ndata = 0;
6d77dbfc 5917 return 0;
de5f70e0 5918 }
ea953ef0 5919
8d76c49e
GN		 5920 if (vcpu->arch.halt_request) {
5921 vcpu->arch.halt_request = 0;
5cb56059 5922 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5923 goto out;
5924 }
5925
ea953ef0 5926 if (signal_pending(current))
80ced186 5927 goto out;
ea953ef0
MG		 5928 if (need_resched())
5929 schedule();
5930 }
5931
80ced186
MG		 5932out:
5933 return ret;
ea953ef0
MG		 5934}
5935
b4a2d31d
RK		 5936static int __grow_ple_window(int val)
5937{
5938 if (ple_window_grow < 1)
5939 return ple_window;
5940
5941 val = min(val, ple_window_actual_max);
5942
5943 if (ple_window_grow < ple_window)
5944 val *= ple_window_grow;
5945 else
5946 val += ple_window_grow;
5947
5948 return val;
5949}
5950
5951static int __shrink_ple_window(int val, int modifier, int minimum)
5952{
5953 if (modifier < 1)
5954 return ple_window;
5955
5956 if (modifier < ple_window)
5957 val /= modifier;
5958 else
5959 val -= modifier;
5960
5961 return max(val, minimum);
5962}
5963
5964static void grow_ple_window(struct kvm_vcpu *vcpu)
5965{
5966 struct vcpu_vmx *vmx = to_vmx(vcpu);
5967 int old = vmx->ple_window;
5968
5969 vmx->ple_window = __grow_ple_window(old);
5970
5971 if (vmx->ple_window != old)
5972 vmx->ple_window_dirty = true;
7b46268d
RK		 5973
5974 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5975}
5976
5977static void shrink_ple_window(struct kvm_vcpu *vcpu)
5978{
5979 struct vcpu_vmx *vmx = to_vmx(vcpu);
5980 int old = vmx->ple_window;
5981
5982 vmx->ple_window = __shrink_ple_window(old,
5983 ple_window_shrink, ple_window);
5984
5985 if (vmx->ple_window != old)
5986 vmx->ple_window_dirty = true;
7b46268d
RK		 5987
5988 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5989}
5990
5991/*
5992 * ple_window_actual_max is computed to be one grow_ple_window() below
5993 * ple_window_max. (See __grow_ple_window for the reason.)
5994 * This prevents overflows, because ple_window_max is int.
5995 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5996 * this process.
5997 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5998 */
5999static void update_ple_window_actual_max(void)
6000{
6001 ple_window_actual_max =
6002 __shrink_ple_window(max(ple_window_max, ple_window),
6003 ple_window_grow, INT_MIN);
6004}
6005
f2c7648d
TC		 6006static __init int hardware_setup(void)
6007{
34a1cd60
TC		 6008 int r = -ENOMEM, i, msr;
6009
6010 rdmsrl_safe(MSR_EFER, &host_efer);
6011
6012 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6013 kvm_define_shared_msr(i, vmx_msr_index[i]);
6014
6015 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6016 if (!vmx_io_bitmap_a)
6017 return r;
6018
6019 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6020 if (!vmx_io_bitmap_b)
6021 goto out;
6022
6023 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6024 if (!vmx_msr_bitmap_legacy)
6025 goto out1;
6026
6027 vmx_msr_bitmap_legacy_x2apic =
6028 (unsigned long *)__get_free_page(GFP_KERNEL);
6029 if (!vmx_msr_bitmap_legacy_x2apic)
6030 goto out2;
6031
6032 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6033 if (!vmx_msr_bitmap_longmode)
6034 goto out3;
6035
6036 vmx_msr_bitmap_longmode_x2apic =
6037 (unsigned long *)__get_free_page(GFP_KERNEL);
6038 if (!vmx_msr_bitmap_longmode_x2apic)
6039 goto out4;
3af18d9c
WV		 6040
6041 if (nested) {
6042 vmx_msr_bitmap_nested =
6043 (unsigned long *)__get_free_page(GFP_KERNEL);
6044 if (!vmx_msr_bitmap_nested)
6045 goto out5;
6046 }
6047
34a1cd60
TC		 6048 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6049 if (!vmx_vmread_bitmap)
3af18d9c 6050 goto out6;
34a1cd60
TC		 6051
6052 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6053 if (!vmx_vmwrite_bitmap)
3af18d9c 6054 goto out7;
34a1cd60
TC		 6055
6056 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6057 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6058
6059 /*
6060 * Allow direct access to the PC debug port (it is often used for I/O
6061 * delays, but the vmexits simply slow things down).
6062 */
6063 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6064 clear_bit(0x80, vmx_io_bitmap_a);
6065
6066 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6067
6068 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6069 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6070 if (nested)
6071 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6072
34a1cd60
TC		 6073 if (setup_vmcs_config(&vmcs_config) < 0) {
6074 r = -EIO;
3af18d9c 6075 goto out8;
baa03522 6076 }
f2c7648d
TC		 6077
6078 if (boot_cpu_has(X86_FEATURE_NX))
6079 kvm_enable_efer_bits(EFER_NX);
6080
6081 if (!cpu_has_vmx_vpid())
6082 enable_vpid = 0;
6083 if (!cpu_has_vmx_shadow_vmcs())
6084 enable_shadow_vmcs = 0;
6085 if (enable_shadow_vmcs)
6086 init_vmcs_shadow_fields();
6087
6088 if (!cpu_has_vmx_ept() ||
6089 !cpu_has_vmx_ept_4levels()) {
6090 enable_ept = 0;
6091 enable_unrestricted_guest = 0;
6092 enable_ept_ad_bits = 0;
6093 }
6094
6095 if (!cpu_has_vmx_ept_ad_bits())
6096 enable_ept_ad_bits = 0;
6097
6098 if (!cpu_has_vmx_unrestricted_guest())
6099 enable_unrestricted_guest = 0;
6100
ad15a296 6101 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6102 flexpriority_enabled = 0;
6103
ad15a296
PB		 6104 /*
6105 * set_apic_access_page_addr() is used to reload apic access
6106 * page upon invalidation. No need to do anything if not
6107 * using the APIC_ACCESS_ADDR VMCS field.
6108 */
6109 if (!flexpriority_enabled)
f2c7648d 6110 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6111
6112 if (!cpu_has_vmx_tpr_shadow())
6113 kvm_x86_ops->update_cr8_intercept = NULL;
6114
6115 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6116 kvm_disable_largepages();
6117
6118 if (!cpu_has_vmx_ple())
6119 ple_gap = 0;
6120
6121 if (!cpu_has_vmx_apicv())
6122 enable_apicv = 0;
6123
6124 if (enable_apicv)
6125 kvm_x86_ops->update_cr8_intercept = NULL;
6126 else {
6127 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6128 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6129 kvm_x86_ops->deliver_posted_interrupt = NULL;
6130 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6131 }
6132
baa03522
TC		 6133 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6134 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6135 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6136 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6137 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6138 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6139 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6140
6141 memcpy(vmx_msr_bitmap_legacy_x2apic,
6142 vmx_msr_bitmap_legacy, PAGE_SIZE);
6143 memcpy(vmx_msr_bitmap_longmode_x2apic,
6144 vmx_msr_bitmap_longmode, PAGE_SIZE);
6145
6146 if (enable_apicv) {
6147 for (msr = 0x800; msr <= 0x8ff; msr++)
6148 vmx_disable_intercept_msr_read_x2apic(msr);
6149
6150 /* According SDM, in x2apic mode, the whole id reg is used.
6151 * But in KVM, it only use the highest eight bits. Need to
6152 * intercept it */
6153 vmx_enable_intercept_msr_read_x2apic(0x802);
6154 /* TMCCT */
6155 vmx_enable_intercept_msr_read_x2apic(0x839);
6156 /* TPR */
6157 vmx_disable_intercept_msr_write_x2apic(0x808);
6158 /* EOI */
6159 vmx_disable_intercept_msr_write_x2apic(0x80b);
6160 /* SELF-IPI */
6161 vmx_disable_intercept_msr_write_x2apic(0x83f);
6162 }
6163
6164 if (enable_ept) {
6165 kvm_mmu_set_mask_ptes(0ull,
6166 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6167 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6168 0ull, VMX_EPT_EXECUTABLE_MASK);
6169 ept_set_mmio_spte_mask();
6170 kvm_enable_tdp();
6171 } else
6172 kvm_disable_tdp();
6173
6174 update_ple_window_actual_max();
6175
843e4330
KH		 6176 /*
6177 * Only enable PML when hardware supports PML feature, and both EPT
6178 * and EPT A/D bit features are enabled -- PML depends on them to work.
6179 */
6180 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6181 enable_pml = 0;
6182
6183 if (!enable_pml) {
6184 kvm_x86_ops->slot_enable_log_dirty = NULL;
6185 kvm_x86_ops->slot_disable_log_dirty = NULL;
6186 kvm_x86_ops->flush_log_dirty = NULL;
6187 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6188 }
6189
f2c7648d 6190 return alloc_kvm_area();
34a1cd60 6191
3af18d9c 6192out8:
34a1cd60 6193 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6194out7:
34a1cd60 6195 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6196out6:
6197 if (nested)
6198 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6199out5:
6200 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6201out4:
6202 free_page((unsigned long)vmx_msr_bitmap_longmode);
6203out3:
6204 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6205out2:
6206 free_page((unsigned long)vmx_msr_bitmap_legacy);
6207out1:
6208 free_page((unsigned long)vmx_io_bitmap_b);
6209out:
6210 free_page((unsigned long)vmx_io_bitmap_a);
6211
6212 return r;
f2c7648d
TC		 6213}
6214
6215static __exit void hardware_unsetup(void)
6216{
34a1cd60
TC		 6217 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6218 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6219 free_page((unsigned long)vmx_msr_bitmap_legacy);
6220 free_page((unsigned long)vmx_msr_bitmap_longmode);
6221 free_page((unsigned long)vmx_io_bitmap_b);
6222 free_page((unsigned long)vmx_io_bitmap_a);
6223 free_page((unsigned long)vmx_vmwrite_bitmap);
6224 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6225 if (nested)
6226 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6227
f2c7648d
TC		 6228 free_kvm_area();
6229}
6230
4b8d54f9
ZE		 6231/*
6232 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6233 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6234 */
9fb41ba8 6235static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6236{
b4a2d31d
RK		 6237 if (ple_gap)
6238 grow_ple_window(vcpu);
6239
4b8d54f9
ZE		 6240 skip_emulated_instruction(vcpu);
6241 kvm_vcpu_on_spin(vcpu);
6242
6243 return 1;
6244}
6245
87c00572 6246static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6247{
87c00572 6248 skip_emulated_instruction(vcpu);
59708670
SY		 6249 return 1;
6250}
6251
87c00572
GS		 6252static int handle_mwait(struct kvm_vcpu *vcpu)
6253{
6254 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6255 return handle_nop(vcpu);
6256}
6257
6258static int handle_monitor(struct kvm_vcpu *vcpu)
6259{
6260 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6261 return handle_nop(vcpu);
6262}
6263
ff2f6fe9
NHE		 6264/*
6265 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6266 * We could reuse a single VMCS for all the L2 guests, but we also want the
6267 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6268 * allows keeping them loaded on the processor, and in the future will allow
6269 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6270 * every entry if they never change.
6271 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6272 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6273 *
6274 * The following functions allocate and free a vmcs02 in this pool.
6275 */
6276
6277/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6278static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6279{
6280 struct vmcs02_list *item;
6281 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6282 if (item->vmptr == vmx->nested.current_vmptr) {
6283 list_move(&item->list, &vmx->nested.vmcs02_pool);
6284 return &item->vmcs02;
6285 }
6286
6287 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6288 /* Recycle the least recently used VMCS. */
6289 item = list_entry(vmx->nested.vmcs02_pool.prev,
6290 struct vmcs02_list, list);
6291 item->vmptr = vmx->nested.current_vmptr;
6292 list_move(&item->list, &vmx->nested.vmcs02_pool);
6293 return &item->vmcs02;
6294 }
6295
6296 /* Create a new VMCS */
0fa24ce3 6297 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6298 if (!item)
6299 return NULL;
6300 item->vmcs02.vmcs = alloc_vmcs();
6301 if (!item->vmcs02.vmcs) {
6302 kfree(item);
6303 return NULL;
6304 }
6305 loaded_vmcs_init(&item->vmcs02);
6306 item->vmptr = vmx->nested.current_vmptr;
6307 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6308 vmx->nested.vmcs02_num++;
6309 return &item->vmcs02;
6310}
6311
6312/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6313static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6314{
6315 struct vmcs02_list *item;
6316 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6317 if (item->vmptr == vmptr) {
6318 free_loaded_vmcs(&item->vmcs02);
6319 list_del(&item->list);
6320 kfree(item);
6321 vmx->nested.vmcs02_num--;
6322 return;
6323 }
6324}
6325
6326/*
6327 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6328 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6329 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6330 */
6331static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6332{
6333 struct vmcs02_list *item, *n;
4fa7734c
PB		 6334
6335 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6336 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6337 /*
6338 * Something will leak if the above WARN triggers. Better than
6339 * a use-after-free.
6340 */
6341 if (vmx->loaded_vmcs == &item->vmcs02)
6342 continue;
6343
6344 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6345 list_del(&item->list);
6346 kfree(item);
4fa7734c 6347 vmx->nested.vmcs02_num--;
ff2f6fe9 6348 }
ff2f6fe9
NHE		 6349}
6350
0658fbaa
ACL		 6351/*
6352 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6353 * set the success or error code of an emulated VMX instruction, as specified
6354 * by Vol 2B, VMX Instruction Reference, "Conventions".
6355 */
6356static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6357{
6358 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6359 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6360 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6361}
6362
6363static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6364{
6365 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6366 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6367 X86_EFLAGS_SF | X86_EFLAGS_OF))
6368 | X86_EFLAGS_CF);
6369}
6370
145c28dd 6371static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6372 u32 vm_instruction_error)
6373{
6374 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6375 /*
6376 * failValid writes the error number to the current VMCS, which
6377 * can't be done there isn't a current VMCS.
6378 */
6379 nested_vmx_failInvalid(vcpu);
6380 return;
6381 }
6382 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6383 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6384 X86_EFLAGS_SF | X86_EFLAGS_OF))
6385 | X86_EFLAGS_ZF);
6386 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6387 /*
6388 * We don't need to force a shadow sync because
6389 * VM_INSTRUCTION_ERROR is not shadowed
6390 */
6391}
145c28dd 6392
ff651cb6
WV		 6393static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6394{
6395 /* TODO: not to reset guest simply here. */
6396 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6397 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6398}
6399
f4124500
JK		 6400static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6401{
6402 struct vcpu_vmx *vmx =
6403 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6404
6405 vmx->nested.preemption_timer_expired = true;
6406 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6407 kvm_vcpu_kick(&vmx->vcpu);
6408
6409 return HRTIMER_NORESTART;
6410}
6411
19677e32
BD		 6412/*
6413 * Decode the memory-address operand of a vmx instruction, as recorded on an
6414 * exit caused by such an instruction (run by a guest hypervisor).
6415 * On success, returns 0. When the operand is invalid, returns 1 and throws
6416 * #UD or #GP.
6417 */
6418static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6419 unsigned long exit_qualification,
6420 u32 vmx_instruction_info, gva_t *ret)
6421{
6422 /*
6423 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6424 * Execution", on an exit, vmx_instruction_info holds most of the
6425 * addressing components of the operand. Only the displacement part
6426 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6427 * For how an actual address is calculated from all these components,
6428 * refer to Vol. 1, "Operand Addressing".
6429 */
6430 int scaling = vmx_instruction_info & 3;
6431 int addr_size = (vmx_instruction_info >> 7) & 7;
6432 bool is_reg = vmx_instruction_info & (1u << 10);
6433 int seg_reg = (vmx_instruction_info >> 15) & 7;
6434 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6435 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6436 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6437 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6438
6439 if (is_reg) {
6440 kvm_queue_exception(vcpu, UD_VECTOR);
6441 return 1;
6442 }
6443
6444 /* Addr = segment_base + offset */
6445 /* offset = base + [index * scale] + displacement */
6446 *ret = vmx_get_segment_base(vcpu, seg_reg);
6447 if (base_is_valid)
6448 *ret += kvm_register_read(vcpu, base_reg);
6449 if (index_is_valid)
6450 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6451 *ret += exit_qualification; /* holds the displacement */
6452
6453 if (addr_size == 1) /* 32 bit */
6454 *ret &= 0xffffffff;
6455
6456 /*
6457 * TODO: throw #GP (and return 1) in various cases that the VM*
6458 * instructions require it - e.g., offset beyond segment limit,
6459 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6460 * address, and so on. Currently these are not checked.
6461 */
6462 return 0;
6463}
6464
3573e22c
BD		 6465/*
6466 * This function performs the various checks including
6467 * - if it's 4KB aligned
6468 * - No bits beyond the physical address width are set
6469 * - Returns 0 on success or else 1
4291b588 6470 * (Intel SDM Section 30.3)
3573e22c 6471 */
4291b588
BD		 6472static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6473 gpa_t *vmpointer)
3573e22c
BD		 6474{
6475 gva_t gva;
6476 gpa_t vmptr;
6477 struct x86_exception e;
6478 struct page *page;
6479 struct vcpu_vmx *vmx = to_vmx(vcpu);
6480 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6481
6482 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6483 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6484 return 1;
6485
6486 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6487 sizeof(vmptr), &e)) {
6488 kvm_inject_page_fault(vcpu, &e);
6489 return 1;
6490 }
6491
6492 switch (exit_reason) {
6493 case EXIT_REASON_VMON:
6494 /*
6495 * SDM 3: 24.11.5
6496 * The first 4 bytes of VMXON region contain the supported
6497 * VMCS revision identifier
6498 *
6499 * Note - IA32_VMX_BASIC[48] will never be 1
6500 * for the nested case;
6501 * which replaces physical address width with 32
6502 *
6503 */
bc39c4db 6504 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6505 nested_vmx_failInvalid(vcpu);
6506 skip_emulated_instruction(vcpu);
6507 return 1;
6508 }
6509
6510 page = nested_get_page(vcpu, vmptr);
6511 if (page == NULL ||
6512 *(u32 *)kmap(page) != VMCS12_REVISION) {
6513 nested_vmx_failInvalid(vcpu);
6514 kunmap(page);
6515 skip_emulated_instruction(vcpu);
6516 return 1;
6517 }
6518 kunmap(page);
6519 vmx->nested.vmxon_ptr = vmptr;
6520 break;
4291b588 6521 case EXIT_REASON_VMCLEAR:
bc39c4db 6522 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6523 nested_vmx_failValid(vcpu,
6524 VMXERR_VMCLEAR_INVALID_ADDRESS);
6525 skip_emulated_instruction(vcpu);
6526 return 1;
6527 }
6528
6529 if (vmptr == vmx->nested.vmxon_ptr) {
6530 nested_vmx_failValid(vcpu,
6531 VMXERR_VMCLEAR_VMXON_POINTER);
6532 skip_emulated_instruction(vcpu);
6533 return 1;
6534 }
6535 break;
6536 case EXIT_REASON_VMPTRLD:
bc39c4db 6537 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6538 nested_vmx_failValid(vcpu,
6539 VMXERR_VMPTRLD_INVALID_ADDRESS);
6540 skip_emulated_instruction(vcpu);
6541 return 1;
6542 }
3573e22c 6543
4291b588
BD		 6544 if (vmptr == vmx->nested.vmxon_ptr) {
6545 nested_vmx_failValid(vcpu,
6546 VMXERR_VMCLEAR_VMXON_POINTER);
6547 skip_emulated_instruction(vcpu);
6548 return 1;
6549 }
6550 break;
3573e22c
BD		 6551 default:
6552 return 1; /* shouldn't happen */
6553 }
6554
4291b588
BD		 6555 if (vmpointer)
6556 *vmpointer = vmptr;
3573e22c
BD		 6557 return 0;
6558}
6559
ec378aee
NHE		 6560/*
6561 * Emulate the VMXON instruction.
6562 * Currently, we just remember that VMX is active, and do not save or even
6563 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6564 * do not currently need to store anything in that guest-allocated memory
6565 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6566 * argument is different from the VMXON pointer (which the spec says they do).
6567 */
6568static int handle_vmon(struct kvm_vcpu *vcpu)
6569{
6570 struct kvm_segment cs;
6571 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6572 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6573 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6574 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6575
6576 /* The Intel VMX Instruction Reference lists a bunch of bits that
6577 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6578 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6579 * Otherwise, we should fail with #UD. We test these now:
6580 */
6581 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6582 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6583 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6584 kvm_queue_exception(vcpu, UD_VECTOR);
6585 return 1;
6586 }
6587
6588 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6589 if (is_long_mode(vcpu) && !cs.l) {
6590 kvm_queue_exception(vcpu, UD_VECTOR);
6591 return 1;
6592 }
6593
6594 if (vmx_get_cpl(vcpu)) {
6595 kvm_inject_gp(vcpu, 0);
6596 return 1;
6597 }
3573e22c 6598
4291b588 6599 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6600 return 1;
6601
145c28dd
AG		 6602 if (vmx->nested.vmxon) {
6603 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6604 skip_emulated_instruction(vcpu);
6605 return 1;
6606 }
b3897a49
NHE		 6607
6608 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6609 != VMXON_NEEDED_FEATURES) {
6610 kvm_inject_gp(vcpu, 0);
6611 return 1;
6612 }
6613
8de48833
AG		 6614 if (enable_shadow_vmcs) {
6615 shadow_vmcs = alloc_vmcs();
6616 if (!shadow_vmcs)
6617 return -ENOMEM;
6618 /* mark vmcs as shadow */
6619 shadow_vmcs->revision_id |= (1u << 31);
6620 /* init shadow vmcs */
6621 vmcs_clear(shadow_vmcs);
6622 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6623 }
ec378aee 6624
ff2f6fe9
NHE		 6625 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6626 vmx->nested.vmcs02_num = 0;
6627
f4124500
JK		 6628 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6629 HRTIMER_MODE_REL);
6630 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6631
ec378aee
NHE		 6632 vmx->nested.vmxon = true;
6633
6634 skip_emulated_instruction(vcpu);
a25eb114 6635 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6636 return 1;
6637}
6638
6639/*
6640 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6641 * for running VMX instructions (except VMXON, whose prerequisites are
6642 * slightly different). It also specifies what exception to inject otherwise.
6643 */
6644static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6645{
6646 struct kvm_segment cs;
6647 struct vcpu_vmx *vmx = to_vmx(vcpu);
6648
6649 if (!vmx->nested.vmxon) {
6650 kvm_queue_exception(vcpu, UD_VECTOR);
6651 return 0;
6652 }
6653
6654 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6655 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6656 (is_long_mode(vcpu) && !cs.l)) {
6657 kvm_queue_exception(vcpu, UD_VECTOR);
6658 return 0;
6659 }
6660
6661 if (vmx_get_cpl(vcpu)) {
6662 kvm_inject_gp(vcpu, 0);
6663 return 0;
6664 }
6665
6666 return 1;
6667}
6668
e7953d7f
AG		 6669static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6670{
8a1b9dd0 6671 u32 exec_control;
9a2a05b9
PB		 6672 if (vmx->nested.current_vmptr == -1ull)
6673 return;
6674
6675 /* current_vmptr and current_vmcs12 are always set/reset together */
6676 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6677 return;
6678
012f83cb 6679 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6680 /* copy to memory all shadowed fields in case
6681 they were modified */
6682 copy_shadow_to_vmcs12(vmx);
6683 vmx->nested.sync_shadow_vmcs = false;
6684 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6685 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6686 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6687 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6688 }
705699a1 6689 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6690 kunmap(vmx->nested.current_vmcs12_page);
6691 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6692 vmx->nested.current_vmptr = -1ull;
6693 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6694}
6695
ec378aee
NHE		 6696/*
6697 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6698 * just stops using VMX.
6699 */
6700static void free_nested(struct vcpu_vmx *vmx)
6701{
6702 if (!vmx->nested.vmxon)
6703 return;
9a2a05b9 6704
ec378aee 6705 vmx->nested.vmxon = false;
9a2a05b9 6706 nested_release_vmcs12(vmx);
e7953d7f
AG		 6707 if (enable_shadow_vmcs)
6708 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6709 /* Unpin physical memory we referred to in current vmcs02 */
6710 if (vmx->nested.apic_access_page) {
6711 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6712 vmx->nested.apic_access_page = NULL;
fe3ef05c 6713 }
a7c0b07d
WL		 6714 if (vmx->nested.virtual_apic_page) {
6715 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6716 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6717 }
705699a1
WV		 6718 if (vmx->nested.pi_desc_page) {
6719 kunmap(vmx->nested.pi_desc_page);
6720 nested_release_page(vmx->nested.pi_desc_page);
6721 vmx->nested.pi_desc_page = NULL;
6722 vmx->nested.pi_desc = NULL;
6723 }
ff2f6fe9
NHE		 6724
6725 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6726}
6727
6728/* Emulate the VMXOFF instruction */
6729static int handle_vmoff(struct kvm_vcpu *vcpu)
6730{
6731 if (!nested_vmx_check_permission(vcpu))
6732 return 1;
6733 free_nested(to_vmx(vcpu));
6734 skip_emulated_instruction(vcpu);
a25eb114 6735 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6736 return 1;
6737}
6738
27d6c865
NHE		 6739/* Emulate the VMCLEAR instruction */
6740static int handle_vmclear(struct kvm_vcpu *vcpu)
6741{
6742 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6743 gpa_t vmptr;
6744 struct vmcs12 *vmcs12;
6745 struct page *page;
27d6c865
NHE		 6746
6747 if (!nested_vmx_check_permission(vcpu))
6748 return 1;
6749
4291b588 6750 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6751 return 1;
27d6c865 6752
9a2a05b9 6753 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6754 nested_release_vmcs12(vmx);
27d6c865
NHE		 6755
6756 page = nested_get_page(vcpu, vmptr);
6757 if (page == NULL) {
6758 /*
6759 * For accurate processor emulation, VMCLEAR beyond available
6760 * physical memory should do nothing at all. However, it is
6761 * possible that a nested vmx bug, not a guest hypervisor bug,
6762 * resulted in this case, so let's shut down before doing any
6763 * more damage:
6764 */
6765 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6766 return 1;
6767 }
6768 vmcs12 = kmap(page);
6769 vmcs12->launch_state = 0;
6770 kunmap(page);
6771 nested_release_page(page);
6772
6773 nested_free_vmcs02(vmx, vmptr);
6774
6775 skip_emulated_instruction(vcpu);
6776 nested_vmx_succeed(vcpu);
6777 return 1;
6778}
6779
cd232ad0
NHE		 6780static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6781
6782/* Emulate the VMLAUNCH instruction */
6783static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6784{
6785 return nested_vmx_run(vcpu, true);
6786}
6787
6788/* Emulate the VMRESUME instruction */
6789static int handle_vmresume(struct kvm_vcpu *vcpu)
6790{
6791
6792 return nested_vmx_run(vcpu, false);
6793}
6794
49f705c5
NHE		 6795enum vmcs_field_type {
6796 VMCS_FIELD_TYPE_U16 = 0,
6797 VMCS_FIELD_TYPE_U64 = 1,
6798 VMCS_FIELD_TYPE_U32 = 2,
6799 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6800};
6801
6802static inline int vmcs_field_type(unsigned long field)
6803{
6804 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6805 return VMCS_FIELD_TYPE_U32;
6806 return (field >> 13) & 0x3 ;
6807}
6808
6809static inline int vmcs_field_readonly(unsigned long field)
6810{
6811 return (((field >> 10) & 0x3) == 1);
6812}
6813
6814/*
6815 * Read a vmcs12 field. Since these can have varying lengths and we return
6816 * one type, we chose the biggest type (u64) and zero-extend the return value
6817 * to that size. Note that the caller, handle_vmread, might need to use only
6818 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6819 * 64-bit fields are to be returned).
6820 */
a2ae9df7
PB		 6821static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6822 unsigned long field, u64 *ret)
49f705c5
NHE		 6823{
6824 short offset = vmcs_field_to_offset(field);
6825 char *p;
6826
6827 if (offset < 0)
a2ae9df7 6828 return offset;
49f705c5
NHE		 6829
6830 p = ((char *)(get_vmcs12(vcpu))) + offset;
6831
6832 switch (vmcs_field_type(field)) {
6833 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6834 *ret = *((natural_width *)p);
a2ae9df7 6835 return 0;
49f705c5
NHE		 6836 case VMCS_FIELD_TYPE_U16:
6837 *ret = *((u16 *)p);
a2ae9df7 6838 return 0;
49f705c5
NHE		 6839 case VMCS_FIELD_TYPE_U32:
6840 *ret = *((u32 *)p);
a2ae9df7 6841 return 0;
49f705c5
NHE		 6842 case VMCS_FIELD_TYPE_U64:
6843 *ret = *((u64 *)p);
a2ae9df7 6844 return 0;
49f705c5 6845 default:
a2ae9df7
PB		 6846 WARN_ON(1);
6847 return -ENOENT;
49f705c5
NHE		 6848 }
6849}
6850
20b97fea 6851
a2ae9df7
PB		 6852static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6853 unsigned long field, u64 field_value){
20b97fea
AG		 6854 short offset = vmcs_field_to_offset(field);
6855 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6856 if (offset < 0)
a2ae9df7 6857 return offset;
20b97fea
AG		 6858
6859 switch (vmcs_field_type(field)) {
6860 case VMCS_FIELD_TYPE_U16:
6861 *(u16 *)p = field_value;
a2ae9df7 6862 return 0;
20b97fea
AG		 6863 case VMCS_FIELD_TYPE_U32:
6864 *(u32 *)p = field_value;
a2ae9df7 6865 return 0;
20b97fea
AG		 6866 case VMCS_FIELD_TYPE_U64:
6867 *(u64 *)p = field_value;
a2ae9df7 6868 return 0;
20b97fea
AG		 6869 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6870 *(natural_width *)p = field_value;
a2ae9df7 6871 return 0;
20b97fea 6872 default:
a2ae9df7
PB		 6873 WARN_ON(1);
6874 return -ENOENT;
20b97fea
AG		 6875 }
6876
6877}
6878
16f5b903
AG		 6879static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6880{
6881 int i;
6882 unsigned long field;
6883 u64 field_value;
6884 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6885 const unsigned long *fields = shadow_read_write_fields;
6886 const int num_fields = max_shadow_read_write_fields;
16f5b903 6887
282da870
JK		 6888 preempt_disable();
6889
16f5b903
AG		 6890 vmcs_load(shadow_vmcs);
6891
6892 for (i = 0; i < num_fields; i++) {
6893 field = fields[i];
6894 switch (vmcs_field_type(field)) {
6895 case VMCS_FIELD_TYPE_U16:
6896 field_value = vmcs_read16(field);
6897 break;
6898 case VMCS_FIELD_TYPE_U32:
6899 field_value = vmcs_read32(field);
6900 break;
6901 case VMCS_FIELD_TYPE_U64:
6902 field_value = vmcs_read64(field);
6903 break;
6904 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6905 field_value = vmcs_readl(field);
6906 break;
a2ae9df7
PB		 6907 default:
6908 WARN_ON(1);
6909 continue;
16f5b903
AG		 6910 }
6911 vmcs12_write_any(&vmx->vcpu, field, field_value);
6912 }
6913
6914 vmcs_clear(shadow_vmcs);
6915 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6916
6917 preempt_enable();
16f5b903
AG		 6918}
6919
c3114420
AG		 6920static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6921{
c2bae893
MK		 6922 const unsigned long *fields[] = {
6923 shadow_read_write_fields,
6924 shadow_read_only_fields
c3114420 6925 };
c2bae893 6926 const int max_fields[] = {
c3114420
AG		 6927 max_shadow_read_write_fields,
6928 max_shadow_read_only_fields
6929 };
6930 int i, q;
6931 unsigned long field;
6932 u64 field_value = 0;
6933 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6934
6935 vmcs_load(shadow_vmcs);
6936
c2bae893 6937 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6938 for (i = 0; i < max_fields[q]; i++) {
6939 field = fields[q][i];
6940 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6941
6942 switch (vmcs_field_type(field)) {
6943 case VMCS_FIELD_TYPE_U16:
6944 vmcs_write16(field, (u16)field_value);
6945 break;
6946 case VMCS_FIELD_TYPE_U32:
6947 vmcs_write32(field, (u32)field_value);
6948 break;
6949 case VMCS_FIELD_TYPE_U64:
6950 vmcs_write64(field, (u64)field_value);
6951 break;
6952 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6953 vmcs_writel(field, (long)field_value);
6954 break;
a2ae9df7
PB		 6955 default:
6956 WARN_ON(1);
6957 break;
c3114420
AG		 6958 }
6959 }
6960 }
6961
6962 vmcs_clear(shadow_vmcs);
6963 vmcs_load(vmx->loaded_vmcs->vmcs);
6964}
6965
49f705c5
NHE		 6966/*
6967 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6968 * used before) all generate the same failure when it is missing.
6969 */
6970static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6971{
6972 struct vcpu_vmx *vmx = to_vmx(vcpu);
6973 if (vmx->nested.current_vmptr == -1ull) {
6974 nested_vmx_failInvalid(vcpu);
6975 skip_emulated_instruction(vcpu);
6976 return 0;
6977 }
6978 return 1;
6979}
6980
6981static int handle_vmread(struct kvm_vcpu *vcpu)
6982{
6983 unsigned long field;
6984 u64 field_value;
6985 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6986 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6987 gva_t gva = 0;
6988
6989 if (!nested_vmx_check_permission(vcpu) ||
6990 !nested_vmx_check_vmcs12(vcpu))
6991 return 1;
6992
6993 /* Decode instruction info and find the field to read */
27e6fb5d 6994 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6995 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6996 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6997 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6998 skip_emulated_instruction(vcpu);
6999 return 1;
7000 }
7001 /*
7002 * Now copy part of this value to register or memory, as requested.
7003 * Note that the number of bits actually copied is 32 or 64 depending
7004 * on the guest's mode (32 or 64 bit), not on the given field's length.
7005 */
7006 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7007 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7008 field_value);
7009 } else {
7010 if (get_vmx_mem_address(vcpu, exit_qualification,
7011 vmx_instruction_info, &gva))
7012 return 1;
7013 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7014 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7015 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7016 }
7017
7018 nested_vmx_succeed(vcpu);
7019 skip_emulated_instruction(vcpu);
7020 return 1;
7021}
7022
7023
7024static int handle_vmwrite(struct kvm_vcpu *vcpu)
7025{
7026 unsigned long field;
7027 gva_t gva;
7028 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7029 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7030 /* The value to write might be 32 or 64 bits, depending on L1's long
7031 * mode, and eventually we need to write that into a field of several
7032 * possible lengths. The code below first zero-extends the value to 64
7033 * bit (field_value), and then copies only the approriate number of
7034 * bits into the vmcs12 field.
7035 */
7036 u64 field_value = 0;
7037 struct x86_exception e;
7038
7039 if (!nested_vmx_check_permission(vcpu) ||
7040 !nested_vmx_check_vmcs12(vcpu))
7041 return 1;
7042
7043 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7044 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7045 (((vmx_instruction_info) >> 3) & 0xf));
7046 else {
7047 if (get_vmx_mem_address(vcpu, exit_qualification,
7048 vmx_instruction_info, &gva))
7049 return 1;
7050 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7051 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7052 kvm_inject_page_fault(vcpu, &e);
7053 return 1;
7054 }
7055 }
7056
7057
27e6fb5d 7058 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7059 if (vmcs_field_readonly(field)) {
7060 nested_vmx_failValid(vcpu,
7061 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7062 skip_emulated_instruction(vcpu);
7063 return 1;
7064 }
7065
a2ae9df7 7066 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7067 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7068 skip_emulated_instruction(vcpu);
7069 return 1;
7070 }
7071
7072 nested_vmx_succeed(vcpu);
7073 skip_emulated_instruction(vcpu);
7074 return 1;
7075}
7076
63846663
NHE		 7077/* Emulate the VMPTRLD instruction */
7078static int handle_vmptrld(struct kvm_vcpu *vcpu)
7079{
7080 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7081 gpa_t vmptr;
8a1b9dd0 7082 u32 exec_control;
63846663
NHE		 7083
7084 if (!nested_vmx_check_permission(vcpu))
7085 return 1;
7086
4291b588 7087 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7088 return 1;
63846663
NHE		 7089
7090 if (vmx->nested.current_vmptr != vmptr) {
7091 struct vmcs12 *new_vmcs12;
7092 struct page *page;
7093 page = nested_get_page(vcpu, vmptr);
7094 if (page == NULL) {
7095 nested_vmx_failInvalid(vcpu);
7096 skip_emulated_instruction(vcpu);
7097 return 1;
7098 }
7099 new_vmcs12 = kmap(page);
7100 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7101 kunmap(page);
7102 nested_release_page_clean(page);
7103 nested_vmx_failValid(vcpu,
7104 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7105 skip_emulated_instruction(vcpu);
7106 return 1;
7107 }
63846663 7108
9a2a05b9 7109 nested_release_vmcs12(vmx);
63846663
NHE		 7110 vmx->nested.current_vmptr = vmptr;
7111 vmx->nested.current_vmcs12 = new_vmcs12;
7112 vmx->nested.current_vmcs12_page = page;
012f83cb 7113 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7114 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7115 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7116 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7117 vmcs_write64(VMCS_LINK_POINTER,
7118 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7119 vmx->nested.sync_shadow_vmcs = true;
7120 }
63846663
NHE		 7121 }
7122
7123 nested_vmx_succeed(vcpu);
7124 skip_emulated_instruction(vcpu);
7125 return 1;
7126}
7127
6a4d7550
NHE		 7128/* Emulate the VMPTRST instruction */
7129static int handle_vmptrst(struct kvm_vcpu *vcpu)
7130{
7131 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7132 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7133 gva_t vmcs_gva;
7134 struct x86_exception e;
7135
7136 if (!nested_vmx_check_permission(vcpu))
7137 return 1;
7138
7139 if (get_vmx_mem_address(vcpu, exit_qualification,
7140 vmx_instruction_info, &vmcs_gva))
7141 return 1;
7142 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7143 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7144 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7145 sizeof(u64), &e)) {
7146 kvm_inject_page_fault(vcpu, &e);
7147 return 1;
7148 }
7149 nested_vmx_succeed(vcpu);
7150 skip_emulated_instruction(vcpu);
7151 return 1;
7152}
7153
bfd0a56b
NHE		 7154/* Emulate the INVEPT instruction */
7155static int handle_invept(struct kvm_vcpu *vcpu)
7156{
b9c237bb 7157 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7158 u32 vmx_instruction_info, types;
7159 unsigned long type;
7160 gva_t gva;
7161 struct x86_exception e;
7162 struct {
7163 u64 eptp, gpa;
7164 } operand;
bfd0a56b 7165
b9c237bb
WV		 7166 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7167 SECONDARY_EXEC_ENABLE_EPT) ||
7168 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7169 kvm_queue_exception(vcpu, UD_VECTOR);
7170 return 1;
7171 }
7172
7173 if (!nested_vmx_check_permission(vcpu))
7174 return 1;
7175
7176 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7177 kvm_queue_exception(vcpu, UD_VECTOR);
7178 return 1;
7179 }
7180
7181 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7182 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7183
b9c237bb 7184 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7185
7186 if (!(types & (1UL << type))) {
7187 nested_vmx_failValid(vcpu,
7188 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7189 return 1;
7190 }
7191
7192 /* According to the Intel VMX instruction reference, the memory
7193 * operand is read even if it isn't needed (e.g., for type==global)
7194 */
7195 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7196 vmx_instruction_info, &gva))
7197 return 1;
7198 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7199 sizeof(operand), &e)) {
7200 kvm_inject_page_fault(vcpu, &e);
7201 return 1;
7202 }
7203
7204 switch (type) {
bfd0a56b
NHE		 7205 case VMX_EPT_EXTENT_GLOBAL:
7206 kvm_mmu_sync_roots(vcpu);
77c3913b 7207 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7208 nested_vmx_succeed(vcpu);
7209 break;
7210 default:
4b855078 7211 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7212 BUG_ON(1);
7213 break;
7214 }
7215
7216 skip_emulated_instruction(vcpu);
7217 return 1;
7218}
7219
a642fc30
PM		 7220static int handle_invvpid(struct kvm_vcpu *vcpu)
7221{
7222 kvm_queue_exception(vcpu, UD_VECTOR);
7223 return 1;
7224}
7225
843e4330
KH		 7226static int handle_pml_full(struct kvm_vcpu *vcpu)
7227{
7228 unsigned long exit_qualification;
7229
7230 trace_kvm_pml_full(vcpu->vcpu_id);
7231
7232 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7233
7234 /*
7235 * PML buffer FULL happened while executing iret from NMI,
7236 * "blocked by NMI" bit has to be set before next VM entry.
7237 */
7238 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7239 cpu_has_virtual_nmis() &&
7240 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7241 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7242 GUEST_INTR_STATE_NMI);
7243
7244 /*
7245 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7246 * here.., and there's no userspace involvement needed for PML.
7247 */
7248 return 1;
7249}
7250
6aa8b732
AK		 7251/*
7252 * The exit handlers return 1 if the exit was handled fully and guest execution
7253 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7254 * to be done to userspace and return 0.
7255 */
772e0318 7256static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7257 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7258 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7259 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7260 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7261 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7262 [EXIT_REASON_CR_ACCESS] = handle_cr,
7263 [EXIT_REASON_DR_ACCESS] = handle_dr,
7264 [EXIT_REASON_CPUID] = handle_cpuid,
7265 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7266 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7267 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7268 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7269 [EXIT_REASON_INVD] = handle_invd,
a7052897 7270 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7271 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7272 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7273 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7274 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7275 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7276 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7277 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7278 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7279 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7280 [EXIT_REASON_VMOFF] = handle_vmoff,
7281 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7282 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7283 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7284 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7285 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7286 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7287 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7288 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7289 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7290 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7291 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7292 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7293 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7294 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7295 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7296 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7297 [EXIT_REASON_XSAVES] = handle_xsaves,
7298 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7299 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7300};
7301
7302static const int kvm_vmx_max_exit_handlers =
50a3485c 7303 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7304
908a7bdd
JK		 7305static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7306 struct vmcs12 *vmcs12)
7307{
7308 unsigned long exit_qualification;
7309 gpa_t bitmap, last_bitmap;
7310 unsigned int port;
7311 int size;
7312 u8 b;
7313
908a7bdd 7314 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7315 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7316
7317 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7318
7319 port = exit_qualification >> 16;
7320 size = (exit_qualification & 7) + 1;
7321
7322 last_bitmap = (gpa_t)-1;
7323 b = -1;
7324
7325 while (size > 0) {
7326 if (port < 0x8000)
7327 bitmap = vmcs12->io_bitmap_a;
7328 else if (port < 0x10000)
7329 bitmap = vmcs12->io_bitmap_b;
7330 else
1d804d07 7331 return true;
908a7bdd
JK		 7332 bitmap += (port & 0x7fff) / 8;
7333
7334 if (last_bitmap != bitmap)
7335 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
1d804d07 7336 return true;
908a7bdd 7337 if (b & (1 << (port & 7)))
1d804d07 7338 return true;
908a7bdd
JK		 7339
7340 port++;
7341 size--;
7342 last_bitmap = bitmap;
7343 }
7344
1d804d07 7345 return false;
908a7bdd
JK		 7346}
7347
644d711a
NHE		 7348/*
7349 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7350 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7351 * disinterest in the current event (read or write a specific MSR) by using an
7352 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7353 */
7354static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7355 struct vmcs12 *vmcs12, u32 exit_reason)
7356{
7357 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7358 gpa_t bitmap;
7359
cbd29cb6 7360 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7361 return true;
644d711a
NHE		 7362
7363 /*
7364 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7365 * for the four combinations of read/write and low/high MSR numbers.
7366 * First we need to figure out which of the four to use:
7367 */
7368 bitmap = vmcs12->msr_bitmap;
7369 if (exit_reason == EXIT_REASON_MSR_WRITE)
7370 bitmap += 2048;
7371 if (msr_index >= 0xc0000000) {
7372 msr_index -= 0xc0000000;
7373 bitmap += 1024;
7374 }
7375
7376 /* Then read the msr_index'th bit from this bitmap: */
7377 if (msr_index < 1024*8) {
7378 unsigned char b;
bd31a7f5 7379 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
1d804d07 7380 return true;
644d711a
NHE		 7381 return 1 & (b >> (msr_index & 7));
7382 } else
1d804d07 7383 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7384}
7385
7386/*
7387 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7388 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7389 * intercept (via guest_host_mask etc.) the current event.
7390 */
7391static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7392 struct vmcs12 *vmcs12)
7393{
7394 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7395 int cr = exit_qualification & 15;
7396 int reg = (exit_qualification >> 8) & 15;
1e32c079 7397 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7398
7399 switch ((exit_qualification >> 4) & 3) {
7400 case 0: /* mov to cr */
7401 switch (cr) {
7402 case 0:
7403 if (vmcs12->cr0_guest_host_mask &
7404 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7405 return true;
644d711a
NHE		 7406 break;
7407 case 3:
7408 if ((vmcs12->cr3_target_count >= 1 &&
7409 vmcs12->cr3_target_value0 == val) ||
7410 (vmcs12->cr3_target_count >= 2 &&
7411 vmcs12->cr3_target_value1 == val) ||
7412 (vmcs12->cr3_target_count >= 3 &&
7413 vmcs12->cr3_target_value2 == val) ||
7414 (vmcs12->cr3_target_count >= 4 &&
7415 vmcs12->cr3_target_value3 == val))
1d804d07 7416 return false;
644d711a 7417 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7418 return true;
644d711a
NHE		 7419 break;
7420 case 4:
7421 if (vmcs12->cr4_guest_host_mask &
7422 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7423 return true;
644d711a
NHE		 7424 break;
7425 case 8:
7426 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7427 return true;
644d711a
NHE		 7428 break;
7429 }
7430 break;
7431 case 2: /* clts */
7432 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7433 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7434 return true;
644d711a
NHE		 7435 break;
7436 case 1: /* mov from cr */
7437 switch (cr) {
7438 case 3:
7439 if (vmcs12->cpu_based_vm_exec_control &
7440 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7441 return true;
644d711a
NHE		 7442 break;
7443 case 8:
7444 if (vmcs12->cpu_based_vm_exec_control &
7445 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7446 return true;
644d711a
NHE		 7447 break;
7448 }
7449 break;
7450 case 3: /* lmsw */
7451 /*
7452 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7453 * cr0. Other attempted changes are ignored, with no exit.
7454 */
7455 if (vmcs12->cr0_guest_host_mask & 0xe &
7456 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7457 return true;
644d711a
NHE		 7458 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7459 !(vmcs12->cr0_read_shadow & 0x1) &&
7460 (val & 0x1))
1d804d07 7461 return true;
644d711a
NHE		 7462 break;
7463 }
1d804d07 7464 return false;
644d711a
NHE		 7465}
7466
7467/*
7468 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7469 * should handle it ourselves in L0 (and then continue L2). Only call this
7470 * when in is_guest_mode (L2).
7471 */
7472static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7473{
644d711a
NHE		 7474 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7475 struct vcpu_vmx *vmx = to_vmx(vcpu);
7476 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7477 u32 exit_reason = vmx->exit_reason;
644d711a 7478
542060ea
JK		 7479 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7480 vmcs_readl(EXIT_QUALIFICATION),
7481 vmx->idt_vectoring_info,
7482 intr_info,
7483 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7484 KVM_ISA_VMX);
7485
644d711a 7486 if (vmx->nested.nested_run_pending)
1d804d07 7487 return false;
644d711a
NHE		 7488
7489 if (unlikely(vmx->fail)) {
bd80158a
JK		 7490 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7491 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7492 return true;
644d711a
NHE		 7493 }
7494
7495 switch (exit_reason) {
7496 case EXIT_REASON_EXCEPTION_NMI:
7497 if (!is_exception(intr_info))
1d804d07 7498 return false;
644d711a
NHE		 7499 else if (is_page_fault(intr_info))
7500 return enable_ept;
e504c909 7501 else if (is_no_device(intr_info) &&
ccf9844e 7502 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7503 return false;
644d711a
NHE		 7504 return vmcs12->exception_bitmap &
7505 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7506 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7507 return false;
644d711a 7508 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7509 return true;
644d711a 7510 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7511 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7512 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7513 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7514 case EXIT_REASON_TASK_SWITCH:
1d804d07 7515 return true;
644d711a 7516 case EXIT_REASON_CPUID:
bc613494 7517 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7518 return false;
7519 return true;
644d711a
NHE		 7520 case EXIT_REASON_HLT:
7521 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7522 case EXIT_REASON_INVD:
1d804d07 7523 return true;
644d711a
NHE		 7524 case EXIT_REASON_INVLPG:
7525 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7526 case EXIT_REASON_RDPMC:
7527 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7528 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7529 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7530 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7531 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7532 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7533 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7534 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7535 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7536 /*
7537 * VMX instructions trap unconditionally. This allows L1 to
7538 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7539 */
1d804d07 7540 return true;
644d711a
NHE		 7541 case EXIT_REASON_CR_ACCESS:
7542 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7543 case EXIT_REASON_DR_ACCESS:
7544 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7545 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7546 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7547 case EXIT_REASON_MSR_READ:
7548 case EXIT_REASON_MSR_WRITE:
7549 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7550 case EXIT_REASON_INVALID_STATE:
1d804d07 7551 return true;
644d711a
NHE		 7552 case EXIT_REASON_MWAIT_INSTRUCTION:
7553 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7554 case EXIT_REASON_MONITOR_INSTRUCTION:
7555 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7556 case EXIT_REASON_PAUSE_INSTRUCTION:
7557 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7558 nested_cpu_has2(vmcs12,
7559 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7560 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7561 return false;
644d711a 7562 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7563 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7564 case EXIT_REASON_APIC_ACCESS:
7565 return nested_cpu_has2(vmcs12,
7566 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7567 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7568 case EXIT_REASON_EOI_INDUCED:
7569 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7570 return true;
644d711a 7571 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7572 /*
7573 * L0 always deals with the EPT violation. If nested EPT is
7574 * used, and the nested mmu code discovers that the address is
7575 * missing in the guest EPT table (EPT12), the EPT violation
7576 * will be injected with nested_ept_inject_page_fault()
7577 */
1d804d07 7578 return false;
644d711a 7579 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7580 /*
7581 * L2 never uses directly L1's EPT, but rather L0's own EPT
7582 * table (shadow on EPT) or a merged EPT table that L0 built
7583 * (EPT on EPT). So any problems with the structure of the
7584 * table is L0's fault.
7585 */
1d804d07 7586 return false;
644d711a
NHE		 7587 case EXIT_REASON_WBINVD:
7588 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7589 case EXIT_REASON_XSETBV:
1d804d07 7590 return true;
81dc01f7
WL		 7591 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7592 /*
7593 * This should never happen, since it is not possible to
7594 * set XSS to a non-zero value---neither in L1 nor in L2.
7595 * If if it were, XSS would have to be checked against
7596 * the XSS exit bitmap in vmcs12.
7597 */
7598 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a 7599 default:
1d804d07 7600 return true;
644d711a
NHE		 7601 }
7602}
7603
586f9607
AK		 7604static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7605{
7606 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7607 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7608}
7609
843e4330
KH		 7610static int vmx_enable_pml(struct vcpu_vmx *vmx)
7611{
7612 struct page *pml_pg;
7613 u32 exec_control;
7614
7615 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7616 if (!pml_pg)
7617 return -ENOMEM;
7618
7619 vmx->pml_pg = pml_pg;
7620
7621 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7622 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7623
7624 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7625 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7626 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7627
7628 return 0;
7629}
7630
7631static void vmx_disable_pml(struct vcpu_vmx *vmx)
7632{
7633 u32 exec_control;
7634
7635 ASSERT(vmx->pml_pg);
7636 __free_page(vmx->pml_pg);
7637 vmx->pml_pg = NULL;
7638
7639 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7640 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7641 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7642}
7643
7644static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7645{
7646 struct kvm *kvm = vmx->vcpu.kvm;
7647 u64 *pml_buf;
7648 u16 pml_idx;
7649
7650 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7651
7652 /* Do nothing if PML buffer is empty */
7653 if (pml_idx == (PML_ENTITY_NUM - 1))
7654 return;
7655
7656 /* PML index always points to next available PML buffer entity */
7657 if (pml_idx >= PML_ENTITY_NUM)
7658 pml_idx = 0;
7659 else
7660 pml_idx++;
7661
7662 pml_buf = page_address(vmx->pml_pg);
7663 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7664 u64 gpa;
7665
7666 gpa = pml_buf[pml_idx];
7667 WARN_ON(gpa & (PAGE_SIZE - 1));
7668 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7669 }
7670
7671 /* reset PML index */
7672 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7673}
7674
7675/*
7676 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7677 * Called before reporting dirty_bitmap to userspace.
7678 */
7679static void kvm_flush_pml_buffers(struct kvm *kvm)
7680{
7681 int i;
7682 struct kvm_vcpu *vcpu;
7683 /*
7684 * We only need to kick vcpu out of guest mode here, as PML buffer
7685 * is flushed at beginning of all VMEXITs, and it's obvious that only
7686 * vcpus running in guest are possible to have unflushed GPAs in PML
7687 * buffer.
7688 */
7689 kvm_for_each_vcpu(i, vcpu, kvm)
7690 kvm_vcpu_kick(vcpu);
7691}
7692
6aa8b732
AK		 7693/*
7694 * The guest has exited. See if we can fix it or if we need userspace
7695 * assistance.
7696 */
851ba692 7697static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7698{
29bd8a78 7699 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7700 u32 exit_reason = vmx->exit_reason;
1155f76a 7701 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7702
843e4330
KH		 7703 /*
7704 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7705 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7706 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7707 * mode as if vcpus is in root mode, the PML buffer must has been
7708 * flushed already.
7709 */
7710 if (enable_pml)
7711 vmx_flush_pml_buffer(vmx);
7712
80ced186 7713 /* If guest state is invalid, start emulating */
14168786 7714 if (vmx->emulation_required)
80ced186 7715 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7716
644d711a 7717 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7718 nested_vmx_vmexit(vcpu, exit_reason,
7719 vmcs_read32(VM_EXIT_INTR_INFO),
7720 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7721 return 1;
7722 }
7723
5120702e
MG		 7724 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7725 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7726 vcpu->run->fail_entry.hardware_entry_failure_reason
7727 = exit_reason;
7728 return 0;
7729 }
7730
29bd8a78 7731 if (unlikely(vmx->fail)) {
851ba692
AK		 7732 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7733 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7734 = vmcs_read32(VM_INSTRUCTION_ERROR);
7735 return 0;
7736 }
6aa8b732 7737
b9bf6882
XG		 7738 /*
7739 * Note:
7740 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7741 * delivery event since it indicates guest is accessing MMIO.
7742 * The vm-exit can be triggered again after return to guest that
7743 * will cause infinite loop.
7744 */
d77c26fc 7745 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7746 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7747 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7748 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7749 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7750 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7751 vcpu->run->internal.ndata = 2;
7752 vcpu->run->internal.data[0] = vectoring_info;
7753 vcpu->run->internal.data[1] = exit_reason;
7754 return 0;
7755 }
3b86cd99 7756
644d711a
NHE		 7757 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7758 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7759 get_vmcs12(vcpu))))) {
c4282df9 7760 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7761 vmx->soft_vnmi_blocked = 0;
3b86cd99 7762 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7763 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7764 /*
7765 * This CPU don't support us in finding the end of an
7766 * NMI-blocked window if the guest runs with IRQs
7767 * disabled. So we pull the trigger after 1 s of
7768 * futile waiting, but inform the user about this.
7769 */
7770 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7771 "state on VCPU %d after 1 s timeout\n",
7772 __func__, vcpu->vcpu_id);
7773 vmx->soft_vnmi_blocked = 0;
3b86cd99 7774 }
3b86cd99
JK		 7775 }
7776
6aa8b732
AK		 7777 if (exit_reason < kvm_vmx_max_exit_handlers
7778 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7779 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7780 else {
2bc19dc3
MT		 7781 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7782 kvm_queue_exception(vcpu, UD_VECTOR);
7783 return 1;
6aa8b732 7784 }
6aa8b732
AK		 7785}
7786
95ba8273 7787static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7788{
a7c0b07d
WL		 7789 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7790
7791 if (is_guest_mode(vcpu) &&
7792 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7793 return;
7794
95ba8273 7795 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7796 vmcs_write32(TPR_THRESHOLD, 0);
7797 return;
7798 }
7799
95ba8273 7800 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7801}
7802
8d14695f
YZ		 7803static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7804{
7805 u32 sec_exec_control;
7806
7807 /*
7808 * There is not point to enable virtualize x2apic without enable
7809 * apicv
7810 */
c7c9c56c
YZ		 7811 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7812 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7813 return;
7814
7815 if (!vm_need_tpr_shadow(vcpu->kvm))
7816 return;
7817
7818 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7819
7820 if (set) {
7821 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7822 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7823 } else {
7824 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7825 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7826 }
7827 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7828
7829 vmx_set_msr_bitmap(vcpu);
7830}
7831
38b99173
TC		 7832static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7833{
7834 struct vcpu_vmx *vmx = to_vmx(vcpu);
7835
7836 /*
7837 * Currently we do not handle the nested case where L2 has an
7838 * APIC access page of its own; that page is still pinned.
7839 * Hence, we skip the case where the VCPU is in guest mode _and_
7840 * L1 prepared an APIC access page for L2.
7841 *
7842 * For the case where L1 and L2 share the same APIC access page
7843 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7844 * in the vmcs12), this function will only update either the vmcs01
7845 * or the vmcs02. If the former, the vmcs02 will be updated by
7846 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7847 * the next L2->L1 exit.
7848 */
7849 if (!is_guest_mode(vcpu) ||
7850 !nested_cpu_has2(vmx->nested.current_vmcs12,
7851 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7852 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7853}
7854
c7c9c56c
YZ		 7855static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7856{
7857 u16 status;
7858 u8 old;
7859
c7c9c56c
YZ		 7860 if (isr == -1)
7861 isr = 0;
7862
7863 status = vmcs_read16(GUEST_INTR_STATUS);
7864 old = status >> 8;
7865 if (isr != old) {
7866 status &= 0xff;
7867 status |= isr << 8;
7868 vmcs_write16(GUEST_INTR_STATUS, status);
7869 }
7870}
7871
7872static void vmx_set_rvi(int vector)
7873{
7874 u16 status;
7875 u8 old;
7876
4114c27d
WW		 7877 if (vector == -1)
7878 vector = 0;
7879
c7c9c56c
YZ		 7880 status = vmcs_read16(GUEST_INTR_STATUS);
7881 old = (u8)status & 0xff;
7882 if ((u8)vector != old) {
7883 status &= ~0xff;
7884 status |= (u8)vector;
7885 vmcs_write16(GUEST_INTR_STATUS, status);
7886 }
7887}
7888
7889static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7890{
4114c27d
WW		 7891 if (!is_guest_mode(vcpu)) {
7892 vmx_set_rvi(max_irr);
7893 return;
7894 }
7895
c7c9c56c
YZ		 7896 if (max_irr == -1)
7897 return;
7898
963fee16 7899 /*
4114c27d
WW		 7900 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7901 * handles it.
963fee16 7902 */
4114c27d 7903 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7904 return;
7905
963fee16 7906 /*
4114c27d 7907 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7908 * is run without virtual interrupt delivery.
7909 */
7910 if (!kvm_event_needs_reinjection(vcpu) &&
7911 vmx_interrupt_allowed(vcpu)) {
7912 kvm_queue_interrupt(vcpu, max_irr, false);
7913 vmx_inject_irq(vcpu);
7914 }
c7c9c56c
YZ		 7915}
7916
7917static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7918{
3d81bc7e
YZ		 7919 if (!vmx_vm_has_apicv(vcpu->kvm))
7920 return;
7921
c7c9c56c
YZ		 7922 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7923 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7924 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7925 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7926}
7927
51aa01d1 7928static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7929{
00eba012
AK		 7930 u32 exit_intr_info;
7931
7932 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7933 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7934 return;
7935
c5ca8e57 7936 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7937 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7938
7939 /* Handle machine checks before interrupts are enabled */
00eba012 7940 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7941 kvm_machine_check();
7942
20f65983 7943 /* We need to handle NMIs before interrupts are enabled */
00eba012 7944 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7945 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7946 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7947 asm("int $2");
ff9d07a0
ZY		 7948 kvm_after_handle_nmi(&vmx->vcpu);
7949 }
51aa01d1 7950}
20f65983 7951
a547c6db
YZ		 7952static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7953{
7954 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7955
7956 /*
7957 * If external interrupt exists, IF bit is set in rflags/eflags on the
7958 * interrupt stack frame, and interrupt will be enabled on a return
7959 * from interrupt handler.
7960 */
7961 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7962 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7963 unsigned int vector;
7964 unsigned long entry;
7965 gate_desc *desc;
7966 struct vcpu_vmx *vmx = to_vmx(vcpu);
7967#ifdef CONFIG_X86_64
7968 unsigned long tmp;
7969#endif
7970
7971 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7972 desc = (gate_desc *)vmx->host_idt_base + vector;
7973 entry = gate_offset(*desc);
7974 asm volatile(
7975#ifdef CONFIG_X86_64
7976 "mov %%" _ASM_SP ", %[sp]\n\t"
7977 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7978 "push $%c[ss]\n\t"
7979 "push %[sp]\n\t"
7980#endif
7981 "pushf\n\t"
7982 "orl $0x200, (%%" _ASM_SP ")\n\t"
7983 __ASM_SIZE(push) " $%c[cs]\n\t"
7984 "call *%[entry]\n\t"
7985 :
7986#ifdef CONFIG_X86_64
7987 [sp]"=&r"(tmp)
7988#endif
7989 :
7990 [entry]"r"(entry),
7991 [ss]"i"(__KERNEL_DS),
7992 [cs]"i"(__KERNEL_CS)
7993 );
7994 } else
7995 local_irq_enable();
7996}
7997
da8999d3
LJ		 7998static bool vmx_mpx_supported(void)
7999{
8000 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8001 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8002}
8003
55412b2e
WL		 8004static bool vmx_xsaves_supported(void)
8005{
8006 return vmcs_config.cpu_based_2nd_exec_ctrl &
8007 SECONDARY_EXEC_XSAVES;
8008}
8009
51aa01d1
AK		 8010static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8011{
c5ca8e57 8012 u32 exit_intr_info;
51aa01d1
AK		 8013 bool unblock_nmi;
8014 u8 vector;
8015 bool idtv_info_valid;
8016
8017 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8018
cf393f75 8019 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8020 if (vmx->nmi_known_unmasked)
8021 return;
c5ca8e57
AK		 8022 /*
8023 * Can't use vmx->exit_intr_info since we're not sure what
8024 * the exit reason is.
8025 */
8026 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8027 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8028 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8029 /*
7b4a25cb 8030 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8031 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8032 * a guest IRET fault.
7b4a25cb
GN		 8033 * SDM 3: 23.2.2 (September 2008)
8034 * Bit 12 is undefined in any of the following cases:
8035 * If the VM exit sets the valid bit in the IDT-vectoring
8036 * information field.
8037 * If the VM exit is due to a double fault.
cf393f75 8038 */
7b4a25cb
GN		 8039 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8040 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8041 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8042 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8043 else
8044 vmx->nmi_known_unmasked =
8045 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8046 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8047 } else if (unlikely(vmx->soft_vnmi_blocked))
8048 vmx->vnmi_blocked_time +=
8049 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8050}
8051
3ab66e8a 8052static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8053 u32 idt_vectoring_info,
8054 int instr_len_field,
8055 int error_code_field)
51aa01d1 8056{
51aa01d1
AK		 8057 u8 vector;
8058 int type;
8059 bool idtv_info_valid;
8060
8061 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8062
3ab66e8a
JK		 8063 vcpu->arch.nmi_injected = false;
8064 kvm_clear_exception_queue(vcpu);
8065 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8066
8067 if (!idtv_info_valid)
8068 return;
8069
3ab66e8a 8070 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8071
668f612f
AK		 8072 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8073 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8074
64a7ec06 8075 switch (type) {
37b96e98 8076 case INTR_TYPE_NMI_INTR:
3ab66e8a 8077 vcpu->arch.nmi_injected = true;
668f612f 8078 /*
7b4a25cb 8079 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8080 * Clear bit "block by NMI" before VM entry if a NMI
8081 * delivery faulted.
668f612f 8082 */
3ab66e8a 8083 vmx_set_nmi_mask(vcpu, false);
37b96e98 8084 break;
37b96e98 8085 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8086 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8087 /* fall through */
8088 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8089 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8090 u32 err = vmcs_read32(error_code_field);
851eb667 8091 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8092 } else
851eb667 8093 kvm_requeue_exception(vcpu, vector);
37b96e98 8094 break;
66fd3f7f 8095 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8096 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8097 /* fall through */
37b96e98 8098 case INTR_TYPE_EXT_INTR:
3ab66e8a 8099 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8100 break;
8101 default:
8102 break;
f7d9238f 8103 }
cf393f75
AK		 8104}
8105
83422e17
AK		 8106static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8107{
3ab66e8a 8108 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8109 VM_EXIT_INSTRUCTION_LEN,
8110 IDT_VECTORING_ERROR_CODE);
8111}
8112
b463a6f7
AK		 8113static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8114{
3ab66e8a 8115 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8116 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8117 VM_ENTRY_INSTRUCTION_LEN,
8118 VM_ENTRY_EXCEPTION_ERROR_CODE);
8119
8120 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8121}
8122
d7cd9796
GN		 8123static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8124{
8125 int i, nr_msrs;
8126 struct perf_guest_switch_msr *msrs;
8127
8128 msrs = perf_guest_get_msrs(&nr_msrs);
8129
8130 if (!msrs)
8131 return;
8132
8133 for (i = 0; i < nr_msrs; i++)
8134 if (msrs[i].host == msrs[i].guest)
8135 clear_atomic_switch_msr(vmx, msrs[i].msr);
8136 else
8137 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8138 msrs[i].host);
8139}
8140
a3b5ba49 8141static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8142{
a2fa3e9f 8143 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8144 unsigned long debugctlmsr, cr4;
104f226b
AK		 8145
8146 /* Record the guest's net vcpu time for enforced NMI injections. */
8147 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8148 vmx->entry_time = ktime_get();
8149
8150 /* Don't enter VMX if guest state is invalid, let the exit handler
8151 start emulation until we arrive back to a valid state */
14168786 8152 if (vmx->emulation_required)
104f226b
AK		 8153 return;
8154
a7653ecd
RK		 8155 if (vmx->ple_window_dirty) {
8156 vmx->ple_window_dirty = false;
8157 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8158 }
8159
012f83cb
AG		 8160 if (vmx->nested.sync_shadow_vmcs) {
8161 copy_vmcs12_to_shadow(vmx);
8162 vmx->nested.sync_shadow_vmcs = false;
8163 }
8164
104f226b
AK		 8165 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8166 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8167 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8168 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8169
1e02ce4c 8170 cr4 = cr4_read_shadow();
d974baa3
AL		 8171 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8172 vmcs_writel(HOST_CR4, cr4);
8173 vmx->host_state.vmcs_host_cr4 = cr4;
8174 }
8175
104f226b
AK		 8176 /* When single-stepping over STI and MOV SS, we must clear the
8177 * corresponding interruptibility bits in the guest state. Otherwise
8178 * vmentry fails as it then expects bit 14 (BS) in pending debug
8179 * exceptions being set, but that's not correct for the guest debugging
8180 * case. */
8181 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8182 vmx_set_interrupt_shadow(vcpu, 0);
8183
d7cd9796 8184 atomic_switch_perf_msrs(vmx);
2a7921b7 8185 debugctlmsr = get_debugctlmsr();
d7cd9796 8186
d462b819 8187 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8188 asm(
6aa8b732 8189 /* Store host registers */
b188c81f
AK		 8190 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8191 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8192 "push %%" _ASM_CX " \n\t"
8193 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8194 "je 1f \n\t"
b188c81f 8195 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8196 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8197 "1: \n\t"
d3edefc0 8198 /* Reload cr2 if changed */
b188c81f
AK		 8199 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8200 "mov %%cr2, %%" _ASM_DX " \n\t"
8201 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8202 "je 2f \n\t"
b188c81f 8203 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8204 "2: \n\t"
6aa8b732 8205 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8206 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8207 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8208 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8209 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8210 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8211 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8212 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8213 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8214#ifdef CONFIG_X86_64
e08aa78a
AK		 8215 "mov %c[r8](%0), %%r8 \n\t"
8216 "mov %c[r9](%0), %%r9 \n\t"
8217 "mov %c[r10](%0), %%r10 \n\t"
8218 "mov %c[r11](%0), %%r11 \n\t"
8219 "mov %c[r12](%0), %%r12 \n\t"
8220 "mov %c[r13](%0), %%r13 \n\t"
8221 "mov %c[r14](%0), %%r14 \n\t"
8222 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8223#endif
b188c81f 8224 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8225
6aa8b732 8226 /* Enter guest mode */
83287ea4 8227 "jne 1f \n\t"
4ecac3fd 8228 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8229 "jmp 2f \n\t"
8230 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8231 "2: "
6aa8b732 8232 /* Save guest registers, load host registers, keep flags */
b188c81f 8233 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8234 "pop %0 \n\t"
b188c81f
AK		 8235 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8236 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8237 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8238 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8239 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8240 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8241 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8242#ifdef CONFIG_X86_64
e08aa78a
AK		 8243 "mov %%r8, %c[r8](%0) \n\t"
8244 "mov %%r9, %c[r9](%0) \n\t"
8245 "mov %%r10, %c[r10](%0) \n\t"
8246 "mov %%r11, %c[r11](%0) \n\t"
8247 "mov %%r12, %c[r12](%0) \n\t"
8248 "mov %%r13, %c[r13](%0) \n\t"
8249 "mov %%r14, %c[r14](%0) \n\t"
8250 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8251#endif
b188c81f
AK		 8252 "mov %%cr2, %%" _ASM_AX " \n\t"
8253 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8254
b188c81f 8255 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8256 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8257 ".pushsection .rodata \n\t"
8258 ".global vmx_return \n\t"
8259 "vmx_return: " _ASM_PTR " 2b \n\t"
8260 ".popsection"
e08aa78a 8261 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8262 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8263 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8264 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8265 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8266 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8267 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8268 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8269 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8270 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8271 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8272#ifdef CONFIG_X86_64
ad312c7c
ZX		 8273 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8274 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8275 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8276 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8277 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8278 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8279 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8280 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8281#endif
40712fae
AK		 8282 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8283 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8284 : "cc", "memory"
8285#ifdef CONFIG_X86_64
b188c81f 8286 , "rax", "rbx", "rdi", "rsi"
c2036300 8287 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8288#else
8289 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8290#endif
8291 );
6aa8b732 8292
2a7921b7
GN		 8293 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8294 if (debugctlmsr)
8295 update_debugctlmsr(debugctlmsr);
8296
aa67f609
AK		 8297#ifndef CONFIG_X86_64
8298 /*
8299 * The sysexit path does not restore ds/es, so we must set them to
8300 * a reasonable value ourselves.
8301 *
8302 * We can't defer this to vmx_load_host_state() since that function
8303 * may be executed in interrupt context, which saves and restore segments
8304 * around it, nullifying its effect.
8305 */
8306 loadsegment(ds, __USER_DS);
8307 loadsegment(es, __USER_DS);
8308#endif
8309
6de4f3ad 8310 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8311 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8312 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8313 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8314 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8315 vcpu->arch.regs_dirty = 0;
8316
1155f76a
AK		 8317 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8318
d462b819 8319 vmx->loaded_vmcs->launched = 1;
1b6269db 8320
51aa01d1 8321 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8322 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8323
e0b890d3
GN		 8324 /*
8325 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8326 * we did not inject a still-pending event to L1 now because of
8327 * nested_run_pending, we need to re-enable this bit.
8328 */
8329 if (vmx->nested.nested_run_pending)
8330 kvm_make_request(KVM_REQ_EVENT, vcpu);
8331
8332 vmx->nested.nested_run_pending = 0;
8333
51aa01d1
AK		 8334 vmx_complete_atomic_exit(vmx);
8335 vmx_recover_nmi_blocking(vmx);
cf393f75 8336 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8337}
8338
4fa7734c
PB		 8339static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8340{
8341 struct vcpu_vmx *vmx = to_vmx(vcpu);
8342 int cpu;
8343
8344 if (vmx->loaded_vmcs == &vmx->vmcs01)
8345 return;
8346
8347 cpu = get_cpu();
8348 vmx->loaded_vmcs = &vmx->vmcs01;
8349 vmx_vcpu_put(vcpu);
8350 vmx_vcpu_load(vcpu, cpu);
8351 vcpu->cpu = cpu;
8352 put_cpu();
8353}
8354
6aa8b732
AK		 8355static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8356{
fb3f0f51
RR		 8357 struct vcpu_vmx *vmx = to_vmx(vcpu);
8358
843e4330
KH		 8359 if (enable_pml)
8360 vmx_disable_pml(vmx);
cdbecfc3 8361 free_vpid(vmx);
4fa7734c
PB		 8362 leave_guest_mode(vcpu);
8363 vmx_load_vmcs01(vcpu);
26a865f4 8364 free_nested(vmx);
4fa7734c 8365 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8366 kfree(vmx->guest_msrs);
8367 kvm_vcpu_uninit(vcpu);
a4770347 8368 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8369}
8370
fb3f0f51 8371static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8372{
fb3f0f51 8373 int err;
c16f862d 8374 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8375 int cpu;
6aa8b732 8376
a2fa3e9f 8377 if (!vmx)
fb3f0f51
RR		 8378 return ERR_PTR(-ENOMEM);
8379
2384d2b3
SY		 8380 allocate_vpid(vmx);
8381
fb3f0f51
RR		 8382 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8383 if (err)
8384 goto free_vcpu;
965b58a5 8385
a2fa3e9f 8386 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8387 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8388 > PAGE_SIZE);
0123be42 8389
be6d05cf 8390 err = -ENOMEM;
fb3f0f51 8391 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8392 goto uninit_vcpu;
8393 }
965b58a5 8394
d462b819
NHE		 8395 vmx->loaded_vmcs = &vmx->vmcs01;
8396 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8397 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8398 goto free_msrs;
d462b819
NHE		 8399 if (!vmm_exclusive)
8400 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8401 loaded_vmcs_init(vmx->loaded_vmcs);
8402 if (!vmm_exclusive)
8403 kvm_cpu_vmxoff();
a2fa3e9f 8404
15ad7146
AK		 8405 cpu = get_cpu();
8406 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8407 vmx->vcpu.cpu = cpu;
8b9cf98c 8408 err = vmx_vcpu_setup(vmx);
fb3f0f51 8409 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8410 put_cpu();
fb3f0f51
RR		 8411 if (err)
8412 goto free_vmcs;
a63cb560 8413 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8414 err = alloc_apic_access_page(kvm);
8415 if (err)
5e4a0b3c 8416 goto free_vmcs;
a63cb560 8417 }
fb3f0f51 8418
b927a3ce
SY		 8419 if (enable_ept) {
8420 if (!kvm->arch.ept_identity_map_addr)
8421 kvm->arch.ept_identity_map_addr =
8422 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8423 err = init_rmode_identity_map(kvm);
8424 if (err)
93ea5388 8425 goto free_vmcs;
b927a3ce 8426 }
b7ebfb05 8427
b9c237bb
WV		 8428 if (nested)
8429 nested_vmx_setup_ctls_msrs(vmx);
8430
705699a1 8431 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8432 vmx->nested.current_vmptr = -1ull;
8433 vmx->nested.current_vmcs12 = NULL;
8434
843e4330
KH		 8435 /*
8436 * If PML is turned on, failure on enabling PML just results in failure
8437 * of creating the vcpu, therefore we can simplify PML logic (by
8438 * avoiding dealing with cases, such as enabling PML partially on vcpus
8439 * for the guest, etc.
8440 */
8441 if (enable_pml) {
8442 err = vmx_enable_pml(vmx);
8443 if (err)
8444 goto free_vmcs;
8445 }
8446
fb3f0f51
RR		 8447 return &vmx->vcpu;
8448
8449free_vmcs:
5f3fbc34 8450 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8451free_msrs:
fb3f0f51
RR		 8452 kfree(vmx->guest_msrs);
8453uninit_vcpu:
8454 kvm_vcpu_uninit(&vmx->vcpu);
8455free_vcpu:
cdbecfc3 8456 free_vpid(vmx);
a4770347 8457 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8458 return ERR_PTR(err);
6aa8b732
AK		 8459}
8460
002c7f7c
YS		 8461static void __init vmx_check_processor_compat(void *rtn)
8462{
8463 struct vmcs_config vmcs_conf;
8464
8465 *(int *)rtn = 0;
8466 if (setup_vmcs_config(&vmcs_conf) < 0)
8467 *(int *)rtn = -EIO;
8468 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8469 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8470 smp_processor_id());
8471 *(int *)rtn = -EIO;
8472 }
8473}
8474
67253af5
SY		 8475static int get_ept_level(void)
8476{
8477 return VMX_EPT_DEFAULT_GAW + 1;
8478}
8479
4b12f0de 8480static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8481{
4b12f0de
SY		 8482 u64 ret;
8483
522c68c4
SY		 8484 /* For VT-d and EPT combination
8485 * 1. MMIO: always map as UC
8486 * 2. EPT with VT-d:
8487 * a. VT-d without snooping control feature: can't guarantee the
8488 * result, try to trust guest.
8489 * b. VT-d with snooping control feature: snooping control feature of
8490 * VT-d engine can guarantee the cache correctness. Just set it
8491 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8492 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8493 * consistent with host MTRR
8494 */
4b12f0de
SY		 8495 if (is_mmio)
8496 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8497 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8498 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8499 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8500 else
522c68c4 8501 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8502 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8503
8504 return ret;
64d4d521
SY		 8505}
8506
17cc3935 8507static int vmx_get_lpage_level(void)
344f414f 8508{
878403b7
SY		 8509 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8510 return PT_DIRECTORY_LEVEL;
8511 else
8512 /* For shadow and EPT supported 1GB page */
8513 return PT_PDPE_LEVEL;
344f414f
JR		 8514}
8515
0e851880
SY		 8516static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8517{
4e47c7a6
SY		 8518 struct kvm_cpuid_entry2 *best;
8519 struct vcpu_vmx *vmx = to_vmx(vcpu);
8520 u32 exec_control;
8521
8522 vmx->rdtscp_enabled = false;
8523 if (vmx_rdtscp_supported()) {
8524 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8525 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8526 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8527 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8528 vmx->rdtscp_enabled = true;
8529 else {
8530 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8531 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8532 exec_control);
8533 }
8534 }
b3a2a907
JK		 8535 if (nested && !vmx->rdtscp_enabled)
8536 vmx->nested.nested_vmx_secondary_ctls_high &=
8537 ~SECONDARY_EXEC_RDTSCP;
4e47c7a6 8538 }
ad756a16 8539
ad756a16
MJ		 8540 /* Exposing INVPCID only when PCID is exposed */
8541 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8542 if (vmx_invpcid_supported() &&
4f977045 8543 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8544 guest_cpuid_has_pcid(vcpu)) {
29282fde 8545 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8546 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8547 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8548 exec_control);
8549 } else {
29282fde
TI		 8550 if (cpu_has_secondary_exec_ctrls()) {
8551 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8552 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8553 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8554 exec_control);
8555 }
ad756a16 8556 if (best)
4f977045 8557 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8558 }
0e851880
SY		 8559}
8560
d4330ef2
JR		 8561static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8562{
7b8050f5
NHE		 8563 if (func == 1 && nested)
8564 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8565}
8566
25d92081
YZ		 8567static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8568 struct x86_exception *fault)
8569{
533558bc
JK		 8570 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8571 u32 exit_reason;
25d92081
YZ		 8572
8573 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8574 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8575 else
533558bc
JK		 8576 exit_reason = EXIT_REASON_EPT_VIOLATION;
8577 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8578 vmcs12->guest_physical_address = fault->address;
8579}
8580
155a97a3
NHE		 8581/* Callbacks for nested_ept_init_mmu_context: */
8582
8583static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8584{
8585 /* return the page table to be shadowed - in our case, EPT12 */
8586 return get_vmcs12(vcpu)->ept_pointer;
8587}
8588
8a3c1a33 8589static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8590{
ad896af0
PB		 8591 WARN_ON(mmu_is_nested(vcpu));
8592 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8593 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8594 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8595 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8596 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8597 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8598
8599 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8600}
8601
8602static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8603{
8604 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8605}
8606
19d5f10b
EK		 8607static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8608 u16 error_code)
8609{
8610 bool inequality, bit;
8611
8612 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8613 inequality =
8614 (error_code & vmcs12->page_fault_error_code_mask) !=
8615 vmcs12->page_fault_error_code_match;
8616 return inequality ^ bit;
8617}
8618
feaf0c7d
GN		 8619static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8620 struct x86_exception *fault)
8621{
8622 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8623
8624 WARN_ON(!is_guest_mode(vcpu));
8625
19d5f10b 8626 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8627 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8628 vmcs_read32(VM_EXIT_INTR_INFO),
8629 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8630 else
8631 kvm_inject_page_fault(vcpu, fault);
8632}
8633
a2bcba50
WL		 8634static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8635 struct vmcs12 *vmcs12)
8636{
8637 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8638 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8639
8640 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8641 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8642 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8643 return false;
8644
8645 /*
8646 * Translate L1 physical address to host physical
8647 * address for vmcs02. Keep the page pinned, so this
8648 * physical address remains valid. We keep a reference
8649 * to it so we can release it later.
8650 */
8651 if (vmx->nested.apic_access_page) /* shouldn't happen */
8652 nested_release_page(vmx->nested.apic_access_page);
8653 vmx->nested.apic_access_page =
8654 nested_get_page(vcpu, vmcs12->apic_access_addr);
8655 }
a7c0b07d
WL		 8656
8657 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8658 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8659 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8660 return false;
8661
8662 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8663 nested_release_page(vmx->nested.virtual_apic_page);
8664 vmx->nested.virtual_apic_page =
8665 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8666
8667 /*
8668 * Failing the vm entry is _not_ what the processor does
8669 * but it's basically the only possibility we have.
8670 * We could still enter the guest if CR8 load exits are
8671 * enabled, CR8 store exits are enabled, and virtualize APIC
8672 * access is disabled; in this case the processor would never
8673 * use the TPR shadow and we could simply clear the bit from
8674 * the execution control. But such a configuration is useless,
8675 * so let's keep the code simple.
8676 */
8677 if (!vmx->nested.virtual_apic_page)
8678 return false;
8679 }
8680
705699a1 8681 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8682 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8683 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8684 return false;
8685
8686 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8687 kunmap(vmx->nested.pi_desc_page);
8688 nested_release_page(vmx->nested.pi_desc_page);
8689 }
8690 vmx->nested.pi_desc_page =
8691 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8692 if (!vmx->nested.pi_desc_page)
8693 return false;
8694
8695 vmx->nested.pi_desc =
8696 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8697 if (!vmx->nested.pi_desc) {
8698 nested_release_page_clean(vmx->nested.pi_desc_page);
8699 return false;
8700 }
8701 vmx->nested.pi_desc =
8702 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8703 (unsigned long)(vmcs12->posted_intr_desc_addr &
8704 (PAGE_SIZE - 1)));
8705 }
8706
a2bcba50
WL		 8707 return true;
8708}
8709
f4124500
JK		 8710static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8711{
8712 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8713 struct vcpu_vmx *vmx = to_vmx(vcpu);
8714
8715 if (vcpu->arch.virtual_tsc_khz == 0)
8716 return;
8717
8718 /* Make sure short timeouts reliably trigger an immediate vmexit.
8719 * hrtimer_start does not guarantee this. */
8720 if (preemption_timeout <= 1) {
8721 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8722 return;
8723 }
8724
8725 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8726 preemption_timeout *= 1000000;
8727 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8728 hrtimer_start(&vmx->nested.preemption_timer,
8729 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8730}
8731
3af18d9c
WV		 8732static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8733 struct vmcs12 *vmcs12)
8734{
8735 int maxphyaddr;
8736 u64 addr;
8737
8738 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8739 return 0;
8740
8741 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8742 WARN_ON(1);
8743 return -EINVAL;
8744 }
8745 maxphyaddr = cpuid_maxphyaddr(vcpu);
8746
8747 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8748 ((addr + PAGE_SIZE) >> maxphyaddr))
8749 return -EINVAL;
8750
8751 return 0;
8752}
8753
8754/*
8755 * Merge L0's and L1's MSR bitmap, return false to indicate that
8756 * we do not use the hardware.
8757 */
8758static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8759 struct vmcs12 *vmcs12)
8760{
82f0dd4b 8761 int msr;
f2b93280
WV		 8762 struct page *page;
8763 unsigned long *msr_bitmap;
8764
8765 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8766 return false;
8767
8768 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8769 if (!page) {
8770 WARN_ON(1);
8771 return false;
8772 }
8773 msr_bitmap = (unsigned long *)kmap(page);
8774 if (!msr_bitmap) {
8775 nested_release_page_clean(page);
8776 WARN_ON(1);
8777 return false;
8778 }
8779
8780 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8781 if (nested_cpu_has_apic_reg_virt(vmcs12))
8782 for (msr = 0x800; msr <= 0x8ff; msr++)
8783 nested_vmx_disable_intercept_for_msr(
8784 msr_bitmap,
8785 vmx_msr_bitmap_nested,
8786 msr, MSR_TYPE_R);
f2b93280
WV		 8787 /* TPR is allowed */
8788 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8789 vmx_msr_bitmap_nested,
8790 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8791 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8792 if (nested_cpu_has_vid(vmcs12)) {
8793 /* EOI and self-IPI are allowed */
8794 nested_vmx_disable_intercept_for_msr(
8795 msr_bitmap,
8796 vmx_msr_bitmap_nested,
8797 APIC_BASE_MSR + (APIC_EOI >> 4),
8798 MSR_TYPE_W);
8799 nested_vmx_disable_intercept_for_msr(
8800 msr_bitmap,
8801 vmx_msr_bitmap_nested,
8802 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8803 MSR_TYPE_W);
8804 }
82f0dd4b
WV		 8805 } else {
8806 /*
8807 * Enable reading intercept of all the x2apic
8808 * MSRs. We should not rely on vmcs12 to do any
8809 * optimizations here, it may have been modified
8810 * by L1.
8811 */
8812 for (msr = 0x800; msr <= 0x8ff; msr++)
8813 __vmx_enable_intercept_for_msr(
8814 vmx_msr_bitmap_nested,
8815 msr,
8816 MSR_TYPE_R);
8817
f2b93280
WV		 8818 __vmx_enable_intercept_for_msr(
8819 vmx_msr_bitmap_nested,
8820 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8821 MSR_TYPE_W);
608406e2
WV		 8822 __vmx_enable_intercept_for_msr(
8823 vmx_msr_bitmap_nested,
8824 APIC_BASE_MSR + (APIC_EOI >> 4),
8825 MSR_TYPE_W);
8826 __vmx_enable_intercept_for_msr(
8827 vmx_msr_bitmap_nested,
8828 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8829 MSR_TYPE_W);
82f0dd4b 8830 }
f2b93280
WV		 8831 kunmap(page);
8832 nested_release_page_clean(page);
8833
8834 return true;
8835}
8836
8837static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8838 struct vmcs12 *vmcs12)
8839{
82f0dd4b 8840 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 8841 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 8842 !nested_cpu_has_vid(vmcs12) &&
8843 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 8844 return 0;
8845
8846 /*
8847 * If virtualize x2apic mode is enabled,
8848 * virtualize apic access must be disabled.
8849 */
82f0dd4b
WV		 8850 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8851 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8852 return -EINVAL;
8853
608406e2
WV		 8854 /*
8855 * If virtual interrupt delivery is enabled,
8856 * we must exit on external interrupts.
8857 */
8858 if (nested_cpu_has_vid(vmcs12) &&
8859 !nested_exit_on_intr(vcpu))
8860 return -EINVAL;
8861
705699a1
WV		 8862 /*
8863 * bits 15:8 should be zero in posted_intr_nv,
8864 * the descriptor address has been already checked
8865 * in nested_get_vmcs12_pages.
8866 */
8867 if (nested_cpu_has_posted_intr(vmcs12) &&
8868 (!nested_cpu_has_vid(vmcs12) ||
8869 !nested_exit_intr_ack_set(vcpu) ||
8870 vmcs12->posted_intr_nv & 0xff00))
8871 return -EINVAL;
8872
f2b93280
WV		 8873 /* tpr shadow is needed by all apicv features. */
8874 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8875 return -EINVAL;
8876
8877 return 0;
3af18d9c
WV		 8878}
8879
e9ac033e
EK		 8880static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8881 unsigned long count_field,
92d71bc6 8882 unsigned long addr_field)
ff651cb6 8883{
92d71bc6 8884 int maxphyaddr;
e9ac033e
EK		 8885 u64 count, addr;
8886
8887 if (vmcs12_read_any(vcpu, count_field, &count) ||
8888 vmcs12_read_any(vcpu, addr_field, &addr)) {
8889 WARN_ON(1);
8890 return -EINVAL;
8891 }
8892 if (count == 0)
8893 return 0;
92d71bc6 8894 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 8895 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8896 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8897 pr_warn_ratelimited(
8898 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8899 addr_field, maxphyaddr, count, addr);
8900 return -EINVAL;
8901 }
8902 return 0;
8903}
8904
8905static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8906 struct vmcs12 *vmcs12)
8907{
e9ac033e
EK		 8908 if (vmcs12->vm_exit_msr_load_count == 0 &&
8909 vmcs12->vm_exit_msr_store_count == 0 &&
8910 vmcs12->vm_entry_msr_load_count == 0)
8911 return 0; /* Fast path */
e9ac033e 8912 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 8913 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 8914 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 8915 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 8916 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 8917 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 8918 return -EINVAL;
8919 return 0;
8920}
8921
8922static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8923 struct vmx_msr_entry *e)
8924{
8925 /* x2APIC MSR accesses are not allowed */
8926 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8927 return -EINVAL;
8928 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8929 e->index == MSR_IA32_UCODE_REV)
8930 return -EINVAL;
8931 if (e->reserved != 0)
ff651cb6
WV		 8932 return -EINVAL;
8933 return 0;
8934}
8935
e9ac033e
EK		 8936static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8937 struct vmx_msr_entry *e)
ff651cb6
WV		 8938{
8939 if (e->index == MSR_FS_BASE ||
8940 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8941 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8942 nested_vmx_msr_check_common(vcpu, e))
8943 return -EINVAL;
8944 return 0;
8945}
8946
8947static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8948 struct vmx_msr_entry *e)
8949{
8950 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8951 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8952 return -EINVAL;
8953 return 0;
8954}
8955
8956/*
8957 * Load guest's/host's msr at nested entry/exit.
8958 * return 0 for success, entry index for failure.
8959 */
8960static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8961{
8962 u32 i;
8963 struct vmx_msr_entry e;
8964 struct msr_data msr;
8965
8966 msr.host_initiated = false;
8967 for (i = 0; i < count; i++) {
e9ac033e
EK		 8968 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8969 &e, sizeof(e))) {
8970 pr_warn_ratelimited(
8971 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8972 __func__, i, gpa + i * sizeof(e));
ff651cb6 8973 goto fail;
e9ac033e
EK		 8974 }
8975 if (nested_vmx_load_msr_check(vcpu, &e)) {
8976 pr_warn_ratelimited(
8977 "%s check failed (%u, 0x%x, 0x%x)\n",
8978 __func__, i, e.index, e.reserved);
8979 goto fail;
8980 }
ff651cb6
WV		 8981 msr.index = e.index;
8982 msr.data = e.value;
e9ac033e
EK		 8983 if (kvm_set_msr(vcpu, &msr)) {
8984 pr_warn_ratelimited(
8985 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8986 __func__, i, e.index, e.value);
ff651cb6 8987 goto fail;
e9ac033e 8988 }
ff651cb6
WV		 8989 }
8990 return 0;
8991fail:
8992 return i + 1;
8993}
8994
8995static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8996{
8997 u32 i;
8998 struct vmx_msr_entry e;
8999
9000 for (i = 0; i < count; i++) {
e9ac033e
EK		 9001 if (kvm_read_guest(vcpu->kvm,
9002 gpa + i * sizeof(e),
9003 &e, 2 * sizeof(u32))) {
9004 pr_warn_ratelimited(
9005 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9006 __func__, i, gpa + i * sizeof(e));
ff651cb6 9007 return -EINVAL;
e9ac033e
EK		 9008 }
9009 if (nested_vmx_store_msr_check(vcpu, &e)) {
9010 pr_warn_ratelimited(
9011 "%s check failed (%u, 0x%x, 0x%x)\n",
9012 __func__, i, e.index, e.reserved);
ff651cb6 9013 return -EINVAL;
e9ac033e
EK		 9014 }
9015 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9016 pr_warn_ratelimited(
9017 "%s cannot read MSR (%u, 0x%x)\n",
9018 __func__, i, e.index);
9019 return -EINVAL;
9020 }
9021 if (kvm_write_guest(vcpu->kvm,
9022 gpa + i * sizeof(e) +
ff651cb6 9023 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 9024 &e.value, sizeof(e.value))) {
9025 pr_warn_ratelimited(
9026 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9027 __func__, i, e.index, e.value);
9028 return -EINVAL;
9029 }
ff651cb6
WV		 9030 }
9031 return 0;
9032}
9033
fe3ef05c
NHE		 9034/*
9035 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9036 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9037 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9038 * guest in a way that will both be appropriate to L1's requests, and our
9039 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9040 * function also has additional necessary side-effects, like setting various
9041 * vcpu->arch fields.
9042 */
9043static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9044{
9045 struct vcpu_vmx *vmx = to_vmx(vcpu);
9046 u32 exec_control;
9047
9048 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9049 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9050 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9051 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9052 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9053 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9054 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9055 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9056 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9057 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9058 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9059 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9060 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9061 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9062 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9063 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9064 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9065 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9066 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9067 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9068 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9069 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9070 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9071 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9072 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9073 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9074 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9075 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9076 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9077 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9078 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9079 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9080 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9081 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9082 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9083 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9084
2996fca0
JK		 9085 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9086 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9087 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9088 } else {
9089 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9090 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9091 }
fe3ef05c
NHE		 9092 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9093 vmcs12->vm_entry_intr_info_field);
9094 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9095 vmcs12->vm_entry_exception_error_code);
9096 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9097 vmcs12->vm_entry_instruction_len);
9098 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9099 vmcs12->guest_interruptibility_info);
fe3ef05c 9100 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9101 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9102 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9103 vmcs12->guest_pending_dbg_exceptions);
9104 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9105 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9106
81dc01f7
WL		 9107 if (nested_cpu_has_xsaves(vmcs12))
9108 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9109 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9110
f4124500
JK		 9111 exec_control = vmcs12->pin_based_vm_exec_control;
9112 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9113 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9114
9115 if (nested_cpu_has_posted_intr(vmcs12)) {
9116 /*
9117 * Note that we use L0's vector here and in
9118 * vmx_deliver_nested_posted_interrupt.
9119 */
9120 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9121 vmx->nested.pi_pending = false;
9122 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9123 vmcs_write64(POSTED_INTR_DESC_ADDR,
9124 page_to_phys(vmx->nested.pi_desc_page) +
9125 (unsigned long)(vmcs12->posted_intr_desc_addr &
9126 (PAGE_SIZE - 1)));
9127 } else
9128 exec_control &= ~PIN_BASED_POSTED_INTR;
9129
f4124500 9130 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9131
f4124500
JK		 9132 vmx->nested.preemption_timer_expired = false;
9133 if (nested_cpu_has_preemption_timer(vmcs12))
9134 vmx_start_preemption_timer(vcpu);
0238ea91 9135
fe3ef05c
NHE		 9136 /*
9137 * Whether page-faults are trapped is determined by a combination of
9138 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9139 * If enable_ept, L0 doesn't care about page faults and we should
9140 * set all of these to L1's desires. However, if !enable_ept, L0 does
9141 * care about (at least some) page faults, and because it is not easy
9142 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9143 * to exit on each and every L2 page fault. This is done by setting
9144 * MASK=MATCH=0 and (see below) EB.PF=1.
9145 * Note that below we don't need special code to set EB.PF beyond the
9146 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9147 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9148 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9149 *
9150 * A problem with this approach (when !enable_ept) is that L1 may be
9151 * injected with more page faults than it asked for. This could have
9152 * caused problems, but in practice existing hypervisors don't care.
9153 * To fix this, we will need to emulate the PFEC checking (on the L1
9154 * page tables), using walk_addr(), when injecting PFs to L1.
9155 */
9156 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9157 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9158 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9159 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9160
9161 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9162 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 9163 if (!vmx->rdtscp_enabled)
9164 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9165 /* Take the following fields only from vmcs12 */
696dfd95 9166 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9167 SECONDARY_EXEC_RDTSCP |
696dfd95 9168 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
b3a2a907 9169 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9170 if (nested_cpu_has(vmcs12,
9171 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9172 exec_control |= vmcs12->secondary_vm_exec_control;
9173
9174 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9175 /*
9176 * If translation failed, no matter: This feature asks
9177 * to exit when accessing the given address, and if it
9178 * can never be accessed, this feature won't do
9179 * anything anyway.
9180 */
9181 if (!vmx->nested.apic_access_page)
9182 exec_control &=
9183 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9184 else
9185 vmcs_write64(APIC_ACCESS_ADDR,
9186 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 9187 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9188 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 9189 exec_control |=
9190 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9191 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9192 }
9193
608406e2
WV		 9194 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9195 vmcs_write64(EOI_EXIT_BITMAP0,
9196 vmcs12->eoi_exit_bitmap0);
9197 vmcs_write64(EOI_EXIT_BITMAP1,
9198 vmcs12->eoi_exit_bitmap1);
9199 vmcs_write64(EOI_EXIT_BITMAP2,
9200 vmcs12->eoi_exit_bitmap2);
9201 vmcs_write64(EOI_EXIT_BITMAP3,
9202 vmcs12->eoi_exit_bitmap3);
9203 vmcs_write16(GUEST_INTR_STATUS,
9204 vmcs12->guest_intr_status);
9205 }
9206
fe3ef05c
NHE		 9207 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9208 }
9209
9210
9211 /*
9212 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9213 * Some constant fields are set here by vmx_set_constant_host_state().
9214 * Other fields are different per CPU, and will be set later when
9215 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9216 */
a547c6db 9217 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9218
9219 /*
9220 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9221 * entry, but only if the current (host) sp changed from the value
9222 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9223 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9224 * here we just force the write to happen on entry.
9225 */
9226 vmx->host_rsp = 0;
9227
9228 exec_control = vmx_exec_control(vmx); /* L0's desires */
9229 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9230 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9231 exec_control &= ~CPU_BASED_TPR_SHADOW;
9232 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9233
9234 if (exec_control & CPU_BASED_TPR_SHADOW) {
9235 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9236 page_to_phys(vmx->nested.virtual_apic_page));
9237 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9238 }
9239
3af18d9c 9240 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9241 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9242 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9243 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9244 } else
9245 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9246
fe3ef05c 9247 /*
3af18d9c 9248 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9249 * Rather, exit every time.
9250 */
fe3ef05c
NHE		 9251 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9252 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9253
9254 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9255
9256 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9257 * bitwise-or of what L1 wants to trap for L2, and what we want to
9258 * trap. Note that CR0.TS also needs updating - we do this later.
9259 */
9260 update_exception_bitmap(vcpu);
9261 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9262 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9263
8049d651
NHE		 9264 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9265 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9266 * bits are further modified by vmx_set_efer() below.
9267 */
f4124500 9268 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9269
9270 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9271 * emulated by vmx_set_efer(), below.
9272 */
2961e876 9273 vm_entry_controls_init(vmx,
8049d651
NHE		 9274 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9275 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9276 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9277
44811c02 9278 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9279 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9280 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9281 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9282 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9283
9284
9285 set_cr4_guest_host_mask(vmx);
9286
36be0b9d
PB		 9287 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9288 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9289
27fc51b2
NHE		 9290 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9291 vmcs_write64(TSC_OFFSET,
9292 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9293 else
9294 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9295
9296 if (enable_vpid) {
9297 /*
9298 * Trivially support vpid by letting L2s share their parent
9299 * L1's vpid. TODO: move to a more elaborate solution, giving
9300 * each L2 its own vpid and exposing the vpid feature to L1.
9301 */
9302 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9303 vmx_flush_tlb(vcpu);
9304 }
9305
155a97a3
NHE		 9306 if (nested_cpu_has_ept(vmcs12)) {
9307 kvm_mmu_unload(vcpu);
9308 nested_ept_init_mmu_context(vcpu);
9309 }
9310
fe3ef05c
NHE		 9311 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9312 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9313 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9314 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9315 else
9316 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9317 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9318 vmx_set_efer(vcpu, vcpu->arch.efer);
9319
9320 /*
9321 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9322 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9323 * The CR0_READ_SHADOW is what L2 should have expected to read given
9324 * the specifications by L1; It's not enough to take
9325 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9326 * have more bits than L1 expected.
9327 */
9328 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9329 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9330
9331 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9332 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9333
9334 /* shadow page tables on either EPT or shadow page tables */
9335 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9336 kvm_mmu_reset_context(vcpu);
9337
feaf0c7d
GN		 9338 if (!enable_ept)
9339 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9340
3633cfc3
NHE		 9341 /*
9342 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9343 */
9344 if (enable_ept) {
9345 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9346 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9347 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9348 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9349 }
9350
fe3ef05c
NHE		 9351 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9352 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9353}
9354
cd232ad0
NHE		 9355/*
9356 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9357 * for running an L2 nested guest.
9358 */
9359static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9360{
9361 struct vmcs12 *vmcs12;
9362 struct vcpu_vmx *vmx = to_vmx(vcpu);
9363 int cpu;
9364 struct loaded_vmcs *vmcs02;
384bb783 9365 bool ia32e;
ff651cb6 9366 u32 msr_entry_idx;
cd232ad0
NHE		 9367
9368 if (!nested_vmx_check_permission(vcpu) ||
9369 !nested_vmx_check_vmcs12(vcpu))
9370 return 1;
9371
9372 skip_emulated_instruction(vcpu);
9373 vmcs12 = get_vmcs12(vcpu);
9374
012f83cb
AG		 9375 if (enable_shadow_vmcs)
9376 copy_shadow_to_vmcs12(vmx);
9377
7c177938
NHE		 9378 /*
9379 * The nested entry process starts with enforcing various prerequisites
9380 * on vmcs12 as required by the Intel SDM, and act appropriately when
9381 * they fail: As the SDM explains, some conditions should cause the
9382 * instruction to fail, while others will cause the instruction to seem
9383 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9384 * To speed up the normal (success) code path, we should avoid checking
9385 * for misconfigurations which will anyway be caught by the processor
9386 * when using the merged vmcs02.
9387 */
9388 if (vmcs12->launch_state == launch) {
9389 nested_vmx_failValid(vcpu,
9390 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9391 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9392 return 1;
9393 }
9394
6dfacadd
JK		 9395 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9396 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9397 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9398 return 1;
9399 }
9400
3af18d9c 9401 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9402 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9403 return 1;
9404 }
9405
3af18d9c 9406 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9407 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9408 return 1;
9409 }
9410
f2b93280
WV		 9411 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9412 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9413 return 1;
9414 }
9415
e9ac033e
EK		 9416 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9417 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9418 return 1;
9419 }
9420
7c177938 9421 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9422 vmx->nested.nested_vmx_true_procbased_ctls_low,
9423 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9424 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9425 vmx->nested.nested_vmx_secondary_ctls_low,
9426 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9427 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9428 vmx->nested.nested_vmx_pinbased_ctls_low,
9429 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9430 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9431 vmx->nested.nested_vmx_true_exit_ctls_low,
9432 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9433 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9434 vmx->nested.nested_vmx_true_entry_ctls_low,
9435 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9436 {
9437 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9438 return 1;
9439 }
9440
9441 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9442 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9443 nested_vmx_failValid(vcpu,
9444 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9445 return 1;
9446 }
9447
b9c237bb 9448 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9449 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9450 nested_vmx_entry_failure(vcpu, vmcs12,
9451 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9452 return 1;
9453 }
9454 if (vmcs12->vmcs_link_pointer != -1ull) {
9455 nested_vmx_entry_failure(vcpu, vmcs12,
9456 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9457 return 1;
9458 }
9459
384bb783 9460 /*
cb0c8cda 9461 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9462 * are performed on the field for the IA32_EFER MSR:
9463 * - Bits reserved in the IA32_EFER MSR must be 0.
9464 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9465 * the IA-32e mode guest VM-exit control. It must also be identical
9466 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9467 * CR0.PG) is 1.
9468 */
9469 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9470 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9471 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9472 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9473 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9474 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9475 nested_vmx_entry_failure(vcpu, vmcs12,
9476 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9477 return 1;
9478 }
9479 }
9480
9481 /*
9482 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9483 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9484 * the values of the LMA and LME bits in the field must each be that of
9485 * the host address-space size VM-exit control.
9486 */
9487 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9488 ia32e = (vmcs12->vm_exit_controls &
9489 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9490 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9491 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9492 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9493 nested_vmx_entry_failure(vcpu, vmcs12,
9494 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9495 return 1;
9496 }
9497 }
9498
7c177938
NHE		 9499 /*
9500 * We're finally done with prerequisite checking, and can start with
9501 * the nested entry.
9502 */
9503
cd232ad0
NHE		 9504 vmcs02 = nested_get_current_vmcs02(vmx);
9505 if (!vmcs02)
9506 return -ENOMEM;
9507
9508 enter_guest_mode(vcpu);
9509
9510 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9511
2996fca0
JK		 9512 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9513 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9514
cd232ad0
NHE		 9515 cpu = get_cpu();
9516 vmx->loaded_vmcs = vmcs02;
9517 vmx_vcpu_put(vcpu);
9518 vmx_vcpu_load(vcpu, cpu);
9519 vcpu->cpu = cpu;
9520 put_cpu();
9521
36c3cc42
JK		 9522 vmx_segment_cache_clear(vmx);
9523
cd232ad0
NHE		 9524 prepare_vmcs02(vcpu, vmcs12);
9525
ff651cb6
WV		 9526 msr_entry_idx = nested_vmx_load_msr(vcpu,
9527 vmcs12->vm_entry_msr_load_addr,
9528 vmcs12->vm_entry_msr_load_count);
9529 if (msr_entry_idx) {
9530 leave_guest_mode(vcpu);
9531 vmx_load_vmcs01(vcpu);
9532 nested_vmx_entry_failure(vcpu, vmcs12,
9533 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9534 return 1;
9535 }
9536
9537 vmcs12->launch_state = 1;
9538
6dfacadd 9539 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9540 return kvm_vcpu_halt(vcpu);
6dfacadd 9541
7af40ad3
JK		 9542 vmx->nested.nested_run_pending = 1;
9543
cd232ad0
NHE		 9544 /*
9545 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9546 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9547 * returned as far as L1 is concerned. It will only return (and set
9548 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9549 */
9550 return 1;
9551}
9552
4704d0be
NHE		 9553/*
9554 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9555 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9556 * This function returns the new value we should put in vmcs12.guest_cr0.
9557 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9558 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9559 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9560 * didn't trap the bit, because if L1 did, so would L0).
9561 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9562 * been modified by L2, and L1 knows it. So just leave the old value of
9563 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9564 * isn't relevant, because if L0 traps this bit it can set it to anything.
9565 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9566 * changed these bits, and therefore they need to be updated, but L0
9567 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9568 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9569 */
9570static inline unsigned long
9571vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9572{
9573 return
9574 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9575 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9576 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9577 vcpu->arch.cr0_guest_owned_bits));
9578}
9579
9580static inline unsigned long
9581vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9582{
9583 return
9584 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9585 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9586 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9587 vcpu->arch.cr4_guest_owned_bits));
9588}
9589
5f3d5799
JK		 9590static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9591 struct vmcs12 *vmcs12)
9592{
9593 u32 idt_vectoring;
9594 unsigned int nr;
9595
851eb667 9596 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9597 nr = vcpu->arch.exception.nr;
9598 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9599
9600 if (kvm_exception_is_soft(nr)) {
9601 vmcs12->vm_exit_instruction_len =
9602 vcpu->arch.event_exit_inst_len;
9603 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9604 } else
9605 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9606
9607 if (vcpu->arch.exception.has_error_code) {
9608 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9609 vmcs12->idt_vectoring_error_code =
9610 vcpu->arch.exception.error_code;
9611 }
9612
9613 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9614 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9615 vmcs12->idt_vectoring_info_field =
9616 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9617 } else if (vcpu->arch.interrupt.pending) {
9618 nr = vcpu->arch.interrupt.nr;
9619 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9620
9621 if (vcpu->arch.interrupt.soft) {
9622 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9623 vmcs12->vm_entry_instruction_len =
9624 vcpu->arch.event_exit_inst_len;
9625 } else
9626 idt_vectoring |= INTR_TYPE_EXT_INTR;
9627
9628 vmcs12->idt_vectoring_info_field = idt_vectoring;
9629 }
9630}
9631
b6b8a145
JK		 9632static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9633{
9634 struct vcpu_vmx *vmx = to_vmx(vcpu);
9635
f4124500
JK		 9636 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9637 vmx->nested.preemption_timer_expired) {
9638 if (vmx->nested.nested_run_pending)
9639 return -EBUSY;
9640 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9641 return 0;
9642 }
9643
b6b8a145 9644 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9645 if (vmx->nested.nested_run_pending ||
9646 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9647 return -EBUSY;
9648 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9649 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9650 INTR_INFO_VALID_MASK, 0);
9651 /*
9652 * The NMI-triggered VM exit counts as injection:
9653 * clear this one and block further NMIs.
9654 */
9655 vcpu->arch.nmi_pending = 0;
9656 vmx_set_nmi_mask(vcpu, true);
9657 return 0;
9658 }
9659
9660 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9661 nested_exit_on_intr(vcpu)) {
9662 if (vmx->nested.nested_run_pending)
9663 return -EBUSY;
9664 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9665 return 0;
b6b8a145
JK		 9666 }
9667
705699a1 9668 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9669}
9670
f4124500
JK		 9671static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9672{
9673 ktime_t remaining =
9674 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9675 u64 value;
9676
9677 if (ktime_to_ns(remaining) <= 0)
9678 return 0;
9679
9680 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9681 do_div(value, 1000000);
9682 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9683}
9684
4704d0be
NHE		 9685/*
9686 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9687 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9688 * and this function updates it to reflect the changes to the guest state while
9689 * L2 was running (and perhaps made some exits which were handled directly by L0
9690 * without going back to L1), and to reflect the exit reason.
9691 * Note that we do not have to copy here all VMCS fields, just those that
9692 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9693 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9694 * which already writes to vmcs12 directly.
9695 */
533558bc
JK		 9696static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9697 u32 exit_reason, u32 exit_intr_info,
9698 unsigned long exit_qualification)
4704d0be
NHE		 9699{
9700 /* update guest state fields: */
9701 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9702 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9703
4704d0be
NHE		 9704 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9705 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9706 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9707
9708 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9709 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9710 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9711 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9712 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9713 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9714 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9715 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9716 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9717 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9718 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9719 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9720 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9721 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9722 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9723 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9724 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9725 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9726 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9727 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9728 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9729 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9730 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9731 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9732 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9733 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9734 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9735 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9736 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9737 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9738 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9739 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9740 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9741 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9742 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9743 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9744
4704d0be
NHE		 9745 vmcs12->guest_interruptibility_info =
9746 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9747 vmcs12->guest_pending_dbg_exceptions =
9748 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9749 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9750 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9751 else
9752 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9753
f4124500
JK		 9754 if (nested_cpu_has_preemption_timer(vmcs12)) {
9755 if (vmcs12->vm_exit_controls &
9756 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9757 vmcs12->vmx_preemption_timer_value =
9758 vmx_get_preemption_timer_value(vcpu);
9759 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9760 }
7854cbca 9761
3633cfc3
NHE		 9762 /*
9763 * In some cases (usually, nested EPT), L2 is allowed to change its
9764 * own CR3 without exiting. If it has changed it, we must keep it.
9765 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9766 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9767 *
9768 * Additionally, restore L2's PDPTR to vmcs12.
9769 */
9770 if (enable_ept) {
9771 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9772 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9773 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9774 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9775 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9776 }
9777
608406e2
WV		 9778 if (nested_cpu_has_vid(vmcs12))
9779 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9780
c18911a2
JK		 9781 vmcs12->vm_entry_controls =
9782 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9783 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9784
2996fca0
JK		 9785 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9786 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9787 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9788 }
9789
4704d0be
NHE		 9790 /* TODO: These cannot have changed unless we have MSR bitmaps and
9791 * the relevant bit asks not to trap the change */
b8c07d55 9792 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9793 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9794 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9795 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9796 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9797 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9798 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9799 if (vmx_mpx_supported())
9800 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9801 if (nested_cpu_has_xsaves(vmcs12))
9802 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9803
9804 /* update exit information fields: */
9805
533558bc
JK		 9806 vmcs12->vm_exit_reason = exit_reason;
9807 vmcs12->exit_qualification = exit_qualification;
4704d0be 9808
533558bc 9809 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9810 if ((vmcs12->vm_exit_intr_info &
9811 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9812 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9813 vmcs12->vm_exit_intr_error_code =
9814 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9815 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9816 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9817 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9818
5f3d5799
JK		 9819 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9820 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9821 * instead of reading the real value. */
4704d0be 9822 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9823
9824 /*
9825 * Transfer the event that L0 or L1 may wanted to inject into
9826 * L2 to IDT_VECTORING_INFO_FIELD.
9827 */
9828 vmcs12_save_pending_event(vcpu, vmcs12);
9829 }
9830
9831 /*
9832 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9833 * preserved above and would only end up incorrectly in L1.
9834 */
9835 vcpu->arch.nmi_injected = false;
9836 kvm_clear_exception_queue(vcpu);
9837 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9838}
9839
9840/*
9841 * A part of what we need to when the nested L2 guest exits and we want to
9842 * run its L1 parent, is to reset L1's guest state to the host state specified
9843 * in vmcs12.
9844 * This function is to be called not only on normal nested exit, but also on
9845 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9846 * Failures During or After Loading Guest State").
9847 * This function should be called when the active VMCS is L1's (vmcs01).
9848 */
733568f9
JK		 9849static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9850 struct vmcs12 *vmcs12)
4704d0be 9851{
21feb4eb
ACL		 9852 struct kvm_segment seg;
9853
4704d0be
NHE		 9854 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9855 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9856 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9857 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9858 else
9859 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9860 vmx_set_efer(vcpu, vcpu->arch.efer);
9861
9862 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9863 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9864 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9865 /*
9866 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9867 * actually changed, because it depends on the current state of
9868 * fpu_active (which may have changed).
9869 * Note that vmx_set_cr0 refers to efer set above.
9870 */
9e3e4dbf 9871 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9872 /*
9873 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9874 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9875 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9876 */
9877 update_exception_bitmap(vcpu);
9878 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9879 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9880
9881 /*
9882 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9883 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9884 */
9885 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9886 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9887
29bf08f1 9888 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9889
4704d0be
NHE		 9890 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9891 kvm_mmu_reset_context(vcpu);
9892
feaf0c7d
GN		 9893 if (!enable_ept)
9894 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9895
4704d0be
NHE		 9896 if (enable_vpid) {
9897 /*
9898 * Trivially support vpid by letting L2s share their parent
9899 * L1's vpid. TODO: move to a more elaborate solution, giving
9900 * each L2 its own vpid and exposing the vpid feature to L1.
9901 */
9902 vmx_flush_tlb(vcpu);
9903 }
9904
9905
9906 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9907 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9908 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9909 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9910 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9911
36be0b9d
PB		 9912 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9913 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9914 vmcs_write64(GUEST_BNDCFGS, 0);
9915
44811c02 9916 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9917 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9918 vcpu->arch.pat = vmcs12->host_ia32_pat;
9919 }
4704d0be
NHE		 9920 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9921 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9922 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9923
21feb4eb
ACL		 9924 /* Set L1 segment info according to Intel SDM
9925 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9926 seg = (struct kvm_segment) {
9927 .base = 0,
9928 .limit = 0xFFFFFFFF,
9929 .selector = vmcs12->host_cs_selector,
9930 .type = 11,
9931 .present = 1,
9932 .s = 1,
9933 .g = 1
9934 };
9935 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9936 seg.l = 1;
9937 else
9938 seg.db = 1;
9939 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9940 seg = (struct kvm_segment) {
9941 .base = 0,
9942 .limit = 0xFFFFFFFF,
9943 .type = 3,
9944 .present = 1,
9945 .s = 1,
9946 .db = 1,
9947 .g = 1
9948 };
9949 seg.selector = vmcs12->host_ds_selector;
9950 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9951 seg.selector = vmcs12->host_es_selector;
9952 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9953 seg.selector = vmcs12->host_ss_selector;
9954 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9955 seg.selector = vmcs12->host_fs_selector;
9956 seg.base = vmcs12->host_fs_base;
9957 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9958 seg.selector = vmcs12->host_gs_selector;
9959 seg.base = vmcs12->host_gs_base;
9960 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9961 seg = (struct kvm_segment) {
205befd9 9962 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9963 .limit = 0x67,
9964 .selector = vmcs12->host_tr_selector,
9965 .type = 11,
9966 .present = 1
9967 };
9968 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9969
503cd0c5
JK		 9970 kvm_set_dr(vcpu, 7, 0x400);
9971 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9972
3af18d9c
WV		 9973 if (cpu_has_vmx_msr_bitmap())
9974 vmx_set_msr_bitmap(vcpu);
9975
ff651cb6
WV		 9976 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9977 vmcs12->vm_exit_msr_load_count))
9978 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9979}
9980
9981/*
9982 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9983 * and modify vmcs12 to make it see what it would expect to see there if
9984 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9985 */
533558bc
JK		 9986static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9987 u32 exit_intr_info,
9988 unsigned long exit_qualification)
4704d0be
NHE		 9989{
9990 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9991 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9992
5f3d5799
JK		 9993 /* trying to cancel vmlaunch/vmresume is a bug */
9994 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9995
4704d0be 9996 leave_guest_mode(vcpu);
533558bc
JK		 9997 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9998 exit_qualification);
4704d0be 9999
ff651cb6
WV		 10000 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10001 vmcs12->vm_exit_msr_store_count))
10002 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10003
f3380ca5
WL		 10004 vmx_load_vmcs01(vcpu);
10005
77b0f5d6
BD		 10006 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10007 && nested_exit_intr_ack_set(vcpu)) {
10008 int irq = kvm_cpu_get_interrupt(vcpu);
10009 WARN_ON(irq < 0);
10010 vmcs12->vm_exit_intr_info = irq |
10011 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10012 }
10013
542060ea
JK		 10014 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10015 vmcs12->exit_qualification,
10016 vmcs12->idt_vectoring_info_field,
10017 vmcs12->vm_exit_intr_info,
10018 vmcs12->vm_exit_intr_error_code,
10019 KVM_ISA_VMX);
4704d0be 10020
2961e876
GN		 10021 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10022 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10023 vmx_segment_cache_clear(vmx);
10024
4704d0be
NHE		 10025 /* if no vmcs02 cache requested, remove the one we used */
10026 if (VMCS02_POOL_SIZE == 0)
10027 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10028
10029 load_vmcs12_host_state(vcpu, vmcs12);
10030
27fc51b2 10031 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10032 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10033
10034 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10035 vmx->host_rsp = 0;
10036
10037 /* Unpin physical memory we referred to in vmcs02 */
10038 if (vmx->nested.apic_access_page) {
10039 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10040 vmx->nested.apic_access_page = NULL;
4704d0be 10041 }
a7c0b07d
WL		 10042 if (vmx->nested.virtual_apic_page) {
10043 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10044 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10045 }
705699a1
WV		 10046 if (vmx->nested.pi_desc_page) {
10047 kunmap(vmx->nested.pi_desc_page);
10048 nested_release_page(vmx->nested.pi_desc_page);
10049 vmx->nested.pi_desc_page = NULL;
10050 vmx->nested.pi_desc = NULL;
10051 }
4704d0be 10052
38b99173
TC		 10053 /*
10054 * We are now running in L2, mmu_notifier will force to reload the
10055 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10056 */
10057 kvm_vcpu_reload_apic_access_page(vcpu);
10058
4704d0be
NHE		 10059 /*
10060 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10061 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10062 * success or failure flag accordingly.
10063 */
10064 if (unlikely(vmx->fail)) {
10065 vmx->fail = 0;
10066 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10067 } else
10068 nested_vmx_succeed(vcpu);
012f83cb
AG		 10069 if (enable_shadow_vmcs)
10070 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10071
10072 /* in case we halted in L2 */
10073 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10074}
10075
42124925
JK		 10076/*
10077 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10078 */
10079static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10080{
10081 if (is_guest_mode(vcpu))
533558bc 10082 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10083 free_nested(to_vmx(vcpu));
10084}
10085
7c177938
NHE		 10086/*
10087 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10088 * 23.7 "VM-entry failures during or after loading guest state" (this also
10089 * lists the acceptable exit-reason and exit-qualification parameters).
10090 * It should only be called before L2 actually succeeded to run, and when
10091 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10092 */
10093static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10094 struct vmcs12 *vmcs12,
10095 u32 reason, unsigned long qualification)
10096{
10097 load_vmcs12_host_state(vcpu, vmcs12);
10098 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10099 vmcs12->exit_qualification = qualification;
10100 nested_vmx_succeed(vcpu);
012f83cb
AG		 10101 if (enable_shadow_vmcs)
10102 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10103}
10104
8a76d7f2
JR		 10105static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10106 struct x86_instruction_info *info,
10107 enum x86_intercept_stage stage)
10108{
10109 return X86EMUL_CONTINUE;
10110}
10111
48d89b92 10112static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10113{
b4a2d31d
RK		 10114 if (ple_gap)
10115 shrink_ple_window(vcpu);
ae97a3b8
RK		 10116}
10117
843e4330
KH		 10118static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10119 struct kvm_memory_slot *slot)
10120{
10121 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10122 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10123}
10124
10125static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10126 struct kvm_memory_slot *slot)
10127{
10128 kvm_mmu_slot_set_dirty(kvm, slot);
10129}
10130
10131static void vmx_flush_log_dirty(struct kvm *kvm)
10132{
10133 kvm_flush_pml_buffers(kvm);
10134}
10135
10136static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10137 struct kvm_memory_slot *memslot,
10138 gfn_t offset, unsigned long mask)
10139{
10140 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10141}
10142
cbdd1bea 10143static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10144 .cpu_has_kvm_support = cpu_has_kvm_support,
10145 .disabled_by_bios = vmx_disabled_by_bios,
10146 .hardware_setup = hardware_setup,
10147 .hardware_unsetup = hardware_unsetup,
002c7f7c 10148 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10149 .hardware_enable = hardware_enable,
10150 .hardware_disable = hardware_disable,
04547156 10151 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 10152
10153 .vcpu_create = vmx_create_vcpu,
10154 .vcpu_free = vmx_free_vcpu,
04d2cc77 10155 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10156
04d2cc77 10157 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10158 .vcpu_load = vmx_vcpu_load,
10159 .vcpu_put = vmx_vcpu_put,
10160
c8639010 10161 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10162 .get_msr = vmx_get_msr,
10163 .set_msr = vmx_set_msr,
10164 .get_segment_base = vmx_get_segment_base,
10165 .get_segment = vmx_get_segment,
10166 .set_segment = vmx_set_segment,
2e4d2653 10167 .get_cpl = vmx_get_cpl,
6aa8b732 10168 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10169 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10170 .decache_cr3 = vmx_decache_cr3,
25c4c276 10171 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10172 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10173 .set_cr3 = vmx_set_cr3,
10174 .set_cr4 = vmx_set_cr4,
6aa8b732 10175 .set_efer = vmx_set_efer,
6aa8b732
AK		 10176 .get_idt = vmx_get_idt,
10177 .set_idt = vmx_set_idt,
10178 .get_gdt = vmx_get_gdt,
10179 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10180 .get_dr6 = vmx_get_dr6,
10181 .set_dr6 = vmx_set_dr6,
020df079 10182 .set_dr7 = vmx_set_dr7,
81908bf4 10183 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10184 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10185 .get_rflags = vmx_get_rflags,
10186 .set_rflags = vmx_set_rflags,
02daab21 10187 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10188
10189 .tlb_flush = vmx_flush_tlb,
6aa8b732 10190
6aa8b732 10191 .run = vmx_vcpu_run,
6062d012 10192 .handle_exit = vmx_handle_exit,
6aa8b732 10193 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10194 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10195 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10196 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10197 .set_irq = vmx_inject_irq,
95ba8273 10198 .set_nmi = vmx_inject_nmi,
298101da 10199 .queue_exception = vmx_queue_exception,
b463a6f7 10200 .cancel_injection = vmx_cancel_injection,
78646121 10201 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10202 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10203 .get_nmi_mask = vmx_get_nmi_mask,
10204 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10205 .enable_nmi_window = enable_nmi_window,
10206 .enable_irq_window = enable_irq_window,
10207 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10208 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10209 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 10210 .vm_has_apicv = vmx_vm_has_apicv,
10211 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10212 .hwapic_irr_update = vmx_hwapic_irr_update,
10213 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10214 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10215 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10216
cbc94022 10217 .set_tss_addr = vmx_set_tss_addr,
67253af5 10218 .get_tdp_level = get_ept_level,
4b12f0de 10219 .get_mt_mask = vmx_get_mt_mask,
229456fc 10220
586f9607 10221 .get_exit_info = vmx_get_exit_info,
586f9607 10222
17cc3935 10223 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10224
10225 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10226
10227 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10228 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10229
10230 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10231
10232 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10233
4051b188 10234 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10235 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10236 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10237 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10238 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10239 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10240
10241 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10242
10243 .check_intercept = vmx_check_intercept,
a547c6db 10244 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10245 .mpx_supported = vmx_mpx_supported,
55412b2e 10246 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10247
10248 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10249
10250 .sched_in = vmx_sched_in,
843e4330
KH		 10251
10252 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10253 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10254 .flush_log_dirty = vmx_flush_log_dirty,
10255 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 10256};
10257
10258static int __init vmx_init(void)
10259{
34a1cd60
TC		 10260 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10261 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10262 if (r)
34a1cd60 10263 return r;
25c5f225 10264
8f536b76
ZY		 10265#ifdef CONFIG_KEXEC
10266 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10267 crash_vmclear_local_loaded_vmcss);
10268#endif
10269
fdef3ad1 10270 return 0;
6aa8b732
AK		 10271}
10272
10273static void __exit vmx_exit(void)
10274{
8f536b76 10275#ifdef CONFIG_KEXEC
3b63a43f 10276 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10277 synchronize_rcu();
10278#endif
10279
cb498ea2 10280 kvm_exit();
6aa8b732
AK		 10281}
10282
10283module_init(vmx_init)
10284module_exit(vmx_exit)
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