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KVM: fix sparse warning
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
6aa8b732 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
c7addb90
AK		 41static int bypass_guest_pf = 1;
42module_param(bypass_guest_pf, bool, 0);
43
2384d2b3
SY		 44static int enable_vpid = 1;
45module_param(enable_vpid, bool, 0);
46
4c9fc8ef
AK		 47static int flexpriority_enabled = 1;
48module_param(flexpriority_enabled, bool, 0);
49
1439442c 50static int enable_ept = 1;
d56f546d
SY		 51module_param(enable_ept, bool, 0);
52
04fa4d32
MG		 53static int emulate_invalid_guest_state = 0;
54module_param(emulate_invalid_guest_state, bool, 0);
55
a2fa3e9f
GH		 56struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60};
61
62struct vcpu_vmx {
fb3f0f51 63 struct kvm_vcpu vcpu;
543e4243 64 struct list_head local_vcpus_link;
313dbd49 65 unsigned long host_rsp;
a2fa3e9f 66 int launched;
29bd8a78 67 u8 fail;
1155f76a 68 u32 idt_vectoring_info;
a2fa3e9f
GH		 69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74#ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76#endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
51c6cf66 83 int guest_efer_loaded;
d77c26fc 84 } host_state;
9c8cba37
AK		 85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
2384d2b3 92 int vpid;
04fa4d32 93 bool emulation_required;
3b86cd99
JK		 94
95 /* Support for vnmi-less CPUs */
96 int soft_vnmi_blocked;
97 ktime_t entry_time;
98 s64 vnmi_blocked_time;
a2fa3e9f
GH		 99};
100
101static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
102{
fb3f0f51 103 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 104}
105
b7ebfb05 106static int init_rmode(struct kvm *kvm);
4e1096d2 107static u64 construct_eptp(unsigned long root_hpa);
75880a01 108
6aa8b732
AK		 109static DEFINE_PER_CPU(struct vmcs *, vmxarea);
110static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 111static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 112
fdef3ad1
HQ		 113static struct page *vmx_io_bitmap_a;
114static struct page *vmx_io_bitmap_b;
25c5f225 115static struct page *vmx_msr_bitmap;
fdef3ad1 116
2384d2b3
SY		 117static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
118static DEFINE_SPINLOCK(vmx_vpid_lock);
119
1c3d14fe 120static struct vmcs_config {
6aa8b732
AK		 121 int size;
122 int order;
123 u32 revision_id;
1c3d14fe
YS		 124 u32 pin_based_exec_ctrl;
125 u32 cpu_based_exec_ctrl;
f78e0e2e 126 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 127 u32 vmexit_ctrl;
128 u32 vmentry_ctrl;
129} vmcs_config;
6aa8b732 130
d56f546d
SY		 131struct vmx_capability {
132 u32 ept;
133 u32 vpid;
134} vmx_capability;
135
6aa8b732
AK		 136#define VMX_SEGMENT_FIELD(seg) \
137 [VCPU_SREG_##seg] = { \
138 .selector = GUEST_##seg##_SELECTOR, \
139 .base = GUEST_##seg##_BASE, \
140 .limit = GUEST_##seg##_LIMIT, \
141 .ar_bytes = GUEST_##seg##_AR_BYTES, \
142 }
143
144static struct kvm_vmx_segment_field {
145 unsigned selector;
146 unsigned base;
147 unsigned limit;
148 unsigned ar_bytes;
149} kvm_vmx_segment_fields[] = {
150 VMX_SEGMENT_FIELD(CS),
151 VMX_SEGMENT_FIELD(DS),
152 VMX_SEGMENT_FIELD(ES),
153 VMX_SEGMENT_FIELD(FS),
154 VMX_SEGMENT_FIELD(GS),
155 VMX_SEGMENT_FIELD(SS),
156 VMX_SEGMENT_FIELD(TR),
157 VMX_SEGMENT_FIELD(LDTR),
158};
159
4d56c8a7
AK		 160/*
161 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
162 * away by decrementing the array size.
163 */
6aa8b732 164static const u32 vmx_msr_index[] = {
05b3e0c2 165#ifdef CONFIG_X86_64
6aa8b732
AK		 166 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
167#endif
168 MSR_EFER, MSR_K6_STAR,
169};
9d8f549d 170#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 171
a2fa3e9f
GH		 172static void load_msrs(struct kvm_msr_entry *e, int n)
173{
174 int i;
175
176 for (i = 0; i < n; ++i)
177 wrmsrl(e[i].index, e[i].data);
178}
179
180static void save_msrs(struct kvm_msr_entry *e, int n)
181{
182 int i;
183
184 for (i = 0; i < n; ++i)
185 rdmsrl(e[i].index, e[i].data);
186}
187
6aa8b732
AK		 188static inline int is_page_fault(u32 intr_info)
189{
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
193}
194
2ab455cc
AL		 195static inline int is_no_device(u32 intr_info)
196{
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
198 INTR_INFO_VALID_MASK)) ==
199 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
200}
201
7aa81cc0
AL		 202static inline int is_invalid_opcode(u32 intr_info)
203{
204 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
205 INTR_INFO_VALID_MASK)) ==
206 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
207}
208
6aa8b732
AK		 209static inline int is_external_interrupt(u32 intr_info)
210{
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
212 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
213}
214
25c5f225
SY		 215static inline int cpu_has_vmx_msr_bitmap(void)
216{
217 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
218}
219
6e5d865c
YS		 220static inline int cpu_has_vmx_tpr_shadow(void)
221{
222 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
223}
224
225static inline int vm_need_tpr_shadow(struct kvm *kvm)
226{
227 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
228}
229
f78e0e2e
SY		 230static inline int cpu_has_secondary_exec_ctrls(void)
231{
232 return (vmcs_config.cpu_based_exec_ctrl &
233 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
234}
235
774ead3a 236static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 237{
4c9fc8ef
AK		 238 return flexpriority_enabled
239 && (vmcs_config.cpu_based_2nd_exec_ctrl &
240 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 241}
242
d56f546d
SY		 243static inline int cpu_has_vmx_invept_individual_addr(void)
244{
245 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
246}
247
248static inline int cpu_has_vmx_invept_context(void)
249{
250 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
251}
252
253static inline int cpu_has_vmx_invept_global(void)
254{
255 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
256}
257
258static inline int cpu_has_vmx_ept(void)
259{
260 return (vmcs_config.cpu_based_2nd_exec_ctrl &
261 SECONDARY_EXEC_ENABLE_EPT);
262}
263
264static inline int vm_need_ept(void)
265{
266 return (cpu_has_vmx_ept() && enable_ept);
267}
268
f78e0e2e
SY		 269static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
270{
271 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
272 (irqchip_in_kernel(kvm)));
273}
274
2384d2b3
SY		 275static inline int cpu_has_vmx_vpid(void)
276{
277 return (vmcs_config.cpu_based_2nd_exec_ctrl &
278 SECONDARY_EXEC_ENABLE_VPID);
279}
280
f08864b4
SY		 281static inline int cpu_has_virtual_nmis(void)
282{
283 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
284}
285
8b9cf98c 286static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 287{
288 int i;
289
a2fa3e9f
GH		 290 for (i = 0; i < vmx->nmsrs; ++i)
291 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 292 return i;
293 return -1;
294}
295
2384d2b3
SY		 296static inline void __invvpid(int ext, u16 vpid, gva_t gva)
297{
298 struct {
299 u64 vpid : 16;
300 u64 rsvd : 48;
301 u64 gva;
302 } operand = { vpid, 0, gva };
303
4ecac3fd 304 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 305 /* CF==1 or ZF==1 --> rc = -1 */
306 "; ja 1f ; ud2 ; 1:"
307 : : "a"(&operand), "c"(ext) : "cc", "memory");
308}
309
1439442c
SY		 310static inline void __invept(int ext, u64 eptp, gpa_t gpa)
311{
312 struct {
313 u64 eptp, gpa;
314 } operand = {eptp, gpa};
315
4ecac3fd 316 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 317 /* CF==1 or ZF==1 --> rc = -1 */
318 "; ja 1f ; ud2 ; 1:\n"
319 : : "a" (&operand), "c" (ext) : "cc", "memory");
320}
321
8b9cf98c 322static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 323{
324 int i;
325
8b9cf98c 326 i = __find_msr_index(vmx, msr);
a75beee6 327 if (i >= 0)
a2fa3e9f 328 return &vmx->guest_msrs[i];
8b6d44c7 329 return NULL;
7725f0ba
AK		 330}
331
6aa8b732
AK		 332static void vmcs_clear(struct vmcs *vmcs)
333{
334 u64 phys_addr = __pa(vmcs);
335 u8 error;
336
4ecac3fd 337 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 338 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
339 : "cc", "memory");
340 if (error)
341 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
342 vmcs, phys_addr);
343}
344
345static void __vcpu_clear(void *arg)
346{
8b9cf98c 347 struct vcpu_vmx *vmx = arg;
d3b2c338 348 int cpu = raw_smp_processor_id();
6aa8b732 349
8b9cf98c 350 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 351 vmcs_clear(vmx->vmcs);
352 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 353 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 354 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 355 list_del(&vmx->local_vcpus_link);
356 vmx->vcpu.cpu = -1;
357 vmx->launched = 0;
6aa8b732
AK		 358}
359
8b9cf98c 360static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 361{
eae5ecb5
AK		 362 if (vmx->vcpu.cpu == -1)
363 return;
8691e5a8 364 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 365}
366
2384d2b3
SY		 367static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
368{
369 if (vmx->vpid == 0)
370 return;
371
372 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
373}
374
1439442c
SY		 375static inline void ept_sync_global(void)
376{
377 if (cpu_has_vmx_invept_global())
378 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
379}
380
381static inline void ept_sync_context(u64 eptp)
382{
383 if (vm_need_ept()) {
384 if (cpu_has_vmx_invept_context())
385 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
386 else
387 ept_sync_global();
388 }
389}
390
391static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
392{
393 if (vm_need_ept()) {
394 if (cpu_has_vmx_invept_individual_addr())
395 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
396 eptp, gpa);
397 else
398 ept_sync_context(eptp);
399 }
400}
401
6aa8b732
AK		 402static unsigned long vmcs_readl(unsigned long field)
403{
404 unsigned long value;
405
4ecac3fd 406 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 407 : "=a"(value) : "d"(field) : "cc");
408 return value;
409}
410
411static u16 vmcs_read16(unsigned long field)
412{
413 return vmcs_readl(field);
414}
415
416static u32 vmcs_read32(unsigned long field)
417{
418 return vmcs_readl(field);
419}
420
421static u64 vmcs_read64(unsigned long field)
422{
05b3e0c2 423#ifdef CONFIG_X86_64
6aa8b732
AK		 424 return vmcs_readl(field);
425#else
426 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
427#endif
428}
429
e52de1b8
AK		 430static noinline void vmwrite_error(unsigned long field, unsigned long value)
431{
432 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
433 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
434 dump_stack();
435}
436
6aa8b732
AK		 437static void vmcs_writel(unsigned long field, unsigned long value)
438{
439 u8 error;
440
4ecac3fd 441 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 442 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 443 if (unlikely(error))
444 vmwrite_error(field, value);
6aa8b732
AK		 445}
446
447static void vmcs_write16(unsigned long field, u16 value)
448{
449 vmcs_writel(field, value);
450}
451
452static void vmcs_write32(unsigned long field, u32 value)
453{
454 vmcs_writel(field, value);
455}
456
457static void vmcs_write64(unsigned long field, u64 value)
458{
6aa8b732 459 vmcs_writel(field, value);
7682f2d0 460#ifndef CONFIG_X86_64
6aa8b732
AK		 461 asm volatile ("");
462 vmcs_writel(field+1, value >> 32);
463#endif
464}
465
2ab455cc
AL		 466static void vmcs_clear_bits(unsigned long field, u32 mask)
467{
468 vmcs_writel(field, vmcs_readl(field) & ~mask);
469}
470
471static void vmcs_set_bits(unsigned long field, u32 mask)
472{
473 vmcs_writel(field, vmcs_readl(field) | mask);
474}
475
abd3f2d6
AK		 476static void update_exception_bitmap(struct kvm_vcpu *vcpu)
477{
478 u32 eb;
479
7aa81cc0 480 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 481 if (!vcpu->fpu_active)
482 eb |= 1u << NM_VECTOR;
483 if (vcpu->guest_debug.enabled)
19bd8afd 484 eb |= 1u << DB_VECTOR;
ad312c7c 485 if (vcpu->arch.rmode.active)
abd3f2d6 486 eb = ~0;
1439442c
SY		 487 if (vm_need_ept())
488 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 489 vmcs_write32(EXCEPTION_BITMAP, eb);
490}
491
33ed6329
AK		 492static void reload_tss(void)
493{
33ed6329
AK		 494 /*
495 * VT restores TR but not its size. Useless.
496 */
497 struct descriptor_table gdt;
a5f61300 498 struct desc_struct *descs;
33ed6329 499
d6e88aec 500 kvm_get_gdt(&gdt);
33ed6329
AK		 501 descs = (void *)gdt.base;
502 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
503 load_TR_desc();
33ed6329
AK		 504}
505
8b9cf98c 506static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 507{
a2fa3e9f 508 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 509 u64 host_efer = vmx->host_msrs[efer_offset].data;
510 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
511 u64 ignore_bits;
512
513 if (efer_offset < 0)
514 return;
515 /*
516 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
517 * outside long mode
518 */
519 ignore_bits = EFER_NX | EFER_SCE;
520#ifdef CONFIG_X86_64
521 ignore_bits |= EFER_LMA | EFER_LME;
522 /* SCE is meaningful only in long mode on Intel */
523 if (guest_efer & EFER_LMA)
524 ignore_bits &= ~(u64)EFER_SCE;
525#endif
526 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
527 return;
2cc51560 528
51c6cf66
AK		 529 vmx->host_state.guest_efer_loaded = 1;
530 guest_efer &= ~ignore_bits;
531 guest_efer |= host_efer & ignore_bits;
532 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 533 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 534}
535
51c6cf66
AK		 536static void reload_host_efer(struct vcpu_vmx *vmx)
537{
538 if (vmx->host_state.guest_efer_loaded) {
539 vmx->host_state.guest_efer_loaded = 0;
540 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
541 }
542}
543
04d2cc77 544static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 545{
04d2cc77
AK		 546 struct vcpu_vmx *vmx = to_vmx(vcpu);
547
a2fa3e9f 548 if (vmx->host_state.loaded)
33ed6329
AK		 549 return;
550
a2fa3e9f 551 vmx->host_state.loaded = 1;
33ed6329
AK		 552 /*
553 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
554 * allow segment selectors with cpl > 0 or ti == 1.
555 */
d6e88aec 556 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 557 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 558 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 559 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 560 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 561 vmx->host_state.fs_reload_needed = 0;
562 } else {
33ed6329 563 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 564 vmx->host_state.fs_reload_needed = 1;
33ed6329 565 }
d6e88aec 566 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 567 if (!(vmx->host_state.gs_sel & 7))
568 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 569 else {
570 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 571 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 572 }
573
574#ifdef CONFIG_X86_64
575 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
576 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
577#else
a2fa3e9f
GH		 578 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
579 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 580#endif
707c0874
AK		 581
582#ifdef CONFIG_X86_64
d77c26fc 583 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 584 save_msrs(vmx->host_msrs +
585 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 586
707c0874 587#endif
a2fa3e9f 588 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 589 load_transition_efer(vmx);
33ed6329
AK		 590}
591
a9b21b62 592static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 593{
15ad7146 594 unsigned long flags;
33ed6329 595
a2fa3e9f 596 if (!vmx->host_state.loaded)
33ed6329
AK		 597 return;
598
e1beb1d3 599 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 600 vmx->host_state.loaded = 0;
152d3f2f 601 if (vmx->host_state.fs_reload_needed)
d6e88aec 602 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 603 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 604 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 605 /*
606 * If we have to reload gs, we must take care to
607 * preserve our gs base.
608 */
15ad7146 609 local_irq_save(flags);
d6e88aec 610 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 611#ifdef CONFIG_X86_64
612 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
613#endif
15ad7146 614 local_irq_restore(flags);
33ed6329 615 }
152d3f2f 616 reload_tss();
a2fa3e9f
GH		 617 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
618 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 619 reload_host_efer(vmx);
33ed6329
AK		 620}
621
a9b21b62
AK		 622static void vmx_load_host_state(struct vcpu_vmx *vmx)
623{
624 preempt_disable();
625 __vmx_load_host_state(vmx);
626 preempt_enable();
627}
628
6aa8b732
AK		 629/*
630 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
631 * vcpu mutex is already taken.
632 */
15ad7146 633static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 634{
a2fa3e9f
GH		 635 struct vcpu_vmx *vmx = to_vmx(vcpu);
636 u64 phys_addr = __pa(vmx->vmcs);
019960ae 637 u64 tsc_this, delta, new_offset;
6aa8b732 638
a3d7f85f 639 if (vcpu->cpu != cpu) {
8b9cf98c 640 vcpu_clear(vmx);
2f599714 641 kvm_migrate_timers(vcpu);
2384d2b3 642 vpid_sync_vcpu_all(vmx);
543e4243
AK		 643 local_irq_disable();
644 list_add(&vmx->local_vcpus_link,
645 &per_cpu(vcpus_on_cpu, cpu));
646 local_irq_enable();
a3d7f85f 647 }
6aa8b732 648
a2fa3e9f 649 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 650 u8 error;
651
a2fa3e9f 652 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 653 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 654 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
655 : "cc");
656 if (error)
657 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 658 vmx->vmcs, phys_addr);
6aa8b732
AK		 659 }
660
661 if (vcpu->cpu != cpu) {
662 struct descriptor_table dt;
663 unsigned long sysenter_esp;
664
665 vcpu->cpu = cpu;
666 /*
667 * Linux uses per-cpu TSS and GDT, so set these when switching
668 * processors.
669 */
d6e88aec
AK		 670 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
671 kvm_get_gdt(&dt);
6aa8b732
AK		 672 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
673
674 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
675 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 676
677 /*
678 * Make sure the time stamp counter is monotonous.
679 */
680 rdtscll(tsc_this);
019960ae
AK		 681 if (tsc_this < vcpu->arch.host_tsc) {
682 delta = vcpu->arch.host_tsc - tsc_this;
683 new_offset = vmcs_read64(TSC_OFFSET) + delta;
684 vmcs_write64(TSC_OFFSET, new_offset);
685 }
6aa8b732 686 }
6aa8b732
AK		 687}
688
689static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
690{
a9b21b62 691 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 692}
693
5fd86fcf
AK		 694static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
695{
696 if (vcpu->fpu_active)
697 return;
698 vcpu->fpu_active = 1;
707d92fa 699 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 700 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 701 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 702 update_exception_bitmap(vcpu);
703}
704
705static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
706{
707 if (!vcpu->fpu_active)
708 return;
709 vcpu->fpu_active = 0;
707d92fa 710 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 711 update_exception_bitmap(vcpu);
712}
713
6aa8b732
AK		 714static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
715{
716 return vmcs_readl(GUEST_RFLAGS);
717}
718
719static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
720{
ad312c7c 721 if (vcpu->arch.rmode.active)
053de044 722 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 723 vmcs_writel(GUEST_RFLAGS, rflags);
724}
725
726static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
727{
728 unsigned long rip;
729 u32 interruptibility;
730
5fdbf976 731 rip = kvm_rip_read(vcpu);
6aa8b732 732 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 733 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 734
735 /*
736 * We emulated an instruction, so temporary interrupt blocking
737 * should be removed, if set.
738 */
739 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
740 if (interruptibility & 3)
741 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
742 interruptibility & ~3);
ad312c7c 743 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 744}
745
298101da
AK		 746static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
747 bool has_error_code, u32 error_code)
748{
77ab6db0
JK		 749 struct vcpu_vmx *vmx = to_vmx(vcpu);
750
751 if (has_error_code)
752 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
753
754 if (vcpu->arch.rmode.active) {
755 vmx->rmode.irq.pending = true;
756 vmx->rmode.irq.vector = nr;
757 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
758 if (nr == BP_VECTOR)
759 vmx->rmode.irq.rip++;
760 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
761 nr | INTR_TYPE_SOFT_INTR
762 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
763 | INTR_INFO_VALID_MASK);
764 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
765 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
766 return;
767 }
768
298101da
AK		 769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
770 nr | INTR_TYPE_EXCEPTION
2e11384c 771 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da 772 | INTR_INFO_VALID_MASK);
298101da
AK		 773}
774
775static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
776{
35920a35 777 return false;
298101da
AK		 778}
779
a75beee6
ED		 780/*
781 * Swap MSR entry in host/guest MSR entry array.
782 */
54e11fa1 783#ifdef CONFIG_X86_64
8b9cf98c 784static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 785{
a2fa3e9f
GH		 786 struct kvm_msr_entry tmp;
787
788 tmp = vmx->guest_msrs[to];
789 vmx->guest_msrs[to] = vmx->guest_msrs[from];
790 vmx->guest_msrs[from] = tmp;
791 tmp = vmx->host_msrs[to];
792 vmx->host_msrs[to] = vmx->host_msrs[from];
793 vmx->host_msrs[from] = tmp;
a75beee6 794}
54e11fa1 795#endif
a75beee6 796
e38aea3e
AK		 797/*
798 * Set up the vmcs to automatically save and restore system
799 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
800 * mode, as fiddling with msrs is very expensive.
801 */
8b9cf98c 802static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 803{
2cc51560 804 int save_nmsrs;
e38aea3e 805
33f9c505 806 vmx_load_host_state(vmx);
a75beee6
ED		 807 save_nmsrs = 0;
808#ifdef CONFIG_X86_64
8b9cf98c 809 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 810 int index;
811
8b9cf98c 812 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 813 if (index >= 0)
8b9cf98c
RR		 814 move_msr_up(vmx, index, save_nmsrs++);
815 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 816 if (index >= 0)
8b9cf98c
RR		 817 move_msr_up(vmx, index, save_nmsrs++);
818 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 819 if (index >= 0)
8b9cf98c
RR		 820 move_msr_up(vmx, index, save_nmsrs++);
821 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 822 if (index >= 0)
8b9cf98c 823 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 824 /*
825 * MSR_K6_STAR is only needed on long mode guests, and only
826 * if efer.sce is enabled.
827 */
8b9cf98c 828 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 829 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 830 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 831 }
832#endif
a2fa3e9f 833 vmx->save_nmsrs = save_nmsrs;
e38aea3e 834
4d56c8a7 835#ifdef CONFIG_X86_64
a2fa3e9f 836 vmx->msr_offset_kernel_gs_base =
8b9cf98c 837 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 838#endif
8b9cf98c 839 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 840}
841
6aa8b732
AK		 842/*
843 * reads and returns guest's timestamp counter "register"
844 * guest_tsc = host_tsc + tsc_offset -- 21.3
845 */
846static u64 guest_read_tsc(void)
847{
848 u64 host_tsc, tsc_offset;
849
850 rdtscll(host_tsc);
851 tsc_offset = vmcs_read64(TSC_OFFSET);
852 return host_tsc + tsc_offset;
853}
854
855/*
856 * writes 'guest_tsc' into guest's timestamp counter "register"
857 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
858 */
859static void guest_write_tsc(u64 guest_tsc)
860{
861 u64 host_tsc;
862
863 rdtscll(host_tsc);
864 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
865}
866
6aa8b732
AK		 867/*
868 * Reads an msr value (of 'msr_index') into 'pdata'.
869 * Returns 0 on success, non-0 otherwise.
870 * Assumes vcpu_load() was already called.
871 */
872static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
873{
874 u64 data;
a2fa3e9f 875 struct kvm_msr_entry *msr;
6aa8b732
AK		 876
877 if (!pdata) {
878 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
879 return -EINVAL;
880 }
881
882 switch (msr_index) {
05b3e0c2 883#ifdef CONFIG_X86_64
6aa8b732
AK		 884 case MSR_FS_BASE:
885 data = vmcs_readl(GUEST_FS_BASE);
886 break;
887 case MSR_GS_BASE:
888 data = vmcs_readl(GUEST_GS_BASE);
889 break;
890 case MSR_EFER:
3bab1f5d 891 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 892#endif
893 case MSR_IA32_TIME_STAMP_COUNTER:
894 data = guest_read_tsc();
895 break;
896 case MSR_IA32_SYSENTER_CS:
897 data = vmcs_read32(GUEST_SYSENTER_CS);
898 break;
899 case MSR_IA32_SYSENTER_EIP:
f5b42c33 900 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 901 break;
902 case MSR_IA32_SYSENTER_ESP:
f5b42c33 903 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 904 break;
6aa8b732 905 default:
8b9cf98c 906 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 907 if (msr) {
908 data = msr->data;
909 break;
6aa8b732 910 }
3bab1f5d 911 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 912 }
913
914 *pdata = data;
915 return 0;
916}
917
918/*
919 * Writes msr value into into the appropriate "register".
920 * Returns 0 on success, non-0 otherwise.
921 * Assumes vcpu_load() was already called.
922 */
923static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
924{
a2fa3e9f
GH		 925 struct vcpu_vmx *vmx = to_vmx(vcpu);
926 struct kvm_msr_entry *msr;
2cc51560
ED		 927 int ret = 0;
928
6aa8b732 929 switch (msr_index) {
05b3e0c2 930#ifdef CONFIG_X86_64
3bab1f5d 931 case MSR_EFER:
a9b21b62 932 vmx_load_host_state(vmx);
2cc51560 933 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 934 break;
6aa8b732
AK		 935 case MSR_FS_BASE:
936 vmcs_writel(GUEST_FS_BASE, data);
937 break;
938 case MSR_GS_BASE:
939 vmcs_writel(GUEST_GS_BASE, data);
940 break;
941#endif
942 case MSR_IA32_SYSENTER_CS:
943 vmcs_write32(GUEST_SYSENTER_CS, data);
944 break;
945 case MSR_IA32_SYSENTER_EIP:
f5b42c33 946 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 947 break;
948 case MSR_IA32_SYSENTER_ESP:
f5b42c33 949 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 950 break;
d27d4aca 951 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732 952 guest_write_tsc(data);
efa67e0d
CL		 953 break;
954 case MSR_P6_PERFCTR0:
955 case MSR_P6_PERFCTR1:
956 case MSR_P6_EVNTSEL0:
957 case MSR_P6_EVNTSEL1:
958 /*
959 * Just discard all writes to the performance counters; this
960 * should keep both older linux and windows 64-bit guests
961 * happy
962 */
963 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
964
6aa8b732 965 break;
468d472f
SY		 966 case MSR_IA32_CR_PAT:
967 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
968 vmcs_write64(GUEST_IA32_PAT, data);
969 vcpu->arch.pat = data;
970 break;
971 }
972 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 973 default:
a9b21b62 974 vmx_load_host_state(vmx);
8b9cf98c 975 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 976 if (msr) {
977 msr->data = data;
978 break;
6aa8b732 979 }
2cc51560 980 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 981 }
982
2cc51560 983 return ret;
6aa8b732
AK		 984}
985
5fdbf976 986static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 987{
5fdbf976
MT		 988 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
989 switch (reg) {
990 case VCPU_REGS_RSP:
991 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
992 break;
993 case VCPU_REGS_RIP:
994 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
995 break;
996 default:
997 break;
998 }
6aa8b732
AK		 999}
1000
1001static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
1002{
1003 unsigned long dr7 = 0x400;
6aa8b732
AK		 1004 int old_singlestep;
1005
6aa8b732
AK		 1006 old_singlestep = vcpu->guest_debug.singlestep;
1007
1008 vcpu->guest_debug.enabled = dbg->enabled;
1009 if (vcpu->guest_debug.enabled) {
1010 int i;
1011
1012 dr7 |= 0x200; /* exact */
1013 for (i = 0; i < 4; ++i) {
1014 if (!dbg->breakpoints[i].enabled)
1015 continue;
1016 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1017 dr7 |= 2 << (i*2); /* global enable */
1018 dr7 |= 0 << (i*4+16); /* execution breakpoint */
1019 }
1020
6aa8b732 1021 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 1022 } else
6aa8b732 1023 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 1024
1025 if (old_singlestep && !vcpu->guest_debug.singlestep) {
1026 unsigned long flags;
1027
1028 flags = vmcs_readl(GUEST_RFLAGS);
1029 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1030 vmcs_writel(GUEST_RFLAGS, flags);
1031 }
1032
abd3f2d6 1033 update_exception_bitmap(vcpu);
6aa8b732
AK		 1034 vmcs_writel(GUEST_DR7, dr7);
1035
1036 return 0;
1037}
1038
2a8067f1
ED		 1039static int vmx_get_irq(struct kvm_vcpu *vcpu)
1040{
f7d9238f
AK		 1041 if (!vcpu->arch.interrupt.pending)
1042 return -1;
1043 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1044}
1045
6aa8b732
AK		 1046static __init int cpu_has_kvm_support(void)
1047{
6210e37b 1048 return cpu_has_vmx();
6aa8b732
AK		 1049}
1050
1051static __init int vmx_disabled_by_bios(void)
1052{
1053 u64 msr;
1054
1055 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1056 return (msr & (FEATURE_CONTROL_LOCKED |
1057 FEATURE_CONTROL_VMXON_ENABLED))
1058 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1059 /* locked but not enabled */
6aa8b732
AK		 1060}
1061
774c47f1 1062static void hardware_enable(void *garbage)
6aa8b732
AK		 1063{
1064 int cpu = raw_smp_processor_id();
1065 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1066 u64 old;
1067
543e4243 1068 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1069 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1070 if ((old & (FEATURE_CONTROL_LOCKED |
1071 FEATURE_CONTROL_VMXON_ENABLED))
1072 != (FEATURE_CONTROL_LOCKED |
1073 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1074 /* enable and lock */
62b3ffb8 1075 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1076 FEATURE_CONTROL_LOCKED |
1077 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1078 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1079 asm volatile (ASM_VMX_VMXON_RAX
1080 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1081 : "memory", "cc");
1082}
1083
543e4243
AK		 1084static void vmclear_local_vcpus(void)
1085{
1086 int cpu = raw_smp_processor_id();
1087 struct vcpu_vmx *vmx, *n;
1088
1089 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1090 local_vcpus_link)
1091 __vcpu_clear(vmx);
1092}
1093
710ff4a8
EH		 1094
1095/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1096 * tricks.
1097 */
1098static void kvm_cpu_vmxoff(void)
6aa8b732 1099{
4ecac3fd 1100 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1101 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1102}
1103
710ff4a8
EH		 1104static void hardware_disable(void *garbage)
1105{
1106 vmclear_local_vcpus();
1107 kvm_cpu_vmxoff();
1108}
1109
1c3d14fe 1110static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1111 u32 msr, u32 *result)
1c3d14fe
YS		 1112{
1113 u32 vmx_msr_low, vmx_msr_high;
1114 u32 ctl = ctl_min | ctl_opt;
1115
1116 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1117
1118 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1119 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1120
1121 /* Ensure minimum (required) set of control bits are supported. */
1122 if (ctl_min & ~ctl)
002c7f7c 1123 return -EIO;
1c3d14fe
YS		 1124
1125 *result = ctl;
1126 return 0;
1127}
1128
002c7f7c 1129static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1130{
1131 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1132 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1133 u32 _pin_based_exec_control = 0;
1134 u32 _cpu_based_exec_control = 0;
f78e0e2e 1135 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1136 u32 _vmexit_control = 0;
1137 u32 _vmentry_control = 0;
1138
1139 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1140 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1141 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1142 &_pin_based_exec_control) < 0)
002c7f7c 1143 return -EIO;
1c3d14fe
YS		 1144
1145 min = CPU_BASED_HLT_EXITING |
1146#ifdef CONFIG_X86_64
1147 CPU_BASED_CR8_LOAD_EXITING |
1148 CPU_BASED_CR8_STORE_EXITING |
1149#endif
d56f546d
SY		 1150 CPU_BASED_CR3_LOAD_EXITING |
1151 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1152 CPU_BASED_USE_IO_BITMAPS |
1153 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1154 CPU_BASED_USE_TSC_OFFSETING |
1155 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1156 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1157 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1158 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1159 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1160 &_cpu_based_exec_control) < 0)
002c7f7c 1161 return -EIO;
6e5d865c
YS		 1162#ifdef CONFIG_X86_64
1163 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1164 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1165 ~CPU_BASED_CR8_STORE_EXITING;
1166#endif
f78e0e2e 1167 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1168 min2 = 0;
1169 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1170 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1171 SECONDARY_EXEC_ENABLE_VPID |
1172 SECONDARY_EXEC_ENABLE_EPT;
1173 if (adjust_vmx_controls(min2, opt2,
1174 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1175 &_cpu_based_2nd_exec_control) < 0)
1176 return -EIO;
1177 }
1178#ifndef CONFIG_X86_64
1179 if (!(_cpu_based_2nd_exec_control &
1180 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1181 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1182#endif
d56f546d 1183 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1184 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1185 enabled */
d56f546d 1186 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1187 CPU_BASED_CR3_STORE_EXITING |
1188 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1189 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1190 &_cpu_based_exec_control) < 0)
1191 return -EIO;
1192 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1193 vmx_capability.ept, vmx_capability.vpid);
1194 }
1c3d14fe
YS		 1195
1196 min = 0;
1197#ifdef CONFIG_X86_64
1198 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1199#endif
468d472f 1200 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1201 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1202 &_vmexit_control) < 0)
002c7f7c 1203 return -EIO;
1c3d14fe 1204
468d472f
SY		 1205 min = 0;
1206 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1207 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1208 &_vmentry_control) < 0)
002c7f7c 1209 return -EIO;
6aa8b732 1210
c68876fd 1211 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1212
1213 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1214 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1215 return -EIO;
1c3d14fe
YS		 1216
1217#ifdef CONFIG_X86_64
1218 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1219 if (vmx_msr_high & (1u<<16))
002c7f7c 1220 return -EIO;
1c3d14fe
YS		 1221#endif
1222
1223 /* Require Write-Back (WB) memory type for VMCS accesses. */
1224 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1225 return -EIO;
1c3d14fe 1226
002c7f7c
YS		 1227 vmcs_conf->size = vmx_msr_high & 0x1fff;
1228 vmcs_conf->order = get_order(vmcs_config.size);
1229 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1230
002c7f7c
YS		 1231 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1232 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1233 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1234 vmcs_conf->vmexit_ctrl = _vmexit_control;
1235 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1236
1237 return 0;
c68876fd 1238}
6aa8b732
AK		 1239
1240static struct vmcs *alloc_vmcs_cpu(int cpu)
1241{
1242 int node = cpu_to_node(cpu);
1243 struct page *pages;
1244 struct vmcs *vmcs;
1245
1c3d14fe 1246 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1247 if (!pages)
1248 return NULL;
1249 vmcs = page_address(pages);
1c3d14fe
YS		 1250 memset(vmcs, 0, vmcs_config.size);
1251 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1252 return vmcs;
1253}
1254
1255static struct vmcs *alloc_vmcs(void)
1256{
d3b2c338 1257 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1258}
1259
1260static void free_vmcs(struct vmcs *vmcs)
1261{
1c3d14fe 1262 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1263}
1264
39959588 1265static void free_kvm_area(void)
6aa8b732
AK		 1266{
1267 int cpu;
1268
1269 for_each_online_cpu(cpu)
1270 free_vmcs(per_cpu(vmxarea, cpu));
1271}
1272
6aa8b732
AK		 1273static __init int alloc_kvm_area(void)
1274{
1275 int cpu;
1276
1277 for_each_online_cpu(cpu) {
1278 struct vmcs *vmcs;
1279
1280 vmcs = alloc_vmcs_cpu(cpu);
1281 if (!vmcs) {
1282 free_kvm_area();
1283 return -ENOMEM;
1284 }
1285
1286 per_cpu(vmxarea, cpu) = vmcs;
1287 }
1288 return 0;
1289}
1290
1291static __init int hardware_setup(void)
1292{
002c7f7c
YS		 1293 if (setup_vmcs_config(&vmcs_config) < 0)
1294 return -EIO;
50a37eb4
JR		 1295
1296 if (boot_cpu_has(X86_FEATURE_NX))
1297 kvm_enable_efer_bits(EFER_NX);
1298
6aa8b732
AK		 1299 return alloc_kvm_area();
1300}
1301
1302static __exit void hardware_unsetup(void)
1303{
1304 free_kvm_area();
1305}
1306
6aa8b732
AK		 1307static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1308{
1309 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1310
6af11b9e 1311 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1312 vmcs_write16(sf->selector, save->selector);
1313 vmcs_writel(sf->base, save->base);
1314 vmcs_write32(sf->limit, save->limit);
1315 vmcs_write32(sf->ar_bytes, save->ar);
1316 } else {
1317 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1318 << AR_DPL_SHIFT;
1319 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1320 }
1321}
1322
1323static void enter_pmode(struct kvm_vcpu *vcpu)
1324{
1325 unsigned long flags;
a89a8fb9 1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1327
a89a8fb9 1328 vmx->emulation_required = 1;
ad312c7c 1329 vcpu->arch.rmode.active = 0;
6aa8b732 1330
ad312c7c
ZX		 1331 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1332 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1333 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1334
1335 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1336 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1337 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1338 vmcs_writel(GUEST_RFLAGS, flags);
1339
66aee91a
RR		 1340 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1341 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1342
1343 update_exception_bitmap(vcpu);
1344
a89a8fb9
MG		 1345 if (emulate_invalid_guest_state)
1346 return;
1347
ad312c7c
ZX		 1348 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1349 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1350 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1351 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1352
1353 vmcs_write16(GUEST_SS_SELECTOR, 0);
1354 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1355
1356 vmcs_write16(GUEST_CS_SELECTOR,
1357 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1358 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1359}
1360
d77c26fc 1361static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1362{
bfc6d222 1363 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1364 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1365 kvm->memslots[0].npages - 3;
1366 return base_gfn << PAGE_SHIFT;
1367 }
bfc6d222 1368 return kvm->arch.tss_addr;
6aa8b732
AK		 1369}
1370
1371static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1372{
1373 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1374
1375 save->selector = vmcs_read16(sf->selector);
1376 save->base = vmcs_readl(sf->base);
1377 save->limit = vmcs_read32(sf->limit);
1378 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1379 vmcs_write16(sf->selector, save->base >> 4);
1380 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1381 vmcs_write32(sf->limit, 0xffff);
1382 vmcs_write32(sf->ar_bytes, 0xf3);
1383}
1384
1385static void enter_rmode(struct kvm_vcpu *vcpu)
1386{
1387 unsigned long flags;
a89a8fb9 1388 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1389
a89a8fb9 1390 vmx->emulation_required = 1;
ad312c7c 1391 vcpu->arch.rmode.active = 1;
6aa8b732 1392
ad312c7c 1393 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1394 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1395
ad312c7c 1396 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1397 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1398
ad312c7c 1399 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1400 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1401
1402 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1403 vcpu->arch.rmode.save_iopl
1404 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1405
053de044 1406 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1407
1408 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1409 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1410 update_exception_bitmap(vcpu);
1411
a89a8fb9
MG		 1412 if (emulate_invalid_guest_state)
1413 goto continue_rmode;
1414
6aa8b732
AK		 1415 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1416 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1417 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1418
1419 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1420 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1421 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1422 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1423 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1424
ad312c7c
ZX		 1425 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1426 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1427 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1428 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1429
a89a8fb9 1430continue_rmode:
8668a3c4 1431 kvm_mmu_reset_context(vcpu);
b7ebfb05 1432 init_rmode(vcpu->kvm);
6aa8b732
AK		 1433}
1434
05b3e0c2 1435#ifdef CONFIG_X86_64
6aa8b732
AK		 1436
1437static void enter_lmode(struct kvm_vcpu *vcpu)
1438{
1439 u32 guest_tr_ar;
1440
1441 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1442 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1443 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1444 __func__);
6aa8b732
AK		 1445 vmcs_write32(GUEST_TR_AR_BYTES,
1446 (guest_tr_ar & ~AR_TYPE_MASK)
1447 | AR_TYPE_BUSY_64_TSS);
1448 }
1449
ad312c7c 1450 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1451
8b9cf98c 1452 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1453 vmcs_write32(VM_ENTRY_CONTROLS,
1454 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1455 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1456}
1457
1458static void exit_lmode(struct kvm_vcpu *vcpu)
1459{
ad312c7c 1460 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1461
1462 vmcs_write32(VM_ENTRY_CONTROLS,
1463 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1464 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1465}
1466
1467#endif
1468
2384d2b3
SY		 1469static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1470{
1471 vpid_sync_vcpu_all(to_vmx(vcpu));
4e1096d2
SY		 1472 if (vm_need_ept())
1473 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1474}
1475
25c4c276 1476static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1477{
ad312c7c
ZX		 1478 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1479 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1480}
1481
1439442c
SY		 1482static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1483{
1484 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1485 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1486 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1487 return;
1488 }
1489 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1490 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1491 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1492 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1493 }
1494}
1495
1496static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1497
1498static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1499 unsigned long cr0,
1500 struct kvm_vcpu *vcpu)
1501{
1502 if (!(cr0 & X86_CR0_PG)) {
1503 /* From paging/starting to nonpaging */
1504 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1505 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1506 (CPU_BASED_CR3_LOAD_EXITING |
1507 CPU_BASED_CR3_STORE_EXITING));
1508 vcpu->arch.cr0 = cr0;
1509 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1510 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1511 *hw_cr0 &= ~X86_CR0_WP;
1512 } else if (!is_paging(vcpu)) {
1513 /* From nonpaging to paging */
1514 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1515 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1516 ~(CPU_BASED_CR3_LOAD_EXITING |
1517 CPU_BASED_CR3_STORE_EXITING));
1518 vcpu->arch.cr0 = cr0;
1519 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1520 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1521 *hw_cr0 &= ~X86_CR0_WP;
1522 }
1523}
1524
1525static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1526 struct kvm_vcpu *vcpu)
1527{
1528 if (!is_paging(vcpu)) {
1529 *hw_cr4 &= ~X86_CR4_PAE;
1530 *hw_cr4 |= X86_CR4_PSE;
1531 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1532 *hw_cr4 &= ~X86_CR4_PAE;
1533}
1534
6aa8b732
AK		 1535static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1536{
1439442c
SY		 1537 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1538 KVM_VM_CR0_ALWAYS_ON;
1539
5fd86fcf
AK		 1540 vmx_fpu_deactivate(vcpu);
1541
ad312c7c 1542 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1543 enter_pmode(vcpu);
1544
ad312c7c 1545 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1546 enter_rmode(vcpu);
1547
05b3e0c2 1548#ifdef CONFIG_X86_64
ad312c7c 1549 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1550 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1551 enter_lmode(vcpu);
707d92fa 1552 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1553 exit_lmode(vcpu);
1554 }
1555#endif
1556
1439442c
SY		 1557 if (vm_need_ept())
1558 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1559
6aa8b732 1560 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1561 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1562 vcpu->arch.cr0 = cr0;
5fd86fcf 1563
707d92fa 1564 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1565 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1566}
1567
1439442c
SY		 1568static u64 construct_eptp(unsigned long root_hpa)
1569{
1570 u64 eptp;
1571
1572 /* TODO write the value reading from MSR */
1573 eptp = VMX_EPT_DEFAULT_MT |
1574 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1575 eptp |= (root_hpa & PAGE_MASK);
1576
1577 return eptp;
1578}
1579
6aa8b732
AK		 1580static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1581{
1439442c
SY		 1582 unsigned long guest_cr3;
1583 u64 eptp;
1584
1585 guest_cr3 = cr3;
1586 if (vm_need_ept()) {
1587 eptp = construct_eptp(cr3);
1588 vmcs_write64(EPT_POINTER, eptp);
1589 ept_sync_context(eptp);
1590 ept_load_pdptrs(vcpu);
1591 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1592 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1593 }
1594
2384d2b3 1595 vmx_flush_tlb(vcpu);
1439442c 1596 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1597 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1598 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1599}
1600
1601static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1602{
1439442c
SY		 1603 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1604 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1605
ad312c7c 1606 vcpu->arch.cr4 = cr4;
1439442c
SY		 1607 if (vm_need_ept())
1608 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1609
1610 vmcs_writel(CR4_READ_SHADOW, cr4);
1611 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1612}
1613
6aa8b732
AK		 1614static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1615{
8b9cf98c
RR		 1616 struct vcpu_vmx *vmx = to_vmx(vcpu);
1617 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1618
ad312c7c 1619 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1620 if (!msr)
1621 return;
6aa8b732
AK		 1622 if (efer & EFER_LMA) {
1623 vmcs_write32(VM_ENTRY_CONTROLS,
1624 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1625 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1626 msr->data = efer;
1627
1628 } else {
1629 vmcs_write32(VM_ENTRY_CONTROLS,
1630 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1631 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1632
1633 msr->data = efer & ~EFER_LME;
1634 }
8b9cf98c 1635 setup_msrs(vmx);
6aa8b732
AK		 1636}
1637
6aa8b732
AK		 1638static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1639{
1640 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1641
1642 return vmcs_readl(sf->base);
1643}
1644
1645static void vmx_get_segment(struct kvm_vcpu *vcpu,
1646 struct kvm_segment *var, int seg)
1647{
1648 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649 u32 ar;
1650
1651 var->base = vmcs_readl(sf->base);
1652 var->limit = vmcs_read32(sf->limit);
1653 var->selector = vmcs_read16(sf->selector);
1654 ar = vmcs_read32(sf->ar_bytes);
1655 if (ar & AR_UNUSABLE_MASK)
1656 ar = 0;
1657 var->type = ar & 15;
1658 var->s = (ar >> 4) & 1;
1659 var->dpl = (ar >> 5) & 3;
1660 var->present = (ar >> 7) & 1;
1661 var->avl = (ar >> 12) & 1;
1662 var->l = (ar >> 13) & 1;
1663 var->db = (ar >> 14) & 1;
1664 var->g = (ar >> 15) & 1;
1665 var->unusable = (ar >> 16) & 1;
1666}
1667
2e4d2653
IE		 1668static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1669{
1670 struct kvm_segment kvm_seg;
1671
1672 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1673 return 0;
1674
1675 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1676 return 3;
1677
1678 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1679 return kvm_seg.selector & 3;
1680}
1681
653e3108 1682static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1683{
6aa8b732
AK		 1684 u32 ar;
1685
653e3108 1686 if (var->unusable)
6aa8b732
AK		 1687 ar = 1 << 16;
1688 else {
1689 ar = var->type & 15;
1690 ar |= (var->s & 1) << 4;
1691 ar |= (var->dpl & 3) << 5;
1692 ar |= (var->present & 1) << 7;
1693 ar |= (var->avl & 1) << 12;
1694 ar |= (var->l & 1) << 13;
1695 ar |= (var->db & 1) << 14;
1696 ar |= (var->g & 1) << 15;
1697 }
f7fbf1fd
UL		 1698 if (ar == 0) /* a 0 value means unusable */
1699 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1700
1701 return ar;
1702}
1703
1704static void vmx_set_segment(struct kvm_vcpu *vcpu,
1705 struct kvm_segment *var, int seg)
1706{
1707 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1708 u32 ar;
1709
ad312c7c
ZX		 1710 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1711 vcpu->arch.rmode.tr.selector = var->selector;
1712 vcpu->arch.rmode.tr.base = var->base;
1713 vcpu->arch.rmode.tr.limit = var->limit;
1714 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1715 return;
1716 }
1717 vmcs_writel(sf->base, var->base);
1718 vmcs_write32(sf->limit, var->limit);
1719 vmcs_write16(sf->selector, var->selector);
ad312c7c 1720 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1721 /*
1722 * Hack real-mode segments into vm86 compatibility.
1723 */
1724 if (var->base == 0xffff0000 && var->selector == 0xf000)
1725 vmcs_writel(sf->base, 0xf0000);
1726 ar = 0xf3;
1727 } else
1728 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1729 vmcs_write32(sf->ar_bytes, ar);
1730}
1731
6aa8b732
AK		 1732static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1733{
1734 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1735
1736 *db = (ar >> 14) & 1;
1737 *l = (ar >> 13) & 1;
1738}
1739
1740static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1741{
1742 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1743 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1744}
1745
1746static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1747{
1748 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1749 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1750}
1751
1752static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1753{
1754 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1755 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1756}
1757
1758static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1759{
1760 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1761 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1762}
1763
648dfaa7
MG		 1764static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1765{
1766 struct kvm_segment var;
1767 u32 ar;
1768
1769 vmx_get_segment(vcpu, &var, seg);
1770 ar = vmx_segment_access_rights(&var);
1771
1772 if (var.base != (var.selector << 4))
1773 return false;
1774 if (var.limit != 0xffff)
1775 return false;
1776 if (ar != 0xf3)
1777 return false;
1778
1779 return true;
1780}
1781
1782static bool code_segment_valid(struct kvm_vcpu *vcpu)
1783{
1784 struct kvm_segment cs;
1785 unsigned int cs_rpl;
1786
1787 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1788 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1789
1790 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1791 return false;
1792 if (!cs.s)
1793 return false;
1794 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1795 if (cs.dpl > cs_rpl)
1796 return false;
1797 } else if (cs.type & AR_TYPE_CODE_MASK) {
1798 if (cs.dpl != cs_rpl)
1799 return false;
1800 }
1801 if (!cs.present)
1802 return false;
1803
1804 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1805 return true;
1806}
1807
1808static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1809{
1810 struct kvm_segment ss;
1811 unsigned int ss_rpl;
1812
1813 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1814 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1815
1816 if ((ss.type != 3) || (ss.type != 7))
1817 return false;
1818 if (!ss.s)
1819 return false;
1820 if (ss.dpl != ss_rpl) /* DPL != RPL */
1821 return false;
1822 if (!ss.present)
1823 return false;
1824
1825 return true;
1826}
1827
1828static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1829{
1830 struct kvm_segment var;
1831 unsigned int rpl;
1832
1833 vmx_get_segment(vcpu, &var, seg);
1834 rpl = var.selector & SELECTOR_RPL_MASK;
1835
1836 if (!var.s)
1837 return false;
1838 if (!var.present)
1839 return false;
1840 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1841 if (var.dpl < rpl) /* DPL < RPL */
1842 return false;
1843 }
1844
1845 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1846 * rights flags
1847 */
1848 return true;
1849}
1850
1851static bool tr_valid(struct kvm_vcpu *vcpu)
1852{
1853 struct kvm_segment tr;
1854
1855 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1856
1857 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1858 return false;
1859 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1860 return false;
1861 if (!tr.present)
1862 return false;
1863
1864 return true;
1865}
1866
1867static bool ldtr_valid(struct kvm_vcpu *vcpu)
1868{
1869 struct kvm_segment ldtr;
1870
1871 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1872
1873 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1874 return false;
1875 if (ldtr.type != 2)
1876 return false;
1877 if (!ldtr.present)
1878 return false;
1879
1880 return true;
1881}
1882
1883static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1884{
1885 struct kvm_segment cs, ss;
1886
1887 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1888 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1889
1890 return ((cs.selector & SELECTOR_RPL_MASK) ==
1891 (ss.selector & SELECTOR_RPL_MASK));
1892}
1893
1894/*
1895 * Check if guest state is valid. Returns true if valid, false if
1896 * not.
1897 * We assume that registers are always usable
1898 */
1899static bool guest_state_valid(struct kvm_vcpu *vcpu)
1900{
1901 /* real mode guest state checks */
1902 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1903 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1904 return false;
1905 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1906 return false;
1907 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1908 return false;
1909 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1910 return false;
1911 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1912 return false;
1913 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1914 return false;
1915 } else {
1916 /* protected mode guest state checks */
1917 if (!cs_ss_rpl_check(vcpu))
1918 return false;
1919 if (!code_segment_valid(vcpu))
1920 return false;
1921 if (!stack_segment_valid(vcpu))
1922 return false;
1923 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1924 return false;
1925 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1926 return false;
1927 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1928 return false;
1929 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1930 return false;
1931 if (!tr_valid(vcpu))
1932 return false;
1933 if (!ldtr_valid(vcpu))
1934 return false;
1935 }
1936 /* TODO:
1937 * - Add checks on RIP
1938 * - Add checks on RFLAGS
1939 */
1940
1941 return true;
1942}
1943
d77c26fc 1944static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1945{
6aa8b732 1946 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1947 u16 data = 0;
10589a46 1948 int ret = 0;
195aefde 1949 int r;
6aa8b732 1950
195aefde
IE		 1951 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1952 if (r < 0)
10589a46 1953 goto out;
195aefde 1954 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1955 r = kvm_write_guest_page(kvm, fn++, &data,
1956 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1957 if (r < 0)
10589a46 1958 goto out;
195aefde
IE		 1959 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1960 if (r < 0)
10589a46 1961 goto out;
195aefde
IE		 1962 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1963 if (r < 0)
10589a46 1964 goto out;
195aefde 1965 data = ~0;
10589a46
MT		 1966 r = kvm_write_guest_page(kvm, fn, &data,
1967 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1968 sizeof(u8));
195aefde 1969 if (r < 0)
10589a46
MT		 1970 goto out;
1971
1972 ret = 1;
1973out:
10589a46 1974 return ret;
6aa8b732
AK		 1975}
1976
b7ebfb05
SY		 1977static int init_rmode_identity_map(struct kvm *kvm)
1978{
1979 int i, r, ret;
1980 pfn_t identity_map_pfn;
1981 u32 tmp;
1982
1983 if (!vm_need_ept())
1984 return 1;
1985 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1986 printk(KERN_ERR "EPT: identity-mapping pagetable "
1987 "haven't been allocated!\n");
1988 return 0;
1989 }
1990 if (likely(kvm->arch.ept_identity_pagetable_done))
1991 return 1;
1992 ret = 0;
1993 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1994 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1995 if (r < 0)
1996 goto out;
1997 /* Set up identity-mapping pagetable for EPT in real mode */
1998 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1999 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2000 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2001 r = kvm_write_guest_page(kvm, identity_map_pfn,
2002 &tmp, i * sizeof(tmp), sizeof(tmp));
2003 if (r < 0)
2004 goto out;
2005 }
2006 kvm->arch.ept_identity_pagetable_done = true;
2007 ret = 1;
2008out:
2009 return ret;
2010}
2011
6aa8b732
AK		 2012static void seg_setup(int seg)
2013{
2014 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2015
2016 vmcs_write16(sf->selector, 0);
2017 vmcs_writel(sf->base, 0);
2018 vmcs_write32(sf->limit, 0xffff);
a16b20da 2019 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2020}
2021
f78e0e2e
SY		 2022static int alloc_apic_access_page(struct kvm *kvm)
2023{
2024 struct kvm_userspace_memory_region kvm_userspace_mem;
2025 int r = 0;
2026
72dc67a6 2027 down_write(&kvm->slots_lock);
bfc6d222 2028 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2029 goto out;
2030 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2031 kvm_userspace_mem.flags = 0;
2032 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2033 kvm_userspace_mem.memory_size = PAGE_SIZE;
2034 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2035 if (r)
2036 goto out;
72dc67a6 2037
bfc6d222 2038 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2039out:
72dc67a6 2040 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2041 return r;
2042}
2043
b7ebfb05
SY		 2044static int alloc_identity_pagetable(struct kvm *kvm)
2045{
2046 struct kvm_userspace_memory_region kvm_userspace_mem;
2047 int r = 0;
2048
2049 down_write(&kvm->slots_lock);
2050 if (kvm->arch.ept_identity_pagetable)
2051 goto out;
2052 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2053 kvm_userspace_mem.flags = 0;
2054 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2055 kvm_userspace_mem.memory_size = PAGE_SIZE;
2056 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2057 if (r)
2058 goto out;
2059
b7ebfb05
SY		 2060 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2061 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2062out:
2063 up_write(&kvm->slots_lock);
2064 return r;
2065}
2066
2384d2b3
SY		 2067static void allocate_vpid(struct vcpu_vmx *vmx)
2068{
2069 int vpid;
2070
2071 vmx->vpid = 0;
2072 if (!enable_vpid || !cpu_has_vmx_vpid())
2073 return;
2074 spin_lock(&vmx_vpid_lock);
2075 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2076 if (vpid < VMX_NR_VPIDS) {
2077 vmx->vpid = vpid;
2078 __set_bit(vpid, vmx_vpid_bitmap);
2079 }
2080 spin_unlock(&vmx_vpid_lock);
2081}
2082
8b2cf73c 2083static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 2084{
2085 void *va;
2086
2087 if (!cpu_has_vmx_msr_bitmap())
2088 return;
2089
2090 /*
2091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2092 * have the write-low and read-high bitmap offsets the wrong way round.
2093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2094 */
2095 va = kmap(msr_bitmap);
2096 if (msr <= 0x1fff) {
2097 __clear_bit(msr, va + 0x000); /* read-low */
2098 __clear_bit(msr, va + 0x800); /* write-low */
2099 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2100 msr &= 0x1fff;
2101 __clear_bit(msr, va + 0x400); /* read-high */
2102 __clear_bit(msr, va + 0xc00); /* write-high */
2103 }
2104 kunmap(msr_bitmap);
2105}
2106
6aa8b732
AK		 2107/*
2108 * Sets up the vmcs for emulated real mode.
2109 */
8b9cf98c 2110static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2111{
468d472f 2112 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2113 u32 junk;
468d472f 2114 u64 host_pat;
6aa8b732
AK		 2115 unsigned long a;
2116 struct descriptor_table dt;
2117 int i;
cd2276a7 2118 unsigned long kvm_vmx_return;
6e5d865c 2119 u32 exec_control;
6aa8b732 2120
6aa8b732 2121 /* I/O */
fdef3ad1
HQ		 2122 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2123 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 2124
25c5f225
SY		 2125 if (cpu_has_vmx_msr_bitmap())
2126 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2127
6aa8b732
AK		 2128 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2129
6aa8b732 2130 /* Control */
1c3d14fe
YS		 2131 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2132 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2133
2134 exec_control = vmcs_config.cpu_based_exec_ctrl;
2135 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2136 exec_control &= ~CPU_BASED_TPR_SHADOW;
2137#ifdef CONFIG_X86_64
2138 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2139 CPU_BASED_CR8_LOAD_EXITING;
2140#endif
2141 }
d56f546d
SY		 2142 if (!vm_need_ept())
2143 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2144 CPU_BASED_CR3_LOAD_EXITING |
2145 CPU_BASED_INVLPG_EXITING;
6e5d865c 2146 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2147
83ff3b9d
SY		 2148 if (cpu_has_secondary_exec_ctrls()) {
2149 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2150 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2151 exec_control &=
2152 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2153 if (vmx->vpid == 0)
2154 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 2155 if (!vm_need_ept())
2156 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2157 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2158 }
f78e0e2e 2159
c7addb90
AK		 2160 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2161 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2162 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2163
2164 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2165 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2166 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2167
2168 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2169 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2170 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2171 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2172 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2173 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2174#ifdef CONFIG_X86_64
6aa8b732
AK		 2175 rdmsrl(MSR_FS_BASE, a);
2176 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2177 rdmsrl(MSR_GS_BASE, a);
2178 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2179#else
2180 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2181 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2182#endif
2183
2184 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2185
d6e88aec 2186 kvm_get_idt(&dt);
6aa8b732
AK		 2187 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2188
d77c26fc 2189 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2190 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2191 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2192 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2193 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2194
2195 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2196 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2197 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2198 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2199 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2200 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2201
468d472f
SY		 2202 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2203 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2204 host_pat = msr_low | ((u64) msr_high << 32);
2205 vmcs_write64(HOST_IA32_PAT, host_pat);
2206 }
2207 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2208 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2209 host_pat = msr_low | ((u64) msr_high << 32);
2210 /* Write the default value follow host pat */
2211 vmcs_write64(GUEST_IA32_PAT, host_pat);
2212 /* Keep arch.pat sync with GUEST_IA32_PAT */
2213 vmx->vcpu.arch.pat = host_pat;
2214 }
2215
6aa8b732
AK		 2216 for (i = 0; i < NR_VMX_MSR; ++i) {
2217 u32 index = vmx_msr_index[i];
2218 u32 data_low, data_high;
2219 u64 data;
a2fa3e9f 2220 int j = vmx->nmsrs;
6aa8b732
AK		 2221
2222 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2223 continue;
432bd6cb
AK		 2224 if (wrmsr_safe(index, data_low, data_high) < 0)
2225 continue;
6aa8b732 2226 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2227 vmx->host_msrs[j].index = index;
2228 vmx->host_msrs[j].reserved = 0;
2229 vmx->host_msrs[j].data = data;
2230 vmx->guest_msrs[j] = vmx->host_msrs[j];
2231 ++vmx->nmsrs;
6aa8b732 2232 }
6aa8b732 2233
1c3d14fe 2234 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2235
2236 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2237 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2238
e00c8cf2
AK		 2239 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2240 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2241
f78e0e2e 2242
e00c8cf2
AK		 2243 return 0;
2244}
2245
b7ebfb05
SY		 2246static int init_rmode(struct kvm *kvm)
2247{
2248 if (!init_rmode_tss(kvm))
2249 return 0;
2250 if (!init_rmode_identity_map(kvm))
2251 return 0;
2252 return 1;
2253}
2254
e00c8cf2
AK		 2255static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2256{
2257 struct vcpu_vmx *vmx = to_vmx(vcpu);
2258 u64 msr;
2259 int ret;
2260
5fdbf976 2261 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2262 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2263 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2264 ret = -ENOMEM;
2265 goto out;
2266 }
2267
ad312c7c 2268 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2269
3b86cd99
JK		 2270 vmx->soft_vnmi_blocked = 0;
2271
ad312c7c 2272 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2273 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2274 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2275 if (vmx->vcpu.vcpu_id == 0)
2276 msr |= MSR_IA32_APICBASE_BSP;
2277 kvm_set_apic_base(&vmx->vcpu, msr);
2278
2279 fx_init(&vmx->vcpu);
2280
5706be0d 2281 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2282 /*
2283 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2284 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2285 */
2286 if (vmx->vcpu.vcpu_id == 0) {
2287 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2288 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2289 } else {
ad312c7c
ZX		 2290 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2291 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2292 }
e00c8cf2
AK		 2293
2294 seg_setup(VCPU_SREG_DS);
2295 seg_setup(VCPU_SREG_ES);
2296 seg_setup(VCPU_SREG_FS);
2297 seg_setup(VCPU_SREG_GS);
2298 seg_setup(VCPU_SREG_SS);
2299
2300 vmcs_write16(GUEST_TR_SELECTOR, 0);
2301 vmcs_writel(GUEST_TR_BASE, 0);
2302 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2303 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2304
2305 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2306 vmcs_writel(GUEST_LDTR_BASE, 0);
2307 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2308 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2309
2310 vmcs_write32(GUEST_SYSENTER_CS, 0);
2311 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2312 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2313
2314 vmcs_writel(GUEST_RFLAGS, 0x02);
2315 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2316 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2317 else
5fdbf976
MT		 2318 kvm_rip_write(vcpu, 0);
2319 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2
AK		 2320
2321 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2322 vmcs_writel(GUEST_DR7, 0x400);
2323
2324 vmcs_writel(GUEST_GDTR_BASE, 0);
2325 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2326
2327 vmcs_writel(GUEST_IDTR_BASE, 0);
2328 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2329
2330 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2331 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2332 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2333
2334 guest_write_tsc(0);
2335
2336 /* Special registers */
2337 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2338
2339 setup_msrs(vmx);
2340
6aa8b732
AK		 2341 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2342
f78e0e2e
SY		 2343 if (cpu_has_vmx_tpr_shadow()) {
2344 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2345 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2346 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2347 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2348 vmcs_write32(TPR_THRESHOLD, 0);
2349 }
2350
2351 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2352 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2353 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2354
2384d2b3
SY		 2355 if (vmx->vpid != 0)
2356 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2357
ad312c7c
ZX		 2358 vmx->vcpu.arch.cr0 = 0x60000010;
2359 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2360 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2361 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2362 vmx_fpu_activate(&vmx->vcpu);
2363 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2364
2384d2b3
SY		 2365 vpid_sync_vcpu_all(vmx);
2366
3200f405 2367 ret = 0;
6aa8b732 2368
a89a8fb9
MG		 2369 /* HACK: Don't enable emulation on guest boot/reset */
2370 vmx->emulation_required = 0;
2371
6aa8b732 2372out:
3200f405 2373 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2374 return ret;
2375}
2376
3b86cd99
JK		 2377static void enable_irq_window(struct kvm_vcpu *vcpu)
2378{
2379 u32 cpu_based_vm_exec_control;
2380
2381 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2382 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2383 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2384}
2385
2386static void enable_nmi_window(struct kvm_vcpu *vcpu)
2387{
2388 u32 cpu_based_vm_exec_control;
2389
2390 if (!cpu_has_virtual_nmis()) {
2391 enable_irq_window(vcpu);
2392 return;
2393 }
2394
2395 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2396 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2398}
2399
85f455f7
ED		 2400static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2401{
9c8cba37
AK		 2402 struct vcpu_vmx *vmx = to_vmx(vcpu);
2403
2714d1d3
FEL		 2404 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2405
fa89a817 2406 ++vcpu->stat.irq_injections;
ad312c7c 2407 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2408 vmx->rmode.irq.pending = true;
2409 vmx->rmode.irq.vector = irq;
5fdbf976 2410 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2411 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2412 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2413 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2414 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2415 return;
2416 }
2417 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2418 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2419}
2420
f08864b4
SY		 2421static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2422{
66a5a347
JK		 2423 struct vcpu_vmx *vmx = to_vmx(vcpu);
2424
3b86cd99
JK		 2425 if (!cpu_has_virtual_nmis()) {
2426 /*
2427 * Tracking the NMI-blocked state in software is built upon
2428 * finding the next open IRQ window. This, in turn, depends on
2429 * well-behaving guests: They have to keep IRQs disabled at
2430 * least as long as the NMI handler runs. Otherwise we may
2431 * cause NMI nesting, maybe breaking the guest. But as this is
2432 * highly unlikely, we can live with the residual risk.
2433 */
2434 vmx->soft_vnmi_blocked = 1;
2435 vmx->vnmi_blocked_time = 0;
2436 }
2437
487b391d 2438 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2439 if (vcpu->arch.rmode.active) {
2440 vmx->rmode.irq.pending = true;
2441 vmx->rmode.irq.vector = NMI_VECTOR;
2442 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2445 INTR_INFO_VALID_MASK);
2446 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2447 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2448 return;
2449 }
f08864b4
SY		 2450 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2451 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2452}
2453
33f089ca
JK		 2454static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2455{
2456 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2457
2458 vcpu->arch.nmi_window_open =
2459 !(guest_intr & (GUEST_INTR_STATE_STI |
2460 GUEST_INTR_STATE_MOV_SS |
2461 GUEST_INTR_STATE_NMI));
3b86cd99
JK		 2462 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2463 vcpu->arch.nmi_window_open = 0;
33f089ca
JK		 2464
2465 vcpu->arch.interrupt_window_open =
2466 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2467 !(guest_intr & (GUEST_INTR_STATE_STI |
2468 GUEST_INTR_STATE_MOV_SS)));
2469}
2470
6aa8b732
AK		 2471static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2472{
ad312c7c
ZX		 2473 int word_index = __ffs(vcpu->arch.irq_summary);
2474 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2475 int irq = word_index * BITS_PER_LONG + bit_index;
2476
ad312c7c
ZX		 2477 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2478 if (!vcpu->arch.irq_pending[word_index])
2479 clear_bit(word_index, &vcpu->arch.irq_summary);
ecfc79c7 2480 kvm_queue_interrupt(vcpu, irq);
6aa8b732
AK		 2481}
2482
f460ee43
JK		 2483static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2484 struct kvm_run *kvm_run)
2485{
2486 vmx_update_window_states(vcpu);
2487
3b86cd99
JK		 2488 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2489 if (vcpu->arch.nmi_window_open) {
2490 vcpu->arch.nmi_pending = false;
2491 vcpu->arch.nmi_injected = true;
2492 } else {
2493 enable_nmi_window(vcpu);
487b391d
JK		 2494 return;
2495 }
3b86cd99
JK		 2496 }
2497 if (vcpu->arch.nmi_injected) {
2498 vmx_inject_nmi(vcpu);
2499 if (vcpu->arch.nmi_pending || kvm_run->request_nmi_window)
487b391d 2500 enable_nmi_window(vcpu);
3b86cd99
JK		 2501 else if (vcpu->arch.irq_summary
2502 || kvm_run->request_interrupt_window)
2503 enable_irq_window(vcpu);
2504 return;
487b391d 2505 }
3b86cd99
JK		 2506 if (!vcpu->arch.nmi_window_open || kvm_run->request_nmi_window)
2507 enable_nmi_window(vcpu);
487b391d 2508
f460ee43
JK		 2509 if (vcpu->arch.interrupt_window_open) {
2510 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2511 kvm_do_inject_irq(vcpu);
2512
2513 if (vcpu->arch.interrupt.pending)
2514 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2515 }
ad312c7c
ZX		 2516 if (!vcpu->arch.interrupt_window_open &&
2517 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
f460ee43 2518 enable_irq_window(vcpu);
6aa8b732
AK		 2519}
2520
cbc94022
IE		 2521static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2522{
2523 int ret;
2524 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2525 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2526 .guest_phys_addr = addr,
2527 .memory_size = PAGE_SIZE * 3,
2528 .flags = 0,
2529 };
2530
2531 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2532 if (ret)
2533 return ret;
bfc6d222 2534 kvm->arch.tss_addr = addr;
cbc94022
IE		 2535 return 0;
2536}
2537
6aa8b732
AK		 2538static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2539{
2540 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2541
2542 set_debugreg(dbg->bp[0], 0);
2543 set_debugreg(dbg->bp[1], 1);
2544 set_debugreg(dbg->bp[2], 2);
2545 set_debugreg(dbg->bp[3], 3);
2546
2547 if (dbg->singlestep) {
2548 unsigned long flags;
2549
2550 flags = vmcs_readl(GUEST_RFLAGS);
2551 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2552 vmcs_writel(GUEST_RFLAGS, flags);
2553 }
2554}
2555
2556static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2557 int vec, u32 err_code)
2558{
b3f37707
NK		 2559 /*
2560 * Instruction with address size override prefix opcode 0x67
2561 * Cause the #SS fault with 0 error code in VM86 mode.
2562 */
2563 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2564 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2565 return 1;
77ab6db0
JK		 2566 /*
2567 * Forward all other exceptions that are valid in real mode.
2568 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2569 * the required debugging infrastructure rework.
2570 */
2571 switch (vec) {
2572 case DE_VECTOR:
2573 case DB_VECTOR:
2574 case BP_VECTOR:
2575 case OF_VECTOR:
2576 case BR_VECTOR:
2577 case UD_VECTOR:
2578 case DF_VECTOR:
2579 case SS_VECTOR:
2580 case GP_VECTOR:
2581 case MF_VECTOR:
2582 kvm_queue_exception(vcpu, vec);
2583 return 1;
2584 }
6aa8b732
AK		 2585 return 0;
2586}
2587
2588static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2589{
1155f76a 2590 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2591 u32 intr_info, error_code;
2592 unsigned long cr2, rip;
2593 u32 vect_info;
2594 enum emulation_result er;
2595
1155f76a 2596 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2597 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2598
2599 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2600 !is_page_fault(intr_info))
6aa8b732 2601 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2602 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2603
85f455f7 2604 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2605 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2606 set_bit(irq, vcpu->arch.irq_pending);
2607 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2608 }
2609
e4a41889 2610 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2611 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2612
2613 if (is_no_device(intr_info)) {
5fd86fcf 2614 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2615 return 1;
2616 }
2617
7aa81cc0 2618 if (is_invalid_opcode(intr_info)) {
571008da 2619 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2620 if (er != EMULATE_DONE)
7ee5d940 2621 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2622 return 1;
2623 }
2624
6aa8b732 2625 error_code = 0;
5fdbf976 2626 rip = kvm_rip_read(vcpu);
2e11384c 2627 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2628 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2629 if (is_page_fault(intr_info)) {
1439442c
SY		 2630 /* EPT won't cause page fault directly */
2631 if (vm_need_ept())
2632 BUG();
6aa8b732 2633 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2634 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2635 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2636 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2637 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2638 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2639 }
2640
ad312c7c 2641 if (vcpu->arch.rmode.active &&
6aa8b732 2642 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2643 error_code)) {
ad312c7c
ZX		 2644 if (vcpu->arch.halt_request) {
2645 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2646 return kvm_emulate_halt(vcpu);
2647 }
6aa8b732 2648 return 1;
72d6e5a0 2649 }
6aa8b732 2650
d77c26fc
MD		 2651 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2652 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2653 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2654 return 0;
2655 }
2656 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2657 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2658 kvm_run->ex.error_code = error_code;
2659 return 0;
2660}
2661
2662static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2663 struct kvm_run *kvm_run)
2664{
1165f5fe 2665 ++vcpu->stat.irq_exits;
2714d1d3 2666 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2667 return 1;
2668}
2669
988ad74f
AK		 2670static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2671{
2672 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2673 return 0;
2674}
6aa8b732 2675
6aa8b732
AK		 2676static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2677{
bfdaab09 2678 unsigned long exit_qualification;
039576c0
AK		 2679 int size, down, in, string, rep;
2680 unsigned port;
6aa8b732 2681
1165f5fe 2682 ++vcpu->stat.io_exits;
bfdaab09 2683 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2684 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2685
2686 if (string) {
3427318f
LV		 2687 if (emulate_instruction(vcpu,
2688 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2689 return 0;
2690 return 1;
2691 }
2692
2693 size = (exit_qualification & 7) + 1;
2694 in = (exit_qualification & 8) != 0;
039576c0 2695 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2696 rep = (exit_qualification & 32) != 0;
2697 port = exit_qualification >> 16;
e70669ab 2698
e93f36bc 2699 skip_emulated_instruction(vcpu);
3090dd73 2700 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2701}
2702
102d8325
IM		 2703static void
2704vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2705{
2706 /*
2707 * Patch in the VMCALL instruction:
2708 */
2709 hypercall[0] = 0x0f;
2710 hypercall[1] = 0x01;
2711 hypercall[2] = 0xc1;
102d8325
IM		 2712}
2713
6aa8b732
AK		 2714static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2715{
bfdaab09 2716 unsigned long exit_qualification;
6aa8b732
AK		 2717 int cr;
2718 int reg;
2719
bfdaab09 2720 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2721 cr = exit_qualification & 15;
2722 reg = (exit_qualification >> 8) & 15;
2723 switch ((exit_qualification >> 4) & 3) {
2724 case 0: /* mov to cr */
5fdbf976
MT		 2725 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2726 (u32)kvm_register_read(vcpu, reg),
2727 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2728 handler);
6aa8b732
AK		 2729 switch (cr) {
2730 case 0:
5fdbf976 2731 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2732 skip_emulated_instruction(vcpu);
2733 return 1;
2734 case 3:
5fdbf976 2735 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2736 skip_emulated_instruction(vcpu);
2737 return 1;
2738 case 4:
5fdbf976 2739 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2740 skip_emulated_instruction(vcpu);
2741 return 1;
2742 case 8:
5fdbf976 2743 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
6aa8b732 2744 skip_emulated_instruction(vcpu);
e5314067
AK		 2745 if (irqchip_in_kernel(vcpu->kvm))
2746 return 1;
253abdee
YS		 2747 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2748 return 0;
6aa8b732
AK		 2749 };
2750 break;
25c4c276 2751 case 2: /* clts */
5fd86fcf 2752 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2753 vcpu->arch.cr0 &= ~X86_CR0_TS;
2754 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2755 vmx_fpu_activate(vcpu);
2714d1d3 2756 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2757 skip_emulated_instruction(vcpu);
2758 return 1;
6aa8b732
AK		 2759 case 1: /*mov from cr*/
2760 switch (cr) {
2761 case 3:
5fdbf976 2762 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2763 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2764 (u32)kvm_register_read(vcpu, reg),
2765 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2766 handler);
6aa8b732
AK		 2767 skip_emulated_instruction(vcpu);
2768 return 1;
2769 case 8:
5fdbf976 2770 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2771 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2772 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2773 skip_emulated_instruction(vcpu);
2774 return 1;
2775 }
2776 break;
2777 case 3: /* lmsw */
2d3ad1f4 2778 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2779
2780 skip_emulated_instruction(vcpu);
2781 return 1;
2782 default:
2783 break;
2784 }
2785 kvm_run->exit_reason = 0;
f0242478 2786 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2787 (int)(exit_qualification >> 4) & 3, cr);
2788 return 0;
2789}
2790
2791static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2792{
bfdaab09 2793 unsigned long exit_qualification;
6aa8b732
AK		 2794 unsigned long val;
2795 int dr, reg;
2796
2797 /*
2798 * FIXME: this code assumes the host is debugging the guest.
2799 * need to deal with guest debugging itself too.
2800 */
bfdaab09 2801 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2802 dr = exit_qualification & 7;
2803 reg = (exit_qualification >> 8) & 15;
6aa8b732
AK		 2804 if (exit_qualification & 16) {
2805 /* mov from dr */
2806 switch (dr) {
2807 case 6:
2808 val = 0xffff0ff0;
2809 break;
2810 case 7:
2811 val = 0x400;
2812 break;
2813 default:
2814 val = 0;
2815 }
5fdbf976 2816 kvm_register_write(vcpu, reg, val);
2714d1d3 2817 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2818 } else {
2819 /* mov to dr */
2820 }
6aa8b732
AK		 2821 skip_emulated_instruction(vcpu);
2822 return 1;
2823}
2824
2825static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2826{
06465c5a
AK		 2827 kvm_emulate_cpuid(vcpu);
2828 return 1;
6aa8b732
AK		 2829}
2830
2831static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2832{
ad312c7c 2833 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2834 u64 data;
2835
2836 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2837 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2838 return 1;
2839 }
2840
2714d1d3
FEL		 2841 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2842 handler);
2843
6aa8b732 2844 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2845 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2846 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2847 skip_emulated_instruction(vcpu);
2848 return 1;
2849}
2850
2851static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2852{
ad312c7c
ZX		 2853 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2854 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2855 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2856
2714d1d3
FEL		 2857 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2858 handler);
2859
6aa8b732 2860 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2861 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2862 return 1;
2863 }
2864
2865 skip_emulated_instruction(vcpu);
2866 return 1;
2867}
2868
6e5d865c
YS		 2869static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2870 struct kvm_run *kvm_run)
2871{
2872 return 1;
2873}
2874
6aa8b732
AK		 2875static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2876 struct kvm_run *kvm_run)
2877{
85f455f7
ED		 2878 u32 cpu_based_vm_exec_control;
2879
2880 /* clear pending irq */
2881 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2882 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2884
2885 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2886 ++vcpu->stat.irq_window_exits;
2714d1d3 2887
c1150d8c
DL		 2888 /*
2889 * If the user space waits to inject interrupts, exit as soon as
2890 * possible
2891 */
2892 if (kvm_run->request_interrupt_window &&
ad312c7c 2893 !vcpu->arch.irq_summary) {
c1150d8c 2894 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2895 return 0;
2896 }
6aa8b732
AK		 2897 return 1;
2898}
2899
2900static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2901{
2902 skip_emulated_instruction(vcpu);
d3bef15f 2903 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2904}
2905
c21415e8
IM		 2906static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2907{
510043da 2908 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2909 kvm_emulate_hypercall(vcpu);
2910 return 1;
c21415e8
IM		 2911}
2912
a7052897
MT		 2913static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2914{
2915 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2916
2917 kvm_mmu_invlpg(vcpu, exit_qualification);
2918 skip_emulated_instruction(vcpu);
2919 return 1;
2920}
2921
e5edaa01
ED		 2922static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2923{
2924 skip_emulated_instruction(vcpu);
2925 /* TODO: Add support for VT-d/pass-through device */
2926 return 1;
2927}
2928
f78e0e2e
SY		 2929static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2930{
2931 u64 exit_qualification;
2932 enum emulation_result er;
2933 unsigned long offset;
2934
2935 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2936 offset = exit_qualification & 0xffful;
2937
2938 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2939
2940 if (er != EMULATE_DONE) {
2941 printk(KERN_ERR
2942 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2943 offset);
2944 return -ENOTSUPP;
2945 }
2946 return 1;
2947}
2948
37817f29
IE		 2949static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2950{
60637aac 2951 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 2952 unsigned long exit_qualification;
2953 u16 tss_selector;
2954 int reason;
2955
2956 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2957
2958 reason = (u32)exit_qualification >> 30;
60637aac
JK		 2959 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2960 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2961 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2962 == INTR_TYPE_NMI_INTR) {
2963 vcpu->arch.nmi_injected = false;
2964 if (cpu_has_virtual_nmis())
2965 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2966 GUEST_INTR_STATE_NMI);
2967 }
37817f29
IE		 2968 tss_selector = exit_qualification;
2969
2970 return kvm_task_switch(vcpu, tss_selector, reason);
2971}
2972
1439442c
SY		 2973static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2974{
2975 u64 exit_qualification;
2976 enum emulation_result er;
2977 gpa_t gpa;
2978 unsigned long hva;
2979 int gla_validity;
2980 int r;
2981
2982 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2983
2984 if (exit_qualification & (1 << 6)) {
2985 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2986 return -ENOTSUPP;
2987 }
2988
2989 gla_validity = (exit_qualification >> 7) & 0x3;
2990 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2991 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2992 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2993 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2994 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2995 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2996 (long unsigned int)exit_qualification);
2997 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2998 kvm_run->hw.hardware_exit_reason = 0;
2999 return -ENOTSUPP;
3000 }
3001
3002 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3003 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3004 if (!kvm_is_error_hva(hva)) {
3005 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3006 if (r < 0) {
3007 printk(KERN_ERR "EPT: Not enough memory!\n");
3008 return -ENOMEM;
3009 }
3010 return 1;
3011 } else {
3012 /* must be MMIO */
3013 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3014
3015 if (er == EMULATE_FAIL) {
3016 printk(KERN_ERR
3017 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3018 er);
3019 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3020 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3021 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3022 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3023 (long unsigned int)exit_qualification);
3024 return -ENOTSUPP;
3025 } else if (er == EMULATE_DO_MMIO)
3026 return 0;
3027 }
3028 return 1;
3029}
3030
f08864b4
SY		 3031static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3032{
3033 u32 cpu_based_vm_exec_control;
3034
3035 /* clear pending NMI */
3036 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3037 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3038 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3039 ++vcpu->stat.nmi_window_exits;
3040
487b391d
JK		 3041 /*
3042 * If the user space waits to inject a NMI, exit as soon as possible
3043 */
3044 if (kvm_run->request_nmi_window && !vcpu->arch.nmi_pending) {
3045 kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN;
3046 return 0;
3047 }
3048
f08864b4
SY		 3049 return 1;
3050}
3051
ea953ef0
MG		 3052static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3053 struct kvm_run *kvm_run)
3054{
3055 struct vcpu_vmx *vmx = to_vmx(vcpu);
3056 int err;
3057
3058 preempt_enable();
3059 local_irq_enable();
3060
3061 while (!guest_state_valid(vcpu)) {
3062 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3063
1d5a4d9b
GT		 3064 if (err == EMULATE_DO_MMIO)
3065 break;
3066
3067 if (err != EMULATE_DONE) {
3068 kvm_report_emulation_failure(vcpu, "emulation failure");
3069 return;
ea953ef0
MG		 3070 }
3071
3072 if (signal_pending(current))
3073 break;
3074 if (need_resched())
3075 schedule();
3076 }
3077
3078 local_irq_disable();
3079 preempt_disable();
3080
1d5a4d9b
GT		 3081 /* Guest state should be valid now except if we need to
3082 * emulate an MMIO */
3083 if (guest_state_valid(vcpu))
3084 vmx->emulation_required = 0;
ea953ef0
MG		 3085}
3086
6aa8b732
AK		 3087/*
3088 * The exit handlers return 1 if the exit was handled fully and guest execution
3089 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3090 * to be done to userspace and return 0.
3091 */
3092static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3093 struct kvm_run *kvm_run) = {
3094 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3095 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3096 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3097 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3098 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3099 [EXIT_REASON_CR_ACCESS] = handle_cr,
3100 [EXIT_REASON_DR_ACCESS] = handle_dr,
3101 [EXIT_REASON_CPUID] = handle_cpuid,
3102 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3103 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3104 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3105 [EXIT_REASON_HLT] = handle_halt,
a7052897 3106 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3107 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3108 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3109 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3110 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3111 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3112 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3113};
3114
3115static const int kvm_vmx_max_exit_handlers =
50a3485c 3116 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3117
3118/*
3119 * The guest has exited. See if we can fix it or if we need userspace
3120 * assistance.
3121 */
3122static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3123{
6aa8b732 3124 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3125 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3126 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3127
5fdbf976
MT		 3128 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3129 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3130
1d5a4d9b
GT		 3131 /* If we need to emulate an MMIO from handle_invalid_guest_state
3132 * we just return 0 */
3133 if (vmx->emulation_required && emulate_invalid_guest_state)
3134 return 0;
3135
1439442c
SY		 3136 /* Access CR3 don't cause VMExit in paging mode, so we need
3137 * to sync with guest real CR3. */
3138 if (vm_need_ept() && is_paging(vcpu)) {
3139 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3140 ept_load_pdptrs(vcpu);
3141 }
3142
29bd8a78
AK		 3143 if (unlikely(vmx->fail)) {
3144 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3145 kvm_run->fail_entry.hardware_entry_failure_reason
3146 = vmcs_read32(VM_INSTRUCTION_ERROR);
3147 return 0;
3148 }
6aa8b732 3149
d77c26fc 3150 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3151 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3152 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3153 exit_reason != EXIT_REASON_TASK_SWITCH))
3154 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3155 "(0x%x) and exit reason is 0x%x\n",
3156 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3157
3158 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3159 if (vcpu->arch.interrupt_window_open) {
3160 vmx->soft_vnmi_blocked = 0;
3161 vcpu->arch.nmi_window_open = 1;
3162 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3163 (kvm_run->request_nmi_window || vcpu->arch.nmi_pending)) {
3164 /*
3165 * This CPU don't support us in finding the end of an
3166 * NMI-blocked window if the guest runs with IRQs
3167 * disabled. So we pull the trigger after 1 s of
3168 * futile waiting, but inform the user about this.
3169 */
3170 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3171 "state on VCPU %d after 1 s timeout\n",
3172 __func__, vcpu->vcpu_id);
3173 vmx->soft_vnmi_blocked = 0;
3174 vmx->vcpu.arch.nmi_window_open = 1;
3175 }
3176
3177 /*
3178 * If the user space waits to inject an NNI, exit ASAP
3179 */
3180 if (vcpu->arch.nmi_window_open && kvm_run->request_nmi_window
3181 && !vcpu->arch.nmi_pending) {
3182 kvm_run->exit_reason = KVM_EXIT_NMI_WINDOW_OPEN;
3183 ++vcpu->stat.nmi_window_exits;
3184 return 0;
3185 }
3186 }
3187
6aa8b732
AK		 3188 if (exit_reason < kvm_vmx_max_exit_handlers
3189 && kvm_vmx_exit_handlers[exit_reason])
3190 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3191 else {
3192 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3193 kvm_run->hw.hardware_exit_reason = exit_reason;
3194 }
3195 return 0;
3196}
3197
6e5d865c
YS		 3198static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3199{
3200 int max_irr, tpr;
3201
3202 if (!vm_need_tpr_shadow(vcpu->kvm))
3203 return;
3204
3205 if (!kvm_lapic_enabled(vcpu) ||
3206 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3207 vmcs_write32(TPR_THRESHOLD, 0);
3208 return;
3209 }
3210
3211 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3212 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3213}
3214
cf393f75
AK		 3215static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3216{
3217 u32 exit_intr_info;
668f612f 3218 u32 idt_vectoring_info;
cf393f75
AK		 3219 bool unblock_nmi;
3220 u8 vector;
668f612f
AK		 3221 int type;
3222 bool idtv_info_valid;
35920a35 3223 u32 error;
cf393f75
AK		 3224
3225 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3226 if (cpu_has_virtual_nmis()) {
3227 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3228 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3229 /*
3230 * SDM 3: 25.7.1.2
3231 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3232 * a guest IRET fault.
3233 */
3234 if (unblock_nmi && vector != DF_VECTOR)
3235 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3236 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3237 } else if (unlikely(vmx->soft_vnmi_blocked))
3238 vmx->vnmi_blocked_time +=
3239 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f
AK		 3240
3241 idt_vectoring_info = vmx->idt_vectoring_info;
3242 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3243 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3244 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3245 if (vmx->vcpu.arch.nmi_injected) {
3246 /*
3247 * SDM 3: 25.7.1.2
3248 * Clear bit "block by NMI" before VM entry if a NMI delivery
3249 * faulted.
3250 */
3251 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3252 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3253 GUEST_INTR_STATE_NMI);
3254 else
3255 vmx->vcpu.arch.nmi_injected = false;
3256 }
35920a35
AK		 3257 kvm_clear_exception_queue(&vmx->vcpu);
3258 if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3259 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3260 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3261 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3262 } else
3263 kvm_queue_exception(&vmx->vcpu, vector);
3264 vmx->idt_vectoring_info = 0;
3265 }
f7d9238f
AK		 3266 kvm_clear_interrupt_queue(&vmx->vcpu);
3267 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3268 kvm_queue_interrupt(&vmx->vcpu, vector);
3269 vmx->idt_vectoring_info = 0;
3270 }
cf393f75
AK		 3271}
3272
85f455f7
ED		 3273static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3274{
6e5d865c
YS		 3275 update_tpr_threshold(vcpu);
3276
33f089ca
JK		 3277 vmx_update_window_states(vcpu);
3278
3b86cd99
JK		 3279 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3280 if (vcpu->arch.interrupt.pending) {
3281 enable_nmi_window(vcpu);
3282 } else if (vcpu->arch.nmi_window_open) {
3283 vcpu->arch.nmi_pending = false;
3284 vcpu->arch.nmi_injected = true;
3285 } else {
3286 enable_nmi_window(vcpu);
f08864b4
SY		 3287 return;
3288 }
f08864b4 3289 }
3b86cd99
JK		 3290 if (vcpu->arch.nmi_injected) {
3291 vmx_inject_nmi(vcpu);
3292 if (vcpu->arch.nmi_pending)
3293 enable_nmi_window(vcpu);
3294 else if (kvm_cpu_has_interrupt(vcpu))
3295 enable_irq_window(vcpu);
3296 return;
3297 }
f7d9238f 3298 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
33f089ca 3299 if (vcpu->arch.interrupt_window_open)
f7d9238f
AK		 3300 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3301 else
3302 enable_irq_window(vcpu);
3303 }
3304 if (vcpu->arch.interrupt.pending) {
3305 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3306 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
df203ec9
AK		 3307 if (kvm_cpu_has_interrupt(vcpu))
3308 enable_irq_window(vcpu);
f7d9238f 3309 }
85f455f7
ED		 3310}
3311
9c8cba37
AK		 3312/*
3313 * Failure to inject an interrupt should give us the information
3314 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3315 * when fetching the interrupt redirection bitmap in the real-mode
3316 * tss, this doesn't happen. So we do it ourselves.
3317 */
3318static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3319{
3320 vmx->rmode.irq.pending = 0;
5fdbf976 3321 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3322 return;
5fdbf976 3323 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3324 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3325 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3326 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3327 return;
3328 }
3329 vmx->idt_vectoring_info =
3330 VECTORING_INFO_VALID_MASK
3331 | INTR_TYPE_EXT_INTR
3332 | vmx->rmode.irq.vector;
3333}
3334
c801949d
AK		 3335#ifdef CONFIG_X86_64
3336#define R "r"
3337#define Q "q"
3338#else
3339#define R "e"
3340#define Q "l"
3341#endif
3342
04d2cc77 3343static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3344{
a2fa3e9f 3345 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3346 u32 intr_info;
e6adf283 3347
3b86cd99
JK		 3348 /* Record the guest's net vcpu time for enforced NMI injections. */
3349 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3350 vmx->entry_time = ktime_get();
3351
a89a8fb9
MG		 3352 /* Handle invalid guest state instead of entering VMX */
3353 if (vmx->emulation_required && emulate_invalid_guest_state) {
3354 handle_invalid_guest_state(vcpu, kvm_run);
3355 return;
3356 }
3357
5fdbf976
MT		 3358 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3359 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3360 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3361 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3362
e6adf283
AK		 3363 /*
3364 * Loading guest fpu may have cleared host cr0.ts
3365 */
3366 vmcs_writel(HOST_CR0, read_cr0());
3367
d77c26fc 3368 asm(
6aa8b732 3369 /* Store host registers */
c801949d
AK		 3370 "push %%"R"dx; push %%"R"bp;"
3371 "push %%"R"cx \n\t"
313dbd49
AK		 3372 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3373 "je 1f \n\t"
3374 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3375 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3376 "1: \n\t"
6aa8b732 3377 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3378 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3379 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3380 "mov %c[cr2](%0), %%"R"ax \n\t"
3381 "mov %%"R"ax, %%cr2 \n\t"
3382 "mov %c[rax](%0), %%"R"ax \n\t"
3383 "mov %c[rbx](%0), %%"R"bx \n\t"
3384 "mov %c[rdx](%0), %%"R"dx \n\t"
3385 "mov %c[rsi](%0), %%"R"si \n\t"
3386 "mov %c[rdi](%0), %%"R"di \n\t"
3387 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3388#ifdef CONFIG_X86_64
e08aa78a
AK		 3389 "mov %c[r8](%0), %%r8 \n\t"
3390 "mov %c[r9](%0), %%r9 \n\t"
3391 "mov %c[r10](%0), %%r10 \n\t"
3392 "mov %c[r11](%0), %%r11 \n\t"
3393 "mov %c[r12](%0), %%r12 \n\t"
3394 "mov %c[r13](%0), %%r13 \n\t"
3395 "mov %c[r14](%0), %%r14 \n\t"
3396 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3397#endif
c801949d
AK		 3398 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3399
6aa8b732 3400 /* Enter guest mode */
cd2276a7 3401 "jne .Llaunched \n\t"
4ecac3fd 3402 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3403 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3404 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3405 ".Lkvm_vmx_return: "
6aa8b732 3406 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3407 "xchg %0, (%%"R"sp) \n\t"
3408 "mov %%"R"ax, %c[rax](%0) \n\t"
3409 "mov %%"R"bx, %c[rbx](%0) \n\t"
3410 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3411 "mov %%"R"dx, %c[rdx](%0) \n\t"
3412 "mov %%"R"si, %c[rsi](%0) \n\t"
3413 "mov %%"R"di, %c[rdi](%0) \n\t"
3414 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3415#ifdef CONFIG_X86_64
e08aa78a
AK		 3416 "mov %%r8, %c[r8](%0) \n\t"
3417 "mov %%r9, %c[r9](%0) \n\t"
3418 "mov %%r10, %c[r10](%0) \n\t"
3419 "mov %%r11, %c[r11](%0) \n\t"
3420 "mov %%r12, %c[r12](%0) \n\t"
3421 "mov %%r13, %c[r13](%0) \n\t"
3422 "mov %%r14, %c[r14](%0) \n\t"
3423 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3424#endif
c801949d
AK		 3425 "mov %%cr2, %%"R"ax \n\t"
3426 "mov %%"R"ax, %c[cr2](%0) \n\t"
3427
3428 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3429 "setbe %c[fail](%0) \n\t"
3430 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3431 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3432 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3433 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3434 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3435 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3436 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3437 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3438 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3439 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3440 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3441#ifdef CONFIG_X86_64
ad312c7c
ZX		 3442 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3443 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3444 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3445 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3446 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3447 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3448 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3449 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3450#endif
ad312c7c 3451 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3452 : "cc", "memory"
c801949d 3453 , R"bx", R"di", R"si"
c2036300 3454#ifdef CONFIG_X86_64
c2036300
LV		 3455 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3456#endif
3457 );
6aa8b732 3458
5fdbf976
MT		 3459 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3460 vcpu->arch.regs_dirty = 0;
3461
1155f76a 3462 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3463 if (vmx->rmode.irq.pending)
3464 fixup_rmode_irq(vmx);
1155f76a 3465
33f089ca 3466 vmx_update_window_states(vcpu);
6aa8b732 3467
d77c26fc 3468 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3469 vmx->launched = 1;
1b6269db
AK		 3470
3471 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3472
3473 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3474 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3475 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3476 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3477 asm("int $2");
2714d1d3 3478 }
cf393f75
AK		 3479
3480 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3481}
3482
c801949d
AK		 3483#undef R
3484#undef Q
3485
6aa8b732
AK		 3486static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3487{
a2fa3e9f
GH		 3488 struct vcpu_vmx *vmx = to_vmx(vcpu);
3489
3490 if (vmx->vmcs) {
543e4243 3491 vcpu_clear(vmx);
a2fa3e9f
GH		 3492 free_vmcs(vmx->vmcs);
3493 vmx->vmcs = NULL;
6aa8b732
AK		 3494 }
3495}
3496
3497static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3498{
fb3f0f51
RR		 3499 struct vcpu_vmx *vmx = to_vmx(vcpu);
3500
2384d2b3
SY		 3501 spin_lock(&vmx_vpid_lock);
3502 if (vmx->vpid != 0)
3503 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3504 spin_unlock(&vmx_vpid_lock);
6aa8b732 3505 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3506 kfree(vmx->host_msrs);
3507 kfree(vmx->guest_msrs);
3508 kvm_vcpu_uninit(vcpu);
a4770347 3509 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3510}
3511
fb3f0f51 3512static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3513{
fb3f0f51 3514 int err;
c16f862d 3515 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3516 int cpu;
6aa8b732 3517
a2fa3e9f 3518 if (!vmx)
fb3f0f51
RR		 3519 return ERR_PTR(-ENOMEM);
3520
2384d2b3
SY		 3521 allocate_vpid(vmx);
3522
fb3f0f51
RR		 3523 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3524 if (err)
3525 goto free_vcpu;
965b58a5 3526
a2fa3e9f 3527 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3528 if (!vmx->guest_msrs) {
3529 err = -ENOMEM;
3530 goto uninit_vcpu;
3531 }
965b58a5 3532
a2fa3e9f
GH		 3533 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3534 if (!vmx->host_msrs)
fb3f0f51 3535 goto free_guest_msrs;
965b58a5 3536
a2fa3e9f
GH		 3537 vmx->vmcs = alloc_vmcs();
3538 if (!vmx->vmcs)
fb3f0f51 3539 goto free_msrs;
a2fa3e9f
GH		 3540
3541 vmcs_clear(vmx->vmcs);
3542
15ad7146
AK		 3543 cpu = get_cpu();
3544 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3545 err = vmx_vcpu_setup(vmx);
fb3f0f51 3546 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3547 put_cpu();
fb3f0f51
RR		 3548 if (err)
3549 goto free_vmcs;
5e4a0b3c
MT		 3550 if (vm_need_virtualize_apic_accesses(kvm))
3551 if (alloc_apic_access_page(kvm) != 0)
3552 goto free_vmcs;
fb3f0f51 3553
b7ebfb05
SY		 3554 if (vm_need_ept())
3555 if (alloc_identity_pagetable(kvm) != 0)
3556 goto free_vmcs;
3557
fb3f0f51
RR		 3558 return &vmx->vcpu;
3559
3560free_vmcs:
3561 free_vmcs(vmx->vmcs);
3562free_msrs:
3563 kfree(vmx->host_msrs);
3564free_guest_msrs:
3565 kfree(vmx->guest_msrs);
3566uninit_vcpu:
3567 kvm_vcpu_uninit(&vmx->vcpu);
3568free_vcpu:
a4770347 3569 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3570 return ERR_PTR(err);
6aa8b732
AK		 3571}
3572
002c7f7c
YS		 3573static void __init vmx_check_processor_compat(void *rtn)
3574{
3575 struct vmcs_config vmcs_conf;
3576
3577 *(int *)rtn = 0;
3578 if (setup_vmcs_config(&vmcs_conf) < 0)
3579 *(int *)rtn = -EIO;
3580 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3581 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3582 smp_processor_id());
3583 *(int *)rtn = -EIO;
3584 }
3585}
3586
67253af5
SY		 3587static int get_ept_level(void)
3588{
3589 return VMX_EPT_DEFAULT_GAW + 1;
3590}
3591
64d4d521
SY		 3592static int vmx_get_mt_mask_shift(void)
3593{
3594 return VMX_EPT_MT_EPTE_SHIFT;
3595}
3596
cbdd1bea 3597static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3598 .cpu_has_kvm_support = cpu_has_kvm_support,
3599 .disabled_by_bios = vmx_disabled_by_bios,
3600 .hardware_setup = hardware_setup,
3601 .hardware_unsetup = hardware_unsetup,
002c7f7c 3602 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3603 .hardware_enable = hardware_enable,
3604 .hardware_disable = hardware_disable,
774ead3a 3605 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3606
3607 .vcpu_create = vmx_create_vcpu,
3608 .vcpu_free = vmx_free_vcpu,
04d2cc77 3609 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3610
04d2cc77 3611 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3612 .vcpu_load = vmx_vcpu_load,
3613 .vcpu_put = vmx_vcpu_put,
3614
3615 .set_guest_debug = set_guest_debug,
04d2cc77 3616 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 3617 .get_msr = vmx_get_msr,
3618 .set_msr = vmx_set_msr,
3619 .get_segment_base = vmx_get_segment_base,
3620 .get_segment = vmx_get_segment,
3621 .set_segment = vmx_set_segment,
2e4d2653 3622 .get_cpl = vmx_get_cpl,
6aa8b732 3623 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3624 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3625 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3626 .set_cr3 = vmx_set_cr3,
3627 .set_cr4 = vmx_set_cr4,
6aa8b732 3628 .set_efer = vmx_set_efer,
6aa8b732
AK		 3629 .get_idt = vmx_get_idt,
3630 .set_idt = vmx_set_idt,
3631 .get_gdt = vmx_get_gdt,
3632 .set_gdt = vmx_set_gdt,
5fdbf976 3633 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3634 .get_rflags = vmx_get_rflags,
3635 .set_rflags = vmx_set_rflags,
3636
3637 .tlb_flush = vmx_flush_tlb,
6aa8b732 3638
6aa8b732 3639 .run = vmx_vcpu_run,
04d2cc77 3640 .handle_exit = kvm_handle_exit,
6aa8b732 3641 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3642 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3643 .get_irq = vmx_get_irq,
3644 .set_irq = vmx_inject_irq,
298101da
AK		 3645 .queue_exception = vmx_queue_exception,
3646 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3647 .inject_pending_irq = vmx_intr_assist,
3648 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3649
3650 .set_tss_addr = vmx_set_tss_addr,
67253af5 3651 .get_tdp_level = get_ept_level,
64d4d521 3652 .get_mt_mask_shift = vmx_get_mt_mask_shift,
6aa8b732
AK		 3653};
3654
3655static int __init vmx_init(void)
3656{
25c5f225 3657 void *va;
fdef3ad1
HQ		 3658 int r;
3659
3660 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3661 if (!vmx_io_bitmap_a)
3662 return -ENOMEM;
3663
3664 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3665 if (!vmx_io_bitmap_b) {
3666 r = -ENOMEM;
3667 goto out;
3668 }
3669
25c5f225
SY		 3670 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3671 if (!vmx_msr_bitmap) {
3672 r = -ENOMEM;
3673 goto out1;
3674 }
3675
fdef3ad1
HQ		 3676 /*
3677 * Allow direct access to the PC debug port (it is often used for I/O
3678 * delays, but the vmexits simply slow things down).
3679 */
25c5f225
SY		 3680 va = kmap(vmx_io_bitmap_a);
3681 memset(va, 0xff, PAGE_SIZE);
3682 clear_bit(0x80, va);
cd0536d7 3683 kunmap(vmx_io_bitmap_a);
fdef3ad1 3684
25c5f225
SY		 3685 va = kmap(vmx_io_bitmap_b);
3686 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3687 kunmap(vmx_io_bitmap_b);
fdef3ad1 3688
25c5f225
SY		 3689 va = kmap(vmx_msr_bitmap);
3690 memset(va, 0xff, PAGE_SIZE);
3691 kunmap(vmx_msr_bitmap);
3692
2384d2b3
SY		 3693 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3694
cb498ea2 3695 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3696 if (r)
25c5f225
SY		 3697 goto out2;
3698
3699 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3700 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3701 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3702 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3703 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3704
5fdbcb9d 3705 if (vm_need_ept()) {
1439442c 3706 bypass_guest_pf = 0;
5fdbcb9d
SY		 3707 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3708 VMX_EPT_WRITABLE_MASK |
928d4bf7 3709 VMX_EPT_IGMT_BIT);
534e38b4 3710 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
64d4d521
SY		 3711 VMX_EPT_EXECUTABLE_MASK,
3712 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
5fdbcb9d
SY		 3713 kvm_enable_tdp();
3714 } else
3715 kvm_disable_tdp();
1439442c 3716
c7addb90
AK		 3717 if (bypass_guest_pf)
3718 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3719
1439442c
SY		 3720 ept_sync_global();
3721
fdef3ad1
HQ		 3722 return 0;
3723
25c5f225
SY		 3724out2:
3725 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3726out1:
3727 __free_page(vmx_io_bitmap_b);
3728out:
3729 __free_page(vmx_io_bitmap_a);
3730 return r;
6aa8b732
AK		 3731}
3732
3733static void __exit vmx_exit(void)
3734{
25c5f225 3735 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3736 __free_page(vmx_io_bitmap_b);
3737 __free_page(vmx_io_bitmap_a);
3738
cb498ea2 3739 kvm_exit();
6aa8b732
AK		 3740}
3741
3742module_init(vmx_init)
3743module_exit(vmx_exit)
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