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KVM: skip_emulated_instruction() decode instruction if size is not known
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
6aa8b732 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
4462d21a 41static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 42module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 43
4462d21a 44static int __read_mostly enable_vpid = 1;
736caefe 45module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 46
4462d21a 47static int __read_mostly flexpriority_enabled = 1;
736caefe 48module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 49
4462d21a 50static int __read_mostly enable_ept = 1;
736caefe 51module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 52
4462d21a 53static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 54module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 55
a2fa3e9f
GH		 56struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60};
61
62struct vcpu_vmx {
fb3f0f51 63 struct kvm_vcpu vcpu;
543e4243 64 struct list_head local_vcpus_link;
313dbd49 65 unsigned long host_rsp;
a2fa3e9f 66 int launched;
29bd8a78 67 u8 fail;
1155f76a 68 u32 idt_vectoring_info;
a2fa3e9f
GH		 69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74#ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76#endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
51c6cf66 83 int guest_efer_loaded;
d77c26fc 84 } host_state;
9c8cba37
AK		 85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
2384d2b3 92 int vpid;
04fa4d32 93 bool emulation_required;
8b3079a5 94 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 95
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked;
98 ktime_t entry_time;
99 s64 vnmi_blocked_time;
a2fa3e9f
GH		 100};
101
102static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103{
fb3f0f51 104 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 105}
106
b7ebfb05 107static int init_rmode(struct kvm *kvm);
4e1096d2 108static u64 construct_eptp(unsigned long root_hpa);
75880a01 109
6aa8b732
AK		 110static DEFINE_PER_CPU(struct vmcs *, vmxarea);
111static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 112static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 113
3e7c73e9
AK		 114static unsigned long *vmx_io_bitmap_a;
115static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 116static unsigned long *vmx_msr_bitmap_legacy;
117static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 118
2384d2b3
SY		 119static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
120static DEFINE_SPINLOCK(vmx_vpid_lock);
121
1c3d14fe 122static struct vmcs_config {
6aa8b732
AK		 123 int size;
124 int order;
125 u32 revision_id;
1c3d14fe
YS		 126 u32 pin_based_exec_ctrl;
127 u32 cpu_based_exec_ctrl;
f78e0e2e 128 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 129 u32 vmexit_ctrl;
130 u32 vmentry_ctrl;
131} vmcs_config;
6aa8b732 132
efff9e53 133static struct vmx_capability {
d56f546d
SY		 134 u32 ept;
135 u32 vpid;
136} vmx_capability;
137
6aa8b732
AK		 138#define VMX_SEGMENT_FIELD(seg) \
139 [VCPU_SREG_##seg] = { \
140 .selector = GUEST_##seg##_SELECTOR, \
141 .base = GUEST_##seg##_BASE, \
142 .limit = GUEST_##seg##_LIMIT, \
143 .ar_bytes = GUEST_##seg##_AR_BYTES, \
144 }
145
146static struct kvm_vmx_segment_field {
147 unsigned selector;
148 unsigned base;
149 unsigned limit;
150 unsigned ar_bytes;
151} kvm_vmx_segment_fields[] = {
152 VMX_SEGMENT_FIELD(CS),
153 VMX_SEGMENT_FIELD(DS),
154 VMX_SEGMENT_FIELD(ES),
155 VMX_SEGMENT_FIELD(FS),
156 VMX_SEGMENT_FIELD(GS),
157 VMX_SEGMENT_FIELD(SS),
158 VMX_SEGMENT_FIELD(TR),
159 VMX_SEGMENT_FIELD(LDTR),
160};
161
4d56c8a7
AK		 162/*
163 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
164 * away by decrementing the array size.
165 */
6aa8b732 166static const u32 vmx_msr_index[] = {
05b3e0c2 167#ifdef CONFIG_X86_64
6aa8b732
AK		 168 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
169#endif
170 MSR_EFER, MSR_K6_STAR,
171};
9d8f549d 172#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 173
a2fa3e9f
GH		 174static void load_msrs(struct kvm_msr_entry *e, int n)
175{
176 int i;
177
178 for (i = 0; i < n; ++i)
179 wrmsrl(e[i].index, e[i].data);
180}
181
182static void save_msrs(struct kvm_msr_entry *e, int n)
183{
184 int i;
185
186 for (i = 0; i < n; ++i)
187 rdmsrl(e[i].index, e[i].data);
188}
189
6aa8b732
AK		 190static inline int is_page_fault(u32 intr_info)
191{
192 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
193 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 194 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 195}
196
2ab455cc
AL		 197static inline int is_no_device(u32 intr_info)
198{
199 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
200 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 201 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 202}
203
7aa81cc0
AL		 204static inline int is_invalid_opcode(u32 intr_info)
205{
206 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
207 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 208 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 209}
210
6aa8b732
AK		 211static inline int is_external_interrupt(u32 intr_info)
212{
213 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
214 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
215}
216
25c5f225
SY		 217static inline int cpu_has_vmx_msr_bitmap(void)
218{
04547156 219 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 220}
221
6e5d865c
YS		 222static inline int cpu_has_vmx_tpr_shadow(void)
223{
04547156 224 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 225}
226
227static inline int vm_need_tpr_shadow(struct kvm *kvm)
228{
04547156 229 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 230}
231
f78e0e2e
SY		 232static inline int cpu_has_secondary_exec_ctrls(void)
233{
04547156
SY		 234 return vmcs_config.cpu_based_exec_ctrl &
235 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 236}
237
774ead3a 238static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 239{
04547156
SY		 240 return vmcs_config.cpu_based_2nd_exec_ctrl &
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
242}
243
244static inline bool cpu_has_vmx_flexpriority(void)
245{
246 return cpu_has_vmx_tpr_shadow() &&
247 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 248}
249
d56f546d
SY		 250static inline int cpu_has_vmx_invept_individual_addr(void)
251{
04547156 252 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 253}
254
255static inline int cpu_has_vmx_invept_context(void)
256{
04547156 257 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 258}
259
260static inline int cpu_has_vmx_invept_global(void)
261{
04547156 262 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 263}
264
265static inline int cpu_has_vmx_ept(void)
266{
04547156
SY		 267 return vmcs_config.cpu_based_2nd_exec_ctrl &
268 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 269}
270
f78e0e2e
SY		 271static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
272{
04547156
SY		 273 return flexpriority_enabled &&
274 (cpu_has_vmx_virtualize_apic_accesses()) &&
275 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 276}
277
2384d2b3
SY		 278static inline int cpu_has_vmx_vpid(void)
279{
04547156
SY		 280 return vmcs_config.cpu_based_2nd_exec_ctrl &
281 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 282}
283
f08864b4
SY		 284static inline int cpu_has_virtual_nmis(void)
285{
286 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
287}
288
04547156
SY		 289static inline bool report_flexpriority(void)
290{
291 return flexpriority_enabled;
292}
293
8b9cf98c 294static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 295{
296 int i;
297
a2fa3e9f
GH		 298 for (i = 0; i < vmx->nmsrs; ++i)
299 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 300 return i;
301 return -1;
302}
303
2384d2b3
SY		 304static inline void __invvpid(int ext, u16 vpid, gva_t gva)
305{
306 struct {
307 u64 vpid : 16;
308 u64 rsvd : 48;
309 u64 gva;
310 } operand = { vpid, 0, gva };
311
4ecac3fd 312 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 313 /* CF==1 or ZF==1 --> rc = -1 */
314 "; ja 1f ; ud2 ; 1:"
315 : : "a"(&operand), "c"(ext) : "cc", "memory");
316}
317
1439442c
SY		 318static inline void __invept(int ext, u64 eptp, gpa_t gpa)
319{
320 struct {
321 u64 eptp, gpa;
322 } operand = {eptp, gpa};
323
4ecac3fd 324 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 325 /* CF==1 or ZF==1 --> rc = -1 */
326 "; ja 1f ; ud2 ; 1:\n"
327 : : "a" (&operand), "c" (ext) : "cc", "memory");
328}
329
8b9cf98c 330static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 331{
332 int i;
333
8b9cf98c 334 i = __find_msr_index(vmx, msr);
a75beee6 335 if (i >= 0)
a2fa3e9f 336 return &vmx->guest_msrs[i];
8b6d44c7 337 return NULL;
7725f0ba
AK		 338}
339
6aa8b732
AK		 340static void vmcs_clear(struct vmcs *vmcs)
341{
342 u64 phys_addr = __pa(vmcs);
343 u8 error;
344
4ecac3fd 345 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 346 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
347 : "cc", "memory");
348 if (error)
349 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
350 vmcs, phys_addr);
351}
352
353static void __vcpu_clear(void *arg)
354{
8b9cf98c 355 struct vcpu_vmx *vmx = arg;
d3b2c338 356 int cpu = raw_smp_processor_id();
6aa8b732 357
8b9cf98c 358 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 359 vmcs_clear(vmx->vmcs);
360 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 361 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 362 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 363 list_del(&vmx->local_vcpus_link);
364 vmx->vcpu.cpu = -1;
365 vmx->launched = 0;
6aa8b732
AK		 366}
367
8b9cf98c 368static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 369{
eae5ecb5
AK		 370 if (vmx->vcpu.cpu == -1)
371 return;
8691e5a8 372 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 373}
374
2384d2b3
SY		 375static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
376{
377 if (vmx->vpid == 0)
378 return;
379
380 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
381}
382
1439442c
SY		 383static inline void ept_sync_global(void)
384{
385 if (cpu_has_vmx_invept_global())
386 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
387}
388
389static inline void ept_sync_context(u64 eptp)
390{
089d034e 391 if (enable_ept) {
1439442c
SY		 392 if (cpu_has_vmx_invept_context())
393 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
394 else
395 ept_sync_global();
396 }
397}
398
399static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
400{
089d034e 401 if (enable_ept) {
1439442c
SY		 402 if (cpu_has_vmx_invept_individual_addr())
403 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
404 eptp, gpa);
405 else
406 ept_sync_context(eptp);
407 }
408}
409
6aa8b732
AK		 410static unsigned long vmcs_readl(unsigned long field)
411{
412 unsigned long value;
413
4ecac3fd 414 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 415 : "=a"(value) : "d"(field) : "cc");
416 return value;
417}
418
419static u16 vmcs_read16(unsigned long field)
420{
421 return vmcs_readl(field);
422}
423
424static u32 vmcs_read32(unsigned long field)
425{
426 return vmcs_readl(field);
427}
428
429static u64 vmcs_read64(unsigned long field)
430{
05b3e0c2 431#ifdef CONFIG_X86_64
6aa8b732
AK		 432 return vmcs_readl(field);
433#else
434 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
435#endif
436}
437
e52de1b8
AK		 438static noinline void vmwrite_error(unsigned long field, unsigned long value)
439{
440 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
441 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
442 dump_stack();
443}
444
6aa8b732
AK		 445static void vmcs_writel(unsigned long field, unsigned long value)
446{
447 u8 error;
448
4ecac3fd 449 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 450 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 451 if (unlikely(error))
452 vmwrite_error(field, value);
6aa8b732
AK		 453}
454
455static void vmcs_write16(unsigned long field, u16 value)
456{
457 vmcs_writel(field, value);
458}
459
460static void vmcs_write32(unsigned long field, u32 value)
461{
462 vmcs_writel(field, value);
463}
464
465static void vmcs_write64(unsigned long field, u64 value)
466{
6aa8b732 467 vmcs_writel(field, value);
7682f2d0 468#ifndef CONFIG_X86_64
6aa8b732
AK		 469 asm volatile ("");
470 vmcs_writel(field+1, value >> 32);
471#endif
472}
473
2ab455cc
AL		 474static void vmcs_clear_bits(unsigned long field, u32 mask)
475{
476 vmcs_writel(field, vmcs_readl(field) & ~mask);
477}
478
479static void vmcs_set_bits(unsigned long field, u32 mask)
480{
481 vmcs_writel(field, vmcs_readl(field) | mask);
482}
483
abd3f2d6
AK		 484static void update_exception_bitmap(struct kvm_vcpu *vcpu)
485{
486 u32 eb;
487
7aa81cc0 488 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 489 if (!vcpu->fpu_active)
490 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 491 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
492 if (vcpu->guest_debug &
493 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
494 eb |= 1u << DB_VECTOR;
495 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
496 eb |= 1u << BP_VECTOR;
497 }
ad312c7c 498 if (vcpu->arch.rmode.active)
abd3f2d6 499 eb = ~0;
089d034e 500 if (enable_ept)
1439442c 501 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 502 vmcs_write32(EXCEPTION_BITMAP, eb);
503}
504
33ed6329
AK		 505static void reload_tss(void)
506{
33ed6329
AK		 507 /*
508 * VT restores TR but not its size. Useless.
509 */
510 struct descriptor_table gdt;
a5f61300 511 struct desc_struct *descs;
33ed6329 512
d6e88aec 513 kvm_get_gdt(&gdt);
33ed6329
AK		 514 descs = (void *)gdt.base;
515 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
516 load_TR_desc();
33ed6329
AK		 517}
518
8b9cf98c 519static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 520{
a2fa3e9f 521 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 522 u64 host_efer = vmx->host_msrs[efer_offset].data;
523 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
524 u64 ignore_bits;
525
526 if (efer_offset < 0)
527 return;
528 /*
529 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
530 * outside long mode
531 */
532 ignore_bits = EFER_NX | EFER_SCE;
533#ifdef CONFIG_X86_64
534 ignore_bits |= EFER_LMA | EFER_LME;
535 /* SCE is meaningful only in long mode on Intel */
536 if (guest_efer & EFER_LMA)
537 ignore_bits &= ~(u64)EFER_SCE;
538#endif
539 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
540 return;
2cc51560 541
51c6cf66
AK		 542 vmx->host_state.guest_efer_loaded = 1;
543 guest_efer &= ~ignore_bits;
544 guest_efer |= host_efer & ignore_bits;
545 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 546 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 547}
548
51c6cf66
AK		 549static void reload_host_efer(struct vcpu_vmx *vmx)
550{
551 if (vmx->host_state.guest_efer_loaded) {
552 vmx->host_state.guest_efer_loaded = 0;
553 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
554 }
555}
556
04d2cc77 557static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 558{
04d2cc77
AK		 559 struct vcpu_vmx *vmx = to_vmx(vcpu);
560
a2fa3e9f 561 if (vmx->host_state.loaded)
33ed6329
AK		 562 return;
563
a2fa3e9f 564 vmx->host_state.loaded = 1;
33ed6329
AK		 565 /*
566 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
567 * allow segment selectors with cpl > 0 or ti == 1.
568 */
d6e88aec 569 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 570 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 571 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 572 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 573 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 574 vmx->host_state.fs_reload_needed = 0;
575 } else {
33ed6329 576 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 577 vmx->host_state.fs_reload_needed = 1;
33ed6329 578 }
d6e88aec 579 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 580 if (!(vmx->host_state.gs_sel & 7))
581 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 582 else {
583 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 584 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 585 }
586
587#ifdef CONFIG_X86_64
588 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
589 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
590#else
a2fa3e9f
GH		 591 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
592 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 593#endif
707c0874
AK		 594
595#ifdef CONFIG_X86_64
d77c26fc 596 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 597 save_msrs(vmx->host_msrs +
598 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 599
707c0874 600#endif
a2fa3e9f 601 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 602 load_transition_efer(vmx);
33ed6329
AK		 603}
604
a9b21b62 605static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 606{
15ad7146 607 unsigned long flags;
33ed6329 608
a2fa3e9f 609 if (!vmx->host_state.loaded)
33ed6329
AK		 610 return;
611
e1beb1d3 612 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 613 vmx->host_state.loaded = 0;
152d3f2f 614 if (vmx->host_state.fs_reload_needed)
d6e88aec 615 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 616 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 617 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 618 /*
619 * If we have to reload gs, we must take care to
620 * preserve our gs base.
621 */
15ad7146 622 local_irq_save(flags);
d6e88aec 623 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 624#ifdef CONFIG_X86_64
625 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
626#endif
15ad7146 627 local_irq_restore(flags);
33ed6329 628 }
152d3f2f 629 reload_tss();
a2fa3e9f
GH		 630 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
631 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 632 reload_host_efer(vmx);
33ed6329
AK		 633}
634
a9b21b62
AK		 635static void vmx_load_host_state(struct vcpu_vmx *vmx)
636{
637 preempt_disable();
638 __vmx_load_host_state(vmx);
639 preempt_enable();
640}
641
6aa8b732
AK		 642/*
643 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
644 * vcpu mutex is already taken.
645 */
15ad7146 646static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 647{
a2fa3e9f
GH		 648 struct vcpu_vmx *vmx = to_vmx(vcpu);
649 u64 phys_addr = __pa(vmx->vmcs);
019960ae 650 u64 tsc_this, delta, new_offset;
6aa8b732 651
a3d7f85f 652 if (vcpu->cpu != cpu) {
8b9cf98c 653 vcpu_clear(vmx);
2f599714 654 kvm_migrate_timers(vcpu);
2384d2b3 655 vpid_sync_vcpu_all(vmx);
543e4243
AK		 656 local_irq_disable();
657 list_add(&vmx->local_vcpus_link,
658 &per_cpu(vcpus_on_cpu, cpu));
659 local_irq_enable();
a3d7f85f 660 }
6aa8b732 661
a2fa3e9f 662 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 663 u8 error;
664
a2fa3e9f 665 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 666 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 667 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
668 : "cc");
669 if (error)
670 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 671 vmx->vmcs, phys_addr);
6aa8b732
AK		 672 }
673
674 if (vcpu->cpu != cpu) {
675 struct descriptor_table dt;
676 unsigned long sysenter_esp;
677
678 vcpu->cpu = cpu;
679 /*
680 * Linux uses per-cpu TSS and GDT, so set these when switching
681 * processors.
682 */
d6e88aec
AK		 683 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
684 kvm_get_gdt(&dt);
6aa8b732
AK		 685 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
686
687 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
688 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 689
690 /*
691 * Make sure the time stamp counter is monotonous.
692 */
693 rdtscll(tsc_this);
019960ae
AK		 694 if (tsc_this < vcpu->arch.host_tsc) {
695 delta = vcpu->arch.host_tsc - tsc_this;
696 new_offset = vmcs_read64(TSC_OFFSET) + delta;
697 vmcs_write64(TSC_OFFSET, new_offset);
698 }
6aa8b732 699 }
6aa8b732
AK		 700}
701
702static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
703{
a9b21b62 704 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 705}
706
5fd86fcf
AK		 707static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->fpu_active)
710 return;
711 vcpu->fpu_active = 1;
707d92fa 712 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 713 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 714 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 715 update_exception_bitmap(vcpu);
716}
717
718static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
719{
720 if (!vcpu->fpu_active)
721 return;
722 vcpu->fpu_active = 0;
707d92fa 723 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 724 update_exception_bitmap(vcpu);
725}
726
6aa8b732
AK		 727static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
728{
729 return vmcs_readl(GUEST_RFLAGS);
730}
731
732static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
733{
ad312c7c 734 if (vcpu->arch.rmode.active)
053de044 735 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 736 vmcs_writel(GUEST_RFLAGS, rflags);
737}
738
2809f5d2
GC		 739static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
740{
741 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
742 int ret = 0;
743
744 if (interruptibility & GUEST_INTR_STATE_STI)
745 ret |= X86_SHADOW_INT_STI;
746 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
747 ret |= X86_SHADOW_INT_MOV_SS;
748
749 return ret & mask;
750}
751
752static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
753{
754 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
755 u32 interruptibility = interruptibility_old;
756
757 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
758
759 if (mask & X86_SHADOW_INT_MOV_SS)
760 interruptibility |= GUEST_INTR_STATE_MOV_SS;
761 if (mask & X86_SHADOW_INT_STI)
762 interruptibility |= GUEST_INTR_STATE_STI;
763
764 if ((interruptibility != interruptibility_old))
765 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
766}
767
6aa8b732
AK		 768static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
769{
770 unsigned long rip;
6aa8b732 771
5fdbf976 772 rip = kvm_rip_read(vcpu);
6aa8b732 773 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 774 kvm_rip_write(vcpu, rip);
6aa8b732 775
2809f5d2
GC		 776 /* skipping an emulated instruction also counts */
777 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 778}
779
298101da
AK		 780static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
781 bool has_error_code, u32 error_code)
782{
77ab6db0 783 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 784 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 785
8ab2d2e2 786 if (has_error_code) {
77ab6db0 787 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 788 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
789 }
77ab6db0
JK		 790
791 if (vcpu->arch.rmode.active) {
792 vmx->rmode.irq.pending = true;
793 vmx->rmode.irq.vector = nr;
794 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
8ab2d2e2 795 if (nr == BP_VECTOR || nr == OF_VECTOR)
77ab6db0 796 vmx->rmode.irq.rip++;
8ab2d2e2
JK		 797 intr_info |= INTR_TYPE_SOFT_INTR;
798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 799 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
800 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
801 return;
802 }
803
8ab2d2e2
JK		 804 if (nr == BP_VECTOR || nr == OF_VECTOR) {
805 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
806 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
807 } else
808 intr_info |= INTR_TYPE_HARD_EXCEPTION;
809
810 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 811}
812
a75beee6
ED		 813/*
814 * Swap MSR entry in host/guest MSR entry array.
815 */
54e11fa1 816#ifdef CONFIG_X86_64
8b9cf98c 817static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 818{
a2fa3e9f
GH		 819 struct kvm_msr_entry tmp;
820
821 tmp = vmx->guest_msrs[to];
822 vmx->guest_msrs[to] = vmx->guest_msrs[from];
823 vmx->guest_msrs[from] = tmp;
824 tmp = vmx->host_msrs[to];
825 vmx->host_msrs[to] = vmx->host_msrs[from];
826 vmx->host_msrs[from] = tmp;
a75beee6 827}
54e11fa1 828#endif
a75beee6 829
e38aea3e
AK		 830/*
831 * Set up the vmcs to automatically save and restore system
832 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
833 * mode, as fiddling with msrs is very expensive.
834 */
8b9cf98c 835static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 836{
2cc51560 837 int save_nmsrs;
5897297b 838 unsigned long *msr_bitmap;
e38aea3e 839
33f9c505 840 vmx_load_host_state(vmx);
a75beee6
ED		 841 save_nmsrs = 0;
842#ifdef CONFIG_X86_64
8b9cf98c 843 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 844 int index;
845
8b9cf98c 846 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 847 if (index >= 0)
8b9cf98c
RR		 848 move_msr_up(vmx, index, save_nmsrs++);
849 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 850 if (index >= 0)
8b9cf98c
RR		 851 move_msr_up(vmx, index, save_nmsrs++);
852 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 853 if (index >= 0)
8b9cf98c
RR		 854 move_msr_up(vmx, index, save_nmsrs++);
855 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 856 if (index >= 0)
8b9cf98c 857 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 858 /*
859 * MSR_K6_STAR is only needed on long mode guests, and only
860 * if efer.sce is enabled.
861 */
8b9cf98c 862 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 863 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 864 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 865 }
866#endif
a2fa3e9f 867 vmx->save_nmsrs = save_nmsrs;
e38aea3e 868
4d56c8a7 869#ifdef CONFIG_X86_64
a2fa3e9f 870 vmx->msr_offset_kernel_gs_base =
8b9cf98c 871 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 872#endif
8b9cf98c 873 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 874
875 if (cpu_has_vmx_msr_bitmap()) {
876 if (is_long_mode(&vmx->vcpu))
877 msr_bitmap = vmx_msr_bitmap_longmode;
878 else
879 msr_bitmap = vmx_msr_bitmap_legacy;
880
881 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
882 }
e38aea3e
AK		 883}
884
6aa8b732
AK		 885/*
886 * reads and returns guest's timestamp counter "register"
887 * guest_tsc = host_tsc + tsc_offset -- 21.3
888 */
889static u64 guest_read_tsc(void)
890{
891 u64 host_tsc, tsc_offset;
892
893 rdtscll(host_tsc);
894 tsc_offset = vmcs_read64(TSC_OFFSET);
895 return host_tsc + tsc_offset;
896}
897
898/*
899 * writes 'guest_tsc' into guest's timestamp counter "register"
900 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
901 */
53f658b3 902static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 903{
6aa8b732
AK		 904 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
905}
906
6aa8b732
AK		 907/*
908 * Reads an msr value (of 'msr_index') into 'pdata'.
909 * Returns 0 on success, non-0 otherwise.
910 * Assumes vcpu_load() was already called.
911 */
912static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
913{
914 u64 data;
a2fa3e9f 915 struct kvm_msr_entry *msr;
6aa8b732
AK		 916
917 if (!pdata) {
918 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
919 return -EINVAL;
920 }
921
922 switch (msr_index) {
05b3e0c2 923#ifdef CONFIG_X86_64
6aa8b732
AK		 924 case MSR_FS_BASE:
925 data = vmcs_readl(GUEST_FS_BASE);
926 break;
927 case MSR_GS_BASE:
928 data = vmcs_readl(GUEST_GS_BASE);
929 break;
930 case MSR_EFER:
3bab1f5d 931 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 932#endif
933 case MSR_IA32_TIME_STAMP_COUNTER:
934 data = guest_read_tsc();
935 break;
936 case MSR_IA32_SYSENTER_CS:
937 data = vmcs_read32(GUEST_SYSENTER_CS);
938 break;
939 case MSR_IA32_SYSENTER_EIP:
f5b42c33 940 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 941 break;
942 case MSR_IA32_SYSENTER_ESP:
f5b42c33 943 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 944 break;
6aa8b732 945 default:
516a1a7e 946 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 947 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 948 if (msr) {
949 data = msr->data;
950 break;
6aa8b732 951 }
3bab1f5d 952 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 953 }
954
955 *pdata = data;
956 return 0;
957}
958
959/*
960 * Writes msr value into into the appropriate "register".
961 * Returns 0 on success, non-0 otherwise.
962 * Assumes vcpu_load() was already called.
963 */
964static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
965{
a2fa3e9f
GH		 966 struct vcpu_vmx *vmx = to_vmx(vcpu);
967 struct kvm_msr_entry *msr;
53f658b3 968 u64 host_tsc;
2cc51560
ED		 969 int ret = 0;
970
6aa8b732 971 switch (msr_index) {
3bab1f5d 972 case MSR_EFER:
a9b21b62 973 vmx_load_host_state(vmx);
2cc51560 974 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 975 break;
16175a79 976#ifdef CONFIG_X86_64
6aa8b732
AK		 977 case MSR_FS_BASE:
978 vmcs_writel(GUEST_FS_BASE, data);
979 break;
980 case MSR_GS_BASE:
981 vmcs_writel(GUEST_GS_BASE, data);
982 break;
983#endif
984 case MSR_IA32_SYSENTER_CS:
985 vmcs_write32(GUEST_SYSENTER_CS, data);
986 break;
987 case MSR_IA32_SYSENTER_EIP:
f5b42c33 988 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 989 break;
990 case MSR_IA32_SYSENTER_ESP:
f5b42c33 991 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 992 break;
d27d4aca 993 case MSR_IA32_TIME_STAMP_COUNTER:
53f658b3
MT		 994 rdtscll(host_tsc);
995 guest_write_tsc(data, host_tsc);
efa67e0d
CL		 996 break;
997 case MSR_P6_PERFCTR0:
998 case MSR_P6_PERFCTR1:
999 case MSR_P6_EVNTSEL0:
1000 case MSR_P6_EVNTSEL1:
1001 /*
1002 * Just discard all writes to the performance counters; this
1003 * should keep both older linux and windows 64-bit guests
1004 * happy
1005 */
1006 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
1007
6aa8b732 1008 break;
468d472f
SY		 1009 case MSR_IA32_CR_PAT:
1010 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1011 vmcs_write64(GUEST_IA32_PAT, data);
1012 vcpu->arch.pat = data;
1013 break;
1014 }
1015 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1016 default:
a9b21b62 1017 vmx_load_host_state(vmx);
8b9cf98c 1018 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 1019 if (msr) {
1020 msr->data = data;
1021 break;
6aa8b732 1022 }
2cc51560 1023 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1024 }
1025
2cc51560 1026 return ret;
6aa8b732
AK		 1027}
1028
5fdbf976 1029static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1030{
5fdbf976
MT		 1031 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1032 switch (reg) {
1033 case VCPU_REGS_RSP:
1034 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1035 break;
1036 case VCPU_REGS_RIP:
1037 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1038 break;
1039 default:
1040 break;
1041 }
6aa8b732
AK		 1042}
1043
d0bfb940 1044static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1045{
d0bfb940
JK		 1046 int old_debug = vcpu->guest_debug;
1047 unsigned long flags;
6aa8b732 1048
d0bfb940
JK		 1049 vcpu->guest_debug = dbg->control;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1051 vcpu->guest_debug = 0;
6aa8b732 1052
ae675ef0
JK		 1053 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1054 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1055 else
1056 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1057
d0bfb940
JK		 1058 flags = vmcs_readl(GUEST_RFLAGS);
1059 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1060 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1061 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1062 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1063 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1064
abd3f2d6 1065 update_exception_bitmap(vcpu);
6aa8b732
AK		 1066
1067 return 0;
1068}
1069
1070static __init int cpu_has_kvm_support(void)
1071{
6210e37b 1072 return cpu_has_vmx();
6aa8b732
AK		 1073}
1074
1075static __init int vmx_disabled_by_bios(void)
1076{
1077 u64 msr;
1078
1079 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1080 return (msr & (FEATURE_CONTROL_LOCKED |
1081 FEATURE_CONTROL_VMXON_ENABLED))
1082 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1083 /* locked but not enabled */
6aa8b732
AK		 1084}
1085
774c47f1 1086static void hardware_enable(void *garbage)
6aa8b732
AK		 1087{
1088 int cpu = raw_smp_processor_id();
1089 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1090 u64 old;
1091
543e4243 1092 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1093 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1094 if ((old & (FEATURE_CONTROL_LOCKED |
1095 FEATURE_CONTROL_VMXON_ENABLED))
1096 != (FEATURE_CONTROL_LOCKED |
1097 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1098 /* enable and lock */
62b3ffb8 1099 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1100 FEATURE_CONTROL_LOCKED |
1101 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1102 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1103 asm volatile (ASM_VMX_VMXON_RAX
1104 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1105 : "memory", "cc");
1106}
1107
543e4243
AK		 1108static void vmclear_local_vcpus(void)
1109{
1110 int cpu = raw_smp_processor_id();
1111 struct vcpu_vmx *vmx, *n;
1112
1113 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1114 local_vcpus_link)
1115 __vcpu_clear(vmx);
1116}
1117
710ff4a8
EH		 1118
1119/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1120 * tricks.
1121 */
1122static void kvm_cpu_vmxoff(void)
6aa8b732 1123{
4ecac3fd 1124 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1125 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1126}
1127
710ff4a8
EH		 1128static void hardware_disable(void *garbage)
1129{
1130 vmclear_local_vcpus();
1131 kvm_cpu_vmxoff();
1132}
1133
1c3d14fe 1134static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1135 u32 msr, u32 *result)
1c3d14fe
YS		 1136{
1137 u32 vmx_msr_low, vmx_msr_high;
1138 u32 ctl = ctl_min | ctl_opt;
1139
1140 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1141
1142 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1143 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1144
1145 /* Ensure minimum (required) set of control bits are supported. */
1146 if (ctl_min & ~ctl)
002c7f7c 1147 return -EIO;
1c3d14fe
YS		 1148
1149 *result = ctl;
1150 return 0;
1151}
1152
002c7f7c 1153static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1154{
1155 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1156 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1157 u32 _pin_based_exec_control = 0;
1158 u32 _cpu_based_exec_control = 0;
f78e0e2e 1159 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1160 u32 _vmexit_control = 0;
1161 u32 _vmentry_control = 0;
1162
1163 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1164 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1165 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1166 &_pin_based_exec_control) < 0)
002c7f7c 1167 return -EIO;
1c3d14fe
YS		 1168
1169 min = CPU_BASED_HLT_EXITING |
1170#ifdef CONFIG_X86_64
1171 CPU_BASED_CR8_LOAD_EXITING |
1172 CPU_BASED_CR8_STORE_EXITING |
1173#endif
d56f546d
SY		 1174 CPU_BASED_CR3_LOAD_EXITING |
1175 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1176 CPU_BASED_USE_IO_BITMAPS |
1177 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1178 CPU_BASED_USE_TSC_OFFSETING |
1179 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1180 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1181 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1182 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1183 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1184 &_cpu_based_exec_control) < 0)
002c7f7c 1185 return -EIO;
6e5d865c
YS		 1186#ifdef CONFIG_X86_64
1187 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1188 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1189 ~CPU_BASED_CR8_STORE_EXITING;
1190#endif
f78e0e2e 1191 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1192 min2 = 0;
1193 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1194 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1195 SECONDARY_EXEC_ENABLE_VPID |
1196 SECONDARY_EXEC_ENABLE_EPT;
1197 if (adjust_vmx_controls(min2, opt2,
1198 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1199 &_cpu_based_2nd_exec_control) < 0)
1200 return -EIO;
1201 }
1202#ifndef CONFIG_X86_64
1203 if (!(_cpu_based_2nd_exec_control &
1204 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1205 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1206#endif
d56f546d 1207 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1208 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1209 enabled */
d56f546d 1210 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1211 CPU_BASED_CR3_STORE_EXITING |
1212 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1213 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1214 &_cpu_based_exec_control) < 0)
1215 return -EIO;
1216 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1217 vmx_capability.ept, vmx_capability.vpid);
1218 }
1c3d14fe
YS		 1219
1220 min = 0;
1221#ifdef CONFIG_X86_64
1222 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1223#endif
468d472f 1224 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1225 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1226 &_vmexit_control) < 0)
002c7f7c 1227 return -EIO;
1c3d14fe 1228
468d472f
SY		 1229 min = 0;
1230 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1231 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1232 &_vmentry_control) < 0)
002c7f7c 1233 return -EIO;
6aa8b732 1234
c68876fd 1235 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1236
1237 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1238 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1239 return -EIO;
1c3d14fe
YS		 1240
1241#ifdef CONFIG_X86_64
1242 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1243 if (vmx_msr_high & (1u<<16))
002c7f7c 1244 return -EIO;
1c3d14fe
YS		 1245#endif
1246
1247 /* Require Write-Back (WB) memory type for VMCS accesses. */
1248 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1249 return -EIO;
1c3d14fe 1250
002c7f7c
YS		 1251 vmcs_conf->size = vmx_msr_high & 0x1fff;
1252 vmcs_conf->order = get_order(vmcs_config.size);
1253 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1254
002c7f7c
YS		 1255 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1256 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1257 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1258 vmcs_conf->vmexit_ctrl = _vmexit_control;
1259 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1260
1261 return 0;
c68876fd 1262}
6aa8b732
AK		 1263
1264static struct vmcs *alloc_vmcs_cpu(int cpu)
1265{
1266 int node = cpu_to_node(cpu);
1267 struct page *pages;
1268 struct vmcs *vmcs;
1269
1c3d14fe 1270 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1271 if (!pages)
1272 return NULL;
1273 vmcs = page_address(pages);
1c3d14fe
YS		 1274 memset(vmcs, 0, vmcs_config.size);
1275 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1276 return vmcs;
1277}
1278
1279static struct vmcs *alloc_vmcs(void)
1280{
d3b2c338 1281 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1282}
1283
1284static void free_vmcs(struct vmcs *vmcs)
1285{
1c3d14fe 1286 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1287}
1288
39959588 1289static void free_kvm_area(void)
6aa8b732
AK		 1290{
1291 int cpu;
1292
1293 for_each_online_cpu(cpu)
1294 free_vmcs(per_cpu(vmxarea, cpu));
1295}
1296
6aa8b732
AK		 1297static __init int alloc_kvm_area(void)
1298{
1299 int cpu;
1300
1301 for_each_online_cpu(cpu) {
1302 struct vmcs *vmcs;
1303
1304 vmcs = alloc_vmcs_cpu(cpu);
1305 if (!vmcs) {
1306 free_kvm_area();
1307 return -ENOMEM;
1308 }
1309
1310 per_cpu(vmxarea, cpu) = vmcs;
1311 }
1312 return 0;
1313}
1314
1315static __init int hardware_setup(void)
1316{
002c7f7c
YS		 1317 if (setup_vmcs_config(&vmcs_config) < 0)
1318 return -EIO;
50a37eb4
JR		 1319
1320 if (boot_cpu_has(X86_FEATURE_NX))
1321 kvm_enable_efer_bits(EFER_NX);
1322
93ba03c2
SY		 1323 if (!cpu_has_vmx_vpid())
1324 enable_vpid = 0;
1325
1326 if (!cpu_has_vmx_ept())
1327 enable_ept = 0;
1328
1329 if (!cpu_has_vmx_flexpriority())
1330 flexpriority_enabled = 0;
1331
95ba8273
GN		 1332 if (!cpu_has_vmx_tpr_shadow())
1333 kvm_x86_ops->update_cr8_intercept = NULL;
1334
6aa8b732
AK		 1335 return alloc_kvm_area();
1336}
1337
1338static __exit void hardware_unsetup(void)
1339{
1340 free_kvm_area();
1341}
1342
6aa8b732
AK		 1343static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1344{
1345 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1346
6af11b9e 1347 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1348 vmcs_write16(sf->selector, save->selector);
1349 vmcs_writel(sf->base, save->base);
1350 vmcs_write32(sf->limit, save->limit);
1351 vmcs_write32(sf->ar_bytes, save->ar);
1352 } else {
1353 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1354 << AR_DPL_SHIFT;
1355 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1356 }
1357}
1358
1359static void enter_pmode(struct kvm_vcpu *vcpu)
1360{
1361 unsigned long flags;
a89a8fb9 1362 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1363
a89a8fb9 1364 vmx->emulation_required = 1;
ad312c7c 1365 vcpu->arch.rmode.active = 0;
6aa8b732 1366
ad312c7c
ZX		 1367 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1368 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1369 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1370
1371 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1372 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1373 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1374 vmcs_writel(GUEST_RFLAGS, flags);
1375
66aee91a
RR		 1376 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1377 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1378
1379 update_exception_bitmap(vcpu);
1380
a89a8fb9
MG		 1381 if (emulate_invalid_guest_state)
1382 return;
1383
ad312c7c
ZX		 1384 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1385 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1386 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1387 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1388
1389 vmcs_write16(GUEST_SS_SELECTOR, 0);
1390 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1391
1392 vmcs_write16(GUEST_CS_SELECTOR,
1393 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1394 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1395}
1396
d77c26fc 1397static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1398{
bfc6d222 1399 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1400 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1401 kvm->memslots[0].npages - 3;
1402 return base_gfn << PAGE_SHIFT;
1403 }
bfc6d222 1404 return kvm->arch.tss_addr;
6aa8b732
AK		 1405}
1406
1407static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1408{
1409 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1410
1411 save->selector = vmcs_read16(sf->selector);
1412 save->base = vmcs_readl(sf->base);
1413 save->limit = vmcs_read32(sf->limit);
1414 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1415 vmcs_write16(sf->selector, save->base >> 4);
1416 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1417 vmcs_write32(sf->limit, 0xffff);
1418 vmcs_write32(sf->ar_bytes, 0xf3);
1419}
1420
1421static void enter_rmode(struct kvm_vcpu *vcpu)
1422{
1423 unsigned long flags;
a89a8fb9 1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1425
a89a8fb9 1426 vmx->emulation_required = 1;
ad312c7c 1427 vcpu->arch.rmode.active = 1;
6aa8b732 1428
ad312c7c 1429 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1430 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1431
ad312c7c 1432 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1433 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1434
ad312c7c 1435 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1436 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1437
1438 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1439 vcpu->arch.rmode.save_iopl
1440 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1441
053de044 1442 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1443
1444 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1445 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1446 update_exception_bitmap(vcpu);
1447
a89a8fb9
MG		 1448 if (emulate_invalid_guest_state)
1449 goto continue_rmode;
1450
6aa8b732
AK		 1451 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1452 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1453 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1454
1455 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1456 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1457 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1458 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1459 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1460
ad312c7c
ZX		 1461 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1462 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1463 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1464 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1465
a89a8fb9 1466continue_rmode:
8668a3c4 1467 kvm_mmu_reset_context(vcpu);
b7ebfb05 1468 init_rmode(vcpu->kvm);
6aa8b732
AK		 1469}
1470
401d10de
AS		 1471static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1472{
1473 struct vcpu_vmx *vmx = to_vmx(vcpu);
1474 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1475
1476 vcpu->arch.shadow_efer = efer;
1477 if (!msr)
1478 return;
1479 if (efer & EFER_LMA) {
1480 vmcs_write32(VM_ENTRY_CONTROLS,
1481 vmcs_read32(VM_ENTRY_CONTROLS) |
1482 VM_ENTRY_IA32E_MODE);
1483 msr->data = efer;
1484 } else {
1485 vmcs_write32(VM_ENTRY_CONTROLS,
1486 vmcs_read32(VM_ENTRY_CONTROLS) &
1487 ~VM_ENTRY_IA32E_MODE);
1488
1489 msr->data = efer & ~EFER_LME;
1490 }
1491 setup_msrs(vmx);
1492}
1493
05b3e0c2 1494#ifdef CONFIG_X86_64
6aa8b732
AK		 1495
1496static void enter_lmode(struct kvm_vcpu *vcpu)
1497{
1498 u32 guest_tr_ar;
1499
1500 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1501 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1502 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1503 __func__);
6aa8b732
AK		 1504 vmcs_write32(GUEST_TR_AR_BYTES,
1505 (guest_tr_ar & ~AR_TYPE_MASK)
1506 | AR_TYPE_BUSY_64_TSS);
1507 }
ad312c7c 1508 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1509 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1510}
1511
1512static void exit_lmode(struct kvm_vcpu *vcpu)
1513{
ad312c7c 1514 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1515
1516 vmcs_write32(VM_ENTRY_CONTROLS,
1517 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1518 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1519}
1520
1521#endif
1522
2384d2b3
SY		 1523static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1524{
1525 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1526 if (enable_ept)
4e1096d2 1527 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1528}
1529
25c4c276 1530static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1531{
ad312c7c
ZX		 1532 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1533 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1534}
1535
1439442c
SY		 1536static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1537{
1538 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1539 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1540 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1541 return;
1542 }
1543 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1544 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1545 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1546 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1547 }
1548}
1549
1550static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1551
1552static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1553 unsigned long cr0,
1554 struct kvm_vcpu *vcpu)
1555{
1556 if (!(cr0 & X86_CR0_PG)) {
1557 /* From paging/starting to nonpaging */
1558 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1559 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1560 (CPU_BASED_CR3_LOAD_EXITING |
1561 CPU_BASED_CR3_STORE_EXITING));
1562 vcpu->arch.cr0 = cr0;
1563 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1564 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1565 *hw_cr0 &= ~X86_CR0_WP;
1566 } else if (!is_paging(vcpu)) {
1567 /* From nonpaging to paging */
1568 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1569 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1570 ~(CPU_BASED_CR3_LOAD_EXITING |
1571 CPU_BASED_CR3_STORE_EXITING));
1572 vcpu->arch.cr0 = cr0;
1573 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1574 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1575 *hw_cr0 &= ~X86_CR0_WP;
1576 }
1577}
1578
1579static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1580 struct kvm_vcpu *vcpu)
1581{
1582 if (!is_paging(vcpu)) {
1583 *hw_cr4 &= ~X86_CR4_PAE;
1584 *hw_cr4 |= X86_CR4_PSE;
1585 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1586 *hw_cr4 &= ~X86_CR4_PAE;
1587}
1588
6aa8b732
AK		 1589static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1590{
1439442c
SY		 1591 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1592 KVM_VM_CR0_ALWAYS_ON;
1593
5fd86fcf
AK		 1594 vmx_fpu_deactivate(vcpu);
1595
ad312c7c 1596 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1597 enter_pmode(vcpu);
1598
ad312c7c 1599 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1600 enter_rmode(vcpu);
1601
05b3e0c2 1602#ifdef CONFIG_X86_64
ad312c7c 1603 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1604 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1605 enter_lmode(vcpu);
707d92fa 1606 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1607 exit_lmode(vcpu);
1608 }
1609#endif
1610
089d034e 1611 if (enable_ept)
1439442c
SY		 1612 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1613
6aa8b732 1614 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1615 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1616 vcpu->arch.cr0 = cr0;
5fd86fcf 1617
707d92fa 1618 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1619 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1620}
1621
1439442c
SY		 1622static u64 construct_eptp(unsigned long root_hpa)
1623{
1624 u64 eptp;
1625
1626 /* TODO write the value reading from MSR */
1627 eptp = VMX_EPT_DEFAULT_MT |
1628 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1629 eptp |= (root_hpa & PAGE_MASK);
1630
1631 return eptp;
1632}
1633
6aa8b732
AK		 1634static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1635{
1439442c
SY		 1636 unsigned long guest_cr3;
1637 u64 eptp;
1638
1639 guest_cr3 = cr3;
089d034e 1640 if (enable_ept) {
1439442c
SY		 1641 eptp = construct_eptp(cr3);
1642 vmcs_write64(EPT_POINTER, eptp);
1643 ept_sync_context(eptp);
1644 ept_load_pdptrs(vcpu);
1645 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1646 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1647 }
1648
2384d2b3 1649 vmx_flush_tlb(vcpu);
1439442c 1650 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1651 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1652 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1653}
1654
1655static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1656{
1439442c
SY		 1657 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1658 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1659
ad312c7c 1660 vcpu->arch.cr4 = cr4;
089d034e 1661 if (enable_ept)
1439442c
SY		 1662 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1663
1664 vmcs_writel(CR4_READ_SHADOW, cr4);
1665 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1666}
1667
6aa8b732
AK		 1668static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1669{
1670 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1671
1672 return vmcs_readl(sf->base);
1673}
1674
1675static void vmx_get_segment(struct kvm_vcpu *vcpu,
1676 struct kvm_segment *var, int seg)
1677{
1678 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1679 u32 ar;
1680
1681 var->base = vmcs_readl(sf->base);
1682 var->limit = vmcs_read32(sf->limit);
1683 var->selector = vmcs_read16(sf->selector);
1684 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1685 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1686 ar = 0;
1687 var->type = ar & 15;
1688 var->s = (ar >> 4) & 1;
1689 var->dpl = (ar >> 5) & 3;
1690 var->present = (ar >> 7) & 1;
1691 var->avl = (ar >> 12) & 1;
1692 var->l = (ar >> 13) & 1;
1693 var->db = (ar >> 14) & 1;
1694 var->g = (ar >> 15) & 1;
1695 var->unusable = (ar >> 16) & 1;
1696}
1697
2e4d2653
IE		 1698static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1699{
1700 struct kvm_segment kvm_seg;
1701
1702 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1703 return 0;
1704
1705 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1706 return 3;
1707
1708 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1709 return kvm_seg.selector & 3;
1710}
1711
653e3108 1712static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1713{
6aa8b732
AK		 1714 u32 ar;
1715
653e3108 1716 if (var->unusable)
6aa8b732
AK		 1717 ar = 1 << 16;
1718 else {
1719 ar = var->type & 15;
1720 ar |= (var->s & 1) << 4;
1721 ar |= (var->dpl & 3) << 5;
1722 ar |= (var->present & 1) << 7;
1723 ar |= (var->avl & 1) << 12;
1724 ar |= (var->l & 1) << 13;
1725 ar |= (var->db & 1) << 14;
1726 ar |= (var->g & 1) << 15;
1727 }
f7fbf1fd
UL		 1728 if (ar == 0) /* a 0 value means unusable */
1729 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1730
1731 return ar;
1732}
1733
1734static void vmx_set_segment(struct kvm_vcpu *vcpu,
1735 struct kvm_segment *var, int seg)
1736{
1737 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1738 u32 ar;
1739
ad312c7c
ZX		 1740 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1741 vcpu->arch.rmode.tr.selector = var->selector;
1742 vcpu->arch.rmode.tr.base = var->base;
1743 vcpu->arch.rmode.tr.limit = var->limit;
1744 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1745 return;
1746 }
1747 vmcs_writel(sf->base, var->base);
1748 vmcs_write32(sf->limit, var->limit);
1749 vmcs_write16(sf->selector, var->selector);
ad312c7c 1750 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1751 /*
1752 * Hack real-mode segments into vm86 compatibility.
1753 */
1754 if (var->base == 0xffff0000 && var->selector == 0xf000)
1755 vmcs_writel(sf->base, 0xf0000);
1756 ar = 0xf3;
1757 } else
1758 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1759 vmcs_write32(sf->ar_bytes, ar);
1760}
1761
6aa8b732
AK		 1762static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1763{
1764 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1765
1766 *db = (ar >> 14) & 1;
1767 *l = (ar >> 13) & 1;
1768}
1769
1770static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1771{
1772 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1773 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1774}
1775
1776static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1777{
1778 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1779 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1780}
1781
1782static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1783{
1784 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1785 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1786}
1787
1788static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1789{
1790 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1791 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1792}
1793
648dfaa7
MG		 1794static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1795{
1796 struct kvm_segment var;
1797 u32 ar;
1798
1799 vmx_get_segment(vcpu, &var, seg);
1800 ar = vmx_segment_access_rights(&var);
1801
1802 if (var.base != (var.selector << 4))
1803 return false;
1804 if (var.limit != 0xffff)
1805 return false;
1806 if (ar != 0xf3)
1807 return false;
1808
1809 return true;
1810}
1811
1812static bool code_segment_valid(struct kvm_vcpu *vcpu)
1813{
1814 struct kvm_segment cs;
1815 unsigned int cs_rpl;
1816
1817 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1818 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1819
1872a3f4
AK		 1820 if (cs.unusable)
1821 return false;
648dfaa7
MG		 1822 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1823 return false;
1824 if (!cs.s)
1825 return false;
1872a3f4 1826 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1827 if (cs.dpl > cs_rpl)
1828 return false;
1872a3f4 1829 } else {
648dfaa7
MG		 1830 if (cs.dpl != cs_rpl)
1831 return false;
1832 }
1833 if (!cs.present)
1834 return false;
1835
1836 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1837 return true;
1838}
1839
1840static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1841{
1842 struct kvm_segment ss;
1843 unsigned int ss_rpl;
1844
1845 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1846 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1847
1872a3f4
AK		 1848 if (ss.unusable)
1849 return true;
1850 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1851 return false;
1852 if (!ss.s)
1853 return false;
1854 if (ss.dpl != ss_rpl) /* DPL != RPL */
1855 return false;
1856 if (!ss.present)
1857 return false;
1858
1859 return true;
1860}
1861
1862static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1863{
1864 struct kvm_segment var;
1865 unsigned int rpl;
1866
1867 vmx_get_segment(vcpu, &var, seg);
1868 rpl = var.selector & SELECTOR_RPL_MASK;
1869
1872a3f4
AK		 1870 if (var.unusable)
1871 return true;
648dfaa7
MG		 1872 if (!var.s)
1873 return false;
1874 if (!var.present)
1875 return false;
1876 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1877 if (var.dpl < rpl) /* DPL < RPL */
1878 return false;
1879 }
1880
1881 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1882 * rights flags
1883 */
1884 return true;
1885}
1886
1887static bool tr_valid(struct kvm_vcpu *vcpu)
1888{
1889 struct kvm_segment tr;
1890
1891 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1892
1872a3f4
AK		 1893 if (tr.unusable)
1894 return false;
648dfaa7
MG		 1895 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1896 return false;
1872a3f4 1897 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1898 return false;
1899 if (!tr.present)
1900 return false;
1901
1902 return true;
1903}
1904
1905static bool ldtr_valid(struct kvm_vcpu *vcpu)
1906{
1907 struct kvm_segment ldtr;
1908
1909 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1910
1872a3f4
AK		 1911 if (ldtr.unusable)
1912 return true;
648dfaa7
MG		 1913 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1914 return false;
1915 if (ldtr.type != 2)
1916 return false;
1917 if (!ldtr.present)
1918 return false;
1919
1920 return true;
1921}
1922
1923static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1924{
1925 struct kvm_segment cs, ss;
1926
1927 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1928 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1929
1930 return ((cs.selector & SELECTOR_RPL_MASK) ==
1931 (ss.selector & SELECTOR_RPL_MASK));
1932}
1933
1934/*
1935 * Check if guest state is valid. Returns true if valid, false if
1936 * not.
1937 * We assume that registers are always usable
1938 */
1939static bool guest_state_valid(struct kvm_vcpu *vcpu)
1940{
1941 /* real mode guest state checks */
1942 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1943 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1944 return false;
1945 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1946 return false;
1947 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1948 return false;
1949 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1950 return false;
1951 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1952 return false;
1953 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1954 return false;
1955 } else {
1956 /* protected mode guest state checks */
1957 if (!cs_ss_rpl_check(vcpu))
1958 return false;
1959 if (!code_segment_valid(vcpu))
1960 return false;
1961 if (!stack_segment_valid(vcpu))
1962 return false;
1963 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1964 return false;
1965 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1966 return false;
1967 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1968 return false;
1969 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1970 return false;
1971 if (!tr_valid(vcpu))
1972 return false;
1973 if (!ldtr_valid(vcpu))
1974 return false;
1975 }
1976 /* TODO:
1977 * - Add checks on RIP
1978 * - Add checks on RFLAGS
1979 */
1980
1981 return true;
1982}
1983
d77c26fc 1984static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1985{
6aa8b732 1986 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1987 u16 data = 0;
10589a46 1988 int ret = 0;
195aefde 1989 int r;
6aa8b732 1990
195aefde
IE		 1991 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1992 if (r < 0)
10589a46 1993 goto out;
195aefde 1994 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1995 r = kvm_write_guest_page(kvm, fn++, &data,
1996 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1997 if (r < 0)
10589a46 1998 goto out;
195aefde
IE		 1999 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2000 if (r < 0)
10589a46 2001 goto out;
195aefde
IE		 2002 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2003 if (r < 0)
10589a46 2004 goto out;
195aefde 2005 data = ~0;
10589a46
MT		 2006 r = kvm_write_guest_page(kvm, fn, &data,
2007 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2008 sizeof(u8));
195aefde 2009 if (r < 0)
10589a46
MT		 2010 goto out;
2011
2012 ret = 1;
2013out:
10589a46 2014 return ret;
6aa8b732
AK		 2015}
2016
b7ebfb05
SY		 2017static int init_rmode_identity_map(struct kvm *kvm)
2018{
2019 int i, r, ret;
2020 pfn_t identity_map_pfn;
2021 u32 tmp;
2022
089d034e 2023 if (!enable_ept)
b7ebfb05
SY		 2024 return 1;
2025 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2026 printk(KERN_ERR "EPT: identity-mapping pagetable "
2027 "haven't been allocated!\n");
2028 return 0;
2029 }
2030 if (likely(kvm->arch.ept_identity_pagetable_done))
2031 return 1;
2032 ret = 0;
2033 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2034 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2035 if (r < 0)
2036 goto out;
2037 /* Set up identity-mapping pagetable for EPT in real mode */
2038 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2039 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2040 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2041 r = kvm_write_guest_page(kvm, identity_map_pfn,
2042 &tmp, i * sizeof(tmp), sizeof(tmp));
2043 if (r < 0)
2044 goto out;
2045 }
2046 kvm->arch.ept_identity_pagetable_done = true;
2047 ret = 1;
2048out:
2049 return ret;
2050}
2051
6aa8b732
AK		 2052static void seg_setup(int seg)
2053{
2054 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2055
2056 vmcs_write16(sf->selector, 0);
2057 vmcs_writel(sf->base, 0);
2058 vmcs_write32(sf->limit, 0xffff);
a16b20da 2059 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2060}
2061
f78e0e2e
SY		 2062static int alloc_apic_access_page(struct kvm *kvm)
2063{
2064 struct kvm_userspace_memory_region kvm_userspace_mem;
2065 int r = 0;
2066
72dc67a6 2067 down_write(&kvm->slots_lock);
bfc6d222 2068 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2069 goto out;
2070 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2071 kvm_userspace_mem.flags = 0;
2072 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2073 kvm_userspace_mem.memory_size = PAGE_SIZE;
2074 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2075 if (r)
2076 goto out;
72dc67a6 2077
bfc6d222 2078 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2079out:
72dc67a6 2080 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2081 return r;
2082}
2083
b7ebfb05
SY		 2084static int alloc_identity_pagetable(struct kvm *kvm)
2085{
2086 struct kvm_userspace_memory_region kvm_userspace_mem;
2087 int r = 0;
2088
2089 down_write(&kvm->slots_lock);
2090 if (kvm->arch.ept_identity_pagetable)
2091 goto out;
2092 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2093 kvm_userspace_mem.flags = 0;
2094 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2095 kvm_userspace_mem.memory_size = PAGE_SIZE;
2096 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2097 if (r)
2098 goto out;
2099
b7ebfb05
SY		 2100 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2101 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2102out:
2103 up_write(&kvm->slots_lock);
2104 return r;
2105}
2106
2384d2b3
SY		 2107static void allocate_vpid(struct vcpu_vmx *vmx)
2108{
2109 int vpid;
2110
2111 vmx->vpid = 0;
919818ab 2112 if (!enable_vpid)
2384d2b3
SY		 2113 return;
2114 spin_lock(&vmx_vpid_lock);
2115 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2116 if (vpid < VMX_NR_VPIDS) {
2117 vmx->vpid = vpid;
2118 __set_bit(vpid, vmx_vpid_bitmap);
2119 }
2120 spin_unlock(&vmx_vpid_lock);
2121}
2122
5897297b 2123static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2124{
3e7c73e9 2125 int f = sizeof(unsigned long);
25c5f225
SY		 2126
2127 if (!cpu_has_vmx_msr_bitmap())
2128 return;
2129
2130 /*
2131 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2132 * have the write-low and read-high bitmap offsets the wrong way round.
2133 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2134 */
25c5f225 2135 if (msr <= 0x1fff) {
3e7c73e9
AK		 2136 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2137 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2138 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2139 msr &= 0x1fff;
3e7c73e9
AK		 2140 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2141 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2142 }
25c5f225
SY		 2143}
2144
5897297b
AK		 2145static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2146{
2147 if (!longmode_only)
2148 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2149 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2150}
2151
6aa8b732
AK		 2152/*
2153 * Sets up the vmcs for emulated real mode.
2154 */
8b9cf98c 2155static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2156{
468d472f 2157 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2158 u32 junk;
53f658b3 2159 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2160 unsigned long a;
2161 struct descriptor_table dt;
2162 int i;
cd2276a7 2163 unsigned long kvm_vmx_return;
6e5d865c 2164 u32 exec_control;
6aa8b732 2165
6aa8b732 2166 /* I/O */
3e7c73e9
AK		 2167 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2168 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2169
25c5f225 2170 if (cpu_has_vmx_msr_bitmap())
5897297b 2171 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2172
6aa8b732
AK		 2173 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2174
6aa8b732 2175 /* Control */
1c3d14fe
YS		 2176 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2177 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2178
2179 exec_control = vmcs_config.cpu_based_exec_ctrl;
2180 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2181 exec_control &= ~CPU_BASED_TPR_SHADOW;
2182#ifdef CONFIG_X86_64
2183 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2184 CPU_BASED_CR8_LOAD_EXITING;
2185#endif
2186 }
089d034e 2187 if (!enable_ept)
d56f546d 2188 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2189 CPU_BASED_CR3_LOAD_EXITING |
2190 CPU_BASED_INVLPG_EXITING;
6e5d865c 2191 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2192
83ff3b9d
SY		 2193 if (cpu_has_secondary_exec_ctrls()) {
2194 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2195 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2196 exec_control &=
2197 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2198 if (vmx->vpid == 0)
2199 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2200 if (!enable_ept)
d56f546d 2201 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2202 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2203 }
f78e0e2e 2204
c7addb90
AK		 2205 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2206 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2207 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2208
2209 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2210 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2211 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2212
2213 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2214 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2215 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2216 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2217 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2218 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2219#ifdef CONFIG_X86_64
6aa8b732
AK		 2220 rdmsrl(MSR_FS_BASE, a);
2221 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2222 rdmsrl(MSR_GS_BASE, a);
2223 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2224#else
2225 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2226 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2227#endif
2228
2229 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2230
d6e88aec 2231 kvm_get_idt(&dt);
6aa8b732
AK		 2232 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2233
d77c26fc 2234 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2235 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2236 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2237 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2239
2240 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2241 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2242 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2243 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2244 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2245 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2246
468d472f
SY		 2247 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2248 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2249 host_pat = msr_low | ((u64) msr_high << 32);
2250 vmcs_write64(HOST_IA32_PAT, host_pat);
2251 }
2252 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2253 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2254 host_pat = msr_low | ((u64) msr_high << 32);
2255 /* Write the default value follow host pat */
2256 vmcs_write64(GUEST_IA32_PAT, host_pat);
2257 /* Keep arch.pat sync with GUEST_IA32_PAT */
2258 vmx->vcpu.arch.pat = host_pat;
2259 }
2260
6aa8b732
AK		 2261 for (i = 0; i < NR_VMX_MSR; ++i) {
2262 u32 index = vmx_msr_index[i];
2263 u32 data_low, data_high;
2264 u64 data;
a2fa3e9f 2265 int j = vmx->nmsrs;
6aa8b732
AK		 2266
2267 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2268 continue;
432bd6cb
AK		 2269 if (wrmsr_safe(index, data_low, data_high) < 0)
2270 continue;
6aa8b732 2271 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2272 vmx->host_msrs[j].index = index;
2273 vmx->host_msrs[j].reserved = 0;
2274 vmx->host_msrs[j].data = data;
2275 vmx->guest_msrs[j] = vmx->host_msrs[j];
2276 ++vmx->nmsrs;
6aa8b732 2277 }
6aa8b732 2278
1c3d14fe 2279 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2280
2281 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2282 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2283
e00c8cf2
AK		 2284 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2285 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2286
53f658b3
MT		 2287 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2288 rdtscll(tsc_this);
2289 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2290 tsc_base = tsc_this;
2291
2292 guest_write_tsc(0, tsc_base);
f78e0e2e 2293
e00c8cf2
AK		 2294 return 0;
2295}
2296
b7ebfb05
SY		 2297static int init_rmode(struct kvm *kvm)
2298{
2299 if (!init_rmode_tss(kvm))
2300 return 0;
2301 if (!init_rmode_identity_map(kvm))
2302 return 0;
2303 return 1;
2304}
2305
e00c8cf2
AK		 2306static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2307{
2308 struct vcpu_vmx *vmx = to_vmx(vcpu);
2309 u64 msr;
2310 int ret;
2311
5fdbf976 2312 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2313 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2314 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2315 ret = -ENOMEM;
2316 goto out;
2317 }
2318
ad312c7c 2319 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2320
3b86cd99
JK		 2321 vmx->soft_vnmi_blocked = 0;
2322
ad312c7c 2323 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2324 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2325 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2326 if (vmx->vcpu.vcpu_id == 0)
2327 msr |= MSR_IA32_APICBASE_BSP;
2328 kvm_set_apic_base(&vmx->vcpu, msr);
2329
2330 fx_init(&vmx->vcpu);
2331
5706be0d 2332 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2333 /*
2334 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2335 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2336 */
2337 if (vmx->vcpu.vcpu_id == 0) {
2338 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2339 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2340 } else {
ad312c7c
ZX		 2341 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2342 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2343 }
e00c8cf2
AK		 2344
2345 seg_setup(VCPU_SREG_DS);
2346 seg_setup(VCPU_SREG_ES);
2347 seg_setup(VCPU_SREG_FS);
2348 seg_setup(VCPU_SREG_GS);
2349 seg_setup(VCPU_SREG_SS);
2350
2351 vmcs_write16(GUEST_TR_SELECTOR, 0);
2352 vmcs_writel(GUEST_TR_BASE, 0);
2353 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2354 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2355
2356 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2357 vmcs_writel(GUEST_LDTR_BASE, 0);
2358 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2359 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2360
2361 vmcs_write32(GUEST_SYSENTER_CS, 0);
2362 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2363 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2364
2365 vmcs_writel(GUEST_RFLAGS, 0x02);
2366 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2367 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2368 else
5fdbf976
MT		 2369 kvm_rip_write(vcpu, 0);
2370 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2371
e00c8cf2
AK		 2372 vmcs_writel(GUEST_DR7, 0x400);
2373
2374 vmcs_writel(GUEST_GDTR_BASE, 0);
2375 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2376
2377 vmcs_writel(GUEST_IDTR_BASE, 0);
2378 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2379
2380 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2381 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2382 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2383
e00c8cf2
AK		 2384 /* Special registers */
2385 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2386
2387 setup_msrs(vmx);
2388
6aa8b732
AK		 2389 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2390
f78e0e2e
SY		 2391 if (cpu_has_vmx_tpr_shadow()) {
2392 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2393 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2394 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2395 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2396 vmcs_write32(TPR_THRESHOLD, 0);
2397 }
2398
2399 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2400 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2401 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2402
2384d2b3
SY		 2403 if (vmx->vpid != 0)
2404 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2405
ad312c7c
ZX		 2406 vmx->vcpu.arch.cr0 = 0x60000010;
2407 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2408 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2409 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2410 vmx_fpu_activate(&vmx->vcpu);
2411 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2412
2384d2b3
SY		 2413 vpid_sync_vcpu_all(vmx);
2414
3200f405 2415 ret = 0;
6aa8b732 2416
a89a8fb9
MG		 2417 /* HACK: Don't enable emulation on guest boot/reset */
2418 vmx->emulation_required = 0;
2419
6aa8b732 2420out:
3200f405 2421 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2422 return ret;
2423}
2424
3b86cd99
JK		 2425static void enable_irq_window(struct kvm_vcpu *vcpu)
2426{
2427 u32 cpu_based_vm_exec_control;
2428
2429 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2430 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2431 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2432}
2433
2434static void enable_nmi_window(struct kvm_vcpu *vcpu)
2435{
2436 u32 cpu_based_vm_exec_control;
2437
2438 if (!cpu_has_virtual_nmis()) {
2439 enable_irq_window(vcpu);
2440 return;
2441 }
2442
2443 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2444 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2445 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2446}
2447
85f455f7
ED		 2448static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2449{
9c8cba37
AK		 2450 struct vcpu_vmx *vmx = to_vmx(vcpu);
2451
2714d1d3
FEL		 2452 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2453
fa89a817 2454 ++vcpu->stat.irq_injections;
ad312c7c 2455 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2456 vmx->rmode.irq.pending = true;
2457 vmx->rmode.irq.vector = irq;
5fdbf976 2458 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2459 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2460 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2461 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2462 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2463 return;
2464 }
2465 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2466 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2467}
2468
f08864b4
SY		 2469static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2470{
66a5a347
JK		 2471 struct vcpu_vmx *vmx = to_vmx(vcpu);
2472
3b86cd99
JK		 2473 if (!cpu_has_virtual_nmis()) {
2474 /*
2475 * Tracking the NMI-blocked state in software is built upon
2476 * finding the next open IRQ window. This, in turn, depends on
2477 * well-behaving guests: They have to keep IRQs disabled at
2478 * least as long as the NMI handler runs. Otherwise we may
2479 * cause NMI nesting, maybe breaking the guest. But as this is
2480 * highly unlikely, we can live with the residual risk.
2481 */
2482 vmx->soft_vnmi_blocked = 1;
2483 vmx->vnmi_blocked_time = 0;
2484 }
2485
487b391d 2486 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2487 if (vcpu->arch.rmode.active) {
2488 vmx->rmode.irq.pending = true;
2489 vmx->rmode.irq.vector = NMI_VECTOR;
2490 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2491 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2492 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2493 INTR_INFO_VALID_MASK);
2494 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2495 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2496 return;
2497 }
f08864b4
SY		 2498 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2499 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2500}
2501
c4282df9 2502static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2503{
3b86cd99 2504 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2505 return 0;
33f089ca 2506
c4282df9
GN		 2507 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2508 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2509 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2510}
2511
78646121
GN		 2512static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2513{
c4282df9
GN		 2514 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2515 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2516 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2517}
2518
cbc94022
IE		 2519static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2520{
2521 int ret;
2522 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2523 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2524 .guest_phys_addr = addr,
2525 .memory_size = PAGE_SIZE * 3,
2526 .flags = 0,
2527 };
2528
2529 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2530 if (ret)
2531 return ret;
bfc6d222 2532 kvm->arch.tss_addr = addr;
cbc94022
IE		 2533 return 0;
2534}
2535
6aa8b732
AK		 2536static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2537 int vec, u32 err_code)
2538{
b3f37707
NK		 2539 /*
2540 * Instruction with address size override prefix opcode 0x67
2541 * Cause the #SS fault with 0 error code in VM86 mode.
2542 */
2543 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2544 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2545 return 1;
77ab6db0
JK		 2546 /*
2547 * Forward all other exceptions that are valid in real mode.
2548 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2549 * the required debugging infrastructure rework.
2550 */
2551 switch (vec) {
77ab6db0 2552 case DB_VECTOR:
d0bfb940
JK		 2553 if (vcpu->guest_debug &
2554 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2555 return 0;
2556 kvm_queue_exception(vcpu, vec);
2557 return 1;
77ab6db0 2558 case BP_VECTOR:
d0bfb940
JK		 2559 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2560 return 0;
2561 /* fall through */
2562 case DE_VECTOR:
77ab6db0
JK		 2563 case OF_VECTOR:
2564 case BR_VECTOR:
2565 case UD_VECTOR:
2566 case DF_VECTOR:
2567 case SS_VECTOR:
2568 case GP_VECTOR:
2569 case MF_VECTOR:
2570 kvm_queue_exception(vcpu, vec);
2571 return 1;
2572 }
6aa8b732
AK		 2573 return 0;
2574}
2575
2576static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2577{
1155f76a 2578 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2579 u32 intr_info, ex_no, error_code;
42dbaa5a 2580 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2581 u32 vect_info;
2582 enum emulation_result er;
2583
1155f76a 2584 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2585 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2586
2587 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2588 !is_page_fault(intr_info))
6aa8b732 2589 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2590 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2591
e4a41889 2592 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2593 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2594
2595 if (is_no_device(intr_info)) {
5fd86fcf 2596 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2597 return 1;
2598 }
2599
7aa81cc0 2600 if (is_invalid_opcode(intr_info)) {
571008da 2601 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2602 if (er != EMULATE_DONE)
7ee5d940 2603 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2604 return 1;
2605 }
2606
6aa8b732 2607 error_code = 0;
5fdbf976 2608 rip = kvm_rip_read(vcpu);
2e11384c 2609 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2610 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2611 if (is_page_fault(intr_info)) {
1439442c 2612 /* EPT won't cause page fault directly */
089d034e 2613 if (enable_ept)
1439442c 2614 BUG();
6aa8b732 2615 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2616 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2617 (u32)((u64)cr2 >> 32), handler);
3298b75c 2618 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2619 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2620 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2621 }
2622
ad312c7c 2623 if (vcpu->arch.rmode.active &&
6aa8b732 2624 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2625 error_code)) {
ad312c7c
ZX		 2626 if (vcpu->arch.halt_request) {
2627 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2628 return kvm_emulate_halt(vcpu);
2629 }
6aa8b732 2630 return 1;
72d6e5a0 2631 }
6aa8b732 2632
d0bfb940 2633 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2634 switch (ex_no) {
2635 case DB_VECTOR:
2636 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2637 if (!(vcpu->guest_debug &
2638 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2639 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2640 kvm_queue_exception(vcpu, DB_VECTOR);
2641 return 1;
2642 }
2643 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2644 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2645 /* fall through */
2646 case BP_VECTOR:
6aa8b732 2647 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2648 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2649 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2650 break;
2651 default:
d0bfb940
JK		 2652 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2653 kvm_run->ex.exception = ex_no;
2654 kvm_run->ex.error_code = error_code;
42dbaa5a 2655 break;
6aa8b732 2656 }
6aa8b732
AK		 2657 return 0;
2658}
2659
2660static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2661 struct kvm_run *kvm_run)
2662{
1165f5fe 2663 ++vcpu->stat.irq_exits;
2714d1d3 2664 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2665 return 1;
2666}
2667
988ad74f
AK		 2668static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2669{
2670 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2671 return 0;
2672}
6aa8b732 2673
6aa8b732
AK		 2674static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2675{
bfdaab09 2676 unsigned long exit_qualification;
34c33d16 2677 int size, in, string;
039576c0 2678 unsigned port;
6aa8b732 2679
1165f5fe 2680 ++vcpu->stat.io_exits;
bfdaab09 2681 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2682 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2683
2684 if (string) {
3427318f
LV		 2685 if (emulate_instruction(vcpu,
2686 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2687 return 0;
2688 return 1;
2689 }
2690
2691 size = (exit_qualification & 7) + 1;
2692 in = (exit_qualification & 8) != 0;
039576c0 2693 port = exit_qualification >> 16;
e70669ab 2694
e93f36bc 2695 skip_emulated_instruction(vcpu);
3090dd73 2696 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2697}
2698
102d8325
IM		 2699static void
2700vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2701{
2702 /*
2703 * Patch in the VMCALL instruction:
2704 */
2705 hypercall[0] = 0x0f;
2706 hypercall[1] = 0x01;
2707 hypercall[2] = 0xc1;
102d8325
IM		 2708}
2709
6aa8b732
AK		 2710static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2711{
bfdaab09 2712 unsigned long exit_qualification;
6aa8b732
AK		 2713 int cr;
2714 int reg;
2715
bfdaab09 2716 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2717 cr = exit_qualification & 15;
2718 reg = (exit_qualification >> 8) & 15;
2719 switch ((exit_qualification >> 4) & 3) {
2720 case 0: /* mov to cr */
5fdbf976
MT		 2721 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2722 (u32)kvm_register_read(vcpu, reg),
2723 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2724 handler);
6aa8b732
AK		 2725 switch (cr) {
2726 case 0:
5fdbf976 2727 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2728 skip_emulated_instruction(vcpu);
2729 return 1;
2730 case 3:
5fdbf976 2731 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2732 skip_emulated_instruction(vcpu);
2733 return 1;
2734 case 4:
5fdbf976 2735 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2736 skip_emulated_instruction(vcpu);
2737 return 1;
0a5fff19
GN		 2738 case 8: {
2739 u8 cr8_prev = kvm_get_cr8(vcpu);
2740 u8 cr8 = kvm_register_read(vcpu, reg);
2741 kvm_set_cr8(vcpu, cr8);
2742 skip_emulated_instruction(vcpu);
2743 if (irqchip_in_kernel(vcpu->kvm))
2744 return 1;
2745 if (cr8_prev <= cr8)
2746 return 1;
2747 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2748 return 0;
2749 }
6aa8b732
AK		 2750 };
2751 break;
25c4c276 2752 case 2: /* clts */
5fd86fcf 2753 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2754 vcpu->arch.cr0 &= ~X86_CR0_TS;
2755 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2756 vmx_fpu_activate(vcpu);
2714d1d3 2757 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2758 skip_emulated_instruction(vcpu);
2759 return 1;
6aa8b732
AK		 2760 case 1: /*mov from cr*/
2761 switch (cr) {
2762 case 3:
5fdbf976 2763 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2764 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2765 (u32)kvm_register_read(vcpu, reg),
2766 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2767 handler);
6aa8b732
AK		 2768 skip_emulated_instruction(vcpu);
2769 return 1;
2770 case 8:
5fdbf976 2771 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2772 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2773 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2774 skip_emulated_instruction(vcpu);
2775 return 1;
2776 }
2777 break;
2778 case 3: /* lmsw */
2d3ad1f4 2779 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2780
2781 skip_emulated_instruction(vcpu);
2782 return 1;
2783 default:
2784 break;
2785 }
2786 kvm_run->exit_reason = 0;
f0242478 2787 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2788 (int)(exit_qualification >> 4) & 3, cr);
2789 return 0;
2790}
2791
2792static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2793{
bfdaab09 2794 unsigned long exit_qualification;
6aa8b732
AK		 2795 unsigned long val;
2796 int dr, reg;
2797
42dbaa5a
JK		 2798 dr = vmcs_readl(GUEST_DR7);
2799 if (dr & DR7_GD) {
2800 /*
2801 * As the vm-exit takes precedence over the debug trap, we
2802 * need to emulate the latter, either for the host or the
2803 * guest debugging itself.
2804 */
2805 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2806 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2807 kvm_run->debug.arch.dr7 = dr;
2808 kvm_run->debug.arch.pc =
2809 vmcs_readl(GUEST_CS_BASE) +
2810 vmcs_readl(GUEST_RIP);
2811 kvm_run->debug.arch.exception = DB_VECTOR;
2812 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2813 return 0;
2814 } else {
2815 vcpu->arch.dr7 &= ~DR7_GD;
2816 vcpu->arch.dr6 |= DR6_BD;
2817 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2818 kvm_queue_exception(vcpu, DB_VECTOR);
2819 return 1;
2820 }
2821 }
2822
bfdaab09 2823 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2824 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2825 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2826 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2827 switch (dr) {
42dbaa5a
JK		 2828 case 0 ... 3:
2829 val = vcpu->arch.db[dr];
2830 break;
6aa8b732 2831 case 6:
42dbaa5a 2832 val = vcpu->arch.dr6;
6aa8b732
AK		 2833 break;
2834 case 7:
42dbaa5a 2835 val = vcpu->arch.dr7;
6aa8b732
AK		 2836 break;
2837 default:
2838 val = 0;
2839 }
5fdbf976 2840 kvm_register_write(vcpu, reg, val);
2714d1d3 2841 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2842 } else {
42dbaa5a
JK		 2843 val = vcpu->arch.regs[reg];
2844 switch (dr) {
2845 case 0 ... 3:
2846 vcpu->arch.db[dr] = val;
2847 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2848 vcpu->arch.eff_db[dr] = val;
2849 break;
2850 case 4 ... 5:
2851 if (vcpu->arch.cr4 & X86_CR4_DE)
2852 kvm_queue_exception(vcpu, UD_VECTOR);
2853 break;
2854 case 6:
2855 if (val & 0xffffffff00000000ULL) {
2856 kvm_queue_exception(vcpu, GP_VECTOR);
2857 break;
2858 }
2859 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2860 break;
2861 case 7:
2862 if (val & 0xffffffff00000000ULL) {
2863 kvm_queue_exception(vcpu, GP_VECTOR);
2864 break;
2865 }
2866 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2867 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2868 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2869 vcpu->arch.switch_db_regs =
2870 (val & DR7_BP_EN_MASK);
2871 }
2872 break;
2873 }
2874 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2875 }
6aa8b732
AK		 2876 skip_emulated_instruction(vcpu);
2877 return 1;
2878}
2879
2880static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2881{
06465c5a
AK		 2882 kvm_emulate_cpuid(vcpu);
2883 return 1;
6aa8b732
AK		 2884}
2885
2886static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2887{
ad312c7c 2888 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2889 u64 data;
2890
2891 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2892 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2893 return 1;
2894 }
2895
2714d1d3
FEL		 2896 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2897 handler);
2898
6aa8b732 2899 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2900 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2901 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2902 skip_emulated_instruction(vcpu);
2903 return 1;
2904}
2905
2906static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2907{
ad312c7c
ZX		 2908 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2909 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2910 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2911
2714d1d3
FEL		 2912 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2913 handler);
2914
6aa8b732 2915 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2916 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2917 return 1;
2918 }
2919
2920 skip_emulated_instruction(vcpu);
2921 return 1;
2922}
2923
6e5d865c
YS		 2924static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2925 struct kvm_run *kvm_run)
2926{
2927 return 1;
2928}
2929
6aa8b732
AK		 2930static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2931 struct kvm_run *kvm_run)
2932{
85f455f7
ED		 2933 u32 cpu_based_vm_exec_control;
2934
2935 /* clear pending irq */
2936 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2937 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2938 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2939
2940 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2941 ++vcpu->stat.irq_window_exits;
2714d1d3 2942
c1150d8c
DL		 2943 /*
2944 * If the user space waits to inject interrupts, exit as soon as
2945 * possible
2946 */
8061823a
GN		 2947 if (!irqchip_in_kernel(vcpu->kvm) &&
2948 kvm_run->request_interrupt_window &&
2949 !kvm_cpu_has_interrupt(vcpu)) {
c1150d8c 2950 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2951 return 0;
2952 }
6aa8b732
AK		 2953 return 1;
2954}
2955
2956static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2957{
2958 skip_emulated_instruction(vcpu);
d3bef15f 2959 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2960}
2961
c21415e8
IM		 2962static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2963{
510043da 2964 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2965 kvm_emulate_hypercall(vcpu);
2966 return 1;
c21415e8
IM		 2967}
2968
a7052897
MT		 2969static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2970{
f9c617f6 2971 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 2972
2973 kvm_mmu_invlpg(vcpu, exit_qualification);
2974 skip_emulated_instruction(vcpu);
2975 return 1;
2976}
2977
e5edaa01
ED		 2978static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2979{
2980 skip_emulated_instruction(vcpu);
2981 /* TODO: Add support for VT-d/pass-through device */
2982 return 1;
2983}
2984
f78e0e2e
SY		 2985static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2986{
f9c617f6 2987 unsigned long exit_qualification;
f78e0e2e
SY		 2988 enum emulation_result er;
2989 unsigned long offset;
2990
f9c617f6 2991 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 2992 offset = exit_qualification & 0xffful;
2993
2994 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2995
2996 if (er != EMULATE_DONE) {
2997 printk(KERN_ERR
2998 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2999 offset);
3000 return -ENOTSUPP;
3001 }
3002 return 1;
3003}
3004
37817f29
IE		 3005static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3006{
60637aac 3007 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3008 unsigned long exit_qualification;
3009 u16 tss_selector;
64a7ec06
GN		 3010 int reason, type, idt_v;
3011
3012 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3013 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3014
3015 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3016
3017 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3018 if (reason == TASK_SWITCH_GATE && idt_v) {
3019 switch (type) {
3020 case INTR_TYPE_NMI_INTR:
3021 vcpu->arch.nmi_injected = false;
3022 if (cpu_has_virtual_nmis())
3023 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3024 GUEST_INTR_STATE_NMI);
3025 break;
3026 case INTR_TYPE_EXT_INTR:
3027 kvm_clear_interrupt_queue(vcpu);
3028 break;
3029 case INTR_TYPE_HARD_EXCEPTION:
3030 case INTR_TYPE_SOFT_EXCEPTION:
3031 kvm_clear_exception_queue(vcpu);
3032 break;
3033 default:
3034 break;
3035 }
60637aac 3036 }
37817f29
IE		 3037 tss_selector = exit_qualification;
3038
64a7ec06
GN		 3039 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3040 type != INTR_TYPE_EXT_INTR &&
3041 type != INTR_TYPE_NMI_INTR))
3042 skip_emulated_instruction(vcpu);
3043
42dbaa5a
JK		 3044 if (!kvm_task_switch(vcpu, tss_selector, reason))
3045 return 0;
3046
3047 /* clear all local breakpoint enable flags */
3048 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3049
3050 /*
3051 * TODO: What about debug traps on tss switch?
3052 * Are we supposed to inject them and update dr6?
3053 */
3054
3055 return 1;
37817f29
IE		 3056}
3057
1439442c
SY		 3058static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3059{
f9c617f6 3060 unsigned long exit_qualification;
1439442c 3061 gpa_t gpa;
1439442c 3062 int gla_validity;
1439442c 3063
f9c617f6 3064 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3065
3066 if (exit_qualification & (1 << 6)) {
3067 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3068 return -ENOTSUPP;
3069 }
3070
3071 gla_validity = (exit_qualification >> 7) & 0x3;
3072 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3073 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3074 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3075 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3076 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3077 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3078 (long unsigned int)exit_qualification);
3079 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3080 kvm_run->hw.hardware_exit_reason = 0;
3081 return -ENOTSUPP;
3082 }
3083
3084 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
49cd7d22 3085 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3086}
3087
f08864b4
SY		 3088static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3089{
3090 u32 cpu_based_vm_exec_control;
3091
3092 /* clear pending NMI */
3093 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3094 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3095 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3096 ++vcpu->stat.nmi_window_exits;
3097
3098 return 1;
3099}
3100
ea953ef0
MG		 3101static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3102 struct kvm_run *kvm_run)
3103{
8b3079a5
AK		 3104 struct vcpu_vmx *vmx = to_vmx(vcpu);
3105 enum emulation_result err = EMULATE_DONE;
ea953ef0
MG		 3106
3107 preempt_enable();
3108 local_irq_enable();
3109
3110 while (!guest_state_valid(vcpu)) {
3111 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3112
1d5a4d9b
GT		 3113 if (err == EMULATE_DO_MMIO)
3114 break;
3115
3116 if (err != EMULATE_DONE) {
3117 kvm_report_emulation_failure(vcpu, "emulation failure");
3118 return;
ea953ef0
MG		 3119 }
3120
3121 if (signal_pending(current))
3122 break;
3123 if (need_resched())
3124 schedule();
3125 }
3126
3127 local_irq_disable();
3128 preempt_disable();
8b3079a5
AK		 3129
3130 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3131}
3132
6aa8b732
AK		 3133/*
3134 * The exit handlers return 1 if the exit was handled fully and guest execution
3135 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3136 * to be done to userspace and return 0.
3137 */
3138static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3139 struct kvm_run *kvm_run) = {
3140 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3141 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3142 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3143 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3144 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3145 [EXIT_REASON_CR_ACCESS] = handle_cr,
3146 [EXIT_REASON_DR_ACCESS] = handle_dr,
3147 [EXIT_REASON_CPUID] = handle_cpuid,
3148 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3149 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3150 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3151 [EXIT_REASON_HLT] = handle_halt,
a7052897 3152 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3153 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3154 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3155 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3156 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3157 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3158 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3159};
3160
3161static const int kvm_vmx_max_exit_handlers =
50a3485c 3162 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3163
3164/*
3165 * The guest has exited. See if we can fix it or if we need userspace
3166 * assistance.
3167 */
6062d012 3168static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 3169{
6aa8b732 3170 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3171 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3172 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3173
5fdbf976
MT		 3174 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3175 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3176
1d5a4d9b
GT		 3177 /* If we need to emulate an MMIO from handle_invalid_guest_state
3178 * we just return 0 */
10f32d84
AK		 3179 if (vmx->emulation_required && emulate_invalid_guest_state) {
3180 if (guest_state_valid(vcpu))
3181 vmx->emulation_required = 0;
8b3079a5 3182 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3183 }
1d5a4d9b 3184
1439442c
SY		 3185 /* Access CR3 don't cause VMExit in paging mode, so we need
3186 * to sync with guest real CR3. */
089d034e 3187 if (enable_ept && is_paging(vcpu)) {
1439442c
SY		 3188 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3189 ept_load_pdptrs(vcpu);
3190 }
3191
29bd8a78
AK		 3192 if (unlikely(vmx->fail)) {
3193 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3194 kvm_run->fail_entry.hardware_entry_failure_reason
3195 = vmcs_read32(VM_INSTRUCTION_ERROR);
3196 return 0;
3197 }
6aa8b732 3198
d77c26fc 3199 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3200 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3201 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3202 exit_reason != EXIT_REASON_TASK_SWITCH))
3203 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3204 "(0x%x) and exit reason is 0x%x\n",
3205 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3206
3207 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3208 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3209 vmx->soft_vnmi_blocked = 0;
3b86cd99 3210 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3211 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3212 /*
3213 * This CPU don't support us in finding the end of an
3214 * NMI-blocked window if the guest runs with IRQs
3215 * disabled. So we pull the trigger after 1 s of
3216 * futile waiting, but inform the user about this.
3217 */
3218 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3219 "state on VCPU %d after 1 s timeout\n",
3220 __func__, vcpu->vcpu_id);
3221 vmx->soft_vnmi_blocked = 0;
3b86cd99 3222 }
3b86cd99
JK		 3223 }
3224
6aa8b732
AK		 3225 if (exit_reason < kvm_vmx_max_exit_handlers
3226 && kvm_vmx_exit_handlers[exit_reason])
3227 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3228 else {
3229 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3230 kvm_run->hw.hardware_exit_reason = exit_reason;
3231 }
3232 return 0;
3233}
3234
95ba8273 3235static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3236{
95ba8273 3237 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3238 vmcs_write32(TPR_THRESHOLD, 0);
3239 return;
3240 }
3241
95ba8273 3242 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3243}
3244
cf393f75
AK		 3245static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3246{
3247 u32 exit_intr_info;
7b4a25cb 3248 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3249 bool unblock_nmi;
3250 u8 vector;
668f612f
AK		 3251 int type;
3252 bool idtv_info_valid;
cf393f75 3253
7b4a25cb 3254 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
cf393f75
AK		 3255 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3256 if (cpu_has_virtual_nmis()) {
3257 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3258 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3259 /*
7b4a25cb 3260 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3261 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3262 * a guest IRET fault.
7b4a25cb
GN		 3263 * SDM 3: 23.2.2 (September 2008)
3264 * Bit 12 is undefined in any of the following cases:
3265 * If the VM exit sets the valid bit in the IDT-vectoring
3266 * information field.
3267 * If the VM exit is due to a double fault.
cf393f75 3268 */
7b4a25cb
GN		 3269 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3270 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3271 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3272 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3273 } else if (unlikely(vmx->soft_vnmi_blocked))
3274 vmx->vnmi_blocked_time +=
3275 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3276
37b96e98
GN		 3277 vmx->vcpu.arch.nmi_injected = false;
3278 kvm_clear_exception_queue(&vmx->vcpu);
3279 kvm_clear_interrupt_queue(&vmx->vcpu);
3280
3281 if (!idtv_info_valid)
3282 return;
3283
668f612f
AK		 3284 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3285 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3286
64a7ec06 3287 switch (type) {
37b96e98
GN		 3288 case INTR_TYPE_NMI_INTR:
3289 vmx->vcpu.arch.nmi_injected = true;
668f612f 3290 /*
7b4a25cb 3291 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3292 * Clear bit "block by NMI" before VM entry if a NMI
3293 * delivery faulted.
668f612f 3294 */
37b96e98
GN		 3295 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3296 GUEST_INTR_STATE_NMI);
3297 break;
3298 case INTR_TYPE_HARD_EXCEPTION:
3299 case INTR_TYPE_SOFT_EXCEPTION:
35920a35 3300 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3301 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3302 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3303 } else
3304 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98
GN		 3305 break;
3306 case INTR_TYPE_EXT_INTR:
f7d9238f 3307 kvm_queue_interrupt(&vmx->vcpu, vector);
37b96e98
GN		 3308 break;
3309 default:
3310 break;
f7d9238f 3311 }
cf393f75
AK		 3312}
3313
9c8cba37
AK		 3314/*
3315 * Failure to inject an interrupt should give us the information
3316 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3317 * when fetching the interrupt redirection bitmap in the real-mode
3318 * tss, this doesn't happen. So we do it ourselves.
3319 */
3320static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3321{
3322 vmx->rmode.irq.pending = 0;
5fdbf976 3323 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3324 return;
5fdbf976 3325 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3326 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3327 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3328 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3329 return;
3330 }
3331 vmx->idt_vectoring_info =
3332 VECTORING_INFO_VALID_MASK
3333 | INTR_TYPE_EXT_INTR
3334 | vmx->rmode.irq.vector;
3335}
3336
c801949d
AK		 3337#ifdef CONFIG_X86_64
3338#define R "r"
3339#define Q "q"
3340#else
3341#define R "e"
3342#define Q "l"
3343#endif
3344
04d2cc77 3345static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3346{
a2fa3e9f 3347 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3348 u32 intr_info;
e6adf283 3349
3b86cd99
JK		 3350 /* Record the guest's net vcpu time for enforced NMI injections. */
3351 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3352 vmx->entry_time = ktime_get();
3353
a89a8fb9
MG		 3354 /* Handle invalid guest state instead of entering VMX */
3355 if (vmx->emulation_required && emulate_invalid_guest_state) {
3356 handle_invalid_guest_state(vcpu, kvm_run);
3357 return;
3358 }
3359
5fdbf976
MT		 3360 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3361 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3362 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3363 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3364
e6adf283
AK		 3365 /*
3366 * Loading guest fpu may have cleared host cr0.ts
3367 */
3368 vmcs_writel(HOST_CR0, read_cr0());
3369
42dbaa5a
JK		 3370 set_debugreg(vcpu->arch.dr6, 6);
3371
d77c26fc 3372 asm(
6aa8b732 3373 /* Store host registers */
c801949d
AK		 3374 "push %%"R"dx; push %%"R"bp;"
3375 "push %%"R"cx \n\t"
313dbd49
AK		 3376 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3377 "je 1f \n\t"
3378 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3379 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3380 "1: \n\t"
6aa8b732 3381 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3382 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3383 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3384 "mov %c[cr2](%0), %%"R"ax \n\t"
3385 "mov %%"R"ax, %%cr2 \n\t"
3386 "mov %c[rax](%0), %%"R"ax \n\t"
3387 "mov %c[rbx](%0), %%"R"bx \n\t"
3388 "mov %c[rdx](%0), %%"R"dx \n\t"
3389 "mov %c[rsi](%0), %%"R"si \n\t"
3390 "mov %c[rdi](%0), %%"R"di \n\t"
3391 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3392#ifdef CONFIG_X86_64
e08aa78a
AK		 3393 "mov %c[r8](%0), %%r8 \n\t"
3394 "mov %c[r9](%0), %%r9 \n\t"
3395 "mov %c[r10](%0), %%r10 \n\t"
3396 "mov %c[r11](%0), %%r11 \n\t"
3397 "mov %c[r12](%0), %%r12 \n\t"
3398 "mov %c[r13](%0), %%r13 \n\t"
3399 "mov %c[r14](%0), %%r14 \n\t"
3400 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3401#endif
c801949d
AK		 3402 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3403
6aa8b732 3404 /* Enter guest mode */
cd2276a7 3405 "jne .Llaunched \n\t"
4ecac3fd 3406 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3407 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3408 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3409 ".Lkvm_vmx_return: "
6aa8b732 3410 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3411 "xchg %0, (%%"R"sp) \n\t"
3412 "mov %%"R"ax, %c[rax](%0) \n\t"
3413 "mov %%"R"bx, %c[rbx](%0) \n\t"
3414 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3415 "mov %%"R"dx, %c[rdx](%0) \n\t"
3416 "mov %%"R"si, %c[rsi](%0) \n\t"
3417 "mov %%"R"di, %c[rdi](%0) \n\t"
3418 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3419#ifdef CONFIG_X86_64
e08aa78a
AK		 3420 "mov %%r8, %c[r8](%0) \n\t"
3421 "mov %%r9, %c[r9](%0) \n\t"
3422 "mov %%r10, %c[r10](%0) \n\t"
3423 "mov %%r11, %c[r11](%0) \n\t"
3424 "mov %%r12, %c[r12](%0) \n\t"
3425 "mov %%r13, %c[r13](%0) \n\t"
3426 "mov %%r14, %c[r14](%0) \n\t"
3427 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3428#endif
c801949d
AK		 3429 "mov %%cr2, %%"R"ax \n\t"
3430 "mov %%"R"ax, %c[cr2](%0) \n\t"
3431
3432 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3433 "setbe %c[fail](%0) \n\t"
3434 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3435 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3436 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3437 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3438 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3439 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3440 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3441 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3442 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3443 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3444 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3445#ifdef CONFIG_X86_64
ad312c7c
ZX		 3446 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3447 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3448 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3449 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3450 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3451 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3452 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3453 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3454#endif
ad312c7c 3455 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3456 : "cc", "memory"
c801949d 3457 , R"bx", R"di", R"si"
c2036300 3458#ifdef CONFIG_X86_64
c2036300
LV		 3459 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3460#endif
3461 );
6aa8b732 3462
5fdbf976
MT		 3463 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3464 vcpu->arch.regs_dirty = 0;
3465
42dbaa5a
JK		 3466 get_debugreg(vcpu->arch.dr6, 6);
3467
1155f76a 3468 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3469 if (vmx->rmode.irq.pending)
3470 fixup_rmode_irq(vmx);
1155f76a 3471
d77c26fc 3472 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3473 vmx->launched = 1;
1b6269db
AK		 3474
3475 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3476
3477 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3478 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3479 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3480 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3481 asm("int $2");
2714d1d3 3482 }
cf393f75
AK		 3483
3484 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3485}
3486
c801949d
AK		 3487#undef R
3488#undef Q
3489
6aa8b732
AK		 3490static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3491{
a2fa3e9f
GH		 3492 struct vcpu_vmx *vmx = to_vmx(vcpu);
3493
3494 if (vmx->vmcs) {
543e4243 3495 vcpu_clear(vmx);
a2fa3e9f
GH		 3496 free_vmcs(vmx->vmcs);
3497 vmx->vmcs = NULL;
6aa8b732
AK		 3498 }
3499}
3500
3501static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3502{
fb3f0f51
RR		 3503 struct vcpu_vmx *vmx = to_vmx(vcpu);
3504
2384d2b3
SY		 3505 spin_lock(&vmx_vpid_lock);
3506 if (vmx->vpid != 0)
3507 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3508 spin_unlock(&vmx_vpid_lock);
6aa8b732 3509 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3510 kfree(vmx->host_msrs);
3511 kfree(vmx->guest_msrs);
3512 kvm_vcpu_uninit(vcpu);
a4770347 3513 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3514}
3515
fb3f0f51 3516static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3517{
fb3f0f51 3518 int err;
c16f862d 3519 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3520 int cpu;
6aa8b732 3521
a2fa3e9f 3522 if (!vmx)
fb3f0f51
RR		 3523 return ERR_PTR(-ENOMEM);
3524
2384d2b3
SY		 3525 allocate_vpid(vmx);
3526
fb3f0f51
RR		 3527 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3528 if (err)
3529 goto free_vcpu;
965b58a5 3530
a2fa3e9f 3531 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3532 if (!vmx->guest_msrs) {
3533 err = -ENOMEM;
3534 goto uninit_vcpu;
3535 }
965b58a5 3536
a2fa3e9f
GH		 3537 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3538 if (!vmx->host_msrs)
fb3f0f51 3539 goto free_guest_msrs;
965b58a5 3540
a2fa3e9f
GH		 3541 vmx->vmcs = alloc_vmcs();
3542 if (!vmx->vmcs)
fb3f0f51 3543 goto free_msrs;
a2fa3e9f
GH		 3544
3545 vmcs_clear(vmx->vmcs);
3546
15ad7146
AK		 3547 cpu = get_cpu();
3548 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3549 err = vmx_vcpu_setup(vmx);
fb3f0f51 3550 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3551 put_cpu();
fb3f0f51
RR		 3552 if (err)
3553 goto free_vmcs;
5e4a0b3c
MT		 3554 if (vm_need_virtualize_apic_accesses(kvm))
3555 if (alloc_apic_access_page(kvm) != 0)
3556 goto free_vmcs;
fb3f0f51 3557
089d034e 3558 if (enable_ept)
b7ebfb05
SY		 3559 if (alloc_identity_pagetable(kvm) != 0)
3560 goto free_vmcs;
3561
fb3f0f51
RR		 3562 return &vmx->vcpu;
3563
3564free_vmcs:
3565 free_vmcs(vmx->vmcs);
3566free_msrs:
3567 kfree(vmx->host_msrs);
3568free_guest_msrs:
3569 kfree(vmx->guest_msrs);
3570uninit_vcpu:
3571 kvm_vcpu_uninit(&vmx->vcpu);
3572free_vcpu:
a4770347 3573 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3574 return ERR_PTR(err);
6aa8b732
AK		 3575}
3576
002c7f7c
YS		 3577static void __init vmx_check_processor_compat(void *rtn)
3578{
3579 struct vmcs_config vmcs_conf;
3580
3581 *(int *)rtn = 0;
3582 if (setup_vmcs_config(&vmcs_conf) < 0)
3583 *(int *)rtn = -EIO;
3584 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3585 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3586 smp_processor_id());
3587 *(int *)rtn = -EIO;
3588 }
3589}
3590
67253af5
SY		 3591static int get_ept_level(void)
3592{
3593 return VMX_EPT_DEFAULT_GAW + 1;
3594}
3595
4b12f0de 3596static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3597{
4b12f0de
SY		 3598 u64 ret;
3599
522c68c4
SY		 3600 /* For VT-d and EPT combination
3601 * 1. MMIO: always map as UC
3602 * 2. EPT with VT-d:
3603 * a. VT-d without snooping control feature: can't guarantee the
3604 * result, try to trust guest.
3605 * b. VT-d with snooping control feature: snooping control feature of
3606 * VT-d engine can guarantee the cache correctness. Just set it
3607 * to WB to keep consistent with host. So the same as item 3.
3608 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3609 * consistent with host MTRR
3610 */
4b12f0de
SY		 3611 if (is_mmio)
3612 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3613 else if (vcpu->kvm->arch.iommu_domain &&
3614 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3615 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3616 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3617 else
522c68c4
SY		 3618 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3619 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3620
3621 return ret;
64d4d521
SY		 3622}
3623
cbdd1bea 3624static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3625 .cpu_has_kvm_support = cpu_has_kvm_support,
3626 .disabled_by_bios = vmx_disabled_by_bios,
3627 .hardware_setup = hardware_setup,
3628 .hardware_unsetup = hardware_unsetup,
002c7f7c 3629 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3630 .hardware_enable = hardware_enable,
3631 .hardware_disable = hardware_disable,
04547156 3632 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3633
3634 .vcpu_create = vmx_create_vcpu,
3635 .vcpu_free = vmx_free_vcpu,
04d2cc77 3636 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3637
04d2cc77 3638 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3639 .vcpu_load = vmx_vcpu_load,
3640 .vcpu_put = vmx_vcpu_put,
3641
3642 .set_guest_debug = set_guest_debug,
3643 .get_msr = vmx_get_msr,
3644 .set_msr = vmx_set_msr,
3645 .get_segment_base = vmx_get_segment_base,
3646 .get_segment = vmx_get_segment,
3647 .set_segment = vmx_set_segment,
2e4d2653 3648 .get_cpl = vmx_get_cpl,
6aa8b732 3649 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3650 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3651 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3652 .set_cr3 = vmx_set_cr3,
3653 .set_cr4 = vmx_set_cr4,
6aa8b732 3654 .set_efer = vmx_set_efer,
6aa8b732
AK		 3655 .get_idt = vmx_get_idt,
3656 .set_idt = vmx_set_idt,
3657 .get_gdt = vmx_get_gdt,
3658 .set_gdt = vmx_set_gdt,
5fdbf976 3659 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3660 .get_rflags = vmx_get_rflags,
3661 .set_rflags = vmx_set_rflags,
3662
3663 .tlb_flush = vmx_flush_tlb,
6aa8b732 3664
6aa8b732 3665 .run = vmx_vcpu_run,
6062d012 3666 .handle_exit = vmx_handle_exit,
6aa8b732 3667 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3668 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3669 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 3670 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3671 .set_irq = vmx_inject_irq,
95ba8273 3672 .set_nmi = vmx_inject_nmi,
298101da 3673 .queue_exception = vmx_queue_exception,
78646121 3674 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3675 .nmi_allowed = vmx_nmi_allowed,
3676 .enable_nmi_window = enable_nmi_window,
3677 .enable_irq_window = enable_irq_window,
3678 .update_cr8_intercept = update_cr8_intercept,
95ba8273 3679
cbc94022 3680 .set_tss_addr = vmx_set_tss_addr,
67253af5 3681 .get_tdp_level = get_ept_level,
4b12f0de 3682 .get_mt_mask = vmx_get_mt_mask,
6aa8b732
AK		 3683};
3684
3685static int __init vmx_init(void)
3686{
fdef3ad1
HQ		 3687 int r;
3688
3e7c73e9 3689 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3690 if (!vmx_io_bitmap_a)
3691 return -ENOMEM;
3692
3e7c73e9 3693 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3694 if (!vmx_io_bitmap_b) {
3695 r = -ENOMEM;
3696 goto out;
3697 }
3698
5897297b
AK		 3699 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3700 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 3701 r = -ENOMEM;
3702 goto out1;
3703 }
3704
5897297b
AK		 3705 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3706 if (!vmx_msr_bitmap_longmode) {
3707 r = -ENOMEM;
3708 goto out2;
3709 }
3710
fdef3ad1
HQ		 3711 /*
3712 * Allow direct access to the PC debug port (it is often used for I/O
3713 * delays, but the vmexits simply slow things down).
3714 */
3e7c73e9
AK		 3715 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3716 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 3717
3e7c73e9 3718 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 3719
5897297b
AK		 3720 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3721 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 3722
2384d2b3
SY		 3723 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3724
cb498ea2 3725 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3726 if (r)
5897297b 3727 goto out3;
25c5f225 3728
5897297b
AK		 3729 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3730 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3731 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3732 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3733 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3734 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 3735
089d034e 3736 if (enable_ept) {
1439442c 3737 bypass_guest_pf = 0;
5fdbcb9d 3738 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 3739 VMX_EPT_WRITABLE_MASK);
534e38b4 3740 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 3741 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 3742 kvm_enable_tdp();
3743 } else
3744 kvm_disable_tdp();
1439442c 3745
c7addb90
AK		 3746 if (bypass_guest_pf)
3747 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3748
1439442c
SY		 3749 ept_sync_global();
3750
fdef3ad1
HQ		 3751 return 0;
3752
5897297b
AK		 3753out3:
3754 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 3755out2:
5897297b 3756 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 3757out1:
3e7c73e9 3758 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 3759out:
3e7c73e9 3760 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3761 return r;
6aa8b732
AK		 3762}
3763
3764static void __exit vmx_exit(void)
3765{
5897297b
AK		 3766 free_page((unsigned long)vmx_msr_bitmap_legacy);
3767 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 3768 free_page((unsigned long)vmx_io_bitmap_b);
3769 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3770
cb498ea2 3771 kvm_exit();
6aa8b732
AK		 3772}
3773
3774module_init(vmx_init)
3775module_exit(vmx_exit)
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