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exec: Remove unused global variable phys_ram_fd
[qemu.git] / target-arm / helper.c
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b5ff1b31 1#include "cpu.h"
022c62cb 2#include "exec/gdbstub.h"
7b59220e 3#include "helper.h"
1de7afc9 4#include "qemu/host-utils.h"
9c17d615 5#include "sysemu/sysemu.h"
1de7afc9 6#include "qemu/bitops.h"
0b03bdfc 7
4a501606
PM		 8#ifndef CONFIG_USER_ONLY
9static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
a8170e5e 11 hwaddr *phys_ptr, int *prot,
4a501606
PM		 12 target_ulong *page_size);
13#endif
14
0ecb72a5 15static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 16{
17 int nregs;
18
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
21 if (reg < nregs) {
22 stfq_le_p(buf, env->vfp.regs[reg]);
23 return 8;
24 }
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
27 nregs += 16;
28 if (reg < nregs) {
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
31 return 16;
32 }
33 }
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
38 }
39 return 0;
40}
41
0ecb72a5 42static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 43{
44 int nregs;
45
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
47 if (reg < nregs) {
48 env->vfp.regs[reg] = ldfq_le_p(buf);
49 return 8;
50 }
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
52 nregs += 16;
53 if (reg < nregs) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
56 return 16;
57 }
58 }
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 63 }
64 return 0;
65}
66
d4e6df63
PM		 67static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
68 uint64_t *value)
69{
70 *value = CPREG_FIELD32(env, ri);
71 return 0;
72}
73
74static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
75 uint64_t value)
76{
77 CPREG_FIELD32(env, ri) = value;
78 return 0;
79}
80
721fae12
PM		 81static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
82 uint64_t *v)
83{
84 /* Raw read of a coprocessor register (as needed for migration, etc)
85 * return true on success, false if the read is impossible for some reason.
86 */
87 if (ri->type & ARM_CP_CONST) {
88 *v = ri->resetvalue;
89 } else if (ri->raw_readfn) {
90 return (ri->raw_readfn(env, ri, v) == 0);
91 } else if (ri->readfn) {
92 return (ri->readfn(env, ri, v) == 0);
93 } else {
94 if (ri->type & ARM_CP_64BIT) {
95 *v = CPREG_FIELD64(env, ri);
96 } else {
97 *v = CPREG_FIELD32(env, ri);
98 }
99 }
100 return true;
101}
102
103static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
104 int64_t v)
105{
106 /* Raw write of a coprocessor register (as needed for migration, etc).
107 * Return true on success, false if the write is impossible for some reason.
108 * Note that constant registers are treated as write-ignored; the
109 * caller should check for success by whether a readback gives the
110 * value written.
111 */
112 if (ri->type & ARM_CP_CONST) {
113 return true;
114 } else if (ri->raw_writefn) {
115 return (ri->raw_writefn(env, ri, v) == 0);
116 } else if (ri->writefn) {
117 return (ri->writefn(env, ri, v) == 0);
118 } else {
119 if (ri->type & ARM_CP_64BIT) {
120 CPREG_FIELD64(env, ri) = v;
121 } else {
122 CPREG_FIELD32(env, ri) = v;
123 }
124 }
125 return true;
126}
127
128bool write_cpustate_to_list(ARMCPU *cpu)
129{
130 /* Write the coprocessor state from cpu->env to the (index,value) list. */
131 int i;
132 bool ok = true;
133
134 for (i = 0; i < cpu->cpreg_array_len; i++) {
135 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
136 const ARMCPRegInfo *ri;
137 uint64_t v;
138 ri = get_arm_cp_reginfo(cpu, regidx);
139 if (!ri) {
140 ok = false;
141 continue;
142 }
143 if (ri->type & ARM_CP_NO_MIGRATE) {
144 continue;
145 }
146 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
147 ok = false;
148 continue;
149 }
150 cpu->cpreg_values[i] = v;
151 }
152 return ok;
153}
154
155bool write_list_to_cpustate(ARMCPU *cpu)
156{
157 int i;
158 bool ok = true;
159
160 for (i = 0; i < cpu->cpreg_array_len; i++) {
161 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
162 uint64_t v = cpu->cpreg_values[i];
163 uint64_t readback;
164 const ARMCPRegInfo *ri;
165
166 ri = get_arm_cp_reginfo(cpu, regidx);
167 if (!ri) {
168 ok = false;
169 continue;
170 }
171 if (ri->type & ARM_CP_NO_MIGRATE) {
172 continue;
173 }
174 /* Write value and confirm it reads back as written
175 * (to catch read-only registers and partially read-only
176 * registers where the incoming migration value doesn't match)
177 */
178 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
179 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
180 readback != v) {
181 ok = false;
182 }
183 }
184 return ok;
185}
186
187static void add_cpreg_to_list(gpointer key, gpointer opaque)
188{
189 ARMCPU *cpu = opaque;
190 uint64_t regidx;
191 const ARMCPRegInfo *ri;
192
193 regidx = *(uint32_t *)key;
194 ri = get_arm_cp_reginfo(cpu, regidx);
195
196 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
197 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
198 /* The value array need not be initialized at this point */
199 cpu->cpreg_array_len++;
200 }
201}
202
203static void count_cpreg(gpointer key, gpointer opaque)
204{
205 ARMCPU *cpu = opaque;
206 uint64_t regidx;
207 const ARMCPRegInfo *ri;
208
209 regidx = *(uint32_t *)key;
210 ri = get_arm_cp_reginfo(cpu, regidx);
211
212 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
213 cpu->cpreg_array_len++;
214 }
215}
216
217static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
218{
219 uint32_t aidx = *(uint32_t *)a;
220 uint32_t bidx = *(uint32_t *)b;
221
222 return aidx - bidx;
223}
224
225void init_cpreg_list(ARMCPU *cpu)
226{
227 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
228 * Note that we require cpreg_tuples[] to be sorted by key ID.
229 */
230 GList *keys;
231 int arraylen;
232
233 keys = g_hash_table_get_keys(cpu->cp_regs);
234 keys = g_list_sort(keys, cpreg_key_compare);
235
236 cpu->cpreg_array_len = 0;
237
238 g_list_foreach(keys, count_cpreg, cpu);
239
240 arraylen = cpu->cpreg_array_len;
241 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
242 cpu->cpreg_values = g_new(uint64_t, arraylen);
243 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
244 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
245 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
246 cpu->cpreg_array_len = 0;
247
248 g_list_foreach(keys, add_cpreg_to_list, cpu);
249
250 assert(cpu->cpreg_array_len == arraylen);
251
252 g_list_free(keys);
253}
254
c983fe6c
PM		 255static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
256{
257 env->cp15.c3 = value;
258 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
259 return 0;
260}
261
08de207b
PM		 262static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
263{
264 if (env->cp15.c13_fcse != value) {
265 /* Unlike real hardware the qemu TLB uses virtual addresses,
266 * not modified virtual addresses, so this causes a TLB flush.
267 */
268 tlb_flush(env, 1);
269 env->cp15.c13_fcse = value;
270 }
271 return 0;
272}
273static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
274 uint64_t value)
275{
276 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
277 /* For VMSA (when not using the LPAE long descriptor page table
278 * format) this register includes the ASID, so do a TLB flush.
279 * For PMSA it is purely a process ID and no action is needed.
280 */
281 tlb_flush(env, 1);
282 }
283 env->cp15.c13_context = value;
284 return 0;
285}
286
d929823f
PM		 287static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
288 uint64_t value)
289{
290 /* Invalidate all (TLBIALL) */
291 tlb_flush(env, 1);
292 return 0;
293}
294
295static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
296 uint64_t value)
297{
298 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
299 tlb_flush_page(env, value & TARGET_PAGE_MASK);
300 return 0;
301}
302
303static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
304 uint64_t value)
305{
306 /* Invalidate by ASID (TLBIASID) */
307 tlb_flush(env, value == 0);
308 return 0;
309}
310
311static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
312 uint64_t value)
313{
314 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
315 tlb_flush_page(env, value & TARGET_PAGE_MASK);
316 return 0;
317}
318
e9aa6c21
PM		 319static const ARMCPRegInfo cp_reginfo[] = {
320 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
321 * version" bits will read as a reserved value, which should cause
322 * Linux to not try to use the debug hardware.
323 */
324 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
325 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 326 /* MMU Domain access control / MPU write buffer control */
327 { .name = "DACR", .cp = 15,
328 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
329 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
d4e6df63 330 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
08de207b
PM		 331 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
332 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 333 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
08de207b
PM		 334 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
335 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 336 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
4fdd17dd
PM		 337 /* ??? This covers not just the impdef TLB lockdown registers but also
338 * some v7VMSA registers relating to TEX remap, so it is overly broad.
339 */
340 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
341 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 342 /* MMU TLB control. Note that the wildcarding means we cover not just
343 * the unified TLB ops but also the dside/iside/inner-shareable variants.
344 */
345 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 346 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
347 .type = ARM_CP_NO_MIGRATE },
d929823f 348 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 349 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
350 .type = ARM_CP_NO_MIGRATE },
d929823f 351 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 352 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
353 .type = ARM_CP_NO_MIGRATE },
d929823f 354 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 355 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
356 .type = ARM_CP_NO_MIGRATE },
c4804214
PM		 357 /* Cache maintenance ops; some of this space may be overridden later. */
358 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
359 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
360 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 361 REGINFO_SENTINEL
362};
363
7d57f408
PM		 364static const ARMCPRegInfo not_v6_cp_reginfo[] = {
365 /* Not all pre-v6 cores implemented this WFI, so this is slightly
366 * over-broad.
367 */
368 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
369 .access = PL1_W, .type = ARM_CP_WFI },
370 REGINFO_SENTINEL
371};
372
373static const ARMCPRegInfo not_v7_cp_reginfo[] = {
374 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
375 * is UNPREDICTABLE; we choose to NOP as most implementations do).
376 */
377 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
378 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 379 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
380 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
381 * OMAPCP will override this space.
382 */
383 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
384 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
385 .resetvalue = 0 },
386 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
387 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
388 .resetvalue = 0 },
776d4e5c
PM		 389 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
390 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
d4e6df63
PM		 391 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
392 .resetvalue = 0 },
7d57f408
PM		 393 REGINFO_SENTINEL
394};
395
2771db27
PM		 396static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
397{
398 if (env->cp15.c1_coproc != value) {
399 env->cp15.c1_coproc = value;
400 /* ??? Is this safe when called from within a TB? */
401 tb_flush(env);
402 }
403 return 0;
404}
405
7d57f408
PM		 406static const ARMCPRegInfo v6_cp_reginfo[] = {
407 /* prefetch by MVA in v6, NOP in v7 */
408 { .name = "MVA_prefetch",
409 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
410 .access = PL1_W, .type = ARM_CP_NOP },
411 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
412 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 413 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 414 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 415 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 416 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 417 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
418 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
419 .resetvalue = 0, },
420 /* Watchpoint Fault Address Register : should actually only be present
421 * for 1136, 1176, 11MPCore.
422 */
423 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
424 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 425 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
426 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
427 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 428 REGINFO_SENTINEL
429};
430
d4e6df63 431
200ac0ef
PM		 432static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
433 uint64_t *value)
434{
435 /* Generic performance monitor register read function for where
436 * user access may be allowed by PMUSERENR.
437 */
438 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
439 return EXCP_UDEF;
440 }
441 *value = CPREG_FIELD32(env, ri);
442 return 0;
443}
444
445static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
446 uint64_t value)
447{
448 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
449 return EXCP_UDEF;
450 }
451 /* only the DP, X, D and E bits are writable */
452 env->cp15.c9_pmcr &= ~0x39;
453 env->cp15.c9_pmcr |= (value & 0x39);
454 return 0;
455}
456
457static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
458 uint64_t value)
459{
460 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
461 return EXCP_UDEF;
462 }
463 value &= (1 << 31);
464 env->cp15.c9_pmcnten |= value;
465 return 0;
466}
467
468static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
469 uint64_t value)
470{
471 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
472 return EXCP_UDEF;
473 }
474 value &= (1 << 31);
475 env->cp15.c9_pmcnten &= ~value;
476 return 0;
477}
478
479static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
480 uint64_t value)
481{
482 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
483 return EXCP_UDEF;
484 }
485 env->cp15.c9_pmovsr &= ~value;
486 return 0;
487}
488
489static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
490 uint64_t value)
491{
492 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
493 return EXCP_UDEF;
494 }
495 env->cp15.c9_pmxevtyper = value & 0xff;
496 return 0;
497}
498
499static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
500 uint64_t value)
501{
502 env->cp15.c9_pmuserenr = value & 1;
503 return 0;
504}
505
506static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
507 uint64_t value)
508{
509 /* We have no event counters so only the C bit can be changed */
510 value &= (1 << 31);
511 env->cp15.c9_pminten |= value;
512 return 0;
513}
514
515static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
516 uint64_t value)
517{
518 value &= (1 << 31);
519 env->cp15.c9_pminten &= ~value;
520 return 0;
521}
522
776d4e5c
PM		 523static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
524 uint64_t *value)
525{
526 ARMCPU *cpu = arm_env_get_cpu(env);
527 *value = cpu->ccsidr[env->cp15.c0_cssel];
528 return 0;
529}
530
531static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
532 uint64_t value)
533{
534 env->cp15.c0_cssel = value & 0xf;
535 return 0;
536}
537
e9aa6c21
PM		 538static const ARMCPRegInfo v7_cp_reginfo[] = {
539 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
540 * debug components
541 */
542 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
543 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 544 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 545 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 546 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
547 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
548 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 549 /* Performance monitors are implementation defined in v7,
550 * but with an ARM recommended set of registers, which we
551 * follow (although we don't actually implement any counters)
552 *
553 * Performance registers fall into three categories:
554 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
555 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
556 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
557 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
558 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
559 */
560 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
561 .access = PL0_RW, .resetvalue = 0,
562 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 563 .readfn = pmreg_read, .writefn = pmcntenset_write,
564 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 565 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
566 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 567 .readfn = pmreg_read, .writefn = pmcntenclr_write,
568 .type = ARM_CP_NO_MIGRATE },
200ac0ef
PM		 569 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
570 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
d4e6df63
PM		 571 .readfn = pmreg_read, .writefn = pmovsr_write,
572 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 573 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
574 * respect PMUSERENR.
575 */
576 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
577 .access = PL0_W, .type = ARM_CP_NOP },
578 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
579 * We choose to RAZ/WI. XXX should respect PMUSERENR.
580 */
581 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
582 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
583 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
584 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
585 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
586 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
587 .access = PL0_RW,
588 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
d4e6df63
PM		 589 .readfn = pmreg_read, .writefn = pmxevtyper_write,
590 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 591 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
592 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
593 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
594 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
595 .access = PL0_R | PL1_RW,
596 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
597 .resetvalue = 0,
d4e6df63 598 .writefn = pmuserenr_write, .raw_writefn = raw_write },
200ac0ef
PM		 599 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
600 .access = PL1_RW,
601 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
602 .resetvalue = 0,
d4e6df63 603 .writefn = pmintenset_write, .raw_writefn = raw_write },
200ac0ef 604 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
d4e6df63 605 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
200ac0ef 606 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
d4e6df63 607 .resetvalue = 0, .writefn = pmintenclr_write, },
2771db27
PM		 608 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
609 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
610 .resetvalue = 0, },
776d4e5c 611 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
d4e6df63 612 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
776d4e5c
PM		 613 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
614 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
615 .writefn = csselr_write, .resetvalue = 0 },
616 /* Auxiliary ID register: this actually has an IMPDEF value but for now
617 * just RAZ for all cores:
618 */
619 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
620 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 621 REGINFO_SENTINEL
622};
623
c326b979
PM		 624static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
625{
626 value &= 1;
627 env->teecr = value;
628 return 0;
629}
630
631static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
632 uint64_t *value)
633{
634 /* This is a helper function because the user access rights
635 * depend on the value of the TEECR.
636 */
637 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
638 return EXCP_UDEF;
639 }
640 *value = env->teehbr;
641 return 0;
642}
643
644static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
645 uint64_t value)
646{
647 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
648 return EXCP_UDEF;
649 }
650 env->teehbr = value;
651 return 0;
652}
653
654static const ARMCPRegInfo t2ee_cp_reginfo[] = {
655 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
656 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
657 .resetvalue = 0,
658 .writefn = teecr_write },
659 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
660 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
d4e6df63 661 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
c326b979
PM		 662 .readfn = teehbr_read, .writefn = teehbr_write },
663 REGINFO_SENTINEL
664};
665
4d31c596
PM		 666static const ARMCPRegInfo v6k_cp_reginfo[] = {
667 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
668 .access = PL0_RW,
669 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
670 .resetvalue = 0 },
671 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
672 .access = PL0_R|PL1_W,
673 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
674 .resetvalue = 0 },
675 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
676 .access = PL1_RW,
677 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
678 .resetvalue = 0 },
679 REGINFO_SENTINEL
680};
681
6cc7a3ae
PM		 682static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
683 /* Dummy implementation: RAZ/WI the whole crn=14 space */
684 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
685 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 686 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
687 .resetvalue = 0 },
6cc7a3ae
PM		 688 REGINFO_SENTINEL
689};
690
4a501606
PM		 691static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
692{
891a2fe7
PM		 693 if (arm_feature(env, ARM_FEATURE_LPAE)) {
694 env->cp15.c7_par = value;
695 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 696 env->cp15.c7_par = value & 0xfffff6ff;
697 } else {
698 env->cp15.c7_par = value & 0xfffff1ff;
699 }
700 return 0;
701}
702
703#ifndef CONFIG_USER_ONLY
704/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 705
706/* Return true if extended addresses are enabled, ie this is an
707 * LPAE implementation and we are using the long-descriptor translation
708 * table format because the TTBCR EAE bit is set.
709 */
710static inline bool extended_addresses_enabled(CPUARMState *env)
711{
712 return arm_feature(env, ARM_FEATURE_LPAE)
713 && (env->cp15.c2_control & (1 << 31));
714}
715
4a501606
PM		 716static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
717{
a8170e5e 718 hwaddr phys_addr;
4a501606
PM		 719 target_ulong page_size;
720 int prot;
721 int ret, is_user = ri->opc2 & 2;
722 int access_type = ri->opc2 & 1;
723
724 if (ri->opc2 & 4) {
725 /* Other states are only available with TrustZone */
726 return EXCP_UDEF;
727 }
728 ret = get_phys_addr(env, value, access_type, is_user,
729 &phys_addr, &prot, &page_size);
702a9357
PM		 730 if (extended_addresses_enabled(env)) {
731 /* ret is a DFSR/IFSR value for the long descriptor
732 * translation table format, but with WnR always clear.
733 * Convert it to a 64-bit PAR.
734 */
735 uint64_t par64 = (1 << 11); /* LPAE bit always set */
736 if (ret == 0) {
737 par64 |= phys_addr & ~0xfffULL;
738 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 739 } else {
702a9357
PM		 740 par64 |= 1; /* F */
741 par64 |= (ret & 0x3f) << 1; /* FS */
742 /* Note that S2WLK and FSTAGE are always zero, because we don't
743 * implement virtualization and therefore there can't be a stage 2
744 * fault.
745 */
4a501606 746 }
702a9357
PM		 747 env->cp15.c7_par = par64;
748 env->cp15.c7_par_hi = par64 >> 32;
4a501606 749 } else {
702a9357
PM		 750 /* ret is a DFSR/IFSR value for the short descriptor
751 * translation table format (with WnR always clear).
752 * Convert it to a 32-bit PAR.
753 */
754 if (ret == 0) {
755 /* We do not set any attribute bits in the PAR */
756 if (page_size == (1 << 24)
757 && arm_feature(env, ARM_FEATURE_V7)) {
758 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
759 } else {
760 env->cp15.c7_par = phys_addr & 0xfffff000;
761 }
762 } else {
763 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
764 ((ret & (12 << 1)) >> 6) |
765 ((ret & 0xf) << 1) | 1;
766 }
767 env->cp15.c7_par_hi = 0;
4a501606
PM		 768 }
769 return 0;
770}
771#endif
772
773static const ARMCPRegInfo vapa_cp_reginfo[] = {
774 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
775 .access = PL1_RW, .resetvalue = 0,
776 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
777 .writefn = par_write },
778#ifndef CONFIG_USER_ONLY
779 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
d4e6df63 780 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
4a501606
PM		 781#endif
782 REGINFO_SENTINEL
783};
784
18032bec
PM		 785/* Return basic MPU access permission bits. */
786static uint32_t simple_mpu_ap_bits(uint32_t val)
787{
788 uint32_t ret;
789 uint32_t mask;
790 int i;
791 ret = 0;
792 mask = 3;
793 for (i = 0; i < 16; i += 2) {
794 ret |= (val >> i) & mask;
795 mask <<= 2;
796 }
797 return ret;
798}
799
800/* Pad basic MPU access permission bits to extended format. */
801static uint32_t extended_mpu_ap_bits(uint32_t val)
802{
803 uint32_t ret;
804 uint32_t mask;
805 int i;
806 ret = 0;
807 mask = 3;
808 for (i = 0; i < 16; i += 2) {
809 ret |= (val & mask) << i;
810 mask <<= 2;
811 }
812 return ret;
813}
814
815static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
816 uint64_t value)
817{
818 env->cp15.c5_data = extended_mpu_ap_bits(value);
819 return 0;
820}
821
822static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
823 uint64_t *value)
824{
825 *value = simple_mpu_ap_bits(env->cp15.c5_data);
826 return 0;
827}
828
829static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
830 uint64_t value)
831{
832 env->cp15.c5_insn = extended_mpu_ap_bits(value);
833 return 0;
834}
835
836static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
837 uint64_t *value)
838{
839 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
840 return 0;
841}
842
06d76f31
PM		 843static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
844 uint64_t *value)
845{
599d64f6 846 if (ri->crm >= 8) {
06d76f31
PM		 847 return EXCP_UDEF;
848 }
849 *value = env->cp15.c6_region[ri->crm];
850 return 0;
851}
852
853static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
854 uint64_t value)
855{
599d64f6 856 if (ri->crm >= 8) {
06d76f31
PM		 857 return EXCP_UDEF;
858 }
859 env->cp15.c6_region[ri->crm] = value;
860 return 0;
861}
862
18032bec
PM		 863static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
864 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
d4e6df63 865 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 866 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
867 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
868 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
d4e6df63 869 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 870 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
871 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
872 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
873 .access = PL1_RW,
874 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
875 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
876 .access = PL1_RW,
877 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 878 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
879 .access = PL1_RW,
880 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
881 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
882 .access = PL1_RW,
883 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 884 /* Protection region base and size registers */
885 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
886 .opc2 = CP_ANY, .access = PL1_RW,
887 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 888 REGINFO_SENTINEL
889};
890
d4e6df63
PM		 891static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
892 uint64_t value)
ecce5c3c 893{
e42c4db3
PM		 894 if (arm_feature(env, ARM_FEATURE_LPAE)) {
895 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
e42c4db3
PM		 896 } else {
897 value &= 7;
898 }
899 /* Note that we always calculate c2_mask and c2_base_mask, but
900 * they are only used for short-descriptor tables (ie if EAE is 0);
901 * for long-descriptor tables the TTBCR fields are used differently
902 * and the c2_mask and c2_base_mask values are meaningless.
903 */
ecce5c3c
PM		 904 env->cp15.c2_control = value;
905 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
906 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
907 return 0;
908}
909
d4e6df63
PM		 910static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
911 uint64_t value)
912{
913 if (arm_feature(env, ARM_FEATURE_LPAE)) {
914 /* With LPAE the TTBCR could result in a change of ASID
915 * via the TTBCR.A1 bit, so do a TLB flush.
916 */
917 tlb_flush(env, 1);
918 }
919 return vmsa_ttbcr_raw_write(env, ri, value);
920}
921
ecce5c3c
PM		 922static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
923{
924 env->cp15.c2_base_mask = 0xffffc000u;
925 env->cp15.c2_control = 0;
926 env->cp15.c2_mask = 0;
927}
928
18032bec
PM		 929static const ARMCPRegInfo vmsa_cp_reginfo[] = {
930 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
931 .access = PL1_RW,
932 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
933 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
934 .access = PL1_RW,
935 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 936 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
937 .access = PL1_RW,
938 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
939 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
940 .access = PL1_RW,
81a60ada 941 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 942 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
943 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
d4e6df63 944 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
ecce5c3c 945 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 946 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
947 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
948 .resetvalue = 0, },
18032bec
PM		 949 REGINFO_SENTINEL
950};
951
1047b9d7
PM		 952static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
953 uint64_t value)
954{
955 env->cp15.c15_ticonfig = value & 0xe7;
956 /* The OS_TYPE bit in this register changes the reported CPUID! */
957 env->cp15.c0_cpuid = (value & (1 << 5)) ?
958 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
959 return 0;
960}
961
962static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
963 uint64_t value)
964{
965 env->cp15.c15_threadid = value & 0xffff;
966 return 0;
967}
968
969static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
970 uint64_t value)
971{
972 /* Wait-for-interrupt (deprecated) */
c3affe56 973 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1047b9d7
PM		 974 return 0;
975}
976
c4804214
PM		 977static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
978 uint64_t value)
979{
980 /* On OMAP there are registers indicating the max/min index of dcache lines
981 * containing a dirty line; cache flush operations have to reset these.
982 */
983 env->cp15.c15_i_max = 0x000;
984 env->cp15.c15_i_min = 0xff0;
985 return 0;
986}
987
18032bec
PM		 988static const ARMCPRegInfo omap_cp_reginfo[] = {
989 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
990 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
991 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 992 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
993 .access = PL1_RW, .type = ARM_CP_NOP },
994 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
995 .access = PL1_RW,
996 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
997 .writefn = omap_ticonfig_write },
998 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
999 .access = PL1_RW,
1000 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1001 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1002 .access = PL1_RW, .resetvalue = 0xff0,
1003 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1004 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1005 .access = PL1_RW,
1006 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1007 .writefn = omap_threadid_write },
1008 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1009 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
d4e6df63 1010 .type = ARM_CP_NO_MIGRATE,
1047b9d7
PM		 1011 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1012 /* TODO: Peripheral port remap register:
1013 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1014 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1015 * when MMU is off.
1016 */
c4804214 1017 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
d4e6df63
PM		 1018 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1019 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
c4804214 1020 .writefn = omap_cachemaint_write },
34f90529
PM		 1021 { .name = "C9", .cp = 15, .crn = 9,
1022 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1023 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 1024 REGINFO_SENTINEL
1025};
1026
1027static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1028 uint64_t value)
1029{
1030 value &= 0x3fff;
1031 if (env->cp15.c15_cpar != value) {
1032 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1033 tb_flush(env);
1034 env->cp15.c15_cpar = value;
1035 }
1036 return 0;
1037}
1038
1039static const ARMCPRegInfo xscale_cp_reginfo[] = {
1040 { .name = "XSCALE_CPAR",
1041 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1042 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1043 .writefn = xscale_cpar_write, },
2771db27
PM		 1044 { .name = "XSCALE_AUXCR",
1045 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1046 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1047 .resetvalue = 0, },
1047b9d7
PM		 1048 REGINFO_SENTINEL
1049};
1050
1051static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1052 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1053 * implementation of this implementation-defined space.
1054 * Ideally this should eventually disappear in favour of actually
1055 * implementing the correct behaviour for all cores.
1056 */
1057 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1058 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1059 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1060 .resetvalue = 0 },
18032bec
PM		 1061 REGINFO_SENTINEL
1062};
1063
c4804214
PM		 1064static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1065 /* Cache status: RAZ because we have no cache so it's always clean */
1066 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
d4e6df63
PM		 1067 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1068 .resetvalue = 0 },
c4804214
PM		 1069 REGINFO_SENTINEL
1070};
1071
1072static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1073 /* We never have a a block transfer operation in progress */
1074 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
d4e6df63
PM		 1075 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1076 .resetvalue = 0 },
30b05bba
PM		 1077 /* The cache ops themselves: these all NOP for QEMU */
1078 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1079 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1080 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1081 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1082 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1083 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1084 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1085 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1086 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1087 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1088 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1089 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 1090 REGINFO_SENTINEL
1091};
1092
1093static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1094 /* The cache test-and-clean instructions always return (1 << 30)
1095 * to indicate that there are no dirty cache lines.
1096 */
1097 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1098 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1099 .resetvalue = (1 << 30) },
c4804214 1100 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1101 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1102 .resetvalue = (1 << 30) },
c4804214
PM		 1103 REGINFO_SENTINEL
1104};
1105
34f90529
PM		 1106static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1107 /* Ignore ReadBuffer accesses */
1108 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1109 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1110 .access = PL1_RW, .resetvalue = 0,
1111 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
34f90529
PM		 1112 REGINFO_SENTINEL
1113};
1114
81bdde9d
PM		 1115static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1116 uint64_t *value)
1117{
55e5c285
AF		 1118 CPUState *cs = CPU(arm_env_get_cpu(env));
1119 uint32_t mpidr = cs->cpu_index;
81bdde9d
PM		 1120 /* We don't support setting cluster ID ([8..11])
1121 * so these bits always RAZ.
1122 */
1123 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1124 mpidr |= (1 << 31);
1125 /* Cores which are uniprocessor (non-coherent)
1126 * but still implement the MP extensions set
1127 * bit 30. (For instance, A9UP.) However we do
1128 * not currently model any of those cores.
1129 */
1130 }
1131 *value = mpidr;
1132 return 0;
1133}
1134
1135static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1136 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
d4e6df63 1137 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
81bdde9d
PM		 1138 REGINFO_SENTINEL
1139};
1140
891a2fe7
PM		 1141static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1142{
1143 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1144 return 0;
1145}
1146
1147static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1148{
1149 env->cp15.c7_par_hi = value >> 32;
1150 env->cp15.c7_par = value;
1151 return 0;
1152}
1153
1154static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1155{
1156 env->cp15.c7_par_hi = 0;
1157 env->cp15.c7_par = 0;
1158}
1159
1160static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1161 uint64_t *value)
1162{
1163 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1164 return 0;
1165}
1166
d4e6df63
PM		 1167static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1168 uint64_t value)
891a2fe7
PM		 1169{
1170 env->cp15.c2_base0_hi = value >> 32;
1171 env->cp15.c2_base0 = value;
d4e6df63
PM		 1172 return 0;
1173}
1174
1175static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1176 uint64_t value)
1177{
891a2fe7
PM		 1178 /* Writes to the 64 bit format TTBRs may change the ASID */
1179 tlb_flush(env, 1);
d4e6df63 1180 return ttbr064_raw_write(env, ri, value);
891a2fe7
PM		 1181}
1182
1183static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1184{
1185 env->cp15.c2_base0_hi = 0;
1186 env->cp15.c2_base0 = 0;
1187}
1188
1189static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1190 uint64_t *value)
1191{
1192 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1193 return 0;
1194}
1195
1196static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1197 uint64_t value)
1198{
1199 env->cp15.c2_base1_hi = value >> 32;
1200 env->cp15.c2_base1 = value;
1201 return 0;
1202}
1203
1204static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1205{
1206 env->cp15.c2_base1_hi = 0;
1207 env->cp15.c2_base1 = 0;
1208}
1209
7ac681cf 1210static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 1211 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 1212 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1213 */
1214 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1215 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1216 .resetvalue = 0 },
1217 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1218 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1219 .resetvalue = 0 },
f9fc619a
PM		 1220 /* 64 bit access versions of the (dummy) debug registers */
1221 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1222 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1223 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1224 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1225 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1226 .access = PL1_RW, .type = ARM_CP_64BIT,
1227 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1228 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1229 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
d4e6df63
PM		 1230 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1231 .resetfn = ttbr064_reset },
891a2fe7
PM		 1232 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1233 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1234 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1235 REGINFO_SENTINEL
1236};
1237
2771db27
PM		 1238static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1239{
1240 env->cp15.c1_sys = value;
1241 /* ??? Lots of these bits are not implemented. */
1242 /* This may enable/disable the MMU, so do a TLB flush. */
1243 tlb_flush(env, 1);
1244 return 0;
1245}
1246
2ceb98c0
PM		 1247void register_cp_regs_for_features(ARMCPU *cpu)
1248{
1249 /* Register all the coprocessor registers based on feature bits */
1250 CPUARMState *env = &cpu->env;
1251 if (arm_feature(env, ARM_FEATURE_M)) {
1252 /* M profile has no coprocessor registers */
1253 return;
1254 }
1255
e9aa6c21 1256 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1257 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1258 /* The ID registers all have impdef reset values */
1259 ARMCPRegInfo v6_idregs[] = {
1260 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1261 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1262 .resetvalue = cpu->id_pfr0 },
1263 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1264 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1265 .resetvalue = cpu->id_pfr1 },
1266 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1267 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1268 .resetvalue = cpu->id_dfr0 },
1269 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1270 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1271 .resetvalue = cpu->id_afr0 },
1272 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1273 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1274 .resetvalue = cpu->id_mmfr0 },
1275 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1276 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1277 .resetvalue = cpu->id_mmfr1 },
1278 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1279 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1280 .resetvalue = cpu->id_mmfr2 },
1281 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1282 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1283 .resetvalue = cpu->id_mmfr3 },
1284 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1285 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1286 .resetvalue = cpu->id_isar0 },
1287 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1288 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1289 .resetvalue = cpu->id_isar1 },
1290 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1291 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1292 .resetvalue = cpu->id_isar2 },
1293 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1294 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1295 .resetvalue = cpu->id_isar3 },
1296 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1297 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1298 .resetvalue = cpu->id_isar4 },
1299 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1300 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1301 .resetvalue = cpu->id_isar5 },
1302 /* 6..7 are as yet unallocated and must RAZ */
1303 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1304 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1305 .resetvalue = 0 },
1306 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1307 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1308 .resetvalue = 0 },
1309 REGINFO_SENTINEL
1310 };
1311 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1312 define_arm_cp_regs(cpu, v6_cp_reginfo);
1313 } else {
1314 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1315 }
4d31c596
PM		 1316 if (arm_feature(env, ARM_FEATURE_V6K)) {
1317 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1318 }
e9aa6c21 1319 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1320 /* v7 performance monitor control register: same implementor
1321 * field as main ID register, and we implement no event counters.
1322 */
1323 ARMCPRegInfo pmcr = {
1324 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1325 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1326 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
d4e6df63
PM		 1327 .readfn = pmreg_read, .writefn = pmcr_write,
1328 .raw_readfn = raw_read, .raw_writefn = raw_write,
200ac0ef 1329 };
776d4e5c
PM		 1330 ARMCPRegInfo clidr = {
1331 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1332 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1333 };
200ac0ef 1334 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1335 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1336 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1337 } else {
1338 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1339 }
18032bec
PM		 1340 if (arm_feature(env, ARM_FEATURE_MPU)) {
1341 /* These are the MPU registers prior to PMSAv6. Any new
1342 * PMSA core later than the ARM946 will require that we
1343 * implement the PMSAv6 or PMSAv7 registers, which are
1344 * completely different.
1345 */
1346 assert(!arm_feature(env, ARM_FEATURE_V6));
1347 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1348 } else {
1349 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1350 }
c326b979
PM		 1351 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1352 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1353 }
6cc7a3ae
PM		 1354 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1355 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1356 }
4a501606
PM		 1357 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1358 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1359 }
c4804214
PM		 1360 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1361 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1362 }
1363 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1364 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1365 }
1366 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1367 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1368 }
18032bec
PM		 1369 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1370 define_arm_cp_regs(cpu, omap_cp_reginfo);
1371 }
34f90529
PM		 1372 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1373 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1374 }
1047b9d7
PM		 1375 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1376 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1377 }
1378 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1379 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1380 }
81bdde9d
PM		 1381 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1382 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1383 }
7ac681cf
PM		 1384 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1385 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1386 }
7884849c
PM		 1387 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1388 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1389 * be read-only (ie write causes UNDEF exception).
1390 */
1391 {
1392 ARMCPRegInfo id_cp_reginfo[] = {
1393 /* Note that the MIDR isn't a simple constant register because
1394 * of the TI925 behaviour where writes to another register can
1395 * cause the MIDR value to change.
1396 */
1397 { .name = "MIDR",
1398 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1399 .access = PL1_R, .resetvalue = cpu->midr,
d4e6df63 1400 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
7884849c
PM		 1401 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1402 { .name = "CTR",
1403 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1404 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1405 { .name = "TCMTR",
1406 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1407 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1408 { .name = "TLBTR",
1409 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1410 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1411 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1412 { .name = "DUMMY",
1413 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1414 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1415 { .name = "DUMMY",
1416 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1417 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1418 { .name = "DUMMY",
1419 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1420 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1421 { .name = "DUMMY",
1422 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1423 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1424 { .name = "DUMMY",
1425 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1426 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1427 REGINFO_SENTINEL
1428 };
1429 ARMCPRegInfo crn0_wi_reginfo = {
1430 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1431 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1432 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1433 };
1434 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1435 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1436 ARMCPRegInfo *r;
1437 /* Register the blanket "writes ignored" value first to cover the
1438 * whole space. Then define the specific ID registers, but update
1439 * their access field to allow write access, so that they ignore
1440 * writes rather than causing them to UNDEF.
1441 */
1442 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1443 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1444 r->access = PL1_RW;
1445 define_one_arm_cp_reg(cpu, r);
1446 }
1447 } else {
1448 /* Just register the standard ID registers (read-only, meaning
1449 * that writes will UNDEF).
1450 */
1451 define_arm_cp_regs(cpu, id_cp_reginfo);
1452 }
1453 }
1454
2771db27
PM		 1455 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1456 ARMCPRegInfo auxcr = {
1457 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1458 .access = PL1_RW, .type = ARM_CP_CONST,
1459 .resetvalue = cpu->reset_auxcr
1460 };
1461 define_one_arm_cp_reg(cpu, &auxcr);
1462 }
1463
1464 /* Generic registers whose values depend on the implementation */
1465 {
1466 ARMCPRegInfo sctlr = {
1467 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1468 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
d4e6df63
PM		 1469 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1470 .raw_writefn = raw_write,
2771db27
PM		 1471 };
1472 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1473 /* Normally we would always end the TB on an SCTLR write, but Linux
1474 * arch/arm/mach-pxa/sleep.S expects two instructions following
1475 * an MMU enable to execute from cache. Imitate this behaviour.
1476 */
1477 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1478 }
1479 define_one_arm_cp_reg(cpu, &sctlr);
1480 }
2ceb98c0
PM		 1481}
1482
778c3a06 1483ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1484{
dec9c2d4 1485 ARMCPU *cpu;
40f137e1 1486 CPUARMState *env;
5900d6b2 1487 ObjectClass *oc;
40f137e1 1488
5900d6b2
AF		 1489 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1490 if (!oc) {
aaed909a 1491 return NULL;
777dc784 1492 }
5900d6b2 1493 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
dec9c2d4 1494 env = &cpu->env;
777dc784 1495 env->cpu_model_str = cpu_model;
14969266
AF		 1496
1497 /* TODO this should be set centrally, once possible */
1498 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
777dc784 1499
14969266
AF		 1500 return cpu;
1501}
1502
1503void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1504{
1505 CPUARMState *env = &cpu->env;
1506
56aebc89
PB		 1507 if (arm_feature(env, ARM_FEATURE_NEON)) {
1508 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1509 51, "arm-neon.xml", 0);
1510 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1511 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1512 35, "arm-vfp3.xml", 0);
1513 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1514 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1515 19, "arm-vfp.xml", 0);
1516 }
40f137e1
PB		 1517}
1518
777dc784
PM		 1519/* Sort alphabetically by type name, except for "any". */
1520static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1521{
777dc784
PM		 1522 ObjectClass *class_a = (ObjectClass *)a;
1523 ObjectClass *class_b = (ObjectClass *)b;
1524 const char *name_a, *name_b;
5adb4839 1525
777dc784
PM		 1526 name_a = object_class_get_name(class_a);
1527 name_b = object_class_get_name(class_b);
51492fd1 1528 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
777dc784 1529 return 1;
51492fd1 1530 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
777dc784
PM		 1531 return -1;
1532 } else {
1533 return strcmp(name_a, name_b);
5adb4839
PB		 1534 }
1535}
1536
777dc784 1537static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1538{
777dc784 1539 ObjectClass *oc = data;
92a31361 1540 CPUListState *s = user_data;
51492fd1
AF		 1541 const char *typename;
1542 char *name;
3371d272 1543
51492fd1
AF		 1544 typename = object_class_get_name(oc);
1545 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
777dc784 1546 (*s->cpu_fprintf)(s->file, " %s\n",
51492fd1
AF		 1547 name);
1548 g_free(name);
777dc784
PM		 1549}
1550
1551void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1552{
92a31361 1553 CPUListState s = {
777dc784
PM		 1554 .file = f,
1555 .cpu_fprintf = cpu_fprintf,
1556 };
1557 GSList *list;
1558
1559 list = object_class_get_list(TYPE_ARM_CPU, false);
1560 list = g_slist_sort(list, arm_cpu_list_compare);
1561 (*cpu_fprintf)(f, "Available CPUs:\n");
1562 g_slist_foreach(list, arm_cpu_list_entry, &s);
1563 g_slist_free(list);
40f137e1
PB		 1564}
1565
4b6a83fb
PM		 1566void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1567 const ARMCPRegInfo *r, void *opaque)
1568{
1569 /* Define implementations of coprocessor registers.
1570 * We store these in a hashtable because typically
1571 * there are less than 150 registers in a space which
1572 * is 16*16*16*8*8 = 262144 in size.
1573 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1574 * If a register is defined twice then the second definition is
1575 * used, so this can be used to define some generic registers and
1576 * then override them with implementation specific variations.
1577 * At least one of the original and the second definition should
1578 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1579 * against accidental use.
1580 */
1581 int crm, opc1, opc2;
1582 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1583 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1584 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1585 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1586 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1587 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1588 /* 64 bit registers have only CRm and Opc1 fields */
1589 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1590 /* Check that the register definition has enough info to handle
1591 * reads and writes if they are permitted.
1592 */
1593 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1594 if (r->access & PL3_R) {
1595 assert(r->fieldoffset || r->readfn);
1596 }
1597 if (r->access & PL3_W) {
1598 assert(r->fieldoffset || r->writefn);
1599 }
1600 }
1601 /* Bad type field probably means missing sentinel at end of reg list */
1602 assert(cptype_valid(r->type));
1603 for (crm = crmmin; crm <= crmmax; crm++) {
1604 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1605 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1606 uint32_t *key = g_new(uint32_t, 1);
1607 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1608 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1609 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1610 r2->opaque = opaque;
1611 /* Make sure reginfo passed to helpers for wildcarded regs
1612 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1613 */
1614 r2->crm = crm;
1615 r2->opc1 = opc1;
1616 r2->opc2 = opc2;
7023ec7e
PM		 1617 /* By convention, for wildcarded registers only the first
1618 * entry is used for migration; the others are marked as
1619 * NO_MIGRATE so we don't try to transfer the register
1620 * multiple times. Special registers (ie NOP/WFI) are
1621 * never migratable.
1622 */
1623 if ((r->type & ARM_CP_SPECIAL) ||
1624 ((r->crm == CP_ANY) && crm != 0) ||
1625 ((r->opc1 == CP_ANY) && opc1 != 0) ||
1626 ((r->opc2 == CP_ANY) && opc2 != 0)) {
1627 r2->type |= ARM_CP_NO_MIGRATE;
1628 }
1629
4b6a83fb
PM		 1630 /* Overriding of an existing definition must be explicitly
1631 * requested.
1632 */
1633 if (!(r->type & ARM_CP_OVERRIDE)) {
1634 ARMCPRegInfo *oldreg;
1635 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1636 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1637 fprintf(stderr, "Register redefined: cp=%d %d bit "
1638 "crn=%d crm=%d opc1=%d opc2=%d, "
1639 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1640 r2->crn, r2->crm, r2->opc1, r2->opc2,
1641 oldreg->name, r2->name);
1642 assert(0);
1643 }
1644 }
1645 g_hash_table_insert(cpu->cp_regs, key, r2);
1646 }
1647 }
1648 }
1649}
1650
1651void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1652 const ARMCPRegInfo *regs, void *opaque)
1653{
1654 /* Define a whole list of registers */
1655 const ARMCPRegInfo *r;
1656 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1657 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1658 }
1659}
1660
1661const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1662{
1663 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1664}
1665
1666int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1667 uint64_t value)
1668{
1669 /* Helper coprocessor write function for write-ignore registers */
1670 return 0;
1671}
1672
1673int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1674{
1675 /* Helper coprocessor write function for read-as-zero registers */
1676 *value = 0;
1677 return 0;
1678}
1679
0ecb72a5 1680static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1681{
1682 /* Return true if it is not valid for us to switch to
1683 * this CPU mode (ie all the UNPREDICTABLE cases in
1684 * the ARM ARM CPSRWriteByInstr pseudocode).
1685 */
1686 switch (mode) {
1687 case ARM_CPU_MODE_USR:
1688 case ARM_CPU_MODE_SYS:
1689 case ARM_CPU_MODE_SVC:
1690 case ARM_CPU_MODE_ABT:
1691 case ARM_CPU_MODE_UND:
1692 case ARM_CPU_MODE_IRQ:
1693 case ARM_CPU_MODE_FIQ:
1694 return 0;
1695 default:
1696 return 1;
1697 }
1698}
1699
2f4a40e5
AZ		 1700uint32_t cpsr_read(CPUARMState *env)
1701{
1702 int ZF;
6fbe23d5
PB		 1703 ZF = (env->ZF == 0);
1704 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1705 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1706 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1707 | ((env->condexec_bits & 0xfc) << 8)
1708 | (env->GE << 16);
1709}
1710
1711void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1712{
2f4a40e5 1713 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1714 env->ZF = (~val) & CPSR_Z;
1715 env->NF = val;
2f4a40e5
AZ		 1716 env->CF = (val >> 29) & 1;
1717 env->VF = (val << 3) & 0x80000000;
1718 }
1719 if (mask & CPSR_Q)
1720 env->QF = ((val & CPSR_Q) != 0);
1721 if (mask & CPSR_T)
1722 env->thumb = ((val & CPSR_T) != 0);
1723 if (mask & CPSR_IT_0_1) {
1724 env->condexec_bits &= ~3;
1725 env->condexec_bits |= (val >> 25) & 3;
1726 }
1727 if (mask & CPSR_IT_2_7) {
1728 env->condexec_bits &= 3;
1729 env->condexec_bits |= (val >> 8) & 0xfc;
1730 }
1731 if (mask & CPSR_GE) {
1732 env->GE = (val >> 16) & 0xf;
1733 }
1734
1735 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1736 if (bad_mode_switch(env, val & CPSR_M)) {
1737 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1738 * We choose to ignore the attempt and leave the CPSR M field
1739 * untouched.
1740 */
1741 mask &= ~CPSR_M;
1742 } else {
1743 switch_mode(env, val & CPSR_M);
1744 }
2f4a40e5
AZ		 1745 }
1746 mask &= ~CACHED_CPSR_BITS;
1747 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1748}
1749
b26eefb6
PB		 1750/* Sign/zero extend */
1751uint32_t HELPER(sxtb16)(uint32_t x)
1752{
1753 uint32_t res;
1754 res = (uint16_t)(int8_t)x;
1755 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1756 return res;
1757}
1758
1759uint32_t HELPER(uxtb16)(uint32_t x)
1760{
1761 uint32_t res;
1762 res = (uint16_t)(uint8_t)x;
1763 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1764 return res;
1765}
1766
f51bbbfe
PB		 1767uint32_t HELPER(clz)(uint32_t x)
1768{
7bbcb0af 1769 return clz32(x);
f51bbbfe
PB		 1770}
1771
3670669c
PB		 1772int32_t HELPER(sdiv)(int32_t num, int32_t den)
1773{
1774 if (den == 0)
1775 return 0;
686eeb93
AJ		 1776 if (num == INT_MIN && den == -1)
1777 return INT_MIN;
3670669c
PB		 1778 return num / den;
1779}
1780
1781uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1782{
1783 if (den == 0)
1784 return 0;
1785 return num / den;
1786}
1787
1788uint32_t HELPER(rbit)(uint32_t x)
1789{
1790 x = ((x & 0xff000000) >> 24)
1791 | ((x & 0x00ff0000) >> 8)
1792 | ((x & 0x0000ff00) << 8)
1793 | ((x & 0x000000ff) << 24);
1794 x = ((x & 0xf0f0f0f0) >> 4)
1795 | ((x & 0x0f0f0f0f) << 4);
1796 x = ((x & 0x88888888) >> 3)
1797 | ((x & 0x44444444) >> 1)
1798 | ((x & 0x22222222) << 1)
1799 | ((x & 0x11111111) << 3);
1800 return x;
1801}
1802
5fafdf24 1803#if defined(CONFIG_USER_ONLY)
b5ff1b31 1804
97a8ea5a 1805void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 1806{
97a8ea5a
AF		 1807 ARMCPU *cpu = ARM_CPU(cs);
1808 CPUARMState *env = &cpu->env;
1809
b5ff1b31
FB		 1810 env->exception_index = -1;
1811}
1812
0ecb72a5 1813int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1814 int mmu_idx)
b5ff1b31
FB		 1815{
1816 if (rw == 2) {
1817 env->exception_index = EXCP_PREFETCH_ABORT;
1818 env->cp15.c6_insn = address;
1819 } else {
1820 env->exception_index = EXCP_DATA_ABORT;
1821 env->cp15.c6_data = address;
1822 }
1823 return 1;
1824}
1825
9ee6e8bb 1826/* These should probably raise undefined insn exceptions. */
0ecb72a5 1827void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1828{
1829 cpu_abort(env, "v7m_mrs %d\n", reg);
1830}
1831
0ecb72a5 1832uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1833{
1834 cpu_abort(env, "v7m_mrs %d\n", reg);
1835 return 0;
1836}
1837
0ecb72a5 1838void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1839{
1840 if (mode != ARM_CPU_MODE_USR)
1841 cpu_abort(env, "Tried to switch out of user mode\n");
1842}
1843
0ecb72a5 1844void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1845{
1846 cpu_abort(env, "banked r13 write\n");
1847}
1848
0ecb72a5 1849uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1850{
1851 cpu_abort(env, "banked r13 read\n");
1852 return 0;
1853}
1854
b5ff1b31
FB		 1855#else
1856
1857/* Map CPU modes onto saved register banks. */
494b00c7 1858int bank_number(int mode)
b5ff1b31
FB		 1859{
1860 switch (mode) {
1861 case ARM_CPU_MODE_USR:
1862 case ARM_CPU_MODE_SYS:
1863 return 0;
1864 case ARM_CPU_MODE_SVC:
1865 return 1;
1866 case ARM_CPU_MODE_ABT:
1867 return 2;
1868 case ARM_CPU_MODE_UND:
1869 return 3;
1870 case ARM_CPU_MODE_IRQ:
1871 return 4;
1872 case ARM_CPU_MODE_FIQ:
1873 return 5;
1874 }
f5206413 1875 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
b5ff1b31
FB		 1876}
1877
0ecb72a5 1878void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1879{
1880 int old_mode;
1881 int i;
1882
1883 old_mode = env->uncached_cpsr & CPSR_M;
1884 if (mode == old_mode)
1885 return;
1886
1887 if (old_mode == ARM_CPU_MODE_FIQ) {
1888 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1889 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1890 } else if (mode == ARM_CPU_MODE_FIQ) {
1891 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1892 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1893 }
1894
f5206413 1895 i = bank_number(old_mode);
b5ff1b31
FB		 1896 env->banked_r13[i] = env->regs[13];
1897 env->banked_r14[i] = env->regs[14];
1898 env->banked_spsr[i] = env->spsr;
1899
f5206413 1900 i = bank_number(mode);
b5ff1b31
FB		 1901 env->regs[13] = env->banked_r13[i];
1902 env->regs[14] = env->banked_r14[i];
1903 env->spsr = env->banked_spsr[i];
1904}
1905
9ee6e8bb
PB		 1906static void v7m_push(CPUARMState *env, uint32_t val)
1907{
1908 env->regs[13] -= 4;
1909 stl_phys(env->regs[13], val);
1910}
1911
1912static uint32_t v7m_pop(CPUARMState *env)
1913{
1914 uint32_t val;
1915 val = ldl_phys(env->regs[13]);
1916 env->regs[13] += 4;
1917 return val;
1918}
1919
1920/* Switch to V7M main or process stack pointer. */
1921static void switch_v7m_sp(CPUARMState *env, int process)
1922{
1923 uint32_t tmp;
1924 if (env->v7m.current_sp != process) {
1925 tmp = env->v7m.other_sp;
1926 env->v7m.other_sp = env->regs[13];
1927 env->regs[13] = tmp;
1928 env->v7m.current_sp = process;
1929 }
1930}
1931
1932static void do_v7m_exception_exit(CPUARMState *env)
1933{
1934 uint32_t type;
1935 uint32_t xpsr;
1936
1937 type = env->regs[15];
1938 if (env->v7m.exception != 0)
983fe826 1939 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1940
1941 /* Switch to the target stack. */
1942 switch_v7m_sp(env, (type & 4) != 0);
1943 /* Pop registers. */
1944 env->regs[0] = v7m_pop(env);
1945 env->regs[1] = v7m_pop(env);
1946 env->regs[2] = v7m_pop(env);
1947 env->regs[3] = v7m_pop(env);
1948 env->regs[12] = v7m_pop(env);
1949 env->regs[14] = v7m_pop(env);
1950 env->regs[15] = v7m_pop(env);
1951 xpsr = v7m_pop(env);
1952 xpsr_write(env, xpsr, 0xfffffdff);
1953 /* Undo stack alignment. */
1954 if (xpsr & 0x200)
1955 env->regs[13] |= 4;
1956 /* ??? The exception return type specifies Thread/Handler mode. However
1957 this is also implied by the xPSR value. Not sure what to do
1958 if there is a mismatch. */
1959 /* ??? Likewise for mismatches between the CONTROL register and the stack
1960 pointer. */
1961}
1962
e6f010cc 1963void arm_v7m_cpu_do_interrupt(CPUState *cs)
9ee6e8bb 1964{
e6f010cc
AF		 1965 ARMCPU *cpu = ARM_CPU(cs);
1966 CPUARMState *env = &cpu->env;
9ee6e8bb
PB		 1967 uint32_t xpsr = xpsr_read(env);
1968 uint32_t lr;
1969 uint32_t addr;
1970
1971 lr = 0xfffffff1;
1972 if (env->v7m.current_sp)
1973 lr |= 4;
1974 if (env->v7m.exception == 0)
1975 lr |= 8;
1976
1977 /* For exceptions we just mark as pending on the NVIC, and let that
1978 handle it. */
1979 /* TODO: Need to escalate if the current priority is higher than the
1980 one we're raising. */
1981 switch (env->exception_index) {
1982 case EXCP_UDEF:
983fe826 1983 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1984 return;
1985 case EXCP_SWI:
314e2296 1986 /* The PC already points to the next instruction. */
983fe826 1987 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1988 return;
1989 case EXCP_PREFETCH_ABORT:
1990 case EXCP_DATA_ABORT:
983fe826 1991 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1992 return;
1993 case EXCP_BKPT:
2ad207d4
PB		 1994 if (semihosting_enabled) {
1995 int nr;
d31dd73e 1996 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1997 if (nr == 0xab) {
1998 env->regs[15] += 2;
1999 env->regs[0] = do_arm_semihosting(env);
2000 return;
2001 }
2002 }
983fe826 2003 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 2004 return;
2005 case EXCP_IRQ:
983fe826 2006 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 2007 break;
2008 case EXCP_EXCEPTION_EXIT:
2009 do_v7m_exception_exit(env);
2010 return;
2011 default:
2012 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2013 return; /* Never happens. Keep compiler happy. */
2014 }
2015
2016 /* Align stack pointer. */
2017 /* ??? Should only do this if Configuration Control Register
2018 STACKALIGN bit is set. */
2019 if (env->regs[13] & 4) {
ab19b0ec 2020 env->regs[13] -= 4;
9ee6e8bb
PB		 2021 xpsr |= 0x200;
2022 }
6c95676b 2023 /* Switch to the handler mode. */
9ee6e8bb
PB		 2024 v7m_push(env, xpsr);
2025 v7m_push(env, env->regs[15]);
2026 v7m_push(env, env->regs[14]);
2027 v7m_push(env, env->regs[12]);
2028 v7m_push(env, env->regs[3]);
2029 v7m_push(env, env->regs[2]);
2030 v7m_push(env, env->regs[1]);
2031 v7m_push(env, env->regs[0]);
2032 switch_v7m_sp(env, 0);
c98d174c
PM		 2033 /* Clear IT bits */
2034 env->condexec_bits = 0;
9ee6e8bb
PB		 2035 env->regs[14] = lr;
2036 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2037 env->regs[15] = addr & 0xfffffffe;
2038 env->thumb = addr & 1;
2039}
2040
b5ff1b31 2041/* Handle a CPU exception. */
97a8ea5a 2042void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 2043{
97a8ea5a
AF		 2044 ARMCPU *cpu = ARM_CPU(cs);
2045 CPUARMState *env = &cpu->env;
b5ff1b31
FB		 2046 uint32_t addr;
2047 uint32_t mask;
2048 int new_mode;
2049 uint32_t offset;
2050
e6f010cc
AF		 2051 assert(!IS_M(env));
2052
b5ff1b31
FB		 2053 /* TODO: Vectored interrupt controller. */
2054 switch (env->exception_index) {
2055 case EXCP_UDEF:
2056 new_mode = ARM_CPU_MODE_UND;
2057 addr = 0x04;
2058 mask = CPSR_I;
2059 if (env->thumb)
2060 offset = 2;
2061 else
2062 offset = 4;
2063 break;
2064 case EXCP_SWI:
8e71621f
PB		 2065 if (semihosting_enabled) {
2066 /* Check for semihosting interrupt. */
2067 if (env->thumb) {
d31dd73e
BS		 2068 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2069 & 0xff;
8e71621f 2070 } else {
d31dd73e 2071 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 2072 & 0xffffff;
8e71621f
PB		 2073 }
2074 /* Only intercept calls from privileged modes, to provide some
2075 semblance of security. */
2076 if (((mask == 0x123456 && !env->thumb)
2077 || (mask == 0xab && env->thumb))
2078 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2079 env->regs[0] = do_arm_semihosting(env);
2080 return;
2081 }
2082 }
b5ff1b31
FB		 2083 new_mode = ARM_CPU_MODE_SVC;
2084 addr = 0x08;
2085 mask = CPSR_I;
601d70b9 2086 /* The PC already points to the next instruction. */
b5ff1b31
FB		 2087 offset = 0;
2088 break;
06c949e6 2089 case EXCP_BKPT:
9ee6e8bb 2090 /* See if this is a semihosting syscall. */
2ad207d4 2091 if (env->thumb && semihosting_enabled) {
d31dd73e 2092 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 2093 if (mask == 0xab
2094 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2095 env->regs[15] += 2;
2096 env->regs[0] = do_arm_semihosting(env);
2097 return;
2098 }
2099 }
81c05daf 2100 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 2101 /* Fall through to prefetch abort. */
2102 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 2103 new_mode = ARM_CPU_MODE_ABT;
2104 addr = 0x0c;
2105 mask = CPSR_A | CPSR_I;
2106 offset = 4;
2107 break;
2108 case EXCP_DATA_ABORT:
2109 new_mode = ARM_CPU_MODE_ABT;
2110 addr = 0x10;
2111 mask = CPSR_A | CPSR_I;
2112 offset = 8;
2113 break;
2114 case EXCP_IRQ:
2115 new_mode = ARM_CPU_MODE_IRQ;
2116 addr = 0x18;
2117 /* Disable IRQ and imprecise data aborts. */
2118 mask = CPSR_A | CPSR_I;
2119 offset = 4;
2120 break;
2121 case EXCP_FIQ:
2122 new_mode = ARM_CPU_MODE_FIQ;
2123 addr = 0x1c;
2124 /* Disable FIQ, IRQ and imprecise data aborts. */
2125 mask = CPSR_A | CPSR_I | CPSR_F;
2126 offset = 4;
2127 break;
2128 default:
2129 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2130 return; /* Never happens. Keep compiler happy. */
2131 }
2132 /* High vectors. */
2133 if (env->cp15.c1_sys & (1 << 13)) {
2134 addr += 0xffff0000;
2135 }
2136 switch_mode (env, new_mode);
2137 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 2138 /* Clear IT bits. */
2139 env->condexec_bits = 0;
30a8cac1 2140 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 2141 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 2142 env->uncached_cpsr |= mask;
be5e7a76
DES		 2143 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2144 * and we should just guard the thumb mode on V4 */
2145 if (arm_feature(env, ARM_FEATURE_V4T)) {
2146 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2147 }
b5ff1b31
FB		 2148 env->regs[14] = env->regs[15] + offset;
2149 env->regs[15] = addr;
259186a7 2150 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
b5ff1b31
FB		 2151}
2152
2153/* Check section/page access permissions.
2154 Returns the page protection flags, or zero if the access is not
2155 permitted. */
0ecb72a5 2156static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 2157 int access_type, int is_user)
b5ff1b31 2158{
9ee6e8bb
PB		 2159 int prot_ro;
2160
dd4ebc2e 2161 if (domain_prot == 3) {
b5ff1b31 2162 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 2163 }
b5ff1b31 2164
9ee6e8bb
PB		 2165 if (access_type == 1)
2166 prot_ro = 0;
2167 else
2168 prot_ro = PAGE_READ;
2169
b5ff1b31
FB		 2170 switch (ap) {
2171 case 0:
78600320 2172 if (access_type == 1)
b5ff1b31
FB		 2173 return 0;
2174 switch ((env->cp15.c1_sys >> 8) & 3) {
2175 case 1:
2176 return is_user ? 0 : PAGE_READ;
2177 case 2:
2178 return PAGE_READ;
2179 default:
2180 return 0;
2181 }
2182 case 1:
2183 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2184 case 2:
2185 if (is_user)
9ee6e8bb 2186 return prot_ro;
b5ff1b31
FB		 2187 else
2188 return PAGE_READ | PAGE_WRITE;
2189 case 3:
2190 return PAGE_READ | PAGE_WRITE;
d4934d18 2191 case 4: /* Reserved. */
9ee6e8bb
PB		 2192 return 0;
2193 case 5:
2194 return is_user ? 0 : prot_ro;
2195 case 6:
2196 return prot_ro;
d4934d18 2197 case 7:
0ab06d83 2198 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 2199 return 0;
2200 return prot_ro;
b5ff1b31
FB		 2201 default:
2202 abort();
2203 }
2204}
2205
0ecb72a5 2206static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 2207{
2208 uint32_t table;
2209
2210 if (address & env->cp15.c2_mask)
2211 table = env->cp15.c2_base1 & 0xffffc000;
2212 else
2213 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2214
2215 table |= (address >> 18) & 0x3ffc;
2216 return table;
2217}
2218
0ecb72a5 2219static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2220 int is_user, hwaddr *phys_ptr,
77a71dd1 2221 int *prot, target_ulong *page_size)
b5ff1b31
FB		 2222{
2223 int code;
2224 uint32_t table;
2225 uint32_t desc;
2226 int type;
2227 int ap;
2228 int domain;
dd4ebc2e 2229 int domain_prot;
a8170e5e 2230 hwaddr phys_addr;
b5ff1b31 2231
9ee6e8bb
PB		 2232 /* Pagetable walk. */
2233 /* Lookup l1 descriptor. */
b2fa1797 2234 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2235 desc = ldl_phys(table);
2236 type = (desc & 3);
dd4ebc2e
JCD		 2237 domain = (desc >> 5) & 0x0f;
2238 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 2239 if (type == 0) {
601d70b9 2240 /* Section translation fault. */
9ee6e8bb
PB		 2241 code = 5;
2242 goto do_fault;
2243 }
dd4ebc2e 2244 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 2245 if (type == 2)
2246 code = 9; /* Section domain fault. */
2247 else
2248 code = 11; /* Page domain fault. */
2249 goto do_fault;
2250 }
2251 if (type == 2) {
2252 /* 1Mb section. */
2253 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2254 ap = (desc >> 10) & 3;
2255 code = 13;
d4c430a8 2256 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2257 } else {
2258 /* Lookup l2 entry. */
2259 if (type == 1) {
2260 /* Coarse pagetable. */
2261 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2262 } else {
2263 /* Fine pagetable. */
2264 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2265 }
2266 desc = ldl_phys(table);
2267 switch (desc & 3) {
2268 case 0: /* Page translation fault. */
2269 code = 7;
2270 goto do_fault;
2271 case 1: /* 64k page. */
2272 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2273 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2274 *page_size = 0x10000;
ce819861 2275 break;
9ee6e8bb
PB		 2276 case 2: /* 4k page. */
2277 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2278 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2279 *page_size = 0x1000;
ce819861 2280 break;
9ee6e8bb
PB		 2281 case 3: /* 1k page. */
2282 if (type == 1) {
2283 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2284 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2285 } else {
2286 /* Page translation fault. */
2287 code = 7;
2288 goto do_fault;
2289 }
2290 } else {
2291 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2292 }
2293 ap = (desc >> 4) & 3;
d4c430a8 2294 *page_size = 0x400;
ce819861
PB		 2295 break;
2296 default:
9ee6e8bb
PB		 2297 /* Never happens, but compiler isn't smart enough to tell. */
2298 abort();
ce819861 2299 }
9ee6e8bb
PB		 2300 code = 15;
2301 }
dd4ebc2e 2302 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2303 if (!*prot) {
2304 /* Access permission fault. */
2305 goto do_fault;
2306 }
3ad493fc 2307 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2308 *phys_ptr = phys_addr;
2309 return 0;
2310do_fault:
2311 return code | (domain << 4);
2312}
2313
0ecb72a5 2314static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2315 int is_user, hwaddr *phys_ptr,
77a71dd1 2316 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2317{
2318 int code;
2319 uint32_t table;
2320 uint32_t desc;
2321 uint32_t xn;
de9b05b8 2322 uint32_t pxn = 0;
9ee6e8bb
PB		 2323 int type;
2324 int ap;
de9b05b8 2325 int domain = 0;
dd4ebc2e 2326 int domain_prot;
a8170e5e 2327 hwaddr phys_addr;
9ee6e8bb
PB		 2328
2329 /* Pagetable walk. */
2330 /* Lookup l1 descriptor. */
b2fa1797 2331 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2332 desc = ldl_phys(table);
2333 type = (desc & 3);
de9b05b8
PM		 2334 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2335 /* Section translation fault, or attempt to use the encoding
2336 * which is Reserved on implementations without PXN.
2337 */
9ee6e8bb 2338 code = 5;
9ee6e8bb 2339 goto do_fault;
de9b05b8
PM		 2340 }
2341 if ((type == 1) || !(desc & (1 << 18))) {
2342 /* Page or Section. */
dd4ebc2e 2343 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2344 }
dd4ebc2e
JCD		 2345 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2346 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2347 if (type != 1) {
9ee6e8bb 2348 code = 9; /* Section domain fault. */
de9b05b8 2349 } else {
9ee6e8bb 2350 code = 11; /* Page domain fault. */
de9b05b8 2351 }
9ee6e8bb
PB		 2352 goto do_fault;
2353 }
de9b05b8 2354 if (type != 1) {
9ee6e8bb
PB		 2355 if (desc & (1 << 18)) {
2356 /* Supersection. */
2357 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2358 *page_size = 0x1000000;
b5ff1b31 2359 } else {
9ee6e8bb
PB		 2360 /* Section. */
2361 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2362 *page_size = 0x100000;
b5ff1b31 2363 }
9ee6e8bb
PB		 2364 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2365 xn = desc & (1 << 4);
de9b05b8 2366 pxn = desc & 1;
9ee6e8bb
PB		 2367 code = 13;
2368 } else {
de9b05b8
PM		 2369 if (arm_feature(env, ARM_FEATURE_PXN)) {
2370 pxn = (desc >> 2) & 1;
2371 }
9ee6e8bb
PB		 2372 /* Lookup l2 entry. */
2373 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2374 desc = ldl_phys(table);
2375 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2376 switch (desc & 3) {
2377 case 0: /* Page translation fault. */
2378 code = 7;
b5ff1b31 2379 goto do_fault;
9ee6e8bb
PB		 2380 case 1: /* 64k page. */
2381 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2382 xn = desc & (1 << 15);
d4c430a8 2383 *page_size = 0x10000;
9ee6e8bb
PB		 2384 break;
2385 case 2: case 3: /* 4k page. */
2386 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2387 xn = desc & 1;
d4c430a8 2388 *page_size = 0x1000;
9ee6e8bb
PB		 2389 break;
2390 default:
2391 /* Never happens, but compiler isn't smart enough to tell. */
2392 abort();
b5ff1b31 2393 }
9ee6e8bb
PB		 2394 code = 15;
2395 }
dd4ebc2e 2396 if (domain_prot == 3) {
c0034328
JR		 2397 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2398 } else {
de9b05b8
PM		 2399 if (pxn && !is_user) {
2400 xn = 1;
2401 }
c0034328
JR		 2402 if (xn && access_type == 2)
2403 goto do_fault;
9ee6e8bb 2404
c0034328
JR		 2405 /* The simplified model uses AP[0] as an access control bit. */
2406 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2407 /* Access flag fault. */
2408 code = (code == 15) ? 6 : 3;
2409 goto do_fault;
2410 }
dd4ebc2e 2411 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2412 if (!*prot) {
2413 /* Access permission fault. */
2414 goto do_fault;
2415 }
2416 if (!xn) {
2417 *prot |= PAGE_EXEC;
2418 }
3ad493fc 2419 }
9ee6e8bb 2420 *phys_ptr = phys_addr;
b5ff1b31
FB		 2421 return 0;
2422do_fault:
2423 return code | (domain << 4);
2424}
2425
3dde962f
PM		 2426/* Fault type for long-descriptor MMU fault reporting; this corresponds
2427 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2428 */
2429typedef enum {
2430 translation_fault = 1,
2431 access_fault = 2,
2432 permission_fault = 3,
2433} MMUFaultType;
2434
2435static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2436 int access_type, int is_user,
a8170e5e 2437 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 2438 target_ulong *page_size_ptr)
2439{
2440 /* Read an LPAE long-descriptor translation table. */
2441 MMUFaultType fault_type = translation_fault;
2442 uint32_t level = 1;
2443 uint32_t epd;
2444 uint32_t tsz;
2445 uint64_t ttbr;
2446 int ttbr_select;
2447 int n;
a8170e5e 2448 hwaddr descaddr;
3dde962f
PM		 2449 uint32_t tableattrs;
2450 target_ulong page_size;
2451 uint32_t attrs;
2452
2453 /* Determine whether this address is in the region controlled by
2454 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2455 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2456 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2457 */
2458 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2459 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2460 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2461 /* there is a ttbr0 region and we are in it (high bits all zero) */
2462 ttbr_select = 0;
2463 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2464 /* there is a ttbr1 region and we are in it (high bits all one) */
2465 ttbr_select = 1;
2466 } else if (!t0sz) {
2467 /* ttbr0 region is "everything not in the ttbr1 region" */
2468 ttbr_select = 0;
2469 } else if (!t1sz) {
2470 /* ttbr1 region is "everything not in the ttbr0 region" */
2471 ttbr_select = 1;
2472 } else {
2473 /* in the gap between the two regions, this is a Translation fault */
2474 fault_type = translation_fault;
2475 goto do_fault;
2476 }
2477
2478 /* Note that QEMU ignores shareability and cacheability attributes,
2479 * so we don't need to do anything with the SH, ORGN, IRGN fields
2480 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2481 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2482 * implement any ASID-like capability so we can ignore it (instead
2483 * we will always flush the TLB any time the ASID is changed).
2484 */
2485 if (ttbr_select == 0) {
2486 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2487 epd = extract32(env->cp15.c2_control, 7, 1);
2488 tsz = t0sz;
2489 } else {
2490 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2491 epd = extract32(env->cp15.c2_control, 23, 1);
2492 tsz = t1sz;
2493 }
2494
2495 if (epd) {
2496 /* Translation table walk disabled => Translation fault on TLB miss */
2497 goto do_fault;
2498 }
2499
2500 /* If the region is small enough we will skip straight to a 2nd level
2501 * lookup. This affects the number of bits of the address used in
2502 * combination with the TTBR to find the first descriptor. ('n' here
2503 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2504 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2505 */
2506 if (tsz > 1) {
2507 level = 2;
2508 n = 14 - tsz;
2509 } else {
2510 n = 5 - tsz;
2511 }
2512
2513 /* Clear the vaddr bits which aren't part of the within-region address,
2514 * so that we don't have to special case things when calculating the
2515 * first descriptor address.
2516 */
2517 address &= (0xffffffffU >> tsz);
2518
2519 /* Now we can extract the actual base address from the TTBR */
2520 descaddr = extract64(ttbr, 0, 40);
2521 descaddr &= ~((1ULL << n) - 1);
2522
2523 tableattrs = 0;
2524 for (;;) {
2525 uint64_t descriptor;
2526
2527 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2528 descriptor = ldq_phys(descaddr);
2529 if (!(descriptor & 1) ||
2530 (!(descriptor & 2) && (level == 3))) {
2531 /* Invalid, or the Reserved level 3 encoding */
2532 goto do_fault;
2533 }
2534 descaddr = descriptor & 0xfffffff000ULL;
2535
2536 if ((descriptor & 2) && (level < 3)) {
2537 /* Table entry. The top five bits are attributes which may
2538 * propagate down through lower levels of the table (and
2539 * which are all arranged so that 0 means "no effect", so
2540 * we can gather them up by ORing in the bits at each level).
2541 */
2542 tableattrs |= extract64(descriptor, 59, 5);
2543 level++;
2544 continue;
2545 }
2546 /* Block entry at level 1 or 2, or page entry at level 3.
2547 * These are basically the same thing, although the number
2548 * of bits we pull in from the vaddr varies.
2549 */
2550 page_size = (1 << (39 - (9 * level)));
2551 descaddr |= (address & (page_size - 1));
2552 /* Extract attributes from the descriptor and merge with table attrs */
2553 attrs = extract64(descriptor, 2, 10)
2554 | (extract64(descriptor, 52, 12) << 10);
2555 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2556 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2557 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2558 * means "force PL1 access only", which means forcing AP[1] to 0.
2559 */
2560 if (extract32(tableattrs, 2, 1)) {
2561 attrs &= ~(1 << 4);
2562 }
2563 /* Since we're always in the Non-secure state, NSTable is ignored. */
2564 break;
2565 }
2566 /* Here descaddr is the final physical address, and attributes
2567 * are all in attrs.
2568 */
2569 fault_type = access_fault;
2570 if ((attrs & (1 << 8)) == 0) {
2571 /* Access flag */
2572 goto do_fault;
2573 }
2574 fault_type = permission_fault;
2575 if (is_user && !(attrs & (1 << 4))) {
2576 /* Unprivileged access not enabled */
2577 goto do_fault;
2578 }
2579 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2580 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2581 /* XN or PXN */
2582 if (access_type == 2) {
2583 goto do_fault;
2584 }
2585 *prot &= ~PAGE_EXEC;
2586 }
2587 if (attrs & (1 << 5)) {
2588 /* Write access forbidden */
2589 if (access_type == 1) {
2590 goto do_fault;
2591 }
2592 *prot &= ~PAGE_WRITE;
2593 }
2594
2595 *phys_ptr = descaddr;
2596 *page_size_ptr = page_size;
2597 return 0;
2598
2599do_fault:
2600 /* Long-descriptor format IFSR/DFSR value */
2601 return (1 << 9) | (fault_type << 2) | level;
2602}
2603
77a71dd1
PM		 2604static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2605 int access_type, int is_user,
a8170e5e 2606 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 2607{
2608 int n;
2609 uint32_t mask;
2610 uint32_t base;
2611
2612 *phys_ptr = address;
2613 for (n = 7; n >= 0; n--) {
2614 base = env->cp15.c6_region[n];
2615 if ((base & 1) == 0)
2616 continue;
2617 mask = 1 << ((base >> 1) & 0x1f);
2618 /* Keep this shift separate from the above to avoid an
2619 (undefined) << 32. */
2620 mask = (mask << 1) - 1;
2621 if (((base ^ address) & ~mask) == 0)
2622 break;
2623 }
2624 if (n < 0)
2625 return 2;
2626
2627 if (access_type == 2) {
2628 mask = env->cp15.c5_insn;
2629 } else {
2630 mask = env->cp15.c5_data;
2631 }
2632 mask = (mask >> (n * 4)) & 0xf;
2633 switch (mask) {
2634 case 0:
2635 return 1;
2636 case 1:
2637 if (is_user)
2638 return 1;
2639 *prot = PAGE_READ | PAGE_WRITE;
2640 break;
2641 case 2:
2642 *prot = PAGE_READ;
2643 if (!is_user)
2644 *prot |= PAGE_WRITE;
2645 break;
2646 case 3:
2647 *prot = PAGE_READ | PAGE_WRITE;
2648 break;
2649 case 5:
2650 if (is_user)
2651 return 1;
2652 *prot = PAGE_READ;
2653 break;
2654 case 6:
2655 *prot = PAGE_READ;
2656 break;
2657 default:
2658 /* Bad permission. */
2659 return 1;
2660 }
3ad493fc 2661 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2662 return 0;
2663}
2664
702a9357
PM		 2665/* get_phys_addr - get the physical address for this virtual address
2666 *
2667 * Find the physical address corresponding to the given virtual address,
2668 * by doing a translation table walk on MMU based systems or using the
2669 * MPU state on MPU based systems.
2670 *
2671 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2672 * prot and page_size are not filled in, and the return value provides
2673 * information on why the translation aborted, in the format of a
2674 * DFSR/IFSR fault register, with the following caveats:
2675 * * we honour the short vs long DFSR format differences.
2676 * * the WnR bit is never set (the caller must do this).
2677 * * for MPU based systems we don't bother to return a full FSR format
2678 * value.
2679 *
2680 * @env: CPUARMState
2681 * @address: virtual address to get physical address for
2682 * @access_type: 0 for read, 1 for write, 2 for execute
2683 * @is_user: 0 for privileged access, 1 for user
2684 * @phys_ptr: set to the physical address corresponding to the virtual address
2685 * @prot: set to the permissions for the page containing phys_ptr
2686 * @page_size: set to the size of the page containing phys_ptr
2687 */
0ecb72a5 2688static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2689 int access_type, int is_user,
a8170e5e 2690 hwaddr *phys_ptr, int *prot,
d4c430a8 2691 target_ulong *page_size)
9ee6e8bb
PB		 2692{
2693 /* Fast Context Switch Extension. */
2694 if (address < 0x02000000)
2695 address += env->cp15.c13_fcse;
2696
2697 if ((env->cp15.c1_sys & 1) == 0) {
2698 /* MMU/MPU disabled. */
2699 *phys_ptr = address;
3ad493fc 2700 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2701 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2702 return 0;
2703 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2704 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2705 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2706 prot);
3dde962f
PM		 2707 } else if (extended_addresses_enabled(env)) {
2708 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2709 prot, page_size);
9ee6e8bb
PB		 2710 } else if (env->cp15.c1_sys & (1 << 23)) {
2711 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2712 prot, page_size);
9ee6e8bb
PB		 2713 } else {
2714 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2715 prot, page_size);
9ee6e8bb
PB		 2716 }
2717}
2718
0ecb72a5 2719int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2720 int access_type, int mmu_idx)
b5ff1b31 2721{
a8170e5e 2722 hwaddr phys_addr;
d4c430a8 2723 target_ulong page_size;
b5ff1b31 2724 int prot;
6ebbf390 2725 int ret, is_user;
b5ff1b31 2726
6ebbf390 2727 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2728 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2729 &page_size);
b5ff1b31
FB		 2730 if (ret == 0) {
2731 /* Map a single [sub]page. */
a8170e5e 2732 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 2733 address &= ~(uint32_t)0x3ff;
3ad493fc 2734 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2735 return 0;
b5ff1b31
FB		 2736 }
2737
2738 if (access_type == 2) {
2739 env->cp15.c5_insn = ret;
2740 env->cp15.c6_insn = address;
2741 env->exception_index = EXCP_PREFETCH_ABORT;
2742 } else {
2743 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2744 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2745 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2746 env->cp15.c6_data = address;
2747 env->exception_index = EXCP_DATA_ABORT;
2748 }
2749 return 1;
2750}
2751
a8170e5e 2752hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31 2753{
a8170e5e 2754 hwaddr phys_addr;
d4c430a8 2755 target_ulong page_size;
b5ff1b31
FB		 2756 int prot;
2757 int ret;
2758
d4c430a8 2759 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2760
2761 if (ret != 0)
2762 return -1;
2763
2764 return phys_addr;
2765}
2766
0ecb72a5 2767void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2768{
39ea3d4e
PM		 2769 if ((env->uncached_cpsr & CPSR_M) == mode) {
2770 env->regs[13] = val;
2771 } else {
f5206413 2772 env->banked_r13[bank_number(mode)] = val;
39ea3d4e 2773 }
9ee6e8bb
PB		 2774}
2775
0ecb72a5 2776uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2777{
39ea3d4e
PM		 2778 if ((env->uncached_cpsr & CPSR_M) == mode) {
2779 return env->regs[13];
2780 } else {
f5206413 2781 return env->banked_r13[bank_number(mode)];
39ea3d4e 2782 }
9ee6e8bb
PB		 2783}
2784
0ecb72a5 2785uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2786{
2787 switch (reg) {
2788 case 0: /* APSR */
2789 return xpsr_read(env) & 0xf8000000;
2790 case 1: /* IAPSR */
2791 return xpsr_read(env) & 0xf80001ff;
2792 case 2: /* EAPSR */
2793 return xpsr_read(env) & 0xff00fc00;
2794 case 3: /* xPSR */
2795 return xpsr_read(env) & 0xff00fdff;
2796 case 5: /* IPSR */
2797 return xpsr_read(env) & 0x000001ff;
2798 case 6: /* EPSR */
2799 return xpsr_read(env) & 0x0700fc00;
2800 case 7: /* IEPSR */
2801 return xpsr_read(env) & 0x0700edff;
2802 case 8: /* MSP */
2803 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2804 case 9: /* PSP */
2805 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2806 case 16: /* PRIMASK */
2807 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2808 case 17: /* BASEPRI */
2809 case 18: /* BASEPRI_MAX */
9ee6e8bb 2810 return env->v7m.basepri;
82845826
SH		 2811 case 19: /* FAULTMASK */
2812 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2813 case 20: /* CONTROL */
2814 return env->v7m.control;
2815 default:
2816 /* ??? For debugging only. */
2817 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2818 return 0;
2819 }
2820}
2821
0ecb72a5 2822void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2823{
2824 switch (reg) {
2825 case 0: /* APSR */
2826 xpsr_write(env, val, 0xf8000000);
2827 break;
2828 case 1: /* IAPSR */
2829 xpsr_write(env, val, 0xf8000000);
2830 break;
2831 case 2: /* EAPSR */
2832 xpsr_write(env, val, 0xfe00fc00);
2833 break;
2834 case 3: /* xPSR */
2835 xpsr_write(env, val, 0xfe00fc00);
2836 break;
2837 case 5: /* IPSR */
2838 /* IPSR bits are readonly. */
2839 break;
2840 case 6: /* EPSR */
2841 xpsr_write(env, val, 0x0600fc00);
2842 break;
2843 case 7: /* IEPSR */
2844 xpsr_write(env, val, 0x0600fc00);
2845 break;
2846 case 8: /* MSP */
2847 if (env->v7m.current_sp)
2848 env->v7m.other_sp = val;
2849 else
2850 env->regs[13] = val;
2851 break;
2852 case 9: /* PSP */
2853 if (env->v7m.current_sp)
2854 env->regs[13] = val;
2855 else
2856 env->v7m.other_sp = val;
2857 break;
2858 case 16: /* PRIMASK */
2859 if (val & 1)
2860 env->uncached_cpsr |= CPSR_I;
2861 else
2862 env->uncached_cpsr &= ~CPSR_I;
2863 break;
82845826 2864 case 17: /* BASEPRI */
9ee6e8bb
PB		 2865 env->v7m.basepri = val & 0xff;
2866 break;
82845826 2867 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2868 val &= 0xff;
2869 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2870 env->v7m.basepri = val;
2871 break;
82845826
SH		 2872 case 19: /* FAULTMASK */
2873 if (val & 1)
2874 env->uncached_cpsr |= CPSR_F;
2875 else
2876 env->uncached_cpsr &= ~CPSR_F;
2877 break;
9ee6e8bb
PB		 2878 case 20: /* CONTROL */
2879 env->v7m.control = val & 3;
2880 switch_v7m_sp(env, (val & 2) != 0);
2881 break;
2882 default:
2883 /* ??? For debugging only. */
2884 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2885 return;
2886 }
2887}
2888
b5ff1b31 2889#endif
6ddbc6e4
PB		 2890
2891/* Note that signed overflow is undefined in C. The following routines are
2892 careful to use unsigned types where modulo arithmetic is required.
2893 Failure to do so _will_ break on newer gcc. */
2894
2895/* Signed saturating arithmetic. */
2896
1654b2d6 2897/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2898static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2899{
2900 uint16_t res;
2901
2902 res = a + b;
2903 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2904 if (a & 0x8000)
2905 res = 0x8000;
2906 else
2907 res = 0x7fff;
2908 }
2909 return res;
2910}
2911
1654b2d6 2912/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2913static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2914{
2915 uint8_t res;
2916
2917 res = a + b;
2918 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2919 if (a & 0x80)
2920 res = 0x80;
2921 else
2922 res = 0x7f;
2923 }
2924 return res;
2925}
2926
1654b2d6 2927/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2928static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2929{
2930 uint16_t res;
2931
2932 res = a - b;
2933 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2934 if (a & 0x8000)
2935 res = 0x8000;
2936 else
2937 res = 0x7fff;
2938 }
2939 return res;
2940}
2941
1654b2d6 2942/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2943static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2944{
2945 uint8_t res;
2946
2947 res = a - b;
2948 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2949 if (a & 0x80)
2950 res = 0x80;
2951 else
2952 res = 0x7f;
2953 }
2954 return res;
2955}
2956
2957#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2958#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2959#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2960#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2961#define PFX q
2962
2963#include "op_addsub.h"
2964
2965/* Unsigned saturating arithmetic. */
460a09c1 2966static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2967{
2968 uint16_t res;
2969 res = a + b;
2970 if (res < a)
2971 res = 0xffff;
2972 return res;
2973}
2974
460a09c1 2975static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2976{
4c4fd3f8 2977 if (a > b)
6ddbc6e4
PB		 2978 return a - b;
2979 else
2980 return 0;
2981}
2982
2983static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2984{
2985 uint8_t res;
2986 res = a + b;
2987 if (res < a)
2988 res = 0xff;
2989 return res;
2990}
2991
2992static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2993{
4c4fd3f8 2994 if (a > b)
6ddbc6e4
PB		 2995 return a - b;
2996 else
2997 return 0;
2998}
2999
3000#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3001#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3002#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3003#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3004#define PFX uq
3005
3006#include "op_addsub.h"
3007
3008/* Signed modulo arithmetic. */
3009#define SARITH16(a, b, n, op) do { \
3010 int32_t sum; \
db6e2e65 3011 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 3012 RESULT(sum, n, 16); \
3013 if (sum >= 0) \
3014 ge |= 3 << (n * 2); \
3015 } while(0)
3016
3017#define SARITH8(a, b, n, op) do { \
3018 int32_t sum; \
db6e2e65 3019 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 3020 RESULT(sum, n, 8); \
3021 if (sum >= 0) \
3022 ge |= 1 << n; \
3023 } while(0)
3024
3025
3026#define ADD16(a, b, n) SARITH16(a, b, n, +)
3027#define SUB16(a, b, n) SARITH16(a, b, n, -)
3028#define ADD8(a, b, n) SARITH8(a, b, n, +)
3029#define SUB8(a, b, n) SARITH8(a, b, n, -)
3030#define PFX s
3031#define ARITH_GE
3032
3033#include "op_addsub.h"
3034
3035/* Unsigned modulo arithmetic. */
3036#define ADD16(a, b, n) do { \
3037 uint32_t sum; \
3038 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3039 RESULT(sum, n, 16); \
a87aa10b 3040 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 3041 ge |= 3 << (n * 2); \
3042 } while(0)
3043
3044#define ADD8(a, b, n) do { \
3045 uint32_t sum; \
3046 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3047 RESULT(sum, n, 8); \
a87aa10b
AZ		 3048 if ((sum >> 8) == 1) \
3049 ge |= 1 << n; \
6ddbc6e4
PB		 3050 } while(0)
3051
3052#define SUB16(a, b, n) do { \
3053 uint32_t sum; \
3054 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3055 RESULT(sum, n, 16); \
3056 if ((sum >> 16) == 0) \
3057 ge |= 3 << (n * 2); \
3058 } while(0)
3059
3060#define SUB8(a, b, n) do { \
3061 uint32_t sum; \
3062 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3063 RESULT(sum, n, 8); \
3064 if ((sum >> 8) == 0) \
a87aa10b 3065 ge |= 1 << n; \
6ddbc6e4
PB		 3066 } while(0)
3067
3068#define PFX u
3069#define ARITH_GE
3070
3071#include "op_addsub.h"
3072
3073/* Halved signed arithmetic. */
3074#define ADD16(a, b, n) \
3075 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3076#define SUB16(a, b, n) \
3077 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3078#define ADD8(a, b, n) \
3079 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3080#define SUB8(a, b, n) \
3081 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3082#define PFX sh
3083
3084#include "op_addsub.h"
3085
3086/* Halved unsigned arithmetic. */
3087#define ADD16(a, b, n) \
3088 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3089#define SUB16(a, b, n) \
3090 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3091#define ADD8(a, b, n) \
3092 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3093#define SUB8(a, b, n) \
3094 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3095#define PFX uh
3096
3097#include "op_addsub.h"
3098
3099static inline uint8_t do_usad(uint8_t a, uint8_t b)
3100{
3101 if (a > b)
3102 return a - b;
3103 else
3104 return b - a;
3105}
3106
3107/* Unsigned sum of absolute byte differences. */
3108uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3109{
3110 uint32_t sum;
3111 sum = do_usad(a, b);
3112 sum += do_usad(a >> 8, b >> 8);
3113 sum += do_usad(a >> 16, b >>16);
3114 sum += do_usad(a >> 24, b >> 24);
3115 return sum;
3116}
3117
3118/* For ARMv6 SEL instruction. */
3119uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3120{
3121 uint32_t mask;
3122
3123 mask = 0;
3124 if (flags & 1)
3125 mask |= 0xff;
3126 if (flags & 2)
3127 mask |= 0xff00;
3128 if (flags & 4)
3129 mask |= 0xff0000;
3130 if (flags & 8)
3131 mask |= 0xff000000;
3132 return (a & mask) | (b & ~mask);
3133}
3134
b90372ad
PM		 3135/* VFP support. We follow the convention used for VFP instructions:
3136 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 3137 "d" suffix. */
3138
3139/* Convert host exception flags to vfp form. */
3140static inline int vfp_exceptbits_from_host(int host_bits)
3141{
3142 int target_bits = 0;
3143
3144 if (host_bits & float_flag_invalid)
3145 target_bits |= 1;
3146 if (host_bits & float_flag_divbyzero)
3147 target_bits |= 2;
3148 if (host_bits & float_flag_overflow)
3149 target_bits |= 4;
36802b6b 3150 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 3151 target_bits |= 8;
3152 if (host_bits & float_flag_inexact)
3153 target_bits |= 0x10;
cecd8504
PM		 3154 if (host_bits & float_flag_input_denormal)
3155 target_bits |= 0x80;
4373f3ce
PB		 3156 return target_bits;
3157}
3158
0ecb72a5 3159uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 3160{
3161 int i;
3162 uint32_t fpscr;
3163
3164 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3165 | (env->vfp.vec_len << 16)
3166 | (env->vfp.vec_stride << 20);
3167 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 3168 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 3169 fpscr |= vfp_exceptbits_from_host(i);
3170 return fpscr;
3171}
3172
0ecb72a5 3173uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 3174{
3175 return HELPER(vfp_get_fpscr)(env);
3176}
3177
4373f3ce
PB		 3178/* Convert vfp exception flags to target form. */
3179static inline int vfp_exceptbits_to_host(int target_bits)
3180{
3181 int host_bits = 0;
3182
3183 if (target_bits & 1)
3184 host_bits |= float_flag_invalid;
3185 if (target_bits & 2)
3186 host_bits |= float_flag_divbyzero;
3187 if (target_bits & 4)
3188 host_bits |= float_flag_overflow;
3189 if (target_bits & 8)
3190 host_bits |= float_flag_underflow;
3191 if (target_bits & 0x10)
3192 host_bits |= float_flag_inexact;
cecd8504
PM		 3193 if (target_bits & 0x80)
3194 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 3195 return host_bits;
3196}
3197
0ecb72a5 3198void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 3199{
3200 int i;
3201 uint32_t changed;
3202
3203 changed = env->vfp.xregs[ARM_VFP_FPSCR];
3204 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3205 env->vfp.vec_len = (val >> 16) & 7;
3206 env->vfp.vec_stride = (val >> 20) & 3;
3207
3208 changed ^= val;
3209 if (changed & (3 << 22)) {
3210 i = (val >> 22) & 3;
3211 switch (i) {
3212 case 0:
3213 i = float_round_nearest_even;
3214 break;
3215 case 1:
3216 i = float_round_up;
3217 break;
3218 case 2:
3219 i = float_round_down;
3220 break;
3221 case 3:
3222 i = float_round_to_zero;
3223 break;
3224 }
3225 set_float_rounding_mode(i, &env->vfp.fp_status);
3226 }
cecd8504 3227 if (changed & (1 << 24)) {
fe76d976 3228 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 3229 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3230 }
5c7908ed
PB		 3231 if (changed & (1 << 25))
3232 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 3233
b12c390b 3234 i = vfp_exceptbits_to_host(val);
4373f3ce 3235 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 3236 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 3237}
3238
0ecb72a5 3239void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 3240{
3241 HELPER(vfp_set_fpscr)(env, val);
3242}
3243
4373f3ce
PB		 3244#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3245
3246#define VFP_BINOP(name) \
ae1857ec 3247float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3248{ \
ae1857ec
PM		 3249 float_status *fpst = fpstp; \
3250 return float32_ ## name(a, b, fpst); \
4373f3ce 3251} \
ae1857ec 3252float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3253{ \
ae1857ec
PM		 3254 float_status *fpst = fpstp; \
3255 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3256}
3257VFP_BINOP(add)
3258VFP_BINOP(sub)
3259VFP_BINOP(mul)
3260VFP_BINOP(div)
3261#undef VFP_BINOP
3262
3263float32 VFP_HELPER(neg, s)(float32 a)
3264{
3265 return float32_chs(a);
3266}
3267
3268float64 VFP_HELPER(neg, d)(float64 a)
3269{
66230e0d 3270 return float64_chs(a);
4373f3ce
PB		 3271}
3272
3273float32 VFP_HELPER(abs, s)(float32 a)
3274{
3275 return float32_abs(a);
3276}
3277
3278float64 VFP_HELPER(abs, d)(float64 a)
3279{
66230e0d 3280 return float64_abs(a);
4373f3ce
PB		 3281}
3282
0ecb72a5 3283float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3284{
3285 return float32_sqrt(a, &env->vfp.fp_status);
3286}
3287
0ecb72a5 3288float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3289{
3290 return float64_sqrt(a, &env->vfp.fp_status);
3291}
3292
3293/* XXX: check quiet/signaling case */
3294#define DO_VFP_cmp(p, type) \
0ecb72a5 3295void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3296{ \
3297 uint32_t flags; \
3298 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3299 case 0: flags = 0x6; break; \
3300 case -1: flags = 0x8; break; \
3301 case 1: flags = 0x2; break; \
3302 default: case 2: flags = 0x3; break; \
3303 } \
3304 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3305 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3306} \
0ecb72a5 3307void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3308{ \
3309 uint32_t flags; \
3310 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3311 case 0: flags = 0x6; break; \
3312 case -1: flags = 0x8; break; \
3313 case 1: flags = 0x2; break; \
3314 default: case 2: flags = 0x3; break; \
3315 } \
3316 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3317 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3318}
3319DO_VFP_cmp(s, float32)
3320DO_VFP_cmp(d, float64)
3321#undef DO_VFP_cmp
3322
5500b06c 3323/* Integer to float and float to integer conversions */
4373f3ce 3324
5500b06c
PM		 3325#define CONV_ITOF(name, fsz, sign) \
3326 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3327{ \
3328 float_status *fpst = fpstp; \
85836979 3329 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3330}
3331
5500b06c
PM		 3332#define CONV_FTOI(name, fsz, sign, round) \
3333uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3334{ \
3335 float_status *fpst = fpstp; \
3336 if (float##fsz##_is_any_nan(x)) { \
3337 float_raise(float_flag_invalid, fpst); \
3338 return 0; \
3339 } \
3340 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3341}
3342
5500b06c
PM		 3343#define FLOAT_CONVS(name, p, fsz, sign) \
3344CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3345CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3346CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3347
5500b06c
PM		 3348FLOAT_CONVS(si, s, 32, )
3349FLOAT_CONVS(si, d, 64, )
3350FLOAT_CONVS(ui, s, 32, u)
3351FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3352
5500b06c
PM		 3353#undef CONV_ITOF
3354#undef CONV_FTOI
3355#undef FLOAT_CONVS
4373f3ce
PB		 3356
3357/* floating point conversion */
0ecb72a5 3358float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3359{
2d627737
PM		 3360 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3361 /* ARM requires that S<->D conversion of any kind of NaN generates
3362 * a quiet NaN by forcing the most significant frac bit to 1.
3363 */
3364 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3365}
3366
0ecb72a5 3367float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3368{
2d627737
PM		 3369 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3370 /* ARM requires that S<->D conversion of any kind of NaN generates
3371 * a quiet NaN by forcing the most significant frac bit to 1.
3372 */
3373 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3374}
3375
3376/* VFP3 fixed point conversion. */
622465e1 3377#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 3378float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3379 void *fpstp) \
4373f3ce 3380{ \
5500b06c 3381 float_status *fpst = fpstp; \
622465e1 3382 float##fsz tmp; \
5500b06c
PM		 3383 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3384 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 3385} \
5500b06c
PM		 3386uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3387 void *fpstp) \
4373f3ce 3388{ \
5500b06c 3389 float_status *fpst = fpstp; \
622465e1
PM		 3390 float##fsz tmp; \
3391 if (float##fsz##_is_any_nan(x)) { \
5500b06c 3392 float_raise(float_flag_invalid, fpst); \
622465e1 3393 return 0; \
09d9487f 3394 } \
5500b06c
PM		 3395 tmp = float##fsz##_scalbn(x, shift, fpst); \
3396 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 3397}
3398
3399VFP_CONV_FIX(sh, d, 64, int16, )
3400VFP_CONV_FIX(sl, d, 64, int32, )
3401VFP_CONV_FIX(uh, d, 64, uint16, u)
3402VFP_CONV_FIX(ul, d, 64, uint32, u)
3403VFP_CONV_FIX(sh, s, 32, int16, )
3404VFP_CONV_FIX(sl, s, 32, int32, )
3405VFP_CONV_FIX(uh, s, 32, uint16, u)
3406VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 3407#undef VFP_CONV_FIX
3408
60011498 3409/* Half precision conversions. */
0ecb72a5 3410static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 3411{
60011498 3412 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3413 float32 r = float16_to_float32(make_float16(a), ieee, s);
3414 if (ieee) {
3415 return float32_maybe_silence_nan(r);
3416 }
3417 return r;
60011498
PB		 3418}
3419
0ecb72a5 3420static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 3421{
60011498 3422 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3423 float16 r = float32_to_float16(a, ieee, s);
3424 if (ieee) {
3425 r = float16_maybe_silence_nan(r);
3426 }
3427 return float16_val(r);
60011498
PB		 3428}
3429
0ecb72a5 3430float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3431{
3432 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3433}
3434
0ecb72a5 3435uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3436{
3437 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3438}
3439
0ecb72a5 3440float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3441{
3442 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3443}
3444
0ecb72a5 3445uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3446{
3447 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3448}
3449
dda3ec49 3450#define float32_two make_float32(0x40000000)
6aae3df1
PM		 3451#define float32_three make_float32(0x40400000)
3452#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 3453
0ecb72a5 3454float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3455{
dda3ec49
PM		 3456 float_status *s = &env->vfp.standard_fp_status;
3457 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3458 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3459 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3460 float_raise(float_flag_input_denormal, s);
3461 }
dda3ec49
PM		 3462 return float32_two;
3463 }
3464 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 3465}
3466
0ecb72a5 3467float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3468{
71826966 3469 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 3470 float32 product;
3471 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3472 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3473 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3474 float_raise(float_flag_input_denormal, s);
3475 }
6aae3df1 3476 return float32_one_point_five;
9ea62f57 3477 }
6aae3df1
PM		 3478 product = float32_mul(a, b, s);
3479 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 3480}
3481
8f8e3aa4
PB		 3482/* NEON helpers. */
3483
56bf4fe2
CL		 3484/* Constants 256 and 512 are used in some helpers; we avoid relying on
3485 * int->float conversions at run-time. */
3486#define float64_256 make_float64(0x4070000000000000LL)
3487#define float64_512 make_float64(0x4080000000000000LL)
3488
fe0e4872
CL		 3489/* The algorithm that must be used to calculate the estimate
3490 * is specified by the ARM ARM.
3491 */
0ecb72a5 3492static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 3493{
1146a817
PM		 3494 /* These calculations mustn't set any fp exception flags,
3495 * so we use a local copy of the fp_status.
3496 */
3497 float_status dummy_status = env->vfp.standard_fp_status;
3498 float_status *s = &dummy_status;
fe0e4872
CL		 3499 /* q = (int)(a * 512.0) */
3500 float64 q = float64_mul(float64_512, a, s);
3501 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3502
3503 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3504 q = int64_to_float64(q_int, s);
3505 q = float64_add(q, float64_half, s);
3506 q = float64_div(q, float64_512, s);
3507 q = float64_div(float64_one, q, s);
3508
3509 /* s = (int)(256.0 * r + 0.5) */
3510 q = float64_mul(q, float64_256, s);
3511 q = float64_add(q, float64_half, s);
3512 q_int = float64_to_int64_round_to_zero(q, s);
3513
3514 /* return (double)s / 256.0 */
3515 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3516}
3517
0ecb72a5 3518float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 3519{
fe0e4872
CL		 3520 float_status *s = &env->vfp.standard_fp_status;
3521 float64 f64;
3522 uint32_t val32 = float32_val(a);
3523
3524 int result_exp;
3525 int a_exp = (val32 & 0x7f800000) >> 23;
3526 int sign = val32 & 0x80000000;
3527
3528 if (float32_is_any_nan(a)) {
3529 if (float32_is_signaling_nan(a)) {
3530 float_raise(float_flag_invalid, s);
3531 }
3532 return float32_default_nan;
3533 } else if (float32_is_infinity(a)) {
3534 return float32_set_sign(float32_zero, float32_is_neg(a));
3535 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3536 if (!float32_is_zero(a)) {
3537 float_raise(float_flag_input_denormal, s);
3538 }
fe0e4872
CL		 3539 float_raise(float_flag_divbyzero, s);
3540 return float32_set_sign(float32_infinity, float32_is_neg(a));
3541 } else if (a_exp >= 253) {
3542 float_raise(float_flag_underflow, s);
3543 return float32_set_sign(float32_zero, float32_is_neg(a));
3544 }
3545
3546 f64 = make_float64((0x3feULL << 52)
3547 | ((int64_t)(val32 & 0x7fffff) << 29));
3548
3549 result_exp = 253 - a_exp;
3550
3551 f64 = recip_estimate(f64, env);
3552
3553 val32 = sign
3554 | ((result_exp & 0xff) << 23)
3555 | ((float64_val(f64) >> 29) & 0x7fffff);
3556 return make_float32(val32);
4373f3ce
PB		 3557}
3558
e07be5d2
CL		 3559/* The algorithm that must be used to calculate the estimate
3560 * is specified by the ARM ARM.
3561 */
0ecb72a5 3562static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3563{
1146a817
PM		 3564 /* These calculations mustn't set any fp exception flags,
3565 * so we use a local copy of the fp_status.
3566 */
3567 float_status dummy_status = env->vfp.standard_fp_status;
3568 float_status *s = &dummy_status;
e07be5d2
CL		 3569 float64 q;
3570 int64_t q_int;
3571
3572 if (float64_lt(a, float64_half, s)) {
3573 /* range 0.25 <= a < 0.5 */
3574
3575 /* a in units of 1/512 rounded down */
3576 /* q0 = (int)(a * 512.0); */
3577 q = float64_mul(float64_512, a, s);
3578 q_int = float64_to_int64_round_to_zero(q, s);
3579
3580 /* reciprocal root r */
3581 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3582 q = int64_to_float64(q_int, s);
3583 q = float64_add(q, float64_half, s);
3584 q = float64_div(q, float64_512, s);
3585 q = float64_sqrt(q, s);
3586 q = float64_div(float64_one, q, s);
3587 } else {
3588 /* range 0.5 <= a < 1.0 */
3589
3590 /* a in units of 1/256 rounded down */
3591 /* q1 = (int)(a * 256.0); */
3592 q = float64_mul(float64_256, a, s);
3593 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3594
3595 /* reciprocal root r */
3596 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3597 q = int64_to_float64(q_int, s);
3598 q = float64_add(q, float64_half, s);
3599 q = float64_div(q, float64_256, s);
3600 q = float64_sqrt(q, s);
3601 q = float64_div(float64_one, q, s);
3602 }
3603 /* r in units of 1/256 rounded to nearest */
3604 /* s = (int)(256.0 * r + 0.5); */
3605
3606 q = float64_mul(q, float64_256,s );
3607 q = float64_add(q, float64_half, s);
3608 q_int = float64_to_int64_round_to_zero(q, s);
3609
3610 /* return (double)s / 256.0;*/
3611 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3612}
3613
0ecb72a5 3614float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3615{
e07be5d2
CL		 3616 float_status *s = &env->vfp.standard_fp_status;
3617 int result_exp;
3618 float64 f64;
3619 uint32_t val;
3620 uint64_t val64;
3621
3622 val = float32_val(a);
3623
3624 if (float32_is_any_nan(a)) {
3625 if (float32_is_signaling_nan(a)) {
3626 float_raise(float_flag_invalid, s);
3627 }
3628 return float32_default_nan;
3629 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3630 if (!float32_is_zero(a)) {
3631 float_raise(float_flag_input_denormal, s);
3632 }
e07be5d2
CL		 3633 float_raise(float_flag_divbyzero, s);
3634 return float32_set_sign(float32_infinity, float32_is_neg(a));
3635 } else if (float32_is_neg(a)) {
3636 float_raise(float_flag_invalid, s);
3637 return float32_default_nan;
3638 } else if (float32_is_infinity(a)) {
3639 return float32_zero;
3640 }
3641
3642 /* Normalize to a double-precision value between 0.25 and 1.0,
3643 * preserving the parity of the exponent. */
3644 if ((val & 0x800000) == 0) {
3645 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3646 | (0x3feULL << 52)
3647 | ((uint64_t)(val & 0x7fffff) << 29));
3648 } else {
3649 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3650 | (0x3fdULL << 52)
3651 | ((uint64_t)(val & 0x7fffff) << 29));
3652 }
3653
3654 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3655
3656 f64 = recip_sqrt_estimate(f64, env);
3657
3658 val64 = float64_val(f64);
3659
26cc6abf 3660 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3661 | ((val64 >> 29) & 0x7fffff);
3662 return make_float32(val);
4373f3ce
PB		 3663}
3664
0ecb72a5 3665uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3666{
fe0e4872
CL		 3667 float64 f64;
3668
3669 if ((a & 0x80000000) == 0) {
3670 return 0xffffffff;
3671 }
3672
3673 f64 = make_float64((0x3feULL << 52)
3674 | ((int64_t)(a & 0x7fffffff) << 21));
3675
3676 f64 = recip_estimate (f64, env);
3677
3678 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3679}
3680
0ecb72a5 3681uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3682{
e07be5d2
CL		 3683 float64 f64;
3684
3685 if ((a & 0xc0000000) == 0) {
3686 return 0xffffffff;
3687 }
3688
3689 if (a & 0x80000000) {
3690 f64 = make_float64((0x3feULL << 52)
3691 | ((uint64_t)(a & 0x7fffffff) << 21));
3692 } else { /* bits 31-30 == '01' */
3693 f64 = make_float64((0x3fdULL << 52)
3694 | ((uint64_t)(a & 0x3fffffff) << 22));
3695 }
3696
3697 f64 = recip_sqrt_estimate(f64, env);
3698
3699 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3700}
fe1479c3 3701
da97f52c
PM		 3702/* VFPv4 fused multiply-accumulate */
3703float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3704{
3705 float_status *fpst = fpstp;
3706 return float32_muladd(a, b, c, 0, fpst);
3707}
3708
3709float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3710{
3711 float_status *fpst = fpstp;
3712 return float64_muladd(a, b, c, 0, fpst);
3713}
Qemu copy for testing