[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef ARM_LIB_H_\r
#define ARM_LIB_H_\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined (MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
  #error "Unknown chipset."\r
#endif\r
\r
#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \\r
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                     EFI_MEMORY_UCE)\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
\r
  // On some platforms, memory mapped flash region is designed as not supporting\r
  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
  // need.\r
  // Do NOT use below two attributes if you are not sure.\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr)  ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS            PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS             VirtualBase;\r
  UINT64                          Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES    Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(\r
  VOID\r
  );\r
typedef VOID (*LINE_OPERATION)(\r
  UINTN\r
  );\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK      (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD    (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC       (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT       (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM  (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK       (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15  (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0  0xFF\r
#define ARM_CORE_AFF1  (0xFF << 8)\r
#define ARM_CORE_AFF2  (0xFF << 16)\r
#define ARM_CORE_AFF3  (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK     ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK  ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)            ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)         (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)  (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID  (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
/** Reads the CCSIDR register for the specified cache.\r
\r
  @param CSSELR The CSSELR cache selection register value.\r
\r
  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
          Returns the contents of the CCSIDR register in AARCH32 mode.\r
**/\r
UINTN\r
ReadCCSIDR (\r
  IN UINT32  CSSELR\r
  );\r
\r
/** Reads the CCSIDR2 for the specified cache.\r
\r
  @param CSSELR The CSSELR cache selection register value\r
\r
  @return The contents of the CCSIDR2 register for the specified cache.\r
**/\r
UINT32\r
ReadCCSIDR2 (\r
  IN UINT32  CSSELR\r
  );\r
\r
/** Reads the Cache Level ID (CLIDR) register.\r
\r
  @return The contents of the CLIDR_EL1 register.\r
**/\r
UINT32\r
ReadCLIDR (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN  Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN  Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN  Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
  IN  UINTN  Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN  Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID  *TranslationTableEntry,\r
  IN  VOID  *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32  Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN  VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32  Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32  Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32  Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32  Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32  Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32  VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
  IN  UINT32  Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN  HypModeVectorBase\r
  );\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN  Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN  Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN  Bits\r
  );\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
#define ARM_ARCH_TIMER_ENABLE   (1 << 0)\r
#define ARM_ARCH_TIMER_IMASK    (1 << 1)\r
#define ARM_ARCH_TIMER_ISTATUS  (1 << 2)\r
\r
UINTN\r
EFIAPI\r
ArmReadCntFrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
  UINTN  FreqInHz\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntPct (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntkCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
  UINTN  Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
  UINTN  Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
  UINTN  Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
  UINTN  Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
  UINTN  Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCt (\r
  VOID\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntpCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
  UINT64  Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
  UINT64  Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvOff (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
  UINT64  Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetPhysicalAddressBits (\r
  VOID\r
  );\r
\r
///\r
///  ID Register Helper functions\r
///\r
\r
/**\r
  Check whether the CPU supports the GIC system register interface (any version)\r
\r
  @return   Whether GIC System Register Interface is supported\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasGicSystemRegisters (\r
  VOID\r
  );\r
\r
/** Checks if CCIDX is implemented.\r
\r
   @retval TRUE  CCIDX is implemented.\r
   @retval FALSE CCIDX is not implemented.\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasCcidx (\r
  VOID\r
  );\r
\r
#ifdef MDE_CPU_ARM\r
///\r
/// AArch32-only ID Register Helper functions\r
///\r
\r
/**\r
  Check whether the CPU supports the Security extensions\r
\r
  @return   Whether the Security extensions are implemented\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasSecurityExtensions (\r
  VOID\r
  );\r
\r
#endif // MDE_CPU_ARM\r
\r
#endif // ARM_LIB_H_\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
a63914d3	5	Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
1e57a462	6	\r
4059386c	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
1e57a462	8	\r
	9	**/\r
	10	\r
cc15a619 PG	11	#ifndef ARM_LIB_H_\r
cc15a619 PG	12	#define ARM_LIB_H_\r
1e57a462	13	\r
	14	#include <Uefi/UefiBaseType.h>\r
	15	\r
25402f5d	16	#ifdef MDE_CPU_ARM\r
70119d27	17	#include <Chipset/ArmV7.h>\r
429309e0	18	#elif defined (MDE_CPU_AARCH64)\r
25402f5d	19	#include <Chipset/AArch64.h>\r
1e57a462	20	#else\r
429309e0	21	#error "Unknown chipset."\r
1e57a462	22	#endif\r
1e57a462	23	\r
429309e0	24	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| EFI_MEMORY_WC \| \\r
e0307a7d AB	25	EFI_MEMORY_WT \| EFI_MEMORY_WB \| \\r
	26	EFI_MEMORY_UCE)\r
	27	\r
1e57a462	28	/**\r
	29	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	30	*\r
	31	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	32	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	33	*/\r
	34	typedef enum {\r
	35	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	36	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	37	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	38	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
829633e3 PL	39	\r
	40	// On some platforms, memory mapped flash region is designed as not supporting\r
	41	// shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
	42	// need.\r
	43	// Do NOT use below two attributes if you are not sure.\r
	44	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
	45	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
	46	\r
1e57a462	47	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	48	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	49	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	50	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	51	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	52	\r
429309e0	53	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
1e57a462	54	\r
1e57a462	55	typedef struct {\r
429309e0 MK	56	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	57	EFI_VIRTUAL_ADDRESS VirtualBase;\r
	58	UINT64 Length;\r
	59	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
1e57a462	60	} ARM_MEMORY_REGION_DESCRIPTOR;\r
1e57a462	61	\r
429309e0 MK	62	typedef VOID (*CACHE_OPERATION)(\r
	63	VOID\r
	64	);\r
	65	typedef VOID (*LINE_OPERATION)(\r
	66	UINTN\r
	67	);\r
1e57a462	68	\r
	69	//\r
	70	// ARM Processor Mode\r
	71	//\r
	72	typedef enum {\r
	73	ARM_PROCESSOR_MODE_USER = 0x10,\r
	74	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	75	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	76	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	77	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	78	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	79	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	80	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	81	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	82	} ARM_PROCESSOR_MODE;\r
	83	\r
	84	//\r
	85	// ARM Cpu IDs\r
	86	//\r
429309e0 MK	87	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	88	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	89	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	90	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	91	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	92	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	93	\r
	94	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	95	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	96	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	97	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	98	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	99	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
1e57a462	100	\r
	101	//\r
	102	// ARM MP Core IDs\r
	103	//\r
429309e0 MK	104	#define ARM_CORE_AFF0 0xFF\r
	105	#define ARM_CORE_AFF1 (0xFF << 8)\r
	106	#define ARM_CORE_AFF2 (0xFF << 16)\r
	107	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	108	\r
	109	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	110	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
	111	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
	112	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
	113	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
	114	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	115	\r
a63914d3 RC	116	/** Reads the CCSIDR register for the specified cache.\r
	117	\r
	118	@param CSSELR The CSSELR cache selection register value.\r
	119	\r
	120	@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
	121	Returns the contents of the CCSIDR register in AARCH32 mode.\r
	122	**/\r
	123	UINTN\r
	124	ReadCCSIDR (\r
429309e0	125	IN UINT32 CSSELR\r
a63914d3 RC	126	);\r
	127	\r
	128	/** Reads the CCSIDR2 for the specified cache.\r
	129	\r
	130	@param CSSELR The CSSELR cache selection register value\r
	131	\r
	132	@return The contents of the CCSIDR2 register for the specified cache.\r
	133	**/\r
	134	UINT32\r
	135	ReadCCSIDR2 (\r
429309e0	136	IN UINT32 CSSELR\r
a63914d3 RC	137	);\r
	138	\r
	139	/** Reads the Cache Level ID (CLIDR) register.\r
	140	\r
	141	@return The contents of the CLIDR_EL1 register.\r
	142	**/\r
	143	UINT32\r
	144	ReadCLIDR (\r
	145	VOID\r
	146	);\r
4f92cfa4	147	\r
1e57a462	148	UINTN\r
	149	EFIAPI\r
	150	ArmDataCacheLineLength (\r
	151	VOID\r
	152	);\r
3402aac7	153	\r
1e57a462	154	UINTN\r
	155	EFIAPI\r
	156	ArmInstructionCacheLineLength (\r
	157	VOID\r
	158	);\r
168d7245	159	\r
c653fc2a AB	160	UINTN\r
	161	EFIAPI\r
	162	ArmCacheWritebackGranule (\r
	163	VOID\r
	164	);\r
	165	\r
168d7245 OM	166	UINTN\r
	167	EFIAPI\r
	168	ArmIsArchTimerImplemented (\r
	169	VOID\r
	170	);\r
	171	\r
64751727	172	UINTN\r
1e57a462	173	EFIAPI\r
64751727	174	ArmCacheInfo (\r
1e57a462	175	VOID\r
	176	);\r
	177	\r
	178	BOOLEAN\r
	179	EFIAPI\r
	180	ArmIsMpCore (\r
	181	VOID\r
	182	);\r
	183	\r
	184	VOID\r
	185	EFIAPI\r
	186	ArmInvalidateDataCache (\r
	187	VOID\r
	188	);\r
	189	\r
1e57a462	190	VOID\r
	191	EFIAPI\r
	192	ArmCleanInvalidateDataCache (\r
	193	VOID\r
	194	);\r
	195	\r
	196	VOID\r
	197	EFIAPI\r
	198	ArmCleanDataCache (\r
	199	VOID\r
	200	);\r
	201	\r
1e57a462	202	VOID\r
	203	EFIAPI\r
	204	ArmInvalidateInstructionCache (\r
	205	VOID\r
	206	);\r
	207	\r
	208	VOID\r
	209	EFIAPI\r
	210	ArmInvalidateDataCacheEntryByMVA (\r
429309e0	211	IN UINTN Address\r
1e57a462	212	);\r
	213	\r
	214	VOID\r
	215	EFIAPI\r
cf580da1	216	ArmCleanDataCacheEntryToPoUByMVA (\r
429309e0	217	IN UINTN Address\r
1e57a462	218	);\r
1e57a462	219	\r
b7de7e3c EC	220	VOID\r
b7de7e3c EC	221	EFIAPI\r
cf580da1	222	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
429309e0	223	IN UINTN Address\r
cf580da1 AB	224	);\r
	225	\r
	226	VOID\r
	227	EFIAPI\r
	228	ArmCleanDataCacheEntryByMVA (\r
429309e0 MK	229	IN UINTN Address\r
429309e0 MK	230	);\r
b7de7e3c	231	\r
1e57a462	232	VOID\r
	233	EFIAPI\r
	234	ArmCleanInvalidateDataCacheEntryByMVA (\r
429309e0	235	IN UINTN Address\r
1e57a462	236	);\r
	237	\r
	238	VOID\r
	239	EFIAPI\r
	240	ArmEnableDataCache (\r
	241	VOID\r
	242	);\r
	243	\r
	244	VOID\r
	245	EFIAPI\r
	246	ArmDisableDataCache (\r
	247	VOID\r
	248	);\r
	249	\r
	250	VOID\r
	251	EFIAPI\r
	252	ArmEnableInstructionCache (\r
	253	VOID\r
	254	);\r
	255	\r
	256	VOID\r
	257	EFIAPI\r
	258	ArmDisableInstructionCache (\r
	259	VOID\r
	260	);\r
3402aac7	261	\r
1e57a462	262	VOID\r
	263	EFIAPI\r
	264	ArmEnableMmu (\r
	265	VOID\r
	266	);\r
	267	\r
	268	VOID\r
	269	EFIAPI\r
	270	ArmDisableMmu (\r
	271	VOID\r
	272	);\r
	273	\r
0ff0e414 OM	274	VOID\r
	275	EFIAPI\r
	276	ArmEnableCachesAndMmu (\r
	277	VOID\r
	278	);\r
	279	\r
1e57a462	280	VOID\r
	281	EFIAPI\r
	282	ArmDisableCachesAndMmu (\r
	283	VOID\r
	284	);\r
	285	\r
1e57a462	286	VOID\r
	287	EFIAPI\r
	288	ArmEnableInterrupts (\r
	289	VOID\r
	290	);\r
	291	\r
	292	UINTN\r
	293	EFIAPI\r
	294	ArmDisableInterrupts (\r
	295	VOID\r
	296	);\r
47585ed5	297	\r
1e57a462	298	BOOLEAN\r
	299	EFIAPI\r
	300	ArmGetInterruptState (\r
	301	VOID\r
	302	);\r
	303	\r
0ff0e414 OM	304	VOID\r
	305	EFIAPI\r
	306	ArmEnableAsynchronousAbort (\r
	307	VOID\r
	308	);\r
	309	\r
47585ed5	310	UINTN\r
47585ed5	311	EFIAPI\r
0ff0e414	312	ArmDisableAsynchronousAbort (\r
47585ed5	313	VOID\r
	314	);\r
	315	\r
	316	VOID\r
	317	EFIAPI\r
	318	ArmEnableIrq (\r
	319	VOID\r
	320	);\r
	321	\r
0ff0e414 OM	322	UINTN\r
	323	EFIAPI\r
	324	ArmDisableIrq (\r
	325	VOID\r
	326	);\r
	327	\r
1e57a462	328	VOID\r
	329	EFIAPI\r
	330	ArmEnableFiq (\r
	331	VOID\r
	332	);\r
	333	\r
	334	UINTN\r
	335	EFIAPI\r
	336	ArmDisableFiq (\r
	337	VOID\r
	338	);\r
3402aac7	339	\r
1e57a462	340	BOOLEAN\r
	341	EFIAPI\r
	342	ArmGetFiqState (\r
	343	VOID\r
	344	);\r
	345	\r
8dd618d2 OM	346	/**\r
	347	* Invalidate Data and Instruction TLBs\r
	348	*/\r
1e57a462	349	VOID\r
	350	EFIAPI\r
	351	ArmInvalidateTlb (\r
	352	VOID\r
	353	);\r
3402aac7	354	\r
1e57a462	355	VOID\r
	356	EFIAPI\r
	357	ArmUpdateTranslationTableEntry (\r
429309e0 MK	358	IN VOID *TranslationTableEntry,\r
429309e0 MK	359	IN VOID *Mva\r
1e57a462	360	);\r
3402aac7	361	\r
1e57a462	362	VOID\r
	363	EFIAPI\r
	364	ArmSetDomainAccessControl (\r
	365	IN UINT32 Domain\r
	366	);\r
	367	\r
	368	VOID\r
	369	EFIAPI\r
	370	ArmSetTTBR0 (\r
	371	IN VOID *TranslationTableBase\r
	372	);\r
	373	\r
ff1f27c0 EL	374	VOID\r
	375	EFIAPI\r
	376	ArmSetTTBCR (\r
429309e0	377	IN UINT32 Bits\r
ff1f27c0 EL	378	);\r
ff1f27c0 EL	379	\r
1e57a462	380	VOID *\r
	381	EFIAPI\r
	382	ArmGetTTBR0BaseAddress (\r
	383	VOID\r
	384	);\r
	385	\r
1e57a462	386	BOOLEAN\r
	387	EFIAPI\r
	388	ArmMmuEnabled (\r
	389	VOID\r
	390	);\r
3402aac7	391	\r
1e57a462	392	VOID\r
	393	EFIAPI\r
	394	ArmEnableBranchPrediction (\r
	395	VOID\r
	396	);\r
	397	\r
	398	VOID\r
	399	EFIAPI\r
	400	ArmDisableBranchPrediction (\r
	401	VOID\r
	402	);\r
	403	\r
	404	VOID\r
	405	EFIAPI\r
	406	ArmSetLowVectors (\r
	407	VOID\r
	408	);\r
	409	\r
	410	VOID\r
	411	EFIAPI\r
	412	ArmSetHighVectors (\r
	413	VOID\r
	414	);\r
	415	\r
	416	VOID\r
	417	EFIAPI\r
	418	ArmDataMemoryBarrier (\r
	419	VOID\r
	420	);\r
3402aac7	421	\r
1e57a462	422	VOID\r
1e57a462	423	EFIAPI\r
cf93a378	424	ArmDataSynchronizationBarrier (\r
1e57a462	425	VOID\r
1e57a462	426	);\r
3402aac7	427	\r
1e57a462	428	VOID\r
	429	EFIAPI\r
	430	ArmInstructionSynchronizationBarrier (\r
	431	VOID\r
	432	);\r
	433	\r
	434	VOID\r
	435	EFIAPI\r
	436	ArmWriteVBar (\r
429309e0	437	IN UINTN VectorBase\r
1e57a462	438	);\r
1e57a462	439	\r
4e57d6d7	440	UINTN\r
1e57a462	441	EFIAPI\r
	442	ArmReadVBar (\r
	443	VOID\r
	444	);\r
	445	\r
	446	VOID\r
	447	EFIAPI\r
	448	ArmWriteAuxCr (\r
429309e0	449	IN UINT32 Bit\r
1e57a462	450	);\r
	451	\r
	452	UINT32\r
	453	EFIAPI\r
	454	ArmReadAuxCr (\r
	455	VOID\r
	456	);\r
	457	\r
	458	VOID\r
	459	EFIAPI\r
	460	ArmSetAuxCrBit (\r
429309e0	461	IN UINT32 Bits\r
1e57a462	462	);\r
	463	\r
	464	VOID\r
	465	EFIAPI\r
	466	ArmUnsetAuxCrBit (\r
429309e0	467	IN UINT32 Bits\r
1e57a462	468	);\r
	469	\r
	470	VOID\r
	471	EFIAPI\r
	472	ArmCallSEV (\r
	473	VOID\r
	474	);\r
	475	\r
	476	VOID\r
	477	EFIAPI\r
	478	ArmCallWFE (\r
	479	VOID\r
	480	);\r
	481	\r
	482	VOID\r
	483	EFIAPI\r
	484	ArmCallWFI (\r
25402f5d	485	\r
1e57a462	486	VOID\r
	487	);\r
	488	\r
	489	UINTN\r
	490	EFIAPI\r
	491	ArmReadMpidr (\r
	492	VOID\r
	493	);\r
	494	\r
9401d6f4 OM	495	UINTN\r
	496	EFIAPI\r
	497	ArmReadMidr (\r
	498	VOID\r
	499	);\r
	500	\r
1e57a462	501	UINT32\r
	502	EFIAPI\r
	503	ArmReadCpacr (\r
	504	VOID\r
	505	);\r
	506	\r
	507	VOID\r
	508	EFIAPI\r
	509	ArmWriteCpacr (\r
429309e0	510	IN UINT32 Access\r
1e57a462	511	);\r
	512	\r
	513	VOID\r
	514	EFIAPI\r
	515	ArmEnableVFP (\r
	516	VOID\r
	517	);\r
	518	\r
46d4d75c OM	519	/**\r
	520	Get the Secure Configuration Register value\r
	521	\r
	522	@return Value read from the Secure Configuration Register\r
	523	\r
	524	**/\r
1e57a462	525	UINT32\r
	526	EFIAPI\r
	527	ArmReadScr (\r
	528	VOID\r
	529	);\r
	530	\r
46d4d75c OM	531	/**\r
	532	Set the Secure Configuration Register\r
	533	\r
	534	@param Value Value to write to the Secure Configuration Register\r
	535	\r
	536	**/\r
1e57a462	537	VOID\r
	538	EFIAPI\r
	539	ArmWriteScr (\r
429309e0	540	IN UINT32 Value\r
1e57a462	541	);\r
	542	\r
	543	UINT32\r
	544	EFIAPI\r
	545	ArmReadMVBar (\r
	546	VOID\r
	547	);\r
	548	\r
	549	VOID\r
	550	EFIAPI\r
	551	ArmWriteMVBar (\r
429309e0	552	IN UINT32 VectorMonitorBase\r
1e57a462	553	);\r
	554	\r
	555	UINT32\r
	556	EFIAPI\r
	557	ArmReadSctlr (\r
	558	VOID\r
	559	);\r
	560	\r
1e1d1697 MZ	561	VOID\r
	562	EFIAPI\r
	563	ArmWriteSctlr (\r
429309e0	564	IN UINT32 Value\r
1e1d1697 MZ	565	);\r
1e1d1697 MZ	566	\r
5ea2c2d3	567	UINTN\r
	568	EFIAPI\r
	569	ArmReadHVBar (\r
	570	VOID\r
	571	);\r
	572	\r
	573	VOID\r
	574	EFIAPI\r
	575	ArmWriteHVBar (\r
429309e0	576	IN UINTN HypModeVectorBase\r
5ea2c2d3	577	);\r
5ea2c2d3	578	\r
52d44f77 OM	579	//\r
	580	// Helper functions for accessing CPU ACTLR\r
	581	//\r
	582	\r
	583	UINTN\r
	584	EFIAPI\r
	585	ArmReadCpuActlr (\r
	586	VOID\r
	587	);\r
	588	\r
	589	VOID\r
	590	EFIAPI\r
	591	ArmWriteCpuActlr (\r
429309e0	592	IN UINTN Val\r
52d44f77 OM	593	);\r
	594	\r
	595	VOID\r
	596	EFIAPI\r
	597	ArmSetCpuActlrBit (\r
429309e0	598	IN UINTN Bits\r
52d44f77 OM	599	);\r
	600	\r
	601	VOID\r
	602	EFIAPI\r
	603	ArmUnsetCpuActlrBit (\r
429309e0	604	IN UINTN Bits\r
52d44f77 OM	605	);\r
52d44f77 OM	606	\r
734bd6cc AB	607	//\r
	608	// Accessors for the architected generic timer registers\r
	609	//\r
	610	\r
429309e0 MK	611	#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
	612	#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
	613	#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
734bd6cc AB	614	\r
	615	UINTN\r
	616	EFIAPI\r
	617	ArmReadCntFrq (\r
	618	VOID\r
	619	);\r
	620	\r
	621	VOID\r
	622	EFIAPI\r
	623	ArmWriteCntFrq (\r
429309e0	624	UINTN FreqInHz\r
734bd6cc AB	625	);\r
	626	\r
	627	UINT64\r
	628	EFIAPI\r
	629	ArmReadCntPct (\r
	630	VOID\r
	631	);\r
	632	\r
	633	UINTN\r
	634	EFIAPI\r
	635	ArmReadCntkCtl (\r
	636	VOID\r
	637	);\r
	638	\r
	639	VOID\r
	640	EFIAPI\r
	641	ArmWriteCntkCtl (\r
429309e0	642	UINTN Val\r
734bd6cc AB	643	);\r
	644	\r
	645	UINTN\r
	646	EFIAPI\r
	647	ArmReadCntpTval (\r
	648	VOID\r
	649	);\r
	650	\r
	651	VOID\r
	652	EFIAPI\r
	653	ArmWriteCntpTval (\r
429309e0	654	UINTN Val\r
734bd6cc AB	655	);\r
	656	\r
	657	UINTN\r
	658	EFIAPI\r
	659	ArmReadCntpCtl (\r
	660	VOID\r
	661	);\r
	662	\r
	663	VOID\r
	664	EFIAPI\r
	665	ArmWriteCntpCtl (\r
429309e0	666	UINTN Val\r
734bd6cc AB	667	);\r
	668	\r
	669	UINTN\r
	670	EFIAPI\r
	671	ArmReadCntvTval (\r
	672	VOID\r
	673	);\r
	674	\r
	675	VOID\r
	676	EFIAPI\r
	677	ArmWriteCntvTval (\r
429309e0	678	UINTN Val\r
734bd6cc AB	679	);\r
	680	\r
	681	UINTN\r
	682	EFIAPI\r
	683	ArmReadCntvCtl (\r
	684	VOID\r
	685	);\r
	686	\r
	687	VOID\r
	688	EFIAPI\r
	689	ArmWriteCntvCtl (\r
429309e0	690	UINTN Val\r
734bd6cc AB	691	);\r
	692	\r
	693	UINT64\r
	694	EFIAPI\r
	695	ArmReadCntvCt (\r
	696	VOID\r
	697	);\r
	698	\r
	699	UINT64\r
	700	EFIAPI\r
	701	ArmReadCntpCval (\r
	702	VOID\r
	703	);\r
	704	\r
	705	VOID\r
	706	EFIAPI\r
	707	ArmWriteCntpCval (\r
429309e0	708	UINT64 Val\r
734bd6cc AB	709	);\r
	710	\r
	711	UINT64\r
	712	EFIAPI\r
	713	ArmReadCntvCval (\r
	714	VOID\r
	715	);\r
	716	\r
	717	VOID\r
	718	EFIAPI\r
	719	ArmWriteCntvCval (\r
429309e0	720	UINT64 Val\r
734bd6cc AB	721	);\r
	722	\r
	723	UINT64\r
	724	EFIAPI\r
	725	ArmReadCntvOff (\r
	726	VOID\r
	727	);\r
	728	\r
	729	VOID\r
	730	EFIAPI\r
	731	ArmWriteCntvOff (\r
429309e0	732	UINT64 Val\r
734bd6cc AB	733	);\r
734bd6cc AB	734	\r
95d04ebc AB	735	UINTN\r
	736	EFIAPI\r
	737	ArmGetPhysicalAddressBits (\r
	738	VOID\r
	739	);\r
	740	\r
5cc25cff LL	741	///\r
	742	/// ID Register Helper functions\r
	743	///\r
	744	\r
	745	/**\r
	746	Check whether the CPU supports the GIC system register interface (any version)\r
	747	\r
	748	@return Whether GIC System Register Interface is supported\r
	749	\r
	750	**/\r
	751	BOOLEAN\r
	752	EFIAPI\r
	753	ArmHasGicSystemRegisters (\r
	754	VOID\r
	755	);\r
	756	\r
6e131aff RC	757	/** Checks if CCIDX is implemented.\r
	758	\r
	759	@retval TRUE CCIDX is implemented.\r
	760	@retval FALSE CCIDX is not implemented.\r
	761	**/\r
	762	BOOLEAN\r
	763	EFIAPI\r
	764	ArmHasCcidx (\r
	765	VOID\r
	766	);\r
	767	\r
740b870d LL	768	#ifdef MDE_CPU_ARM\r
	769	///\r
	770	/// AArch32-only ID Register Helper functions\r
	771	///\r
429309e0	772	\r
740b870d LL	773	/**\r
	774	Check whether the CPU supports the Security extensions\r
	775	\r
	776	@return Whether the Security extensions are implemented\r
	777	\r
	778	**/\r
	779	BOOLEAN\r
	780	EFIAPI\r
	781	ArmHasSecurityExtensions (\r
	782	VOID\r
	783	);\r
429309e0	784	\r
740b870d LL	785	#endif // MDE_CPU_ARM\r
740b870d LL	786	\r
cc15a619	787	#endif // ARM_LIB_H_\r