[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                     EFI_MEMORY_UCE)\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
\r
  // On some platforms, memory mapped flash region is designed as not supporting\r
  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
  // need.\r
  // Do NOT use below two attributes if you are not sure.\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
IN  UINTN   Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32 Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
  IN  UINT32   Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
\r
UINTN\r
EFIAPI\r
ArmReadCntFrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
  UINTN   FreqInHz\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntPct (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntkCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
  UINTN   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCt (\r
  VOID\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntpCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvOff (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
  UINT64   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetPhysicalAddressBits (\r
  VOID\r
  );\r
\r
\r
///\r
///  ID Register Helper functions\r
///\r
\r
/**\r
  Check whether the CPU supports the GIC system register interface (any version)\r
\r
  @return   Whether GIC System Register Interface is supported\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasGicSystemRegisters (\r
  VOID\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
5cc25cff	5	Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
1e57a462	6	\r
4059386c	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
1e57a462	8	\r
	9	**/\r
	10	\r
	11	#ifndef __ARM_LIB__\r
	12	#define __ARM_LIB__\r
	13	\r
	14	#include <Uefi/UefiBaseType.h>\r
	15	\r
25402f5d	16	#ifdef MDE_CPU_ARM\r
70119d27	17	#include <Chipset/ArmV7.h>\r
25402f5d HL	18	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	19	#include <Chipset/AArch64.h>\r
1e57a462	20	#else\r
25402f5d	21	#error "Unknown chipset."\r
1e57a462	22	#endif\r
1e57a462	23	\r
e0307a7d AB	24	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| EFI_MEMORY_WC \| \\r
	25	EFI_MEMORY_WT \| EFI_MEMORY_WB \| \\r
	26	EFI_MEMORY_UCE)\r
	27	\r
1e57a462	28	/**\r
	29	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	30	*\r
	31	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	32	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	33	*/\r
	34	typedef enum {\r
	35	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	36	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	37	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	38	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
829633e3 PL	39	\r
	40	// On some platforms, memory mapped flash region is designed as not supporting\r
	41	// shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
	42	// need.\r
	43	// Do NOT use below two attributes if you are not sure.\r
	44	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
	45	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
	46	\r
1e57a462	47	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	48	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	49	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	50	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	51	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	52	\r
	53	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	54	\r
	55	typedef struct {\r
	56	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	57	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	58	UINT64 Length;\r
1e57a462	59	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	60	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	61	\r
	62	typedef VOID (*CACHE_OPERATION)(VOID);\r
	63	typedef VOID (*LINE_OPERATION)(UINTN);\r
	64	\r
	65	//\r
	66	// ARM Processor Mode\r
	67	//\r
	68	typedef enum {\r
	69	ARM_PROCESSOR_MODE_USER = 0x10,\r
	70	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	71	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	72	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	73	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	74	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	75	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	76	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	77	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	78	} ARM_PROCESSOR_MODE;\r
	79	\r
	80	//\r
	81	// ARM Cpu IDs\r
	82	//\r
	83	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	84	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	85	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	86	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	87	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	88	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	89	\r
	90	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	91	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	92	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	93	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	94	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	95	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	96	\r
	97	//\r
	98	// ARM MP Core IDs\r
	99	//\r
90ed18ca OM	100	#define ARM_CORE_AFF0 0xFF\r
	101	#define ARM_CORE_AFF1 (0xFF << 8)\r
	102	#define ARM_CORE_AFF2 (0xFF << 16)\r
	103	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	104	\r
	105	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	106	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	107	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	108	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	109	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	110	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	111	\r
1e57a462	112	UINTN\r
	113	EFIAPI\r
	114	ArmDataCacheLineLength (\r
	115	VOID\r
	116	);\r
3402aac7	117	\r
1e57a462	118	UINTN\r
	119	EFIAPI\r
	120	ArmInstructionCacheLineLength (\r
	121	VOID\r
	122	);\r
168d7245	123	\r
c653fc2a AB	124	UINTN\r
	125	EFIAPI\r
	126	ArmCacheWritebackGranule (\r
	127	VOID\r
	128	);\r
	129	\r
168d7245 OM	130	UINTN\r
	131	EFIAPI\r
	132	ArmIsArchTimerImplemented (\r
	133	VOID\r
	134	);\r
	135	\r
	136	UINTN\r
	137	EFIAPI\r
	138	ArmReadIdPfr0 (\r
	139	VOID\r
	140	);\r
	141	\r
	142	UINTN\r
	143	EFIAPI\r
	144	ArmReadIdPfr1 (\r
	145	VOID\r
	146	);\r
	147	\r
64751727	148	UINTN\r
1e57a462	149	EFIAPI\r
64751727	150	ArmCacheInfo (\r
1e57a462	151	VOID\r
	152	);\r
	153	\r
	154	BOOLEAN\r
	155	EFIAPI\r
	156	ArmIsMpCore (\r
	157	VOID\r
	158	);\r
	159	\r
	160	VOID\r
	161	EFIAPI\r
	162	ArmInvalidateDataCache (\r
	163	VOID\r
	164	);\r
	165	\r
	166	\r
	167	VOID\r
	168	EFIAPI\r
	169	ArmCleanInvalidateDataCache (\r
	170	VOID\r
	171	);\r
	172	\r
	173	VOID\r
	174	EFIAPI\r
	175	ArmCleanDataCache (\r
	176	VOID\r
	177	);\r
	178	\r
1e57a462	179	VOID\r
	180	EFIAPI\r
	181	ArmInvalidateInstructionCache (\r
	182	VOID\r
	183	);\r
	184	\r
	185	VOID\r
	186	EFIAPI\r
	187	ArmInvalidateDataCacheEntryByMVA (\r
	188	IN UINTN Address\r
	189	);\r
	190	\r
	191	VOID\r
	192	EFIAPI\r
cf580da1	193	ArmCleanDataCacheEntryToPoUByMVA (\r
1e57a462	194	IN UINTN Address\r
	195	);\r
	196	\r
b7de7e3c EC	197	VOID\r
b7de7e3c EC	198	EFIAPI\r
cf580da1 AB	199	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
	200	IN UINTN Address\r
	201	);\r
	202	\r
	203	VOID\r
	204	EFIAPI\r
	205	ArmCleanDataCacheEntryByMVA (\r
b7de7e3c EC	206	IN UINTN Address\r
	207	);\r
	208	\r
1e57a462	209	VOID\r
	210	EFIAPI\r
	211	ArmCleanInvalidateDataCacheEntryByMVA (\r
	212	IN UINTN Address\r
	213	);\r
	214	\r
	215	VOID\r
	216	EFIAPI\r
	217	ArmEnableDataCache (\r
	218	VOID\r
	219	);\r
	220	\r
	221	VOID\r
	222	EFIAPI\r
	223	ArmDisableDataCache (\r
	224	VOID\r
	225	);\r
	226	\r
	227	VOID\r
	228	EFIAPI\r
	229	ArmEnableInstructionCache (\r
	230	VOID\r
	231	);\r
	232	\r
	233	VOID\r
	234	EFIAPI\r
	235	ArmDisableInstructionCache (\r
	236	VOID\r
	237	);\r
3402aac7	238	\r
1e57a462	239	VOID\r
	240	EFIAPI\r
	241	ArmEnableMmu (\r
	242	VOID\r
	243	);\r
	244	\r
	245	VOID\r
	246	EFIAPI\r
	247	ArmDisableMmu (\r
	248	VOID\r
	249	);\r
	250	\r
0ff0e414 OM	251	VOID\r
	252	EFIAPI\r
	253	ArmEnableCachesAndMmu (\r
	254	VOID\r
	255	);\r
	256	\r
1e57a462	257	VOID\r
	258	EFIAPI\r
	259	ArmDisableCachesAndMmu (\r
	260	VOID\r
	261	);\r
	262	\r
1e57a462	263	VOID\r
	264	EFIAPI\r
	265	ArmEnableInterrupts (\r
	266	VOID\r
	267	);\r
	268	\r
	269	UINTN\r
	270	EFIAPI\r
	271	ArmDisableInterrupts (\r
	272	VOID\r
	273	);\r
47585ed5	274	\r
1e57a462	275	BOOLEAN\r
	276	EFIAPI\r
	277	ArmGetInterruptState (\r
	278	VOID\r
	279	);\r
	280	\r
0ff0e414 OM	281	VOID\r
	282	EFIAPI\r
	283	ArmEnableAsynchronousAbort (\r
	284	VOID\r
	285	);\r
	286	\r
47585ed5	287	UINTN\r
47585ed5	288	EFIAPI\r
0ff0e414	289	ArmDisableAsynchronousAbort (\r
47585ed5	290	VOID\r
	291	);\r
	292	\r
	293	VOID\r
	294	EFIAPI\r
	295	ArmEnableIrq (\r
	296	VOID\r
	297	);\r
	298	\r
0ff0e414 OM	299	UINTN\r
	300	EFIAPI\r
	301	ArmDisableIrq (\r
	302	VOID\r
	303	);\r
	304	\r
1e57a462	305	VOID\r
	306	EFIAPI\r
	307	ArmEnableFiq (\r
	308	VOID\r
	309	);\r
	310	\r
	311	UINTN\r
	312	EFIAPI\r
	313	ArmDisableFiq (\r
	314	VOID\r
	315	);\r
3402aac7	316	\r
1e57a462	317	BOOLEAN\r
	318	EFIAPI\r
	319	ArmGetFiqState (\r
	320	VOID\r
	321	);\r
	322	\r
8dd618d2 OM	323	/**\r
	324	* Invalidate Data and Instruction TLBs\r
	325	*/\r
1e57a462	326	VOID\r
	327	EFIAPI\r
	328	ArmInvalidateTlb (\r
	329	VOID\r
	330	);\r
3402aac7	331	\r
1e57a462	332	VOID\r
	333	EFIAPI\r
	334	ArmUpdateTranslationTableEntry (\r
	335	IN VOID *TranslationTableEntry,\r
	336	IN VOID *Mva\r
	337	);\r
3402aac7	338	\r
1e57a462	339	VOID\r
	340	EFIAPI\r
	341	ArmSetDomainAccessControl (\r
	342	IN UINT32 Domain\r
	343	);\r
	344	\r
	345	VOID\r
	346	EFIAPI\r
	347	ArmSetTTBR0 (\r
	348	IN VOID *TranslationTableBase\r
	349	);\r
	350	\r
ff1f27c0 EL	351	VOID\r
	352	EFIAPI\r
	353	ArmSetTTBCR (\r
	354	IN UINT32 Bits\r
	355	);\r
	356	\r
1e57a462	357	VOID *\r
	358	EFIAPI\r
	359	ArmGetTTBR0BaseAddress (\r
	360	VOID\r
	361	);\r
	362	\r
1e57a462	363	BOOLEAN\r
	364	EFIAPI\r
	365	ArmMmuEnabled (\r
	366	VOID\r
	367	);\r
3402aac7	368	\r
1e57a462	369	VOID\r
	370	EFIAPI\r
	371	ArmEnableBranchPrediction (\r
	372	VOID\r
	373	);\r
	374	\r
	375	VOID\r
	376	EFIAPI\r
	377	ArmDisableBranchPrediction (\r
	378	VOID\r
	379	);\r
	380	\r
	381	VOID\r
	382	EFIAPI\r
	383	ArmSetLowVectors (\r
	384	VOID\r
	385	);\r
	386	\r
	387	VOID\r
	388	EFIAPI\r
	389	ArmSetHighVectors (\r
	390	VOID\r
	391	);\r
	392	\r
	393	VOID\r
	394	EFIAPI\r
	395	ArmDataMemoryBarrier (\r
	396	VOID\r
	397	);\r
3402aac7	398	\r
1e57a462	399	VOID\r
1e57a462	400	EFIAPI\r
cf93a378	401	ArmDataSynchronizationBarrier (\r
1e57a462	402	VOID\r
1e57a462	403	);\r
3402aac7	404	\r
1e57a462	405	VOID\r
	406	EFIAPI\r
	407	ArmInstructionSynchronizationBarrier (\r
	408	VOID\r
	409	);\r
	410	\r
	411	VOID\r
	412	EFIAPI\r
	413	ArmWriteVBar (\r
4e57d6d7	414	IN UINTN VectorBase\r
1e57a462	415	);\r
1e57a462	416	\r
4e57d6d7	417	UINTN\r
1e57a462	418	EFIAPI\r
	419	ArmReadVBar (\r
	420	VOID\r
	421	);\r
	422	\r
	423	VOID\r
	424	EFIAPI\r
	425	ArmWriteAuxCr (\r
	426	IN UINT32 Bit\r
	427	);\r
	428	\r
	429	UINT32\r
	430	EFIAPI\r
	431	ArmReadAuxCr (\r
	432	VOID\r
	433	);\r
	434	\r
	435	VOID\r
	436	EFIAPI\r
	437	ArmSetAuxCrBit (\r
	438	IN UINT32 Bits\r
	439	);\r
	440	\r
	441	VOID\r
	442	EFIAPI\r
	443	ArmUnsetAuxCrBit (\r
	444	IN UINT32 Bits\r
	445	);\r
	446	\r
	447	VOID\r
	448	EFIAPI\r
	449	ArmCallSEV (\r
	450	VOID\r
	451	);\r
	452	\r
	453	VOID\r
	454	EFIAPI\r
	455	ArmCallWFE (\r
	456	VOID\r
	457	);\r
	458	\r
	459	VOID\r
	460	EFIAPI\r
	461	ArmCallWFI (\r
25402f5d	462	\r
1e57a462	463	VOID\r
	464	);\r
	465	\r
	466	UINTN\r
	467	EFIAPI\r
	468	ArmReadMpidr (\r
	469	VOID\r
	470	);\r
	471	\r
9401d6f4 OM	472	UINTN\r
	473	EFIAPI\r
	474	ArmReadMidr (\r
	475	VOID\r
	476	);\r
	477	\r
1e57a462	478	UINT32\r
	479	EFIAPI\r
	480	ArmReadCpacr (\r
	481	VOID\r
	482	);\r
	483	\r
	484	VOID\r
	485	EFIAPI\r
	486	ArmWriteCpacr (\r
	487	IN UINT32 Access\r
	488	);\r
	489	\r
	490	VOID\r
	491	EFIAPI\r
	492	ArmEnableVFP (\r
	493	VOID\r
	494	);\r
	495	\r
46d4d75c OM	496	/**\r
	497	Get the Secure Configuration Register value\r
	498	\r
	499	@return Value read from the Secure Configuration Register\r
	500	\r
	501	**/\r
1e57a462	502	UINT32\r
	503	EFIAPI\r
	504	ArmReadScr (\r
	505	VOID\r
	506	);\r
	507	\r
46d4d75c OM	508	/**\r
	509	Set the Secure Configuration Register\r
	510	\r
	511	@param Value Value to write to the Secure Configuration Register\r
	512	\r
	513	**/\r
1e57a462	514	VOID\r
	515	EFIAPI\r
	516	ArmWriteScr (\r
46d4d75c	517	IN UINT32 Value\r
1e57a462	518	);\r
	519	\r
	520	UINT32\r
	521	EFIAPI\r
	522	ArmReadMVBar (\r
	523	VOID\r
	524	);\r
	525	\r
	526	VOID\r
	527	EFIAPI\r
	528	ArmWriteMVBar (\r
	529	IN UINT32 VectorMonitorBase\r
	530	);\r
	531	\r
	532	UINT32\r
	533	EFIAPI\r
	534	ArmReadSctlr (\r
	535	VOID\r
	536	);\r
	537	\r
1e1d1697 MZ	538	VOID\r
	539	EFIAPI\r
	540	ArmWriteSctlr (\r
	541	IN UINT32 Value\r
	542	);\r
	543	\r
5ea2c2d3	544	UINTN\r
	545	EFIAPI\r
	546	ArmReadHVBar (\r
	547	VOID\r
	548	);\r
	549	\r
	550	VOID\r
	551	EFIAPI\r
	552	ArmWriteHVBar (\r
	553	IN UINTN HypModeVectorBase\r
	554	);\r
	555	\r
52d44f77 OM	556	\r
	557	//\r
	558	// Helper functions for accessing CPU ACTLR\r
	559	//\r
	560	\r
	561	UINTN\r
	562	EFIAPI\r
	563	ArmReadCpuActlr (\r
	564	VOID\r
	565	);\r
	566	\r
	567	VOID\r
	568	EFIAPI\r
	569	ArmWriteCpuActlr (\r
	570	IN UINTN Val\r
	571	);\r
	572	\r
	573	VOID\r
	574	EFIAPI\r
	575	ArmSetCpuActlrBit (\r
	576	IN UINTN Bits\r
	577	);\r
	578	\r
	579	VOID\r
	580	EFIAPI\r
	581	ArmUnsetCpuActlrBit (\r
	582	IN UINTN Bits\r
	583	);\r
	584	\r
734bd6cc AB	585	//\r
	586	// Accessors for the architected generic timer registers\r
	587	//\r
	588	\r
	589	#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
	590	#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
	591	#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
	592	\r
	593	UINTN\r
	594	EFIAPI\r
	595	ArmReadCntFrq (\r
	596	VOID\r
	597	);\r
	598	\r
	599	VOID\r
	600	EFIAPI\r
	601	ArmWriteCntFrq (\r
	602	UINTN FreqInHz\r
	603	);\r
	604	\r
	605	UINT64\r
	606	EFIAPI\r
	607	ArmReadCntPct (\r
	608	VOID\r
	609	);\r
	610	\r
	611	UINTN\r
	612	EFIAPI\r
	613	ArmReadCntkCtl (\r
	614	VOID\r
	615	);\r
	616	\r
	617	VOID\r
	618	EFIAPI\r
	619	ArmWriteCntkCtl (\r
	620	UINTN Val\r
	621	);\r
	622	\r
	623	UINTN\r
	624	EFIAPI\r
	625	ArmReadCntpTval (\r
	626	VOID\r
	627	);\r
	628	\r
	629	VOID\r
	630	EFIAPI\r
	631	ArmWriteCntpTval (\r
	632	UINTN Val\r
	633	);\r
	634	\r
	635	UINTN\r
	636	EFIAPI\r
	637	ArmReadCntpCtl (\r
	638	VOID\r
	639	);\r
	640	\r
	641	VOID\r
	642	EFIAPI\r
	643	ArmWriteCntpCtl (\r
	644	UINTN Val\r
	645	);\r
	646	\r
	647	UINTN\r
	648	EFIAPI\r
649	ArmReadCntvTval (\r
650	VOID\r
651	);\r
652	\r
653	VOID\r
654	EFIAPI\r
655	ArmWriteCntvTval (\r
656	UINTN Val\r
657	);\r
658	\r
659	UINTN\r
660	EFIAPI\r
661	ArmReadCntvCtl (\r
662	VOID\r
663	);\r
664	\r
665	VOID\r
666	EFIAPI\r
667	ArmWriteCntvCtl (\r
668	UINTN Val\r
669	);\r
670	\r
671	UINT64\r
672	EFIAPI\r
673	ArmReadCntvCt (\r
674	VOID\r
675	);\r
676	\r
677	UINT64\r
678	EFIAPI\r
679	ArmReadCntpCval (\r
680	VOID\r
681	);\r
682	\r
683	VOID\r
684	EFIAPI\r
685	ArmWriteCntpCval (\r
686	UINT64 Val\r
687	);\r
688	\r
689	UINT64\r
690	EFIAPI\r
691	ArmReadCntvCval (\r
692	VOID\r
693	);\r
694	\r
695	VOID\r
696	EFIAPI\r
697	ArmWriteCntvCval (\r
698	UINT64 Val\r
699	);\r
700	\r
701	UINT64\r
702	EFIAPI\r
703	ArmReadCntvOff (\r
704	VOID\r
705	);\r
706	\r
707	VOID\r
708	EFIAPI\r
709	ArmWriteCntvOff (\r
710	UINT64 Val\r
711	);\r
712	\r
95d04ebc AB	713	UINTN\r
	714	EFIAPI\r
	715	ArmGetPhysicalAddressBits (\r
	716	VOID\r
	717	);\r
	718	\r
5cc25cff LL	719	\r
	720	///\r
	721	/// ID Register Helper functions\r
	722	///\r
	723	\r
	724	/**\r
	725	Check whether the CPU supports the GIC system register interface (any version)\r
	726	\r
	727	@return Whether GIC System Register Interface is supported\r
	728	\r
	729	**/\r
	730	BOOLEAN\r
	731	EFIAPI\r
	732	ArmHasGicSystemRegisters (\r
	733	VOID\r
	734	);\r
	735	\r
1e57a462	736	#endif // __ARM_LIB__\r