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aspeed: Use the boot_rom region of the fby35 machine
[mirror_qemu.git] / hw / arm / aspeed.c
CommitLineData
327d8e4e
AJ		 1/*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12#include "qemu/osdep.h"
da34e65c 13#include "qapi/error.h"
12ec8bd5 14#include "hw/arm/boot.h"
fca9ca1b 15#include "hw/arm/aspeed.h"
00442402 16#include "hw/arm/aspeed_soc.h"
c0216b94 17#include "hw/arm/aspeed_eeprom.h"
3ec75e39 18#include "hw/i2c/i2c_mux_pca954x.h"
93198b6c 19#include "hw/i2c/smbus_eeprom.h"
044475f3 20#include "hw/misc/pca9552.h"
9618ebae 21#include "hw/nvram/eeprom_at24c.h"
5e9ae4b1 22#include "hw/sensor/tmp105.h"
7cfbde5e 23#include "hw/misc/led.h"
a27bd6c7 24#include "hw/qdev-properties.h"
e1ad9bc4 25#include "sysemu/block-backend.h"
fa699e80 26#include "sysemu/reset.h"
d769a1da
CLG		 27#include "hw/loader.h"
28#include "qemu/error-report.h"
a9df9622 29#include "qemu/units.h"
66c895b8 30#include "hw/qdev-clock.h"
d2b3eaef 31#include "sysemu/sysemu.h"
327d8e4e 32
74fb1f38 33static struct arm_boot_info aspeed_board_binfo = {
b033271f 34 .board_id = -1, /* device-tree-only board */
327d8e4e
AJ		 35};
36
612b219a 37struct AspeedMachineState {
888b2b03
PMD		 38 /* Private */
39 MachineState parent_obj;
40 /* Public */
41
ff90606f 42 AspeedSoCState soc;
262259ea 43 MemoryRegion boot_rom;
888b2b03 44 bool mmio_exec;
9820e52f
CLG		 45 char *fmc_model;
46 char *spi_model;
ea066d39 47};
327d8e4e 48
ef17f836 49/* Palmetto hardware value: 0x120CE416 */
8da33ef7
CLG		 50#define PALMETTO_BMC_HW_STRAP1 ( \
51 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
52 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
53 SCU_AST2400_HW_STRAP_ACPI_DIS | \
54 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
55 SCU_HW_STRAP_VGA_CLASS_CODE | \
56 SCU_HW_STRAP_LPC_RESET_PIN | \
57 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
58 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
59 SCU_HW_STRAP_SPI_WIDTH | \
60 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
61 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
62
40a38df5
ES		 63/* TODO: Find the actual hardware value */
64#define SUPERMICROX11_BMC_HW_STRAP1 ( \
65 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
66 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
67 SCU_AST2400_HW_STRAP_ACPI_DIS | \
68 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
69 SCU_HW_STRAP_VGA_CLASS_CODE | \
70 SCU_HW_STRAP_LPC_RESET_PIN | \
71 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
72 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
73 SCU_HW_STRAP_SPI_WIDTH | \
74 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
75 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
76
47936597
GR		 77/* TODO: Find the actual hardware value */
78#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
79 AST2500_HW_STRAP1_DEFAULTS | \
80 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
81 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
82 SCU_AST2500_HW_STRAP_UART_DEBUG | \
83 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
84 SCU_HW_STRAP_SPI_WIDTH | \
85 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
86
ef17f836 87/* AST2500 evb hardware value: 0xF100C2E6 */
9a7c1750
CLG		 88#define AST2500_EVB_HW_STRAP1 (( \
89 AST2500_HW_STRAP1_DEFAULTS | \
90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
92 SCU_AST2500_HW_STRAP_UART_DEBUG | \
93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
94 SCU_HW_STRAP_MAC1_RGMII | \
95 SCU_HW_STRAP_MAC0_RGMII) & \
96 ~SCU_HW_STRAP_2ND_BOOT_WDT)
97
ef17f836
CLG		 98/* Romulus hardware value: 0xF10AD206 */
99#define ROMULUS_BMC_HW_STRAP1 ( \
100 AST2500_HW_STRAP1_DEFAULTS | \
101 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
102 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
103 SCU_AST2500_HW_STRAP_UART_DEBUG | \
104 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
105 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
106 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
107
143b040f
PW		 108/* Sonorapass hardware value: 0xF100D216 */
109#define SONORAPASS_BMC_HW_STRAP1 ( \
110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
112 SCU_AST2500_HW_STRAP_UART_DEBUG | \
113 SCU_AST2500_HW_STRAP_RESERVED28 | \
114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
115 SCU_HW_STRAP_VGA_CLASS_CODE | \
116 SCU_HW_STRAP_LPC_RESET_PIN | \
117 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
118 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
119 SCU_HW_STRAP_VGA_BIOS_ROM | \
120 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
121 SCU_AST2500_HW_STRAP_RESERVED1)
122
95f068c8
JW		 123#define G220A_BMC_HW_STRAP1 ( \
124 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
125 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
126 SCU_AST2500_HW_STRAP_UART_DEBUG | \
127 SCU_AST2500_HW_STRAP_RESERVED28 | \
128 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
129 SCU_HW_STRAP_2ND_BOOT_WDT | \
130 SCU_HW_STRAP_VGA_CLASS_CODE | \
131 SCU_HW_STRAP_LPC_RESET_PIN | \
132 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
133 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
134 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
135 SCU_AST2500_HW_STRAP_RESERVED1)
136
82b6a3f6
JW		 137/* FP5280G2 hardware value: 0XF100D286 */
138#define FP5280G2_BMC_HW_STRAP1 ( \
139 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
140 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
141 SCU_AST2500_HW_STRAP_UART_DEBUG | \
142 SCU_AST2500_HW_STRAP_RESERVED28 | \
143 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
144 SCU_HW_STRAP_VGA_CLASS_CODE | \
145 SCU_HW_STRAP_LPC_RESET_PIN | \
146 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
147 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
148 SCU_HW_STRAP_MAC1_RGMII | \
149 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
150 SCU_AST2500_HW_STRAP_RESERVED1)
151
62c2c2eb
CLG		 152/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
153#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
154
9cccb912
PV		 155/* Quanta-Q71l hardware value */
156#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
157 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
158 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
159 SCU_AST2400_HW_STRAP_ACPI_DIS | \
160 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
161 SCU_HW_STRAP_VGA_CLASS_CODE | \
162 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
163 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
164 SCU_HW_STRAP_SPI_WIDTH | \
165 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
166 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
167
ccc2c418
CLG		 168/* AST2600 evb hardware value */
169#define AST2600_EVB_HW_STRAP1 0x000000C0
170#define AST2600_EVB_HW_STRAP2 0x00000003
171
63ceb818
CLG		 172/* Tacoma hardware value */
173#define TACOMA_BMC_HW_STRAP1 0x00000000
7582591a 174#define TACOMA_BMC_HW_STRAP2 0x00000040
63ceb818 175
58e52bdb 176/* Rainier hardware value: (QEMU prototype) */
b6d1df64
JS		 177#define RAINIER_BMC_HW_STRAP1 0x00422016
178#define RAINIER_BMC_HW_STRAP2 0x80000848
58e52bdb 179
febbe308
PD		 180/* Fuji hardware value */
181#define FUJI_BMC_HW_STRAP1 0x00000000
182#define FUJI_BMC_HW_STRAP2 0x00000000
183
a20c54b1
PW		 184/* Bletchley hardware value */
185/* TODO: Leave same as EVB for now. */
186#define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
187#define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
188
fb6b3c8d
JHY		 189/* Qualcomm DC-SCM hardware value */
190#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
191#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
192
9bb6d140
JS		 193#define AST_SMP_MAILBOX_BASE 0x1e6e2180
194#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
195#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
196#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
197#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
198#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
199#define AST_SMP_MBOX_GOSIGN 0xabbaab00
200
201static void aspeed_write_smpboot(ARMCPU *cpu,
202 const struct arm_boot_info *info)
203{
902bba54
CLG		 204 AddressSpace *as = arm_boot_address_space(cpu, info);
205 static const ARMInsnFixup poll_mailbox_ready[] = {
9bb6d140
JS		 206 /*
207 * r2 = per-cpu go sign value
208 * r1 = AST_SMP_MBOX_FIELD_ENTRY
209 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
210 */
902bba54
CLG		 211 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
212 { 0xe21000ff }, /* ands r0, r0, #255 */
213 { 0xe59f201c }, /* ldr r2, [pc, #28] */
214 { 0xe1822000 }, /* orr r2, r2, r0 */
215
216 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
217 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
218
219 { 0xe320f002 }, /* wfe */
220 { 0xe5904000 }, /* ldr r4, [r0] */
221 { 0xe1520004 }, /* cmp r2, r4 */
222 { 0x1afffffb }, /* bne <wfe> */
223 { 0xe591f000 }, /* ldr pc, [r1] */
224 { AST_SMP_MBOX_GOSIGN },
225 { AST_SMP_MBOX_FIELD_ENTRY },
226 { AST_SMP_MBOX_FIELD_GOSIGN },
227 { 0, FIXUP_TERMINATOR }
9bb6d140 228 };
902bba54 229 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
9bb6d140 230
902bba54
CLG		 231 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
232 poll_mailbox_ready, fixupcontext);
9bb6d140
JS		 233}
234
235static void aspeed_reset_secondary(ARMCPU *cpu,
236 const struct arm_boot_info *info)
237{
238 AddressSpace *as = arm_boot_address_space(cpu, info);
239 CPUState *cs = CPU(cpu);
240
241 /* info->smp_bootreg_addr */
242 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
243 MEMTXATTRS_UNSPECIFIED, NULL);
244 cpu_set_pc(cs, info->smp_loader_start);
245}
246
8b744a6a 247static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
d769a1da
CLG		 248 Error **errp)
249{
05e6e40a 250 g_autofree void *storage = NULL;
0c7209be
CLG		 251 int64_t size;
252
253 /* The block backend size should have already been 'validated' by
254 * the creation of the m25p80 object.
255 */
256 size = blk_getlength(blk);
257 if (size <= 0) {
258 error_setg(errp, "failed to get flash size");
259 return;
260 }
d769a1da 261
0c7209be
CLG		 262 if (rom_size > size) {
263 rom_size = size;
d769a1da
CLG		 264 }
265
05e6e40a 266 storage = g_malloc0(rom_size);
a9262f55 267 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
d769a1da
CLG		 268 error_setg(errp, "failed to read the initial flash content");
269 return;
270 }
271
272 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
d769a1da
CLG		 273}
274
8b744a6a
CLG		 275/*
276 * Create a ROM and copy the flash contents at the expected address
277 * (0x0). Boots faster than execute-in-place.
278 */
262259ea 279static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
8b744a6a
CLG		 280 uint64_t rom_size)
281{
262259ea 282 AspeedSoCState *soc = &bmc->soc;
8b744a6a 283
262259ea 284 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
8b744a6a
CLG		 285 &error_abort);
286 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
262259ea 287 &bmc->boot_rom, 1);
8b744a6a
CLG		 288 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
289}
290
1099ad10 291void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
9bd4ac61 292 unsigned int count, int unit0)
e1ad9bc4 293{
179b2058
PW		 294 int i;
295
296 if (!flashtype) {
297 return;
298 }
e1ad9bc4 299
9bd4ac61 300 for (i = 0; i < count; ++i) {
8ec239f2 301 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
e1ad9bc4 302 qemu_irq cs_line;
a7d78bef 303 DeviceState *dev;
e1ad9bc4 304
a7d78bef 305 dev = qdev_new(flashtype);
e1ad9bc4 306 if (dinfo) {
a7d78bef 307 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
e1ad9bc4 308 }
a7d78bef 309 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
e1ad9bc4 310
a7d78bef 311 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
b22a2d40 312 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
e1ad9bc4
CLG		 313 }
314}
315
a29e3e12
AJ		 316static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
317{
318 DeviceState *card;
319
756f739b
PMD		 320 if (!dinfo) {
321 return;
a29e3e12 322 }
756f739b
PMD		 323 card = qdev_new(TYPE_SD_CARD);
324 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
325 &error_fatal);
3e80f690
MA		 326 qdev_realize_and_unref(card,
327 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
328 &error_fatal);
a29e3e12
AJ		 329}
330
d2b3eaef
PD		 331static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
332{
333 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
334 AspeedSoCState *s = &bmc->soc;
335 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
336
337 aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
338 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
339 if (uart == amc->uart_default) {
340 continue;
341 }
342 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
343 }
344}
345
baa4732b 346static void aspeed_machine_init(MachineState *machine)
327d8e4e 347{
888b2b03 348 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
baa4732b 349 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
b033271f 350 AspeedSoCClass *sc;
2bea128c 351 int i;
d3bad7e7 352 NICInfo *nd = &nd_table[0];
327d8e4e 353
9fc7fc4d 354 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
327d8e4e 355
b033271f
CLG		 356 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
357
533eb415 358 /*
346160cb
CLG		 359 * This will error out if the RAM size is not supported by the
360 * memory controller of the SoC.
533eb415 361 */
6e504a98 362 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
533eb415
IM		 363 &error_fatal);
364
d3bad7e7
CLG		 365 for (i = 0; i < sc->macs_num; i++) {
366 if ((amc->macs_mask & (1 << i)) && nd->used) {
367 qemu_check_nic_model(nd, TYPE_FTGMAC100);
368 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
369 nd++;
370 }
371 }
372
5325cc34 373 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
87e79af0 374 &error_abort);
5325cc34 375 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
ccc2c418 376 &error_abort);
4dd9d554
PD		 377 object_property_set_link(OBJECT(&bmc->soc), "memory",
378 OBJECT(get_system_memory()), &error_abort);
5325cc34 379 object_property_set_link(OBJECT(&bmc->soc), "dram",
0df2d9a6 380 OBJECT(machine->ram), &error_abort);
b6e70d1d
JS		 381 if (machine->kernel_filename) {
382 /*
383 * When booting with a -kernel command line there is no u-boot
384 * that runs to unlock the SCU. In this case set the default to
385 * be unlocked as the kernel expects
386 */
5325cc34
MA		 387 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
388 ASPEED_SCU_PROT_KEY, &error_abort);
b6e70d1d 389 }
d2b3eaef 390 connect_serial_hds_to_uarts(bmc);
ce189ab2 391 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
327d8e4e 392
8ec239f2
MA		 393 aspeed_board_init_flashes(&bmc->soc.fmc,
394 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
9bd4ac61 395 amc->num_cs, 0);
8ec239f2
MA		 396 aspeed_board_init_flashes(&bmc->soc.spi[0],
397 bmc->spi_model ? bmc->spi_model : amc->spi_model,
9bd4ac61 398 1, amc->num_cs);
74fb1f38 399
b7f1a0cb 400 if (machine->kernel_filename && sc->num_cpus > 1) {
9bb6d140
JS		 401 /* With no u-boot we must set up a boot stub for the secondary CPU */
402 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
f489960d 403 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
9bb6d140
JS		 404 0x80, &error_abort);
405 memory_region_add_subregion(get_system_memory(),
406 AST_SMP_MAILBOX_BASE, smpboot);
407
408 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
409 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
410 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
411 }
412
6e504a98 413 aspeed_board_binfo.ram_size = machine->ram_size;
347df6f8 414 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
e1ad9bc4 415
baa4732b
CLG		 416 if (amc->i2c_init) {
417 amc->i2c_init(bmc);
2cf6cb50
CLG		 418 }
419
0e2c24c6 420 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
8ec239f2
MA		 421 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
422 drive_get(IF_SD, 0, i));
a29e3e12 423 }
2bea128c 424
a29e3e12 425 if (bmc->soc.emmc.num_slots) {
8ec239f2
MA		 426 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
427 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
2bea128c
EJ		 428 }
429
8b744a6a
CLG		 430 if (!bmc->mmio_exec) {
431 DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
432
433 if (mtd0) {
434 uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
262259ea 435 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size);
8b744a6a
CLG		 436 }
437 }
438
2744ece8 439 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
74fb1f38 440}
b033271f 441
612b219a 442static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
2cf6cb50
CLG		 443{
444 AspeedSoCState *soc = &bmc->soc;
a87e81b9 445 DeviceState *dev;
3d165f12 446 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
2cf6cb50
CLG		 447
448 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
449 * enough to provide basic RTC features. Alarms will be missing */
1373b15b 450 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
a87e81b9 451
7a204cbd 452 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
3d165f12
CLG		 453 eeprom_buf);
454
a87e81b9 455 /* add a TMP423 temperature sensor */
1373b15b
PMD		 456 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
457 "tmp423", 0x4c));
5325cc34
MA		 458 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
459 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
460 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
461 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
2cf6cb50
CLG		 462}
463
9cccb912
PV		 464static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
465{
466 AspeedSoCState *soc = &bmc->soc;
467
468 /*
469 * The quanta-q71l platform expects tmp75s which are compatible with
470 * tmp105s.
471 */
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
475
476 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
477 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
478 /* TODO: Add Memory Riser i2c mux and eeproms. */
479
3ec75e39
PV		 480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
482
9cccb912 483 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
3ec75e39
PV		 484
485 /* i2c-7 */
486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
9cccb912
PV		 487 /* - i2c@0: pmbus@59 */
488 /* - i2c@1: pmbus@58 */
489 /* - i2c@2: pmbus@58 */
490 /* - i2c@3: pmbus@59 */
3ec75e39 491
9cccb912
PV		 492 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
493 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
494}
495
612b219a 496static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
2cf6cb50
CLG		 497{
498 AspeedSoCState *soc = &bmc->soc;
3d165f12
CLG		 499 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
500
7a204cbd 501 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
3d165f12 502 eeprom_buf);
2cf6cb50
CLG		 503
504 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
1373b15b 505 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
044475f3 506 TYPE_TMP105, 0x4d);
2cf6cb50
CLG		 507}
508
612b219a 509static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
ccc2c418 510{
52bcd997
HC		 511 AspeedSoCState *soc = &bmc->soc;
512 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
513
514 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
515 eeprom_buf);
516
517 /* LM75 is compatible with TMP105 driver */
518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
519 TYPE_TMP105, 0x4d);
ccc2c418
CLG		 520}
521
34f73a81
KP		 522static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
523{
524 AspeedSoCState *soc = &bmc->soc;
525
526 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
527 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
528 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
0a1f86ba
KP		 529 /* TMP421 */
530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
531 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
533
34f73a81
KP		 534}
535
612b219a 536static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
6c4567c7
CLG		 537{
538 AspeedSoCState *soc = &bmc->soc;
539
540 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
541 * good enough */
1373b15b 542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
6c4567c7
CLG		 543}
544
6c323aba
KP		 545static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
546{
547 AspeedSoCState *soc = &bmc->soc;
548
549 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
550 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
551 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
a09d357d
KP		 552 /* TMP421 */
553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
6c323aba
KP		 556}
557
f4aec252
CLG		 558static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
559{
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
561 TYPE_PCA9552, addr);
562}
563
612b219a 564static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
143b040f
PW		 565{
566 AspeedSoCState *soc = &bmc->soc;
567
568 /* bus 2 : */
1373b15b
PMD		 569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
143b040f
PW		 571 /* bus 2 : pca9546 @ 0x73 */
572
573 /* bus 3 : pca9548 @ 0x70 */
574
575 /* bus 4 : */
576 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
7a204cbd 577 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
143b040f
PW		 578 eeprom4_54);
579 /* PCA9539 @ 0x76, but PCA9552 is compatible */
f4aec252 580 create_pca9552(soc, 4, 0x76);
143b040f 581 /* PCA9539 @ 0x77, but PCA9552 is compatible */
f4aec252 582 create_pca9552(soc, 4, 0x77);
143b040f
PW		 583
584 /* bus 6 : */
1373b15b
PMD		 585 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
586 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
143b040f
PW		 587 /* bus 6 : pca9546 @ 0x73 */
588
589 /* bus 8 : */
590 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
7a204cbd 591 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
143b040f 592 eeprom8_56);
f4aec252
CLG		 593 create_pca9552(soc, 8, 0x60);
594 create_pca9552(soc, 8, 0x61);
143b040f
PW		 595 /* bus 8 : adc128d818 @ 0x1d */
596 /* bus 8 : adc128d818 @ 0x1f */
597
598 /*
599 * bus 13 : pca9548 @ 0x71
600 * - channel 3:
601 * - tmm421 @ 0x4c
602 * - tmp421 @ 0x4e
603 * - tmp421 @ 0x4f
604 */
605
606}
607
612b219a 608static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
62c2c2eb 609{
7cfbde5e
PMD		 610 static const struct {
611 unsigned gpio_id;
612 LEDColor color;
613 const char *description;
614 bool gpio_polarity;
615 } pca1_leds[] = {
616 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
617 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
618 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
619 };
62c2c2eb 620 AspeedSoCState *soc = &bmc->soc;
3d165f12 621 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
15ce12cf 622 DeviceState *dev;
7cfbde5e 623 LEDState *led;
62c2c2eb 624
63ceb818 625 /* Bus 3: TODO bmp280@77 */
db437ca6 626 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
15ce12cf 627 qdev_prop_set_string(dev, "description", "pca1");
2616f572
PMD		 628 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
629 aspeed_i2c_get_bus(&soc->i2c, 3),
630 &error_fatal);
8c9a61d7 631
7cfbde5e
PMD		 632 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
633 led = led_create_simple(OBJECT(bmc),
634 pca1_leds[i].gpio_polarity,
635 pca1_leds[i].color,
636 pca1_leds[i].description);
637 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
638 qdev_get_gpio_in(DEVICE(led), 0));
639 }
b61ea6e7 640 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
2a75e8c3 641 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
1373b15b
PMD		 642 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
62c2c2eb
CLG		 644
645 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
1373b15b 646 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
044475f3 647 0x4a);
6c4567c7
CLG		 648
649 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
650 * good enough */
1373b15b 651 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
3d165f12 652
7a204cbd 653 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
3d165f12 654 eeprom_buf);
db437ca6 655 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
15ce12cf 656 qdev_prop_set_string(dev, "description", "pca0");
2616f572
PMD		 657 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
658 aspeed_i2c_get_bus(&soc->i2c, 11),
659 &error_fatal);
63ceb818 660 /* Bus 11: TODO ucd90160@64 */
62c2c2eb
CLG		 661}
662
95f068c8
JW		 663static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
664{
665 AspeedSoCState *soc = &bmc->soc;
666 DeviceState *dev;
667
668 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
669 "emc1413", 0x4c));
670 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
671 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
672 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
673
674 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
675 "emc1413", 0x4c));
676 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
677 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
678 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
679
680 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
681 "emc1413", 0x4c));
682 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
683 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
684 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
6f5f6507
JW		 685
686 static uint8_t eeprom_buf[2 * 1024] = {
687 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
688 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
689 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
690 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
691 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
692 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
693 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
694 };
695 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
696 eeprom_buf);
95f068c8
JW		 697}
698
82b6a3f6
JW		 699static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
700{
701 AspeedSoCState *soc = &bmc->soc;
702 I2CSlave *i2c_mux;
703
704 /* The at24c256 */
705 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
706
707 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
709 0x48);
710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
711 0x49);
712
713 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
714 "pca9546", 0x70);
715 /* It expects a TMP112 but a TMP105 is compatible */
716 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
717 0x4a);
718
719 /* It expects a ds3232 but a ds1338 is good enough */
720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
721
722 /* It expects a pca9555 but a pca9552 is compatible */
f4aec252 723 create_pca9552(soc, 8, 0x30);
82b6a3f6
JW		 724}
725
58e52bdb
CLG		 726static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
727{
728 AspeedSoCState *soc = &bmc->soc;
fa6d98c0
JS		 729 I2CSlave *i2c_mux;
730
9077e09a 731 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
58e52bdb 732
f4aec252 733 create_pca9552(soc, 3, 0x61);
bcb122f8 734
58e52bdb
CLG		 735 /* The rainier expects a TMP275 but a TMP105 is compatible */
736 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
737 0x48);
738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
739 0x49);
740 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
741 0x4a);
fa6d98c0
JS		 742 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
743 "pca9546", 0x70);
9077e09a
PD		 744 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
745 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
746 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
f4aec252 747 create_pca9552(soc, 4, 0x60);
58e52bdb
CLG		 748
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
750 0x48);
751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
752 0x49);
f4aec252
CLG		 753 create_pca9552(soc, 5, 0x60);
754 create_pca9552(soc, 5, 0x61);
fa6d98c0
JS		 755 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
756 "pca9546", 0x70);
9077e09a
PD		 757 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
758 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
58e52bdb
CLG		 759
760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
761 0x48);
762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
763 0x4a);
764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
765 0x4b);
fa6d98c0
JS		 766 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
767 "pca9546", 0x70);
9077e09a
PD		 768 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
769 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
770 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
771 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
58e52bdb 772
f4aec252
CLG		 773 create_pca9552(soc, 7, 0x30);
774 create_pca9552(soc, 7, 0x31);
775 create_pca9552(soc, 7, 0x32);
776 create_pca9552(soc, 7, 0x33);
f4aec252
CLG		 777 create_pca9552(soc, 7, 0x60);
778 create_pca9552(soc, 7, 0x61);
b61ea6e7 779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
58e52bdb
CLG		 780 /* Bus 7: TODO si7021-a20@20 */
781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
782 0x48);
2a75e8c3 783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
9077e09a
PD		 784 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
785 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
58e52bdb
CLG		 786
787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
788 0x48);
789 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
790 0x4a);
be85508f
NP		 791 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
792 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
793 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
794 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
f4aec252
CLG		 795 create_pca9552(soc, 8, 0x60);
796 create_pca9552(soc, 8, 0x61);
58e52bdb
CLG		 797 /* Bus 8: ucd90320@11 */
798 /* Bus 8: ucd90320@b */
799 /* Bus 8: ucd90320@c */
800
801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
9077e09a 803 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
58e52bdb
CLG		 804
805 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
9077e09a 807 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
58e52bdb
CLG		 808
809 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
810 0x48);
811 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
812 0x49);
fa6d98c0
JS		 813 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
814 "pca9546", 0x70);
9077e09a
PD		 815 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
816 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
f4aec252 817 create_pca9552(soc, 11, 0x60);
fa6d98c0
JS		 818
819
9077e09a 820 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
f4aec252 821 create_pca9552(soc, 13, 0x60);
fa6d98c0 822
9077e09a 823 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
f4aec252 824 create_pca9552(soc, 14, 0x60);
fa6d98c0 825
9077e09a 826 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
f4aec252 827 create_pca9552(soc, 15, 0x60);
58e52bdb
CLG		 828}
829
febbe308
PD		 830static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
831 I2CBus **channels)
832{
833 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
834 for (int i = 0; i < 8; i++) {
835 channels[i] = pca954x_i2c_get_bus(mux, i);
836 }
837}
838
839#define TYPE_LM75 TYPE_TMP105
840#define TYPE_TMP75 TYPE_TMP105
841#define TYPE_TMP422 "tmp422"
842
843static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
844{
845 AspeedSoCState *soc = &bmc->soc;
846 I2CBus *i2c[144] = {};
847
848 for (int i = 0; i < 16; i++) {
849 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
850 }
851 I2CBus *i2c180 = i2c[2];
852 I2CBus *i2c480 = i2c[8];
853 I2CBus *i2c600 = i2c[11];
854
855 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
856 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
857 /* NOTE: The device tree skips [32, 40) in the alias numbering */
858 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
859 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
860 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
861 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
862 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
863 for (int i = 0; i < 8; i++) {
864 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
865 }
866
867 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
868 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
869
ef0eb67e
SS		 870 /*
871 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
872 * 24c02 size is 2Kbits or 256 bytes
873 */
874 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
875 at24c_eeprom_init(i2c[20], 0x50, 256);
876 at24c_eeprom_init(i2c[22], 0x52, 256);
febbe308
PD		 877
878 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
879 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
880 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
881 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
882
ef0eb67e 883 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
febbe308
PD		 884 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
885
886 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
ef0eb67e 887 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
febbe308
PD		 888 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
889 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
890
891 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
892 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
893
ef0eb67e 894 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
febbe308
PD		 895 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
896 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
ef0eb67e
SS		 897 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
898 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
899 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
900 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
febbe308 901
ef0eb67e 902 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
febbe308
PD		 903 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
904 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
ef0eb67e
SS		 905 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
906 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
907 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
908 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
909 at24c_eeprom_init(i2c[28], 0x50, 256);
febbe308
PD		 910
911 for (int i = 0; i < 8; i++) {
9077e09a 912 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
febbe308
PD		 913 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
914 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
915 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
916 }
917}
918
a20c54b1
PW		 919#define TYPE_TMP421 "tmp421"
920
921static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
922{
923 AspeedSoCState *soc = &bmc->soc;
924 I2CBus *i2c[13] = {};
925 for (int i = 0; i < 13; i++) {
926 if ((i == 8) || (i == 11)) {
927 continue;
928 }
929 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
930 }
931
932 /* Bus 0 - 5 all have the same config. */
933 for (int i = 0; i < 6; i++) {
934 /* Missing model: ti,ina230 @ 0x45 */
935 /* Missing model: mps,mp5023 @ 0x40 */
936 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
937 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
938 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
939 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
940 /* Missing model: fsc,fusb302 @ 0x22 */
941 }
942
943 /* Bus 6 */
944 at24c_eeprom_init(i2c[6], 0x56, 65536);
945 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
946 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
947
948
949 /* Bus 7 */
950 at24c_eeprom_init(i2c[7], 0x54, 65536);
951
952 /* Bus 9 */
953 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
954
955 /* Bus 10 */
956 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
957 /* Missing model: ti,hdc1080 @ 0x40 */
958 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
959
960 /* Bus 12 */
961 /* Missing model: adi,adm1278 @ 0x11 */
962 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
963 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
964 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
965}
966
fa699e80
PD		 967static void fby35_i2c_init(AspeedMachineState *bmc)
968{
969 AspeedSoCState *soc = &bmc->soc;
970 I2CBus *i2c[16];
971
972 for (int i = 0; i < 16; i++) {
973 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
974 }
975
976 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
977 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
978 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
979 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
980 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
981 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
982
9077e09a
PD		 983 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
984 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
c0216b94
PD		 985 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
986 fby35_nic_fruid_len);
987 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
988 fby35_bb_fruid_len);
989 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
990 fby35_bmc_fruid_len);
fa699e80
PD		 991
992 /*
993 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
994 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
995 * each.
996 */
997}
998
fb6b3c8d
JHY		 999static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1000{
1001 AspeedSoCState *soc = &bmc->soc;
1002
1003 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1004}
1005
ece4cccd
GG		 1006static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1007{
1008 AspeedSoCState *soc = &bmc->soc;
2a7a5d5c 1009 I2CSlave *therm_mux, *cpuvr_mux;
ece4cccd
GG		 1010
1011 /* Create the generic DC-SCM hardware */
1012 qcom_dc_scm_bmc_i2c_init(bmc);
1013
1014 /* Now create the Firework specific hardware */
2a75e8c3 1015
2a7a5d5c
JHY		 1016 /* I2C7 CPUVR MUX */
1017 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1018 "pca9546", 0x70);
1019 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1020 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1021 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1022 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1023
cfc68f16
MK		 1024 /* I2C8 Thermal Diodes*/
1025 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1026 "pca9548", 0x70);
1027 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1028 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1029 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1030 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1031 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1032
2a75e8c3
MK		 1033 /* I2C9 Fan Controller (MAX31785) */
1034 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1035 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
ece4cccd
GG		 1036}
1037
1a15311a
CLG		 1038static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1039{
1040 return ASPEED_MACHINE(obj)->mmio_exec;
1041}
1042
1043static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1044{
1045 ASPEED_MACHINE(obj)->mmio_exec = value;
1046}
1047
1048static void aspeed_machine_instance_init(Object *obj)
1049{
1050 ASPEED_MACHINE(obj)->mmio_exec = false;
1051}
1052
9820e52f
CLG		 1053static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1054{
1055 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1056 return g_strdup(bmc->fmc_model);
1057}
1058
1059static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1060{
1061 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1062
1063 g_free(bmc->fmc_model);
1064 bmc->fmc_model = g_strdup(value);
1065}
1066
1067static char *aspeed_get_spi_model(Object *obj, Error **errp)
1068{
1069 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1070 return g_strdup(bmc->spi_model);
1071}
1072
1073static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1074{
1075 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1076
1077 g_free(bmc->spi_model);
1078 bmc->spi_model = g_strdup(value);
1079}
1080
1a15311a
CLG		 1081static void aspeed_machine_class_props_init(ObjectClass *oc)
1082{
1083 object_class_property_add_bool(oc, "execute-in-place",
1084 aspeed_get_mmio_exec,
d2623129 1085 aspeed_set_mmio_exec);
1a15311a 1086 object_class_property_set_description(oc, "execute-in-place",
7eecec7d 1087 "boot directly from CE0 flash device");
9820e52f
CLG		 1088
1089 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1090 aspeed_set_fmc_model);
1091 object_class_property_set_description(oc, "fmc-model",
1092 "Change the FMC Flash model");
1093 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1094 aspeed_set_spi_model);
1095 object_class_property_set_description(oc, "spi-model",
1096 "Change the SPI Flash model");
1a15311a
CLG		 1097}
1098
b7f1a0cb
CLG		 1099static int aspeed_soc_num_cpus(const char *soc_name)
1100{
1101 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1102 return sc->num_cpus;
1103}
1104
fca9ca1b 1105static void aspeed_machine_class_init(ObjectClass *oc, void *data)
62c2c2eb
CLG		 1106{
1107 MachineClass *mc = MACHINE_CLASS(oc);
d3bad7e7 1108 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
62c2c2eb 1109
fca9ca1b 1110 mc->init = aspeed_machine_init;
62c2c2eb
CLG		 1111 mc->no_floppy = 1;
1112 mc->no_cdrom = 1;
1113 mc->no_parallel = 1;
afcbaed6 1114 mc->default_ram_id = "ram";
d3bad7e7 1115 amc->macs_mask = ASPEED_MAC0_ON;
5d63d0c7 1116 amc->uart_default = ASPEED_DEV_UART5;
1a15311a
CLG		 1117
1118 aspeed_machine_class_props_init(oc);
62c2c2eb
CLG		 1119}
1120
baa4732b
CLG		 1121static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1122{
1123 MachineClass *mc = MACHINE_CLASS(oc);
1124 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1125
1126 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1127 amc->soc_name = "ast2400-a1";
1128 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1129 amc->fmc_model = "n25q256a";
70322913 1130 amc->spi_model = "mx25l25635f";
baa4732b
CLG		 1131 amc->num_cs = 1;
1132 amc->i2c_init = palmetto_bmc_i2c_init;
1133 mc->default_ram_size = 256 * MiB;
b7f1a0cb
CLG		 1134 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1135 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1136};
1137
9cccb912
PV		 1138static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1139{
1140 MachineClass *mc = MACHINE_CLASS(oc);
1141 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1142
1143 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1144 amc->soc_name = "ast2400-a1";
1145 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1146 amc->fmc_model = "n25q256a";
1147 amc->spi_model = "mx25l25635e";
1148 amc->num_cs = 1;
1149 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1150 mc->default_ram_size = 128 * MiB;
1151 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1152 aspeed_soc_num_cpus(amc->soc_name);
1153}
1154
40a38df5
ES		 1155static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1156 void *data)
1157{
1158 MachineClass *mc = MACHINE_CLASS(oc);
1159 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1160
1161 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1162 amc->soc_name = "ast2400-a1";
1163 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1164 amc->fmc_model = "mx25l25635e";
1165 amc->spi_model = "mx25l25635e";
1166 amc->num_cs = 1;
1167 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1168 amc->i2c_init = palmetto_bmc_i2c_init;
1169 mc->default_ram_size = 256 * MiB;
1170}
1171
47936597
GR		 1172static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1173 void *data)
1174{
1175 MachineClass *mc = MACHINE_CLASS(oc);
1176 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1177
1178 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1179 amc->soc_name = "ast2500-a1";
1180 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1181 amc->fmc_model = "mx25l25635e";
1182 amc->spi_model = "mx25l25635e";
1183 amc->num_cs = 1;
1184 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1185 amc->i2c_init = palmetto_bmc_i2c_init;
1186 mc->default_ram_size = 512 * MiB;
1187 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1188 aspeed_soc_num_cpus(amc->soc_name);
1189}
1190
baa4732b
CLG		 1191static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1192{
1193 MachineClass *mc = MACHINE_CLASS(oc);
1194 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1195
1196 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1197 amc->soc_name = "ast2500-a1";
1198 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
753abfc4 1199 amc->fmc_model = "mx25l25635e";
70322913 1200 amc->spi_model = "mx25l25635f";
baa4732b
CLG		 1201 amc->num_cs = 1;
1202 amc->i2c_init = ast2500_evb_i2c_init;
1203 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1204 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1205 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1206};
1207
34f73a81
KP		 1208static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1209{
1210 MachineClass *mc = MACHINE_CLASS(oc);
1211 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1212
1213 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1214 amc->soc_name = "ast2500-a1";
1215 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1216 amc->hw_strap2 = 0;
1217 amc->fmc_model = "n25q256a";
1218 amc->spi_model = "mx25l25635e";
1219 amc->num_cs = 2;
1220 amc->i2c_init = yosemitev2_bmc_i2c_init;
1221 mc->default_ram_size = 512 * MiB;
1222 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1223 aspeed_soc_num_cpus(amc->soc_name);
1224};
1225
baa4732b
CLG		 1226static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1227{
1228 MachineClass *mc = MACHINE_CLASS(oc);
1229 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1230
1231 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1232 amc->soc_name = "ast2500-a1";
1233 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1234 amc->fmc_model = "n25q256a";
1235 amc->spi_model = "mx66l1g45g";
1236 amc->num_cs = 2;
1237 amc->i2c_init = romulus_bmc_i2c_init;
1238 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1239 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1240 aspeed_soc_num_cpus(amc->soc_name);
fca9ca1b
CLG		 1241};
1242
6c323aba
KP		 1243static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1244{
1245 MachineClass *mc = MACHINE_CLASS(oc);
1246 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1247
1248 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1249 amc->soc_name = "ast2500-a1";
1250 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1251 amc->hw_strap2 = 0;
1252 amc->fmc_model = "n25q256a";
1253 amc->spi_model = "mx25l25635e";
1254 amc->num_cs = 2;
1255 amc->i2c_init = tiogapass_bmc_i2c_init;
1256 mc->default_ram_size = 1 * GiB;
1257 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1258 aspeed_soc_num_cpus(amc->soc_name);
1259 aspeed_soc_num_cpus(amc->soc_name);
1260};
1261
143b040f
PW		 1262static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1263{
1264 MachineClass *mc = MACHINE_CLASS(oc);
1265 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1266
1267 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1268 amc->soc_name = "ast2500-a1";
1269 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1270 amc->fmc_model = "mx66l1g45g";
1271 amc->spi_model = "mx66l1g45g";
1272 amc->num_cs = 2;
1273 amc->i2c_init = sonorapass_bmc_i2c_init;
1274 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1275 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1276 aspeed_soc_num_cpus(amc->soc_name);
143b040f
PW		 1277};
1278
baa4732b
CLG		 1279static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1280{
1281 MachineClass *mc = MACHINE_CLASS(oc);
1282 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1283
1284 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1285 amc->soc_name = "ast2500-a1";
1286 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
70322913 1287 amc->fmc_model = "mx25l25635f";
baa4732b
CLG		 1288 amc->spi_model = "mx66l1g45g";
1289 amc->num_cs = 2;
1290 amc->i2c_init = witherspoon_bmc_i2c_init;
1291 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1292 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1293 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1294};
1295
1296static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1297{
1298 MachineClass *mc = MACHINE_CLASS(oc);
1299 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1300
f548f201 1301 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
c5811bb3 1302 amc->soc_name = "ast2600-a3";
baa4732b
CLG		 1303 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1304 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
753abfc4 1305 amc->fmc_model = "mx66u51235f";
baa4732b
CLG		 1306 amc->spi_model = "mx66u51235f";
1307 amc->num_cs = 1;
29193286
GR		 1308 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1309 ASPEED_MAC3_ON;
baa4732b
CLG		 1310 amc->i2c_init = ast2600_evb_i2c_init;
1311 mc->default_ram_size = 1 * GiB;
b7f1a0cb
CLG		 1312 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1313 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1314};
1315
63ceb818
CLG		 1316static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1317{
1318 MachineClass *mc = MACHINE_CLASS(oc);
1319 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1320
f548f201 1321 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
c5811bb3 1322 amc->soc_name = "ast2600-a3";
63ceb818
CLG		 1323 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1324 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1325 amc->fmc_model = "mx66l1g45g";
1326 amc->spi_model = "mx66l1g45g";
1327 amc->num_cs = 2;
d3bad7e7 1328 amc->macs_mask = ASPEED_MAC2_ON;
63ceb818
CLG		 1329 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1330 mc->default_ram_size = 1 * GiB;
b7f1a0cb
CLG		 1331 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1332 aspeed_soc_num_cpus(amc->soc_name);
63ceb818
CLG		 1333};
1334
95f068c8
JW		 1335static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1336{
1337 MachineClass *mc = MACHINE_CLASS(oc);
1338 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1339
1340 mc->desc = "Bytedance G220A BMC (ARM1176)";
1341 amc->soc_name = "ast2500-a1";
1342 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1343 amc->fmc_model = "n25q512a";
1344 amc->spi_model = "mx25l25635e";
1345 amc->num_cs = 2;
5bb825c8 1346 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
95f068c8
JW		 1347 amc->i2c_init = g220a_bmc_i2c_init;
1348 mc->default_ram_size = 1024 * MiB;
1349 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1350 aspeed_soc_num_cpus(amc->soc_name);
1351};
1352
82b6a3f6
JW		 1353static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1354{
1355 MachineClass *mc = MACHINE_CLASS(oc);
1356 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1357
1358 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1359 amc->soc_name = "ast2500-a1";
1360 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1361 amc->fmc_model = "n25q512a";
1362 amc->spi_model = "mx25l25635e";
1363 amc->num_cs = 2;
1364 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1365 amc->i2c_init = fp5280g2_bmc_i2c_init;
1366 mc->default_ram_size = 512 * MiB;
1367 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1368 aspeed_soc_num_cpus(amc->soc_name);
1369};
1370
58e52bdb
CLG		 1371static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1372{
1373 MachineClass *mc = MACHINE_CLASS(oc);
1374 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1375
f548f201 1376 mc->desc = "IBM Rainier BMC (Cortex-A7)";
c5811bb3 1377 amc->soc_name = "ast2600-a3";
58e52bdb
CLG		 1378 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1379 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1380 amc->fmc_model = "mx66l1g45g";
1381 amc->spi_model = "mx66l1g45g";
1382 amc->num_cs = 2;
1383 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1384 amc->i2c_init = rainier_bmc_i2c_init;
1385 mc->default_ram_size = 1 * GiB;
1386 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1387 aspeed_soc_num_cpus(amc->soc_name);
1388};
1389
febbe308
PD		 1390/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1391#if HOST_LONG_BITS == 32
1392#define FUJI_BMC_RAM_SIZE (1 * GiB)
1393#else
1394#define FUJI_BMC_RAM_SIZE (2 * GiB)
1395#endif
1396
1397static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1398{
1399 MachineClass *mc = MACHINE_CLASS(oc);
1400 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1401
1402 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1403 amc->soc_name = "ast2600-a3";
1404 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1405 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1406 amc->fmc_model = "mx66l1g45g";
1407 amc->spi_model = "mx66l1g45g";
1408 amc->num_cs = 2;
1409 amc->macs_mask = ASPEED_MAC3_ON;
1410 amc->i2c_init = fuji_bmc_i2c_init;
1411 amc->uart_default = ASPEED_DEV_UART1;
1412 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1413 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1414 aspeed_soc_num_cpus(amc->soc_name);
1415};
1416
104bdaff
PW		 1417/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1418#if HOST_LONG_BITS == 32
1419#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1420#else
1421#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1422#endif
1423
a20c54b1
PW		 1424static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1425{
1426 MachineClass *mc = MACHINE_CLASS(oc);
1427 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1428
1429 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1430 amc->soc_name = "ast2600-a3";
1431 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1432 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1433 amc->fmc_model = "w25q01jvq";
1434 amc->spi_model = NULL;
1435 amc->num_cs = 2;
1436 amc->macs_mask = ASPEED_MAC2_ON;
1437 amc->i2c_init = bletchley_bmc_i2c_init;
104bdaff 1438 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
a20c54b1
PW		 1439 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1440 aspeed_soc_num_cpus(amc->soc_name);
1441}
1442
7966d70f 1443static void fby35_reset(MachineState *state, ShutdownCause reason)
fa699e80
PD		 1444{
1445 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1446 AspeedGPIOState *gpio = &bmc->soc.gpio;
1447
7966d70f 1448 qemu_devices_reset(reason);
fa699e80 1449
f0418558 1450 /* Board ID: 7 (Class-1, 4 slots) */
fa699e80
PD		 1451 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1452 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1453 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1454 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
f0418558
PD		 1455
1456 /* Slot presence pins, inverse polarity. (False means present) */
1457 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1458 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1459 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1460 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1461
1462 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1463 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1464 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1465 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1466 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
fa699e80
PD		 1467}
1468
1469static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1470{
1471 MachineClass *mc = MACHINE_CLASS(oc);
1472 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1473
1474 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1475 mc->reset = fby35_reset;
1476 amc->fmc_model = "mx66l1g45g";
1477 amc->num_cs = 2;
1478 amc->macs_mask = ASPEED_MAC3_ON;
1479 amc->i2c_init = fby35_i2c_init;
1480 /* FIXME: Replace this macro with something more general */
1481 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1482}
1483
66c895b8
JL		 1484#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1485/* Main SYSCLK frequency in Hz (200MHz) */
1486#define SYSCLK_FRQ 200000000ULL
1487
1488static void aspeed_minibmc_machine_init(MachineState *machine)
1489{
1490 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1491 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1492 Clock *sysclk;
1493
1494 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1495 clock_set_hz(sysclk, SYSCLK_FRQ);
1496
1497 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1498 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1499
4dd9d554
PD		 1500 object_property_set_link(OBJECT(&bmc->soc), "memory",
1501 OBJECT(get_system_memory()), &error_abort);
d2b3eaef 1502 connect_serial_hds_to_uarts(bmc);
66c895b8
JL		 1503 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1504
1505 aspeed_board_init_flashes(&bmc->soc.fmc,
1506 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1507 amc->num_cs,
1508 0);
1509
1510 aspeed_board_init_flashes(&bmc->soc.spi[0],
1511 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1512 amc->num_cs, amc->num_cs);
1513
1514 aspeed_board_init_flashes(&bmc->soc.spi[1],
1515 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1516 amc->num_cs, (amc->num_cs * 2));
1517
1518 if (amc->i2c_init) {
1519 amc->i2c_init(bmc);
1520 }
1521
1522 armv7m_load_kernel(ARM_CPU(first_cpu),
1523 machine->kernel_filename,
761c532a 1524 0,
66c895b8
JL		 1525 AST1030_INTERNAL_FLASH_SIZE);
1526}
1527
4c70ab16
TL		 1528static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1529{
1530 AspeedSoCState *soc = &bmc->soc;
1531
1532 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1533 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1534 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1535
1536 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1537 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1538}
1539
66c895b8
JL		 1540static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1541 void *data)
1542{
1543 MachineClass *mc = MACHINE_CLASS(oc);
1544 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1545
1546 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1547 amc->soc_name = "ast1030-a1";
1548 amc->hw_strap1 = 0;
1549 amc->hw_strap2 = 0;
1550 mc->init = aspeed_minibmc_machine_init;
4c70ab16 1551 amc->i2c_init = ast1030_evb_i2c_init;
66c895b8
JL		 1552 mc->default_ram_size = 0;
1553 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1554 amc->fmc_model = "sst25vf032b";
1555 amc->spi_model = "sst25vf032b";
1556 amc->num_cs = 2;
1557 amc->macs_mask = 0;
1558}
1559
fb6b3c8d
JHY		 1560static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1561 void *data)
1562{
1563 MachineClass *mc = MACHINE_CLASS(oc);
1564 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1565
1566 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1567 amc->soc_name = "ast2600-a3";
1568 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1569 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1570 amc->fmc_model = "n25q512a";
1571 amc->spi_model = "n25q512a";
1572 amc->num_cs = 2;
1573 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1574 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1575 mc->default_ram_size = 1 * GiB;
1576 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1577 aspeed_soc_num_cpus(amc->soc_name);
1578};
1579
ece4cccd
GG		 1580static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1581 void *data)
1582{
1583 MachineClass *mc = MACHINE_CLASS(oc);
1584 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1585
1586 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1587 amc->soc_name = "ast2600-a3";
1588 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1589 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1590 amc->fmc_model = "n25q512a";
1591 amc->spi_model = "n25q512a";
1592 amc->num_cs = 2;
1593 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1594 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1595 mc->default_ram_size = 1 * GiB;
1596 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1597 aspeed_soc_num_cpus(amc->soc_name);
1598};
1599
baa4732b 1600static const TypeInfo aspeed_machine_types[] = {
fca9ca1b 1601 {
baa4732b
CLG		 1602 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1603 .parent = TYPE_ASPEED_MACHINE,
1604 .class_init = aspeed_machine_palmetto_class_init,
40a38df5
ES		 1605 }, {
1606 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1607 .parent = TYPE_ASPEED_MACHINE,
1608 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
47936597
GR		 1609 }, {
1610 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1611 .parent = TYPE_ASPEED_MACHINE,
1612 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
fca9ca1b 1613 }, {
baa4732b
CLG		 1614 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1615 .parent = TYPE_ASPEED_MACHINE,
1616 .class_init = aspeed_machine_ast2500_evb_class_init,
fca9ca1b 1617 }, {
baa4732b
CLG		 1618 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1619 .parent = TYPE_ASPEED_MACHINE,
1620 .class_init = aspeed_machine_romulus_class_init,
143b040f
PW		 1621 }, {
1622 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1623 .parent = TYPE_ASPEED_MACHINE,
1624 .class_init = aspeed_machine_sonorapass_class_init,
fca9ca1b 1625 }, {
baa4732b
CLG		 1626 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1627 .parent = TYPE_ASPEED_MACHINE,
1628 .class_init = aspeed_machine_witherspoon_class_init,
ccc2c418 1629 }, {
baa4732b
CLG		 1630 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1631 .parent = TYPE_ASPEED_MACHINE,
1632 .class_init = aspeed_machine_ast2600_evb_class_init,
34f73a81
KP		 1633 }, {
1634 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1635 .parent = TYPE_ASPEED_MACHINE,
1636 .class_init = aspeed_machine_yosemitev2_class_init,
63ceb818
CLG		 1637 }, {
1638 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1639 .parent = TYPE_ASPEED_MACHINE,
1640 .class_init = aspeed_machine_tacoma_class_init,
6c323aba
KP		 1641 }, {
1642 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1643 .parent = TYPE_ASPEED_MACHINE,
1644 .class_init = aspeed_machine_tiogapass_class_init,
95f068c8
JW		 1645 }, {
1646 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1647 .parent = TYPE_ASPEED_MACHINE,
1648 .class_init = aspeed_machine_g220a_class_init,
fb6b3c8d
JHY		 1649 }, {
1650 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1651 .parent = TYPE_ASPEED_MACHINE,
1652 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
ece4cccd
GG		 1653 }, {
1654 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1655 .parent = TYPE_ASPEED_MACHINE,
1656 .class_init = aspeed_machine_qcom_firework_class_init,
82b6a3f6
JW		 1657 }, {
1658 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1659 .parent = TYPE_ASPEED_MACHINE,
1660 .class_init = aspeed_machine_fp5280g2_class_init,
9cccb912
PV		 1661 }, {
1662 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1663 .parent = TYPE_ASPEED_MACHINE,
1664 .class_init = aspeed_machine_quanta_q71l_class_init,
58e52bdb
CLG		 1665 }, {
1666 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1667 .parent = TYPE_ASPEED_MACHINE,
1668 .class_init = aspeed_machine_rainier_class_init,
febbe308
PD		 1669 }, {
1670 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1671 .parent = TYPE_ASPEED_MACHINE,
1672 .class_init = aspeed_machine_fuji_class_init,
a20c54b1
PW		 1673 }, {
1674 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1675 .parent = TYPE_ASPEED_MACHINE,
1676 .class_init = aspeed_machine_bletchley_class_init,
fa699e80
PD		 1677 }, {
1678 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1679 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1680 .class_init = aspeed_machine_fby35_class_init,
66c895b8
JL		 1681 }, {
1682 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1683 .parent = TYPE_ASPEED_MACHINE,
1684 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
baa4732b
CLG		 1685 }, {
1686 .name = TYPE_ASPEED_MACHINE,
1687 .parent = TYPE_MACHINE,
888b2b03 1688 .instance_size = sizeof(AspeedMachineState),
1a15311a 1689 .instance_init = aspeed_machine_instance_init,
baa4732b
CLG		 1690 .class_size = sizeof(AspeedMachineClass),
1691 .class_init = aspeed_machine_class_init,
1692 .abstract = true,
fca9ca1b 1693 }
baa4732b 1694};
74fb1f38 1695
baa4732b 1696DEFINE_TYPES(aspeed_machine_types)
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