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pci: call object_unparent() before free_qdev()
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3
AF		 30#include "qapi/qapi-visit-core.h"
31
28f52cc0
VR		 32#include "hyperv.h"
33
c6dc6f63
AP		 34/* feature flags taken from "Intel Processor Identification and the CPUID
35 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
36 * between feature naming conventions, aliases may be added.
37 */
38static const char *feature_name[] = {
39 "fpu", "vme", "de", "pse",
40 "tsc", "msr", "pae", "mce",
41 "cx8", "apic", NULL, "sep",
42 "mtrr", "pge", "mca", "cmov",
43 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
44 NULL, "ds" /* Intel dts */, "acpi", "mmx",
45 "fxsr", "sse", "sse2", "ss",
46 "ht" /* Intel htt */, "tm", "ia64", "pbe",
47};
48static const char *ext_feature_name[] = {
f370be3c 49 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 50 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 51 "tm2", "ssse3", "cid", NULL,
e117f772 52 "fma", "cx16", "xtpr", "pdcm",
c6dc6f63 53 NULL, NULL, "dca", "sse4.1|sse4_1",
e117f772 54 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 55 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 56 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 57};
58static const char *ext2_feature_name[] = {
59 "fpu", "vme", "de", "pse",
60 "tsc", "msr", "pae", "mce",
61 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
62 "mtrr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 64 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 65 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 66 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 67};
68static const char *ext3_feature_name[] = {
69 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
70 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 71 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 72 "skinit", "wdt", NULL, NULL,
e117f772 73 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 74 NULL, NULL, NULL, NULL,
75 NULL, NULL, NULL, NULL,
76 NULL, NULL, NULL, NULL,
77};
78
79static const char *kvm_feature_name[] = {
642258c6 80 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
c6dc6f63
AP		 81 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
83 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
84};
85
296acb64
JR		 86static const char *svm_feature_name[] = {
87 "npt", "lbrv", "svm_lock", "nrip_save",
88 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
89 NULL, NULL, "pause_filter", NULL,
90 "pfthreshold", NULL, NULL, NULL,
91 NULL, NULL, NULL, NULL,
92 NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95};
96
c6dc6f63
AP		 97/* collects per-function cpuid data
98 */
99typedef struct model_features_t {
100 uint32_t *guest_feat;
101 uint32_t *host_feat;
102 uint32_t check_feat;
103 const char **flag_names;
104 uint32_t cpuid;
105 } model_features_t;
106
107int check_cpuid = 0;
108int enforce_cpuid = 0;
109
bb44e0d1
JK		 110void host_cpuid(uint32_t function, uint32_t count,
111 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 112{
113#if defined(CONFIG_KVM)
a1fd24af
AL		 114 uint32_t vec[4];
115
116#ifdef __x86_64__
117 asm volatile("cpuid"
118 : "=a"(vec[0]), "=b"(vec[1]),
119 "=c"(vec[2]), "=d"(vec[3])
120 : "0"(function), "c"(count) : "cc");
121#else
122 asm volatile("pusha \n\t"
123 "cpuid \n\t"
124 "mov %%eax, 0(%2) \n\t"
125 "mov %%ebx, 4(%2) \n\t"
126 "mov %%ecx, 8(%2) \n\t"
127 "mov %%edx, 12(%2) \n\t"
128 "popa"
129 : : "a"(function), "c"(count), "S"(vec)
130 : "memory", "cc");
131#endif
132
bdde476a 133 if (eax)
a1fd24af 134 *eax = vec[0];
bdde476a 135 if (ebx)
a1fd24af 136 *ebx = vec[1];
bdde476a 137 if (ecx)
a1fd24af 138 *ecx = vec[2];
bdde476a 139 if (edx)
a1fd24af 140 *edx = vec[3];
bdde476a
AP		 141#endif
142}
c6dc6f63
AP		 143
144#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
145
146/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
147 * a substring. ex if !NULL points to the first char after a substring,
148 * otherwise the string is assumed to sized by a terminating nul.
149 * Return lexical ordering of *s1:*s2.
150 */
151static int sstrcmp(const char *s1, const char *e1, const char *s2,
152 const char *e2)
153{
154 for (;;) {
155 if (!*s1 || !*s2 || *s1 != *s2)
156 return (*s1 - *s2);
157 ++s1, ++s2;
158 if (s1 == e1 && s2 == e2)
159 return (0);
160 else if (s1 == e1)
161 return (*s2);
162 else if (s2 == e2)
163 return (*s1);
164 }
165}
166
167/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
168 * '|' delimited (possibly empty) strings in which case search for a match
169 * within the alternatives proceeds left to right. Return 0 for success,
170 * non-zero otherwise.
171 */
172static int altcmp(const char *s, const char *e, const char *altstr)
173{
174 const char *p, *q;
175
176 for (q = p = altstr; ; ) {
177 while (*p && *p != '|')
178 ++p;
179 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
180 return (0);
181 if (!*p)
182 return (1);
183 else
184 q = ++p;
185 }
186}
187
188/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 189 * *pval and return true, otherwise return false
c6dc6f63 190 */
e41e0fc6
JK		 191static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
192 const char **featureset)
c6dc6f63
AP		 193{
194 uint32_t mask;
195 const char **ppc;
e41e0fc6 196 bool found = false;
c6dc6f63 197
e41e0fc6 198 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 199 if (*ppc && !altcmp(s, e, *ppc)) {
200 *pval |= mask;
e41e0fc6 201 found = true;
c6dc6f63 202 }
e41e0fc6
JK		 203 }
204 return found;
c6dc6f63
AP		 205}
206
207static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
208 uint32_t *ext_features,
209 uint32_t *ext2_features,
210 uint32_t *ext3_features,
296acb64
JR		 211 uint32_t *kvm_features,
212 uint32_t *svm_features)
c6dc6f63
AP		 213{
214 if (!lookup_feature(features, flagname, NULL, feature_name) &&
215 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
216 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
217 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 218 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
219 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 220 fprintf(stderr, "CPU feature %s not found\n", flagname);
221}
222
223typedef struct x86_def_t {
224 struct x86_def_t *next;
225 const char *name;
226 uint32_t level;
227 uint32_t vendor1, vendor2, vendor3;
228 int family;
229 int model;
230 int stepping;
b862d1fe 231 int tsc_khz;
296acb64
JR		 232 uint32_t features, ext_features, ext2_features, ext3_features;
233 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 234 uint32_t xlevel;
235 char model_id[48];
236 int vendor_override;
237 uint32_t flags;
b3baa152
BW		 238 /* Store the results of Centaur's CPUID instructions */
239 uint32_t ext4_features;
240 uint32_t xlevel2;
c6dc6f63
AP		 241} x86_def_t;
242
243#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
244#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
245 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
246#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
247 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
248 CPUID_PSE36 | CPUID_FXSR)
249#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
250#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
251 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
252 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
253 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 254#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 255
551a2dec
AP		 256#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
257 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
258 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
259 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
260 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 261 /* partly implemented:
262 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
263 CPUID_PSE36 (needed for Solaris) */
264 /* missing:
265 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 266#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 267 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 268 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 269 /* missing:
270 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 271 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 272#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
273 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
274 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 275 /* missing:
276 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 277#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
278 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 279#define TCG_SVM_FEATURES 0
551a2dec 280
c6dc6f63
AP		 281/* maintains list of cpu model definitions
282 */
283static x86_def_t *x86_defs = {NULL};
284
285/* built-in cpu model definitions (deprecated)
286 */
287static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 288 {
289 .name = "qemu64",
290 .level = 4,
291 .vendor1 = CPUID_VENDOR_AMD_1,
292 .vendor2 = CPUID_VENDOR_AMD_2,
293 .vendor3 = CPUID_VENDOR_AMD_3,
294 .family = 6,
295 .model = 2,
296 .stepping = 3,
297 .features = PPRO_FEATURES |
c6dc6f63 298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 299 CPUID_PSE36,
300 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 301 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 302 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
303 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
304 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
305 .xlevel = 0x8000000A,
306 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
307 },
308 {
309 .name = "phenom",
310 .level = 5,
311 .vendor1 = CPUID_VENDOR_AMD_1,
312 .vendor2 = CPUID_VENDOR_AMD_2,
313 .vendor3 = CPUID_VENDOR_AMD_3,
314 .family = 16,
315 .model = 2,
316 .stepping = 3,
c6dc6f63
AP		 317 .features = PPRO_FEATURES |
318 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 319 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 320 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
321 CPUID_EXT_POPCNT,
42673936 322 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 323 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
324 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 325 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 326 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
327 CPUID_EXT3_CR8LEG,
328 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
329 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
330 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
331 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 332 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 333 .xlevel = 0x8000001A,
334 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
335 },
336 {
337 .name = "core2duo",
338 .level = 10,
339 .family = 6,
340 .model = 15,
341 .stepping = 11,
c6dc6f63
AP		 342 .features = PPRO_FEATURES |
343 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 344 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
345 CPUID_HT | CPUID_TM | CPUID_PBE,
346 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
347 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
348 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 349 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
350 .ext3_features = CPUID_EXT3_LAHF_LM,
351 .xlevel = 0x80000008,
352 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
353 },
354 {
355 .name = "kvm64",
356 .level = 5,
357 .vendor1 = CPUID_VENDOR_INTEL_1,
358 .vendor2 = CPUID_VENDOR_INTEL_2,
359 .vendor3 = CPUID_VENDOR_INTEL_3,
360 .family = 15,
361 .model = 6,
362 .stepping = 1,
363 /* Missing: CPUID_VME, CPUID_HT */
364 .features = PPRO_FEATURES |
365 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
366 CPUID_PSE36,
367 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
368 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
369 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 370 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 371 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
372 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
373 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
374 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
375 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
376 .ext3_features = 0,
377 .xlevel = 0x80000008,
378 .model_id = "Common KVM processor"
379 },
c6dc6f63
AP		 380 {
381 .name = "qemu32",
382 .level = 4,
383 .family = 6,
384 .model = 3,
385 .stepping = 3,
386 .features = PPRO_FEATURES,
387 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 388 .xlevel = 0x80000004,
c6dc6f63
AP		 389 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
390 },
eafaf1e5
AP		 391 {
392 .name = "kvm32",
393 .level = 5,
394 .family = 15,
395 .model = 6,
396 .stepping = 1,
397 .features = PPRO_FEATURES |
398 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
399 .ext_features = CPUID_EXT_SSE3,
400 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
401 .ext3_features = 0,
402 .xlevel = 0x80000008,
403 .model_id = "Common 32-bit KVM processor"
404 },
c6dc6f63
AP		 405 {
406 .name = "coreduo",
407 .level = 10,
408 .family = 6,
409 .model = 14,
410 .stepping = 8,
c6dc6f63 411 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 412 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
413 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
414 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
415 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 416 .ext2_features = CPUID_EXT2_NX,
417 .xlevel = 0x80000008,
418 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
419 },
420 {
421 .name = "486",
58012d66 422 .level = 1,
c6dc6f63
AP		 423 .family = 4,
424 .model = 0,
425 .stepping = 0,
426 .features = I486_FEATURES,
427 .xlevel = 0,
428 },
429 {
430 .name = "pentium",
431 .level = 1,
432 .family = 5,
433 .model = 4,
434 .stepping = 3,
435 .features = PENTIUM_FEATURES,
436 .xlevel = 0,
437 },
438 {
439 .name = "pentium2",
440 .level = 2,
441 .family = 6,
442 .model = 5,
443 .stepping = 2,
444 .features = PENTIUM2_FEATURES,
445 .xlevel = 0,
446 },
447 {
448 .name = "pentium3",
449 .level = 2,
450 .family = 6,
451 .model = 7,
452 .stepping = 3,
453 .features = PENTIUM3_FEATURES,
454 .xlevel = 0,
455 },
456 {
457 .name = "athlon",
458 .level = 2,
459 .vendor1 = CPUID_VENDOR_AMD_1,
460 .vendor2 = CPUID_VENDOR_AMD_2,
461 .vendor3 = CPUID_VENDOR_AMD_3,
462 .family = 6,
463 .model = 2,
464 .stepping = 3,
465 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 466 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63
AP		 467 .xlevel = 0x80000008,
468 /* XXX: put another string ? */
469 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
470 },
471 {
472 .name = "n270",
473 /* original is on level 10 */
474 .level = 5,
475 .family = 6,
476 .model = 28,
477 .stepping = 2,
478 .features = PPRO_FEATURES |
8560efed
AJ		 479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
480 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 481 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 482 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
483 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 484 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 485 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 486 .xlevel = 0x8000000A,
487 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
488 },
489};
490
491static int cpu_x86_fill_model_id(char *str)
492{
493 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
494 int i;
495
496 for (i = 0; i < 3; i++) {
497 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
498 memcpy(str + i * 16 + 0, &eax, 4);
499 memcpy(str + i * 16 + 4, &ebx, 4);
500 memcpy(str + i * 16 + 8, &ecx, 4);
501 memcpy(str + i * 16 + 12, &edx, 4);
502 }
503 return 0;
504}
505
506static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
507{
508 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
509
510 x86_cpu_def->name = "host";
511 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
512 x86_cpu_def->level = eax;
513 x86_cpu_def->vendor1 = ebx;
514 x86_cpu_def->vendor2 = edx;
515 x86_cpu_def->vendor3 = ecx;
516
517 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
518 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
519 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
520 x86_cpu_def->stepping = eax & 0x0F;
521 x86_cpu_def->ext_features = ecx;
522 x86_cpu_def->features = edx;
523
524 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
525 x86_cpu_def->xlevel = eax;
526
527 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
528 x86_cpu_def->ext2_features = edx;
529 x86_cpu_def->ext3_features = ecx;
530 cpu_x86_fill_model_id(x86_cpu_def->model_id);
531 x86_cpu_def->vendor_override = 0;
532
b3baa152
BW		 533 /* Call Centaur's CPUID instruction. */
534 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
535 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
536 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
537 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
538 if (eax >= 0xC0000001) {
539 /* Support VIA max extended level */
540 x86_cpu_def->xlevel2 = eax;
541 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
542 x86_cpu_def->ext4_features = edx;
543 }
544 }
296acb64
JR		 545
546 /*
547 * Every SVM feature requires emulation support in KVM - so we can't just
548 * read the host features here. KVM might even support SVM features not
549 * available on the host hardware. Just set all bits and mask out the
550 * unsupported ones later.
551 */
552 x86_cpu_def->svm_features = -1;
553
c6dc6f63
AP		 554 return 0;
555}
556
557static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
558{
559 int i;
560
561 for (i = 0; i < 32; ++i)
562 if (1 << i & mask) {
563 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
564 " flag '%s' [0x%08x]\n",
565 f->cpuid >> 16, f->cpuid & 0xffff,
566 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
567 break;
568 }
569 return 0;
570}
571
572/* best effort attempt to inform user requested cpu flags aren't making
573 * their way to the guest. Note: ft[].check_feat ideally should be
574 * specified via a guest_def field to suppress report of extraneous flags.
575 */
576static int check_features_against_host(x86_def_t *guest_def)
577{
578 x86_def_t host_def;
579 uint32_t mask;
580 int rv, i;
581 struct model_features_t ft[] = {
582 {&guest_def->features, &host_def.features,
583 ~0, feature_name, 0x00000000},
584 {&guest_def->ext_features, &host_def.ext_features,
585 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
586 {&guest_def->ext2_features, &host_def.ext2_features,
587 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
588 {&guest_def->ext3_features, &host_def.ext3_features,
589 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
590
591 cpu_x86_fill_host(&host_def);
66fe09ee 592 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 593 for (mask = 1; mask; mask <<= 1)
594 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
595 !(*ft[i].host_feat & mask)) {
596 unavailable_host_feature(&ft[i], mask);
597 rv = 1;
598 }
599 return rv;
600}
601
95b8519d
AF		 602static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
603 const char *name, Error **errp)
604{
605 X86CPU *cpu = X86_CPU(obj);
606 CPUX86State *env = &cpu->env;
607 int64_t value;
608
609 value = (env->cpuid_version >> 8) & 0xf;
610 if (value == 0xf) {
611 value += (env->cpuid_version >> 20) & 0xff;
612 }
613 visit_type_int(v, &value, name, errp);
614}
615
71ad61d3
AF		 616static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
617 const char *name, Error **errp)
ed5e1ec3 618{
71ad61d3
AF		 619 X86CPU *cpu = X86_CPU(obj);
620 CPUX86State *env = &cpu->env;
621 const int64_t min = 0;
622 const int64_t max = 0xff + 0xf;
623 int64_t value;
624
625 visit_type_int(v, &value, name, errp);
626 if (error_is_set(errp)) {
627 return;
628 }
629 if (value < min || value > max) {
630 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
631 name ? name : "null", value, min, max);
632 return;
633 }
634
ed5e1ec3 635 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 636 if (value > 0x0f) {
637 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 638 } else {
71ad61d3 639 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 640 }
641}
642
67e30c83
AF		 643static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
644 const char *name, Error **errp)
645{
646 X86CPU *cpu = X86_CPU(obj);
647 CPUX86State *env = &cpu->env;
648 int64_t value;
649
650 value = (env->cpuid_version >> 4) & 0xf;
651 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
652 visit_type_int(v, &value, name, errp);
653}
654
c5291a4f
AF		 655static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
656 const char *name, Error **errp)
b0704cbd 657{
c5291a4f
AF		 658 X86CPU *cpu = X86_CPU(obj);
659 CPUX86State *env = &cpu->env;
660 const int64_t min = 0;
661 const int64_t max = 0xff;
662 int64_t value;
663
664 visit_type_int(v, &value, name, errp);
665 if (error_is_set(errp)) {
666 return;
667 }
668 if (value < min || value > max) {
669 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
670 name ? name : "null", value, min, max);
671 return;
672 }
673
b0704cbd 674 env->cpuid_version &= ~0xf00f0;
c5291a4f 675 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 676}
677
35112e41
AF		 678static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
679 void *opaque, const char *name,
680 Error **errp)
681{
682 X86CPU *cpu = X86_CPU(obj);
683 CPUX86State *env = &cpu->env;
684 int64_t value;
685
686 value = env->cpuid_version & 0xf;
687 visit_type_int(v, &value, name, errp);
688}
689
036e2222
AF		 690static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
691 void *opaque, const char *name,
692 Error **errp)
38c3dc46 693{
036e2222
AF		 694 X86CPU *cpu = X86_CPU(obj);
695 CPUX86State *env = &cpu->env;
696 const int64_t min = 0;
697 const int64_t max = 0xf;
698 int64_t value;
699
700 visit_type_int(v, &value, name, errp);
701 if (error_is_set(errp)) {
702 return;
703 }
704 if (value < min || value > max) {
705 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
706 name ? name : "null", value, min, max);
707 return;
708 }
709
38c3dc46 710 env->cpuid_version &= ~0xf;
036e2222 711 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 712}
713
8e1898bf
AF		 714static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
715 const char *name, Error **errp)
716{
717 X86CPU *cpu = X86_CPU(obj);
718 int64_t value;
719
720 value = cpu->env.cpuid_level;
721 /* TODO Use visit_type_uint32() once available */
722 visit_type_int(v, &value, name, errp);
723}
724
725static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
726 const char *name, Error **errp)
727{
728 X86CPU *cpu = X86_CPU(obj);
729 const int64_t min = 0;
730 const int64_t max = UINT32_MAX;
731 int64_t value;
732
733 /* TODO Use visit_type_uint32() once available */
734 visit_type_int(v, &value, name, errp);
735 if (error_is_set(errp)) {
736 return;
737 }
738 if (value < min || value > max) {
739 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
740 name ? name : "null", value, min, max);
741 return;
742 }
743
744 cpu->env.cpuid_level = value;
745}
746
16b93aa8
AF		 747static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
748 const char *name, Error **errp)
749{
750 X86CPU *cpu = X86_CPU(obj);
751 int64_t value;
752
753 value = cpu->env.cpuid_xlevel;
754 /* TODO Use visit_type_uint32() once available */
755 visit_type_int(v, &value, name, errp);
756}
757
758static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
759 const char *name, Error **errp)
760{
761 X86CPU *cpu = X86_CPU(obj);
762 const int64_t min = 0;
763 const int64_t max = UINT32_MAX;
764 int64_t value;
765
766 /* TODO Use visit_type_uint32() once available */
767 visit_type_int(v, &value, name, errp);
768 if (error_is_set(errp)) {
769 return;
770 }
771 if (value < min || value > max) {
772 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
773 name ? name : "null", value, min, max);
774 return;
775 }
776
777 cpu->env.cpuid_xlevel = value;
778}
779
d480e1af
AF		 780static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
781{
782 X86CPU *cpu = X86_CPU(obj);
783 CPUX86State *env = &cpu->env;
784 char *value;
785 int i;
786
787 value = (char *)g_malloc(12 + 1);
788 for (i = 0; i < 4; i++) {
789 value[i ] = env->cpuid_vendor1 >> (8 * i);
790 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
791 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
792 }
793 value[12] = '\0';
794 return value;
795}
796
797static void x86_cpuid_set_vendor(Object *obj, const char *value,
798 Error **errp)
799{
800 X86CPU *cpu = X86_CPU(obj);
801 CPUX86State *env = &cpu->env;
802 int i;
803
804 if (strlen(value) != 12) {
805 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
806 "vendor", value);
807 return;
808 }
809
810 env->cpuid_vendor1 = 0;
811 env->cpuid_vendor2 = 0;
812 env->cpuid_vendor3 = 0;
813 for (i = 0; i < 4; i++) {
814 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
815 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
816 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
817 }
818 env->cpuid_vendor_override = 1;
819}
820
63e886eb
AF		 821static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
822{
823 X86CPU *cpu = X86_CPU(obj);
824 CPUX86State *env = &cpu->env;
825 char *value;
826 int i;
827
828 value = g_malloc(48 + 1);
829 for (i = 0; i < 48; i++) {
830 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
831 }
832 value[48] = '\0';
833 return value;
834}
835
938d4c25
AF		 836static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
837 Error **errp)
dcce6675 838{
938d4c25
AF		 839 X86CPU *cpu = X86_CPU(obj);
840 CPUX86State *env = &cpu->env;
dcce6675
AF		 841 int c, len, i;
842
843 if (model_id == NULL) {
844 model_id = "";
845 }
846 len = strlen(model_id);
d0a6acf4 847 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 848 for (i = 0; i < 48; i++) {
849 if (i >= len) {
850 c = '\0';
851 } else {
852 c = (uint8_t)model_id[i];
853 }
854 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
855 }
856}
857
89e48965
AF		 858static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
859 const char *name, Error **errp)
860{
861 X86CPU *cpu = X86_CPU(obj);
862 int64_t value;
863
864 value = cpu->env.tsc_khz * 1000;
865 visit_type_int(v, &value, name, errp);
866}
867
868static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
869 const char *name, Error **errp)
870{
871 X86CPU *cpu = X86_CPU(obj);
872 const int64_t min = 0;
873 const int64_t max = INT_MAX;
874 int64_t value;
875
876 visit_type_int(v, &value, name, errp);
877 if (error_is_set(errp)) {
878 return;
879 }
880 if (value < min || value > max) {
881 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
882 name ? name : "null", value, min, max);
883 return;
884 }
885
886 cpu->env.tsc_khz = value / 1000;
887}
888
c6dc6f63
AP		 889static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
890{
891 unsigned int i;
892 x86_def_t *def;
893
d3c481b3 894 char *s = g_strdup(cpu_model);
c6dc6f63 895 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 896 /* Features to be added*/
897 uint32_t plus_features = 0, plus_ext_features = 0;
898 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
899 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
900 /* Features to be removed */
901 uint32_t minus_features = 0, minus_ext_features = 0;
902 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
903 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 904 uint32_t numvalue;
905
906 for (def = x86_defs; def; def = def->next)
04c5b17a 907 if (name && !strcmp(name, def->name))
c6dc6f63 908 break;
04c5b17a 909 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 910 cpu_x86_fill_host(x86_cpu_def);
911 } else if (!def) {
912 goto error;
913 } else {
914 memcpy(x86_cpu_def, def, sizeof(*def));
915 }
916
917 plus_kvm_features = ~0; /* not supported bits will be filtered out later */
918
919 add_flagname_to_bitmaps("hypervisor", &plus_features,
920 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 921 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 922
923 featurestr = strtok(NULL, ",");
924
925 while (featurestr) {
926 char *val;
927 if (featurestr[0] == '+') {
296acb64
JR		 928 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
929 &plus_ext_features, &plus_ext2_features,
930 &plus_ext3_features, &plus_kvm_features,
931 &plus_svm_features);
c6dc6f63 932 } else if (featurestr[0] == '-') {
296acb64
JR		 933 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
934 &minus_ext_features, &minus_ext2_features,
935 &minus_ext3_features, &minus_kvm_features,
936 &minus_svm_features);
c6dc6f63
AP		 937 } else if ((val = strchr(featurestr, '='))) {
938 *val = 0; val++;
939 if (!strcmp(featurestr, "family")) {
940 char *err;
941 numvalue = strtoul(val, &err, 0);
a88a677f 942 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 943 fprintf(stderr, "bad numerical value %s\n", val);
944 goto error;
945 }
946 x86_cpu_def->family = numvalue;
947 } else if (!strcmp(featurestr, "model")) {
948 char *err;
949 numvalue = strtoul(val, &err, 0);
950 if (!*val || *err || numvalue > 0xff) {
951 fprintf(stderr, "bad numerical value %s\n", val);
952 goto error;
953 }
954 x86_cpu_def->model = numvalue;
955 } else if (!strcmp(featurestr, "stepping")) {
956 char *err;
957 numvalue = strtoul(val, &err, 0);
958 if (!*val || *err || numvalue > 0xf) {
959 fprintf(stderr, "bad numerical value %s\n", val);
960 goto error;
961 }
962 x86_cpu_def->stepping = numvalue ;
963 } else if (!strcmp(featurestr, "level")) {
964 char *err;
965 numvalue = strtoul(val, &err, 0);
966 if (!*val || *err) {
967 fprintf(stderr, "bad numerical value %s\n", val);
968 goto error;
969 }
970 x86_cpu_def->level = numvalue;
971 } else if (!strcmp(featurestr, "xlevel")) {
972 char *err;
973 numvalue = strtoul(val, &err, 0);
974 if (!*val || *err) {
975 fprintf(stderr, "bad numerical value %s\n", val);
976 goto error;
977 }
978 if (numvalue < 0x80000000) {
2f7a21c4 979 numvalue += 0x80000000;
c6dc6f63
AP		 980 }
981 x86_cpu_def->xlevel = numvalue;
982 } else if (!strcmp(featurestr, "vendor")) {
983 if (strlen(val) != 12) {
984 fprintf(stderr, "vendor string must be 12 chars long\n");
985 goto error;
986 }
987 x86_cpu_def->vendor1 = 0;
988 x86_cpu_def->vendor2 = 0;
989 x86_cpu_def->vendor3 = 0;
990 for(i = 0; i < 4; i++) {
991 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
992 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
993 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
994 }
995 x86_cpu_def->vendor_override = 1;
996 } else if (!strcmp(featurestr, "model_id")) {
997 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
998 val);
b862d1fe
JR		 999 } else if (!strcmp(featurestr, "tsc_freq")) {
1000 int64_t tsc_freq;
1001 char *err;
1002
1003 tsc_freq = strtosz_suffix_unit(val, &err,
1004 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1005 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1006 fprintf(stderr, "bad numerical value %s\n", val);
1007 goto error;
1008 }
1009 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1010 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1011 char *err;
1012 numvalue = strtoul(val, &err, 0);
1013 if (!*val || *err) {
1014 fprintf(stderr, "bad numerical value %s\n", val);
1015 goto error;
1016 }
1017 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1018 } else {
1019 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1020 goto error;
1021 }
1022 } else if (!strcmp(featurestr, "check")) {
1023 check_cpuid = 1;
1024 } else if (!strcmp(featurestr, "enforce")) {
1025 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1026 } else if (!strcmp(featurestr, "hv_relaxed")) {
1027 hyperv_enable_relaxed_timing(true);
1028 } else if (!strcmp(featurestr, "hv_vapic")) {
1029 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1030 } else {
1031 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1032 goto error;
1033 }
1034 featurestr = strtok(NULL, ",");
1035 }
1036 x86_cpu_def->features |= plus_features;
1037 x86_cpu_def->ext_features |= plus_ext_features;
1038 x86_cpu_def->ext2_features |= plus_ext2_features;
1039 x86_cpu_def->ext3_features |= plus_ext3_features;
1040 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1041 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 1042 x86_cpu_def->features &= ~minus_features;
1043 x86_cpu_def->ext_features &= ~minus_ext_features;
1044 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1045 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1046 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1047 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 1048 if (check_cpuid) {
1049 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1050 goto error;
1051 }
d3c481b3 1052 g_free(s);
c6dc6f63
AP		 1053 return 0;
1054
1055error:
d3c481b3 1056 g_free(s);
c6dc6f63
AP		 1057 return -1;
1058}
1059
1060/* generate a composite string into buf of all cpuid names in featureset
1061 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1062 * if flags, suppress names undefined in featureset.
1063 */
1064static void listflags(char *buf, int bufsize, uint32_t fbits,
1065 const char **featureset, uint32_t flags)
1066{
1067 const char **p = &featureset[31];
1068 char *q, *b, bit;
1069 int nc;
1070
1071 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1072 *buf = '\0';
1073 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1074 if (fbits & 1 << bit && (*p || !flags)) {
1075 if (*p)
1076 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1077 else
1078 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1079 if (bufsize <= nc) {
1080 if (b) {
1081 memcpy(b, "...", sizeof("..."));
1082 }
1083 return;
1084 }
1085 q += nc;
1086 bufsize -= nc;
1087 }
1088}
1089
1090/* generate CPU information:
1091 * -? list model names
1092 * -?model list model names/IDs
1093 * -?dump output all model (x86_def_t) data
1094 * -?cpuid list all recognized cpuid flag names
1095 */
9a78eead 1096void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 1097{
1098 unsigned char model = !strcmp("?model", optarg);
1099 unsigned char dump = !strcmp("?dump", optarg);
1100 unsigned char cpuid = !strcmp("?cpuid", optarg);
1101 x86_def_t *def;
1102 char buf[256];
1103
1104 if (cpuid) {
1105 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
1106 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
1107 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1108 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
1109 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1110 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
1111 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1112 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
1113 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
1114 return;
1115 }
1116 for (def = x86_defs; def; def = def->next) {
1117 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
1118 if (model || dump) {
1119 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1120 } else {
1121 (*cpu_fprintf)(f, "x86 %16s\n", buf);
1122 }
1123 if (dump) {
1124 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
1125 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
1126 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
1127 buf[12] = '\0';
1128 (*cpu_fprintf)(f,
1129 " family %d model %d stepping %d level %d xlevel 0x%x"
1130 " vendor \"%s\"\n",
1131 def->family, def->model, def->stepping, def->level,
1132 def->xlevel, buf);
1133 listflags(buf, sizeof (buf), def->features, feature_name, 0);
1134 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
1135 buf);
1136 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
1137 0);
1138 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
1139 buf);
1140 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
1141 0);
1142 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
1143 def->ext2_features, buf);
1144 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
1145 0);
1146 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
1147 def->ext3_features, buf);
1148 (*cpu_fprintf)(f, "\n");
1149 }
1150 }
ed2c54d4
AP		 1151 if (kvm_enabled()) {
1152 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1153 }
c6dc6f63
AP		 1154}
1155
61dcd775 1156int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1157{
61dcd775 1158 CPUX86State *env = &cpu->env;
c6dc6f63 1159 x86_def_t def1, *def = &def1;
71ad61d3 1160 Error *error = NULL;
c6dc6f63 1161
db0ad1ba
JR		 1162 memset(def, 0, sizeof(*def));
1163
c6dc6f63
AP		 1164 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1165 return -1;
1166 if (def->vendor1) {
1167 env->cpuid_vendor1 = def->vendor1;
1168 env->cpuid_vendor2 = def->vendor2;
1169 env->cpuid_vendor3 = def->vendor3;
1170 } else {
1171 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1172 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1173 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1174 }
1175 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1176 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1177 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1178 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1179 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1180 env->cpuid_features = def->features;
c6dc6f63
AP		 1181 env->cpuid_ext_features = def->ext_features;
1182 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1183 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1184 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1185 env->cpuid_kvm_features = def->kvm_features;
296acb64 1186 env->cpuid_svm_features = def->svm_features;
b3baa152
BW		 1187 env->cpuid_ext4_features = def->ext4_features;
1188 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1189 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1190 "tsc-frequency", &error);
551a2dec
AP		 1191 if (!kvm_enabled()) {
1192 env->cpuid_features &= TCG_FEATURES;
1193 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1194 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1195#ifdef TARGET_X86_64
1196 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1197#endif
1198 );
1199 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1200 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1201 }
938d4c25 1202 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1203 if (error_is_set(&error)) {
1204 error_free(error);
1205 return -1;
1206 }
c6dc6f63
AP		 1207 return 0;
1208}
1209
1210#if !defined(CONFIG_USER_ONLY)
1211/* copy vendor id string to 32 bit register, nul pad as needed
1212 */
1213static void cpyid(const char *s, uint32_t *id)
1214{
1215 char *d = (char *)id;
1216 char i;
1217
1218 for (i = sizeof (*id); i--; )
1219 *d++ = *s ? *s++ : '\0';
1220}
1221
1222/* interpret radix and convert from string to arbitrary scalar,
1223 * otherwise flag failure
1224 */
1225#define setscalar(pval, str, perr) \
1226{ \
1227 char *pend; \
1228 unsigned long ul; \
1229 \
1230 ul = strtoul(str, &pend, 0); \
1231 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1232}
1233
1234/* map cpuid options to feature bits, otherwise return failure
1235 * (option tags in *str are delimited by whitespace)
1236 */
1237static void setfeatures(uint32_t *pval, const char *str,
1238 const char **featureset, int *perr)
1239{
1240 const char *p, *q;
1241
1242 for (q = p = str; *p || *q; q = p) {
1243 while (iswhite(*p))
1244 q = ++p;
1245 while (*p && !iswhite(*p))
1246 ++p;
1247 if (!*q && !*p)
1248 return;
1249 if (!lookup_feature(pval, q, p, featureset)) {
1250 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1251 (int)(p - q), q);
1252 *perr = 1;
1253 return;
1254 }
1255 }
1256}
1257
1258/* map config file options to x86_def_t form
1259 */
1260static int cpudef_setfield(const char *name, const char *str, void *opaque)
1261{
1262 x86_def_t *def = opaque;
1263 int err = 0;
1264
1265 if (!strcmp(name, "name")) {
99e1dec0 1266 g_free((void *)def->name);
d3c481b3 1267 def->name = g_strdup(str);
c6dc6f63
AP		 1268 } else if (!strcmp(name, "model_id")) {
1269 strncpy(def->model_id, str, sizeof (def->model_id));
1270 } else if (!strcmp(name, "level")) {
1271 setscalar(&def->level, str, &err)
1272 } else if (!strcmp(name, "vendor")) {
1273 cpyid(&str[0], &def->vendor1);
1274 cpyid(&str[4], &def->vendor2);
1275 cpyid(&str[8], &def->vendor3);
1276 } else if (!strcmp(name, "family")) {
1277 setscalar(&def->family, str, &err)
1278 } else if (!strcmp(name, "model")) {
1279 setscalar(&def->model, str, &err)
1280 } else if (!strcmp(name, "stepping")) {
1281 setscalar(&def->stepping, str, &err)
1282 } else if (!strcmp(name, "feature_edx")) {
1283 setfeatures(&def->features, str, feature_name, &err);
1284 } else if (!strcmp(name, "feature_ecx")) {
1285 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1286 } else if (!strcmp(name, "extfeature_edx")) {
1287 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1288 } else if (!strcmp(name, "extfeature_ecx")) {
1289 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1290 } else if (!strcmp(name, "xlevel")) {
1291 setscalar(&def->xlevel, str, &err)
1292 } else {
1293 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1294 return (1);
1295 }
1296 if (err) {
1297 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1298 return (1);
1299 }
1300 return (0);
1301}
1302
1303/* register config file entry as x86_def_t
1304 */
1305static int cpudef_register(QemuOpts *opts, void *opaque)
1306{
7267c094 1307 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1308
1309 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1310 def->next = x86_defs;
1311 x86_defs = def;
1312 return (0);
1313}
0e26b7b8
BS		 1314
1315void cpu_clear_apic_feature(CPUX86State *env)
1316{
1317 env->cpuid_features &= ~CPUID_APIC;
1318}
1319
c6dc6f63
AP		 1320#endif /* !CONFIG_USER_ONLY */
1321
1322/* register "cpudef" models defined in configuration file. Here we first
1323 * preload any built-in definitions
1324 */
1325void x86_cpudef_setup(void)
1326{
1327 int i;
1328
1329 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1330 builtin_x86_defs[i].next = x86_defs;
1331 builtin_x86_defs[i].flags = 1;
1332 x86_defs = &builtin_x86_defs[i];
1333 }
1334#if !defined(CONFIG_USER_ONLY)
3329f07b 1335 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1336#endif
1337}
1338
c6dc6f63
AP		 1339static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1340 uint32_t *ecx, uint32_t *edx)
1341{
1342 *ebx = env->cpuid_vendor1;
1343 *edx = env->cpuid_vendor2;
1344 *ecx = env->cpuid_vendor3;
1345
1346 /* sysenter isn't supported on compatibility mode on AMD, syscall
1347 * isn't supported in compatibility mode on Intel.
1348 * Normally we advertise the actual cpu vendor, but you can override
1349 * this if you want to use KVM's sysenter/syscall emulation
1350 * in compatibility mode and when doing cross vendor migration
1351 */
89354998 1352 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1353 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1354 }
1355}
1356
1357void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1358 uint32_t *eax, uint32_t *ebx,
1359 uint32_t *ecx, uint32_t *edx)
1360{
1361 /* test if maximum index reached */
1362 if (index & 0x80000000) {
b3baa152
BW		 1363 if (index > env->cpuid_xlevel) {
1364 if (env->cpuid_xlevel2 > 0) {
1365 /* Handle the Centaur's CPUID instruction. */
1366 if (index > env->cpuid_xlevel2) {
1367 index = env->cpuid_xlevel2;
1368 } else if (index < 0xC0000000) {
1369 index = env->cpuid_xlevel;
1370 }
1371 } else {
1372 index = env->cpuid_xlevel;
1373 }
1374 }
c6dc6f63
AP		 1375 } else {
1376 if (index > env->cpuid_level)
1377 index = env->cpuid_level;
1378 }
1379
1380 switch(index) {
1381 case 0:
1382 *eax = env->cpuid_level;
1383 get_cpuid_vendor(env, ebx, ecx, edx);
1384 break;
1385 case 1:
1386 *eax = env->cpuid_version;
1387 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1388 *ecx = env->cpuid_ext_features;
1389 *edx = env->cpuid_features;
1390 if (env->nr_cores * env->nr_threads > 1) {
1391 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1392 *edx |= 1 << 28; /* HTT bit */
1393 }
1394 break;
1395 case 2:
1396 /* cache info: needed for Pentium Pro compatibility */
1397 *eax = 1;
1398 *ebx = 0;
1399 *ecx = 0;
1400 *edx = 0x2c307d;
1401 break;
1402 case 4:
1403 /* cache info: needed for Core compatibility */
1404 if (env->nr_cores > 1) {
2f7a21c4 1405 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1406 } else {
2f7a21c4 1407 *eax = 0;
c6dc6f63
AP		 1408 }
1409 switch (count) {
1410 case 0: /* L1 dcache info */
1411 *eax |= 0x0000121;
1412 *ebx = 0x1c0003f;
1413 *ecx = 0x000003f;
1414 *edx = 0x0000001;
1415 break;
1416 case 1: /* L1 icache info */
1417 *eax |= 0x0000122;
1418 *ebx = 0x1c0003f;
1419 *ecx = 0x000003f;
1420 *edx = 0x0000001;
1421 break;
1422 case 2: /* L2 cache info */
1423 *eax |= 0x0000143;
1424 if (env->nr_threads > 1) {
1425 *eax |= (env->nr_threads - 1) << 14;
1426 }
1427 *ebx = 0x3c0003f;
1428 *ecx = 0x0000fff;
1429 *edx = 0x0000001;
1430 break;
1431 default: /* end of info */
1432 *eax = 0;
1433 *ebx = 0;
1434 *ecx = 0;
1435 *edx = 0;
1436 break;
1437 }
1438 break;
1439 case 5:
1440 /* mwait info: needed for Core compatibility */
1441 *eax = 0; /* Smallest monitor-line size in bytes */
1442 *ebx = 0; /* Largest monitor-line size in bytes */
1443 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1444 *edx = 0;
1445 break;
1446 case 6:
1447 /* Thermal and Power Leaf */
1448 *eax = 0;
1449 *ebx = 0;
1450 *ecx = 0;
1451 *edx = 0;
1452 break;
f7911686
YW		 1453 case 7:
1454 if (kvm_enabled()) {
ba9bc59e
JK		 1455 KVMState *s = env->kvm_state;
1456
1457 *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
1458 *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
1459 *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
1460 *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
f7911686
YW		 1461 } else {
1462 *eax = 0;
1463 *ebx = 0;
1464 *ecx = 0;
1465 *edx = 0;
1466 }
1467 break;
c6dc6f63
AP		 1468 case 9:
1469 /* Direct Cache Access Information Leaf */
1470 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1471 *ebx = 0;
1472 *ecx = 0;
1473 *edx = 0;
1474 break;
1475 case 0xA:
1476 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1477 if (kvm_enabled()) {
1478 KVMState *s = env->kvm_state;
1479
1480 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1481 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1482 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1483 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1484 } else {
1485 *eax = 0;
1486 *ebx = 0;
1487 *ecx = 0;
1488 *edx = 0;
1489 }
c6dc6f63 1490 break;
51e49430
SY		 1491 case 0xD:
1492 /* Processor Extended State */
1493 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1494 *eax = 0;
1495 *ebx = 0;
1496 *ecx = 0;
1497 *edx = 0;
1498 break;
1499 }
1500 if (kvm_enabled()) {
ba9bc59e
JK		 1501 KVMState *s = env->kvm_state;
1502
1503 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1504 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1505 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1506 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1507 } else {
1508 *eax = 0;
1509 *ebx = 0;
1510 *ecx = 0;
1511 *edx = 0;
1512 }
1513 break;
c6dc6f63
AP		 1514 case 0x80000000:
1515 *eax = env->cpuid_xlevel;
1516 *ebx = env->cpuid_vendor1;
1517 *edx = env->cpuid_vendor2;
1518 *ecx = env->cpuid_vendor3;
1519 break;
1520 case 0x80000001:
1521 *eax = env->cpuid_version;
1522 *ebx = 0;
1523 *ecx = env->cpuid_ext3_features;
1524 *edx = env->cpuid_ext2_features;
1525
1526 /* The Linux kernel checks for the CMPLegacy bit and
1527 * discards multiple thread information if it is set.
1528 * So dont set it here for Intel to make Linux guests happy.
1529 */
1530 if (env->nr_cores * env->nr_threads > 1) {
1531 uint32_t tebx, tecx, tedx;
1532 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1533 if (tebx != CPUID_VENDOR_INTEL_1 ||
1534 tedx != CPUID_VENDOR_INTEL_2 ||
1535 tecx != CPUID_VENDOR_INTEL_3) {
1536 *ecx |= 1 << 1; /* CmpLegacy bit */
1537 }
1538 }
c6dc6f63
AP		 1539 break;
1540 case 0x80000002:
1541 case 0x80000003:
1542 case 0x80000004:
1543 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1544 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1545 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1546 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1547 break;
1548 case 0x80000005:
1549 /* cache info (L1 cache) */
1550 *eax = 0x01ff01ff;
1551 *ebx = 0x01ff01ff;
1552 *ecx = 0x40020140;
1553 *edx = 0x40020140;
1554 break;
1555 case 0x80000006:
1556 /* cache info (L2 cache) */
1557 *eax = 0;
1558 *ebx = 0x42004200;
1559 *ecx = 0x02008140;
1560 *edx = 0;
1561 break;
1562 case 0x80000008:
1563 /* virtual & phys address size in low 2 bytes. */
1564/* XXX: This value must match the one used in the MMU code. */
1565 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1566 /* 64 bit processor */
1567/* XXX: The physical address space is limited to 42 bits in exec.c. */
1568 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1569 } else {
1570 if (env->cpuid_features & CPUID_PSE36)
1571 *eax = 0x00000024; /* 36 bits physical */
1572 else
1573 *eax = 0x00000020; /* 32 bits physical */
1574 }
1575 *ebx = 0;
1576 *ecx = 0;
1577 *edx = 0;
1578 if (env->nr_cores * env->nr_threads > 1) {
1579 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1580 }
1581 break;
1582 case 0x8000000A:
296acb64
JR		 1583 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1584 *eax = 0x00000001; /* SVM Revision */
1585 *ebx = 0x00000010; /* nr of ASIDs */
1586 *ecx = 0;
1587 *edx = env->cpuid_svm_features; /* optional features */
1588 } else {
1589 *eax = 0;
1590 *ebx = 0;
1591 *ecx = 0;
1592 *edx = 0;
1593 }
c6dc6f63 1594 break;
b3baa152
BW		 1595 case 0xC0000000:
1596 *eax = env->cpuid_xlevel2;
1597 *ebx = 0;
1598 *ecx = 0;
1599 *edx = 0;
1600 break;
1601 case 0xC0000001:
1602 /* Support for VIA CPU's CPUID instruction */
1603 *eax = env->cpuid_version;
1604 *ebx = 0;
1605 *ecx = 0;
1606 *edx = env->cpuid_ext4_features;
1607 break;
1608 case 0xC0000002:
1609 case 0xC0000003:
1610 case 0xC0000004:
1611 /* Reserved for the future, and now filled with zero */
1612 *eax = 0;
1613 *ebx = 0;
1614 *ecx = 0;
1615 *edx = 0;
1616 break;
c6dc6f63
AP		 1617 default:
1618 /* reserved values: zero */
1619 *eax = 0;
1620 *ebx = 0;
1621 *ecx = 0;
1622 *edx = 0;
1623 break;
1624 }
1625}
5fd2087a
AF		 1626
1627/* CPUClass::reset() */
1628static void x86_cpu_reset(CPUState *s)
1629{
1630 X86CPU *cpu = X86_CPU(s);
1631 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1632 CPUX86State *env = &cpu->env;
c1958aea
AF		 1633 int i;
1634
1635 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1636 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1637 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1638 }
5fd2087a
AF		 1639
1640 xcc->parent_reset(s);
1641
c1958aea
AF		 1642
1643 memset(env, 0, offsetof(CPUX86State, breakpoints));
1644
1645 tlb_flush(env, 1);
1646
1647 env->old_exception = -1;
1648
1649 /* init to reset state */
1650
1651#ifdef CONFIG_SOFTMMU
1652 env->hflags |= HF_SOFTMMU_MASK;
1653#endif
1654 env->hflags2 |= HF2_GIF_MASK;
1655
1656 cpu_x86_update_cr0(env, 0x60000010);
1657 env->a20_mask = ~0x0;
1658 env->smbase = 0x30000;
1659
1660 env->idt.limit = 0xffff;
1661 env->gdt.limit = 0xffff;
1662 env->ldt.limit = 0xffff;
1663 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1664 env->tr.limit = 0xffff;
1665 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1666
1667 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1668 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1669 DESC_R_MASK | DESC_A_MASK);
1670 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1671 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1672 DESC_A_MASK);
1673 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1674 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1675 DESC_A_MASK);
1676 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1677 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1678 DESC_A_MASK);
1679 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1680 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1681 DESC_A_MASK);
1682 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1683 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1684 DESC_A_MASK);
1685
1686 env->eip = 0xfff0;
1687 env->regs[R_EDX] = env->cpuid_version;
1688
1689 env->eflags = 0x2;
1690
1691 /* FPU init */
1692 for (i = 0; i < 8; i++) {
1693 env->fptags[i] = 1;
1694 }
1695 env->fpuc = 0x37f;
1696
1697 env->mxcsr = 0x1f80;
1698
1699 env->pat = 0x0007040600070406ULL;
1700 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1701
1702 memset(env->dr, 0, sizeof(env->dr));
1703 env->dr[6] = DR6_FIXED_1;
1704 env->dr[7] = DR7_FIXED_1;
1705 cpu_breakpoint_remove_all(env, BP_CPU);
1706 cpu_watchpoint_remove_all(env, BP_CPU);
5fd2087a
AF		 1707}
1708
de024815
AF		 1709static void mce_init(X86CPU *cpu)
1710{
1711 CPUX86State *cenv = &cpu->env;
1712 unsigned int bank;
1713
1714 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1715 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1716 (CPUID_MCE | CPUID_MCA)) {
1717 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1718 cenv->mcg_ctl = ~(uint64_t)0;
1719 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1720 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1721 }
1722 }
1723}
1724
7a059953
AF		 1725void x86_cpu_realize(Object *obj, Error **errp)
1726{
1727 X86CPU *cpu = X86_CPU(obj);
1728
1729 mce_init(cpu);
1730 qemu_init_vcpu(&cpu->env);
1731}
1732
de024815
AF		 1733static void x86_cpu_initfn(Object *obj)
1734{
1735 X86CPU *cpu = X86_CPU(obj);
1736 CPUX86State *env = &cpu->env;
1737
1738 cpu_exec_init(env);
71ad61d3
AF		 1739
1740 object_property_add(obj, "family", "int",
95b8519d 1741 x86_cpuid_version_get_family,
71ad61d3 1742 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1743 object_property_add(obj, "model", "int",
67e30c83 1744 x86_cpuid_version_get_model,
c5291a4f 1745 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1746 object_property_add(obj, "stepping", "int",
35112e41 1747 x86_cpuid_version_get_stepping,
036e2222 1748 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1749 object_property_add(obj, "level", "int",
1750 x86_cpuid_get_level,
1751 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1752 object_property_add(obj, "xlevel", "int",
1753 x86_cpuid_get_xlevel,
1754 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 1755 object_property_add_str(obj, "vendor",
1756 x86_cpuid_get_vendor,
1757 x86_cpuid_set_vendor, NULL);
938d4c25 1758 object_property_add_str(obj, "model-id",
63e886eb 1759 x86_cpuid_get_model_id,
938d4c25 1760 x86_cpuid_set_model_id, NULL);
89e48965
AF		 1761 object_property_add(obj, "tsc-frequency", "int",
1762 x86_cpuid_get_tsc_freq,
1763 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 1764
de024815 1765 env->cpuid_apic_id = env->cpu_index;
de024815
AF		 1766}
1767
5fd2087a
AF		 1768static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1769{
1770 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1771 CPUClass *cc = CPU_CLASS(oc);
1772
1773 xcc->parent_reset = cc->reset;
1774 cc->reset = x86_cpu_reset;
1775}
1776
1777static const TypeInfo x86_cpu_type_info = {
1778 .name = TYPE_X86_CPU,
1779 .parent = TYPE_CPU,
1780 .instance_size = sizeof(X86CPU),
de024815 1781 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1782 .abstract = false,
1783 .class_size = sizeof(X86CPUClass),
1784 .class_init = x86_cpu_common_class_init,
1785};
1786
1787static void x86_cpu_register_types(void)
1788{
1789 type_register_static(&x86_cpu_type_info);
1790}
1791
1792type_init(x86_cpu_register_types)
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