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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
4c822698 | 10 | #include <linux/sched/idle.h> |
b17b0153 | 11 | #include <linux/sched/debug.h> |
29930025 | 12 | #include <linux/sched/task.h> |
68db0cf1 | 13 | #include <linux/sched/task_stack.h> |
186f4360 PG |
14 | #include <linux/init.h> |
15 | #include <linux/export.h> | |
7f424a8b | 16 | #include <linux/pm.h> |
162a688e | 17 | #include <linux/tick.h> |
9d62dcdf | 18 | #include <linux/random.h> |
7c68af6e | 19 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
20 | #include <linux/dmi.h> |
21 | #include <linux/utsname.h> | |
90e24014 RW |
22 | #include <linux/stackprotector.h> |
23 | #include <linux/tick.h> | |
24 | #include <linux/cpuidle.h> | |
61613521 | 25 | #include <trace/events/power.h> |
24f1e32c | 26 | #include <linux/hw_breakpoint.h> |
93789b32 | 27 | #include <asm/cpu.h> |
d3ec5cae | 28 | #include <asm/apic.h> |
2c1b284e | 29 | #include <asm/syscalls.h> |
7c0f6ba6 | 30 | #include <linux/uaccess.h> |
b253149b | 31 | #include <asm/mwait.h> |
78f7f1e5 | 32 | #include <asm/fpu/internal.h> |
66cb5917 | 33 | #include <asm/debugreg.h> |
90e24014 | 34 | #include <asm/nmi.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
8838eb6c | 36 | #include <asm/mce.h> |
9fda6a06 | 37 | #include <asm/vm86.h> |
7b32aead | 38 | #include <asm/switch_to.h> |
b7ffc44d | 39 | #include <asm/desc.h> |
e9ea1e7f | 40 | #include <asm/prctl.h> |
0b35aca2 | 41 | #include <asm/spec-ctrl.h> |
90e24014 | 42 | |
45046892 TG |
43 | /* |
44 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
45 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
46 | * so they are allowed to end up in the .data..cacheline_aligned | |
47 | * section. Since TSS's are completely CPU-local, we want them | |
48 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
49 | */ | |
f45e5749 | 50 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 51 | .x86_tss = { |
8c6b12e8 AL |
52 | /* |
53 | * .sp0 is only used when entering ring 0 from a lower | |
54 | * privilege level. Since the init task never runs anything | |
55 | * but ring 0 code, there is no need for a valid value here. | |
56 | * Poison it. | |
57 | */ | |
58 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
281be4ff AL |
59 | |
60 | #ifdef CONFIG_X86_64 | |
61 | /* | |
62 | * .sp1 is cpu_current_top_of_stack. The init task never | |
63 | * runs user code, but cpu_current_top_of_stack should still | |
64 | * be well defined before the first context switch. | |
65 | */ | |
66 | .sp1 = TOP_OF_INIT_STACK, | |
67 | #endif | |
68 | ||
d0a0de21 AL |
69 | #ifdef CONFIG_X86_32 |
70 | .ss0 = __KERNEL_DS, | |
71 | .ss1 = __KERNEL_CS, | |
72 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
73 | #endif | |
74 | }, | |
75 | #ifdef CONFIG_X86_32 | |
76 | /* | |
77 | * Note that the .io_bitmap member must be extra-big. This is because | |
78 | * the CPU will access an additional byte beyond the end of the IO | |
79 | * permission bitmap. The extra byte must be all 1 bits, and must | |
80 | * be within the limit. | |
81 | */ | |
82 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
83 | #endif | |
84 | }; | |
785be108 | 85 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 86 | |
b7ceaec1 AL |
87 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
88 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 89 | |
55ccf3fe SS |
90 | /* |
91 | * this gets called so that we can store lazy state into memory and copy the | |
92 | * current task into the new thread. | |
93 | */ | |
61c4628b SS |
94 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
95 | { | |
5aaeb5c0 | 96 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
97 | #ifdef CONFIG_VM86 |
98 | dst->thread.vm86 = NULL; | |
99 | #endif | |
f1853505 | 100 | |
c69e098b | 101 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 102 | } |
7f424a8b | 103 | |
389d1fb1 JF |
104 | /* |
105 | * Free current thread data structures etc.. | |
106 | */ | |
e6464694 | 107 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 108 | { |
e6464694 | 109 | struct thread_struct *t = &tsk->thread; |
250981e6 | 110 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 111 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 112 | |
250981e6 | 113 | if (bp) { |
785be108 | 114 | struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu()); |
389d1fb1 | 115 | |
389d1fb1 JF |
116 | t->io_bitmap_ptr = NULL; |
117 | clear_thread_flag(TIF_IO_BITMAP); | |
118 | /* | |
119 | * Careful, clear this in the TSS too: | |
120 | */ | |
121 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
122 | t->io_bitmap_max = 0; | |
123 | put_cpu(); | |
250981e6 | 124 | kfree(bp); |
389d1fb1 | 125 | } |
1dcc8d7b | 126 | |
9fda6a06 BG |
127 | free_vm86(t); |
128 | ||
50338615 | 129 | fpu__drop(fpu); |
389d1fb1 JF |
130 | } |
131 | ||
132 | void flush_thread(void) | |
133 | { | |
134 | struct task_struct *tsk = current; | |
135 | ||
24f1e32c | 136 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 137 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 138 | |
04c8e01d | 139 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
140 | } |
141 | ||
389d1fb1 JF |
142 | void disable_TSC(void) |
143 | { | |
144 | preempt_disable(); | |
145 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
146 | /* | |
147 | * Must flip the CPU state synchronously with | |
148 | * TIF_NOTSC in the current running context. | |
149 | */ | |
5a920155 | 150 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
151 | preempt_enable(); |
152 | } | |
153 | ||
389d1fb1 JF |
154 | static void enable_TSC(void) |
155 | { | |
156 | preempt_disable(); | |
157 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
158 | /* | |
159 | * Must flip the CPU state synchronously with | |
160 | * TIF_NOTSC in the current running context. | |
161 | */ | |
5a920155 | 162 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
163 | preempt_enable(); |
164 | } | |
165 | ||
166 | int get_tsc_mode(unsigned long adr) | |
167 | { | |
168 | unsigned int val; | |
169 | ||
170 | if (test_thread_flag(TIF_NOTSC)) | |
171 | val = PR_TSC_SIGSEGV; | |
172 | else | |
173 | val = PR_TSC_ENABLE; | |
174 | ||
175 | return put_user(val, (unsigned int __user *)adr); | |
176 | } | |
177 | ||
178 | int set_tsc_mode(unsigned int val) | |
179 | { | |
180 | if (val == PR_TSC_SIGSEGV) | |
181 | disable_TSC(); | |
182 | else if (val == PR_TSC_ENABLE) | |
183 | enable_TSC(); | |
184 | else | |
185 | return -EINVAL; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
e9ea1e7f KH |
190 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
191 | ||
192 | static void set_cpuid_faulting(bool on) | |
193 | { | |
194 | u64 msrval; | |
195 | ||
196 | msrval = this_cpu_read(msr_misc_features_shadow); | |
197 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
198 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
199 | this_cpu_write(msr_misc_features_shadow, msrval); | |
200 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
201 | } | |
202 | ||
203 | static void disable_cpuid(void) | |
204 | { | |
205 | preempt_disable(); | |
206 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
207 | /* | |
208 | * Must flip the CPU state synchronously with | |
209 | * TIF_NOCPUID in the current running context. | |
210 | */ | |
211 | set_cpuid_faulting(true); | |
212 | } | |
213 | preempt_enable(); | |
214 | } | |
215 | ||
216 | static void enable_cpuid(void) | |
217 | { | |
218 | preempt_disable(); | |
219 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
220 | /* | |
221 | * Must flip the CPU state synchronously with | |
222 | * TIF_NOCPUID in the current running context. | |
223 | */ | |
224 | set_cpuid_faulting(false); | |
225 | } | |
226 | preempt_enable(); | |
227 | } | |
228 | ||
229 | static int get_cpuid_mode(void) | |
230 | { | |
231 | return !test_thread_flag(TIF_NOCPUID); | |
232 | } | |
233 | ||
234 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
235 | { | |
236 | if (!static_cpu_has(X86_FEATURE_CPUID_FAULT)) | |
237 | return -ENODEV; | |
238 | ||
239 | if (cpuid_enabled) | |
240 | enable_cpuid(); | |
241 | else | |
242 | disable_cpuid(); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Called immediately after a successful exec. | |
249 | */ | |
250 | void arch_setup_new_exec(void) | |
251 | { | |
252 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
253 | if (test_thread_flag(TIF_NOCPUID)) | |
254 | enable_cpuid(); | |
255 | } | |
256 | ||
af8b3cd3 KH |
257 | static inline void switch_to_bitmap(struct tss_struct *tss, |
258 | struct thread_struct *prev, | |
259 | struct thread_struct *next, | |
260 | unsigned long tifp, unsigned long tifn) | |
261 | { | |
262 | if (tifn & _TIF_IO_BITMAP) { | |
263 | /* | |
264 | * Copy the relevant range of the IO bitmap. | |
265 | * Normally this is 128 bytes or less: | |
266 | */ | |
267 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
268 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
269 | /* | |
270 | * Make sure that the TSS limit is correct for the CPU | |
271 | * to notice the IO bitmap. | |
272 | */ | |
273 | refresh_tss_limit(); | |
274 | } else if (tifp & _TIF_IO_BITMAP) { | |
275 | /* | |
276 | * Clear any possible leftover bits: | |
277 | */ | |
278 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
279 | } | |
280 | } | |
281 | ||
29f068d1 TG |
282 | #ifdef CONFIG_SMP |
283 | ||
284 | struct ssb_state { | |
285 | struct ssb_state *shared_state; | |
286 | raw_spinlock_t lock; | |
287 | unsigned int disable_state; | |
288 | unsigned long local_state; | |
289 | }; | |
290 | ||
291 | #define LSTATE_SSB 0 | |
292 | ||
293 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
294 | ||
295 | void speculative_store_bypass_ht_init(void) | |
0b35aca2 | 296 | { |
29f068d1 TG |
297 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
298 | unsigned int this_cpu = smp_processor_id(); | |
299 | unsigned int cpu; | |
300 | ||
301 | st->local_state = 0; | |
302 | ||
303 | /* | |
304 | * Shared state setup happens once on the first bringup | |
305 | * of the CPU. It's not destroyed on CPU hotunplug. | |
306 | */ | |
307 | if (st->shared_state) | |
308 | return; | |
309 | ||
310 | raw_spin_lock_init(&st->lock); | |
311 | ||
312 | /* | |
313 | * Go over HT siblings and check whether one of them has set up the | |
314 | * shared state pointer already. | |
315 | */ | |
316 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
317 | if (cpu == this_cpu) | |
318 | continue; | |
319 | ||
320 | if (!per_cpu(ssb_state, cpu).shared_state) | |
321 | continue; | |
322 | ||
323 | /* Link it to the state of the sibling: */ | |
324 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
325 | return; | |
326 | } | |
327 | ||
328 | /* | |
329 | * First HT sibling to come up on the core. Link shared state of | |
330 | * the first HT sibling to itself. The siblings on the same core | |
331 | * which come up later will see the shared state pointer and link | |
332 | * themself to the state of this CPU. | |
333 | */ | |
334 | st->shared_state = st; | |
335 | } | |
0b35aca2 | 336 | |
29f068d1 TG |
337 | /* |
338 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
339 | * and last sibling to disable it, disables it for the whole core. This how | |
340 | * MSR_SPEC_CTRL works in "hardware": | |
341 | * | |
342 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
343 | */ | |
344 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
345 | { | |
346 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
347 | u64 msr = x86_amd_ls_cfg_base; | |
348 | ||
349 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
350 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
0b35aca2 | 351 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
29f068d1 TG |
352 | return; |
353 | } | |
354 | ||
355 | if (tifn & _TIF_SSBD) { | |
356 | /* | |
357 | * Since this can race with prctl(), block reentry on the | |
358 | * same CPU. | |
359 | */ | |
360 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
361 | return; | |
362 | ||
363 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
364 | ||
365 | raw_spin_lock(&st->shared_state->lock); | |
366 | /* First sibling enables SSBD: */ | |
367 | if (!st->shared_state->disable_state) | |
368 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
369 | st->shared_state->disable_state++; | |
370 | raw_spin_unlock(&st->shared_state->lock); | |
0b35aca2 | 371 | } else { |
29f068d1 TG |
372 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
373 | return; | |
374 | ||
375 | raw_spin_lock(&st->shared_state->lock); | |
376 | st->shared_state->disable_state--; | |
377 | if (!st->shared_state->disable_state) | |
378 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
379 | raw_spin_unlock(&st->shared_state->lock); | |
0b35aca2 TG |
380 | } |
381 | } | |
29f068d1 TG |
382 | #else |
383 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
384 | { | |
385 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
386 | ||
387 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
388 | } | |
389 | #endif | |
390 | ||
08e65b2a TL |
391 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
392 | { | |
393 | /* | |
394 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
395 | * so ssbd_tif_to_spec_ctrl() just works. | |
396 | */ | |
397 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
398 | } | |
399 | ||
29f068d1 TG |
400 | static __always_inline void intel_set_ssb_state(unsigned long tifn) |
401 | { | |
402 | u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn); | |
403 | ||
404 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
405 | } | |
406 | ||
407 | static __always_inline void __speculative_store_bypass_update(unsigned long tifn) | |
408 | { | |
08e65b2a TL |
409 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) |
410 | amd_set_ssb_virt_state(tifn); | |
411 | else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
29f068d1 TG |
412 | amd_set_core_ssb_state(tifn); |
413 | else | |
414 | intel_set_ssb_state(tifn); | |
415 | } | |
0b35aca2 | 416 | |
559c7a59 | 417 | void speculative_store_bypass_update(unsigned long tif) |
0b35aca2 | 418 | { |
29f068d1 | 419 | preempt_disable(); |
559c7a59 | 420 | __speculative_store_bypass_update(tif); |
29f068d1 | 421 | preempt_enable(); |
0b35aca2 TG |
422 | } |
423 | ||
389d1fb1 JF |
424 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
425 | struct tss_struct *tss) | |
426 | { | |
427 | struct thread_struct *prev, *next; | |
af8b3cd3 | 428 | unsigned long tifp, tifn; |
389d1fb1 JF |
429 | |
430 | prev = &prev_p->thread; | |
431 | next = &next_p->thread; | |
432 | ||
af8b3cd3 KH |
433 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
434 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
435 | switch_to_bitmap(tss, prev, next, tifp, tifn); | |
436 | ||
437 | propagate_user_return_notify(prev_p, next_p); | |
438 | ||
b9894a2f KH |
439 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
440 | arch_has_block_step()) { | |
441 | unsigned long debugctl, msk; | |
ea8e61b7 | 442 | |
b9894a2f | 443 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 444 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
445 | msk = tifn & _TIF_BLOCKSTEP; |
446 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
447 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 448 | } |
389d1fb1 | 449 | |
5a920155 TG |
450 | if ((tifp ^ tifn) & _TIF_NOTSC) |
451 | cr4_toggle_bits(X86_CR4_TSD); | |
e9ea1e7f KH |
452 | |
453 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
454 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
0b35aca2 | 455 | |
0c0f6741 | 456 | if ((tifp ^ tifn) & _TIF_SSBD) |
0b35aca2 | 457 | __speculative_store_bypass_update(tifn); |
389d1fb1 JF |
458 | } |
459 | ||
00dba564 TG |
460 | /* |
461 | * Idle related variables and functions | |
462 | */ | |
d1896049 | 463 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
464 | EXPORT_SYMBOL(boot_option_idle_override); |
465 | ||
a476bda3 | 466 | static void (*x86_idle)(void); |
00dba564 | 467 | |
90e24014 RW |
468 | #ifndef CONFIG_SMP |
469 | static inline void play_dead(void) | |
470 | { | |
471 | BUG(); | |
472 | } | |
473 | #endif | |
474 | ||
7d1a9417 TG |
475 | void arch_cpu_idle_enter(void) |
476 | { | |
6a369583 | 477 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 478 | local_touch_nmi(); |
7d1a9417 | 479 | } |
90e24014 | 480 | |
7d1a9417 TG |
481 | void arch_cpu_idle_dead(void) |
482 | { | |
483 | play_dead(); | |
484 | } | |
90e24014 | 485 | |
7d1a9417 TG |
486 | /* |
487 | * Called from the generic idle code. | |
488 | */ | |
489 | void arch_cpu_idle(void) | |
490 | { | |
16f8b05a | 491 | x86_idle(); |
90e24014 RW |
492 | } |
493 | ||
00dba564 | 494 | /* |
7d1a9417 | 495 | * We use this if we don't have any better idle routine.. |
00dba564 | 496 | */ |
6727ad9e | 497 | void __cpuidle default_idle(void) |
00dba564 | 498 | { |
4d0e42cc | 499 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 500 | safe_halt(); |
4d0e42cc | 501 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 502 | } |
60b8b1de | 503 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
504 | EXPORT_SYMBOL(default_idle); |
505 | #endif | |
506 | ||
6a377ddc LB |
507 | #ifdef CONFIG_XEN |
508 | bool xen_set_default_idle(void) | |
e5fd47bf | 509 | { |
a476bda3 | 510 | bool ret = !!x86_idle; |
e5fd47bf | 511 | |
a476bda3 | 512 | x86_idle = default_idle; |
e5fd47bf KRW |
513 | |
514 | return ret; | |
515 | } | |
6a377ddc | 516 | #endif |
d3ec5cae IV |
517 | void stop_this_cpu(void *dummy) |
518 | { | |
519 | local_irq_disable(); | |
520 | /* | |
521 | * Remove this CPU: | |
522 | */ | |
4f062896 | 523 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 524 | disable_local_APIC(); |
8838eb6c | 525 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 526 | |
27be4570 LB |
527 | for (;;) |
528 | halt(); | |
7f424a8b PZ |
529 | } |
530 | ||
aa276e1c | 531 | /* |
07c94a38 BP |
532 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
533 | * states (local apic timer and TSC stop). | |
aa276e1c | 534 | */ |
02c68a02 | 535 | static void amd_e400_idle(void) |
aa276e1c | 536 | { |
07c94a38 BP |
537 | /* |
538 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
539 | * gets set after static_cpu_has() places have been converted via | |
540 | * alternatives. | |
541 | */ | |
542 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
543 | default_idle(); | |
544 | return; | |
aa276e1c TG |
545 | } |
546 | ||
07c94a38 | 547 | tick_broadcast_enter(); |
aa276e1c | 548 | |
07c94a38 | 549 | default_idle(); |
0beefa20 | 550 | |
07c94a38 BP |
551 | /* |
552 | * The switch back from broadcast mode needs to be called with | |
553 | * interrupts disabled. | |
554 | */ | |
555 | local_irq_disable(); | |
556 | tick_broadcast_exit(); | |
557 | local_irq_enable(); | |
aa276e1c TG |
558 | } |
559 | ||
b253149b LB |
560 | /* |
561 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
562 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
563 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
564 | * | |
565 | * Some AMD machines are the opposite, they depend on using HALT. | |
566 | * | |
567 | * So for default C1, which is used during boot until cpuidle loads, | |
568 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
569 | */ | |
570 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
571 | { | |
572 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
573 | return 0; | |
574 | ||
08e237fa | 575 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
576 | return 0; |
577 | ||
578 | return 1; | |
579 | } | |
580 | ||
581 | /* | |
0fb0328d HR |
582 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
583 | * with interrupts enabled and no flags, which is backwards compatible with the | |
584 | * original MWAIT implementation. | |
b253149b | 585 | */ |
6727ad9e | 586 | static __cpuidle void mwait_idle(void) |
b253149b | 587 | { |
f8e617f4 | 588 | if (!current_set_polling_and_test()) { |
e43d0189 | 589 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 590 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 591 | mb(); /* quirk */ |
b253149b | 592 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 593 | mb(); /* quirk */ |
f8e617f4 | 594 | } |
b253149b | 595 | |
357b57d7 | 596 | if (ibrs_inuse) |
adae8f0d | 597 | native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
9aff3d50 | 598 | |
b253149b | 599 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
9aff3d50 | 600 | if (!need_resched()) { |
b253149b | 601 | __sti_mwait(0, 0); |
357b57d7 | 602 | if (ibrs_inuse) |
adae8f0d | 603 | native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | SPEC_CTRL_IBRS); |
9aff3d50 | 604 | } else { |
357b57d7 | 605 | if (ibrs_inuse) |
adae8f0d | 606 | native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | SPEC_CTRL_IBRS); |
b253149b | 607 | local_irq_enable(); |
9aff3d50 | 608 | } |
e43d0189 | 609 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 610 | } else { |
b253149b | 611 | local_irq_enable(); |
f8e617f4 MG |
612 | } |
613 | __current_clr_polling(); | |
b253149b LB |
614 | } |
615 | ||
148f9bb8 | 616 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 617 | { |
3e5095d1 | 618 | #ifdef CONFIG_SMP |
7d1a9417 | 619 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 620 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 621 | #endif |
7d1a9417 | 622 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
623 | return; |
624 | ||
3344ed30 | 625 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 626 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 627 | x86_idle = amd_e400_idle; |
b253149b LB |
628 | } else if (prefer_mwait_c1_over_halt(c)) { |
629 | pr_info("using mwait in idle threads\n"); | |
630 | x86_idle = mwait_idle; | |
6ddd2a27 | 631 | } else |
a476bda3 | 632 | x86_idle = default_idle; |
7f424a8b PZ |
633 | } |
634 | ||
07c94a38 | 635 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 636 | { |
07c94a38 BP |
637 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
638 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
639 | local_irq_disable(); | |
640 | tick_broadcast_force(); | |
641 | local_irq_enable(); | |
642 | } | |
30e1e6d1 RR |
643 | } |
644 | ||
e7ff3a47 TG |
645 | void __init arch_post_acpi_subsys_init(void) |
646 | { | |
647 | u32 lo, hi; | |
648 | ||
649 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
650 | return; | |
651 | ||
652 | /* | |
653 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
654 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
655 | * MSR_K8_INT_PENDING_MSG. | |
656 | */ | |
657 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
658 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
659 | return; | |
660 | ||
661 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
662 | ||
663 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
664 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
665 | pr_info("System has AMD C1E enabled\n"); | |
666 | } | |
667 | ||
7f424a8b PZ |
668 | static int __init idle_setup(char *str) |
669 | { | |
ab6bc3e3 CG |
670 | if (!str) |
671 | return -EINVAL; | |
672 | ||
7f424a8b | 673 | if (!strcmp(str, "poll")) { |
c767a54b | 674 | pr_info("using polling idle threads\n"); |
d1896049 | 675 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 676 | cpu_idle_poll_ctrl(true); |
d1896049 | 677 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
678 | /* |
679 | * When the boot option of idle=halt is added, halt is | |
680 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
681 | * won't be used again. | |
682 | * To continue to load the CPU idle driver, don't touch | |
683 | * the boot_option_idle_override. | |
684 | */ | |
a476bda3 | 685 | x86_idle = default_idle; |
d1896049 | 686 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
687 | } else if (!strcmp(str, "nomwait")) { |
688 | /* | |
689 | * If the boot option of "idle=nomwait" is added, | |
690 | * it means that mwait will be disabled for CPU C2/C3 | |
691 | * states. In such case it won't touch the variable | |
692 | * of boot_option_idle_override. | |
693 | */ | |
d1896049 | 694 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 695 | } else |
7f424a8b PZ |
696 | return -1; |
697 | ||
7f424a8b PZ |
698 | return 0; |
699 | } | |
700 | early_param("idle", idle_setup); | |
701 | ||
9d62dcdf AW |
702 | unsigned long arch_align_stack(unsigned long sp) |
703 | { | |
704 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
705 | sp -= get_random_int() % 8192; | |
706 | return sp & ~0xf; | |
707 | } | |
708 | ||
709 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
710 | { | |
9c6f0902 | 711 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
712 | } |
713 | ||
7ba78053 TG |
714 | /* |
715 | * Called from fs/proc with a reference on @p to find the function | |
716 | * which called into schedule(). This needs to be done carefully | |
717 | * because the task might wake up and we might look at a stack | |
718 | * changing under us. | |
719 | */ | |
720 | unsigned long get_wchan(struct task_struct *p) | |
721 | { | |
74327a3e | 722 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
723 | int count = 0; |
724 | ||
725 | if (!p || p == current || p->state == TASK_RUNNING) | |
726 | return 0; | |
727 | ||
74327a3e AL |
728 | if (!try_get_task_stack(p)) |
729 | return 0; | |
730 | ||
7ba78053 TG |
731 | start = (unsigned long)task_stack_page(p); |
732 | if (!start) | |
74327a3e | 733 | goto out; |
7ba78053 TG |
734 | |
735 | /* | |
736 | * Layout of the stack page: | |
737 | * | |
738 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
739 | * PADDING | |
740 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
741 | * stack | |
15f4eae7 | 742 | * ----------- bottom = start |
7ba78053 TG |
743 | * |
744 | * The tasks stack pointer points at the location where the | |
745 | * framepointer is stored. The data on the stack is: | |
746 | * ... IP FP ... IP FP | |
747 | * | |
748 | * We need to read FP and IP, so we need to adjust the upper | |
749 | * bound by another unsigned long. | |
750 | */ | |
751 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
752 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 753 | bottom = start; |
7ba78053 TG |
754 | |
755 | sp = READ_ONCE(p->thread.sp); | |
756 | if (sp < bottom || sp > top) | |
74327a3e | 757 | goto out; |
7ba78053 | 758 | |
7b32aead | 759 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
760 | do { |
761 | if (fp < bottom || fp > top) | |
74327a3e | 762 | goto out; |
f7d27c35 | 763 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
764 | if (!in_sched_functions(ip)) { |
765 | ret = ip; | |
766 | goto out; | |
767 | } | |
f7d27c35 | 768 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 769 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
770 | |
771 | out: | |
772 | put_task_stack(p); | |
773 | return ret; | |
7ba78053 | 774 | } |
b0b9b014 KH |
775 | |
776 | long do_arch_prctl_common(struct task_struct *task, int option, | |
777 | unsigned long cpuid_enabled) | |
778 | { | |
e9ea1e7f KH |
779 | switch (option) { |
780 | case ARCH_GET_CPUID: | |
781 | return get_cpuid_mode(); | |
782 | case ARCH_SET_CPUID: | |
783 | return set_cpuid_mode(task, cpuid_enabled); | |
784 | } | |
785 | ||
b0b9b014 KH |
786 | return -EINVAL; |
787 | } |