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[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
022c62cb 2#include "exec/gdbstub.h"
7b59220e 3#include "helper.h"
1de7afc9 4#include "qemu/host-utils.h"
9c17d615 5#include "sysemu/sysemu.h"
1de7afc9 6#include "qemu/bitops.h"
0b03bdfc 7
4a501606
PM		 8#ifndef CONFIG_USER_ONLY
9static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
a8170e5e 11 hwaddr *phys_ptr, int *prot,
4a501606
PM		 12 target_ulong *page_size);
13#endif
14
0ecb72a5 15static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 16{
17 int nregs;
18
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
21 if (reg < nregs) {
22 stfq_le_p(buf, env->vfp.regs[reg]);
23 return 8;
24 }
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
27 nregs += 16;
28 if (reg < nregs) {
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
31 return 16;
32 }
33 }
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
38 }
39 return 0;
40}
41
0ecb72a5 42static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 43{
44 int nregs;
45
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
47 if (reg < nregs) {
48 env->vfp.regs[reg] = ldfq_le_p(buf);
49 return 8;
50 }
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
52 nregs += 16;
53 if (reg < nregs) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
56 return 16;
57 }
58 }
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 63 }
64 return 0;
65}
66
d4e6df63
PM		 67static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
68 uint64_t *value)
69{
70 *value = CPREG_FIELD32(env, ri);
71 return 0;
72}
73
74static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
75 uint64_t value)
76{
77 CPREG_FIELD32(env, ri) = value;
78 return 0;
79}
80
721fae12
PM		 81static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
82 uint64_t *v)
83{
84 /* Raw read of a coprocessor register (as needed for migration, etc)
85 * return true on success, false if the read is impossible for some reason.
86 */
87 if (ri->type & ARM_CP_CONST) {
88 *v = ri->resetvalue;
89 } else if (ri->raw_readfn) {
90 return (ri->raw_readfn(env, ri, v) == 0);
91 } else if (ri->readfn) {
92 return (ri->readfn(env, ri, v) == 0);
93 } else {
94 if (ri->type & ARM_CP_64BIT) {
95 *v = CPREG_FIELD64(env, ri);
96 } else {
97 *v = CPREG_FIELD32(env, ri);
98 }
99 }
100 return true;
101}
102
103static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
104 int64_t v)
105{
106 /* Raw write of a coprocessor register (as needed for migration, etc).
107 * Return true on success, false if the write is impossible for some reason.
108 * Note that constant registers are treated as write-ignored; the
109 * caller should check for success by whether a readback gives the
110 * value written.
111 */
112 if (ri->type & ARM_CP_CONST) {
113 return true;
114 } else if (ri->raw_writefn) {
115 return (ri->raw_writefn(env, ri, v) == 0);
116 } else if (ri->writefn) {
117 return (ri->writefn(env, ri, v) == 0);
118 } else {
119 if (ri->type & ARM_CP_64BIT) {
120 CPREG_FIELD64(env, ri) = v;
121 } else {
122 CPREG_FIELD32(env, ri) = v;
123 }
124 }
125 return true;
126}
127
128bool write_cpustate_to_list(ARMCPU *cpu)
129{
130 /* Write the coprocessor state from cpu->env to the (index,value) list. */
131 int i;
132 bool ok = true;
133
134 for (i = 0; i < cpu->cpreg_array_len; i++) {
135 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
136 const ARMCPRegInfo *ri;
137 uint64_t v;
138 ri = get_arm_cp_reginfo(cpu, regidx);
139 if (!ri) {
140 ok = false;
141 continue;
142 }
143 if (ri->type & ARM_CP_NO_MIGRATE) {
144 continue;
145 }
146 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
147 ok = false;
148 continue;
149 }
150 cpu->cpreg_values[i] = v;
151 }
152 return ok;
153}
154
155bool write_list_to_cpustate(ARMCPU *cpu)
156{
157 int i;
158 bool ok = true;
159
160 for (i = 0; i < cpu->cpreg_array_len; i++) {
161 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
162 uint64_t v = cpu->cpreg_values[i];
163 uint64_t readback;
164 const ARMCPRegInfo *ri;
165
166 ri = get_arm_cp_reginfo(cpu, regidx);
167 if (!ri) {
168 ok = false;
169 continue;
170 }
171 if (ri->type & ARM_CP_NO_MIGRATE) {
172 continue;
173 }
174 /* Write value and confirm it reads back as written
175 * (to catch read-only registers and partially read-only
176 * registers where the incoming migration value doesn't match)
177 */
178 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
179 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
180 readback != v) {
181 ok = false;
182 }
183 }
184 return ok;
185}
186
187static void add_cpreg_to_list(gpointer key, gpointer opaque)
188{
189 ARMCPU *cpu = opaque;
190 uint64_t regidx;
191 const ARMCPRegInfo *ri;
192
193 regidx = *(uint32_t *)key;
194 ri = get_arm_cp_reginfo(cpu, regidx);
195
196 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
197 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
198 /* The value array need not be initialized at this point */
199 cpu->cpreg_array_len++;
200 }
201}
202
203static void count_cpreg(gpointer key, gpointer opaque)
204{
205 ARMCPU *cpu = opaque;
206 uint64_t regidx;
207 const ARMCPRegInfo *ri;
208
209 regidx = *(uint32_t *)key;
210 ri = get_arm_cp_reginfo(cpu, regidx);
211
212 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
213 cpu->cpreg_array_len++;
214 }
215}
216
217static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
218{
219 uint32_t aidx = *(uint32_t *)a;
220 uint32_t bidx = *(uint32_t *)b;
221
222 return aidx - bidx;
223}
224
82a3a118
PM		 225static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
226{
227 GList **plist = udata;
228
229 *plist = g_list_prepend(*plist, key);
230}
231
721fae12
PM		 232void init_cpreg_list(ARMCPU *cpu)
233{
234 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
235 * Note that we require cpreg_tuples[] to be sorted by key ID.
236 */
82a3a118 237 GList *keys = NULL;
721fae12
PM		 238 int arraylen;
239
82a3a118
PM		 240 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
241
721fae12
PM		 242 keys = g_list_sort(keys, cpreg_key_compare);
243
244 cpu->cpreg_array_len = 0;
245
246 g_list_foreach(keys, count_cpreg, cpu);
247
248 arraylen = cpu->cpreg_array_len;
249 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
250 cpu->cpreg_values = g_new(uint64_t, arraylen);
251 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
252 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
253 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
254 cpu->cpreg_array_len = 0;
255
256 g_list_foreach(keys, add_cpreg_to_list, cpu);
257
258 assert(cpu->cpreg_array_len == arraylen);
259
260 g_list_free(keys);
261}
262
c983fe6c
PM		 263static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
264{
265 env->cp15.c3 = value;
266 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
267 return 0;
268}
269
08de207b
PM		 270static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
271{
272 if (env->cp15.c13_fcse != value) {
273 /* Unlike real hardware the qemu TLB uses virtual addresses,
274 * not modified virtual addresses, so this causes a TLB flush.
275 */
276 tlb_flush(env, 1);
277 env->cp15.c13_fcse = value;
278 }
279 return 0;
280}
281static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
282 uint64_t value)
283{
284 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
285 /* For VMSA (when not using the LPAE long descriptor page table
286 * format) this register includes the ASID, so do a TLB flush.
287 * For PMSA it is purely a process ID and no action is needed.
288 */
289 tlb_flush(env, 1);
290 }
291 env->cp15.c13_context = value;
292 return 0;
293}
294
d929823f
PM		 295static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
296 uint64_t value)
297{
298 /* Invalidate all (TLBIALL) */
299 tlb_flush(env, 1);
300 return 0;
301}
302
303static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
304 uint64_t value)
305{
306 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
307 tlb_flush_page(env, value & TARGET_PAGE_MASK);
308 return 0;
309}
310
311static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
312 uint64_t value)
313{
314 /* Invalidate by ASID (TLBIASID) */
315 tlb_flush(env, value == 0);
316 return 0;
317}
318
319static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
320 uint64_t value)
321{
322 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
323 tlb_flush_page(env, value & TARGET_PAGE_MASK);
324 return 0;
325}
326
e9aa6c21
PM		 327static const ARMCPRegInfo cp_reginfo[] = {
328 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
329 * version" bits will read as a reserved value, which should cause
330 * Linux to not try to use the debug hardware.
331 */
332 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
333 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 334 /* MMU Domain access control / MPU write buffer control */
335 { .name = "DACR", .cp = 15,
336 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
337 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
d4e6df63 338 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
08de207b
PM		 339 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
340 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 341 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
08de207b
PM		 342 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
343 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 344 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
4fdd17dd
PM		 345 /* ??? This covers not just the impdef TLB lockdown registers but also
346 * some v7VMSA registers relating to TEX remap, so it is overly broad.
347 */
348 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
349 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 350 /* MMU TLB control. Note that the wildcarding means we cover not just
351 * the unified TLB ops but also the dside/iside/inner-shareable variants.
352 */
353 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 354 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
355 .type = ARM_CP_NO_MIGRATE },
d929823f 356 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 357 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
358 .type = ARM_CP_NO_MIGRATE },
d929823f 359 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 360 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
361 .type = ARM_CP_NO_MIGRATE },
d929823f 362 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 363 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
364 .type = ARM_CP_NO_MIGRATE },
c4804214
PM		 365 /* Cache maintenance ops; some of this space may be overridden later. */
366 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
367 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
368 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 369 REGINFO_SENTINEL
370};
371
7d57f408
PM		 372static const ARMCPRegInfo not_v6_cp_reginfo[] = {
373 /* Not all pre-v6 cores implemented this WFI, so this is slightly
374 * over-broad.
375 */
376 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
377 .access = PL1_W, .type = ARM_CP_WFI },
378 REGINFO_SENTINEL
379};
380
381static const ARMCPRegInfo not_v7_cp_reginfo[] = {
382 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
383 * is UNPREDICTABLE; we choose to NOP as most implementations do).
384 */
385 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
386 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 387 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
388 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
389 * OMAPCP will override this space.
390 */
391 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
392 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
393 .resetvalue = 0 },
394 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
395 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
396 .resetvalue = 0 },
776d4e5c
PM		 397 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
398 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
d4e6df63
PM		 399 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
400 .resetvalue = 0 },
7d57f408
PM		 401 REGINFO_SENTINEL
402};
403
2771db27
PM		 404static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
405{
406 if (env->cp15.c1_coproc != value) {
407 env->cp15.c1_coproc = value;
408 /* ??? Is this safe when called from within a TB? */
409 tb_flush(env);
410 }
411 return 0;
412}
413
7d57f408
PM		 414static const ARMCPRegInfo v6_cp_reginfo[] = {
415 /* prefetch by MVA in v6, NOP in v7 */
416 { .name = "MVA_prefetch",
417 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
418 .access = PL1_W, .type = ARM_CP_NOP },
419 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
420 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 421 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 422 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 423 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 424 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 425 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
426 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
427 .resetvalue = 0, },
428 /* Watchpoint Fault Address Register : should actually only be present
429 * for 1136, 1176, 11MPCore.
430 */
431 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
432 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 433 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
434 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
435 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 436 REGINFO_SENTINEL
437};
438
d4e6df63 439
200ac0ef
PM		 440static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
441 uint64_t *value)
442{
443 /* Generic performance monitor register read function for where
444 * user access may be allowed by PMUSERENR.
445 */
446 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
447 return EXCP_UDEF;
448 }
449 *value = CPREG_FIELD32(env, ri);
450 return 0;
451}
452
453static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
454 uint64_t value)
455{
456 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
457 return EXCP_UDEF;
458 }
459 /* only the DP, X, D and E bits are writable */
460 env->cp15.c9_pmcr &= ~0x39;
461 env->cp15.c9_pmcr |= (value & 0x39);
462 return 0;
463}
464
465static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
466 uint64_t value)
467{
468 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
469 return EXCP_UDEF;
470 }
471 value &= (1 << 31);
472 env->cp15.c9_pmcnten |= value;
473 return 0;
474}
475
476static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
477 uint64_t value)
478{
479 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
480 return EXCP_UDEF;
481 }
482 value &= (1 << 31);
483 env->cp15.c9_pmcnten &= ~value;
484 return 0;
485}
486
487static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
488 uint64_t value)
489{
490 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
491 return EXCP_UDEF;
492 }
493 env->cp15.c9_pmovsr &= ~value;
494 return 0;
495}
496
497static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
498 uint64_t value)
499{
500 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
501 return EXCP_UDEF;
502 }
503 env->cp15.c9_pmxevtyper = value & 0xff;
504 return 0;
505}
506
507static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
508 uint64_t value)
509{
510 env->cp15.c9_pmuserenr = value & 1;
511 return 0;
512}
513
514static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
515 uint64_t value)
516{
517 /* We have no event counters so only the C bit can be changed */
518 value &= (1 << 31);
519 env->cp15.c9_pminten |= value;
520 return 0;
521}
522
523static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
524 uint64_t value)
525{
526 value &= (1 << 31);
527 env->cp15.c9_pminten &= ~value;
528 return 0;
529}
530
776d4e5c
PM		 531static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
532 uint64_t *value)
533{
534 ARMCPU *cpu = arm_env_get_cpu(env);
535 *value = cpu->ccsidr[env->cp15.c0_cssel];
536 return 0;
537}
538
539static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
540 uint64_t value)
541{
542 env->cp15.c0_cssel = value & 0xf;
543 return 0;
544}
545
e9aa6c21
PM		 546static const ARMCPRegInfo v7_cp_reginfo[] = {
547 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
548 * debug components
549 */
550 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
551 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 552 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 553 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 554 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
555 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
556 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 557 /* Performance monitors are implementation defined in v7,
558 * but with an ARM recommended set of registers, which we
559 * follow (although we don't actually implement any counters)
560 *
561 * Performance registers fall into three categories:
562 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
563 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
564 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
565 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
566 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
567 */
568 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
569 .access = PL0_RW, .resetvalue = 0,
570 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 571 .readfn = pmreg_read, .writefn = pmcntenset_write,
572 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 573 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
574 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 575 .readfn = pmreg_read, .writefn = pmcntenclr_write,
576 .type = ARM_CP_NO_MIGRATE },
200ac0ef
PM		 577 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
578 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
d4e6df63
PM		 579 .readfn = pmreg_read, .writefn = pmovsr_write,
580 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 581 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
582 * respect PMUSERENR.
583 */
584 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
585 .access = PL0_W, .type = ARM_CP_NOP },
586 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
587 * We choose to RAZ/WI. XXX should respect PMUSERENR.
588 */
589 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
590 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
591 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
592 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
593 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
594 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
595 .access = PL0_RW,
596 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
d4e6df63
PM		 597 .readfn = pmreg_read, .writefn = pmxevtyper_write,
598 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 599 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
600 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
601 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
602 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
603 .access = PL0_R | PL1_RW,
604 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
605 .resetvalue = 0,
d4e6df63 606 .writefn = pmuserenr_write, .raw_writefn = raw_write },
200ac0ef
PM		 607 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
608 .access = PL1_RW,
609 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
610 .resetvalue = 0,
d4e6df63 611 .writefn = pmintenset_write, .raw_writefn = raw_write },
200ac0ef 612 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
d4e6df63 613 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
200ac0ef 614 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
d4e6df63 615 .resetvalue = 0, .writefn = pmintenclr_write, },
2771db27
PM		 616 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
617 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
618 .resetvalue = 0, },
776d4e5c 619 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
d4e6df63 620 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
776d4e5c
PM		 621 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
622 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
623 .writefn = csselr_write, .resetvalue = 0 },
624 /* Auxiliary ID register: this actually has an IMPDEF value but for now
625 * just RAZ for all cores:
626 */
627 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
628 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 629 REGINFO_SENTINEL
630};
631
c326b979
PM		 632static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
633{
634 value &= 1;
635 env->teecr = value;
636 return 0;
637}
638
639static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
640 uint64_t *value)
641{
642 /* This is a helper function because the user access rights
643 * depend on the value of the TEECR.
644 */
645 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
646 return EXCP_UDEF;
647 }
648 *value = env->teehbr;
649 return 0;
650}
651
652static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
653 uint64_t value)
654{
655 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
656 return EXCP_UDEF;
657 }
658 env->teehbr = value;
659 return 0;
660}
661
662static const ARMCPRegInfo t2ee_cp_reginfo[] = {
663 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
664 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
665 .resetvalue = 0,
666 .writefn = teecr_write },
667 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
668 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
d4e6df63 669 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
c326b979
PM		 670 .readfn = teehbr_read, .writefn = teehbr_write },
671 REGINFO_SENTINEL
672};
673
4d31c596
PM		 674static const ARMCPRegInfo v6k_cp_reginfo[] = {
675 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
676 .access = PL0_RW,
677 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
678 .resetvalue = 0 },
679 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
680 .access = PL0_R|PL1_W,
681 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
682 .resetvalue = 0 },
683 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
684 .access = PL1_RW,
685 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
686 .resetvalue = 0 },
687 REGINFO_SENTINEL
688};
689
6cc7a3ae
PM		 690static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
691 /* Dummy implementation: RAZ/WI the whole crn=14 space */
692 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
693 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 694 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
695 .resetvalue = 0 },
6cc7a3ae
PM		 696 REGINFO_SENTINEL
697};
698
4a501606
PM		 699static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
700{
891a2fe7
PM		 701 if (arm_feature(env, ARM_FEATURE_LPAE)) {
702 env->cp15.c7_par = value;
703 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 704 env->cp15.c7_par = value & 0xfffff6ff;
705 } else {
706 env->cp15.c7_par = value & 0xfffff1ff;
707 }
708 return 0;
709}
710
711#ifndef CONFIG_USER_ONLY
712/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 713
714/* Return true if extended addresses are enabled, ie this is an
715 * LPAE implementation and we are using the long-descriptor translation
716 * table format because the TTBCR EAE bit is set.
717 */
718static inline bool extended_addresses_enabled(CPUARMState *env)
719{
720 return arm_feature(env, ARM_FEATURE_LPAE)
721 && (env->cp15.c2_control & (1 << 31));
722}
723
4a501606
PM		 724static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
725{
a8170e5e 726 hwaddr phys_addr;
4a501606
PM		 727 target_ulong page_size;
728 int prot;
729 int ret, is_user = ri->opc2 & 2;
730 int access_type = ri->opc2 & 1;
731
732 if (ri->opc2 & 4) {
733 /* Other states are only available with TrustZone */
734 return EXCP_UDEF;
735 }
736 ret = get_phys_addr(env, value, access_type, is_user,
737 &phys_addr, &prot, &page_size);
702a9357
PM		 738 if (extended_addresses_enabled(env)) {
739 /* ret is a DFSR/IFSR value for the long descriptor
740 * translation table format, but with WnR always clear.
741 * Convert it to a 64-bit PAR.
742 */
743 uint64_t par64 = (1 << 11); /* LPAE bit always set */
744 if (ret == 0) {
745 par64 |= phys_addr & ~0xfffULL;
746 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 747 } else {
702a9357
PM		 748 par64 |= 1; /* F */
749 par64 |= (ret & 0x3f) << 1; /* FS */
750 /* Note that S2WLK and FSTAGE are always zero, because we don't
751 * implement virtualization and therefore there can't be a stage 2
752 * fault.
753 */
4a501606 754 }
702a9357
PM		 755 env->cp15.c7_par = par64;
756 env->cp15.c7_par_hi = par64 >> 32;
4a501606 757 } else {
702a9357
PM		 758 /* ret is a DFSR/IFSR value for the short descriptor
759 * translation table format (with WnR always clear).
760 * Convert it to a 32-bit PAR.
761 */
762 if (ret == 0) {
763 /* We do not set any attribute bits in the PAR */
764 if (page_size == (1 << 24)
765 && arm_feature(env, ARM_FEATURE_V7)) {
766 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
767 } else {
768 env->cp15.c7_par = phys_addr & 0xfffff000;
769 }
770 } else {
771 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
772 ((ret & (12 << 1)) >> 6) |
773 ((ret & 0xf) << 1) | 1;
774 }
775 env->cp15.c7_par_hi = 0;
4a501606
PM		 776 }
777 return 0;
778}
779#endif
780
781static const ARMCPRegInfo vapa_cp_reginfo[] = {
782 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
783 .access = PL1_RW, .resetvalue = 0,
784 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
785 .writefn = par_write },
786#ifndef CONFIG_USER_ONLY
787 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
d4e6df63 788 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
4a501606
PM		 789#endif
790 REGINFO_SENTINEL
791};
792
18032bec
PM		 793/* Return basic MPU access permission bits. */
794static uint32_t simple_mpu_ap_bits(uint32_t val)
795{
796 uint32_t ret;
797 uint32_t mask;
798 int i;
799 ret = 0;
800 mask = 3;
801 for (i = 0; i < 16; i += 2) {
802 ret |= (val >> i) & mask;
803 mask <<= 2;
804 }
805 return ret;
806}
807
808/* Pad basic MPU access permission bits to extended format. */
809static uint32_t extended_mpu_ap_bits(uint32_t val)
810{
811 uint32_t ret;
812 uint32_t mask;
813 int i;
814 ret = 0;
815 mask = 3;
816 for (i = 0; i < 16; i += 2) {
817 ret |= (val & mask) << i;
818 mask <<= 2;
819 }
820 return ret;
821}
822
823static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
824 uint64_t value)
825{
826 env->cp15.c5_data = extended_mpu_ap_bits(value);
827 return 0;
828}
829
830static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
831 uint64_t *value)
832{
833 *value = simple_mpu_ap_bits(env->cp15.c5_data);
834 return 0;
835}
836
837static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
838 uint64_t value)
839{
840 env->cp15.c5_insn = extended_mpu_ap_bits(value);
841 return 0;
842}
843
844static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
845 uint64_t *value)
846{
847 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
848 return 0;
849}
850
06d76f31
PM		 851static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
852 uint64_t *value)
853{
599d64f6 854 if (ri->crm >= 8) {
06d76f31
PM		 855 return EXCP_UDEF;
856 }
857 *value = env->cp15.c6_region[ri->crm];
858 return 0;
859}
860
861static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
862 uint64_t value)
863{
599d64f6 864 if (ri->crm >= 8) {
06d76f31
PM		 865 return EXCP_UDEF;
866 }
867 env->cp15.c6_region[ri->crm] = value;
868 return 0;
869}
870
18032bec
PM		 871static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
872 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
d4e6df63 873 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 874 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
875 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
876 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
d4e6df63 877 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 878 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
879 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
880 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
881 .access = PL1_RW,
882 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
883 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
884 .access = PL1_RW,
885 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 886 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
887 .access = PL1_RW,
888 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
889 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
890 .access = PL1_RW,
891 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 892 /* Protection region base and size registers */
893 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
894 .opc2 = CP_ANY, .access = PL1_RW,
895 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 896 REGINFO_SENTINEL
897};
898
d4e6df63
PM		 899static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
900 uint64_t value)
ecce5c3c 901{
2ebcebe2
PM		 902 int maskshift = extract32(value, 0, 3);
903
e42c4db3
PM		 904 if (arm_feature(env, ARM_FEATURE_LPAE)) {
905 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
e42c4db3
PM		 906 } else {
907 value &= 7;
908 }
909 /* Note that we always calculate c2_mask and c2_base_mask, but
910 * they are only used for short-descriptor tables (ie if EAE is 0);
911 * for long-descriptor tables the TTBCR fields are used differently
912 * and the c2_mask and c2_base_mask values are meaningless.
913 */
ecce5c3c 914 env->cp15.c2_control = value;
2ebcebe2
PM		 915 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
916 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
ecce5c3c
PM		 917 return 0;
918}
919
d4e6df63
PM		 920static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
921 uint64_t value)
922{
923 if (arm_feature(env, ARM_FEATURE_LPAE)) {
924 /* With LPAE the TTBCR could result in a change of ASID
925 * via the TTBCR.A1 bit, so do a TLB flush.
926 */
927 tlb_flush(env, 1);
928 }
929 return vmsa_ttbcr_raw_write(env, ri, value);
930}
931
ecce5c3c
PM		 932static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
933{
934 env->cp15.c2_base_mask = 0xffffc000u;
935 env->cp15.c2_control = 0;
936 env->cp15.c2_mask = 0;
937}
938
18032bec
PM		 939static const ARMCPRegInfo vmsa_cp_reginfo[] = {
940 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
941 .access = PL1_RW,
942 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
943 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
944 .access = PL1_RW,
945 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 946 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
947 .access = PL1_RW,
948 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
949 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
950 .access = PL1_RW,
81a60ada 951 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 952 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
953 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
d4e6df63 954 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
ecce5c3c 955 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 956 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
957 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
958 .resetvalue = 0, },
18032bec
PM		 959 REGINFO_SENTINEL
960};
961
1047b9d7
PM		 962static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
963 uint64_t value)
964{
965 env->cp15.c15_ticonfig = value & 0xe7;
966 /* The OS_TYPE bit in this register changes the reported CPUID! */
967 env->cp15.c0_cpuid = (value & (1 << 5)) ?
968 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
969 return 0;
970}
971
972static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
973 uint64_t value)
974{
975 env->cp15.c15_threadid = value & 0xffff;
976 return 0;
977}
978
979static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
980 uint64_t value)
981{
982 /* Wait-for-interrupt (deprecated) */
c3affe56 983 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1047b9d7
PM		 984 return 0;
985}
986
c4804214
PM		 987static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
988 uint64_t value)
989{
990 /* On OMAP there are registers indicating the max/min index of dcache lines
991 * containing a dirty line; cache flush operations have to reset these.
992 */
993 env->cp15.c15_i_max = 0x000;
994 env->cp15.c15_i_min = 0xff0;
995 return 0;
996}
997
18032bec
PM		 998static const ARMCPRegInfo omap_cp_reginfo[] = {
999 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1000 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1001 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 1002 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1003 .access = PL1_RW, .type = ARM_CP_NOP },
1004 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1005 .access = PL1_RW,
1006 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1007 .writefn = omap_ticonfig_write },
1008 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1009 .access = PL1_RW,
1010 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1011 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1012 .access = PL1_RW, .resetvalue = 0xff0,
1013 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1014 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1015 .access = PL1_RW,
1016 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1017 .writefn = omap_threadid_write },
1018 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1019 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
d4e6df63 1020 .type = ARM_CP_NO_MIGRATE,
1047b9d7
PM		 1021 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1022 /* TODO: Peripheral port remap register:
1023 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1024 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1025 * when MMU is off.
1026 */
c4804214 1027 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
d4e6df63
PM		 1028 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1029 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
c4804214 1030 .writefn = omap_cachemaint_write },
34f90529
PM		 1031 { .name = "C9", .cp = 15, .crn = 9,
1032 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1033 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 1034 REGINFO_SENTINEL
1035};
1036
1037static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1038 uint64_t value)
1039{
1040 value &= 0x3fff;
1041 if (env->cp15.c15_cpar != value) {
1042 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1043 tb_flush(env);
1044 env->cp15.c15_cpar = value;
1045 }
1046 return 0;
1047}
1048
1049static const ARMCPRegInfo xscale_cp_reginfo[] = {
1050 { .name = "XSCALE_CPAR",
1051 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1052 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1053 .writefn = xscale_cpar_write, },
2771db27
PM		 1054 { .name = "XSCALE_AUXCR",
1055 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1056 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1057 .resetvalue = 0, },
1047b9d7
PM		 1058 REGINFO_SENTINEL
1059};
1060
1061static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1062 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1063 * implementation of this implementation-defined space.
1064 * Ideally this should eventually disappear in favour of actually
1065 * implementing the correct behaviour for all cores.
1066 */
1067 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1068 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1069 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1070 .resetvalue = 0 },
18032bec
PM		 1071 REGINFO_SENTINEL
1072};
1073
c4804214
PM		 1074static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1075 /* Cache status: RAZ because we have no cache so it's always clean */
1076 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
d4e6df63
PM		 1077 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1078 .resetvalue = 0 },
c4804214
PM		 1079 REGINFO_SENTINEL
1080};
1081
1082static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1083 /* We never have a a block transfer operation in progress */
1084 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
d4e6df63
PM		 1085 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1086 .resetvalue = 0 },
30b05bba
PM		 1087 /* The cache ops themselves: these all NOP for QEMU */
1088 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1089 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1090 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1091 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1092 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1093 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1094 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1095 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1096 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1097 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1098 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1099 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 1100 REGINFO_SENTINEL
1101};
1102
1103static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1104 /* The cache test-and-clean instructions always return (1 << 30)
1105 * to indicate that there are no dirty cache lines.
1106 */
1107 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1108 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1109 .resetvalue = (1 << 30) },
c4804214 1110 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1111 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1112 .resetvalue = (1 << 30) },
c4804214
PM		 1113 REGINFO_SENTINEL
1114};
1115
34f90529
PM		 1116static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1117 /* Ignore ReadBuffer accesses */
1118 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1119 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1120 .access = PL1_RW, .resetvalue = 0,
1121 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
34f90529
PM		 1122 REGINFO_SENTINEL
1123};
1124
81bdde9d
PM		 1125static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1126 uint64_t *value)
1127{
55e5c285
AF		 1128 CPUState *cs = CPU(arm_env_get_cpu(env));
1129 uint32_t mpidr = cs->cpu_index;
81bdde9d
PM		 1130 /* We don't support setting cluster ID ([8..11])
1131 * so these bits always RAZ.
1132 */
1133 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1134 mpidr |= (1 << 31);
1135 /* Cores which are uniprocessor (non-coherent)
1136 * but still implement the MP extensions set
1137 * bit 30. (For instance, A9UP.) However we do
1138 * not currently model any of those cores.
1139 */
1140 }
1141 *value = mpidr;
1142 return 0;
1143}
1144
1145static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1146 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
d4e6df63 1147 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
81bdde9d
PM		 1148 REGINFO_SENTINEL
1149};
1150
891a2fe7
PM		 1151static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1152{
1153 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1154 return 0;
1155}
1156
1157static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1158{
1159 env->cp15.c7_par_hi = value >> 32;
1160 env->cp15.c7_par = value;
1161 return 0;
1162}
1163
1164static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1165{
1166 env->cp15.c7_par_hi = 0;
1167 env->cp15.c7_par = 0;
1168}
1169
1170static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1171 uint64_t *value)
1172{
1173 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1174 return 0;
1175}
1176
d4e6df63
PM		 1177static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1178 uint64_t value)
891a2fe7
PM		 1179{
1180 env->cp15.c2_base0_hi = value >> 32;
1181 env->cp15.c2_base0 = value;
d4e6df63
PM		 1182 return 0;
1183}
1184
1185static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1186 uint64_t value)
1187{
891a2fe7
PM		 1188 /* Writes to the 64 bit format TTBRs may change the ASID */
1189 tlb_flush(env, 1);
d4e6df63 1190 return ttbr064_raw_write(env, ri, value);
891a2fe7
PM		 1191}
1192
1193static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1194{
1195 env->cp15.c2_base0_hi = 0;
1196 env->cp15.c2_base0 = 0;
1197}
1198
1199static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1200 uint64_t *value)
1201{
1202 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1203 return 0;
1204}
1205
1206static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1207 uint64_t value)
1208{
1209 env->cp15.c2_base1_hi = value >> 32;
1210 env->cp15.c2_base1 = value;
1211 return 0;
1212}
1213
1214static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1215{
1216 env->cp15.c2_base1_hi = 0;
1217 env->cp15.c2_base1 = 0;
1218}
1219
7ac681cf 1220static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 1221 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 1222 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1223 */
1224 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1225 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1226 .resetvalue = 0 },
1227 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1228 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1229 .resetvalue = 0 },
f9fc619a
PM		 1230 /* 64 bit access versions of the (dummy) debug registers */
1231 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1232 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1233 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1234 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1235 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1236 .access = PL1_RW, .type = ARM_CP_64BIT,
1237 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1238 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1239 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
d4e6df63
PM		 1240 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1241 .resetfn = ttbr064_reset },
891a2fe7
PM		 1242 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1243 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1244 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1245 REGINFO_SENTINEL
1246};
1247
2771db27
PM		 1248static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1249{
1250 env->cp15.c1_sys = value;
1251 /* ??? Lots of these bits are not implemented. */
1252 /* This may enable/disable the MMU, so do a TLB flush. */
1253 tlb_flush(env, 1);
1254 return 0;
1255}
1256
2ceb98c0
PM		 1257void register_cp_regs_for_features(ARMCPU *cpu)
1258{
1259 /* Register all the coprocessor registers based on feature bits */
1260 CPUARMState *env = &cpu->env;
1261 if (arm_feature(env, ARM_FEATURE_M)) {
1262 /* M profile has no coprocessor registers */
1263 return;
1264 }
1265
e9aa6c21 1266 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1267 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1268 /* The ID registers all have impdef reset values */
1269 ARMCPRegInfo v6_idregs[] = {
1270 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1271 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1272 .resetvalue = cpu->id_pfr0 },
1273 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1274 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1275 .resetvalue = cpu->id_pfr1 },
1276 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1277 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1278 .resetvalue = cpu->id_dfr0 },
1279 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1280 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1281 .resetvalue = cpu->id_afr0 },
1282 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1283 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1284 .resetvalue = cpu->id_mmfr0 },
1285 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1286 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1287 .resetvalue = cpu->id_mmfr1 },
1288 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1289 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1290 .resetvalue = cpu->id_mmfr2 },
1291 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1292 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1293 .resetvalue = cpu->id_mmfr3 },
1294 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1295 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1296 .resetvalue = cpu->id_isar0 },
1297 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1298 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1299 .resetvalue = cpu->id_isar1 },
1300 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1301 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1302 .resetvalue = cpu->id_isar2 },
1303 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1304 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1305 .resetvalue = cpu->id_isar3 },
1306 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1307 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1308 .resetvalue = cpu->id_isar4 },
1309 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1310 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1311 .resetvalue = cpu->id_isar5 },
1312 /* 6..7 are as yet unallocated and must RAZ */
1313 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1314 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1315 .resetvalue = 0 },
1316 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1317 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1318 .resetvalue = 0 },
1319 REGINFO_SENTINEL
1320 };
1321 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1322 define_arm_cp_regs(cpu, v6_cp_reginfo);
1323 } else {
1324 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1325 }
4d31c596
PM		 1326 if (arm_feature(env, ARM_FEATURE_V6K)) {
1327 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1328 }
e9aa6c21 1329 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1330 /* v7 performance monitor control register: same implementor
1331 * field as main ID register, and we implement no event counters.
1332 */
1333 ARMCPRegInfo pmcr = {
1334 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1335 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1336 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
d4e6df63
PM		 1337 .readfn = pmreg_read, .writefn = pmcr_write,
1338 .raw_readfn = raw_read, .raw_writefn = raw_write,
200ac0ef 1339 };
776d4e5c
PM		 1340 ARMCPRegInfo clidr = {
1341 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1342 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1343 };
200ac0ef 1344 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1345 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1346 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1347 } else {
1348 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1349 }
18032bec
PM		 1350 if (arm_feature(env, ARM_FEATURE_MPU)) {
1351 /* These are the MPU registers prior to PMSAv6. Any new
1352 * PMSA core later than the ARM946 will require that we
1353 * implement the PMSAv6 or PMSAv7 registers, which are
1354 * completely different.
1355 */
1356 assert(!arm_feature(env, ARM_FEATURE_V6));
1357 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1358 } else {
1359 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1360 }
c326b979
PM		 1361 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1362 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1363 }
6cc7a3ae
PM		 1364 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1365 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1366 }
4a501606
PM		 1367 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1368 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1369 }
c4804214
PM		 1370 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1371 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1372 }
1373 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1374 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1375 }
1376 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1377 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1378 }
18032bec
PM		 1379 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1380 define_arm_cp_regs(cpu, omap_cp_reginfo);
1381 }
34f90529
PM		 1382 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1383 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1384 }
1047b9d7
PM		 1385 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1386 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1387 }
1388 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1389 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1390 }
7ac681cf
PM		 1391 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1392 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1393 }
7884849c
PM		 1394 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1395 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1396 * be read-only (ie write causes UNDEF exception).
1397 */
1398 {
1399 ARMCPRegInfo id_cp_reginfo[] = {
1400 /* Note that the MIDR isn't a simple constant register because
1401 * of the TI925 behaviour where writes to another register can
1402 * cause the MIDR value to change.
97ce8d61
PC		 1403 *
1404 * Unimplemented registers in the c15 0 0 0 space default to
1405 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1406 * and friends override accordingly.
7884849c
PM		 1407 */
1408 { .name = "MIDR",
97ce8d61 1409 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7884849c 1410 .access = PL1_R, .resetvalue = cpu->midr,
d4e6df63 1411 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
97ce8d61
PC		 1412 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1413 .type = ARM_CP_OVERRIDE },
7884849c
PM		 1414 { .name = "CTR",
1415 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1416 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1417 { .name = "TCMTR",
1418 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1419 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1420 { .name = "TLBTR",
1421 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1422 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1423 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1424 { .name = "DUMMY",
1425 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1426 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1427 { .name = "DUMMY",
1428 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1429 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1430 { .name = "DUMMY",
1431 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1432 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1433 { .name = "DUMMY",
1434 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1435 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1436 { .name = "DUMMY",
1437 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1438 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1439 REGINFO_SENTINEL
1440 };
1441 ARMCPRegInfo crn0_wi_reginfo = {
1442 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1443 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1444 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1445 };
1446 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1447 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1448 ARMCPRegInfo *r;
1449 /* Register the blanket "writes ignored" value first to cover the
a703eda1
PC		 1450 * whole space. Then update the specific ID registers to allow write
1451 * access, so that they ignore writes rather than causing them to
1452 * UNDEF.
7884849c
PM		 1453 */
1454 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1455 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1456 r->access = PL1_RW;
7884849c 1457 }
7884849c 1458 }
a703eda1 1459 define_arm_cp_regs(cpu, id_cp_reginfo);
7884849c
PM		 1460 }
1461
97ce8d61
PC		 1462 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1463 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1464 }
1465
2771db27
PM		 1466 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1467 ARMCPRegInfo auxcr = {
1468 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1469 .access = PL1_RW, .type = ARM_CP_CONST,
1470 .resetvalue = cpu->reset_auxcr
1471 };
1472 define_one_arm_cp_reg(cpu, &auxcr);
1473 }
1474
1475 /* Generic registers whose values depend on the implementation */
1476 {
1477 ARMCPRegInfo sctlr = {
1478 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1479 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
d4e6df63
PM		 1480 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1481 .raw_writefn = raw_write,
2771db27
PM		 1482 };
1483 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1484 /* Normally we would always end the TB on an SCTLR write, but Linux
1485 * arch/arm/mach-pxa/sleep.S expects two instructions following
1486 * an MMU enable to execute from cache. Imitate this behaviour.
1487 */
1488 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1489 }
1490 define_one_arm_cp_reg(cpu, &sctlr);
1491 }
2ceb98c0
PM		 1492}
1493
778c3a06 1494ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1495{
dec9c2d4 1496 ARMCPU *cpu;
40f137e1 1497 CPUARMState *env;
5900d6b2 1498 ObjectClass *oc;
40f137e1 1499
5900d6b2
AF		 1500 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1501 if (!oc) {
aaed909a 1502 return NULL;
777dc784 1503 }
5900d6b2 1504 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
dec9c2d4 1505 env = &cpu->env;
777dc784 1506 env->cpu_model_str = cpu_model;
14969266
AF		 1507
1508 /* TODO this should be set centrally, once possible */
1509 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
777dc784 1510
14969266
AF		 1511 return cpu;
1512}
1513
1514void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1515{
22169d41 1516 CPUState *cs = CPU(cpu);
14969266
AF		 1517 CPUARMState *env = &cpu->env;
1518
56aebc89 1519 if (arm_feature(env, ARM_FEATURE_NEON)) {
22169d41 1520 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1521 51, "arm-neon.xml", 0);
1522 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
22169d41 1523 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1524 35, "arm-vfp3.xml", 0);
1525 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
22169d41 1526 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1527 19, "arm-vfp.xml", 0);
1528 }
40f137e1
PB		 1529}
1530
777dc784
PM		 1531/* Sort alphabetically by type name, except for "any". */
1532static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1533{
777dc784
PM		 1534 ObjectClass *class_a = (ObjectClass *)a;
1535 ObjectClass *class_b = (ObjectClass *)b;
1536 const char *name_a, *name_b;
5adb4839 1537
777dc784
PM		 1538 name_a = object_class_get_name(class_a);
1539 name_b = object_class_get_name(class_b);
51492fd1 1540 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
777dc784 1541 return 1;
51492fd1 1542 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
777dc784
PM		 1543 return -1;
1544 } else {
1545 return strcmp(name_a, name_b);
5adb4839
PB		 1546 }
1547}
1548
777dc784 1549static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1550{
777dc784 1551 ObjectClass *oc = data;
92a31361 1552 CPUListState *s = user_data;
51492fd1
AF		 1553 const char *typename;
1554 char *name;
3371d272 1555
51492fd1
AF		 1556 typename = object_class_get_name(oc);
1557 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
777dc784 1558 (*s->cpu_fprintf)(s->file, " %s\n",
51492fd1
AF		 1559 name);
1560 g_free(name);
777dc784
PM		 1561}
1562
1563void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1564{
92a31361 1565 CPUListState s = {
777dc784
PM		 1566 .file = f,
1567 .cpu_fprintf = cpu_fprintf,
1568 };
1569 GSList *list;
1570
1571 list = object_class_get_list(TYPE_ARM_CPU, false);
1572 list = g_slist_sort(list, arm_cpu_list_compare);
1573 (*cpu_fprintf)(f, "Available CPUs:\n");
1574 g_slist_foreach(list, arm_cpu_list_entry, &s);
1575 g_slist_free(list);
40f137e1
PB		 1576}
1577
4b6a83fb
PM		 1578void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1579 const ARMCPRegInfo *r, void *opaque)
1580{
1581 /* Define implementations of coprocessor registers.
1582 * We store these in a hashtable because typically
1583 * there are less than 150 registers in a space which
1584 * is 16*16*16*8*8 = 262144 in size.
1585 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1586 * If a register is defined twice then the second definition is
1587 * used, so this can be used to define some generic registers and
1588 * then override them with implementation specific variations.
1589 * At least one of the original and the second definition should
1590 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1591 * against accidental use.
1592 */
1593 int crm, opc1, opc2;
1594 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1595 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1596 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1597 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1598 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1599 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1600 /* 64 bit registers have only CRm and Opc1 fields */
1601 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1602 /* Check that the register definition has enough info to handle
1603 * reads and writes if they are permitted.
1604 */
1605 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1606 if (r->access & PL3_R) {
1607 assert(r->fieldoffset || r->readfn);
1608 }
1609 if (r->access & PL3_W) {
1610 assert(r->fieldoffset || r->writefn);
1611 }
1612 }
1613 /* Bad type field probably means missing sentinel at end of reg list */
1614 assert(cptype_valid(r->type));
1615 for (crm = crmmin; crm <= crmmax; crm++) {
1616 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1617 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1618 uint32_t *key = g_new(uint32_t, 1);
1619 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1620 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1621 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
204a9c43
PC		 1622 if (opaque) {
1623 r2->opaque = opaque;
1624 }
4b6a83fb
PM		 1625 /* Make sure reginfo passed to helpers for wildcarded regs
1626 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1627 */
1628 r2->crm = crm;
1629 r2->opc1 = opc1;
1630 r2->opc2 = opc2;
7023ec7e
PM		 1631 /* By convention, for wildcarded registers only the first
1632 * entry is used for migration; the others are marked as
1633 * NO_MIGRATE so we don't try to transfer the register
1634 * multiple times. Special registers (ie NOP/WFI) are
1635 * never migratable.
1636 */
1637 if ((r->type & ARM_CP_SPECIAL) ||
1638 ((r->crm == CP_ANY) && crm != 0) ||
1639 ((r->opc1 == CP_ANY) && opc1 != 0) ||
1640 ((r->opc2 == CP_ANY) && opc2 != 0)) {
1641 r2->type |= ARM_CP_NO_MIGRATE;
1642 }
1643
4b6a83fb
PM		 1644 /* Overriding of an existing definition must be explicitly
1645 * requested.
1646 */
1647 if (!(r->type & ARM_CP_OVERRIDE)) {
1648 ARMCPRegInfo *oldreg;
1649 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1650 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1651 fprintf(stderr, "Register redefined: cp=%d %d bit "
1652 "crn=%d crm=%d opc1=%d opc2=%d, "
1653 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1654 r2->crn, r2->crm, r2->opc1, r2->opc2,
1655 oldreg->name, r2->name);
1656 assert(0);
1657 }
1658 }
1659 g_hash_table_insert(cpu->cp_regs, key, r2);
1660 }
1661 }
1662 }
1663}
1664
1665void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1666 const ARMCPRegInfo *regs, void *opaque)
1667{
1668 /* Define a whole list of registers */
1669 const ARMCPRegInfo *r;
1670 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1671 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1672 }
1673}
1674
1675const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1676{
1677 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1678}
1679
1680int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1681 uint64_t value)
1682{
1683 /* Helper coprocessor write function for write-ignore registers */
1684 return 0;
1685}
1686
1687int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1688{
1689 /* Helper coprocessor write function for read-as-zero registers */
1690 *value = 0;
1691 return 0;
1692}
1693
0ecb72a5 1694static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1695{
1696 /* Return true if it is not valid for us to switch to
1697 * this CPU mode (ie all the UNPREDICTABLE cases in
1698 * the ARM ARM CPSRWriteByInstr pseudocode).
1699 */
1700 switch (mode) {
1701 case ARM_CPU_MODE_USR:
1702 case ARM_CPU_MODE_SYS:
1703 case ARM_CPU_MODE_SVC:
1704 case ARM_CPU_MODE_ABT:
1705 case ARM_CPU_MODE_UND:
1706 case ARM_CPU_MODE_IRQ:
1707 case ARM_CPU_MODE_FIQ:
1708 return 0;
1709 default:
1710 return 1;
1711 }
1712}
1713
2f4a40e5
AZ		 1714uint32_t cpsr_read(CPUARMState *env)
1715{
1716 int ZF;
6fbe23d5
PB		 1717 ZF = (env->ZF == 0);
1718 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1719 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1720 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1721 | ((env->condexec_bits & 0xfc) << 8)
1722 | (env->GE << 16);
1723}
1724
1725void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1726{
2f4a40e5 1727 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1728 env->ZF = (~val) & CPSR_Z;
1729 env->NF = val;
2f4a40e5
AZ		 1730 env->CF = (val >> 29) & 1;
1731 env->VF = (val << 3) & 0x80000000;
1732 }
1733 if (mask & CPSR_Q)
1734 env->QF = ((val & CPSR_Q) != 0);
1735 if (mask & CPSR_T)
1736 env->thumb = ((val & CPSR_T) != 0);
1737 if (mask & CPSR_IT_0_1) {
1738 env->condexec_bits &= ~3;
1739 env->condexec_bits |= (val >> 25) & 3;
1740 }
1741 if (mask & CPSR_IT_2_7) {
1742 env->condexec_bits &= 3;
1743 env->condexec_bits |= (val >> 8) & 0xfc;
1744 }
1745 if (mask & CPSR_GE) {
1746 env->GE = (val >> 16) & 0xf;
1747 }
1748
1749 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1750 if (bad_mode_switch(env, val & CPSR_M)) {
1751 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1752 * We choose to ignore the attempt and leave the CPSR M field
1753 * untouched.
1754 */
1755 mask &= ~CPSR_M;
1756 } else {
1757 switch_mode(env, val & CPSR_M);
1758 }
2f4a40e5
AZ		 1759 }
1760 mask &= ~CACHED_CPSR_BITS;
1761 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1762}
1763
b26eefb6
PB		 1764/* Sign/zero extend */
1765uint32_t HELPER(sxtb16)(uint32_t x)
1766{
1767 uint32_t res;
1768 res = (uint16_t)(int8_t)x;
1769 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1770 return res;
1771}
1772
1773uint32_t HELPER(uxtb16)(uint32_t x)
1774{
1775 uint32_t res;
1776 res = (uint16_t)(uint8_t)x;
1777 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1778 return res;
1779}
1780
f51bbbfe
PB		 1781uint32_t HELPER(clz)(uint32_t x)
1782{
7bbcb0af 1783 return clz32(x);
f51bbbfe
PB		 1784}
1785
3670669c
PB		 1786int32_t HELPER(sdiv)(int32_t num, int32_t den)
1787{
1788 if (den == 0)
1789 return 0;
686eeb93
AJ		 1790 if (num == INT_MIN && den == -1)
1791 return INT_MIN;
3670669c
PB		 1792 return num / den;
1793}
1794
1795uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1796{
1797 if (den == 0)
1798 return 0;
1799 return num / den;
1800}
1801
1802uint32_t HELPER(rbit)(uint32_t x)
1803{
1804 x = ((x & 0xff000000) >> 24)
1805 | ((x & 0x00ff0000) >> 8)
1806 | ((x & 0x0000ff00) << 8)
1807 | ((x & 0x000000ff) << 24);
1808 x = ((x & 0xf0f0f0f0) >> 4)
1809 | ((x & 0x0f0f0f0f) << 4);
1810 x = ((x & 0x88888888) >> 3)
1811 | ((x & 0x44444444) >> 1)
1812 | ((x & 0x22222222) << 1)
1813 | ((x & 0x11111111) << 3);
1814 return x;
1815}
1816
5fafdf24 1817#if defined(CONFIG_USER_ONLY)
b5ff1b31 1818
97a8ea5a 1819void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 1820{
97a8ea5a
AF		 1821 ARMCPU *cpu = ARM_CPU(cs);
1822 CPUARMState *env = &cpu->env;
1823
b5ff1b31
FB		 1824 env->exception_index = -1;
1825}
1826
0ecb72a5 1827int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1828 int mmu_idx)
b5ff1b31
FB		 1829{
1830 if (rw == 2) {
1831 env->exception_index = EXCP_PREFETCH_ABORT;
1832 env->cp15.c6_insn = address;
1833 } else {
1834 env->exception_index = EXCP_DATA_ABORT;
1835 env->cp15.c6_data = address;
1836 }
1837 return 1;
1838}
1839
9ee6e8bb 1840/* These should probably raise undefined insn exceptions. */
0ecb72a5 1841void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1842{
1843 cpu_abort(env, "v7m_mrs %d\n", reg);
1844}
1845
0ecb72a5 1846uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1847{
1848 cpu_abort(env, "v7m_mrs %d\n", reg);
1849 return 0;
1850}
1851
0ecb72a5 1852void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1853{
1854 if (mode != ARM_CPU_MODE_USR)
1855 cpu_abort(env, "Tried to switch out of user mode\n");
1856}
1857
0ecb72a5 1858void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1859{
1860 cpu_abort(env, "banked r13 write\n");
1861}
1862
0ecb72a5 1863uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1864{
1865 cpu_abort(env, "banked r13 read\n");
1866 return 0;
1867}
1868
b5ff1b31
FB		 1869#else
1870
1871/* Map CPU modes onto saved register banks. */
494b00c7 1872int bank_number(int mode)
b5ff1b31
FB		 1873{
1874 switch (mode) {
1875 case ARM_CPU_MODE_USR:
1876 case ARM_CPU_MODE_SYS:
1877 return 0;
1878 case ARM_CPU_MODE_SVC:
1879 return 1;
1880 case ARM_CPU_MODE_ABT:
1881 return 2;
1882 case ARM_CPU_MODE_UND:
1883 return 3;
1884 case ARM_CPU_MODE_IRQ:
1885 return 4;
1886 case ARM_CPU_MODE_FIQ:
1887 return 5;
1888 }
f5206413 1889 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
b5ff1b31
FB		 1890}
1891
0ecb72a5 1892void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1893{
1894 int old_mode;
1895 int i;
1896
1897 old_mode = env->uncached_cpsr & CPSR_M;
1898 if (mode == old_mode)
1899 return;
1900
1901 if (old_mode == ARM_CPU_MODE_FIQ) {
1902 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1903 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1904 } else if (mode == ARM_CPU_MODE_FIQ) {
1905 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1906 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1907 }
1908
f5206413 1909 i = bank_number(old_mode);
b5ff1b31
FB		 1910 env->banked_r13[i] = env->regs[13];
1911 env->banked_r14[i] = env->regs[14];
1912 env->banked_spsr[i] = env->spsr;
1913
f5206413 1914 i = bank_number(mode);
b5ff1b31
FB		 1915 env->regs[13] = env->banked_r13[i];
1916 env->regs[14] = env->banked_r14[i];
1917 env->spsr = env->banked_spsr[i];
1918}
1919
9ee6e8bb
PB		 1920static void v7m_push(CPUARMState *env, uint32_t val)
1921{
1922 env->regs[13] -= 4;
1923 stl_phys(env->regs[13], val);
1924}
1925
1926static uint32_t v7m_pop(CPUARMState *env)
1927{
1928 uint32_t val;
1929 val = ldl_phys(env->regs[13]);
1930 env->regs[13] += 4;
1931 return val;
1932}
1933
1934/* Switch to V7M main or process stack pointer. */
1935static void switch_v7m_sp(CPUARMState *env, int process)
1936{
1937 uint32_t tmp;
1938 if (env->v7m.current_sp != process) {
1939 tmp = env->v7m.other_sp;
1940 env->v7m.other_sp = env->regs[13];
1941 env->regs[13] = tmp;
1942 env->v7m.current_sp = process;
1943 }
1944}
1945
1946static void do_v7m_exception_exit(CPUARMState *env)
1947{
1948 uint32_t type;
1949 uint32_t xpsr;
1950
1951 type = env->regs[15];
1952 if (env->v7m.exception != 0)
983fe826 1953 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1954
1955 /* Switch to the target stack. */
1956 switch_v7m_sp(env, (type & 4) != 0);
1957 /* Pop registers. */
1958 env->regs[0] = v7m_pop(env);
1959 env->regs[1] = v7m_pop(env);
1960 env->regs[2] = v7m_pop(env);
1961 env->regs[3] = v7m_pop(env);
1962 env->regs[12] = v7m_pop(env);
1963 env->regs[14] = v7m_pop(env);
1964 env->regs[15] = v7m_pop(env);
1965 xpsr = v7m_pop(env);
1966 xpsr_write(env, xpsr, 0xfffffdff);
1967 /* Undo stack alignment. */
1968 if (xpsr & 0x200)
1969 env->regs[13] |= 4;
1970 /* ??? The exception return type specifies Thread/Handler mode. However
1971 this is also implied by the xPSR value. Not sure what to do
1972 if there is a mismatch. */
1973 /* ??? Likewise for mismatches between the CONTROL register and the stack
1974 pointer. */
1975}
1976
e6f010cc 1977void arm_v7m_cpu_do_interrupt(CPUState *cs)
9ee6e8bb 1978{
e6f010cc
AF		 1979 ARMCPU *cpu = ARM_CPU(cs);
1980 CPUARMState *env = &cpu->env;
9ee6e8bb
PB		 1981 uint32_t xpsr = xpsr_read(env);
1982 uint32_t lr;
1983 uint32_t addr;
1984
1985 lr = 0xfffffff1;
1986 if (env->v7m.current_sp)
1987 lr |= 4;
1988 if (env->v7m.exception == 0)
1989 lr |= 8;
1990
1991 /* For exceptions we just mark as pending on the NVIC, and let that
1992 handle it. */
1993 /* TODO: Need to escalate if the current priority is higher than the
1994 one we're raising. */
1995 switch (env->exception_index) {
1996 case EXCP_UDEF:
983fe826 1997 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1998 return;
1999 case EXCP_SWI:
314e2296 2000 /* The PC already points to the next instruction. */
983fe826 2001 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 2002 return;
2003 case EXCP_PREFETCH_ABORT:
2004 case EXCP_DATA_ABORT:
983fe826 2005 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 2006 return;
2007 case EXCP_BKPT:
2ad207d4
PB		 2008 if (semihosting_enabled) {
2009 int nr;
d31dd73e 2010 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 2011 if (nr == 0xab) {
2012 env->regs[15] += 2;
2013 env->regs[0] = do_arm_semihosting(env);
2014 return;
2015 }
2016 }
983fe826 2017 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 2018 return;
2019 case EXCP_IRQ:
983fe826 2020 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 2021 break;
2022 case EXCP_EXCEPTION_EXIT:
2023 do_v7m_exception_exit(env);
2024 return;
2025 default:
2026 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2027 return; /* Never happens. Keep compiler happy. */
2028 }
2029
2030 /* Align stack pointer. */
2031 /* ??? Should only do this if Configuration Control Register
2032 STACKALIGN bit is set. */
2033 if (env->regs[13] & 4) {
ab19b0ec 2034 env->regs[13] -= 4;
9ee6e8bb
PB		 2035 xpsr |= 0x200;
2036 }
6c95676b 2037 /* Switch to the handler mode. */
9ee6e8bb
PB		 2038 v7m_push(env, xpsr);
2039 v7m_push(env, env->regs[15]);
2040 v7m_push(env, env->regs[14]);
2041 v7m_push(env, env->regs[12]);
2042 v7m_push(env, env->regs[3]);
2043 v7m_push(env, env->regs[2]);
2044 v7m_push(env, env->regs[1]);
2045 v7m_push(env, env->regs[0]);
2046 switch_v7m_sp(env, 0);
c98d174c
PM		 2047 /* Clear IT bits */
2048 env->condexec_bits = 0;
9ee6e8bb
PB		 2049 env->regs[14] = lr;
2050 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2051 env->regs[15] = addr & 0xfffffffe;
2052 env->thumb = addr & 1;
2053}
2054
b5ff1b31 2055/* Handle a CPU exception. */
97a8ea5a 2056void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 2057{
97a8ea5a
AF		 2058 ARMCPU *cpu = ARM_CPU(cs);
2059 CPUARMState *env = &cpu->env;
b5ff1b31
FB		 2060 uint32_t addr;
2061 uint32_t mask;
2062 int new_mode;
2063 uint32_t offset;
2064
e6f010cc
AF		 2065 assert(!IS_M(env));
2066
b5ff1b31
FB		 2067 /* TODO: Vectored interrupt controller. */
2068 switch (env->exception_index) {
2069 case EXCP_UDEF:
2070 new_mode = ARM_CPU_MODE_UND;
2071 addr = 0x04;
2072 mask = CPSR_I;
2073 if (env->thumb)
2074 offset = 2;
2075 else
2076 offset = 4;
2077 break;
2078 case EXCP_SWI:
8e71621f
PB		 2079 if (semihosting_enabled) {
2080 /* Check for semihosting interrupt. */
2081 if (env->thumb) {
d31dd73e
BS		 2082 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2083 & 0xff;
8e71621f 2084 } else {
d31dd73e 2085 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 2086 & 0xffffff;
8e71621f
PB		 2087 }
2088 /* Only intercept calls from privileged modes, to provide some
2089 semblance of security. */
2090 if (((mask == 0x123456 && !env->thumb)
2091 || (mask == 0xab && env->thumb))
2092 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2093 env->regs[0] = do_arm_semihosting(env);
2094 return;
2095 }
2096 }
b5ff1b31
FB		 2097 new_mode = ARM_CPU_MODE_SVC;
2098 addr = 0x08;
2099 mask = CPSR_I;
601d70b9 2100 /* The PC already points to the next instruction. */
b5ff1b31
FB		 2101 offset = 0;
2102 break;
06c949e6 2103 case EXCP_BKPT:
9ee6e8bb 2104 /* See if this is a semihosting syscall. */
2ad207d4 2105 if (env->thumb && semihosting_enabled) {
d31dd73e 2106 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 2107 if (mask == 0xab
2108 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2109 env->regs[15] += 2;
2110 env->regs[0] = do_arm_semihosting(env);
2111 return;
2112 }
2113 }
81c05daf 2114 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 2115 /* Fall through to prefetch abort. */
2116 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 2117 new_mode = ARM_CPU_MODE_ABT;
2118 addr = 0x0c;
2119 mask = CPSR_A | CPSR_I;
2120 offset = 4;
2121 break;
2122 case EXCP_DATA_ABORT:
2123 new_mode = ARM_CPU_MODE_ABT;
2124 addr = 0x10;
2125 mask = CPSR_A | CPSR_I;
2126 offset = 8;
2127 break;
2128 case EXCP_IRQ:
2129 new_mode = ARM_CPU_MODE_IRQ;
2130 addr = 0x18;
2131 /* Disable IRQ and imprecise data aborts. */
2132 mask = CPSR_A | CPSR_I;
2133 offset = 4;
2134 break;
2135 case EXCP_FIQ:
2136 new_mode = ARM_CPU_MODE_FIQ;
2137 addr = 0x1c;
2138 /* Disable FIQ, IRQ and imprecise data aborts. */
2139 mask = CPSR_A | CPSR_I | CPSR_F;
2140 offset = 4;
2141 break;
2142 default:
2143 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2144 return; /* Never happens. Keep compiler happy. */
2145 }
2146 /* High vectors. */
2147 if (env->cp15.c1_sys & (1 << 13)) {
2148 addr += 0xffff0000;
2149 }
2150 switch_mode (env, new_mode);
2151 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 2152 /* Clear IT bits. */
2153 env->condexec_bits = 0;
30a8cac1 2154 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 2155 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 2156 env->uncached_cpsr |= mask;
be5e7a76
DES		 2157 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2158 * and we should just guard the thumb mode on V4 */
2159 if (arm_feature(env, ARM_FEATURE_V4T)) {
2160 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2161 }
b5ff1b31
FB		 2162 env->regs[14] = env->regs[15] + offset;
2163 env->regs[15] = addr;
259186a7 2164 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
b5ff1b31
FB		 2165}
2166
2167/* Check section/page access permissions.
2168 Returns the page protection flags, or zero if the access is not
2169 permitted. */
0ecb72a5 2170static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 2171 int access_type, int is_user)
b5ff1b31 2172{
9ee6e8bb
PB		 2173 int prot_ro;
2174
dd4ebc2e 2175 if (domain_prot == 3) {
b5ff1b31 2176 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 2177 }
b5ff1b31 2178
9ee6e8bb
PB		 2179 if (access_type == 1)
2180 prot_ro = 0;
2181 else
2182 prot_ro = PAGE_READ;
2183
b5ff1b31
FB		 2184 switch (ap) {
2185 case 0:
78600320 2186 if (access_type == 1)
b5ff1b31
FB		 2187 return 0;
2188 switch ((env->cp15.c1_sys >> 8) & 3) {
2189 case 1:
2190 return is_user ? 0 : PAGE_READ;
2191 case 2:
2192 return PAGE_READ;
2193 default:
2194 return 0;
2195 }
2196 case 1:
2197 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2198 case 2:
2199 if (is_user)
9ee6e8bb 2200 return prot_ro;
b5ff1b31
FB		 2201 else
2202 return PAGE_READ | PAGE_WRITE;
2203 case 3:
2204 return PAGE_READ | PAGE_WRITE;
d4934d18 2205 case 4: /* Reserved. */
9ee6e8bb
PB		 2206 return 0;
2207 case 5:
2208 return is_user ? 0 : prot_ro;
2209 case 6:
2210 return prot_ro;
d4934d18 2211 case 7:
0ab06d83 2212 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 2213 return 0;
2214 return prot_ro;
b5ff1b31
FB		 2215 default:
2216 abort();
2217 }
2218}
2219
0ecb72a5 2220static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 2221{
2222 uint32_t table;
2223
2224 if (address & env->cp15.c2_mask)
2225 table = env->cp15.c2_base1 & 0xffffc000;
2226 else
2227 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2228
2229 table |= (address >> 18) & 0x3ffc;
2230 return table;
2231}
2232
0ecb72a5 2233static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2234 int is_user, hwaddr *phys_ptr,
77a71dd1 2235 int *prot, target_ulong *page_size)
b5ff1b31
FB		 2236{
2237 int code;
2238 uint32_t table;
2239 uint32_t desc;
2240 int type;
2241 int ap;
2242 int domain;
dd4ebc2e 2243 int domain_prot;
a8170e5e 2244 hwaddr phys_addr;
b5ff1b31 2245
9ee6e8bb
PB		 2246 /* Pagetable walk. */
2247 /* Lookup l1 descriptor. */
b2fa1797 2248 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2249 desc = ldl_phys(table);
2250 type = (desc & 3);
dd4ebc2e
JCD		 2251 domain = (desc >> 5) & 0x0f;
2252 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 2253 if (type == 0) {
601d70b9 2254 /* Section translation fault. */
9ee6e8bb
PB		 2255 code = 5;
2256 goto do_fault;
2257 }
dd4ebc2e 2258 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 2259 if (type == 2)
2260 code = 9; /* Section domain fault. */
2261 else
2262 code = 11; /* Page domain fault. */
2263 goto do_fault;
2264 }
2265 if (type == 2) {
2266 /* 1Mb section. */
2267 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2268 ap = (desc >> 10) & 3;
2269 code = 13;
d4c430a8 2270 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2271 } else {
2272 /* Lookup l2 entry. */
2273 if (type == 1) {
2274 /* Coarse pagetable. */
2275 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2276 } else {
2277 /* Fine pagetable. */
2278 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2279 }
2280 desc = ldl_phys(table);
2281 switch (desc & 3) {
2282 case 0: /* Page translation fault. */
2283 code = 7;
2284 goto do_fault;
2285 case 1: /* 64k page. */
2286 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2287 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2288 *page_size = 0x10000;
ce819861 2289 break;
9ee6e8bb
PB		 2290 case 2: /* 4k page. */
2291 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2292 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2293 *page_size = 0x1000;
ce819861 2294 break;
9ee6e8bb
PB		 2295 case 3: /* 1k page. */
2296 if (type == 1) {
2297 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2298 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2299 } else {
2300 /* Page translation fault. */
2301 code = 7;
2302 goto do_fault;
2303 }
2304 } else {
2305 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2306 }
2307 ap = (desc >> 4) & 3;
d4c430a8 2308 *page_size = 0x400;
ce819861
PB		 2309 break;
2310 default:
9ee6e8bb
PB		 2311 /* Never happens, but compiler isn't smart enough to tell. */
2312 abort();
ce819861 2313 }
9ee6e8bb
PB		 2314 code = 15;
2315 }
dd4ebc2e 2316 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2317 if (!*prot) {
2318 /* Access permission fault. */
2319 goto do_fault;
2320 }
3ad493fc 2321 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2322 *phys_ptr = phys_addr;
2323 return 0;
2324do_fault:
2325 return code | (domain << 4);
2326}
2327
0ecb72a5 2328static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2329 int is_user, hwaddr *phys_ptr,
77a71dd1 2330 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2331{
2332 int code;
2333 uint32_t table;
2334 uint32_t desc;
2335 uint32_t xn;
de9b05b8 2336 uint32_t pxn = 0;
9ee6e8bb
PB		 2337 int type;
2338 int ap;
de9b05b8 2339 int domain = 0;
dd4ebc2e 2340 int domain_prot;
a8170e5e 2341 hwaddr phys_addr;
9ee6e8bb
PB		 2342
2343 /* Pagetable walk. */
2344 /* Lookup l1 descriptor. */
b2fa1797 2345 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2346 desc = ldl_phys(table);
2347 type = (desc & 3);
de9b05b8
PM		 2348 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2349 /* Section translation fault, or attempt to use the encoding
2350 * which is Reserved on implementations without PXN.
2351 */
9ee6e8bb 2352 code = 5;
9ee6e8bb 2353 goto do_fault;
de9b05b8
PM		 2354 }
2355 if ((type == 1) || !(desc & (1 << 18))) {
2356 /* Page or Section. */
dd4ebc2e 2357 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2358 }
dd4ebc2e
JCD		 2359 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2360 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2361 if (type != 1) {
9ee6e8bb 2362 code = 9; /* Section domain fault. */
de9b05b8 2363 } else {
9ee6e8bb 2364 code = 11; /* Page domain fault. */
de9b05b8 2365 }
9ee6e8bb
PB		 2366 goto do_fault;
2367 }
de9b05b8 2368 if (type != 1) {
9ee6e8bb
PB		 2369 if (desc & (1 << 18)) {
2370 /* Supersection. */
2371 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2372 *page_size = 0x1000000;
b5ff1b31 2373 } else {
9ee6e8bb
PB		 2374 /* Section. */
2375 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2376 *page_size = 0x100000;
b5ff1b31 2377 }
9ee6e8bb
PB		 2378 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2379 xn = desc & (1 << 4);
de9b05b8 2380 pxn = desc & 1;
9ee6e8bb
PB		 2381 code = 13;
2382 } else {
de9b05b8
PM		 2383 if (arm_feature(env, ARM_FEATURE_PXN)) {
2384 pxn = (desc >> 2) & 1;
2385 }
9ee6e8bb
PB		 2386 /* Lookup l2 entry. */
2387 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2388 desc = ldl_phys(table);
2389 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2390 switch (desc & 3) {
2391 case 0: /* Page translation fault. */
2392 code = 7;
b5ff1b31 2393 goto do_fault;
9ee6e8bb
PB		 2394 case 1: /* 64k page. */
2395 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2396 xn = desc & (1 << 15);
d4c430a8 2397 *page_size = 0x10000;
9ee6e8bb
PB		 2398 break;
2399 case 2: case 3: /* 4k page. */
2400 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2401 xn = desc & 1;
d4c430a8 2402 *page_size = 0x1000;
9ee6e8bb
PB		 2403 break;
2404 default:
2405 /* Never happens, but compiler isn't smart enough to tell. */
2406 abort();
b5ff1b31 2407 }
9ee6e8bb
PB		 2408 code = 15;
2409 }
dd4ebc2e 2410 if (domain_prot == 3) {
c0034328
JR		 2411 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2412 } else {
de9b05b8
PM		 2413 if (pxn && !is_user) {
2414 xn = 1;
2415 }
c0034328
JR		 2416 if (xn && access_type == 2)
2417 goto do_fault;
9ee6e8bb 2418
c0034328
JR		 2419 /* The simplified model uses AP[0] as an access control bit. */
2420 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2421 /* Access flag fault. */
2422 code = (code == 15) ? 6 : 3;
2423 goto do_fault;
2424 }
dd4ebc2e 2425 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2426 if (!*prot) {
2427 /* Access permission fault. */
2428 goto do_fault;
2429 }
2430 if (!xn) {
2431 *prot |= PAGE_EXEC;
2432 }
3ad493fc 2433 }
9ee6e8bb 2434 *phys_ptr = phys_addr;
b5ff1b31
FB		 2435 return 0;
2436do_fault:
2437 return code | (domain << 4);
2438}
2439
3dde962f
PM		 2440/* Fault type for long-descriptor MMU fault reporting; this corresponds
2441 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2442 */
2443typedef enum {
2444 translation_fault = 1,
2445 access_fault = 2,
2446 permission_fault = 3,
2447} MMUFaultType;
2448
2449static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2450 int access_type, int is_user,
a8170e5e 2451 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 2452 target_ulong *page_size_ptr)
2453{
2454 /* Read an LPAE long-descriptor translation table. */
2455 MMUFaultType fault_type = translation_fault;
2456 uint32_t level = 1;
2457 uint32_t epd;
2458 uint32_t tsz;
2459 uint64_t ttbr;
2460 int ttbr_select;
2461 int n;
a8170e5e 2462 hwaddr descaddr;
3dde962f
PM		 2463 uint32_t tableattrs;
2464 target_ulong page_size;
2465 uint32_t attrs;
2466
2467 /* Determine whether this address is in the region controlled by
2468 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2469 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2470 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2471 */
2472 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2473 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2474 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2475 /* there is a ttbr0 region and we are in it (high bits all zero) */
2476 ttbr_select = 0;
2477 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2478 /* there is a ttbr1 region and we are in it (high bits all one) */
2479 ttbr_select = 1;
2480 } else if (!t0sz) {
2481 /* ttbr0 region is "everything not in the ttbr1 region" */
2482 ttbr_select = 0;
2483 } else if (!t1sz) {
2484 /* ttbr1 region is "everything not in the ttbr0 region" */
2485 ttbr_select = 1;
2486 } else {
2487 /* in the gap between the two regions, this is a Translation fault */
2488 fault_type = translation_fault;
2489 goto do_fault;
2490 }
2491
2492 /* Note that QEMU ignores shareability and cacheability attributes,
2493 * so we don't need to do anything with the SH, ORGN, IRGN fields
2494 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2495 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2496 * implement any ASID-like capability so we can ignore it (instead
2497 * we will always flush the TLB any time the ASID is changed).
2498 */
2499 if (ttbr_select == 0) {
2500 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2501 epd = extract32(env->cp15.c2_control, 7, 1);
2502 tsz = t0sz;
2503 } else {
2504 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2505 epd = extract32(env->cp15.c2_control, 23, 1);
2506 tsz = t1sz;
2507 }
2508
2509 if (epd) {
2510 /* Translation table walk disabled => Translation fault on TLB miss */
2511 goto do_fault;
2512 }
2513
2514 /* If the region is small enough we will skip straight to a 2nd level
2515 * lookup. This affects the number of bits of the address used in
2516 * combination with the TTBR to find the first descriptor. ('n' here
2517 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2518 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2519 */
2520 if (tsz > 1) {
2521 level = 2;
2522 n = 14 - tsz;
2523 } else {
2524 n = 5 - tsz;
2525 }
2526
2527 /* Clear the vaddr bits which aren't part of the within-region address,
2528 * so that we don't have to special case things when calculating the
2529 * first descriptor address.
2530 */
2531 address &= (0xffffffffU >> tsz);
2532
2533 /* Now we can extract the actual base address from the TTBR */
2534 descaddr = extract64(ttbr, 0, 40);
2535 descaddr &= ~((1ULL << n) - 1);
2536
2537 tableattrs = 0;
2538 for (;;) {
2539 uint64_t descriptor;
2540
2541 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2542 descriptor = ldq_phys(descaddr);
2543 if (!(descriptor & 1) ||
2544 (!(descriptor & 2) && (level == 3))) {
2545 /* Invalid, or the Reserved level 3 encoding */
2546 goto do_fault;
2547 }
2548 descaddr = descriptor & 0xfffffff000ULL;
2549
2550 if ((descriptor & 2) && (level < 3)) {
2551 /* Table entry. The top five bits are attributes which may
2552 * propagate down through lower levels of the table (and
2553 * which are all arranged so that 0 means "no effect", so
2554 * we can gather them up by ORing in the bits at each level).
2555 */
2556 tableattrs |= extract64(descriptor, 59, 5);
2557 level++;
2558 continue;
2559 }
2560 /* Block entry at level 1 or 2, or page entry at level 3.
2561 * These are basically the same thing, although the number
2562 * of bits we pull in from the vaddr varies.
2563 */
2564 page_size = (1 << (39 - (9 * level)));
2565 descaddr |= (address & (page_size - 1));
2566 /* Extract attributes from the descriptor and merge with table attrs */
2567 attrs = extract64(descriptor, 2, 10)
2568 | (extract64(descriptor, 52, 12) << 10);
2569 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2570 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2571 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2572 * means "force PL1 access only", which means forcing AP[1] to 0.
2573 */
2574 if (extract32(tableattrs, 2, 1)) {
2575 attrs &= ~(1 << 4);
2576 }
2577 /* Since we're always in the Non-secure state, NSTable is ignored. */
2578 break;
2579 }
2580 /* Here descaddr is the final physical address, and attributes
2581 * are all in attrs.
2582 */
2583 fault_type = access_fault;
2584 if ((attrs & (1 << 8)) == 0) {
2585 /* Access flag */
2586 goto do_fault;
2587 }
2588 fault_type = permission_fault;
2589 if (is_user && !(attrs & (1 << 4))) {
2590 /* Unprivileged access not enabled */
2591 goto do_fault;
2592 }
2593 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2594 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2595 /* XN or PXN */
2596 if (access_type == 2) {
2597 goto do_fault;
2598 }
2599 *prot &= ~PAGE_EXEC;
2600 }
2601 if (attrs & (1 << 5)) {
2602 /* Write access forbidden */
2603 if (access_type == 1) {
2604 goto do_fault;
2605 }
2606 *prot &= ~PAGE_WRITE;
2607 }
2608
2609 *phys_ptr = descaddr;
2610 *page_size_ptr = page_size;
2611 return 0;
2612
2613do_fault:
2614 /* Long-descriptor format IFSR/DFSR value */
2615 return (1 << 9) | (fault_type << 2) | level;
2616}
2617
77a71dd1
PM		 2618static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2619 int access_type, int is_user,
a8170e5e 2620 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 2621{
2622 int n;
2623 uint32_t mask;
2624 uint32_t base;
2625
2626 *phys_ptr = address;
2627 for (n = 7; n >= 0; n--) {
2628 base = env->cp15.c6_region[n];
2629 if ((base & 1) == 0)
2630 continue;
2631 mask = 1 << ((base >> 1) & 0x1f);
2632 /* Keep this shift separate from the above to avoid an
2633 (undefined) << 32. */
2634 mask = (mask << 1) - 1;
2635 if (((base ^ address) & ~mask) == 0)
2636 break;
2637 }
2638 if (n < 0)
2639 return 2;
2640
2641 if (access_type == 2) {
2642 mask = env->cp15.c5_insn;
2643 } else {
2644 mask = env->cp15.c5_data;
2645 }
2646 mask = (mask >> (n * 4)) & 0xf;
2647 switch (mask) {
2648 case 0:
2649 return 1;
2650 case 1:
2651 if (is_user)
2652 return 1;
2653 *prot = PAGE_READ | PAGE_WRITE;
2654 break;
2655 case 2:
2656 *prot = PAGE_READ;
2657 if (!is_user)
2658 *prot |= PAGE_WRITE;
2659 break;
2660 case 3:
2661 *prot = PAGE_READ | PAGE_WRITE;
2662 break;
2663 case 5:
2664 if (is_user)
2665 return 1;
2666 *prot = PAGE_READ;
2667 break;
2668 case 6:
2669 *prot = PAGE_READ;
2670 break;
2671 default:
2672 /* Bad permission. */
2673 return 1;
2674 }
3ad493fc 2675 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2676 return 0;
2677}
2678
702a9357
PM		 2679/* get_phys_addr - get the physical address for this virtual address
2680 *
2681 * Find the physical address corresponding to the given virtual address,
2682 * by doing a translation table walk on MMU based systems or using the
2683 * MPU state on MPU based systems.
2684 *
2685 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2686 * prot and page_size are not filled in, and the return value provides
2687 * information on why the translation aborted, in the format of a
2688 * DFSR/IFSR fault register, with the following caveats:
2689 * * we honour the short vs long DFSR format differences.
2690 * * the WnR bit is never set (the caller must do this).
2691 * * for MPU based systems we don't bother to return a full FSR format
2692 * value.
2693 *
2694 * @env: CPUARMState
2695 * @address: virtual address to get physical address for
2696 * @access_type: 0 for read, 1 for write, 2 for execute
2697 * @is_user: 0 for privileged access, 1 for user
2698 * @phys_ptr: set to the physical address corresponding to the virtual address
2699 * @prot: set to the permissions for the page containing phys_ptr
2700 * @page_size: set to the size of the page containing phys_ptr
2701 */
0ecb72a5 2702static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2703 int access_type, int is_user,
a8170e5e 2704 hwaddr *phys_ptr, int *prot,
d4c430a8 2705 target_ulong *page_size)
9ee6e8bb
PB		 2706{
2707 /* Fast Context Switch Extension. */
2708 if (address < 0x02000000)
2709 address += env->cp15.c13_fcse;
2710
2711 if ((env->cp15.c1_sys & 1) == 0) {
2712 /* MMU/MPU disabled. */
2713 *phys_ptr = address;
3ad493fc 2714 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2715 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2716 return 0;
2717 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2718 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2719 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2720 prot);
3dde962f
PM		 2721 } else if (extended_addresses_enabled(env)) {
2722 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2723 prot, page_size);
9ee6e8bb
PB		 2724 } else if (env->cp15.c1_sys & (1 << 23)) {
2725 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2726 prot, page_size);
9ee6e8bb
PB		 2727 } else {
2728 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2729 prot, page_size);
9ee6e8bb
PB		 2730 }
2731}
2732
0ecb72a5 2733int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2734 int access_type, int mmu_idx)
b5ff1b31 2735{
a8170e5e 2736 hwaddr phys_addr;
d4c430a8 2737 target_ulong page_size;
b5ff1b31 2738 int prot;
6ebbf390 2739 int ret, is_user;
b5ff1b31 2740
6ebbf390 2741 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2742 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2743 &page_size);
b5ff1b31
FB		 2744 if (ret == 0) {
2745 /* Map a single [sub]page. */
a8170e5e 2746 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 2747 address &= ~(uint32_t)0x3ff;
3ad493fc 2748 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2749 return 0;
b5ff1b31
FB		 2750 }
2751
2752 if (access_type == 2) {
2753 env->cp15.c5_insn = ret;
2754 env->cp15.c6_insn = address;
2755 env->exception_index = EXCP_PREFETCH_ABORT;
2756 } else {
2757 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2758 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2759 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2760 env->cp15.c6_data = address;
2761 env->exception_index = EXCP_DATA_ABORT;
2762 }
2763 return 1;
2764}
2765
00b941e5 2766hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
b5ff1b31 2767{
00b941e5 2768 ARMCPU *cpu = ARM_CPU(cs);
a8170e5e 2769 hwaddr phys_addr;
d4c430a8 2770 target_ulong page_size;
b5ff1b31
FB		 2771 int prot;
2772 int ret;
2773
00b941e5 2774 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31 2775
00b941e5 2776 if (ret != 0) {
b5ff1b31 2777 return -1;
00b941e5 2778 }
b5ff1b31
FB		 2779
2780 return phys_addr;
2781}
2782
0ecb72a5 2783void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2784{
39ea3d4e
PM		 2785 if ((env->uncached_cpsr & CPSR_M) == mode) {
2786 env->regs[13] = val;
2787 } else {
f5206413 2788 env->banked_r13[bank_number(mode)] = val;
39ea3d4e 2789 }
9ee6e8bb
PB		 2790}
2791
0ecb72a5 2792uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2793{
39ea3d4e
PM		 2794 if ((env->uncached_cpsr & CPSR_M) == mode) {
2795 return env->regs[13];
2796 } else {
f5206413 2797 return env->banked_r13[bank_number(mode)];
39ea3d4e 2798 }
9ee6e8bb
PB		 2799}
2800
0ecb72a5 2801uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2802{
2803 switch (reg) {
2804 case 0: /* APSR */
2805 return xpsr_read(env) & 0xf8000000;
2806 case 1: /* IAPSR */
2807 return xpsr_read(env) & 0xf80001ff;
2808 case 2: /* EAPSR */
2809 return xpsr_read(env) & 0xff00fc00;
2810 case 3: /* xPSR */
2811 return xpsr_read(env) & 0xff00fdff;
2812 case 5: /* IPSR */
2813 return xpsr_read(env) & 0x000001ff;
2814 case 6: /* EPSR */
2815 return xpsr_read(env) & 0x0700fc00;
2816 case 7: /* IEPSR */
2817 return xpsr_read(env) & 0x0700edff;
2818 case 8: /* MSP */
2819 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2820 case 9: /* PSP */
2821 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2822 case 16: /* PRIMASK */
2823 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2824 case 17: /* BASEPRI */
2825 case 18: /* BASEPRI_MAX */
9ee6e8bb 2826 return env->v7m.basepri;
82845826
SH		 2827 case 19: /* FAULTMASK */
2828 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2829 case 20: /* CONTROL */
2830 return env->v7m.control;
2831 default:
2832 /* ??? For debugging only. */
2833 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2834 return 0;
2835 }
2836}
2837
0ecb72a5 2838void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2839{
2840 switch (reg) {
2841 case 0: /* APSR */
2842 xpsr_write(env, val, 0xf8000000);
2843 break;
2844 case 1: /* IAPSR */
2845 xpsr_write(env, val, 0xf8000000);
2846 break;
2847 case 2: /* EAPSR */
2848 xpsr_write(env, val, 0xfe00fc00);
2849 break;
2850 case 3: /* xPSR */
2851 xpsr_write(env, val, 0xfe00fc00);
2852 break;
2853 case 5: /* IPSR */
2854 /* IPSR bits are readonly. */
2855 break;
2856 case 6: /* EPSR */
2857 xpsr_write(env, val, 0x0600fc00);
2858 break;
2859 case 7: /* IEPSR */
2860 xpsr_write(env, val, 0x0600fc00);
2861 break;
2862 case 8: /* MSP */
2863 if (env->v7m.current_sp)
2864 env->v7m.other_sp = val;
2865 else
2866 env->regs[13] = val;
2867 break;
2868 case 9: /* PSP */
2869 if (env->v7m.current_sp)
2870 env->regs[13] = val;
2871 else
2872 env->v7m.other_sp = val;
2873 break;
2874 case 16: /* PRIMASK */
2875 if (val & 1)
2876 env->uncached_cpsr |= CPSR_I;
2877 else
2878 env->uncached_cpsr &= ~CPSR_I;
2879 break;
82845826 2880 case 17: /* BASEPRI */
9ee6e8bb
PB		 2881 env->v7m.basepri = val & 0xff;
2882 break;
82845826 2883 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2884 val &= 0xff;
2885 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2886 env->v7m.basepri = val;
2887 break;
82845826
SH		 2888 case 19: /* FAULTMASK */
2889 if (val & 1)
2890 env->uncached_cpsr |= CPSR_F;
2891 else
2892 env->uncached_cpsr &= ~CPSR_F;
2893 break;
9ee6e8bb
PB		 2894 case 20: /* CONTROL */
2895 env->v7m.control = val & 3;
2896 switch_v7m_sp(env, (val & 2) != 0);
2897 break;
2898 default:
2899 /* ??? For debugging only. */
2900 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2901 return;
2902 }
2903}
2904
b5ff1b31 2905#endif
6ddbc6e4
PB		 2906
2907/* Note that signed overflow is undefined in C. The following routines are
2908 careful to use unsigned types where modulo arithmetic is required.
2909 Failure to do so _will_ break on newer gcc. */
2910
2911/* Signed saturating arithmetic. */
2912
1654b2d6 2913/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2914static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2915{
2916 uint16_t res;
2917
2918 res = a + b;
2919 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2920 if (a & 0x8000)
2921 res = 0x8000;
2922 else
2923 res = 0x7fff;
2924 }
2925 return res;
2926}
2927
1654b2d6 2928/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2929static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2930{
2931 uint8_t res;
2932
2933 res = a + b;
2934 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2935 if (a & 0x80)
2936 res = 0x80;
2937 else
2938 res = 0x7f;
2939 }
2940 return res;
2941}
2942
1654b2d6 2943/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2944static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2945{
2946 uint16_t res;
2947
2948 res = a - b;
2949 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2950 if (a & 0x8000)
2951 res = 0x8000;
2952 else
2953 res = 0x7fff;
2954 }
2955 return res;
2956}
2957
1654b2d6 2958/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2959static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2960{
2961 uint8_t res;
2962
2963 res = a - b;
2964 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2965 if (a & 0x80)
2966 res = 0x80;
2967 else
2968 res = 0x7f;
2969 }
2970 return res;
2971}
2972
2973#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2974#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2975#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2976#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2977#define PFX q
2978
2979#include "op_addsub.h"
2980
2981/* Unsigned saturating arithmetic. */
460a09c1 2982static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2983{
2984 uint16_t res;
2985 res = a + b;
2986 if (res < a)
2987 res = 0xffff;
2988 return res;
2989}
2990
460a09c1 2991static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2992{
4c4fd3f8 2993 if (a > b)
6ddbc6e4
PB		 2994 return a - b;
2995 else
2996 return 0;
2997}
2998
2999static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3000{
3001 uint8_t res;
3002 res = a + b;
3003 if (res < a)
3004 res = 0xff;
3005 return res;
3006}
3007
3008static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3009{
4c4fd3f8 3010 if (a > b)
6ddbc6e4
PB		 3011 return a - b;
3012 else
3013 return 0;
3014}
3015
3016#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3017#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3018#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3019#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3020#define PFX uq
3021
3022#include "op_addsub.h"
3023
3024/* Signed modulo arithmetic. */
3025#define SARITH16(a, b, n, op) do { \
3026 int32_t sum; \
db6e2e65 3027 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 3028 RESULT(sum, n, 16); \
3029 if (sum >= 0) \
3030 ge |= 3 << (n * 2); \
3031 } while(0)
3032
3033#define SARITH8(a, b, n, op) do { \
3034 int32_t sum; \
db6e2e65 3035 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 3036 RESULT(sum, n, 8); \
3037 if (sum >= 0) \
3038 ge |= 1 << n; \
3039 } while(0)
3040
3041
3042#define ADD16(a, b, n) SARITH16(a, b, n, +)
3043#define SUB16(a, b, n) SARITH16(a, b, n, -)
3044#define ADD8(a, b, n) SARITH8(a, b, n, +)
3045#define SUB8(a, b, n) SARITH8(a, b, n, -)
3046#define PFX s
3047#define ARITH_GE
3048
3049#include "op_addsub.h"
3050
3051/* Unsigned modulo arithmetic. */
3052#define ADD16(a, b, n) do { \
3053 uint32_t sum; \
3054 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3055 RESULT(sum, n, 16); \
a87aa10b 3056 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 3057 ge |= 3 << (n * 2); \
3058 } while(0)
3059
3060#define ADD8(a, b, n) do { \
3061 uint32_t sum; \
3062 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3063 RESULT(sum, n, 8); \
a87aa10b
AZ		 3064 if ((sum >> 8) == 1) \
3065 ge |= 1 << n; \
6ddbc6e4
PB		 3066 } while(0)
3067
3068#define SUB16(a, b, n) do { \
3069 uint32_t sum; \
3070 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3071 RESULT(sum, n, 16); \
3072 if ((sum >> 16) == 0) \
3073 ge |= 3 << (n * 2); \
3074 } while(0)
3075
3076#define SUB8(a, b, n) do { \
3077 uint32_t sum; \
3078 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3079 RESULT(sum, n, 8); \
3080 if ((sum >> 8) == 0) \
a87aa10b 3081 ge |= 1 << n; \
6ddbc6e4
PB		 3082 } while(0)
3083
3084#define PFX u
3085#define ARITH_GE
3086
3087#include "op_addsub.h"
3088
3089/* Halved signed arithmetic. */
3090#define ADD16(a, b, n) \
3091 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3092#define SUB16(a, b, n) \
3093 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3094#define ADD8(a, b, n) \
3095 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3096#define SUB8(a, b, n) \
3097 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3098#define PFX sh
3099
3100#include "op_addsub.h"
3101
3102/* Halved unsigned arithmetic. */
3103#define ADD16(a, b, n) \
3104 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3105#define SUB16(a, b, n) \
3106 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3107#define ADD8(a, b, n) \
3108 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3109#define SUB8(a, b, n) \
3110 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3111#define PFX uh
3112
3113#include "op_addsub.h"
3114
3115static inline uint8_t do_usad(uint8_t a, uint8_t b)
3116{
3117 if (a > b)
3118 return a - b;
3119 else
3120 return b - a;
3121}
3122
3123/* Unsigned sum of absolute byte differences. */
3124uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3125{
3126 uint32_t sum;
3127 sum = do_usad(a, b);
3128 sum += do_usad(a >> 8, b >> 8);
3129 sum += do_usad(a >> 16, b >>16);
3130 sum += do_usad(a >> 24, b >> 24);
3131 return sum;
3132}
3133
3134/* For ARMv6 SEL instruction. */
3135uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3136{
3137 uint32_t mask;
3138
3139 mask = 0;
3140 if (flags & 1)
3141 mask |= 0xff;
3142 if (flags & 2)
3143 mask |= 0xff00;
3144 if (flags & 4)
3145 mask |= 0xff0000;
3146 if (flags & 8)
3147 mask |= 0xff000000;
3148 return (a & mask) | (b & ~mask);
3149}
3150
b90372ad
PM		 3151/* VFP support. We follow the convention used for VFP instructions:
3152 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 3153 "d" suffix. */
3154
3155/* Convert host exception flags to vfp form. */
3156static inline int vfp_exceptbits_from_host(int host_bits)
3157{
3158 int target_bits = 0;
3159
3160 if (host_bits & float_flag_invalid)
3161 target_bits |= 1;
3162 if (host_bits & float_flag_divbyzero)
3163 target_bits |= 2;
3164 if (host_bits & float_flag_overflow)
3165 target_bits |= 4;
36802b6b 3166 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 3167 target_bits |= 8;
3168 if (host_bits & float_flag_inexact)
3169 target_bits |= 0x10;
cecd8504
PM		 3170 if (host_bits & float_flag_input_denormal)
3171 target_bits |= 0x80;
4373f3ce
PB		 3172 return target_bits;
3173}
3174
0ecb72a5 3175uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 3176{
3177 int i;
3178 uint32_t fpscr;
3179
3180 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3181 | (env->vfp.vec_len << 16)
3182 | (env->vfp.vec_stride << 20);
3183 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 3184 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 3185 fpscr |= vfp_exceptbits_from_host(i);
3186 return fpscr;
3187}
3188
0ecb72a5 3189uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 3190{
3191 return HELPER(vfp_get_fpscr)(env);
3192}
3193
4373f3ce
PB		 3194/* Convert vfp exception flags to target form. */
3195static inline int vfp_exceptbits_to_host(int target_bits)
3196{
3197 int host_bits = 0;
3198
3199 if (target_bits & 1)
3200 host_bits |= float_flag_invalid;
3201 if (target_bits & 2)
3202 host_bits |= float_flag_divbyzero;
3203 if (target_bits & 4)
3204 host_bits |= float_flag_overflow;
3205 if (target_bits & 8)
3206 host_bits |= float_flag_underflow;
3207 if (target_bits & 0x10)
3208 host_bits |= float_flag_inexact;
cecd8504
PM		 3209 if (target_bits & 0x80)
3210 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 3211 return host_bits;
3212}
3213
0ecb72a5 3214void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 3215{
3216 int i;
3217 uint32_t changed;
3218
3219 changed = env->vfp.xregs[ARM_VFP_FPSCR];
3220 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3221 env->vfp.vec_len = (val >> 16) & 7;
3222 env->vfp.vec_stride = (val >> 20) & 3;
3223
3224 changed ^= val;
3225 if (changed & (3 << 22)) {
3226 i = (val >> 22) & 3;
3227 switch (i) {
3228 case 0:
3229 i = float_round_nearest_even;
3230 break;
3231 case 1:
3232 i = float_round_up;
3233 break;
3234 case 2:
3235 i = float_round_down;
3236 break;
3237 case 3:
3238 i = float_round_to_zero;
3239 break;
3240 }
3241 set_float_rounding_mode(i, &env->vfp.fp_status);
3242 }
cecd8504 3243 if (changed & (1 << 24)) {
fe76d976 3244 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 3245 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3246 }
5c7908ed
PB		 3247 if (changed & (1 << 25))
3248 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 3249
b12c390b 3250 i = vfp_exceptbits_to_host(val);
4373f3ce 3251 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 3252 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 3253}
3254
0ecb72a5 3255void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 3256{
3257 HELPER(vfp_set_fpscr)(env, val);
3258}
3259
4373f3ce
PB		 3260#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3261
3262#define VFP_BINOP(name) \
ae1857ec 3263float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3264{ \
ae1857ec
PM		 3265 float_status *fpst = fpstp; \
3266 return float32_ ## name(a, b, fpst); \
4373f3ce 3267} \
ae1857ec 3268float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3269{ \
ae1857ec
PM		 3270 float_status *fpst = fpstp; \
3271 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3272}
3273VFP_BINOP(add)
3274VFP_BINOP(sub)
3275VFP_BINOP(mul)
3276VFP_BINOP(div)
3277#undef VFP_BINOP
3278
3279float32 VFP_HELPER(neg, s)(float32 a)
3280{
3281 return float32_chs(a);
3282}
3283
3284float64 VFP_HELPER(neg, d)(float64 a)
3285{
66230e0d 3286 return float64_chs(a);
4373f3ce
PB		 3287}
3288
3289float32 VFP_HELPER(abs, s)(float32 a)
3290{
3291 return float32_abs(a);
3292}
3293
3294float64 VFP_HELPER(abs, d)(float64 a)
3295{
66230e0d 3296 return float64_abs(a);
4373f3ce
PB		 3297}
3298
0ecb72a5 3299float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3300{
3301 return float32_sqrt(a, &env->vfp.fp_status);
3302}
3303
0ecb72a5 3304float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3305{
3306 return float64_sqrt(a, &env->vfp.fp_status);
3307}
3308
3309/* XXX: check quiet/signaling case */
3310#define DO_VFP_cmp(p, type) \
0ecb72a5 3311void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3312{ \
3313 uint32_t flags; \
3314 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3315 case 0: flags = 0x6; break; \
3316 case -1: flags = 0x8; break; \
3317 case 1: flags = 0x2; break; \
3318 default: case 2: flags = 0x3; break; \
3319 } \
3320 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3321 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3322} \
0ecb72a5 3323void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3324{ \
3325 uint32_t flags; \
3326 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3327 case 0: flags = 0x6; break; \
3328 case -1: flags = 0x8; break; \
3329 case 1: flags = 0x2; break; \
3330 default: case 2: flags = 0x3; break; \
3331 } \
3332 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3333 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3334}
3335DO_VFP_cmp(s, float32)
3336DO_VFP_cmp(d, float64)
3337#undef DO_VFP_cmp
3338
5500b06c 3339/* Integer to float and float to integer conversions */
4373f3ce 3340
5500b06c
PM		 3341#define CONV_ITOF(name, fsz, sign) \
3342 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3343{ \
3344 float_status *fpst = fpstp; \
85836979 3345 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3346}
3347
5500b06c
PM		 3348#define CONV_FTOI(name, fsz, sign, round) \
3349uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3350{ \
3351 float_status *fpst = fpstp; \
3352 if (float##fsz##_is_any_nan(x)) { \
3353 float_raise(float_flag_invalid, fpst); \
3354 return 0; \
3355 } \
3356 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3357}
3358
5500b06c
PM		 3359#define FLOAT_CONVS(name, p, fsz, sign) \
3360CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3361CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3362CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3363
5500b06c
PM		 3364FLOAT_CONVS(si, s, 32, )
3365FLOAT_CONVS(si, d, 64, )
3366FLOAT_CONVS(ui, s, 32, u)
3367FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3368
5500b06c
PM		 3369#undef CONV_ITOF
3370#undef CONV_FTOI
3371#undef FLOAT_CONVS
4373f3ce
PB		 3372
3373/* floating point conversion */
0ecb72a5 3374float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3375{
2d627737
PM		 3376 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3377 /* ARM requires that S<->D conversion of any kind of NaN generates
3378 * a quiet NaN by forcing the most significant frac bit to 1.
3379 */
3380 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3381}
3382
0ecb72a5 3383float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3384{
2d627737
PM		 3385 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3386 /* ARM requires that S<->D conversion of any kind of NaN generates
3387 * a quiet NaN by forcing the most significant frac bit to 1.
3388 */
3389 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3390}
3391
3392/* VFP3 fixed point conversion. */
622465e1 3393#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 3394float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3395 void *fpstp) \
4373f3ce 3396{ \
5500b06c 3397 float_status *fpst = fpstp; \
622465e1 3398 float##fsz tmp; \
5500b06c
PM		 3399 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3400 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 3401} \
5500b06c
PM		 3402uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3403 void *fpstp) \
4373f3ce 3404{ \
5500b06c 3405 float_status *fpst = fpstp; \
622465e1
PM		 3406 float##fsz tmp; \
3407 if (float##fsz##_is_any_nan(x)) { \
5500b06c 3408 float_raise(float_flag_invalid, fpst); \
622465e1 3409 return 0; \
09d9487f 3410 } \
5500b06c
PM		 3411 tmp = float##fsz##_scalbn(x, shift, fpst); \
3412 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 3413}
3414
3415VFP_CONV_FIX(sh, d, 64, int16, )
3416VFP_CONV_FIX(sl, d, 64, int32, )
3417VFP_CONV_FIX(uh, d, 64, uint16, u)
3418VFP_CONV_FIX(ul, d, 64, uint32, u)
3419VFP_CONV_FIX(sh, s, 32, int16, )
3420VFP_CONV_FIX(sl, s, 32, int32, )
3421VFP_CONV_FIX(uh, s, 32, uint16, u)
3422VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 3423#undef VFP_CONV_FIX
3424
60011498 3425/* Half precision conversions. */
0ecb72a5 3426static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 3427{
60011498 3428 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3429 float32 r = float16_to_float32(make_float16(a), ieee, s);
3430 if (ieee) {
3431 return float32_maybe_silence_nan(r);
3432 }
3433 return r;
60011498
PB		 3434}
3435
0ecb72a5 3436static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 3437{
60011498 3438 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3439 float16 r = float32_to_float16(a, ieee, s);
3440 if (ieee) {
3441 r = float16_maybe_silence_nan(r);
3442 }
3443 return float16_val(r);
60011498
PB		 3444}
3445
0ecb72a5 3446float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3447{
3448 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3449}
3450
0ecb72a5 3451uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3452{
3453 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3454}
3455
0ecb72a5 3456float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3457{
3458 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3459}
3460
0ecb72a5 3461uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3462{
3463 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3464}
3465
dda3ec49 3466#define float32_two make_float32(0x40000000)
6aae3df1
PM		 3467#define float32_three make_float32(0x40400000)
3468#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 3469
0ecb72a5 3470float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3471{
dda3ec49
PM		 3472 float_status *s = &env->vfp.standard_fp_status;
3473 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3474 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3475 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3476 float_raise(float_flag_input_denormal, s);
3477 }
dda3ec49
PM		 3478 return float32_two;
3479 }
3480 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 3481}
3482
0ecb72a5 3483float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3484{
71826966 3485 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 3486 float32 product;
3487 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3488 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3489 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3490 float_raise(float_flag_input_denormal, s);
3491 }
6aae3df1 3492 return float32_one_point_five;
9ea62f57 3493 }
6aae3df1
PM		 3494 product = float32_mul(a, b, s);
3495 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 3496}
3497
8f8e3aa4
PB		 3498/* NEON helpers. */
3499
56bf4fe2
CL		 3500/* Constants 256 and 512 are used in some helpers; we avoid relying on
3501 * int->float conversions at run-time. */
3502#define float64_256 make_float64(0x4070000000000000LL)
3503#define float64_512 make_float64(0x4080000000000000LL)
3504
fe0e4872
CL		 3505/* The algorithm that must be used to calculate the estimate
3506 * is specified by the ARM ARM.
3507 */
0ecb72a5 3508static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 3509{
1146a817
PM		 3510 /* These calculations mustn't set any fp exception flags,
3511 * so we use a local copy of the fp_status.
3512 */
3513 float_status dummy_status = env->vfp.standard_fp_status;
3514 float_status *s = &dummy_status;
fe0e4872
CL		 3515 /* q = (int)(a * 512.0) */
3516 float64 q = float64_mul(float64_512, a, s);
3517 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3518
3519 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3520 q = int64_to_float64(q_int, s);
3521 q = float64_add(q, float64_half, s);
3522 q = float64_div(q, float64_512, s);
3523 q = float64_div(float64_one, q, s);
3524
3525 /* s = (int)(256.0 * r + 0.5) */
3526 q = float64_mul(q, float64_256, s);
3527 q = float64_add(q, float64_half, s);
3528 q_int = float64_to_int64_round_to_zero(q, s);
3529
3530 /* return (double)s / 256.0 */
3531 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3532}
3533
0ecb72a5 3534float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 3535{
fe0e4872
CL		 3536 float_status *s = &env->vfp.standard_fp_status;
3537 float64 f64;
3538 uint32_t val32 = float32_val(a);
3539
3540 int result_exp;
3541 int a_exp = (val32 & 0x7f800000) >> 23;
3542 int sign = val32 & 0x80000000;
3543
3544 if (float32_is_any_nan(a)) {
3545 if (float32_is_signaling_nan(a)) {
3546 float_raise(float_flag_invalid, s);
3547 }
3548 return float32_default_nan;
3549 } else if (float32_is_infinity(a)) {
3550 return float32_set_sign(float32_zero, float32_is_neg(a));
3551 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3552 if (!float32_is_zero(a)) {
3553 float_raise(float_flag_input_denormal, s);
3554 }
fe0e4872
CL		 3555 float_raise(float_flag_divbyzero, s);
3556 return float32_set_sign(float32_infinity, float32_is_neg(a));
3557 } else if (a_exp >= 253) {
3558 float_raise(float_flag_underflow, s);
3559 return float32_set_sign(float32_zero, float32_is_neg(a));
3560 }
3561
3562 f64 = make_float64((0x3feULL << 52)
3563 | ((int64_t)(val32 & 0x7fffff) << 29));
3564
3565 result_exp = 253 - a_exp;
3566
3567 f64 = recip_estimate(f64, env);
3568
3569 val32 = sign
3570 | ((result_exp & 0xff) << 23)
3571 | ((float64_val(f64) >> 29) & 0x7fffff);
3572 return make_float32(val32);
4373f3ce
PB		 3573}
3574
e07be5d2
CL		 3575/* The algorithm that must be used to calculate the estimate
3576 * is specified by the ARM ARM.
3577 */
0ecb72a5 3578static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3579{
1146a817
PM		 3580 /* These calculations mustn't set any fp exception flags,
3581 * so we use a local copy of the fp_status.
3582 */
3583 float_status dummy_status = env->vfp.standard_fp_status;
3584 float_status *s = &dummy_status;
e07be5d2
CL		 3585 float64 q;
3586 int64_t q_int;
3587
3588 if (float64_lt(a, float64_half, s)) {
3589 /* range 0.25 <= a < 0.5 */
3590
3591 /* a in units of 1/512 rounded down */
3592 /* q0 = (int)(a * 512.0); */
3593 q = float64_mul(float64_512, a, s);
3594 q_int = float64_to_int64_round_to_zero(q, s);
3595
3596 /* reciprocal root r */
3597 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3598 q = int64_to_float64(q_int, s);
3599 q = float64_add(q, float64_half, s);
3600 q = float64_div(q, float64_512, s);
3601 q = float64_sqrt(q, s);
3602 q = float64_div(float64_one, q, s);
3603 } else {
3604 /* range 0.5 <= a < 1.0 */
3605
3606 /* a in units of 1/256 rounded down */
3607 /* q1 = (int)(a * 256.0); */
3608 q = float64_mul(float64_256, a, s);
3609 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3610
3611 /* reciprocal root r */
3612 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3613 q = int64_to_float64(q_int, s);
3614 q = float64_add(q, float64_half, s);
3615 q = float64_div(q, float64_256, s);
3616 q = float64_sqrt(q, s);
3617 q = float64_div(float64_one, q, s);
3618 }
3619 /* r in units of 1/256 rounded to nearest */
3620 /* s = (int)(256.0 * r + 0.5); */
3621
3622 q = float64_mul(q, float64_256,s );
3623 q = float64_add(q, float64_half, s);
3624 q_int = float64_to_int64_round_to_zero(q, s);
3625
3626 /* return (double)s / 256.0;*/
3627 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3628}
3629
0ecb72a5 3630float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3631{
e07be5d2
CL		 3632 float_status *s = &env->vfp.standard_fp_status;
3633 int result_exp;
3634 float64 f64;
3635 uint32_t val;
3636 uint64_t val64;
3637
3638 val = float32_val(a);
3639
3640 if (float32_is_any_nan(a)) {
3641 if (float32_is_signaling_nan(a)) {
3642 float_raise(float_flag_invalid, s);
3643 }
3644 return float32_default_nan;
3645 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3646 if (!float32_is_zero(a)) {
3647 float_raise(float_flag_input_denormal, s);
3648 }
e07be5d2
CL		 3649 float_raise(float_flag_divbyzero, s);
3650 return float32_set_sign(float32_infinity, float32_is_neg(a));
3651 } else if (float32_is_neg(a)) {
3652 float_raise(float_flag_invalid, s);
3653 return float32_default_nan;
3654 } else if (float32_is_infinity(a)) {
3655 return float32_zero;
3656 }
3657
3658 /* Normalize to a double-precision value between 0.25 and 1.0,
3659 * preserving the parity of the exponent. */
3660 if ((val & 0x800000) == 0) {
3661 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3662 | (0x3feULL << 52)
3663 | ((uint64_t)(val & 0x7fffff) << 29));
3664 } else {
3665 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3666 | (0x3fdULL << 52)
3667 | ((uint64_t)(val & 0x7fffff) << 29));
3668 }
3669
3670 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3671
3672 f64 = recip_sqrt_estimate(f64, env);
3673
3674 val64 = float64_val(f64);
3675
26cc6abf 3676 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3677 | ((val64 >> 29) & 0x7fffff);
3678 return make_float32(val);
4373f3ce
PB		 3679}
3680
0ecb72a5 3681uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3682{
fe0e4872
CL		 3683 float64 f64;
3684
3685 if ((a & 0x80000000) == 0) {
3686 return 0xffffffff;
3687 }
3688
3689 f64 = make_float64((0x3feULL << 52)
3690 | ((int64_t)(a & 0x7fffffff) << 21));
3691
3692 f64 = recip_estimate (f64, env);
3693
3694 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3695}
3696
0ecb72a5 3697uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3698{
e07be5d2
CL		 3699 float64 f64;
3700
3701 if ((a & 0xc0000000) == 0) {
3702 return 0xffffffff;
3703 }
3704
3705 if (a & 0x80000000) {
3706 f64 = make_float64((0x3feULL << 52)
3707 | ((uint64_t)(a & 0x7fffffff) << 21));
3708 } else { /* bits 31-30 == '01' */
3709 f64 = make_float64((0x3fdULL << 52)
3710 | ((uint64_t)(a & 0x3fffffff) << 22));
3711 }
3712
3713 f64 = recip_sqrt_estimate(f64, env);
3714
3715 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3716}
fe1479c3 3717
da97f52c
PM		 3718/* VFPv4 fused multiply-accumulate */
3719float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3720{
3721 float_status *fpst = fpstp;
3722 return float32_muladd(a, b, c, 0, fpst);
3723}
3724
3725float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3726{
3727 float_status *fpst = fpstp;
3728 return float64_muladd(a, b, c, 0, fpst);
3729}
Qemu copy for testing