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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
c207aee4 | 36 | #include <linux/frame.h> |
bcaf287c | 37 | #include <linux/nospec.h> |
5fdbf976 | 38 | #include "kvm_cache_regs.h" |
35920a35 | 39 | #include "x86.h" |
e495606d | 40 | |
28b835d6 | 41 | #include <asm/cpu.h> |
6aa8b732 | 42 | #include <asm/io.h> |
3b3be0d1 | 43 | #include <asm/desc.h> |
13673a90 | 44 | #include <asm/vmx.h> |
6210e37b | 45 | #include <asm/virtext.h> |
a0861c02 | 46 | #include <asm/mce.h> |
952f07ec | 47 | #include <asm/fpu/internal.h> |
d7cd9796 | 48 | #include <asm/perf_event.h> |
81908bf4 | 49 | #include <asm/debugreg.h> |
8f536b76 | 50 | #include <asm/kexec.h> |
dab2087d | 51 | #include <asm/apic.h> |
efc64404 | 52 | #include <asm/irq_remapping.h> |
d6e41f11 | 53 | #include <asm/mmu_context.h> |
f471d71b | 54 | #include <asm/microcode.h> |
d7a6a163 | 55 | #include <asm/spec-ctrl.h> |
6aa8b732 | 56 | |
229456fc | 57 | #include "trace.h" |
25462f7f | 58 | #include "pmu.h" |
229456fc | 59 | |
4ecac3fd | 60 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
61 | #define __ex_clear(x, reg) \ |
62 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 63 | |
6aa8b732 AK |
64 | MODULE_AUTHOR("Qumranet"); |
65 | MODULE_LICENSE("GPL"); | |
66 | ||
e9bda3b3 JT |
67 | static const struct x86_cpu_id vmx_cpu_id[] = { |
68 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
69 | {} | |
70 | }; | |
71 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
72 | ||
476bc001 | 73 | static bool __read_mostly enable_vpid = 1; |
736caefe | 74 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 75 | |
d02fcf50 PB |
76 | static bool __read_mostly enable_vnmi = 1; |
77 | module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); | |
78 | ||
476bc001 | 79 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 80 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 81 | |
476bc001 | 82 | static bool __read_mostly enable_ept = 1; |
736caefe | 83 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 84 | |
476bc001 | 85 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
86 | module_param_named(unrestricted_guest, |
87 | enable_unrestricted_guest, bool, S_IRUGO); | |
88 | ||
83c3a331 XH |
89 | static bool __read_mostly enable_ept_ad_bits = 1; |
90 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
91 | ||
a27685c3 | 92 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 93 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 94 | |
476bc001 | 95 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
96 | module_param(fasteoi, bool, S_IRUGO); |
97 | ||
5a71785d | 98 | static bool __read_mostly enable_apicv = 1; |
01e439be | 99 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 100 | |
abc4fc58 AG |
101 | static bool __read_mostly enable_shadow_vmcs = 1; |
102 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
103 | /* |
104 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
105 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
106 | * use VMX instructions. | |
107 | */ | |
476bc001 | 108 | static bool __read_mostly nested = 0; |
801d3424 NHE |
109 | module_param(nested, bool, S_IRUGO); |
110 | ||
20300099 WL |
111 | static u64 __read_mostly host_xss; |
112 | ||
843e4330 KH |
113 | static bool __read_mostly enable_pml = 1; |
114 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
115 | ||
4b0be90f PB |
116 | #define MSR_TYPE_R 1 |
117 | #define MSR_TYPE_W 2 | |
118 | #define MSR_TYPE_RW 3 | |
119 | ||
120 | #define MSR_BITMAP_MODE_X2APIC 1 | |
121 | #define MSR_BITMAP_MODE_X2APIC_APICV 2 | |
122 | #define MSR_BITMAP_MODE_LM 4 | |
123 | ||
64903d61 HZ |
124 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
125 | ||
64672c95 YJ |
126 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
127 | static int __read_mostly cpu_preemption_timer_multi; | |
128 | static bool __read_mostly enable_preemption_timer = 1; | |
129 | #ifdef CONFIG_X86_64 | |
130 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
131 | #endif | |
132 | ||
5037878e GN |
133 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
134 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
135 | #define KVM_VM_CR0_ALWAYS_ON \ |
136 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
137 | #define KVM_CR4_GUEST_OWNED_BITS \ |
138 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
fd8cb433 | 139 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) |
4c38609a | 140 | |
cdc0e244 AK |
141 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
142 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
143 | ||
78ac8b47 AK |
144 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
145 | ||
f4124500 JK |
146 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
147 | ||
16c2aec6 JD |
148 | /* |
149 | * Hyper-V requires all of these, so mark them as supported even though | |
150 | * they are just treated the same as all-context. | |
151 | */ | |
152 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
153 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
154 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
155 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
156 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
157 | ||
4b8d54f9 ZE |
158 | /* |
159 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
160 | * ple_gap: upper bound on the amount of time between two successive | |
161 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 162 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
163 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
164 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
165 | * less than 2^12 cycles | |
166 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
167 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
168 | */ | |
b4a2d31d RK |
169 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
170 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
171 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
172 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
173 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
174 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
175 | ||
4b8d54f9 ZE |
176 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
177 | module_param(ple_gap, int, S_IRUGO); | |
178 | ||
179 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
180 | module_param(ple_window, int, S_IRUGO); | |
181 | ||
b4a2d31d RK |
182 | /* Default doubles per-vcpu window every exit. */ |
183 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
184 | module_param(ple_window_grow, int, S_IRUGO); | |
185 | ||
186 | /* Default resets per-vcpu window every exit to ple_window. */ | |
187 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
188 | module_param(ple_window_shrink, int, S_IRUGO); | |
189 | ||
190 | /* Default is to compute the maximum so we can never overflow. */ | |
191 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
192 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
193 | module_param(ple_window_max, int, S_IRUGO); | |
194 | ||
83287ea4 AK |
195 | extern const ulong vmx_return; |
196 | ||
1749555e | 197 | static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); |
12960b11 | 198 | static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); |
eeec2ec1 | 199 | static DEFINE_MUTEX(vmx_l1d_flush_mutex); |
1749555e | 200 | |
2bcd5b01 TG |
201 | /* Storage for pre module init parameter parsing */ |
202 | static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; | |
1749555e KRW |
203 | |
204 | static const struct { | |
205 | const char *option; | |
206 | enum vmx_l1d_flush_state cmd; | |
207 | } vmentry_l1d_param[] = { | |
b9cfedcd | 208 | {"auto", VMENTER_L1D_FLUSH_AUTO}, |
1749555e KRW |
209 | {"never", VMENTER_L1D_FLUSH_NEVER}, |
210 | {"cond", VMENTER_L1D_FLUSH_COND}, | |
211 | {"always", VMENTER_L1D_FLUSH_ALWAYS}, | |
212 | }; | |
213 | ||
2bcd5b01 TG |
214 | #define L1D_CACHE_ORDER 4 |
215 | static void *vmx_l1d_flush_pages; | |
216 | ||
217 | static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) | |
1749555e | 218 | { |
2bcd5b01 | 219 | struct page *page; |
55bd6950 | 220 | unsigned int i; |
1749555e | 221 | |
2bcd5b01 TG |
222 | if (!enable_ept) { |
223 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; | |
224 | return 0; | |
225 | } | |
226 | ||
364a4311 PB |
227 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { |
228 | u64 msr; | |
229 | ||
230 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); | |
231 | if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { | |
232 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; | |
233 | return 0; | |
234 | } | |
235 | } | |
236 | ||
24fcb53c JK |
237 | /* If set to auto use the default l1tf mitigation method */ |
238 | if (l1tf == VMENTER_L1D_FLUSH_AUTO) { | |
239 | switch (l1tf_mitigation) { | |
240 | case L1TF_MITIGATION_OFF: | |
241 | l1tf = VMENTER_L1D_FLUSH_NEVER; | |
242 | break; | |
243 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
244 | case L1TF_MITIGATION_FLUSH: | |
245 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
246 | l1tf = VMENTER_L1D_FLUSH_COND; | |
247 | break; | |
248 | case L1TF_MITIGATION_FULL: | |
249 | case L1TF_MITIGATION_FULL_FORCE: | |
250 | l1tf = VMENTER_L1D_FLUSH_ALWAYS; | |
251 | break; | |
252 | } | |
253 | } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { | |
254 | l1tf = VMENTER_L1D_FLUSH_ALWAYS; | |
255 | } | |
256 | ||
2bcd5b01 TG |
257 | if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && |
258 | !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { | |
259 | page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); | |
260 | if (!page) | |
261 | return -ENOMEM; | |
262 | vmx_l1d_flush_pages = page_address(page); | |
55bd6950 NS |
263 | |
264 | /* | |
265 | * Initialize each page with a different pattern in | |
266 | * order to protect against KSM in the nested | |
267 | * virtualization case. | |
268 | */ | |
269 | for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { | |
270 | memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, | |
271 | PAGE_SIZE); | |
272 | } | |
1749555e KRW |
273 | } |
274 | ||
2bcd5b01 TG |
275 | l1tf_vmx_mitigation = l1tf; |
276 | ||
522c7bed TG |
277 | if (l1tf != VMENTER_L1D_FLUSH_NEVER) |
278 | static_branch_enable(&vmx_l1d_should_flush); | |
279 | else | |
280 | static_branch_disable(&vmx_l1d_should_flush); | |
ae021965 | 281 | |
12960b11 NS |
282 | if (l1tf == VMENTER_L1D_FLUSH_COND) |
283 | static_branch_enable(&vmx_l1d_flush_cond); | |
522c7bed | 284 | else |
12960b11 | 285 | static_branch_disable(&vmx_l1d_flush_cond); |
2bcd5b01 TG |
286 | return 0; |
287 | } | |
288 | ||
289 | static int vmentry_l1d_flush_parse(const char *s) | |
290 | { | |
291 | unsigned int i; | |
292 | ||
293 | if (s) { | |
294 | for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { | |
522c7bed | 295 | if (sysfs_streq(s, vmentry_l1d_param[i].option)) |
2bcd5b01 TG |
296 | return vmentry_l1d_param[i].cmd; |
297 | } | |
298 | } | |
1749555e KRW |
299 | return -EINVAL; |
300 | } | |
301 | ||
2bcd5b01 TG |
302 | static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) |
303 | { | |
eeec2ec1 | 304 | int l1tf, ret; |
2bcd5b01 TG |
305 | |
306 | if (!boot_cpu_has(X86_BUG_L1TF)) | |
307 | return 0; | |
308 | ||
309 | l1tf = vmentry_l1d_flush_parse(s); | |
310 | if (l1tf < 0) | |
311 | return l1tf; | |
312 | ||
313 | /* | |
314 | * Has vmx_init() run already? If not then this is the pre init | |
315 | * parameter parsing. In that case just store the value and let | |
316 | * vmx_init() do the proper setup after enable_ept has been | |
317 | * established. | |
318 | */ | |
319 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { | |
320 | vmentry_l1d_flush_param = l1tf; | |
321 | return 0; | |
322 | } | |
323 | ||
eeec2ec1 TG |
324 | mutex_lock(&vmx_l1d_flush_mutex); |
325 | ret = vmx_setup_l1d_flush(l1tf); | |
326 | mutex_unlock(&vmx_l1d_flush_mutex); | |
327 | return ret; | |
2bcd5b01 TG |
328 | } |
329 | ||
1749555e KRW |
330 | static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) |
331 | { | |
2bcd5b01 | 332 | return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); |
1749555e KRW |
333 | } |
334 | ||
335 | static const struct kernel_param_ops vmentry_l1d_flush_ops = { | |
336 | .set = vmentry_l1d_flush_set, | |
337 | .get = vmentry_l1d_flush_get, | |
338 | }; | |
522c7bed | 339 | module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); |
1749555e | 340 | |
8bf00a52 | 341 | #define NR_AUTOLOAD_MSRS 8 |
61d2ef2c | 342 | |
a2fa3e9f GH |
343 | struct vmcs { |
344 | u32 revision_id; | |
345 | u32 abort; | |
346 | char data[0]; | |
347 | }; | |
348 | ||
d462b819 NHE |
349 | /* |
350 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
351 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
352 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
353 | */ | |
354 | struct loaded_vmcs { | |
355 | struct vmcs *vmcs; | |
355f4fb1 | 356 | struct vmcs *shadow_vmcs; |
d462b819 | 357 | int cpu; |
4c4a6f79 PB |
358 | bool launched; |
359 | bool nmi_known_unmasked; | |
44889942 LP |
360 | unsigned long vmcs_host_cr3; /* May not match real cr3 */ |
361 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ | |
8a1b4392 PB |
362 | /* Support for vnmi-less CPUs */ |
363 | int soft_vnmi_blocked; | |
364 | ktime_t entry_time; | |
365 | s64 vnmi_blocked_time; | |
4b0be90f | 366 | unsigned long *msr_bitmap; |
d462b819 NHE |
367 | struct list_head loaded_vmcss_on_cpu_link; |
368 | }; | |
369 | ||
26bb0981 AK |
370 | struct shared_msr_entry { |
371 | unsigned index; | |
372 | u64 data; | |
d5696725 | 373 | u64 mask; |
26bb0981 AK |
374 | }; |
375 | ||
a9d30f33 NHE |
376 | /* |
377 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
378 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
379 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
380 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
381 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
382 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
8819227c | 383 | * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the |
a9d30f33 NHE |
384 | * underlying hardware which will be used to run L2. |
385 | * This structure is packed to ensure that its layout is identical across | |
386 | * machines (necessary for live migration). | |
387 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
388 | */ | |
22bd0358 | 389 | typedef u64 natural_width; |
a9d30f33 NHE |
390 | struct __packed vmcs12 { |
391 | /* According to the Intel spec, a VMCS region must start with the | |
392 | * following two fields. Then follow implementation-specific data. | |
393 | */ | |
394 | u32 revision_id; | |
395 | u32 abort; | |
22bd0358 | 396 | |
27d6c865 NHE |
397 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
398 | u32 padding[7]; /* room for future expansion */ | |
399 | ||
22bd0358 NHE |
400 | u64 io_bitmap_a; |
401 | u64 io_bitmap_b; | |
402 | u64 msr_bitmap; | |
403 | u64 vm_exit_msr_store_addr; | |
404 | u64 vm_exit_msr_load_addr; | |
405 | u64 vm_entry_msr_load_addr; | |
406 | u64 tsc_offset; | |
407 | u64 virtual_apic_page_addr; | |
408 | u64 apic_access_addr; | |
705699a1 | 409 | u64 posted_intr_desc_addr; |
27c42a1b | 410 | u64 vm_function_control; |
22bd0358 | 411 | u64 ept_pointer; |
608406e2 WV |
412 | u64 eoi_exit_bitmap0; |
413 | u64 eoi_exit_bitmap1; | |
414 | u64 eoi_exit_bitmap2; | |
415 | u64 eoi_exit_bitmap3; | |
41ab9372 | 416 | u64 eptp_list_address; |
81dc01f7 | 417 | u64 xss_exit_bitmap; |
22bd0358 NHE |
418 | u64 guest_physical_address; |
419 | u64 vmcs_link_pointer; | |
c5f983f6 | 420 | u64 pml_address; |
22bd0358 NHE |
421 | u64 guest_ia32_debugctl; |
422 | u64 guest_ia32_pat; | |
423 | u64 guest_ia32_efer; | |
424 | u64 guest_ia32_perf_global_ctrl; | |
425 | u64 guest_pdptr0; | |
426 | u64 guest_pdptr1; | |
427 | u64 guest_pdptr2; | |
428 | u64 guest_pdptr3; | |
36be0b9d | 429 | u64 guest_bndcfgs; |
22bd0358 NHE |
430 | u64 host_ia32_pat; |
431 | u64 host_ia32_efer; | |
432 | u64 host_ia32_perf_global_ctrl; | |
433 | u64 padding64[8]; /* room for future expansion */ | |
434 | /* | |
435 | * To allow migration of L1 (complete with its L2 guests) between | |
436 | * machines of different natural widths (32 or 64 bit), we cannot have | |
437 | * unsigned long fields with no explict size. We use u64 (aliased | |
438 | * natural_width) instead. Luckily, x86 is little-endian. | |
439 | */ | |
440 | natural_width cr0_guest_host_mask; | |
441 | natural_width cr4_guest_host_mask; | |
442 | natural_width cr0_read_shadow; | |
443 | natural_width cr4_read_shadow; | |
444 | natural_width cr3_target_value0; | |
445 | natural_width cr3_target_value1; | |
446 | natural_width cr3_target_value2; | |
447 | natural_width cr3_target_value3; | |
448 | natural_width exit_qualification; | |
449 | natural_width guest_linear_address; | |
450 | natural_width guest_cr0; | |
451 | natural_width guest_cr3; | |
452 | natural_width guest_cr4; | |
453 | natural_width guest_es_base; | |
454 | natural_width guest_cs_base; | |
455 | natural_width guest_ss_base; | |
456 | natural_width guest_ds_base; | |
457 | natural_width guest_fs_base; | |
458 | natural_width guest_gs_base; | |
459 | natural_width guest_ldtr_base; | |
460 | natural_width guest_tr_base; | |
461 | natural_width guest_gdtr_base; | |
462 | natural_width guest_idtr_base; | |
463 | natural_width guest_dr7; | |
464 | natural_width guest_rsp; | |
465 | natural_width guest_rip; | |
466 | natural_width guest_rflags; | |
467 | natural_width guest_pending_dbg_exceptions; | |
468 | natural_width guest_sysenter_esp; | |
469 | natural_width guest_sysenter_eip; | |
470 | natural_width host_cr0; | |
471 | natural_width host_cr3; | |
472 | natural_width host_cr4; | |
473 | natural_width host_fs_base; | |
474 | natural_width host_gs_base; | |
475 | natural_width host_tr_base; | |
476 | natural_width host_gdtr_base; | |
477 | natural_width host_idtr_base; | |
478 | natural_width host_ia32_sysenter_esp; | |
479 | natural_width host_ia32_sysenter_eip; | |
480 | natural_width host_rsp; | |
481 | natural_width host_rip; | |
482 | natural_width paddingl[8]; /* room for future expansion */ | |
483 | u32 pin_based_vm_exec_control; | |
484 | u32 cpu_based_vm_exec_control; | |
485 | u32 exception_bitmap; | |
486 | u32 page_fault_error_code_mask; | |
487 | u32 page_fault_error_code_match; | |
488 | u32 cr3_target_count; | |
489 | u32 vm_exit_controls; | |
490 | u32 vm_exit_msr_store_count; | |
491 | u32 vm_exit_msr_load_count; | |
492 | u32 vm_entry_controls; | |
493 | u32 vm_entry_msr_load_count; | |
494 | u32 vm_entry_intr_info_field; | |
495 | u32 vm_entry_exception_error_code; | |
496 | u32 vm_entry_instruction_len; | |
497 | u32 tpr_threshold; | |
498 | u32 secondary_vm_exec_control; | |
499 | u32 vm_instruction_error; | |
500 | u32 vm_exit_reason; | |
501 | u32 vm_exit_intr_info; | |
502 | u32 vm_exit_intr_error_code; | |
503 | u32 idt_vectoring_info_field; | |
504 | u32 idt_vectoring_error_code; | |
505 | u32 vm_exit_instruction_len; | |
506 | u32 vmx_instruction_info; | |
507 | u32 guest_es_limit; | |
508 | u32 guest_cs_limit; | |
509 | u32 guest_ss_limit; | |
510 | u32 guest_ds_limit; | |
511 | u32 guest_fs_limit; | |
512 | u32 guest_gs_limit; | |
513 | u32 guest_ldtr_limit; | |
514 | u32 guest_tr_limit; | |
515 | u32 guest_gdtr_limit; | |
516 | u32 guest_idtr_limit; | |
517 | u32 guest_es_ar_bytes; | |
518 | u32 guest_cs_ar_bytes; | |
519 | u32 guest_ss_ar_bytes; | |
520 | u32 guest_ds_ar_bytes; | |
521 | u32 guest_fs_ar_bytes; | |
522 | u32 guest_gs_ar_bytes; | |
523 | u32 guest_ldtr_ar_bytes; | |
524 | u32 guest_tr_ar_bytes; | |
525 | u32 guest_interruptibility_info; | |
526 | u32 guest_activity_state; | |
527 | u32 guest_sysenter_cs; | |
528 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
529 | u32 vmx_preemption_timer_value; |
530 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 531 | u16 virtual_processor_id; |
705699a1 | 532 | u16 posted_intr_nv; |
22bd0358 NHE |
533 | u16 guest_es_selector; |
534 | u16 guest_cs_selector; | |
535 | u16 guest_ss_selector; | |
536 | u16 guest_ds_selector; | |
537 | u16 guest_fs_selector; | |
538 | u16 guest_gs_selector; | |
539 | u16 guest_ldtr_selector; | |
540 | u16 guest_tr_selector; | |
608406e2 | 541 | u16 guest_intr_status; |
c5f983f6 | 542 | u16 guest_pml_index; |
22bd0358 NHE |
543 | u16 host_es_selector; |
544 | u16 host_cs_selector; | |
545 | u16 host_ss_selector; | |
546 | u16 host_ds_selector; | |
547 | u16 host_fs_selector; | |
548 | u16 host_gs_selector; | |
549 | u16 host_tr_selector; | |
a9d30f33 NHE |
550 | }; |
551 | ||
552 | /* | |
553 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
554 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
555 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
556 | */ | |
557 | #define VMCS12_REVISION 0x11e57ed0 | |
558 | ||
559 | /* | |
560 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
561 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
562 | * current implementation, 4K are reserved to avoid future complications. | |
563 | */ | |
564 | #define VMCS12_SIZE 0x1000 | |
565 | ||
ec378aee NHE |
566 | /* |
567 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
568 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
569 | */ | |
570 | struct nested_vmx { | |
571 | /* Has the level1 guest done vmxon? */ | |
572 | bool vmxon; | |
3573e22c | 573 | gpa_t vmxon_ptr; |
c5f983f6 | 574 | bool pml_full; |
a9d30f33 NHE |
575 | |
576 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
577 | gpa_t current_vmptr; | |
4f2777bc DM |
578 | /* |
579 | * Cache of the guest's VMCS, existing outside of guest memory. | |
580 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
8ca44e88 | 581 | * memory during VMCLEAR and VMPTRLD. |
4f2777bc DM |
582 | */ |
583 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
584 | /* |
585 | * Indicates if the shadow vmcs must be updated with the | |
586 | * data hold by vmcs12 | |
587 | */ | |
588 | bool sync_shadow_vmcs; | |
ff2f6fe9 | 589 | |
dccbfcf5 | 590 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
591 | /* L2 must run next, and mustn't decide to exit to L1. */ |
592 | bool nested_run_pending; | |
8819227c JM |
593 | |
594 | struct loaded_vmcs vmcs02; | |
595 | ||
fe3ef05c | 596 | /* |
8819227c JM |
597 | * Guest pages referred to in the vmcs02 with host-physical |
598 | * pointers, so we must keep them pinned while L2 runs. | |
fe3ef05c NHE |
599 | */ |
600 | struct page *apic_access_page; | |
a7c0b07d | 601 | struct page *virtual_apic_page; |
705699a1 WV |
602 | struct page *pi_desc_page; |
603 | struct pi_desc *pi_desc; | |
604 | bool pi_pending; | |
605 | u16 posted_intr_nv; | |
f4124500 JK |
606 | |
607 | struct hrtimer preemption_timer; | |
608 | bool preemption_timer_expired; | |
2996fca0 JK |
609 | |
610 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
611 | u64 vmcs01_debugctl; | |
b9c237bb | 612 | |
5c614b35 WL |
613 | u16 vpid02; |
614 | u16 last_vpid; | |
615 | ||
0115f9cb DM |
616 | /* |
617 | * We only store the "true" versions of the VMX capability MSRs. We | |
618 | * generate the "non-true" versions by setting the must-be-1 bits | |
619 | * according to the SDM. | |
620 | */ | |
b9c237bb WV |
621 | u32 nested_vmx_procbased_ctls_low; |
622 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
623 | u32 nested_vmx_secondary_ctls_low; |
624 | u32 nested_vmx_secondary_ctls_high; | |
625 | u32 nested_vmx_pinbased_ctls_low; | |
626 | u32 nested_vmx_pinbased_ctls_high; | |
627 | u32 nested_vmx_exit_ctls_low; | |
628 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
629 | u32 nested_vmx_entry_ctls_low; |
630 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
631 | u32 nested_vmx_misc_low; |
632 | u32 nested_vmx_misc_high; | |
633 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 634 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
635 | u64 nested_vmx_basic; |
636 | u64 nested_vmx_cr0_fixed0; | |
637 | u64 nested_vmx_cr0_fixed1; | |
638 | u64 nested_vmx_cr4_fixed0; | |
639 | u64 nested_vmx_cr4_fixed1; | |
640 | u64 nested_vmx_vmcs_enum; | |
27c42a1b | 641 | u64 nested_vmx_vmfunc_controls; |
72e9cbdb LP |
642 | |
643 | /* SMM related state */ | |
644 | struct { | |
645 | /* in VMX operation on SMM entry? */ | |
646 | bool vmxon; | |
647 | /* in guest mode on SMM entry? */ | |
648 | bool guest_mode; | |
649 | } smm; | |
ec378aee NHE |
650 | }; |
651 | ||
01e439be | 652 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
653 | #define POSTED_INTR_SN 1 |
654 | ||
01e439be YZ |
655 | /* Posted-Interrupt Descriptor */ |
656 | struct pi_desc { | |
657 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
658 | union { |
659 | struct { | |
660 | /* bit 256 - Outstanding Notification */ | |
661 | u16 on : 1, | |
662 | /* bit 257 - Suppress Notification */ | |
663 | sn : 1, | |
664 | /* bit 271:258 - Reserved */ | |
665 | rsvd_1 : 14; | |
666 | /* bit 279:272 - Notification Vector */ | |
667 | u8 nv; | |
668 | /* bit 287:280 - Reserved */ | |
669 | u8 rsvd_2; | |
670 | /* bit 319:288 - Notification Destination */ | |
671 | u32 ndst; | |
672 | }; | |
673 | u64 control; | |
674 | }; | |
675 | u32 rsvd[6]; | |
01e439be YZ |
676 | } __aligned(64); |
677 | ||
a20ed54d YZ |
678 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
679 | { | |
680 | return test_and_set_bit(POSTED_INTR_ON, | |
681 | (unsigned long *)&pi_desc->control); | |
682 | } | |
683 | ||
684 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
685 | { | |
686 | return test_and_clear_bit(POSTED_INTR_ON, | |
687 | (unsigned long *)&pi_desc->control); | |
688 | } | |
689 | ||
690 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
691 | { | |
692 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
693 | } | |
694 | ||
ebbfc765 FW |
695 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
696 | { | |
697 | return clear_bit(POSTED_INTR_SN, | |
698 | (unsigned long *)&pi_desc->control); | |
699 | } | |
700 | ||
701 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
702 | { | |
703 | return set_bit(POSTED_INTR_SN, | |
704 | (unsigned long *)&pi_desc->control); | |
705 | } | |
706 | ||
ad361091 PB |
707 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
708 | { | |
709 | clear_bit(POSTED_INTR_ON, | |
710 | (unsigned long *)&pi_desc->control); | |
711 | } | |
712 | ||
ebbfc765 FW |
713 | static inline int pi_test_on(struct pi_desc *pi_desc) |
714 | { | |
715 | return test_bit(POSTED_INTR_ON, | |
716 | (unsigned long *)&pi_desc->control); | |
717 | } | |
718 | ||
719 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
720 | { | |
721 | return test_bit(POSTED_INTR_SN, | |
722 | (unsigned long *)&pi_desc->control); | |
723 | } | |
724 | ||
6e3dedb6 KRW |
725 | struct vmx_msrs { |
726 | unsigned int nr; | |
727 | struct vmx_msr_entry val[NR_AUTOLOAD_MSRS]; | |
728 | }; | |
729 | ||
a2fa3e9f | 730 | struct vcpu_vmx { |
fb3f0f51 | 731 | struct kvm_vcpu vcpu; |
313dbd49 | 732 | unsigned long host_rsp; |
29bd8a78 | 733 | u8 fail; |
4b0be90f | 734 | u8 msr_bitmap_mode; |
51aa01d1 | 735 | u32 exit_intr_info; |
1155f76a | 736 | u32 idt_vectoring_info; |
6de12732 | 737 | ulong rflags; |
26bb0981 | 738 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
739 | int nmsrs; |
740 | int save_nmsrs; | |
a547c6db | 741 | unsigned long host_idt_base; |
a2fa3e9f | 742 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
743 | u64 msr_host_kernel_gs_base; |
744 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 745 | #endif |
33241bfe | 746 | |
a6005a79 | 747 | u64 arch_capabilities; |
74469996 | 748 | u64 spec_ctrl; |
a6005a79 | 749 | |
2961e876 GN |
750 | u32 vm_entry_controls_shadow; |
751 | u32 vm_exit_controls_shadow; | |
80154d77 PB |
752 | u32 secondary_exec_control; |
753 | ||
d462b819 NHE |
754 | /* |
755 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
756 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
757 | * guest (L2), it points to a different VMCS. | |
758 | */ | |
759 | struct loaded_vmcs vmcs01; | |
760 | struct loaded_vmcs *loaded_vmcs; | |
761 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c | 762 | struct msr_autoload { |
6e3dedb6 KRW |
763 | struct vmx_msrs guest; |
764 | struct vmx_msrs host; | |
61d2ef2c | 765 | } msr_autoload; |
a2fa3e9f GH |
766 | struct { |
767 | int loaded; | |
768 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
769 | #ifdef CONFIG_X86_64 |
770 | u16 ds_sel, es_sel; | |
771 | #endif | |
152d3f2f LV |
772 | int gs_ldt_reload_needed; |
773 | int fs_reload_needed; | |
da8999d3 | 774 | u64 msr_host_bndcfgs; |
d77c26fc | 775 | } host_state; |
9c8cba37 | 776 | struct { |
7ffd92c5 | 777 | int vm86_active; |
78ac8b47 | 778 | ulong save_rflags; |
f5f7b2fe AK |
779 | struct kvm_segment segs[8]; |
780 | } rmode; | |
781 | struct { | |
782 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
783 | struct kvm_save_segment { |
784 | u16 selector; | |
785 | unsigned long base; | |
786 | u32 limit; | |
787 | u32 ar; | |
f5f7b2fe | 788 | } seg[8]; |
2fb92db1 | 789 | } segment_cache; |
2384d2b3 | 790 | int vpid; |
04fa4d32 | 791 | bool emulation_required; |
3b86cd99 | 792 | |
a0861c02 | 793 | u32 exit_reason; |
4e47c7a6 | 794 | |
01e439be YZ |
795 | /* Posted interrupt descriptor */ |
796 | struct pi_desc pi_desc; | |
797 | ||
ec378aee NHE |
798 | /* Support for a guest hypervisor (nested VMX) */ |
799 | struct nested_vmx nested; | |
a7653ecd RK |
800 | |
801 | /* Dynamic PLE window. */ | |
802 | int ple_window; | |
803 | bool ple_window_dirty; | |
843e4330 KH |
804 | |
805 | /* Support for PML */ | |
806 | #define PML_ENTITY_NUM 512 | |
807 | struct page *pml_pg; | |
2680d6da | 808 | |
64672c95 YJ |
809 | /* apic deadline value in host tsc */ |
810 | u64 hv_deadline_tsc; | |
811 | ||
2680d6da | 812 | u64 current_tsc_ratio; |
1be0e61c | 813 | |
1be0e61c | 814 | u32 host_pkru; |
3b84080b | 815 | |
37e4c997 HZ |
816 | /* |
817 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
818 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
819 | * in msr_ia32_feature_control_valid_bits. | |
820 | */ | |
3b84080b | 821 | u64 msr_ia32_feature_control; |
37e4c997 | 822 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
823 | }; |
824 | ||
2fb92db1 AK |
825 | enum segment_cache_field { |
826 | SEG_FIELD_SEL = 0, | |
827 | SEG_FIELD_BASE = 1, | |
828 | SEG_FIELD_LIMIT = 2, | |
829 | SEG_FIELD_AR = 3, | |
830 | ||
831 | SEG_FIELD_NR = 4 | |
832 | }; | |
833 | ||
a2fa3e9f GH |
834 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
835 | { | |
fb3f0f51 | 836 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
837 | } |
838 | ||
efc64404 FW |
839 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
840 | { | |
841 | return &(to_vmx(vcpu)->pi_desc); | |
842 | } | |
843 | ||
22bd0358 NHE |
844 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
845 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
846 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
847 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
848 | ||
4607c2d7 | 849 | |
fe2b201b | 850 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
851 | /* |
852 | * We do NOT shadow fields that are modified when L0 | |
853 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
854 | * VMXON...) executed by L1. | |
855 | * For example, VM_INSTRUCTION_ERROR is read | |
856 | * by L1 if a vmx instruction fails (part of the error path). | |
857 | * Note the code assumes this logic. If for some reason | |
858 | * we start shadowing these fields then we need to | |
859 | * force a shadow sync when L0 emulates vmx instructions | |
860 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
861 | * by nested_vmx_failValid) | |
862 | */ | |
863 | VM_EXIT_REASON, | |
864 | VM_EXIT_INTR_INFO, | |
865 | VM_EXIT_INSTRUCTION_LEN, | |
866 | IDT_VECTORING_INFO_FIELD, | |
867 | IDT_VECTORING_ERROR_CODE, | |
868 | VM_EXIT_INTR_ERROR_CODE, | |
869 | EXIT_QUALIFICATION, | |
870 | GUEST_LINEAR_ADDRESS, | |
871 | GUEST_PHYSICAL_ADDRESS | |
872 | }; | |
fe2b201b | 873 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
874 | ARRAY_SIZE(shadow_read_only_fields); |
875 | ||
fe2b201b | 876 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 877 | TPR_THRESHOLD, |
4607c2d7 AG |
878 | GUEST_RIP, |
879 | GUEST_RSP, | |
880 | GUEST_CR0, | |
881 | GUEST_CR3, | |
882 | GUEST_CR4, | |
883 | GUEST_INTERRUPTIBILITY_INFO, | |
884 | GUEST_RFLAGS, | |
885 | GUEST_CS_SELECTOR, | |
886 | GUEST_CS_AR_BYTES, | |
887 | GUEST_CS_LIMIT, | |
888 | GUEST_CS_BASE, | |
889 | GUEST_ES_BASE, | |
36be0b9d | 890 | GUEST_BNDCFGS, |
4607c2d7 AG |
891 | CR0_GUEST_HOST_MASK, |
892 | CR0_READ_SHADOW, | |
893 | CR4_READ_SHADOW, | |
894 | TSC_OFFSET, | |
895 | EXCEPTION_BITMAP, | |
896 | CPU_BASED_VM_EXEC_CONTROL, | |
897 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
898 | VM_ENTRY_INTR_INFO_FIELD, | |
899 | VM_ENTRY_INSTRUCTION_LEN, | |
900 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
901 | HOST_FS_BASE, | |
902 | HOST_GS_BASE, | |
903 | HOST_FS_SELECTOR, | |
904 | HOST_GS_SELECTOR | |
905 | }; | |
fe2b201b | 906 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
907 | ARRAY_SIZE(shadow_read_write_fields); |
908 | ||
772e0318 | 909 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 910 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 911 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
912 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
913 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
914 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
915 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
916 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
917 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
918 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
919 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 920 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
c5f983f6 | 921 | FIELD(GUEST_PML_INDEX, guest_pml_index), |
22bd0358 NHE |
922 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
923 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
924 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
925 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
926 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
927 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
928 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
929 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
930 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
931 | FIELD64(MSR_BITMAP, msr_bitmap), | |
932 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
933 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
934 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
935 | FIELD64(TSC_OFFSET, tsc_offset), | |
936 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
937 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 938 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
27c42a1b | 939 | FIELD64(VM_FUNCTION_CONTROL, vm_function_control), |
22bd0358 | 940 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
941 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
942 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
943 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
944 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
41ab9372 | 945 | FIELD64(EPTP_LIST_ADDRESS, eptp_list_address), |
81dc01f7 | 946 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
947 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
948 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
c5f983f6 | 949 | FIELD64(PML_ADDRESS, pml_address), |
22bd0358 NHE |
950 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
951 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
952 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
953 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
954 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
955 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
956 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
957 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 958 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
959 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
960 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
961 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
962 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
963 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
964 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
965 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
966 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
967 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
968 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
969 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
970 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
971 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
972 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
973 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
974 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
975 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
976 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
977 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
978 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
979 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
980 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
981 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
982 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
983 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
984 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
985 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
986 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
987 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
988 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
989 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
990 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
991 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
992 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
993 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
994 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
995 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
996 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
997 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
998 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
999 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
1000 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
1001 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
1002 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
1003 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
1004 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
1005 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
1006 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
1007 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 1008 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
1009 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
1010 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
1011 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
1012 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
1013 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
1014 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
1015 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
1016 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
1017 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
1018 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
1019 | FIELD(GUEST_CR0, guest_cr0), | |
1020 | FIELD(GUEST_CR3, guest_cr3), | |
1021 | FIELD(GUEST_CR4, guest_cr4), | |
1022 | FIELD(GUEST_ES_BASE, guest_es_base), | |
1023 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
1024 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
1025 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
1026 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
1027 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
1028 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
1029 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
1030 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
1031 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
1032 | FIELD(GUEST_DR7, guest_dr7), | |
1033 | FIELD(GUEST_RSP, guest_rsp), | |
1034 | FIELD(GUEST_RIP, guest_rip), | |
1035 | FIELD(GUEST_RFLAGS, guest_rflags), | |
1036 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
1037 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
1038 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
1039 | FIELD(HOST_CR0, host_cr0), | |
1040 | FIELD(HOST_CR3, host_cr3), | |
1041 | FIELD(HOST_CR4, host_cr4), | |
1042 | FIELD(HOST_FS_BASE, host_fs_base), | |
1043 | FIELD(HOST_GS_BASE, host_gs_base), | |
1044 | FIELD(HOST_TR_BASE, host_tr_base), | |
1045 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
1046 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
1047 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
1048 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
1049 | FIELD(HOST_RSP, host_rsp), | |
1050 | FIELD(HOST_RIP, host_rip), | |
1051 | }; | |
22bd0358 NHE |
1052 | |
1053 | static inline short vmcs_field_to_offset(unsigned long field) | |
1054 | { | |
bcaf287c DW |
1055 | const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table); |
1056 | unsigned short offset; | |
a2ae9df7 | 1057 | |
bcaf287c DW |
1058 | BUILD_BUG_ON(size > SHRT_MAX); |
1059 | if (field >= size) | |
75f139aa AH |
1060 | return -ENOENT; |
1061 | ||
bcaf287c DW |
1062 | field = array_index_nospec(field, size); |
1063 | offset = vmcs_field_to_offset_table[field]; | |
1064 | if (offset == 0) | |
a2ae9df7 | 1065 | return -ENOENT; |
bcaf287c | 1066 | return offset; |
22bd0358 NHE |
1067 | } |
1068 | ||
a9d30f33 NHE |
1069 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
1070 | { | |
4f2777bc | 1071 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
1072 | } |
1073 | ||
995f00a6 | 1074 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu); |
bfd0a56b | 1075 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
995f00a6 | 1076 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); |
f53cd63c | 1077 | static bool vmx_xsaves_supported(void); |
b246dd5d OW |
1078 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
1079 | struct kvm_segment *var, int seg); | |
1080 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1081 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
1082 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
1083 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
16f5b903 | 1084 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
b96fb439 PB |
1085 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); |
1086 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); | |
1087 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, | |
1088 | u16 error_code); | |
4b0be90f | 1089 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); |
33241bfe AR |
1090 | static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
1091 | u32 msr, int type); | |
75880a01 | 1092 | |
6aa8b732 AK |
1093 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
1094 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
1095 | /* |
1096 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
1097 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
1098 | */ | |
1099 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 1100 | |
bf9f6ac8 FW |
1101 | /* |
1102 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
1103 | * can find which vCPU should be waken up. | |
1104 | */ | |
1105 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
1106 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
1107 | ||
23611332 RK |
1108 | enum { |
1109 | VMX_IO_BITMAP_A, | |
1110 | VMX_IO_BITMAP_B, | |
23611332 RK |
1111 | VMX_VMREAD_BITMAP, |
1112 | VMX_VMWRITE_BITMAP, | |
1113 | VMX_BITMAP_NR | |
1114 | }; | |
1115 | ||
1116 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
1117 | ||
1118 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
1119 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
23611332 RK |
1120 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) |
1121 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 1122 | |
110312c8 | 1123 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 1124 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 1125 | |
2384d2b3 SY |
1126 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
1127 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
1128 | ||
1c3d14fe | 1129 | static struct vmcs_config { |
6aa8b732 AK |
1130 | int size; |
1131 | int order; | |
9ac7e3e8 | 1132 | u32 basic_cap; |
6aa8b732 | 1133 | u32 revision_id; |
1c3d14fe YS |
1134 | u32 pin_based_exec_ctrl; |
1135 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 1136 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
1137 | u32 vmexit_ctrl; |
1138 | u32 vmentry_ctrl; | |
1139 | } vmcs_config; | |
6aa8b732 | 1140 | |
efff9e53 | 1141 | static struct vmx_capability { |
d56f546d SY |
1142 | u32 ept; |
1143 | u32 vpid; | |
1144 | } vmx_capability; | |
1145 | ||
6aa8b732 AK |
1146 | #define VMX_SEGMENT_FIELD(seg) \ |
1147 | [VCPU_SREG_##seg] = { \ | |
1148 | .selector = GUEST_##seg##_SELECTOR, \ | |
1149 | .base = GUEST_##seg##_BASE, \ | |
1150 | .limit = GUEST_##seg##_LIMIT, \ | |
1151 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
1152 | } | |
1153 | ||
772e0318 | 1154 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
1155 | unsigned selector; |
1156 | unsigned base; | |
1157 | unsigned limit; | |
1158 | unsigned ar_bytes; | |
1159 | } kvm_vmx_segment_fields[] = { | |
1160 | VMX_SEGMENT_FIELD(CS), | |
1161 | VMX_SEGMENT_FIELD(DS), | |
1162 | VMX_SEGMENT_FIELD(ES), | |
1163 | VMX_SEGMENT_FIELD(FS), | |
1164 | VMX_SEGMENT_FIELD(GS), | |
1165 | VMX_SEGMENT_FIELD(SS), | |
1166 | VMX_SEGMENT_FIELD(TR), | |
1167 | VMX_SEGMENT_FIELD(LDTR), | |
1168 | }; | |
1169 | ||
26bb0981 AK |
1170 | static u64 host_efer; |
1171 | ||
6de4f3ad AK |
1172 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1173 | ||
4d56c8a7 | 1174 | /* |
8c06585d | 1175 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1176 | * away by decrementing the array size. |
1177 | */ | |
6aa8b732 | 1178 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1179 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1180 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1181 | #endif |
8c06585d | 1182 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1183 | }; |
6aa8b732 | 1184 | |
5bb16016 | 1185 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1186 | { |
1187 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1188 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1189 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1190 | } | |
1191 | ||
6f05485d JK |
1192 | static inline bool is_debug(u32 intr_info) |
1193 | { | |
1194 | return is_exception_n(intr_info, DB_VECTOR); | |
1195 | } | |
1196 | ||
1197 | static inline bool is_breakpoint(u32 intr_info) | |
1198 | { | |
1199 | return is_exception_n(intr_info, BP_VECTOR); | |
1200 | } | |
1201 | ||
5bb16016 JK |
1202 | static inline bool is_page_fault(u32 intr_info) |
1203 | { | |
1204 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1205 | } |
1206 | ||
31299944 | 1207 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1208 | { |
5bb16016 | 1209 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1210 | } |
1211 | ||
31299944 | 1212 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1213 | { |
5bb16016 | 1214 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1215 | } |
1216 | ||
31299944 | 1217 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1218 | { |
1219 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1220 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1221 | } | |
1222 | ||
31299944 | 1223 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1224 | { |
1225 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1226 | INTR_INFO_VALID_MASK)) == | |
1227 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1228 | } | |
1229 | ||
3252850d LT |
1230 | /* Undocumented: icebp/int1 */ |
1231 | static inline bool is_icebp(u32 intr_info) | |
1232 | { | |
1233 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1234 | == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK); | |
1235 | } | |
1236 | ||
31299944 | 1237 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1238 | { |
04547156 | 1239 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1240 | } |
1241 | ||
31299944 | 1242 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1243 | { |
04547156 | 1244 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1245 | } |
1246 | ||
35754c98 | 1247 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1248 | { |
35754c98 | 1249 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1250 | } |
1251 | ||
31299944 | 1252 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1253 | { |
04547156 SY |
1254 | return vmcs_config.cpu_based_exec_ctrl & |
1255 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1256 | } |
1257 | ||
774ead3a | 1258 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1259 | { |
04547156 SY |
1260 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1261 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1262 | } | |
1263 | ||
8d14695f YZ |
1264 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1265 | { | |
1266 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1267 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1268 | } | |
1269 | ||
83d4c286 YZ |
1270 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1271 | { | |
1272 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1273 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1274 | } | |
1275 | ||
c7c9c56c YZ |
1276 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1277 | { | |
1278 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1279 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1280 | } | |
1281 | ||
64672c95 YJ |
1282 | /* |
1283 | * Comment's format: document - errata name - stepping - processor name. | |
1284 | * Refer from | |
1285 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1286 | */ | |
1287 | static u32 vmx_preemption_cpu_tfms[] = { | |
1288 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1289 | 0x000206E6, | |
1290 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1291 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1292 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1293 | 0x00020652, | |
1294 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1295 | 0x00020655, | |
1296 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1297 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1298 | /* | |
1299 | * 320767.pdf - AAP86 - B1 - | |
1300 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1301 | */ | |
1302 | 0x000106E5, | |
1303 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1304 | 0x000106A0, | |
1305 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1306 | 0x000106A1, | |
1307 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1308 | 0x000106A4, | |
1309 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1310 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1311 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1312 | 0x000106A5, | |
1313 | }; | |
1314 | ||
1315 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1316 | { | |
1317 | u32 eax = cpuid_eax(0x00000001), i; | |
1318 | ||
1319 | /* Clear the reserved bits */ | |
1320 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1321 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1322 | if (eax == vmx_preemption_cpu_tfms[i]) |
1323 | return true; | |
1324 | ||
1325 | return false; | |
1326 | } | |
1327 | ||
1328 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1329 | { | |
64672c95 YJ |
1330 | return vmcs_config.pin_based_exec_ctrl & |
1331 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1332 | } | |
1333 | ||
01e439be YZ |
1334 | static inline bool cpu_has_vmx_posted_intr(void) |
1335 | { | |
d6a858d1 PB |
1336 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1337 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1338 | } |
1339 | ||
1340 | static inline bool cpu_has_vmx_apicv(void) | |
1341 | { | |
1342 | return cpu_has_vmx_apic_register_virt() && | |
1343 | cpu_has_vmx_virtual_intr_delivery() && | |
1344 | cpu_has_vmx_posted_intr(); | |
1345 | } | |
1346 | ||
04547156 SY |
1347 | static inline bool cpu_has_vmx_flexpriority(void) |
1348 | { | |
1349 | return cpu_has_vmx_tpr_shadow() && | |
1350 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1351 | } |
1352 | ||
e799794e MT |
1353 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1354 | { | |
31299944 | 1355 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1356 | } |
1357 | ||
e799794e MT |
1358 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1359 | { | |
31299944 | 1360 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1361 | } |
1362 | ||
878403b7 SY |
1363 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1364 | { | |
31299944 | 1365 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1366 | } |
1367 | ||
4bc9b982 SY |
1368 | static inline bool cpu_has_vmx_ept_4levels(void) |
1369 | { | |
1370 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1371 | } | |
1372 | ||
42aa53b4 DH |
1373 | static inline bool cpu_has_vmx_ept_mt_wb(void) |
1374 | { | |
1375 | return vmx_capability.ept & VMX_EPTP_WB_BIT; | |
1376 | } | |
1377 | ||
855feb67 YZ |
1378 | static inline bool cpu_has_vmx_ept_5levels(void) |
1379 | { | |
1380 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; | |
1381 | } | |
1382 | ||
83c3a331 XH |
1383 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1384 | { | |
1385 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1386 | } | |
1387 | ||
31299944 | 1388 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1389 | { |
31299944 | 1390 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1391 | } |
1392 | ||
31299944 | 1393 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1394 | { |
31299944 | 1395 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1396 | } |
1397 | ||
518c8aee GJ |
1398 | static inline bool cpu_has_vmx_invvpid_single(void) |
1399 | { | |
1400 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1401 | } | |
1402 | ||
b9d762fa GJ |
1403 | static inline bool cpu_has_vmx_invvpid_global(void) |
1404 | { | |
1405 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1406 | } | |
1407 | ||
08d839c4 WL |
1408 | static inline bool cpu_has_vmx_invvpid(void) |
1409 | { | |
1410 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1411 | } | |
1412 | ||
31299944 | 1413 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1414 | { |
04547156 SY |
1415 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1416 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1417 | } |
1418 | ||
31299944 | 1419 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1420 | { |
1421 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1422 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1423 | } | |
1424 | ||
31299944 | 1425 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1426 | { |
1427 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1428 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1429 | } | |
1430 | ||
9ac7e3e8 JD |
1431 | static inline bool cpu_has_vmx_basic_inout(void) |
1432 | { | |
1433 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1434 | } | |
1435 | ||
35754c98 | 1436 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1437 | { |
35754c98 | 1438 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1439 | } |
1440 | ||
31299944 | 1441 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1442 | { |
04547156 SY |
1443 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1444 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1445 | } |
1446 | ||
31299944 | 1447 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1448 | { |
1449 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1450 | SECONDARY_EXEC_RDTSCP; | |
1451 | } | |
1452 | ||
ad756a16 MJ |
1453 | static inline bool cpu_has_vmx_invpcid(void) |
1454 | { | |
1455 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1456 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1457 | } | |
1458 | ||
8a1b4392 PB |
1459 | static inline bool cpu_has_virtual_nmis(void) |
1460 | { | |
1461 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1462 | } | |
1463 | ||
f5f48ee1 SY |
1464 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1465 | { | |
1466 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1467 | SECONDARY_EXEC_WBINVD_EXITING; | |
1468 | } | |
1469 | ||
abc4fc58 AG |
1470 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1471 | { | |
1472 | u64 vmx_msr; | |
1473 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1474 | /* check if the cpu supports writing r/o exit information fields */ | |
1475 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1476 | return false; | |
1477 | ||
1478 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1479 | SECONDARY_EXEC_SHADOW_VMCS; | |
1480 | } | |
1481 | ||
843e4330 KH |
1482 | static inline bool cpu_has_vmx_pml(void) |
1483 | { | |
1484 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1485 | } | |
1486 | ||
64903d61 HZ |
1487 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1488 | { | |
1489 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1490 | SECONDARY_EXEC_TSC_SCALING; | |
1491 | } | |
1492 | ||
2a499e49 BD |
1493 | static inline bool cpu_has_vmx_vmfunc(void) |
1494 | { | |
1495 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1496 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
1497 | } | |
1498 | ||
04547156 SY |
1499 | static inline bool report_flexpriority(void) |
1500 | { | |
1501 | return flexpriority_enabled; | |
1502 | } | |
1503 | ||
c7c2c709 JM |
1504 | static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) |
1505 | { | |
1506 | return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low); | |
1507 | } | |
1508 | ||
fe3ef05c NHE |
1509 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1510 | { | |
1511 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1512 | } | |
1513 | ||
1514 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1515 | { | |
1516 | return (vmcs12->cpu_based_vm_exec_control & | |
1517 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1518 | (vmcs12->secondary_vm_exec_control & bit); | |
1519 | } | |
1520 | ||
f4124500 JK |
1521 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1522 | { | |
1523 | return vmcs12->pin_based_vm_exec_control & | |
1524 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1525 | } | |
1526 | ||
155a97a3 NHE |
1527 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1528 | { | |
1529 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1530 | } | |
1531 | ||
81dc01f7 WL |
1532 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1533 | { | |
3db13480 | 1534 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); |
81dc01f7 WL |
1535 | } |
1536 | ||
c5f983f6 BD |
1537 | static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) |
1538 | { | |
1539 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); | |
1540 | } | |
1541 | ||
f2b93280 WV |
1542 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1543 | { | |
1544 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1545 | } | |
1546 | ||
5c614b35 WL |
1547 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1548 | { | |
1549 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1550 | } | |
1551 | ||
82f0dd4b WV |
1552 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1553 | { | |
1554 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1555 | } | |
1556 | ||
608406e2 WV |
1557 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1558 | { | |
1559 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1560 | } | |
1561 | ||
705699a1 WV |
1562 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1563 | { | |
1564 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1565 | } | |
1566 | ||
27c42a1b BD |
1567 | static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) |
1568 | { | |
1569 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); | |
1570 | } | |
1571 | ||
41ab9372 BD |
1572 | static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) |
1573 | { | |
1574 | return nested_cpu_has_vmfunc(vmcs12) && | |
1575 | (vmcs12->vm_function_control & | |
1576 | VMX_VMFUNC_EPTP_SWITCHING); | |
1577 | } | |
1578 | ||
ef85b673 | 1579 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1580 | { |
1581 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1582 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1583 | } |
1584 | ||
533558bc JK |
1585 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1586 | u32 exit_intr_info, | |
1587 | unsigned long exit_qualification); | |
7c177938 NHE |
1588 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1589 | struct vmcs12 *vmcs12, | |
1590 | u32 reason, unsigned long qualification); | |
1591 | ||
8b9cf98c | 1592 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1593 | { |
1594 | int i; | |
1595 | ||
a2fa3e9f | 1596 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1597 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1598 | return i; |
1599 | return -1; | |
1600 | } | |
1601 | ||
2384d2b3 SY |
1602 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1603 | { | |
1604 | struct { | |
1605 | u64 vpid : 16; | |
1606 | u64 rsvd : 48; | |
1607 | u64 gva; | |
1608 | } operand = { vpid, 0, gva }; | |
1609 | ||
4ecac3fd | 1610 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1611 | /* CF==1 or ZF==1 --> rc = -1 */ |
1612 | "; ja 1f ; ud2 ; 1:" | |
1613 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1614 | } | |
1615 | ||
1439442c SY |
1616 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1617 | { | |
1618 | struct { | |
1619 | u64 eptp, gpa; | |
1620 | } operand = {eptp, gpa}; | |
1621 | ||
4ecac3fd | 1622 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1623 | /* CF==1 or ZF==1 --> rc = -1 */ |
1624 | "; ja 1f ; ud2 ; 1:\n" | |
1625 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1626 | } | |
1627 | ||
26bb0981 | 1628 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1629 | { |
1630 | int i; | |
1631 | ||
8b9cf98c | 1632 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1633 | if (i >= 0) |
a2fa3e9f | 1634 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1635 | return NULL; |
7725f0ba AK |
1636 | } |
1637 | ||
6aa8b732 AK |
1638 | static void vmcs_clear(struct vmcs *vmcs) |
1639 | { | |
1640 | u64 phys_addr = __pa(vmcs); | |
1641 | u8 error; | |
1642 | ||
4ecac3fd | 1643 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1644 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1645 | : "cc", "memory"); |
1646 | if (error) | |
1647 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1648 | vmcs, phys_addr); | |
1649 | } | |
1650 | ||
d462b819 NHE |
1651 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1652 | { | |
1653 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1654 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1655 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1656 | loaded_vmcs->cpu = -1; |
1657 | loaded_vmcs->launched = 0; | |
1658 | } | |
1659 | ||
7725b894 DX |
1660 | static void vmcs_load(struct vmcs *vmcs) |
1661 | { | |
1662 | u64 phys_addr = __pa(vmcs); | |
1663 | u8 error; | |
1664 | ||
1665 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1666 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1667 | : "cc", "memory"); |
1668 | if (error) | |
2844d849 | 1669 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1670 | vmcs, phys_addr); |
1671 | } | |
1672 | ||
2965faa5 | 1673 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1674 | /* |
1675 | * This bitmap is used to indicate whether the vmclear | |
1676 | * operation is enabled on all cpus. All disabled by | |
1677 | * default. | |
1678 | */ | |
1679 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1680 | ||
1681 | static inline void crash_enable_local_vmclear(int cpu) | |
1682 | { | |
1683 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1684 | } | |
1685 | ||
1686 | static inline void crash_disable_local_vmclear(int cpu) | |
1687 | { | |
1688 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1689 | } | |
1690 | ||
1691 | static inline int crash_local_vmclear_enabled(int cpu) | |
1692 | { | |
1693 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1694 | } | |
1695 | ||
1696 | static void crash_vmclear_local_loaded_vmcss(void) | |
1697 | { | |
1698 | int cpu = raw_smp_processor_id(); | |
1699 | struct loaded_vmcs *v; | |
1700 | ||
1701 | if (!crash_local_vmclear_enabled(cpu)) | |
1702 | return; | |
1703 | ||
1704 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1705 | loaded_vmcss_on_cpu_link) | |
1706 | vmcs_clear(v->vmcs); | |
1707 | } | |
1708 | #else | |
1709 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1710 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1711 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1712 | |
d462b819 | 1713 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1714 | { |
d462b819 | 1715 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1716 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1717 | |
d462b819 NHE |
1718 | if (loaded_vmcs->cpu != cpu) |
1719 | return; /* vcpu migration can race with cpu offline */ | |
1720 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1721 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1722 | crash_disable_local_vmclear(cpu); |
d462b819 | 1723 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1724 | |
1725 | /* | |
1726 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1727 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1728 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1729 | * then adds the vmcs into percpu list before it is deleted. | |
1730 | */ | |
1731 | smp_wmb(); | |
1732 | ||
d462b819 | 1733 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1734 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1735 | } |
1736 | ||
d462b819 | 1737 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1738 | { |
e6c7d321 XG |
1739 | int cpu = loaded_vmcs->cpu; |
1740 | ||
1741 | if (cpu != -1) | |
1742 | smp_call_function_single(cpu, | |
1743 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1744 | } |
1745 | ||
dd5f5341 | 1746 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1747 | { |
dd5f5341 | 1748 | if (vpid == 0) |
2384d2b3 SY |
1749 | return; |
1750 | ||
518c8aee | 1751 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1752 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1753 | } |
1754 | ||
b9d762fa GJ |
1755 | static inline void vpid_sync_vcpu_global(void) |
1756 | { | |
1757 | if (cpu_has_vmx_invvpid_global()) | |
1758 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1759 | } | |
1760 | ||
dd5f5341 | 1761 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1762 | { |
1763 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1764 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1765 | else |
1766 | vpid_sync_vcpu_global(); | |
1767 | } | |
1768 | ||
1439442c SY |
1769 | static inline void ept_sync_global(void) |
1770 | { | |
f5f51586 | 1771 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
1439442c SY |
1772 | } |
1773 | ||
1774 | static inline void ept_sync_context(u64 eptp) | |
1775 | { | |
0e1252dc DH |
1776 | if (cpu_has_vmx_invept_context()) |
1777 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1778 | else | |
1779 | ept_sync_global(); | |
1439442c SY |
1780 | } |
1781 | ||
8a86aea9 PB |
1782 | static __always_inline void vmcs_check16(unsigned long field) |
1783 | { | |
1784 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1785 | "16-bit accessor invalid for 64-bit field"); | |
1786 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1787 | "16-bit accessor invalid for 64-bit high field"); | |
1788 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1789 | "16-bit accessor invalid for 32-bit high field"); | |
1790 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1791 | "16-bit accessor invalid for natural width field"); | |
1792 | } | |
1793 | ||
1794 | static __always_inline void vmcs_check32(unsigned long field) | |
1795 | { | |
1796 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1797 | "32-bit accessor invalid for 16-bit field"); | |
1798 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1799 | "32-bit accessor invalid for natural width field"); | |
1800 | } | |
1801 | ||
1802 | static __always_inline void vmcs_check64(unsigned long field) | |
1803 | { | |
1804 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1805 | "64-bit accessor invalid for 16-bit field"); | |
1806 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1807 | "64-bit accessor invalid for 64-bit high field"); | |
1808 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1809 | "64-bit accessor invalid for 32-bit field"); | |
1810 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1811 | "64-bit accessor invalid for natural width field"); | |
1812 | } | |
1813 | ||
1814 | static __always_inline void vmcs_checkl(unsigned long field) | |
1815 | { | |
1816 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1817 | "Natural width accessor invalid for 16-bit field"); | |
1818 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1819 | "Natural width accessor invalid for 64-bit field"); | |
1820 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1821 | "Natural width accessor invalid for 64-bit high field"); | |
1822 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1823 | "Natural width accessor invalid for 32-bit field"); | |
1824 | } | |
1825 | ||
1826 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1827 | { |
5e520e62 | 1828 | unsigned long value; |
6aa8b732 | 1829 | |
5e520e62 AK |
1830 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1831 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1832 | return value; |
1833 | } | |
1834 | ||
96304217 | 1835 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1836 | { |
8a86aea9 PB |
1837 | vmcs_check16(field); |
1838 | return __vmcs_readl(field); | |
6aa8b732 AK |
1839 | } |
1840 | ||
96304217 | 1841 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1842 | { |
8a86aea9 PB |
1843 | vmcs_check32(field); |
1844 | return __vmcs_readl(field); | |
6aa8b732 AK |
1845 | } |
1846 | ||
96304217 | 1847 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1848 | { |
8a86aea9 | 1849 | vmcs_check64(field); |
05b3e0c2 | 1850 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1851 | return __vmcs_readl(field); |
6aa8b732 | 1852 | #else |
8a86aea9 | 1853 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1854 | #endif |
1855 | } | |
1856 | ||
8a86aea9 PB |
1857 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1858 | { | |
1859 | vmcs_checkl(field); | |
1860 | return __vmcs_readl(field); | |
1861 | } | |
1862 | ||
e52de1b8 AK |
1863 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1864 | { | |
1865 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1866 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1867 | dump_stack(); | |
1868 | } | |
1869 | ||
8a86aea9 | 1870 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1871 | { |
1872 | u8 error; | |
1873 | ||
4ecac3fd | 1874 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1875 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1876 | if (unlikely(error)) |
1877 | vmwrite_error(field, value); | |
6aa8b732 AK |
1878 | } |
1879 | ||
8a86aea9 | 1880 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1881 | { |
8a86aea9 PB |
1882 | vmcs_check16(field); |
1883 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1884 | } |
1885 | ||
8a86aea9 | 1886 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1887 | { |
8a86aea9 PB |
1888 | vmcs_check32(field); |
1889 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1890 | } |
1891 | ||
8a86aea9 | 1892 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1893 | { |
8a86aea9 PB |
1894 | vmcs_check64(field); |
1895 | __vmcs_writel(field, value); | |
7682f2d0 | 1896 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1897 | asm volatile (""); |
8a86aea9 | 1898 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1899 | #endif |
1900 | } | |
1901 | ||
8a86aea9 | 1902 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1903 | { |
8a86aea9 PB |
1904 | vmcs_checkl(field); |
1905 | __vmcs_writel(field, value); | |
2ab455cc AL |
1906 | } |
1907 | ||
8a86aea9 | 1908 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1909 | { |
8a86aea9 PB |
1910 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1911 | "vmcs_clear_bits does not support 64-bit fields"); | |
1912 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1913 | } |
1914 | ||
8a86aea9 | 1915 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1916 | { |
8a86aea9 PB |
1917 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1918 | "vmcs_set_bits does not support 64-bit fields"); | |
1919 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1920 | } |
1921 | ||
8391ce44 PB |
1922 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1923 | { | |
1924 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1925 | } | |
1926 | ||
2961e876 GN |
1927 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1928 | { | |
1929 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1930 | vmx->vm_entry_controls_shadow = val; | |
1931 | } | |
1932 | ||
1933 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1934 | { | |
1935 | if (vmx->vm_entry_controls_shadow != val) | |
1936 | vm_entry_controls_init(vmx, val); | |
1937 | } | |
1938 | ||
1939 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1940 | { | |
1941 | return vmx->vm_entry_controls_shadow; | |
1942 | } | |
1943 | ||
1944 | ||
1945 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1946 | { | |
1947 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1948 | } | |
1949 | ||
1950 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1951 | { | |
1952 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1953 | } | |
1954 | ||
8391ce44 PB |
1955 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1956 | { | |
1957 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1958 | } | |
1959 | ||
2961e876 GN |
1960 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1961 | { | |
1962 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1963 | vmx->vm_exit_controls_shadow = val; | |
1964 | } | |
1965 | ||
1966 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1967 | { | |
1968 | if (vmx->vm_exit_controls_shadow != val) | |
1969 | vm_exit_controls_init(vmx, val); | |
1970 | } | |
1971 | ||
1972 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1973 | { | |
1974 | return vmx->vm_exit_controls_shadow; | |
1975 | } | |
1976 | ||
1977 | ||
1978 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1979 | { | |
1980 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1981 | } | |
1982 | ||
1983 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1984 | { | |
1985 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1986 | } | |
1987 | ||
2fb92db1 AK |
1988 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1989 | { | |
1990 | vmx->segment_cache.bitmask = 0; | |
1991 | } | |
1992 | ||
1993 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1994 | unsigned field) | |
1995 | { | |
1996 | bool ret; | |
1997 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1998 | ||
1999 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
2000 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
2001 | vmx->segment_cache.bitmask = 0; | |
2002 | } | |
2003 | ret = vmx->segment_cache.bitmask & mask; | |
2004 | vmx->segment_cache.bitmask |= mask; | |
2005 | return ret; | |
2006 | } | |
2007 | ||
2008 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
2009 | { | |
2010 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
2011 | ||
2012 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
2013 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
2014 | return *p; | |
2015 | } | |
2016 | ||
2017 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
2018 | { | |
2019 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
2020 | ||
2021 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
2022 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
2023 | return *p; | |
2024 | } | |
2025 | ||
2026 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
2027 | { | |
2028 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
2029 | ||
2030 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
2031 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
2032 | return *p; | |
2033 | } | |
2034 | ||
2035 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
2036 | { | |
2037 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
2038 | ||
2039 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
2040 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
2041 | return *p; | |
2042 | } | |
2043 | ||
abd3f2d6 AK |
2044 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
2045 | { | |
2046 | u32 eb; | |
2047 | ||
bd89525a | 2048 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 2049 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
2050 | if ((vcpu->guest_debug & |
2051 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
2052 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
2053 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 2054 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 2055 | eb = ~0; |
089d034e | 2056 | if (enable_ept) |
1439442c | 2057 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
2058 | |
2059 | /* When we are running a nested L2 guest and L1 specified for it a | |
2060 | * certain exception bitmap, we must trap the same exceptions and pass | |
2061 | * them to L1. When running L2, we will only handle the exceptions | |
2062 | * specified above if L1 did not want them. | |
2063 | */ | |
2064 | if (is_guest_mode(vcpu)) | |
2065 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
2066 | ||
abd3f2d6 AK |
2067 | vmcs_write32(EXCEPTION_BITMAP, eb); |
2068 | } | |
2069 | ||
74469996 KA |
2070 | /* |
2071 | * Check if MSR is intercepted for currently loaded MSR bitmap. | |
2072 | */ | |
2073 | static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) | |
2074 | { | |
2075 | unsigned long *msr_bitmap; | |
2076 | int f = sizeof(unsigned long); | |
2077 | ||
2078 | if (!cpu_has_vmx_msr_bitmap()) | |
2079 | return true; | |
2080 | ||
2081 | msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; | |
2082 | ||
2083 | if (msr <= 0x1fff) { | |
2084 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
2085 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2086 | msr &= 0x1fff; | |
2087 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
2088 | } | |
2089 | ||
2090 | return true; | |
2091 | } | |
2092 | ||
33241bfe AR |
2093 | /* |
2094 | * Check if MSR is intercepted for L01 MSR bitmap. | |
2095 | */ | |
2096 | static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr) | |
2097 | { | |
2098 | unsigned long *msr_bitmap; | |
2099 | int f = sizeof(unsigned long); | |
2100 | ||
2101 | if (!cpu_has_vmx_msr_bitmap()) | |
2102 | return true; | |
2103 | ||
2104 | msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; | |
2105 | ||
2106 | if (msr <= 0x1fff) { | |
2107 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
2108 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2109 | msr &= 0x1fff; | |
2110 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
2111 | } | |
2112 | ||
2113 | return true; | |
2114 | } | |
2115 | ||
2961e876 GN |
2116 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
2117 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 2118 | { |
2961e876 GN |
2119 | vm_entry_controls_clearbit(vmx, entry); |
2120 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
2121 | } |
2122 | ||
d8066b74 KRW |
2123 | static int find_msr(struct vmx_msrs *m, unsigned int msr) |
2124 | { | |
2125 | unsigned int i; | |
2126 | ||
2127 | for (i = 0; i < m->nr; ++i) { | |
2128 | if (m->val[i].index == msr) | |
2129 | return i; | |
2130 | } | |
2131 | return -ENOENT; | |
2132 | } | |
2133 | ||
61d2ef2c AK |
2134 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
2135 | { | |
d8066b74 | 2136 | int i; |
61d2ef2c AK |
2137 | struct msr_autoload *m = &vmx->msr_autoload; |
2138 | ||
8bf00a52 GN |
2139 | switch (msr) { |
2140 | case MSR_EFER: | |
2141 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
2142 | clear_atomic_switch_msr_special(vmx, |
2143 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
2144 | VM_EXIT_LOAD_IA32_EFER); |
2145 | return; | |
2146 | } | |
2147 | break; | |
2148 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2149 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 2150 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
2151 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
2152 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
2153 | return; | |
2154 | } | |
2155 | break; | |
110312c8 | 2156 | } |
d8066b74 KRW |
2157 | i = find_msr(&m->guest, msr); |
2158 | if (i < 0) | |
0666648b | 2159 | goto skip_guest; |
6e3dedb6 | 2160 | --m->guest.nr; |
6e3dedb6 | 2161 | m->guest.val[i] = m->guest.val[m->guest.nr]; |
6e3dedb6 | 2162 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); |
0666648b KRW |
2163 | |
2164 | skip_guest: | |
2165 | i = find_msr(&m->host, msr); | |
2166 | if (i < 0) | |
2167 | return; | |
2168 | ||
2169 | --m->host.nr; | |
2170 | m->host.val[i] = m->host.val[m->host.nr]; | |
6e3dedb6 | 2171 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); |
61d2ef2c AK |
2172 | } |
2173 | ||
2961e876 GN |
2174 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
2175 | unsigned long entry, unsigned long exit, | |
2176 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
2177 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
2178 | { |
2179 | vmcs_write64(guest_val_vmcs, guest_val); | |
2180 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
2181 | vm_entry_controls_setbit(vmx, entry); |
2182 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
2183 | } |
2184 | ||
61d2ef2c | 2185 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
129ce7ac | 2186 | u64 guest_val, u64 host_val, bool entry_only) |
61d2ef2c | 2187 | { |
129ce7ac | 2188 | int i, j = 0; |
61d2ef2c AK |
2189 | struct msr_autoload *m = &vmx->msr_autoload; |
2190 | ||
8bf00a52 GN |
2191 | switch (msr) { |
2192 | case MSR_EFER: | |
2193 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
2194 | add_atomic_switch_msr_special(vmx, |
2195 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
2196 | VM_EXIT_LOAD_IA32_EFER, |
2197 | GUEST_IA32_EFER, | |
2198 | HOST_IA32_EFER, | |
2199 | guest_val, host_val); | |
2200 | return; | |
2201 | } | |
2202 | break; | |
2203 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2204 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 2205 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
2206 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
2207 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
2208 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
2209 | HOST_IA32_PERF_GLOBAL_CTRL, | |
2210 | guest_val, host_val); | |
2211 | return; | |
2212 | } | |
2213 | break; | |
7099e2e1 RK |
2214 | case MSR_IA32_PEBS_ENABLE: |
2215 | /* PEBS needs a quiescent period after being disabled (to write | |
2216 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
2217 | * provide that period, so a CPU could write host's record into | |
2218 | * guest's memory. | |
2219 | */ | |
2220 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
2221 | } |
2222 | ||
d8066b74 | 2223 | i = find_msr(&m->guest, msr); |
129ce7ac KRW |
2224 | if (!entry_only) |
2225 | j = find_msr(&m->host, msr); | |
2226 | ||
0666648b | 2227 | if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) { |
60266204 | 2228 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
2229 | "Can't add msr %x\n", msr); |
2230 | return; | |
0666648b KRW |
2231 | } |
2232 | if (i < 0) { | |
d8066b74 | 2233 | i = m->guest.nr++; |
6e3dedb6 | 2234 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); |
0666648b | 2235 | } |
129ce7ac KRW |
2236 | m->guest.val[i].index = msr; |
2237 | m->guest.val[i].value = guest_val; | |
2238 | ||
2239 | if (entry_only) | |
2240 | return; | |
2241 | ||
0666648b KRW |
2242 | if (j < 0) { |
2243 | j = m->host.nr++; | |
6e3dedb6 | 2244 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); |
61d2ef2c | 2245 | } |
0666648b KRW |
2246 | m->host.val[j].index = msr; |
2247 | m->host.val[j].value = host_val; | |
61d2ef2c AK |
2248 | } |
2249 | ||
92c0d900 | 2250 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2251 | { |
844a5fe2 PB |
2252 | u64 guest_efer = vmx->vcpu.arch.efer; |
2253 | u64 ignore_bits = 0; | |
2254 | ||
2255 | if (!enable_ept) { | |
2256 | /* | |
2257 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
2258 | * host CPUID is more efficient than testing guest CPUID | |
2259 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2260 | */ | |
2261 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2262 | guest_efer |= EFER_NX; | |
2263 | else if (!(guest_efer & EFER_NX)) | |
2264 | ignore_bits |= EFER_NX; | |
2265 | } | |
3a34a881 | 2266 | |
51c6cf66 | 2267 | /* |
844a5fe2 | 2268 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2269 | */ |
844a5fe2 | 2270 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2271 | #ifdef CONFIG_X86_64 |
2272 | ignore_bits |= EFER_LMA | EFER_LME; | |
2273 | /* SCE is meaningful only in long mode on Intel */ | |
2274 | if (guest_efer & EFER_LMA) | |
2275 | ignore_bits &= ~(u64)EFER_SCE; | |
2276 | #endif | |
84ad33ef AK |
2277 | |
2278 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2279 | |
2280 | /* | |
2281 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2282 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2283 | * atomically, since it's faster than switching it manually. | |
2284 | */ | |
2285 | if (cpu_has_load_ia32_efer || | |
2286 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2287 | if (!(guest_efer & EFER_LMA)) |
2288 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2289 | if (guest_efer != host_efer) |
2290 | add_atomic_switch_msr(vmx, MSR_EFER, | |
129ce7ac | 2291 | guest_efer, host_efer, false); |
84ad33ef | 2292 | return false; |
844a5fe2 PB |
2293 | } else { |
2294 | guest_efer &= ~ignore_bits; | |
2295 | guest_efer |= host_efer & ignore_bits; | |
2296 | ||
2297 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2298 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2299 | |
844a5fe2 PB |
2300 | return true; |
2301 | } | |
51c6cf66 AK |
2302 | } |
2303 | ||
e28baead AL |
2304 | #ifdef CONFIG_X86_32 |
2305 | /* | |
2306 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2307 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2308 | * out the current bases to poke them into the VMCS before entry. | |
2309 | */ | |
2d49ec72 GN |
2310 | static unsigned long segment_base(u16 selector) |
2311 | { | |
8c2e41f7 | 2312 | struct desc_struct *table; |
2d49ec72 GN |
2313 | unsigned long v; |
2314 | ||
8c2e41f7 | 2315 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2316 | return 0; |
2317 | ||
45fc8757 | 2318 | table = get_current_gdt_ro(); |
2d49ec72 | 2319 | |
8c2e41f7 | 2320 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2321 | u16 ldt_selector = kvm_read_ldt(); |
2322 | ||
8c2e41f7 | 2323 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2324 | return 0; |
2325 | ||
8c2e41f7 | 2326 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2327 | } |
8c2e41f7 | 2328 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2329 | return v; |
2330 | } | |
e28baead | 2331 | #endif |
2d49ec72 | 2332 | |
04d2cc77 | 2333 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2334 | { |
04d2cc77 | 2335 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2336 | int i; |
04d2cc77 | 2337 | |
a2fa3e9f | 2338 | if (vmx->host_state.loaded) |
33ed6329 AK |
2339 | return; |
2340 | ||
a2fa3e9f | 2341 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2342 | /* |
2343 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2344 | * allow segment selectors with cpl > 0 or ti == 1. | |
2345 | */ | |
d6e88aec | 2346 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2347 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2348 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2349 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2350 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2351 | vmx->host_state.fs_reload_needed = 0; |
2352 | } else { | |
33ed6329 | 2353 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2354 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2355 | } |
9581d442 | 2356 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2357 | if (!(vmx->host_state.gs_sel & 7)) |
2358 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2359 | else { |
2360 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2361 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2362 | } |
2363 | ||
b2da15ac AK |
2364 | #ifdef CONFIG_X86_64 |
2365 | savesegment(ds, vmx->host_state.ds_sel); | |
2366 | savesegment(es, vmx->host_state.es_sel); | |
2367 | #endif | |
2368 | ||
33ed6329 AK |
2369 | #ifdef CONFIG_X86_64 |
2370 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2371 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2372 | #else | |
a2fa3e9f GH |
2373 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2374 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2375 | #endif |
707c0874 AK |
2376 | |
2377 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2378 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2379 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2380 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2381 | #endif |
da8999d3 LJ |
2382 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2383 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2384 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2385 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2386 | vmx->guest_msrs[i].data, |
2387 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2388 | } |
2389 | ||
a9b21b62 | 2390 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2391 | { |
a2fa3e9f | 2392 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2393 | return; |
2394 | ||
e1beb1d3 | 2395 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2396 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2397 | #ifdef CONFIG_X86_64 |
2398 | if (is_long_mode(&vmx->vcpu)) | |
2399 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2400 | #endif | |
152d3f2f | 2401 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2402 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2403 | #ifdef CONFIG_X86_64 |
9581d442 | 2404 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2405 | #else |
2406 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2407 | #endif |
33ed6329 | 2408 | } |
0a77fe4c AK |
2409 | if (vmx->host_state.fs_reload_needed) |
2410 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2411 | #ifdef CONFIG_X86_64 |
2412 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2413 | loadsegment(ds, vmx->host_state.ds_sel); | |
2414 | loadsegment(es, vmx->host_state.es_sel); | |
2415 | } | |
b2da15ac | 2416 | #endif |
b7ffc44d | 2417 | invalidate_tss_limit(); |
44ea2b17 | 2418 | #ifdef CONFIG_X86_64 |
c8770e7b | 2419 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2420 | #endif |
da8999d3 LJ |
2421 | if (vmx->host_state.msr_host_bndcfgs) |
2422 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
45fc8757 | 2423 | load_fixmap_gdt(raw_smp_processor_id()); |
33ed6329 AK |
2424 | } |
2425 | ||
a9b21b62 AK |
2426 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2427 | { | |
2428 | preempt_disable(); | |
2429 | __vmx_load_host_state(vmx); | |
2430 | preempt_enable(); | |
2431 | } | |
2432 | ||
28b835d6 FW |
2433 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2434 | { | |
2435 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2436 | struct pi_desc old, new; | |
2437 | unsigned int dest; | |
2438 | ||
31afb2ea PB |
2439 | /* |
2440 | * In case of hot-plug or hot-unplug, we may have to undo | |
2441 | * vmx_vcpu_pi_put even if there is no assigned device. And we | |
2442 | * always keep PI.NDST up to date for simplicity: it makes the | |
2443 | * code easier, and CPU migration is not a fast path. | |
2444 | */ | |
2445 | if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) | |
28b835d6 FW |
2446 | return; |
2447 | ||
31afb2ea PB |
2448 | /* |
2449 | * First handle the simple case where no cmpxchg is necessary; just | |
2450 | * allow posting non-urgent interrupts. | |
2451 | * | |
2452 | * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change | |
2453 | * PI.NDST: pi_post_block will do it for us and the wakeup_handler | |
2454 | * expects the VCPU to be on the blocked_vcpu_list that matches | |
2455 | * PI.NDST. | |
2456 | */ | |
2457 | if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || | |
2458 | vcpu->cpu == cpu) { | |
2459 | pi_clear_sn(pi_desc); | |
28b835d6 | 2460 | return; |
31afb2ea | 2461 | } |
28b835d6 | 2462 | |
31afb2ea | 2463 | /* The full case. */ |
28b835d6 FW |
2464 | do { |
2465 | old.control = new.control = pi_desc->control; | |
2466 | ||
31afb2ea | 2467 | dest = cpu_physical_id(cpu); |
28b835d6 | 2468 | |
31afb2ea PB |
2469 | if (x2apic_enabled()) |
2470 | new.ndst = dest; | |
2471 | else | |
2472 | new.ndst = (dest << 8) & 0xFF00; | |
28b835d6 | 2473 | |
28b835d6 | 2474 | new.sn = 0; |
c0a1666b PB |
2475 | } while (cmpxchg64(&pi_desc->control, old.control, |
2476 | new.control) != old.control); | |
28b835d6 | 2477 | } |
1be0e61c | 2478 | |
c95ba92a PF |
2479 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2480 | { | |
2481 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2482 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2483 | } | |
2484 | ||
6aa8b732 AK |
2485 | /* |
2486 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2487 | * vcpu mutex is already taken. | |
2488 | */ | |
15ad7146 | 2489 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2490 | { |
a2fa3e9f | 2491 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2492 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2493 | |
b80c76ec | 2494 | if (!already_loaded) { |
fe0e80be | 2495 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2496 | local_irq_disable(); |
8f536b76 | 2497 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2498 | |
2499 | /* | |
2500 | * Read loaded_vmcs->cpu should be before fetching | |
2501 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2502 | * See the comments in __loaded_vmcs_clear(). | |
2503 | */ | |
2504 | smp_rmb(); | |
2505 | ||
d462b819 NHE |
2506 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2507 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2508 | crash_enable_local_vmclear(cpu); |
92fe13be | 2509 | local_irq_enable(); |
b80c76ec JM |
2510 | } |
2511 | ||
2512 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2513 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2514 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
33241bfe | 2515 | indirect_branch_prediction_barrier(); |
b80c76ec JM |
2516 | } |
2517 | ||
2518 | if (!already_loaded) { | |
59c58ceb | 2519 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
2520 | unsigned long sysenter_esp; |
2521 | ||
2522 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2523 | |
6aa8b732 AK |
2524 | /* |
2525 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2526 | * processors. See 22.2.4. |
6aa8b732 | 2527 | */ |
e0c23063 | 2528 | vmcs_writel(HOST_TR_BASE, |
72f5e08d | 2529 | (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); |
59c58ceb | 2530 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 | 2531 | |
b7ffc44d AL |
2532 | /* |
2533 | * VM exits change the host TR limit to 0x67 after a VM | |
2534 | * exit. This is okay, since 0x67 covers everything except | |
2535 | * the IO bitmap and have have code to handle the IO bitmap | |
2536 | * being lost after a VM exit. | |
2537 | */ | |
2538 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2539 | ||
6aa8b732 AK |
2540 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2541 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2542 | |
d462b819 | 2543 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2544 | } |
28b835d6 | 2545 | |
2680d6da OH |
2546 | /* Setup TSC multiplier */ |
2547 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2548 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2549 | decache_tsc_multiplier(vmx); | |
2680d6da | 2550 | |
28b835d6 | 2551 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2552 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2553 | } |
2554 | ||
2555 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2556 | { | |
2557 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2558 | ||
2559 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2560 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2561 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2562 | return; |
2563 | ||
2564 | /* Set SN when the vCPU is preempted */ | |
2565 | if (vcpu->preempted) | |
2566 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2567 | } |
2568 | ||
2569 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2570 | { | |
28b835d6 FW |
2571 | vmx_vcpu_pi_put(vcpu); |
2572 | ||
a9b21b62 | 2573 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2574 | } |
2575 | ||
f244deed WL |
2576 | static bool emulation_required(struct kvm_vcpu *vcpu) |
2577 | { | |
2578 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
2579 | } | |
2580 | ||
edcafe3c AK |
2581 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2582 | ||
fe3ef05c NHE |
2583 | /* |
2584 | * Return the cr0 value that a nested guest would read. This is a combination | |
2585 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2586 | * its hypervisor (cr0_read_shadow). | |
2587 | */ | |
2588 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2589 | { | |
2590 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2591 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2592 | } | |
2593 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2594 | { | |
2595 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2596 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2597 | } | |
2598 | ||
6aa8b732 AK |
2599 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2600 | { | |
78ac8b47 | 2601 | unsigned long rflags, save_rflags; |
345dcaa8 | 2602 | |
6de12732 AK |
2603 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2604 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2605 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2606 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2607 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2608 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2609 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2610 | } | |
2611 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2612 | } |
6de12732 | 2613 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2614 | } |
2615 | ||
2616 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2617 | { | |
f244deed WL |
2618 | unsigned long old_rflags = vmx_get_rflags(vcpu); |
2619 | ||
6de12732 AK |
2620 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2621 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2622 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2623 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2624 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2625 | } |
6aa8b732 | 2626 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed WL |
2627 | |
2628 | if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) | |
2629 | to_vmx(vcpu)->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
2630 | } |
2631 | ||
37ccdcbe | 2632 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2633 | { |
2634 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2635 | int ret = 0; | |
2636 | ||
2637 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2638 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2639 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2640 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2641 | |
37ccdcbe | 2642 | return ret; |
2809f5d2 GC |
2643 | } |
2644 | ||
2645 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2646 | { | |
2647 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2648 | u32 interruptibility = interruptibility_old; | |
2649 | ||
2650 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2651 | ||
48005f64 | 2652 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2653 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2654 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2655 | interruptibility |= GUEST_INTR_STATE_STI; |
2656 | ||
2657 | if ((interruptibility != interruptibility_old)) | |
2658 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2659 | } | |
2660 | ||
6aa8b732 AK |
2661 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2662 | { | |
2663 | unsigned long rip; | |
6aa8b732 | 2664 | |
5fdbf976 | 2665 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2666 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2667 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2668 | |
2809f5d2 GC |
2669 | /* skipping an emulated instruction also counts */ |
2670 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2671 | } |
2672 | ||
b96fb439 PB |
2673 | static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, |
2674 | unsigned long exit_qual) | |
2675 | { | |
2676 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2677 | unsigned int nr = vcpu->arch.exception.nr; | |
2678 | u32 intr_info = nr | INTR_INFO_VALID_MASK; | |
2679 | ||
2680 | if (vcpu->arch.exception.has_error_code) { | |
2681 | vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; | |
2682 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | |
2683 | } | |
2684 | ||
2685 | if (kvm_exception_is_soft(nr)) | |
2686 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
2687 | else | |
2688 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2689 | ||
2690 | if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && | |
2691 | vmx_get_nmi_mask(vcpu)) | |
2692 | intr_info |= INTR_INFO_UNBLOCK_NMI; | |
2693 | ||
2694 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); | |
2695 | } | |
2696 | ||
0b6ac343 NHE |
2697 | /* |
2698 | * KVM wants to inject page-faults which it got to the guest. This function | |
2699 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2700 | */ |
bfcf83b1 | 2701 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) |
0b6ac343 NHE |
2702 | { |
2703 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
adfe20fb | 2704 | unsigned int nr = vcpu->arch.exception.nr; |
0b6ac343 | 2705 | |
b96fb439 PB |
2706 | if (nr == PF_VECTOR) { |
2707 | if (vcpu->arch.exception.nested_apf) { | |
bfcf83b1 | 2708 | *exit_qual = vcpu->arch.apf.nested_apf_token; |
b96fb439 PB |
2709 | return 1; |
2710 | } | |
2711 | /* | |
2712 | * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception. | |
2713 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2714 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 | |
2715 | * can be written only when inject_pending_event runs. This should be | |
2716 | * conditional on a new capability---if the capability is disabled, | |
2717 | * kvm_multiple_exception would write the ancillary information to | |
2718 | * CR2 or DR6, for backwards ABI-compatibility. | |
2719 | */ | |
2720 | if (nested_vmx_is_page_fault_vmexit(vmcs12, | |
2721 | vcpu->arch.exception.error_code)) { | |
bfcf83b1 | 2722 | *exit_qual = vcpu->arch.cr2; |
b96fb439 PB |
2723 | return 1; |
2724 | } | |
2725 | } else { | |
b96fb439 | 2726 | if (vmcs12->exception_bitmap & (1u << nr)) { |
bfcf83b1 WL |
2727 | if (nr == DB_VECTOR) |
2728 | *exit_qual = vcpu->arch.dr6; | |
2729 | else | |
2730 | *exit_qual = 0; | |
b96fb439 PB |
2731 | return 1; |
2732 | } | |
adfe20fb WL |
2733 | } |
2734 | ||
b96fb439 | 2735 | return 0; |
0b6ac343 NHE |
2736 | } |
2737 | ||
cfcd20e5 | 2738 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 2739 | { |
77ab6db0 | 2740 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
2741 | unsigned nr = vcpu->arch.exception.nr; |
2742 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 2743 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 2744 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2745 | |
8ab2d2e2 | 2746 | if (has_error_code) { |
77ab6db0 | 2747 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2748 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2749 | } | |
77ab6db0 | 2750 | |
7ffd92c5 | 2751 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2752 | int inc_eip = 0; |
2753 | if (kvm_exception_is_soft(nr)) | |
2754 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2755 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2756 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2757 | return; |
2758 | } | |
2759 | ||
299f0328 SC |
2760 | WARN_ON_ONCE(vmx->emulation_required); |
2761 | ||
66fd3f7f GN |
2762 | if (kvm_exception_is_soft(nr)) { |
2763 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2764 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2765 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2766 | } else | |
2767 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2768 | ||
2769 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2770 | } |
2771 | ||
4e47c7a6 SY |
2772 | static bool vmx_rdtscp_supported(void) |
2773 | { | |
2774 | return cpu_has_vmx_rdtscp(); | |
2775 | } | |
2776 | ||
ad756a16 MJ |
2777 | static bool vmx_invpcid_supported(void) |
2778 | { | |
2779 | return cpu_has_vmx_invpcid() && enable_ept; | |
2780 | } | |
2781 | ||
a75beee6 ED |
2782 | /* |
2783 | * Swap MSR entry in host/guest MSR entry array. | |
2784 | */ | |
8b9cf98c | 2785 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2786 | { |
26bb0981 | 2787 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2788 | |
2789 | tmp = vmx->guest_msrs[to]; | |
2790 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2791 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2792 | } |
2793 | ||
e38aea3e AK |
2794 | /* |
2795 | * Set up the vmcs to automatically save and restore system | |
2796 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2797 | * mode, as fiddling with msrs is very expensive. | |
2798 | */ | |
8b9cf98c | 2799 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2800 | { |
26bb0981 | 2801 | int save_nmsrs, index; |
e38aea3e | 2802 | |
a75beee6 ED |
2803 | save_nmsrs = 0; |
2804 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2805 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2806 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2807 | if (index >= 0) |
8b9cf98c RR |
2808 | move_msr_up(vmx, index, save_nmsrs++); |
2809 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2810 | if (index >= 0) |
8b9cf98c RR |
2811 | move_msr_up(vmx, index, save_nmsrs++); |
2812 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2813 | if (index >= 0) |
8b9cf98c | 2814 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2815 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
d6321d49 | 2816 | if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) |
4e47c7a6 | 2817 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2818 | /* |
8c06585d | 2819 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2820 | * if efer.sce is enabled. |
2821 | */ | |
8c06585d | 2822 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2823 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2824 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2825 | } |
2826 | #endif | |
92c0d900 AK |
2827 | index = __find_msr_index(vmx, MSR_EFER); |
2828 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2829 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2830 | |
26bb0981 | 2831 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2832 | |
8d14695f | 2833 | if (cpu_has_vmx_msr_bitmap()) |
4b0be90f | 2834 | vmx_update_msr_bitmap(&vmx->vcpu); |
e38aea3e AK |
2835 | } |
2836 | ||
f7f5542f KA |
2837 | static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) |
2838 | { | |
2839 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2840 | ||
2841 | if (is_guest_mode(vcpu) && | |
2842 | (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) | |
2843 | return vcpu->arch.tsc_offset - vmcs12->tsc_offset; | |
2844 | ||
2845 | return vcpu->arch.tsc_offset; | |
2846 | } | |
2847 | ||
6aa8b732 | 2848 | /* |
99e3e30a | 2849 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2850 | */ |
99e3e30a | 2851 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2852 | { |
27fc51b2 | 2853 | if (is_guest_mode(vcpu)) { |
7991825b | 2854 | /* |
27fc51b2 NHE |
2855 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2856 | * to the spec, this should set L1's TSC; The offset that L1 | |
2857 | * set for L2 remains unchanged, and still needs to be added | |
2858 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2859 | */ |
27fc51b2 | 2860 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2861 | /* recalculate vmcs02.TSC_OFFSET: */ |
2862 | vmcs12 = get_vmcs12(vcpu); | |
2863 | vmcs_write64(TSC_OFFSET, offset + | |
2864 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2865 | vmcs12->tsc_offset : 0)); | |
2866 | } else { | |
489223ed YY |
2867 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2868 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2869 | vmcs_write64(TSC_OFFSET, offset); |
2870 | } | |
6aa8b732 AK |
2871 | } |
2872 | ||
801d3424 NHE |
2873 | /* |
2874 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2875 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2876 | * all guests if the "nested" module option is off, and can also be disabled | |
2877 | * for a single guest by disabling its VMX cpuid bit. | |
2878 | */ | |
2879 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2880 | { | |
d6321d49 | 2881 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
2882 | } |
2883 | ||
b87a51ae NHE |
2884 | /* |
2885 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2886 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2887 | * The same values should also be used to verify that vmcs12 control fields are | |
2888 | * valid during nested entry from L1 to L2. | |
2889 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2890 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2891 | * bit in the high half is on if the corresponding bit in the control field | |
2892 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2893 | */ |
b9c237bb | 2894 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2895 | { |
2896 | /* | |
2897 | * Note that as a general rule, the high half of the MSRs (bits in | |
2898 | * the control fields which may be 1) should be initialized by the | |
2899 | * intersection of the underlying hardware's MSR (i.e., features which | |
2900 | * can be supported) and the list of features we want to expose - | |
2901 | * because they are known to be properly supported in our code. | |
2902 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2903 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2904 | * reason is that if one of these bits is necessary, it will appear | |
2905 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2906 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
7313c698 | 2907 | * nested_vmx_exit_reflected() will not pass related exits to L1. |
b87a51ae NHE |
2908 | * These rules have exceptions below. |
2909 | */ | |
2910 | ||
2911 | /* pin-based controls */ | |
eabeaacc | 2912 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2913 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2914 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2915 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2916 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2917 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2918 | PIN_BASED_EXT_INTR_MASK | | |
2919 | PIN_BASED_NMI_EXITING | | |
2920 | PIN_BASED_VIRTUAL_NMIS; | |
2921 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2922 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2923 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2924 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2925 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2926 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2927 | |
3dbcd8da | 2928 | /* exit controls */ |
c0dfee58 | 2929 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2930 | vmx->nested.nested_vmx_exit_ctls_low, |
2931 | vmx->nested.nested_vmx_exit_ctls_high); | |
2932 | vmx->nested.nested_vmx_exit_ctls_low = | |
2933 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2934 | |
b9c237bb | 2935 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2936 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2937 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2938 | #endif |
f4124500 | 2939 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2940 | vmx->nested.nested_vmx_exit_ctls_high |= |
2941 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2942 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2943 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2944 | ||
a87036ad | 2945 | if (kvm_mpx_supported()) |
b9c237bb | 2946 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2947 | |
2996fca0 | 2948 | /* We support free control of debug control saving. */ |
0115f9cb | 2949 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2950 | |
b87a51ae NHE |
2951 | /* entry controls */ |
2952 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2953 | vmx->nested.nested_vmx_entry_ctls_low, |
2954 | vmx->nested.nested_vmx_entry_ctls_high); | |
2955 | vmx->nested.nested_vmx_entry_ctls_low = | |
2956 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2957 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2958 | #ifdef CONFIG_X86_64 |
2959 | VM_ENTRY_IA32E_MODE | | |
2960 | #endif | |
2961 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2962 | vmx->nested.nested_vmx_entry_ctls_high |= |
2963 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2964 | if (kvm_mpx_supported()) |
b9c237bb | 2965 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2966 | |
2996fca0 | 2967 | /* We support free control of debug control loading. */ |
0115f9cb | 2968 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2969 | |
b87a51ae NHE |
2970 | /* cpu-based controls */ |
2971 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2972 | vmx->nested.nested_vmx_procbased_ctls_low, |
2973 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2974 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2975 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2976 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2977 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2978 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2979 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2980 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2981 | CPU_BASED_CR3_STORE_EXITING | | |
2982 | #ifdef CONFIG_X86_64 | |
2983 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2984 | #endif | |
2985 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2986 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2987 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2988 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2989 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2990 | /* |
2991 | * We can allow some features even when not supported by the | |
2992 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2993 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2994 | * without MSR bitmaps. | |
2995 | */ | |
b9c237bb WV |
2996 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2997 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2998 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2999 | |
3dcdf3ec | 3000 | /* We support free control of CR3 access interception. */ |
0115f9cb | 3001 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
3002 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
3003 | ||
80154d77 PB |
3004 | /* |
3005 | * secondary cpu-based controls. Do not include those that | |
3006 | * depend on CPUID bits, they are added later by vmx_cpuid_update. | |
3007 | */ | |
b87a51ae | 3008 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
b9c237bb WV |
3009 | vmx->nested.nested_vmx_secondary_ctls_low, |
3010 | vmx->nested.nested_vmx_secondary_ctls_high); | |
3011 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
3012 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 3013 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
1b07304c | 3014 | SECONDARY_EXEC_DESC | |
f2b93280 | 3015 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 3016 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 3017 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
3db13480 | 3018 | SECONDARY_EXEC_WBINVD_EXITING; |
c18911a2 | 3019 | |
afa61f75 NHE |
3020 | if (enable_ept) { |
3021 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 3022 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 3023 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 3024 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 3025 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 BD |
3026 | if (cpu_has_vmx_ept_execute_only()) |
3027 | vmx->nested.nested_vmx_ept_caps |= | |
3028 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 3029 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 | 3030 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
7db74265 PB |
3031 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
3032 | VMX_EPT_1GB_PAGE_BIT; | |
03efce6f BD |
3033 | if (enable_ept_ad_bits) { |
3034 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3035 | SECONDARY_EXEC_ENABLE_PML; | |
7461fbc4 | 3036 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT; |
03efce6f | 3037 | } |
1c13bffd | 3038 | } |
afa61f75 | 3039 | |
27c42a1b BD |
3040 | if (cpu_has_vmx_vmfunc()) { |
3041 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3042 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
41ab9372 BD |
3043 | /* |
3044 | * Advertise EPTP switching unconditionally | |
3045 | * since we emulate it | |
3046 | */ | |
575b3a2c WL |
3047 | if (enable_ept) |
3048 | vmx->nested.nested_vmx_vmfunc_controls = | |
3049 | VMX_VMFUNC_EPTP_SWITCHING; | |
27c42a1b BD |
3050 | } |
3051 | ||
ef697a71 PB |
3052 | /* |
3053 | * Old versions of KVM use the single-context version without | |
3054 | * checking for support, so declare that it is supported even | |
3055 | * though it is treated as global context. The alternative is | |
3056 | * not failing the single-context invvpid, and it is worse. | |
3057 | */ | |
63cb6d5f WL |
3058 | if (enable_vpid) { |
3059 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3060 | SECONDARY_EXEC_ENABLE_VPID; | |
089d7b6e | 3061 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 3062 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
1c13bffd | 3063 | } |
99b83ac8 | 3064 | |
0790ec17 RK |
3065 | if (enable_unrestricted_guest) |
3066 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3067 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
3068 | ||
c18911a2 | 3069 | /* miscellaneous data */ |
b9c237bb WV |
3070 | rdmsr(MSR_IA32_VMX_MISC, |
3071 | vmx->nested.nested_vmx_misc_low, | |
3072 | vmx->nested.nested_vmx_misc_high); | |
3073 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
3074 | vmx->nested.nested_vmx_misc_low |= | |
3075 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 3076 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 3077 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
3078 | |
3079 | /* | |
3080 | * This MSR reports some information about VMX support. We | |
3081 | * should return information about the VMX we emulate for the | |
3082 | * guest, and the VMCS structure we give it - not about the | |
3083 | * VMX support of the underlying hardware. | |
3084 | */ | |
3085 | vmx->nested.nested_vmx_basic = | |
3086 | VMCS12_REVISION | | |
3087 | VMX_BASIC_TRUE_CTLS | | |
3088 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
3089 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
3090 | ||
3091 | if (cpu_has_vmx_basic_inout()) | |
3092 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
3093 | ||
3094 | /* | |
8322ebbb | 3095 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
3096 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
3097 | * We picked the standard core2 setting. | |
3098 | */ | |
3099 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
3100 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
3101 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 3102 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
3103 | |
3104 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
3105 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
3106 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
3107 | |
3108 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
3109 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
3110 | } |
3111 | ||
3899152c DM |
3112 | /* |
3113 | * if fixed0[i] == 1: val[i] must be 1 | |
3114 | * if fixed1[i] == 0: val[i] must be 0 | |
3115 | */ | |
3116 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
3117 | { | |
3118 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
3119 | } |
3120 | ||
3121 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
3122 | { | |
3899152c | 3123 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
3124 | } |
3125 | ||
3126 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
3127 | { | |
3128 | return low | ((u64)high << 32); | |
3129 | } | |
3130 | ||
62cc6b9d DM |
3131 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
3132 | { | |
3133 | superset &= mask; | |
3134 | subset &= mask; | |
3135 | ||
3136 | return (superset | subset) == superset; | |
3137 | } | |
3138 | ||
3139 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
3140 | { | |
3141 | const u64 feature_and_reserved = | |
3142 | /* feature (except bit 48; see below) */ | |
3143 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
3144 | /* reserved */ | |
3145 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
3146 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
3147 | ||
3148 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
3149 | return -EINVAL; | |
3150 | ||
3151 | /* | |
3152 | * KVM does not emulate a version of VMX that constrains physical | |
3153 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
3154 | */ | |
3155 | if (data & BIT_ULL(48)) | |
3156 | return -EINVAL; | |
3157 | ||
3158 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
3159 | vmx_basic_vmcs_revision_id(data)) | |
3160 | return -EINVAL; | |
3161 | ||
3162 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
3163 | return -EINVAL; | |
3164 | ||
3165 | vmx->nested.nested_vmx_basic = data; | |
3166 | return 0; | |
3167 | } | |
3168 | ||
3169 | static int | |
3170 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3171 | { | |
3172 | u64 supported; | |
3173 | u32 *lowp, *highp; | |
3174 | ||
3175 | switch (msr_index) { | |
3176 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3177 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
3178 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
3179 | break; | |
3180 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3181 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
3182 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
3183 | break; | |
3184 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3185 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
3186 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
3187 | break; | |
3188 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3189 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
3190 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
3191 | break; | |
3192 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3193 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
3194 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
3195 | break; | |
3196 | default: | |
3197 | BUG(); | |
3198 | } | |
3199 | ||
3200 | supported = vmx_control_msr(*lowp, *highp); | |
3201 | ||
3202 | /* Check must-be-1 bits are still 1. */ | |
3203 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
3204 | return -EINVAL; | |
3205 | ||
3206 | /* Check must-be-0 bits are still 0. */ | |
3207 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
3208 | return -EINVAL; | |
3209 | ||
3210 | *lowp = data; | |
3211 | *highp = data >> 32; | |
3212 | return 0; | |
3213 | } | |
3214 | ||
3215 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
3216 | { | |
3217 | const u64 feature_and_reserved_bits = | |
3218 | /* feature */ | |
3219 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
3220 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
3221 | /* reserved */ | |
3222 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
3223 | u64 vmx_misc; | |
3224 | ||
3225 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
3226 | vmx->nested.nested_vmx_misc_high); | |
3227 | ||
3228 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3229 | return -EINVAL; | |
3230 | ||
3231 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
3232 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
3233 | vmx_misc_preemption_timer_rate(data) != | |
3234 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3235 | return -EINVAL; | |
3236 | ||
3237 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3238 | return -EINVAL; | |
3239 | ||
3240 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3241 | return -EINVAL; | |
3242 | ||
3243 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3244 | return -EINVAL; | |
3245 | ||
3246 | vmx->nested.nested_vmx_misc_low = data; | |
3247 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
3248 | return 0; | |
3249 | } | |
3250 | ||
3251 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3252 | { | |
3253 | u64 vmx_ept_vpid_cap; | |
3254 | ||
3255 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
3256 | vmx->nested.nested_vmx_vpid_caps); | |
3257 | ||
3258 | /* Every bit is either reserved or a feature bit. */ | |
3259 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3260 | return -EINVAL; | |
3261 | ||
3262 | vmx->nested.nested_vmx_ept_caps = data; | |
3263 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
3264 | return 0; | |
3265 | } | |
3266 | ||
3267 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3268 | { | |
3269 | u64 *msr; | |
3270 | ||
3271 | switch (msr_index) { | |
3272 | case MSR_IA32_VMX_CR0_FIXED0: | |
3273 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
3274 | break; | |
3275 | case MSR_IA32_VMX_CR4_FIXED0: | |
3276 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
3277 | break; | |
3278 | default: | |
3279 | BUG(); | |
3280 | } | |
3281 | ||
3282 | /* | |
3283 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3284 | * must be 1 in the restored value. | |
3285 | */ | |
3286 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3287 | return -EINVAL; | |
3288 | ||
3289 | *msr = data; | |
3290 | return 0; | |
3291 | } | |
3292 | ||
3293 | /* | |
3294 | * Called when userspace is restoring VMX MSRs. | |
3295 | * | |
3296 | * Returns 0 on success, non-0 otherwise. | |
3297 | */ | |
3298 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3299 | { |
b9c237bb WV |
3300 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3301 | ||
b87a51ae | 3302 | switch (msr_index) { |
b87a51ae | 3303 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3304 | return vmx_restore_vmx_basic(vmx, data); |
3305 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3306 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3307 | case MSR_IA32_VMX_EXIT_CTLS: | |
3308 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3309 | /* |
62cc6b9d DM |
3310 | * The "non-true" VMX capability MSRs are generated from the |
3311 | * "true" MSRs, so we do not support restoring them directly. | |
3312 | * | |
3313 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3314 | * should restore the "true" MSRs with the must-be-1 bits | |
3315 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3316 | * DEFAULT SETTINGS". | |
b87a51ae | 3317 | */ |
62cc6b9d DM |
3318 | return -EINVAL; |
3319 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3320 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3321 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3322 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3323 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3324 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3325 | case MSR_IA32_VMX_MISC: | |
3326 | return vmx_restore_vmx_misc(vmx, data); | |
3327 | case MSR_IA32_VMX_CR0_FIXED0: | |
3328 | case MSR_IA32_VMX_CR4_FIXED0: | |
3329 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3330 | case MSR_IA32_VMX_CR0_FIXED1: | |
3331 | case MSR_IA32_VMX_CR4_FIXED1: | |
3332 | /* | |
3333 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3334 | * do not support restoring them directly. | |
3335 | */ | |
3336 | return -EINVAL; | |
3337 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3338 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3339 | case MSR_IA32_VMX_VMCS_ENUM: | |
3340 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3341 | return 0; | |
3342 | default: | |
b87a51ae | 3343 | /* |
62cc6b9d | 3344 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3345 | */ |
62cc6b9d DM |
3346 | return -EINVAL; |
3347 | } | |
3348 | } | |
3349 | ||
3350 | /* Returns 0 on success, non-0 otherwise. */ | |
3351 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3352 | { | |
3353 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3354 | ||
3355 | switch (msr_index) { | |
3356 | case MSR_IA32_VMX_BASIC: | |
3357 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3358 | break; |
3359 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3360 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3361 | *pdata = vmx_control_msr( |
3362 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3363 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3364 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3365 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3366 | break; |
3367 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3368 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3369 | *pdata = vmx_control_msr( |
3370 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3371 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3372 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3373 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3374 | break; |
3375 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3376 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3377 | *pdata = vmx_control_msr( |
3378 | vmx->nested.nested_vmx_exit_ctls_low, | |
3379 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3380 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3381 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3382 | break; |
3383 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3384 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3385 | *pdata = vmx_control_msr( |
3386 | vmx->nested.nested_vmx_entry_ctls_low, | |
3387 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3388 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3389 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3390 | break; |
3391 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3392 | *pdata = vmx_control_msr( |
3393 | vmx->nested.nested_vmx_misc_low, | |
3394 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3395 | break; |
b87a51ae | 3396 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3397 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3398 | break; |
3399 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3400 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3401 | break; |
3402 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3403 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3404 | break; |
3405 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3406 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3407 | break; |
3408 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3409 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3410 | break; |
3411 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3412 | *pdata = vmx_control_msr( |
3413 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3414 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3415 | break; |
3416 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3417 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3418 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae | 3419 | break; |
27c42a1b BD |
3420 | case MSR_IA32_VMX_VMFUNC: |
3421 | *pdata = vmx->nested.nested_vmx_vmfunc_controls; | |
3422 | break; | |
b87a51ae | 3423 | default: |
b87a51ae | 3424 | return 1; |
b3897a49 NHE |
3425 | } |
3426 | ||
b87a51ae NHE |
3427 | return 0; |
3428 | } | |
3429 | ||
37e4c997 HZ |
3430 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3431 | uint64_t val) | |
3432 | { | |
3433 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3434 | ||
3435 | return !(val & ~valid_bits); | |
3436 | } | |
3437 | ||
ab1bebf8 TL |
3438 | static int vmx_get_msr_feature(struct kvm_msr_entry *msr) |
3439 | { | |
3440 | return 1; | |
3441 | } | |
3442 | ||
6aa8b732 AK |
3443 | /* |
3444 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3445 | * Returns 0 on success, non-0 otherwise. | |
3446 | * Assumes vcpu_load() was already called. | |
3447 | */ | |
609e36d3 | 3448 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3449 | { |
26bb0981 | 3450 | struct shared_msr_entry *msr; |
6aa8b732 | 3451 | |
609e36d3 | 3452 | switch (msr_info->index) { |
05b3e0c2 | 3453 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3454 | case MSR_FS_BASE: |
609e36d3 | 3455 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3456 | break; |
3457 | case MSR_GS_BASE: | |
609e36d3 | 3458 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3459 | break; |
44ea2b17 AK |
3460 | case MSR_KERNEL_GS_BASE: |
3461 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3462 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3463 | break; |
26bb0981 | 3464 | #endif |
6aa8b732 | 3465 | case MSR_EFER: |
609e36d3 | 3466 | return kvm_get_msr_common(vcpu, msr_info); |
74469996 KA |
3467 | case MSR_IA32_SPEC_CTRL: |
3468 | if (!msr_info->host_initiated && | |
5856293c | 3469 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
74469996 KA |
3470 | return 1; |
3471 | ||
3472 | msr_info->data = to_vmx(vcpu)->spec_ctrl; | |
3473 | break; | |
a6005a79 KA |
3474 | case MSR_IA32_ARCH_CAPABILITIES: |
3475 | if (!msr_info->host_initiated && | |
3476 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3477 | return 1; | |
3478 | msr_info->data = to_vmx(vcpu)->arch_capabilities; | |
3479 | break; | |
6aa8b732 | 3480 | case MSR_IA32_SYSENTER_CS: |
609e36d3 | 3481 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3482 | break; |
3483 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3484 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3485 | break; |
3486 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3487 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3488 | break; |
0dd376e7 | 3489 | case MSR_IA32_BNDCFGS: |
691bd434 | 3490 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3491 | (!msr_info->host_initiated && |
3492 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3493 | return 1; |
609e36d3 | 3494 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3495 | break; |
c45dcc71 AR |
3496 | case MSR_IA32_MCG_EXT_CTL: |
3497 | if (!msr_info->host_initiated && | |
3498 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3499 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3500 | return 1; |
c45dcc71 AR |
3501 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3502 | break; | |
cae50139 | 3503 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3504 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3505 | break; |
3506 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3507 | if (!nested_vmx_allowed(vcpu)) | |
3508 | return 1; | |
609e36d3 | 3509 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3510 | case MSR_IA32_XSS: |
3511 | if (!vmx_xsaves_supported()) | |
3512 | return 1; | |
609e36d3 | 3513 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3514 | break; |
4e47c7a6 | 3515 | case MSR_TSC_AUX: |
d6321d49 RK |
3516 | if (!msr_info->host_initiated && |
3517 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3518 | return 1; |
3519 | /* Otherwise falls through */ | |
6aa8b732 | 3520 | default: |
609e36d3 | 3521 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3522 | if (msr) { |
609e36d3 | 3523 | msr_info->data = msr->data; |
3bab1f5d | 3524 | break; |
6aa8b732 | 3525 | } |
609e36d3 | 3526 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3527 | } |
3528 | ||
6aa8b732 AK |
3529 | return 0; |
3530 | } | |
3531 | ||
cae50139 JK |
3532 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3533 | ||
6aa8b732 AK |
3534 | /* |
3535 | * Writes msr value into into the appropriate "register". | |
3536 | * Returns 0 on success, non-0 otherwise. | |
3537 | * Assumes vcpu_load() was already called. | |
3538 | */ | |
8fe8ab46 | 3539 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3540 | { |
a2fa3e9f | 3541 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3542 | struct shared_msr_entry *msr; |
2cc51560 | 3543 | int ret = 0; |
8fe8ab46 WA |
3544 | u32 msr_index = msr_info->index; |
3545 | u64 data = msr_info->data; | |
2cc51560 | 3546 | |
6aa8b732 | 3547 | switch (msr_index) { |
3bab1f5d | 3548 | case MSR_EFER: |
8fe8ab46 | 3549 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3550 | break; |
16175a79 | 3551 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3552 | case MSR_FS_BASE: |
2fb92db1 | 3553 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3554 | vmcs_writel(GUEST_FS_BASE, data); |
3555 | break; | |
3556 | case MSR_GS_BASE: | |
2fb92db1 | 3557 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3558 | vmcs_writel(GUEST_GS_BASE, data); |
3559 | break; | |
44ea2b17 AK |
3560 | case MSR_KERNEL_GS_BASE: |
3561 | vmx_load_host_state(vmx); | |
3562 | vmx->msr_guest_kernel_gs_base = data; | |
3563 | break; | |
6aa8b732 AK |
3564 | #endif |
3565 | case MSR_IA32_SYSENTER_CS: | |
3566 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3567 | break; | |
3568 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3569 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3570 | break; |
3571 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3572 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3573 | break; |
0dd376e7 | 3574 | case MSR_IA32_BNDCFGS: |
691bd434 | 3575 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3576 | (!msr_info->host_initiated && |
3577 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3578 | return 1; |
fd8cb433 | 3579 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 3580 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 3581 | return 1; |
0dd376e7 LJ |
3582 | vmcs_write64(GUEST_BNDCFGS, data); |
3583 | break; | |
74469996 KA |
3584 | case MSR_IA32_SPEC_CTRL: |
3585 | if (!msr_info->host_initiated && | |
5856293c | 3586 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
74469996 KA |
3587 | return 1; |
3588 | ||
3589 | /* The STIBP bit doesn't fault even if it's not advertised */ | |
8fe36c9d | 3590 | if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) |
74469996 KA |
3591 | return 1; |
3592 | ||
3593 | vmx->spec_ctrl = data; | |
3594 | ||
3595 | if (!data) | |
3596 | break; | |
3597 | ||
3598 | /* | |
3599 | * For non-nested: | |
3600 | * When it's written (to non-zero) for the first time, pass | |
3601 | * it through. | |
3602 | * | |
3603 | * For nested: | |
3604 | * The handling of the MSR bitmap for L2 guests is done in | |
3605 | * nested_vmx_merge_msr_bitmap. We should not touch the | |
3606 | * vmcs02.msr_bitmap here since it gets completely overwritten | |
3607 | * in the merging. We update the vmcs01 here for L1 as well | |
3608 | * since it will end up touching the MSR anyway now. | |
3609 | */ | |
3610 | vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, | |
3611 | MSR_IA32_SPEC_CTRL, | |
3612 | MSR_TYPE_RW); | |
3613 | break; | |
33241bfe AR |
3614 | case MSR_IA32_PRED_CMD: |
3615 | if (!msr_info->host_initiated && | |
33241bfe AR |
3616 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
3617 | return 1; | |
3618 | ||
3619 | if (data & ~PRED_CMD_IBPB) | |
3620 | return 1; | |
3621 | ||
3622 | if (!data) | |
3623 | break; | |
3624 | ||
3625 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
3626 | ||
3627 | /* | |
3628 | * For non-nested: | |
3629 | * When it's written (to non-zero) for the first time, pass | |
3630 | * it through. | |
3631 | * | |
3632 | * For nested: | |
3633 | * The handling of the MSR bitmap for L2 guests is done in | |
3634 | * nested_vmx_merge_msr_bitmap. We should not touch the | |
3635 | * vmcs02.msr_bitmap here since it gets completely overwritten | |
3636 | * in the merging. | |
3637 | */ | |
3638 | vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, | |
3639 | MSR_TYPE_W); | |
3640 | break; | |
a6005a79 KA |
3641 | case MSR_IA32_ARCH_CAPABILITIES: |
3642 | if (!msr_info->host_initiated) | |
3643 | return 1; | |
3644 | vmx->arch_capabilities = data; | |
3645 | break; | |
468d472f SY |
3646 | case MSR_IA32_CR_PAT: |
3647 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3648 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3649 | return 1; | |
468d472f SY |
3650 | vmcs_write64(GUEST_IA32_PAT, data); |
3651 | vcpu->arch.pat = data; | |
3652 | break; | |
3653 | } | |
8fe8ab46 | 3654 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3655 | break; |
ba904635 WA |
3656 | case MSR_IA32_TSC_ADJUST: |
3657 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3658 | break; |
c45dcc71 AR |
3659 | case MSR_IA32_MCG_EXT_CTL: |
3660 | if ((!msr_info->host_initiated && | |
3661 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3662 | FEATURE_CONTROL_LMCE)) || | |
3663 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3664 | return 1; | |
3665 | vcpu->arch.mcg_ext_ctl = data; | |
3666 | break; | |
cae50139 | 3667 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3668 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3669 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3670 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3671 | return 1; | |
3b84080b | 3672 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3673 | if (msr_info->host_initiated && data == 0) |
3674 | vmx_leave_nested(vcpu); | |
3675 | break; | |
3676 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3677 | if (!msr_info->host_initiated) |
3678 | return 1; /* they are read-only */ | |
3679 | if (!nested_vmx_allowed(vcpu)) | |
3680 | return 1; | |
3681 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3682 | case MSR_IA32_XSS: |
3683 | if (!vmx_xsaves_supported()) | |
3684 | return 1; | |
3685 | /* | |
3686 | * The only supported bit as of Skylake is bit 8, but | |
3687 | * it is not supported on KVM. | |
3688 | */ | |
3689 | if (data != 0) | |
3690 | return 1; | |
3691 | vcpu->arch.ia32_xss = data; | |
3692 | if (vcpu->arch.ia32_xss != host_xss) | |
3693 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
129ce7ac | 3694 | vcpu->arch.ia32_xss, host_xss, false); |
20300099 WL |
3695 | else |
3696 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3697 | break; | |
4e47c7a6 | 3698 | case MSR_TSC_AUX: |
d6321d49 RK |
3699 | if (!msr_info->host_initiated && |
3700 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3701 | return 1; |
3702 | /* Check reserved bit, higher 32 bits should be zero */ | |
3703 | if ((data >> 32) != 0) | |
3704 | return 1; | |
3705 | /* Otherwise falls through */ | |
6aa8b732 | 3706 | default: |
8b9cf98c | 3707 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3708 | if (msr) { |
8b3c3104 | 3709 | u64 old_msr_data = msr->data; |
3bab1f5d | 3710 | msr->data = data; |
2225fd56 AK |
3711 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3712 | preempt_disable(); | |
8b3c3104 AH |
3713 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3714 | msr->mask); | |
2225fd56 | 3715 | preempt_enable(); |
8b3c3104 AH |
3716 | if (ret) |
3717 | msr->data = old_msr_data; | |
2225fd56 | 3718 | } |
3bab1f5d | 3719 | break; |
6aa8b732 | 3720 | } |
8fe8ab46 | 3721 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3722 | } |
3723 | ||
2cc51560 | 3724 | return ret; |
6aa8b732 AK |
3725 | } |
3726 | ||
5fdbf976 | 3727 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3728 | { |
5fdbf976 MT |
3729 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3730 | switch (reg) { | |
3731 | case VCPU_REGS_RSP: | |
3732 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3733 | break; | |
3734 | case VCPU_REGS_RIP: | |
3735 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3736 | break; | |
6de4f3ad AK |
3737 | case VCPU_EXREG_PDPTR: |
3738 | if (enable_ept) | |
3739 | ept_save_pdptrs(vcpu); | |
3740 | break; | |
5fdbf976 MT |
3741 | default: |
3742 | break; | |
3743 | } | |
6aa8b732 AK |
3744 | } |
3745 | ||
6aa8b732 AK |
3746 | static __init int cpu_has_kvm_support(void) |
3747 | { | |
6210e37b | 3748 | return cpu_has_vmx(); |
6aa8b732 AK |
3749 | } |
3750 | ||
3751 | static __init int vmx_disabled_by_bios(void) | |
3752 | { | |
3753 | u64 msr; | |
3754 | ||
3755 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3756 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3757 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3758 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3759 | && tboot_enabled()) | |
3760 | return 1; | |
23f3e991 | 3761 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3762 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3763 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3764 | && !tboot_enabled()) { |
3765 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3766 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3767 | return 1; |
f9335afe | 3768 | } |
23f3e991 JC |
3769 | /* launched w/o TXT and VMX disabled */ |
3770 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3771 | && !tboot_enabled()) | |
3772 | return 1; | |
cafd6659 SW |
3773 | } |
3774 | ||
3775 | return 0; | |
6aa8b732 AK |
3776 | } |
3777 | ||
7725b894 DX |
3778 | static void kvm_cpu_vmxon(u64 addr) |
3779 | { | |
fe0e80be | 3780 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3781 | intel_pt_handle_vmx(1); |
3782 | ||
7725b894 DX |
3783 | asm volatile (ASM_VMX_VMXON_RAX |
3784 | : : "a"(&addr), "m"(addr) | |
3785 | : "memory", "cc"); | |
3786 | } | |
3787 | ||
13a34e06 | 3788 | static int hardware_enable(void) |
6aa8b732 AK |
3789 | { |
3790 | int cpu = raw_smp_processor_id(); | |
3791 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3792 | u64 old, test_bits; |
6aa8b732 | 3793 | |
1e02ce4c | 3794 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3795 | return -EBUSY; |
3796 | ||
d462b819 | 3797 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3798 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3799 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3800 | |
3801 | /* | |
3802 | * Now we can enable the vmclear operation in kdump | |
3803 | * since the loaded_vmcss_on_cpu list on this cpu | |
3804 | * has been initialized. | |
3805 | * | |
3806 | * Though the cpu is not in VMX operation now, there | |
3807 | * is no problem to enable the vmclear operation | |
3808 | * for the loaded_vmcss_on_cpu list is empty! | |
3809 | */ | |
3810 | crash_enable_local_vmclear(cpu); | |
3811 | ||
6aa8b732 | 3812 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3813 | |
3814 | test_bits = FEATURE_CONTROL_LOCKED; | |
3815 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3816 | if (tboot_enabled()) | |
3817 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3818 | ||
3819 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3820 | /* enable and lock */ |
cafd6659 SW |
3821 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3822 | } | |
fe0e80be | 3823 | kvm_cpu_vmxon(phys_addr); |
fdf288bf DH |
3824 | if (enable_ept) |
3825 | ept_sync_global(); | |
10474ae8 AG |
3826 | |
3827 | return 0; | |
6aa8b732 AK |
3828 | } |
3829 | ||
d462b819 | 3830 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3831 | { |
3832 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3833 | struct loaded_vmcs *v, *n; |
543e4243 | 3834 | |
d462b819 NHE |
3835 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3836 | loaded_vmcss_on_cpu_link) | |
3837 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3838 | } |
3839 | ||
710ff4a8 EH |
3840 | |
3841 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3842 | * tricks. | |
3843 | */ | |
3844 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3845 | { |
4ecac3fd | 3846 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3847 | |
3848 | intel_pt_handle_vmx(0); | |
fe0e80be | 3849 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3850 | } |
3851 | ||
13a34e06 | 3852 | static void hardware_disable(void) |
710ff4a8 | 3853 | { |
fe0e80be DH |
3854 | vmclear_local_loaded_vmcss(); |
3855 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3856 | } |
3857 | ||
1c3d14fe | 3858 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3859 | u32 msr, u32 *result) |
1c3d14fe YS |
3860 | { |
3861 | u32 vmx_msr_low, vmx_msr_high; | |
3862 | u32 ctl = ctl_min | ctl_opt; | |
3863 | ||
3864 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3865 | ||
3866 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3867 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3868 | ||
3869 | /* Ensure minimum (required) set of control bits are supported. */ | |
3870 | if (ctl_min & ~ctl) | |
002c7f7c | 3871 | return -EIO; |
1c3d14fe YS |
3872 | |
3873 | *result = ctl; | |
3874 | return 0; | |
3875 | } | |
3876 | ||
110312c8 AK |
3877 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3878 | { | |
3879 | u32 vmx_msr_low, vmx_msr_high; | |
3880 | ||
3881 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3882 | return vmx_msr_high & ctl; | |
3883 | } | |
3884 | ||
002c7f7c | 3885 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3886 | { |
3887 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3888 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3889 | u32 _pin_based_exec_control = 0; |
3890 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3891 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3892 | u32 _vmexit_control = 0; |
3893 | u32 _vmentry_control = 0; | |
3894 | ||
10166744 | 3895 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3896 | #ifdef CONFIG_X86_64 |
3897 | CPU_BASED_CR8_LOAD_EXITING | | |
3898 | CPU_BASED_CR8_STORE_EXITING | | |
3899 | #endif | |
d56f546d SY |
3900 | CPU_BASED_CR3_LOAD_EXITING | |
3901 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3902 | CPU_BASED_USE_IO_BITMAPS | |
3903 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3904 | CPU_BASED_USE_TSC_OFFSETING | |
fee84b07 AK |
3905 | CPU_BASED_INVLPG_EXITING | |
3906 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3907 | |
668fffa3 MT |
3908 | if (!kvm_mwait_in_guest()) |
3909 | min |= CPU_BASED_MWAIT_EXITING | | |
3910 | CPU_BASED_MONITOR_EXITING; | |
3911 | ||
f78e0e2e | 3912 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3913 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3914 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3915 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3916 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3917 | return -EIO; |
6e5d865c YS |
3918 | #ifdef CONFIG_X86_64 |
3919 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3920 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3921 | ~CPU_BASED_CR8_STORE_EXITING; | |
3922 | #endif | |
f78e0e2e | 3923 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3924 | min2 = 0; |
3925 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3926 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3927 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3928 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3929 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3930 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3931 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3932 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3933 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3934 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3935 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3936 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3937 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
3938 | SECONDARY_EXEC_RDSEED_EXITING | |
3939 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 3940 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 BD |
3941 | SECONDARY_EXEC_TSC_SCALING | |
3942 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
d56f546d SY |
3943 | if (adjust_vmx_controls(min2, opt2, |
3944 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3945 | &_cpu_based_2nd_exec_control) < 0) |
3946 | return -EIO; | |
3947 | } | |
3948 | #ifndef CONFIG_X86_64 | |
3949 | if (!(_cpu_based_2nd_exec_control & | |
3950 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3951 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3952 | #endif | |
83d4c286 YZ |
3953 | |
3954 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3955 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3956 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3957 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3958 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3959 | |
61f1dd90 WL |
3960 | rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, |
3961 | &vmx_capability.ept, &vmx_capability.vpid); | |
3962 | ||
d56f546d | 3963 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3964 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3965 | enabled */ | |
5fff7d27 GN |
3966 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3967 | CPU_BASED_CR3_STORE_EXITING | | |
3968 | CPU_BASED_INVLPG_EXITING); | |
61f1dd90 WL |
3969 | } else if (vmx_capability.ept) { |
3970 | vmx_capability.ept = 0; | |
3971 | pr_warn_once("EPT CAP should not exist if not support " | |
3972 | "1-setting enable EPT VM-execution control\n"); | |
3973 | } | |
3974 | if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && | |
3975 | vmx_capability.vpid) { | |
3976 | vmx_capability.vpid = 0; | |
3977 | pr_warn_once("VPID CAP should not exist if not support " | |
3978 | "1-setting enable VPID VM-execution control\n"); | |
d56f546d | 3979 | } |
1c3d14fe | 3980 | |
91fa0f8e | 3981 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3982 | #ifdef CONFIG_X86_64 |
3983 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3984 | #endif | |
a547c6db | 3985 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3986 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3987 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3988 | &_vmexit_control) < 0) | |
002c7f7c | 3989 | return -EIO; |
1c3d14fe | 3990 | |
8a1b4392 PB |
3991 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
3992 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | | |
3993 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3994 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3995 | &_pin_based_exec_control) < 0) | |
3996 | return -EIO; | |
3997 | ||
1c17c3e6 PB |
3998 | if (cpu_has_broken_vmx_preemption_timer()) |
3999 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 4000 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 4001 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
4002 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
4003 | ||
c845f9c6 | 4004 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 4005 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
4006 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
4007 | &_vmentry_control) < 0) | |
002c7f7c | 4008 | return -EIO; |
6aa8b732 | 4009 | |
c68876fd | 4010 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
4011 | |
4012 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
4013 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 4014 | return -EIO; |
1c3d14fe YS |
4015 | |
4016 | #ifdef CONFIG_X86_64 | |
4017 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
4018 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 4019 | return -EIO; |
1c3d14fe YS |
4020 | #endif |
4021 | ||
4022 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
4023 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 4024 | return -EIO; |
1c3d14fe | 4025 | |
002c7f7c | 4026 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 4027 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 4028 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 4029 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 4030 | |
002c7f7c YS |
4031 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
4032 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 4033 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
4034 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
4035 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 4036 | |
110312c8 AK |
4037 | cpu_has_load_ia32_efer = |
4038 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
4039 | VM_ENTRY_LOAD_IA32_EFER) | |
4040 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
4041 | VM_EXIT_LOAD_IA32_EFER); | |
4042 | ||
8bf00a52 GN |
4043 | cpu_has_load_perf_global_ctrl = |
4044 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
4045 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
4046 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
4047 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
4048 | ||
4049 | /* | |
4050 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 4051 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
4052 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
4053 | * | |
4054 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
4055 | * | |
4056 | * AAK155 (model 26) | |
4057 | * AAP115 (model 30) | |
4058 | * AAT100 (model 37) | |
4059 | * BC86,AAY89,BD102 (model 44) | |
4060 | * BA97 (model 46) | |
4061 | * | |
4062 | */ | |
4063 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
4064 | switch (boot_cpu_data.x86_model) { | |
4065 | case 26: | |
4066 | case 30: | |
4067 | case 37: | |
4068 | case 44: | |
4069 | case 46: | |
4070 | cpu_has_load_perf_global_ctrl = false; | |
4071 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
4072 | "does not work properly. Using workaround\n"); | |
4073 | break; | |
4074 | default: | |
4075 | break; | |
4076 | } | |
4077 | } | |
4078 | ||
782511b0 | 4079 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
4080 | rdmsrl(MSR_IA32_XSS, host_xss); |
4081 | ||
1c3d14fe | 4082 | return 0; |
c68876fd | 4083 | } |
6aa8b732 AK |
4084 | |
4085 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
4086 | { | |
4087 | int node = cpu_to_node(cpu); | |
4088 | struct page *pages; | |
4089 | struct vmcs *vmcs; | |
4090 | ||
96db800f | 4091 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
4092 | if (!pages) |
4093 | return NULL; | |
4094 | vmcs = page_address(pages); | |
1c3d14fe YS |
4095 | memset(vmcs, 0, vmcs_config.size); |
4096 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
4097 | return vmcs; |
4098 | } | |
4099 | ||
6aa8b732 AK |
4100 | static void free_vmcs(struct vmcs *vmcs) |
4101 | { | |
1c3d14fe | 4102 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
4103 | } |
4104 | ||
d462b819 NHE |
4105 | /* |
4106 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
4107 | */ | |
4108 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
4109 | { | |
4110 | if (!loaded_vmcs->vmcs) | |
4111 | return; | |
4112 | loaded_vmcs_clear(loaded_vmcs); | |
4113 | free_vmcs(loaded_vmcs->vmcs); | |
4114 | loaded_vmcs->vmcs = NULL; | |
4b0be90f PB |
4115 | if (loaded_vmcs->msr_bitmap) |
4116 | free_page((unsigned long)loaded_vmcs->msr_bitmap); | |
355f4fb1 | 4117 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
4118 | } |
4119 | ||
b6d7026d PB |
4120 | static struct vmcs *alloc_vmcs(void) |
4121 | { | |
4122 | return alloc_vmcs_cpu(raw_smp_processor_id()); | |
4123 | } | |
4124 | ||
4125 | static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
4126 | { | |
4127 | loaded_vmcs->vmcs = alloc_vmcs(); | |
4128 | if (!loaded_vmcs->vmcs) | |
4129 | return -ENOMEM; | |
4130 | ||
4131 | loaded_vmcs->shadow_vmcs = NULL; | |
4132 | loaded_vmcs_init(loaded_vmcs); | |
4b0be90f PB |
4133 | |
4134 | if (cpu_has_vmx_msr_bitmap()) { | |
4135 | loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
4136 | if (!loaded_vmcs->msr_bitmap) | |
4137 | goto out_vmcs; | |
4138 | memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); | |
4139 | } | |
b6d7026d | 4140 | return 0; |
4b0be90f PB |
4141 | |
4142 | out_vmcs: | |
4143 | free_loaded_vmcs(loaded_vmcs); | |
4144 | return -ENOMEM; | |
b6d7026d PB |
4145 | } |
4146 | ||
39959588 | 4147 | static void free_kvm_area(void) |
6aa8b732 AK |
4148 | { |
4149 | int cpu; | |
4150 | ||
3230bb47 | 4151 | for_each_possible_cpu(cpu) { |
6aa8b732 | 4152 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
4153 | per_cpu(vmxarea, cpu) = NULL; |
4154 | } | |
6aa8b732 AK |
4155 | } |
4156 | ||
85fd514e JM |
4157 | enum vmcs_field_type { |
4158 | VMCS_FIELD_TYPE_U16 = 0, | |
4159 | VMCS_FIELD_TYPE_U64 = 1, | |
4160 | VMCS_FIELD_TYPE_U32 = 2, | |
4161 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
4162 | }; | |
4163 | ||
4164 | static inline int vmcs_field_type(unsigned long field) | |
4165 | { | |
4166 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
4167 | return VMCS_FIELD_TYPE_U32; | |
4168 | return (field >> 13) & 0x3 ; | |
4169 | } | |
4170 | ||
4171 | static inline int vmcs_field_readonly(unsigned long field) | |
4172 | { | |
4173 | return (((field >> 10) & 0x3) == 1); | |
4174 | } | |
4175 | ||
fe2b201b BD |
4176 | static void init_vmcs_shadow_fields(void) |
4177 | { | |
4178 | int i, j; | |
4179 | ||
4180 | /* No checks for read only fields yet */ | |
4181 | ||
4182 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
4183 | switch (shadow_read_write_fields[i]) { | |
4184 | case GUEST_BNDCFGS: | |
a87036ad | 4185 | if (!kvm_mpx_supported()) |
fe2b201b BD |
4186 | continue; |
4187 | break; | |
4188 | default: | |
4189 | break; | |
4190 | } | |
4191 | ||
4192 | if (j < i) | |
4193 | shadow_read_write_fields[j] = | |
4194 | shadow_read_write_fields[i]; | |
4195 | j++; | |
4196 | } | |
4197 | max_shadow_read_write_fields = j; | |
4198 | ||
4199 | /* shadowed fields guest access without vmexit */ | |
4200 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
85fd514e JM |
4201 | unsigned long field = shadow_read_write_fields[i]; |
4202 | ||
4203 | clear_bit(field, vmx_vmwrite_bitmap); | |
4204 | clear_bit(field, vmx_vmread_bitmap); | |
4205 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) { | |
4206 | clear_bit(field + 1, vmx_vmwrite_bitmap); | |
4207 | clear_bit(field + 1, vmx_vmread_bitmap); | |
4208 | } | |
4209 | } | |
4210 | for (i = 0; i < max_shadow_read_only_fields; i++) { | |
4211 | unsigned long field = shadow_read_only_fields[i]; | |
4212 | ||
4213 | clear_bit(field, vmx_vmread_bitmap); | |
4214 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) | |
4215 | clear_bit(field + 1, vmx_vmread_bitmap); | |
fe2b201b | 4216 | } |
fe2b201b BD |
4217 | } |
4218 | ||
6aa8b732 AK |
4219 | static __init int alloc_kvm_area(void) |
4220 | { | |
4221 | int cpu; | |
4222 | ||
3230bb47 | 4223 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
4224 | struct vmcs *vmcs; |
4225 | ||
4226 | vmcs = alloc_vmcs_cpu(cpu); | |
4227 | if (!vmcs) { | |
4228 | free_kvm_area(); | |
4229 | return -ENOMEM; | |
4230 | } | |
4231 | ||
4232 | per_cpu(vmxarea, cpu) = vmcs; | |
4233 | } | |
4234 | return 0; | |
4235 | } | |
4236 | ||
91b0aa2c | 4237 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 4238 | struct kvm_segment *save) |
6aa8b732 | 4239 | { |
d99e4152 GN |
4240 | if (!emulate_invalid_guest_state) { |
4241 | /* | |
4242 | * CS and SS RPL should be equal during guest entry according | |
4243 | * to VMX spec, but in reality it is not always so. Since vcpu | |
4244 | * is in the middle of the transition from real mode to | |
4245 | * protected mode it is safe to assume that RPL 0 is a good | |
4246 | * default value. | |
4247 | */ | |
4248 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
4249 | save->selector &= ~SEGMENT_RPL_MASK; |
4250 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 4251 | save->s = 1; |
6aa8b732 | 4252 | } |
d99e4152 | 4253 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
4254 | } |
4255 | ||
4256 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
4257 | { | |
4258 | unsigned long flags; | |
a89a8fb9 | 4259 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4260 | |
d99e4152 GN |
4261 | /* |
4262 | * Update real mode segment cache. It may be not up-to-date if sement | |
4263 | * register was written while vcpu was in a guest mode. | |
4264 | */ | |
4265 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4266 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4267 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4268 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
4269 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
4270 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
4271 | ||
7ffd92c5 | 4272 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 4273 | |
2fb92db1 AK |
4274 | vmx_segment_cache_clear(vmx); |
4275 | ||
f5f7b2fe | 4276 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
4277 | |
4278 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
4279 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
4280 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
4281 | vmcs_writel(GUEST_RFLAGS, flags); |
4282 | ||
66aee91a RR |
4283 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
4284 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
4285 | |
4286 | update_exception_bitmap(vcpu); | |
4287 | ||
91b0aa2c GN |
4288 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
4289 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
4290 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4291 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4292 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
4293 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
4294 | } |
4295 | ||
f5f7b2fe | 4296 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 4297 | { |
772e0318 | 4298 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
4299 | struct kvm_segment var = *save; |
4300 | ||
4301 | var.dpl = 0x3; | |
4302 | if (seg == VCPU_SREG_CS) | |
4303 | var.type = 0x3; | |
4304 | ||
4305 | if (!emulate_invalid_guest_state) { | |
4306 | var.selector = var.base >> 4; | |
4307 | var.base = var.base & 0xffff0; | |
4308 | var.limit = 0xffff; | |
4309 | var.g = 0; | |
4310 | var.db = 0; | |
4311 | var.present = 1; | |
4312 | var.s = 1; | |
4313 | var.l = 0; | |
4314 | var.unusable = 0; | |
4315 | var.type = 0x3; | |
4316 | var.avl = 0; | |
4317 | if (save->base & 0xf) | |
4318 | printk_once(KERN_WARNING "kvm: segment base is not " | |
4319 | "paragraph aligned when entering " | |
4320 | "protected mode (seg=%d)", seg); | |
4321 | } | |
6aa8b732 | 4322 | |
d99e4152 | 4323 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 4324 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
4325 | vmcs_write32(sf->limit, var.limit); |
4326 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
4327 | } |
4328 | ||
4329 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
4330 | { | |
4331 | unsigned long flags; | |
a89a8fb9 | 4332 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4333 | |
f5f7b2fe AK |
4334 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
4335 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4336 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4337 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4338 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
4339 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
4340 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 4341 | |
7ffd92c5 | 4342 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 4343 | |
776e58ea GN |
4344 | /* |
4345 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 4346 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 4347 | */ |
4918c6ca | 4348 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
4349 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
4350 | "called before entering vcpu\n"); | |
776e58ea | 4351 | |
2fb92db1 AK |
4352 | vmx_segment_cache_clear(vmx); |
4353 | ||
4918c6ca | 4354 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 4355 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
4356 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4357 | ||
4358 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4359 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4360 | |
053de044 | 4361 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4362 | |
4363 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4364 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4365 | update_exception_bitmap(vcpu); |
4366 | ||
d99e4152 GN |
4367 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4368 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4369 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4370 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4371 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4372 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4373 | |
8668a3c4 | 4374 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4375 | } |
4376 | ||
401d10de AS |
4377 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4378 | { | |
4379 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4380 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4381 | ||
4382 | if (!msr) | |
4383 | return; | |
401d10de | 4384 | |
44ea2b17 AK |
4385 | /* |
4386 | * Force kernel_gs_base reloading before EFER changes, as control | |
4387 | * of this msr depends on is_long_mode(). | |
4388 | */ | |
4389 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4390 | vcpu->arch.efer = efer; |
401d10de | 4391 | if (efer & EFER_LMA) { |
2961e876 | 4392 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4393 | msr->data = efer; |
4394 | } else { | |
2961e876 | 4395 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4396 | |
4397 | msr->data = efer & ~EFER_LME; | |
4398 | } | |
4399 | setup_msrs(vmx); | |
4400 | } | |
4401 | ||
05b3e0c2 | 4402 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4403 | |
4404 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4405 | { | |
4406 | u32 guest_tr_ar; | |
4407 | ||
2fb92db1 AK |
4408 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4409 | ||
6aa8b732 | 4410 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4411 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4412 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4413 | __func__); | |
6aa8b732 | 4414 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4415 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4416 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4417 | } |
da38f438 | 4418 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4419 | } |
4420 | ||
4421 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4422 | { | |
2961e876 | 4423 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4424 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4425 | } |
4426 | ||
4427 | #endif | |
4428 | ||
dd5f5341 | 4429 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 4430 | { |
dd180b3e XG |
4431 | if (enable_ept) { |
4432 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
4433 | return; | |
995f00a6 | 4434 | ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4435 | } else { |
4436 | vpid_sync_context(vpid); | |
dd180b3e | 4437 | } |
2384d2b3 SY |
4438 | } |
4439 | ||
dd5f5341 WL |
4440 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
4441 | { | |
4442 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
4443 | } | |
4444 | ||
e8467fda AK |
4445 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4446 | { | |
4447 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4448 | ||
4449 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4450 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4451 | } | |
4452 | ||
aff48baa AK |
4453 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4454 | { | |
4455 | if (enable_ept && is_paging(vcpu)) | |
4456 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4457 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4458 | } | |
4459 | ||
25c4c276 | 4460 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4461 | { |
fc78f519 AK |
4462 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4463 | ||
4464 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4465 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4466 | } |
4467 | ||
1439442c SY |
4468 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4469 | { | |
d0d538b9 GN |
4470 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4471 | ||
6de4f3ad AK |
4472 | if (!test_bit(VCPU_EXREG_PDPTR, |
4473 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4474 | return; | |
4475 | ||
1439442c | 4476 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4477 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4478 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4479 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4480 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4481 | } |
4482 | } | |
4483 | ||
8f5d549f AK |
4484 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4485 | { | |
d0d538b9 GN |
4486 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4487 | ||
8f5d549f | 4488 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4489 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4490 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4491 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4492 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4493 | } |
6de4f3ad AK |
4494 | |
4495 | __set_bit(VCPU_EXREG_PDPTR, | |
4496 | (unsigned long *)&vcpu->arch.regs_avail); | |
4497 | __set_bit(VCPU_EXREG_PDPTR, | |
4498 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4499 | } |
4500 | ||
3899152c DM |
4501 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4502 | { | |
4503 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4504 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4505 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4506 | ||
4507 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4508 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4509 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4510 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4511 | ||
4512 | return fixed_bits_valid(val, fixed0, fixed1); | |
4513 | } | |
4514 | ||
4515 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4516 | { | |
4517 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4518 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4519 | ||
4520 | return fixed_bits_valid(val, fixed0, fixed1); | |
4521 | } | |
4522 | ||
4523 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4524 | { | |
4525 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4526 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4527 | ||
4528 | return fixed_bits_valid(val, fixed0, fixed1); | |
4529 | } | |
4530 | ||
4531 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4532 | #define nested_guest_cr4_valid nested_cr4_valid | |
4533 | #define nested_host_cr4_valid nested_cr4_valid | |
4534 | ||
5e1746d6 | 4535 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4536 | |
4537 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4538 | unsigned long cr0, | |
4539 | struct kvm_vcpu *vcpu) | |
4540 | { | |
5233dd51 MT |
4541 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4542 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4543 | if (!(cr0 & X86_CR0_PG)) { |
4544 | /* From paging/starting to nonpaging */ | |
4545 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4546 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4547 | (CPU_BASED_CR3_LOAD_EXITING | |
4548 | CPU_BASED_CR3_STORE_EXITING)); | |
4549 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4550 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4551 | } else if (!is_paging(vcpu)) { |
4552 | /* From nonpaging to paging */ | |
4553 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4554 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4555 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4556 | CPU_BASED_CR3_STORE_EXITING)); | |
4557 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4558 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4559 | } |
95eb84a7 SY |
4560 | |
4561 | if (!(cr0 & X86_CR0_WP)) | |
4562 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4563 | } |
4564 | ||
6aa8b732 AK |
4565 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4566 | { | |
7ffd92c5 | 4567 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4568 | unsigned long hw_cr0; |
4569 | ||
5037878e | 4570 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4571 | if (enable_unrestricted_guest) |
5037878e | 4572 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4573 | else { |
5037878e | 4574 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4575 | |
218e763f GN |
4576 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4577 | enter_pmode(vcpu); | |
6aa8b732 | 4578 | |
218e763f GN |
4579 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4580 | enter_rmode(vcpu); | |
4581 | } | |
6aa8b732 | 4582 | |
05b3e0c2 | 4583 | #ifdef CONFIG_X86_64 |
f6801dff | 4584 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4585 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4586 | enter_lmode(vcpu); |
707d92fa | 4587 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4588 | exit_lmode(vcpu); |
4589 | } | |
4590 | #endif | |
4591 | ||
089d034e | 4592 | if (enable_ept) |
1439442c SY |
4593 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4594 | ||
6aa8b732 | 4595 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4596 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4597 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4598 | |
4599 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4600 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4601 | } |
4602 | ||
855feb67 YZ |
4603 | static int get_ept_level(struct kvm_vcpu *vcpu) |
4604 | { | |
4605 | if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) | |
4606 | return 5; | |
4607 | return 4; | |
4608 | } | |
4609 | ||
995f00a6 | 4610 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) |
1439442c | 4611 | { |
855feb67 YZ |
4612 | u64 eptp = VMX_EPTP_MT_WB; |
4613 | ||
4614 | eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; | |
1439442c | 4615 | |
995f00a6 PF |
4616 | if (enable_ept_ad_bits && |
4617 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 4618 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
4619 | eptp |= (root_hpa & PAGE_MASK); |
4620 | ||
4621 | return eptp; | |
4622 | } | |
4623 | ||
6aa8b732 AK |
4624 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4625 | { | |
1439442c SY |
4626 | unsigned long guest_cr3; |
4627 | u64 eptp; | |
4628 | ||
4629 | guest_cr3 = cr3; | |
089d034e | 4630 | if (enable_ept) { |
995f00a6 | 4631 | eptp = construct_eptp(vcpu, cr3); |
1439442c | 4632 | vmcs_write64(EPT_POINTER, eptp); |
59ab5a8f JK |
4633 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4634 | guest_cr3 = kvm_read_cr3(vcpu); | |
4635 | else | |
4636 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4637 | ept_load_pdptrs(vcpu); |
1439442c SY |
4638 | } |
4639 | ||
2384d2b3 | 4640 | vmx_flush_tlb(vcpu); |
1439442c | 4641 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4642 | } |
4643 | ||
5e1746d6 | 4644 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4645 | { |
085e68ee BS |
4646 | /* |
4647 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4648 | * is in force while we are in guest mode. Do not let guests control | |
4649 | * this bit, even if host CR4.MCE == 0. | |
4650 | */ | |
4651 | unsigned long hw_cr4 = | |
4652 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4653 | (cr4 & ~X86_CR4_MCE) | | |
4654 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4655 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4656 | |
5e1746d6 NHE |
4657 | if (cr4 & X86_CR4_VMXE) { |
4658 | /* | |
4659 | * To use VMXON (and later other VMX instructions), a guest | |
4660 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4661 | * So basically the check on whether to allow nested VMX | |
4662 | * is here. | |
4663 | */ | |
4664 | if (!nested_vmx_allowed(vcpu)) | |
4665 | return 1; | |
1a0d74e6 | 4666 | } |
3899152c DM |
4667 | |
4668 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4669 | return 1; |
4670 | ||
ad312c7c | 4671 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4672 | if (enable_ept) { |
4673 | if (!is_paging(vcpu)) { | |
4674 | hw_cr4 &= ~X86_CR4_PAE; | |
4675 | hw_cr4 |= X86_CR4_PSE; | |
4676 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4677 | hw_cr4 &= ~X86_CR4_PAE; | |
4678 | } | |
4679 | } | |
1439442c | 4680 | |
656ec4a4 RK |
4681 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4682 | /* | |
ddba2628 HH |
4683 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4684 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4685 | * to be manually disabled when guest switches to non-paging | |
4686 | * mode. | |
4687 | * | |
4688 | * If !enable_unrestricted_guest, the CPU is always running | |
4689 | * with CR0.PG=1 and CR4 needs to be modified. | |
4690 | * If enable_unrestricted_guest, the CPU automatically | |
4691 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4692 | */ |
ddba2628 | 4693 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4694 | |
1439442c SY |
4695 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4696 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4697 | return 0; |
6aa8b732 AK |
4698 | } |
4699 | ||
6aa8b732 AK |
4700 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4701 | struct kvm_segment *var, int seg) | |
4702 | { | |
a9179499 | 4703 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4704 | u32 ar; |
4705 | ||
c6ad1153 | 4706 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4707 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4708 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4709 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4710 | return; |
1390a28b AK |
4711 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4712 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4713 | return; | |
a9179499 | 4714 | } |
2fb92db1 AK |
4715 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4716 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4717 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4718 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4719 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4720 | var->type = ar & 15; |
4721 | var->s = (ar >> 4) & 1; | |
4722 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4723 | /* |
4724 | * Some userspaces do not preserve unusable property. Since usable | |
4725 | * segment has to be present according to VMX spec we can use present | |
4726 | * property to amend userspace bug by making unusable segment always | |
4727 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4728 | * segment as unusable. | |
4729 | */ | |
4730 | var->present = !var->unusable; | |
6aa8b732 AK |
4731 | var->avl = (ar >> 12) & 1; |
4732 | var->l = (ar >> 13) & 1; | |
4733 | var->db = (ar >> 14) & 1; | |
4734 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4735 | } |
4736 | ||
a9179499 AK |
4737 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4738 | { | |
a9179499 AK |
4739 | struct kvm_segment s; |
4740 | ||
4741 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4742 | vmx_get_segment(vcpu, &s, seg); | |
4743 | return s.base; | |
4744 | } | |
2fb92db1 | 4745 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4746 | } |
4747 | ||
b09408d0 | 4748 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4749 | { |
b09408d0 MT |
4750 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4751 | ||
ae9fedc7 | 4752 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4753 | return 0; |
ae9fedc7 PB |
4754 | else { |
4755 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4756 | return VMX_AR_DPL(ar); |
69c73028 | 4757 | } |
69c73028 AK |
4758 | } |
4759 | ||
653e3108 | 4760 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4761 | { |
6aa8b732 AK |
4762 | u32 ar; |
4763 | ||
f0495f9b | 4764 | if (var->unusable || !var->present) |
6aa8b732 AK |
4765 | ar = 1 << 16; |
4766 | else { | |
4767 | ar = var->type & 15; | |
4768 | ar |= (var->s & 1) << 4; | |
4769 | ar |= (var->dpl & 3) << 5; | |
4770 | ar |= (var->present & 1) << 7; | |
4771 | ar |= (var->avl & 1) << 12; | |
4772 | ar |= (var->l & 1) << 13; | |
4773 | ar |= (var->db & 1) << 14; | |
4774 | ar |= (var->g & 1) << 15; | |
4775 | } | |
653e3108 AK |
4776 | |
4777 | return ar; | |
4778 | } | |
4779 | ||
4780 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4781 | struct kvm_segment *var, int seg) | |
4782 | { | |
7ffd92c5 | 4783 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4784 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4785 | |
2fb92db1 AK |
4786 | vmx_segment_cache_clear(vmx); |
4787 | ||
1ecd50a9 GN |
4788 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4789 | vmx->rmode.segs[seg] = *var; | |
4790 | if (seg == VCPU_SREG_TR) | |
4791 | vmcs_write16(sf->selector, var->selector); | |
4792 | else if (var->s) | |
4793 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4794 | goto out; |
653e3108 | 4795 | } |
1ecd50a9 | 4796 | |
653e3108 AK |
4797 | vmcs_writel(sf->base, var->base); |
4798 | vmcs_write32(sf->limit, var->limit); | |
4799 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4800 | |
4801 | /* | |
4802 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4803 | * qemu binaries. | |
4804 | * IA32 arch specifies that at the time of processor reset the | |
4805 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4806 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4807 | * state vmexit when "unrestricted guest" mode is turned on. |
4808 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4809 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4810 | * kvm hack. | |
4811 | */ | |
4812 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4813 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4814 | |
f924d66d | 4815 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4816 | |
4817 | out: | |
98eb2f8b | 4818 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4819 | } |
4820 | ||
6aa8b732 AK |
4821 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4822 | { | |
2fb92db1 | 4823 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4824 | |
4825 | *db = (ar >> 14) & 1; | |
4826 | *l = (ar >> 13) & 1; | |
4827 | } | |
4828 | ||
89a27f4d | 4829 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4830 | { |
89a27f4d GN |
4831 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4832 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4833 | } |
4834 | ||
89a27f4d | 4835 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4836 | { |
89a27f4d GN |
4837 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4838 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4839 | } |
4840 | ||
89a27f4d | 4841 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4842 | { |
89a27f4d GN |
4843 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4844 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4845 | } |
4846 | ||
89a27f4d | 4847 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4848 | { |
89a27f4d GN |
4849 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4850 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4851 | } |
4852 | ||
648dfaa7 MG |
4853 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4854 | { | |
4855 | struct kvm_segment var; | |
4856 | u32 ar; | |
4857 | ||
4858 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4859 | var.dpl = 0x3; |
0647f4aa GN |
4860 | if (seg == VCPU_SREG_CS) |
4861 | var.type = 0x3; | |
648dfaa7 MG |
4862 | ar = vmx_segment_access_rights(&var); |
4863 | ||
4864 | if (var.base != (var.selector << 4)) | |
4865 | return false; | |
89efbed0 | 4866 | if (var.limit != 0xffff) |
648dfaa7 | 4867 | return false; |
07f42f5f | 4868 | if (ar != 0xf3) |
648dfaa7 MG |
4869 | return false; |
4870 | ||
4871 | return true; | |
4872 | } | |
4873 | ||
4874 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4875 | { | |
4876 | struct kvm_segment cs; | |
4877 | unsigned int cs_rpl; | |
4878 | ||
4879 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4880 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4881 | |
1872a3f4 AK |
4882 | if (cs.unusable) |
4883 | return false; | |
4d283ec9 | 4884 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4885 | return false; |
4886 | if (!cs.s) | |
4887 | return false; | |
4d283ec9 | 4888 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4889 | if (cs.dpl > cs_rpl) |
4890 | return false; | |
1872a3f4 | 4891 | } else { |
648dfaa7 MG |
4892 | if (cs.dpl != cs_rpl) |
4893 | return false; | |
4894 | } | |
4895 | if (!cs.present) | |
4896 | return false; | |
4897 | ||
4898 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4899 | return true; | |
4900 | } | |
4901 | ||
4902 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4903 | { | |
4904 | struct kvm_segment ss; | |
4905 | unsigned int ss_rpl; | |
4906 | ||
4907 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4908 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4909 | |
1872a3f4 AK |
4910 | if (ss.unusable) |
4911 | return true; | |
4912 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4913 | return false; |
4914 | if (!ss.s) | |
4915 | return false; | |
4916 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4917 | return false; | |
4918 | if (!ss.present) | |
4919 | return false; | |
4920 | ||
4921 | return true; | |
4922 | } | |
4923 | ||
4924 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4925 | { | |
4926 | struct kvm_segment var; | |
4927 | unsigned int rpl; | |
4928 | ||
4929 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4930 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4931 | |
1872a3f4 AK |
4932 | if (var.unusable) |
4933 | return true; | |
648dfaa7 MG |
4934 | if (!var.s) |
4935 | return false; | |
4936 | if (!var.present) | |
4937 | return false; | |
4d283ec9 | 4938 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4939 | if (var.dpl < rpl) /* DPL < RPL */ |
4940 | return false; | |
4941 | } | |
4942 | ||
4943 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4944 | * rights flags | |
4945 | */ | |
4946 | return true; | |
4947 | } | |
4948 | ||
4949 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4950 | { | |
4951 | struct kvm_segment tr; | |
4952 | ||
4953 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4954 | ||
1872a3f4 AK |
4955 | if (tr.unusable) |
4956 | return false; | |
b32a9918 | 4957 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4958 | return false; |
1872a3f4 | 4959 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4960 | return false; |
4961 | if (!tr.present) | |
4962 | return false; | |
4963 | ||
4964 | return true; | |
4965 | } | |
4966 | ||
4967 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4968 | { | |
4969 | struct kvm_segment ldtr; | |
4970 | ||
4971 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4972 | ||
1872a3f4 AK |
4973 | if (ldtr.unusable) |
4974 | return true; | |
b32a9918 | 4975 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4976 | return false; |
4977 | if (ldtr.type != 2) | |
4978 | return false; | |
4979 | if (!ldtr.present) | |
4980 | return false; | |
4981 | ||
4982 | return true; | |
4983 | } | |
4984 | ||
4985 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4986 | { | |
4987 | struct kvm_segment cs, ss; | |
4988 | ||
4989 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4990 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4991 | ||
b32a9918 NA |
4992 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4993 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4994 | } |
4995 | ||
4996 | /* | |
4997 | * Check if guest state is valid. Returns true if valid, false if | |
4998 | * not. | |
4999 | * We assume that registers are always usable | |
5000 | */ | |
5001 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
5002 | { | |
c5e97c80 GN |
5003 | if (enable_unrestricted_guest) |
5004 | return true; | |
5005 | ||
648dfaa7 | 5006 | /* real mode guest state checks */ |
f13882d8 | 5007 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
5008 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
5009 | return false; | |
5010 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
5011 | return false; | |
5012 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
5013 | return false; | |
5014 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
5015 | return false; | |
5016 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
5017 | return false; | |
5018 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
5019 | return false; | |
5020 | } else { | |
5021 | /* protected mode guest state checks */ | |
5022 | if (!cs_ss_rpl_check(vcpu)) | |
5023 | return false; | |
5024 | if (!code_segment_valid(vcpu)) | |
5025 | return false; | |
5026 | if (!stack_segment_valid(vcpu)) | |
5027 | return false; | |
5028 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
5029 | return false; | |
5030 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
5031 | return false; | |
5032 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
5033 | return false; | |
5034 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
5035 | return false; | |
5036 | if (!tr_valid(vcpu)) | |
5037 | return false; | |
5038 | if (!ldtr_valid(vcpu)) | |
5039 | return false; | |
5040 | } | |
5041 | /* TODO: | |
5042 | * - Add checks on RIP | |
5043 | * - Add checks on RFLAGS | |
5044 | */ | |
5045 | ||
5046 | return true; | |
5047 | } | |
5048 | ||
5fa99cbe JM |
5049 | static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) |
5050 | { | |
5051 | return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); | |
5052 | } | |
5053 | ||
d77c26fc | 5054 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 5055 | { |
40dcaa9f | 5056 | gfn_t fn; |
195aefde | 5057 | u16 data = 0; |
1f755a82 | 5058 | int idx, r; |
6aa8b732 | 5059 | |
40dcaa9f | 5060 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 5061 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
5062 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
5063 | if (r < 0) | |
10589a46 | 5064 | goto out; |
195aefde | 5065 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
5066 | r = kvm_write_guest_page(kvm, fn++, &data, |
5067 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 5068 | if (r < 0) |
10589a46 | 5069 | goto out; |
195aefde IE |
5070 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
5071 | if (r < 0) | |
10589a46 | 5072 | goto out; |
195aefde IE |
5073 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
5074 | if (r < 0) | |
10589a46 | 5075 | goto out; |
195aefde | 5076 | data = ~0; |
10589a46 MT |
5077 | r = kvm_write_guest_page(kvm, fn, &data, |
5078 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
5079 | sizeof(u8)); | |
10589a46 | 5080 | out: |
40dcaa9f | 5081 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 5082 | return r; |
6aa8b732 AK |
5083 | } |
5084 | ||
b7ebfb05 SY |
5085 | static int init_rmode_identity_map(struct kvm *kvm) |
5086 | { | |
f51770ed | 5087 | int i, idx, r = 0; |
ba049e93 | 5088 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
5089 | u32 tmp; |
5090 | ||
a255d479 TC |
5091 | /* Protect kvm->arch.ept_identity_pagetable_done. */ |
5092 | mutex_lock(&kvm->slots_lock); | |
5093 | ||
f51770ed | 5094 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 5095 | goto out2; |
a255d479 | 5096 | |
d8a6e365 DH |
5097 | if (!kvm->arch.ept_identity_map_addr) |
5098 | kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b927a3ce | 5099 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 | 5100 | |
d8a6e365 DH |
5101 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
5102 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
f51770ed | 5103 | if (r < 0) |
a255d479 TC |
5104 | goto out2; |
5105 | ||
40dcaa9f | 5106 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
5107 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
5108 | if (r < 0) | |
5109 | goto out; | |
5110 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
5111 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
5112 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
5113 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
5114 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
5115 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
5116 | if (r < 0) | |
5117 | goto out; | |
5118 | } | |
5119 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 5120 | |
b7ebfb05 | 5121 | out: |
40dcaa9f | 5122 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
5123 | |
5124 | out2: | |
5125 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 5126 | return r; |
b7ebfb05 SY |
5127 | } |
5128 | ||
6aa8b732 AK |
5129 | static void seg_setup(int seg) |
5130 | { | |
772e0318 | 5131 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 5132 | unsigned int ar; |
6aa8b732 AK |
5133 | |
5134 | vmcs_write16(sf->selector, 0); | |
5135 | vmcs_writel(sf->base, 0); | |
5136 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
5137 | ar = 0x93; |
5138 | if (seg == VCPU_SREG_CS) | |
5139 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
5140 | |
5141 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
5142 | } |
5143 | ||
f78e0e2e SY |
5144 | static int alloc_apic_access_page(struct kvm *kvm) |
5145 | { | |
4484141a | 5146 | struct page *page; |
f78e0e2e SY |
5147 | int r = 0; |
5148 | ||
79fac95e | 5149 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 5150 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 5151 | goto out; |
1d8007bd PB |
5152 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
5153 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
5154 | if (r) |
5155 | goto out; | |
72dc67a6 | 5156 | |
73a6d941 | 5157 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
5158 | if (is_error_page(page)) { |
5159 | r = -EFAULT; | |
5160 | goto out; | |
5161 | } | |
5162 | ||
c24ae0dc TC |
5163 | /* |
5164 | * Do not pin the page in memory, so that memory hot-unplug | |
5165 | * is able to migrate it. | |
5166 | */ | |
5167 | put_page(page); | |
5168 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 5169 | out: |
79fac95e | 5170 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
5171 | return r; |
5172 | } | |
5173 | ||
991e7a0e | 5174 | static int allocate_vpid(void) |
2384d2b3 SY |
5175 | { |
5176 | int vpid; | |
5177 | ||
919818ab | 5178 | if (!enable_vpid) |
991e7a0e | 5179 | return 0; |
2384d2b3 SY |
5180 | spin_lock(&vmx_vpid_lock); |
5181 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 5182 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 5183 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
5184 | else |
5185 | vpid = 0; | |
2384d2b3 | 5186 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 5187 | return vpid; |
2384d2b3 SY |
5188 | } |
5189 | ||
991e7a0e | 5190 | static void free_vpid(int vpid) |
cdbecfc3 | 5191 | { |
991e7a0e | 5192 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
5193 | return; |
5194 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 5195 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
5196 | spin_unlock(&vmx_vpid_lock); |
5197 | } | |
5198 | ||
4b0be90f PB |
5199 | static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
5200 | u32 msr, int type) | |
25c5f225 | 5201 | { |
3e7c73e9 | 5202 | int f = sizeof(unsigned long); |
25c5f225 SY |
5203 | |
5204 | if (!cpu_has_vmx_msr_bitmap()) | |
5205 | return; | |
5206 | ||
5207 | /* | |
5208 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5209 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5210 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5211 | */ | |
25c5f225 | 5212 | if (msr <= 0x1fff) { |
8d14695f YZ |
5213 | if (type & MSR_TYPE_R) |
5214 | /* read-low */ | |
5215 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
5216 | ||
5217 | if (type & MSR_TYPE_W) | |
5218 | /* write-low */ | |
5219 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
5220 | ||
25c5f225 SY |
5221 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
5222 | msr &= 0x1fff; | |
8d14695f YZ |
5223 | if (type & MSR_TYPE_R) |
5224 | /* read-high */ | |
5225 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
5226 | ||
5227 | if (type & MSR_TYPE_W) | |
5228 | /* write-high */ | |
5229 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
5230 | ||
5231 | } | |
5232 | } | |
5233 | ||
4b0be90f PB |
5234 | static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, |
5235 | u32 msr, int type) | |
5236 | { | |
5237 | int f = sizeof(unsigned long); | |
5238 | ||
5239 | if (!cpu_has_vmx_msr_bitmap()) | |
5240 | return; | |
5241 | ||
5242 | /* | |
5243 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5244 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5245 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5246 | */ | |
5247 | if (msr <= 0x1fff) { | |
5248 | if (type & MSR_TYPE_R) | |
5249 | /* read-low */ | |
5250 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
5251 | ||
5252 | if (type & MSR_TYPE_W) | |
5253 | /* write-low */ | |
5254 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
5255 | ||
5256 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5257 | msr &= 0x1fff; | |
5258 | if (type & MSR_TYPE_R) | |
5259 | /* read-high */ | |
5260 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
5261 | ||
5262 | if (type & MSR_TYPE_W) | |
5263 | /* write-high */ | |
5264 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
5265 | ||
5266 | } | |
5267 | } | |
5268 | ||
5269 | static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap, | |
5270 | u32 msr, int type, bool value) | |
5271 | { | |
5272 | if (value) | |
5273 | vmx_enable_intercept_for_msr(msr_bitmap, msr, type); | |
5274 | else | |
5275 | vmx_disable_intercept_for_msr(msr_bitmap, msr, type); | |
5276 | } | |
5277 | ||
f2b93280 WV |
5278 | /* |
5279 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
5280 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
5281 | */ | |
5282 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
5283 | unsigned long *msr_bitmap_nested, | |
5284 | u32 msr, int type) | |
5285 | { | |
5286 | int f = sizeof(unsigned long); | |
5287 | ||
5288 | if (!cpu_has_vmx_msr_bitmap()) { | |
5289 | WARN_ON(1); | |
5290 | return; | |
5291 | } | |
5292 | ||
5293 | /* | |
5294 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5295 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5296 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5297 | */ | |
5298 | if (msr <= 0x1fff) { | |
5299 | if (type & MSR_TYPE_R && | |
5300 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
5301 | /* read-low */ | |
5302 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
5303 | ||
5304 | if (type & MSR_TYPE_W && | |
5305 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
5306 | /* write-low */ | |
5307 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
5308 | ||
5309 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5310 | msr &= 0x1fff; | |
5311 | if (type & MSR_TYPE_R && | |
5312 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
5313 | /* read-high */ | |
5314 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
5315 | ||
5316 | if (type & MSR_TYPE_W && | |
5317 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
5318 | /* write-high */ | |
5319 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
5320 | ||
5321 | } | |
5322 | } | |
5323 | ||
4b0be90f | 5324 | static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) |
5897297b | 5325 | { |
4b0be90f PB |
5326 | u8 mode = 0; |
5327 | ||
5328 | if (cpu_has_secondary_exec_ctrls() && | |
5329 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
5330 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
5331 | mode |= MSR_BITMAP_MODE_X2APIC; | |
5332 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) | |
5333 | mode |= MSR_BITMAP_MODE_X2APIC_APICV; | |
5334 | } | |
5335 | ||
5336 | if (is_long_mode(vcpu)) | |
5337 | mode |= MSR_BITMAP_MODE_LM; | |
5338 | ||
5339 | return mode; | |
8d14695f YZ |
5340 | } |
5341 | ||
4b0be90f PB |
5342 | #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) |
5343 | ||
5344 | static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, | |
5345 | u8 mode) | |
8d14695f | 5346 | { |
4b0be90f PB |
5347 | int msr; |
5348 | ||
5349 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { | |
5350 | unsigned word = msr / BITS_PER_LONG; | |
5351 | msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; | |
5352 | msr_bitmap[word + (0x800 / sizeof(long))] = ~0; | |
5353 | } | |
5354 | ||
5355 | if (mode & MSR_BITMAP_MODE_X2APIC) { | |
5356 | /* | |
5357 | * TPR reads and writes can be virtualized even if virtual interrupt | |
5358 | * delivery is not in use. | |
5359 | */ | |
5360 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); | |
5361 | if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { | |
5362 | vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); | |
5363 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); | |
5364 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); | |
5365 | } | |
f6e90f9e | 5366 | } |
5897297b AK |
5367 | } |
5368 | ||
4b0be90f PB |
5369 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) |
5370 | { | |
5371 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5372 | unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; | |
5373 | u8 mode = vmx_msr_bitmap_mode(vcpu); | |
5374 | u8 changed = mode ^ vmx->msr_bitmap_mode; | |
5375 | ||
5376 | if (!changed) | |
5377 | return; | |
5378 | ||
5379 | vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW, | |
5380 | !(mode & MSR_BITMAP_MODE_LM)); | |
5381 | ||
5382 | if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) | |
5383 | vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); | |
5384 | ||
5385 | vmx->msr_bitmap_mode = mode; | |
5386 | } | |
5387 | ||
b2a05fef | 5388 | static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) |
d50ab6c1 | 5389 | { |
d62caabb | 5390 | return enable_apicv; |
d50ab6c1 PB |
5391 | } |
5392 | ||
c9f04407 DM |
5393 | static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) |
5394 | { | |
5395 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5396 | gfn_t gfn; | |
5397 | ||
5398 | /* | |
5399 | * Don't need to mark the APIC access page dirty; it is never | |
5400 | * written to by the CPU during APIC virtualization. | |
5401 | */ | |
5402 | ||
5403 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5404 | gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; | |
5405 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5406 | } | |
5407 | ||
5408 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
5409 | gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; | |
5410 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5411 | } | |
5412 | } | |
5413 | ||
5414 | ||
6342c50a | 5415 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
5416 | { |
5417 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5418 | int max_irr; | |
5419 | void *vapic_page; | |
5420 | u16 status; | |
5421 | ||
c9f04407 DM |
5422 | if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) |
5423 | return; | |
705699a1 | 5424 | |
c9f04407 DM |
5425 | vmx->nested.pi_pending = false; |
5426 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
5427 | return; | |
705699a1 | 5428 | |
c9f04407 DM |
5429 | max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); |
5430 | if (max_irr != 256) { | |
705699a1 | 5431 | vapic_page = kmap(vmx->nested.virtual_apic_page); |
705699a1 WV |
5432 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); |
5433 | kunmap(vmx->nested.virtual_apic_page); | |
5434 | ||
5435 | status = vmcs_read16(GUEST_INTR_STATUS); | |
5436 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
5437 | status &= ~0xff; | |
5438 | status |= (u8)max_irr; | |
5439 | vmcs_write16(GUEST_INTR_STATUS, status); | |
5440 | } | |
5441 | } | |
c9f04407 DM |
5442 | |
5443 | nested_mark_vmcs12_pages_dirty(vcpu); | |
705699a1 WV |
5444 | } |
5445 | ||
06a5524f WV |
5446 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
5447 | bool nested) | |
21bc8dc5 RK |
5448 | { |
5449 | #ifdef CONFIG_SMP | |
06a5524f WV |
5450 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
5451 | ||
21bc8dc5 | 5452 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 5453 | /* |
5753743f HZ |
5454 | * The vector of interrupt to be delivered to vcpu had |
5455 | * been set in PIR before this function. | |
5456 | * | |
5457 | * Following cases will be reached in this block, and | |
5458 | * we always send a notification event in all cases as | |
5459 | * explained below. | |
5460 | * | |
5461 | * Case 1: vcpu keeps in non-root mode. Sending a | |
5462 | * notification event posts the interrupt to vcpu. | |
5463 | * | |
5464 | * Case 2: vcpu exits to root mode and is still | |
5465 | * runnable. PIR will be synced to vIRR before the | |
5466 | * next vcpu entry. Sending a notification event in | |
5467 | * this case has no effect, as vcpu is not in root | |
5468 | * mode. | |
28b835d6 | 5469 | * |
5753743f HZ |
5470 | * Case 3: vcpu exits to root mode and is blocked. |
5471 | * vcpu_block() has already synced PIR to vIRR and | |
5472 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
5473 | * a blocked vcpu here does not wait for any requested | |
5474 | * interrupts in PIR, and sending a notification event | |
5475 | * which has no effect is safe here. | |
28b835d6 | 5476 | */ |
28b835d6 | 5477 | |
06a5524f | 5478 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
5479 | return true; |
5480 | } | |
5481 | #endif | |
5482 | return false; | |
5483 | } | |
5484 | ||
705699a1 WV |
5485 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5486 | int vector) | |
5487 | { | |
5488 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5489 | ||
5490 | if (is_guest_mode(vcpu) && | |
5491 | vector == vmx->nested.posted_intr_nv) { | |
705699a1 WV |
5492 | /* |
5493 | * If a posted intr is not recognized by hardware, | |
5494 | * we will accomplish it in the next vmentry. | |
5495 | */ | |
5496 | vmx->nested.pi_pending = true; | |
5497 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7b616667 LA |
5498 | /* the PIR and ON have been set by L1. */ |
5499 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) | |
5500 | kvm_vcpu_kick(vcpu); | |
705699a1 WV |
5501 | return 0; |
5502 | } | |
5503 | return -1; | |
5504 | } | |
a20ed54d YZ |
5505 | /* |
5506 | * Send interrupt to vcpu via posted interrupt way. | |
5507 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5508 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5509 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5510 | * interrupt from PIR in next vmentry. | |
5511 | */ | |
5512 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5513 | { | |
5514 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5515 | int r; | |
5516 | ||
705699a1 WV |
5517 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5518 | if (!r) | |
5519 | return; | |
5520 | ||
a20ed54d YZ |
5521 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5522 | return; | |
5523 | ||
b95234c8 PB |
5524 | /* If a previous notification has sent the IPI, nothing to do. */ |
5525 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
5526 | return; | |
5527 | ||
06a5524f | 5528 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) |
a20ed54d YZ |
5529 | kvm_vcpu_kick(vcpu); |
5530 | } | |
5531 | ||
a3a8ff8e NHE |
5532 | /* |
5533 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5534 | * will not change in the lifetime of the guest. | |
5535 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5536 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5537 | */ | |
a547c6db | 5538 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5539 | { |
5540 | u32 low32, high32; | |
5541 | unsigned long tmpl; | |
5542 | struct desc_ptr dt; | |
d6e41f11 | 5543 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 5544 | |
04ac88ab AL |
5545 | cr0 = read_cr0(); |
5546 | WARN_ON(cr0 & X86_CR0_TS); | |
5547 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
5548 | |
5549 | /* | |
5550 | * Save the most likely value for this task's CR3 in the VMCS. | |
5551 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
5552 | */ | |
6c690ee1 | 5553 | cr3 = __read_cr3(); |
d6e41f11 | 5554 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
44889942 | 5555 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
a3a8ff8e | 5556 | |
d974baa3 | 5557 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5558 | cr4 = cr4_read_shadow(); |
d974baa3 | 5559 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
44889942 | 5560 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 | 5561 | |
a3a8ff8e | 5562 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5563 | #ifdef CONFIG_X86_64 |
5564 | /* | |
5565 | * Load null selectors, so we can avoid reloading them in | |
5566 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5567 | * too (the expected case). | |
5568 | */ | |
5569 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5570 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5571 | #else | |
a3a8ff8e NHE |
5572 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5573 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5574 | #endif |
a3a8ff8e NHE |
5575 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5576 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5577 | ||
87930019 | 5578 | store_idt(&dt); |
a3a8ff8e | 5579 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
a547c6db | 5580 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5581 | |
83287ea4 | 5582 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5583 | |
5584 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5585 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5586 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5587 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5588 | ||
5589 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5590 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5591 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5592 | } | |
5593 | } | |
5594 | ||
bf8179a0 NHE |
5595 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5596 | { | |
5597 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5598 | if (enable_ept) | |
5599 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5600 | if (is_guest_mode(&vmx->vcpu)) |
5601 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5602 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5603 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5604 | } | |
5605 | ||
01e439be YZ |
5606 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5607 | { | |
5608 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5609 | ||
d62caabb | 5610 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5611 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
d02fcf50 PB |
5612 | |
5613 | if (!enable_vnmi) | |
5614 | pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; | |
5615 | ||
64672c95 YJ |
5616 | /* Enable the preemption timer dynamically */ |
5617 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5618 | return pin_based_exec_ctrl; |
5619 | } | |
5620 | ||
d62caabb AS |
5621 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5622 | { | |
5623 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5624 | ||
5625 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5626 | if (cpu_has_secondary_exec_ctrls()) { |
5627 | if (kvm_vcpu_apicv_active(vcpu)) | |
5628 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5629 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5630 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5631 | else | |
5632 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5633 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5634 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5635 | } | |
5636 | ||
5637 | if (cpu_has_vmx_msr_bitmap()) | |
4b0be90f | 5638 | vmx_update_msr_bitmap(vcpu); |
d62caabb AS |
5639 | } |
5640 | ||
bf8179a0 NHE |
5641 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5642 | { | |
5643 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5644 | |
5645 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5646 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5647 | ||
35754c98 | 5648 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5649 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5650 | #ifdef CONFIG_X86_64 | |
5651 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5652 | CPU_BASED_CR8_LOAD_EXITING; | |
5653 | #endif | |
5654 | } | |
5655 | if (!enable_ept) | |
5656 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5657 | CPU_BASED_CR3_LOAD_EXITING | | |
5658 | CPU_BASED_INVLPG_EXITING; | |
5659 | return exec_control; | |
5660 | } | |
5661 | ||
45ec368c | 5662 | static bool vmx_rdrand_supported(void) |
bf8179a0 | 5663 | { |
45ec368c | 5664 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
736fdf72 | 5665 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5666 | } |
5667 | ||
75f4fc8d JM |
5668 | static bool vmx_rdseed_supported(void) |
5669 | { | |
5670 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
736fdf72 | 5671 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5672 | } |
5673 | ||
80154d77 | 5674 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 5675 | { |
80154d77 PB |
5676 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
5677 | ||
bf8179a0 | 5678 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
80154d77 | 5679 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
5680 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5681 | if (vmx->vpid == 0) | |
5682 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5683 | if (!enable_ept) { | |
5684 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5685 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5686 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5687 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5688 | } |
5689 | if (!enable_unrestricted_guest) | |
5690 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5691 | if (!ple_gap) | |
5692 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
80154d77 | 5693 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
5694 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5695 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5696 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5697 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5698 | (handle_vmptrld). | |
5699 | We can NOT enable shadow_vmcs here because we don't have yet | |
5700 | a current VMCS12 | |
5701 | */ | |
5702 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5703 | |
5704 | if (!enable_pml) | |
5705 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5706 | |
3db13480 PB |
5707 | if (vmx_xsaves_supported()) { |
5708 | /* Exposing XSAVES only when XSAVE is exposed */ | |
5709 | bool xsaves_enabled = | |
5710 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
5711 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
5712 | ||
5713 | if (!xsaves_enabled) | |
5714 | exec_control &= ~SECONDARY_EXEC_XSAVES; | |
5715 | ||
5716 | if (nested) { | |
5717 | if (xsaves_enabled) | |
5718 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5719 | SECONDARY_EXEC_XSAVES; | |
5720 | else | |
5721 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5722 | ~SECONDARY_EXEC_XSAVES; | |
5723 | } | |
5724 | } | |
5725 | ||
80154d77 PB |
5726 | if (vmx_rdtscp_supported()) { |
5727 | bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); | |
5728 | if (!rdtscp_enabled) | |
5729 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5730 | ||
5731 | if (nested) { | |
5732 | if (rdtscp_enabled) | |
5733 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5734 | SECONDARY_EXEC_RDTSCP; | |
5735 | else | |
5736 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5737 | ~SECONDARY_EXEC_RDTSCP; | |
5738 | } | |
5739 | } | |
5740 | ||
5741 | if (vmx_invpcid_supported()) { | |
5742 | /* Exposing INVPCID only when PCID is exposed */ | |
5743 | bool invpcid_enabled = | |
5744 | guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && | |
5745 | guest_cpuid_has(vcpu, X86_FEATURE_PCID); | |
5746 | ||
5747 | if (!invpcid_enabled) { | |
5748 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5749 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
5750 | } | |
5751 | ||
5752 | if (nested) { | |
5753 | if (invpcid_enabled) | |
5754 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5755 | SECONDARY_EXEC_ENABLE_INVPCID; | |
5756 | else | |
5757 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5758 | ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5759 | } | |
5760 | } | |
5761 | ||
45ec368c JM |
5762 | if (vmx_rdrand_supported()) { |
5763 | bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); | |
5764 | if (rdrand_enabled) | |
736fdf72 | 5765 | exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5766 | |
5767 | if (nested) { | |
5768 | if (rdrand_enabled) | |
5769 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5770 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5771 | else |
5772 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5773 | ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5774 | } |
5775 | } | |
5776 | ||
75f4fc8d JM |
5777 | if (vmx_rdseed_supported()) { |
5778 | bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); | |
5779 | if (rdseed_enabled) | |
736fdf72 | 5780 | exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5781 | |
5782 | if (nested) { | |
5783 | if (rdseed_enabled) | |
5784 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5785 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5786 | else |
5787 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5788 | ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5789 | } |
5790 | } | |
5791 | ||
80154d77 | 5792 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
5793 | } |
5794 | ||
ce88decf XG |
5795 | static void ept_set_mmio_spte_mask(void) |
5796 | { | |
5797 | /* | |
5798 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5799 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5800 | */ |
dcdca5fe PF |
5801 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, |
5802 | VMX_EPT_MISCONFIG_WX_VALUE); | |
ce88decf XG |
5803 | } |
5804 | ||
f53cd63c | 5805 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5806 | /* |
5807 | * Sets up the vmcs for emulated real mode. | |
5808 | */ | |
12d79917 | 5809 | static void vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5810 | { |
2e4ce7f5 | 5811 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5812 | unsigned long a; |
2e4ce7f5 | 5813 | #endif |
6aa8b732 | 5814 | int i; |
6aa8b732 | 5815 | |
6aa8b732 | 5816 | /* I/O */ |
3e7c73e9 AK |
5817 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5818 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5819 | |
4607c2d7 AG |
5820 | if (enable_shadow_vmcs) { |
5821 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5822 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5823 | } | |
25c5f225 | 5824 | if (cpu_has_vmx_msr_bitmap()) |
4b0be90f | 5825 | vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); |
25c5f225 | 5826 | |
6aa8b732 AK |
5827 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5828 | ||
6aa8b732 | 5829 | /* Control */ |
01e439be | 5830 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5831 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5832 | |
bf8179a0 | 5833 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5834 | |
dfa169bb | 5835 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 5836 | vmx_compute_secondary_exec_control(vmx); |
bf8179a0 | 5837 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
80154d77 | 5838 | vmx->secondary_exec_control); |
dfa169bb | 5839 | } |
f78e0e2e | 5840 | |
d62caabb | 5841 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5842 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5843 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5844 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5845 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5846 | ||
5847 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5848 | |
0bcf261c | 5849 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5850 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5851 | } |
5852 | ||
4b8d54f9 ZE |
5853 | if (ple_gap) { |
5854 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5855 | vmx->ple_window = ple_window; |
5856 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5857 | } |
5858 | ||
c3707958 XG |
5859 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5860 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5861 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5862 | ||
9581d442 AK |
5863 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5864 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5865 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5866 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5867 | rdmsrl(MSR_FS_BASE, a); |
5868 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5869 | rdmsrl(MSR_GS_BASE, a); | |
5870 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5871 | #else | |
5872 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5873 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5874 | #endif | |
5875 | ||
2a499e49 BD |
5876 | if (cpu_has_vmx_vmfunc()) |
5877 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
5878 | ||
2cc51560 ED |
5879 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5880 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
6e3dedb6 | 5881 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); |
2cc51560 | 5882 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
6e3dedb6 | 5883 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); |
6aa8b732 | 5884 | |
74545705 RK |
5885 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5886 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5887 | |
03916db9 | 5888 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5889 | u32 index = vmx_msr_index[i]; |
5890 | u32 data_low, data_high; | |
a2fa3e9f | 5891 | int j = vmx->nmsrs; |
6aa8b732 AK |
5892 | |
5893 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5894 | continue; | |
432bd6cb AK |
5895 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5896 | continue; | |
26bb0981 AK |
5897 | vmx->guest_msrs[j].index = i; |
5898 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5899 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5900 | ++vmx->nmsrs; |
6aa8b732 | 5901 | } |
6aa8b732 | 5902 | |
1ccd9994 | 5903 | vmx->arch_capabilities = kvm_get_arch_capabilities(); |
2961e876 GN |
5904 | |
5905 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5906 | |
5907 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5908 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5909 | |
bd7e5b08 PB |
5910 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
5911 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
5912 | ||
bf8179a0 | 5913 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5914 | |
f53cd63c WL |
5915 | if (vmx_xsaves_supported()) |
5916 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5917 | ||
4e59516a PF |
5918 | if (enable_pml) { |
5919 | ASSERT(vmx->pml_pg); | |
5920 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5921 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5922 | } | |
e00c8cf2 AK |
5923 | } |
5924 | ||
d28bc9dd | 5925 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5926 | { |
5927 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5928 | struct msr_data apic_base_msr; |
d28bc9dd | 5929 | u64 cr0; |
e00c8cf2 | 5930 | |
7ffd92c5 | 5931 | vmx->rmode.vm86_active = 0; |
74469996 | 5932 | vmx->spec_ctrl = 0; |
e00c8cf2 | 5933 | |
ad312c7c | 5934 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5935 | kvm_set_cr8(vcpu, 0); |
5936 | ||
5937 | if (!init_event) { | |
5938 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5939 | MSR_IA32_APICBASE_ENABLE; | |
5940 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5941 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5942 | apic_base_msr.host_initiated = true; | |
5943 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5944 | } | |
e00c8cf2 | 5945 | |
2fb92db1 AK |
5946 | vmx_segment_cache_clear(vmx); |
5947 | ||
5706be0d | 5948 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5949 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5950 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5951 | |
5952 | seg_setup(VCPU_SREG_DS); | |
5953 | seg_setup(VCPU_SREG_ES); | |
5954 | seg_setup(VCPU_SREG_FS); | |
5955 | seg_setup(VCPU_SREG_GS); | |
5956 | seg_setup(VCPU_SREG_SS); | |
5957 | ||
5958 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5959 | vmcs_writel(GUEST_TR_BASE, 0); | |
5960 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5961 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5962 | ||
5963 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5964 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5965 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5966 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5967 | ||
d28bc9dd NA |
5968 | if (!init_event) { |
5969 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5970 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5971 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5972 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5973 | } | |
e00c8cf2 | 5974 | |
c37c2873 | 5975 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
66450a21 | 5976 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5977 | |
e00c8cf2 AK |
5978 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5979 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5980 | ||
5981 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5982 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5983 | ||
443381a8 | 5984 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5985 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5986 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
a554d207 WL |
5987 | if (kvm_mpx_supported()) |
5988 | vmcs_write64(GUEST_BNDCFGS, 0); | |
e00c8cf2 | 5989 | |
e00c8cf2 AK |
5990 | setup_msrs(vmx); |
5991 | ||
6aa8b732 AK |
5992 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5993 | ||
d28bc9dd | 5994 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5995 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5996 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5997 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5998 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5999 | vmcs_write32(TPR_THRESHOLD, 0); |
6000 | } | |
6001 | ||
a73896cb | 6002 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 6003 | |
2384d2b3 SY |
6004 | if (vmx->vpid != 0) |
6005 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
6006 | ||
d28bc9dd | 6007 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 6008 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 6009 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 6010 | vmx_set_cr4(vcpu, 0); |
5690891b | 6011 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 6012 | |
d28bc9dd | 6013 | update_exception_bitmap(vcpu); |
6aa8b732 | 6014 | |
dd5f5341 | 6015 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
6016 | } |
6017 | ||
b6f1250e NHE |
6018 | /* |
6019 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
6020 | * For most existing hypervisors, this will always return true. | |
6021 | */ | |
6022 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
6023 | { | |
6024 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
6025 | PIN_BASED_EXT_INTR_MASK; | |
6026 | } | |
6027 | ||
77b0f5d6 BD |
6028 | /* |
6029 | * In nested virtualization, check if L1 has set | |
6030 | * VM_EXIT_ACK_INTR_ON_EXIT | |
6031 | */ | |
6032 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
6033 | { | |
6034 | return get_vmcs12(vcpu)->vm_exit_controls & | |
6035 | VM_EXIT_ACK_INTR_ON_EXIT; | |
6036 | } | |
6037 | ||
ea8ceb83 JK |
6038 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
6039 | { | |
6040 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
6041 | PIN_BASED_NMI_EXITING; | |
6042 | } | |
6043 | ||
c9a7953f | 6044 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 6045 | { |
47c0152e PB |
6046 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
6047 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
6048 | } |
6049 | ||
c9a7953f | 6050 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 6051 | { |
d02fcf50 | 6052 | if (!enable_vnmi || |
8a1b4392 | 6053 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
6054 | enable_irq_window(vcpu); |
6055 | return; | |
6056 | } | |
3b86cd99 | 6057 | |
47c0152e PB |
6058 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
6059 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
6060 | } |
6061 | ||
66fd3f7f | 6062 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 6063 | { |
9c8cba37 | 6064 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
6065 | uint32_t intr; |
6066 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 6067 | |
229456fc | 6068 | trace_kvm_inj_virq(irq); |
2714d1d3 | 6069 | |
fa89a817 | 6070 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 6071 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
6072 | int inc_eip = 0; |
6073 | if (vcpu->arch.interrupt.soft) | |
6074 | inc_eip = vcpu->arch.event_exit_inst_len; | |
6075 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 6076 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
6077 | return; |
6078 | } | |
66fd3f7f GN |
6079 | intr = irq | INTR_INFO_VALID_MASK; |
6080 | if (vcpu->arch.interrupt.soft) { | |
6081 | intr |= INTR_TYPE_SOFT_INTR; | |
6082 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
6083 | vmx->vcpu.arch.event_exit_inst_len); | |
6084 | } else | |
6085 | intr |= INTR_TYPE_EXT_INTR; | |
6086 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
6087 | } |
6088 | ||
f08864b4 SY |
6089 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
6090 | { | |
66a5a347 JK |
6091 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6092 | ||
d02fcf50 | 6093 | if (!enable_vnmi) { |
8a1b4392 PB |
6094 | /* |
6095 | * Tracking the NMI-blocked state in software is built upon | |
6096 | * finding the next open IRQ window. This, in turn, depends on | |
6097 | * well-behaving guests: They have to keep IRQs disabled at | |
6098 | * least as long as the NMI handler runs. Otherwise we may | |
6099 | * cause NMI nesting, maybe breaking the guest. But as this is | |
6100 | * highly unlikely, we can live with the residual risk. | |
6101 | */ | |
6102 | vmx->loaded_vmcs->soft_vnmi_blocked = 1; | |
6103 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
6104 | } | |
6105 | ||
4c4a6f79 PB |
6106 | ++vcpu->stat.nmi_injections; |
6107 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 6108 | |
7ffd92c5 | 6109 | if (vmx->rmode.vm86_active) { |
71f9833b | 6110 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 6111 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
6112 | return; |
6113 | } | |
c5a6d5f7 | 6114 | |
f08864b4 SY |
6115 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
6116 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
6117 | } |
6118 | ||
3cfc3092 JK |
6119 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
6120 | { | |
4c4a6f79 PB |
6121 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6122 | bool masked; | |
6123 | ||
d02fcf50 | 6124 | if (!enable_vnmi) |
8a1b4392 | 6125 | return vmx->loaded_vmcs->soft_vnmi_blocked; |
4c4a6f79 | 6126 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9d58b931 | 6127 | return false; |
4c4a6f79 PB |
6128 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
6129 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
6130 | return masked; | |
3cfc3092 JK |
6131 | } |
6132 | ||
6133 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
6134 | { | |
6135 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6136 | ||
d02fcf50 | 6137 | if (!enable_vnmi) { |
8a1b4392 PB |
6138 | if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { |
6139 | vmx->loaded_vmcs->soft_vnmi_blocked = masked; | |
6140 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
6141 | } | |
6142 | } else { | |
6143 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
6144 | if (masked) | |
6145 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6146 | GUEST_INTR_STATE_NMI); | |
6147 | else | |
6148 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6149 | GUEST_INTR_STATE_NMI); | |
6150 | } | |
3cfc3092 JK |
6151 | } |
6152 | ||
2505dc9f JK |
6153 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
6154 | { | |
b6b8a145 JK |
6155 | if (to_vmx(vcpu)->nested.nested_run_pending) |
6156 | return 0; | |
ea8ceb83 | 6157 | |
d02fcf50 | 6158 | if (!enable_vnmi && |
8a1b4392 PB |
6159 | to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) |
6160 | return 0; | |
6161 | ||
2505dc9f JK |
6162 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
6163 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
6164 | | GUEST_INTR_STATE_NMI)); | |
6165 | } | |
6166 | ||
78646121 GN |
6167 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
6168 | { | |
b6b8a145 JK |
6169 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
6170 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
6171 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
6172 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
6173 | } |
6174 | ||
cbc94022 IE |
6175 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
6176 | { | |
6177 | int ret; | |
cbc94022 | 6178 | |
1d8007bd PB |
6179 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
6180 | PAGE_SIZE * 3); | |
cbc94022 IE |
6181 | if (ret) |
6182 | return ret; | |
bfc6d222 | 6183 | kvm->arch.tss_addr = addr; |
1f755a82 | 6184 | return init_rmode_tss(kvm); |
cbc94022 IE |
6185 | } |
6186 | ||
0ca1b4f4 | 6187 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 6188 | { |
77ab6db0 | 6189 | switch (vec) { |
77ab6db0 | 6190 | case BP_VECTOR: |
c573cd22 JK |
6191 | /* |
6192 | * Update instruction length as we may reinject the exception | |
6193 | * from user space while in guest debugging mode. | |
6194 | */ | |
6195 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
6196 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 6197 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
6198 | return false; |
6199 | /* fall through */ | |
6200 | case DB_VECTOR: | |
6201 | if (vcpu->guest_debug & | |
6202 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
6203 | return false; | |
d0bfb940 JK |
6204 | /* fall through */ |
6205 | case DE_VECTOR: | |
77ab6db0 JK |
6206 | case OF_VECTOR: |
6207 | case BR_VECTOR: | |
6208 | case UD_VECTOR: | |
6209 | case DF_VECTOR: | |
6210 | case SS_VECTOR: | |
6211 | case GP_VECTOR: | |
6212 | case MF_VECTOR: | |
0ca1b4f4 GN |
6213 | return true; |
6214 | break; | |
77ab6db0 | 6215 | } |
0ca1b4f4 GN |
6216 | return false; |
6217 | } | |
6218 | ||
6219 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
6220 | int vec, u32 err_code) | |
6221 | { | |
6222 | /* | |
6223 | * Instruction with address size override prefix opcode 0x67 | |
6224 | * Cause the #SS fault with 0 error code in VM86 mode. | |
6225 | */ | |
6226 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
6227 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
6228 | if (vcpu->arch.halt_request) { | |
6229 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6230 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
6231 | } |
6232 | return 1; | |
6233 | } | |
6234 | return 0; | |
6235 | } | |
6236 | ||
6237 | /* | |
6238 | * Forward all other exceptions that are valid in real mode. | |
6239 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
6240 | * the required debugging infrastructure rework. | |
6241 | */ | |
6242 | kvm_queue_exception(vcpu, vec); | |
6243 | return 1; | |
6aa8b732 AK |
6244 | } |
6245 | ||
a0861c02 AK |
6246 | /* |
6247 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
6248 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
6249 | * We pass a fake environment to the machine check handler because we want | |
6250 | * the guest to be always treated like user space, no matter what context | |
6251 | * it used internally. | |
6252 | */ | |
6253 | static void kvm_machine_check(void) | |
6254 | { | |
6255 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
6256 | struct pt_regs regs = { | |
6257 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
6258 | .flags = X86_EFLAGS_IF, | |
6259 | }; | |
6260 | ||
6261 | do_machine_check(®s, 0); | |
6262 | #endif | |
6263 | } | |
6264 | ||
851ba692 | 6265 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
6266 | { |
6267 | /* already handled by vcpu_run */ | |
6268 | return 1; | |
6269 | } | |
6270 | ||
851ba692 | 6271 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 6272 | { |
1155f76a | 6273 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 6274 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 6275 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 6276 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
6277 | u32 vect_info; |
6278 | enum emulation_result er; | |
6279 | ||
1155f76a | 6280 | vect_info = vmx->idt_vectoring_info; |
88786475 | 6281 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 6282 | |
a0861c02 | 6283 | if (is_machine_check(intr_info)) |
851ba692 | 6284 | return handle_machine_check(vcpu); |
a0861c02 | 6285 | |
ef85b673 | 6286 | if (is_nmi(intr_info)) |
1b6269db | 6287 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 6288 | |
7aa81cc0 | 6289 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 6290 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
61cb57c9 LA |
6291 | if (er == EMULATE_USER_EXIT) |
6292 | return 0; | |
7aa81cc0 | 6293 | if (er != EMULATE_DONE) |
7ee5d940 | 6294 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
6295 | return 1; |
6296 | } | |
6297 | ||
6aa8b732 | 6298 | error_code = 0; |
2e11384c | 6299 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 6300 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
6301 | |
6302 | /* | |
6303 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
6304 | * MMIO, it is better to report an internal error. | |
6305 | * See the comments in vmx_handle_exit. | |
6306 | */ | |
6307 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
6308 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
6309 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6310 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 6311 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
6312 | vcpu->run->internal.data[0] = vect_info; |
6313 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 6314 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
6315 | return 0; |
6316 | } | |
6317 | ||
6aa8b732 AK |
6318 | if (is_page_fault(intr_info)) { |
6319 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1261bfa3 WL |
6320 | /* EPT won't cause page fault directly */ |
6321 | WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); | |
d0006530 | 6322 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); |
6aa8b732 AK |
6323 | } |
6324 | ||
d0bfb940 | 6325 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
6326 | |
6327 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
6328 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
6329 | ||
42dbaa5a | 6330 | switch (ex_no) { |
54a20552 EN |
6331 | case AC_VECTOR: |
6332 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
6333 | return 1; | |
42dbaa5a JK |
6334 | case DB_VECTOR: |
6335 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
6336 | if (!(vcpu->guest_debug & | |
6337 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 6338 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6339 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
3252850d | 6340 | if (is_icebp(intr_info)) |
fd2a445a HD |
6341 | skip_emulated_instruction(vcpu); |
6342 | ||
42dbaa5a JK |
6343 | kvm_queue_exception(vcpu, DB_VECTOR); |
6344 | return 1; | |
6345 | } | |
6346 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
6347 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
6348 | /* fall through */ | |
6349 | case BP_VECTOR: | |
c573cd22 JK |
6350 | /* |
6351 | * Update instruction length as we may reinject #BP from | |
6352 | * user space while in guest debugging mode. Reading it for | |
6353 | * #DB as well causes no harm, it is not used in that case. | |
6354 | */ | |
6355 | vmx->vcpu.arch.event_exit_inst_len = | |
6356 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 6357 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 6358 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
6359 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
6360 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
6361 | break; |
6362 | default: | |
d0bfb940 JK |
6363 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
6364 | kvm_run->ex.exception = ex_no; | |
6365 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 6366 | break; |
6aa8b732 | 6367 | } |
6aa8b732 AK |
6368 | return 0; |
6369 | } | |
6370 | ||
851ba692 | 6371 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6372 | { |
1165f5fe | 6373 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
6374 | return 1; |
6375 | } | |
6376 | ||
851ba692 | 6377 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 6378 | { |
851ba692 | 6379 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 6380 | vcpu->mmio_needed = 0; |
988ad74f AK |
6381 | return 0; |
6382 | } | |
6aa8b732 | 6383 | |
851ba692 | 6384 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 6385 | { |
bfdaab09 | 6386 | unsigned long exit_qualification; |
6affcbed | 6387 | int size, in, string, ret; |
039576c0 | 6388 | unsigned port; |
6aa8b732 | 6389 | |
bfdaab09 | 6390 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 6391 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 6392 | in = (exit_qualification & 8) != 0; |
e70669ab | 6393 | |
cf8f70bf | 6394 | ++vcpu->stat.io_exits; |
e70669ab | 6395 | |
cf8f70bf | 6396 | if (string || in) |
51d8b661 | 6397 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 6398 | |
cf8f70bf GN |
6399 | port = exit_qualification >> 16; |
6400 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 6401 | |
6affcbed KH |
6402 | ret = kvm_skip_emulated_instruction(vcpu); |
6403 | ||
6404 | /* | |
6405 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
6406 | * KVM_EXIT_DEBUG here. | |
6407 | */ | |
6408 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
6409 | } |
6410 | ||
102d8325 IM |
6411 | static void |
6412 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
6413 | { | |
6414 | /* | |
6415 | * Patch in the VMCALL instruction: | |
6416 | */ | |
6417 | hypercall[0] = 0x0f; | |
6418 | hypercall[1] = 0x01; | |
6419 | hypercall[2] = 0xc1; | |
102d8325 IM |
6420 | } |
6421 | ||
0fa06071 | 6422 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
6423 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
6424 | { | |
eeadf9e7 | 6425 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
6426 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6427 | unsigned long orig_val = val; | |
6428 | ||
eeadf9e7 NHE |
6429 | /* |
6430 | * We get here when L2 changed cr0 in a way that did not change | |
6431 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
6432 | * but did change L0 shadowed bits. So we first calculate the |
6433 | * effective cr0 value that L1 would like to write into the | |
6434 | * hardware. It consists of the L2-owned bits from the new | |
6435 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 6436 | */ |
1a0d74e6 JK |
6437 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
6438 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
6439 | ||
3899152c | 6440 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 6441 | return 1; |
1a0d74e6 JK |
6442 | |
6443 | if (kvm_set_cr0(vcpu, val)) | |
6444 | return 1; | |
6445 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 6446 | return 0; |
1a0d74e6 JK |
6447 | } else { |
6448 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 6449 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 6450 | return 1; |
3899152c | 6451 | |
eeadf9e7 | 6452 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 6453 | } |
eeadf9e7 NHE |
6454 | } |
6455 | ||
6456 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
6457 | { | |
6458 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
6459 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6460 | unsigned long orig_val = val; | |
6461 | ||
6462 | /* analogously to handle_set_cr0 */ | |
6463 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
6464 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
6465 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 6466 | return 1; |
1a0d74e6 | 6467 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
6468 | return 0; |
6469 | } else | |
6470 | return kvm_set_cr4(vcpu, val); | |
6471 | } | |
6472 | ||
851ba692 | 6473 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6474 | { |
229456fc | 6475 | unsigned long exit_qualification, val; |
6aa8b732 AK |
6476 | int cr; |
6477 | int reg; | |
49a9b07e | 6478 | int err; |
6affcbed | 6479 | int ret; |
6aa8b732 | 6480 | |
bfdaab09 | 6481 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
6482 | cr = exit_qualification & 15; |
6483 | reg = (exit_qualification >> 8) & 15; | |
6484 | switch ((exit_qualification >> 4) & 3) { | |
6485 | case 0: /* mov to cr */ | |
1e32c079 | 6486 | val = kvm_register_readl(vcpu, reg); |
229456fc | 6487 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
6488 | switch (cr) { |
6489 | case 0: | |
eeadf9e7 | 6490 | err = handle_set_cr0(vcpu, val); |
6affcbed | 6491 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6492 | case 3: |
2390218b | 6493 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 6494 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6495 | case 4: |
eeadf9e7 | 6496 | err = handle_set_cr4(vcpu, val); |
6affcbed | 6497 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
6498 | case 8: { |
6499 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 6500 | u8 cr8 = (u8)val; |
eea1cff9 | 6501 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 6502 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 6503 | if (lapic_in_kernel(vcpu)) |
6affcbed | 6504 | return ret; |
0a5fff19 | 6505 | if (cr8_prev <= cr8) |
6affcbed KH |
6506 | return ret; |
6507 | /* | |
6508 | * TODO: we might be squashing a | |
6509 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
6510 | * KVM_EXIT_DEBUG here. | |
6511 | */ | |
851ba692 | 6512 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
6513 | return 0; |
6514 | } | |
4b8073e4 | 6515 | } |
6aa8b732 | 6516 | break; |
25c4c276 | 6517 | case 2: /* clts */ |
bd7e5b08 PB |
6518 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
6519 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 6520 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 6521 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6522 | case 1: /*mov from cr*/ |
6523 | switch (cr) { | |
6524 | case 3: | |
9f8fe504 AK |
6525 | val = kvm_read_cr3(vcpu); |
6526 | kvm_register_write(vcpu, reg, val); | |
6527 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6528 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 6529 | case 8: |
229456fc MT |
6530 | val = kvm_get_cr8(vcpu); |
6531 | kvm_register_write(vcpu, reg, val); | |
6532 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6533 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6534 | } |
6535 | break; | |
6536 | case 3: /* lmsw */ | |
a1f83a74 | 6537 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6538 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6539 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6540 | |
6affcbed | 6541 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6542 | default: |
6543 | break; | |
6544 | } | |
851ba692 | 6545 | vcpu->run->exit_reason = 0; |
a737f256 | 6546 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6547 | (int)(exit_qualification >> 4) & 3, cr); |
6548 | return 0; | |
6549 | } | |
6550 | ||
851ba692 | 6551 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6552 | { |
bfdaab09 | 6553 | unsigned long exit_qualification; |
16f8a6f9 NA |
6554 | int dr, dr7, reg; |
6555 | ||
6556 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6557 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6558 | ||
6559 | /* First, if DR does not exist, trigger UD */ | |
6560 | if (!kvm_require_dr(vcpu, dr)) | |
6561 | return 1; | |
6aa8b732 | 6562 | |
f2483415 | 6563 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6564 | if (!kvm_require_cpl(vcpu, 0)) |
6565 | return 1; | |
16f8a6f9 NA |
6566 | dr7 = vmcs_readl(GUEST_DR7); |
6567 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6568 | /* |
6569 | * As the vm-exit takes precedence over the debug trap, we | |
6570 | * need to emulate the latter, either for the host or the | |
6571 | * guest debugging itself. | |
6572 | */ | |
6573 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6574 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6575 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6576 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6577 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6578 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6579 | return 0; |
6580 | } else { | |
7305eb5d | 6581 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6582 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6583 | kvm_queue_exception(vcpu, DB_VECTOR); |
6584 | return 1; | |
6585 | } | |
6586 | } | |
6587 | ||
81908bf4 | 6588 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6589 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6590 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6591 | |
6592 | /* | |
6593 | * No more DR vmexits; force a reload of the debug registers | |
6594 | * and reenter on this instruction. The next vmexit will | |
6595 | * retrieve the full state of the debug registers. | |
6596 | */ | |
6597 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6598 | return 1; | |
6599 | } | |
6600 | ||
42dbaa5a JK |
6601 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6602 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6603 | unsigned long val; |
4c4d563b JK |
6604 | |
6605 | if (kvm_get_dr(vcpu, dr, &val)) | |
6606 | return 1; | |
6607 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6608 | } else |
5777392e | 6609 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6610 | return 1; |
6611 | ||
6affcbed | 6612 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6613 | } |
6614 | ||
73aaf249 JK |
6615 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6616 | { | |
6617 | return vcpu->arch.dr6; | |
6618 | } | |
6619 | ||
6620 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6621 | { | |
6622 | } | |
6623 | ||
81908bf4 PB |
6624 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6625 | { | |
81908bf4 PB |
6626 | get_debugreg(vcpu->arch.db[0], 0); |
6627 | get_debugreg(vcpu->arch.db[1], 1); | |
6628 | get_debugreg(vcpu->arch.db[2], 2); | |
6629 | get_debugreg(vcpu->arch.db[3], 3); | |
6630 | get_debugreg(vcpu->arch.dr6, 6); | |
6631 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6632 | ||
6633 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6634 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6635 | } |
6636 | ||
020df079 GN |
6637 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6638 | { | |
6639 | vmcs_writel(GUEST_DR7, val); | |
6640 | } | |
6641 | ||
851ba692 | 6642 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6643 | { |
6a908b62 | 6644 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6645 | } |
6646 | ||
851ba692 | 6647 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6648 | { |
ad312c7c | 6649 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6650 | struct msr_data msr_info; |
6aa8b732 | 6651 | |
609e36d3 PB |
6652 | msr_info.index = ecx; |
6653 | msr_info.host_initiated = false; | |
6654 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6655 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6656 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6657 | return 1; |
6658 | } | |
6659 | ||
609e36d3 | 6660 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6661 | |
6aa8b732 | 6662 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6663 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6664 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6665 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6666 | } |
6667 | ||
851ba692 | 6668 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6669 | { |
8fe8ab46 | 6670 | struct msr_data msr; |
ad312c7c ZX |
6671 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6672 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6673 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6674 | |
8fe8ab46 WA |
6675 | msr.data = data; |
6676 | msr.index = ecx; | |
6677 | msr.host_initiated = false; | |
854e8bb1 | 6678 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6679 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6680 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6681 | return 1; |
6682 | } | |
6683 | ||
59200273 | 6684 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6685 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6686 | } |
6687 | ||
851ba692 | 6688 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6689 | { |
eb90f341 | 6690 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6691 | return 1; |
6692 | } | |
6693 | ||
851ba692 | 6694 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6695 | { |
47c0152e PB |
6696 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6697 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6698 | |
3842d135 AK |
6699 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6700 | ||
a26bf12a | 6701 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6702 | return 1; |
6703 | } | |
6704 | ||
851ba692 | 6705 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6706 | { |
d3bef15f | 6707 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6708 | } |
6709 | ||
851ba692 | 6710 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6711 | { |
0d9c055e | 6712 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6713 | } |
6714 | ||
ec25d5e6 GN |
6715 | static int handle_invd(struct kvm_vcpu *vcpu) |
6716 | { | |
51d8b661 | 6717 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6718 | } |
6719 | ||
851ba692 | 6720 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6721 | { |
f9c617f6 | 6722 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6723 | |
6724 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6725 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6726 | } |
6727 | ||
fee84b07 AK |
6728 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6729 | { | |
6730 | int err; | |
6731 | ||
6732 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6733 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6734 | } |
6735 | ||
851ba692 | 6736 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6737 | { |
6affcbed | 6738 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6739 | } |
6740 | ||
2acf923e DC |
6741 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6742 | { | |
6743 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6744 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6745 | ||
6746 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6747 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6748 | return 1; |
6749 | } | |
6750 | ||
f53cd63c WL |
6751 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6752 | { | |
6affcbed | 6753 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6754 | WARN(1, "this should never happen\n"); |
6755 | return 1; | |
6756 | } | |
6757 | ||
6758 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6759 | { | |
6affcbed | 6760 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6761 | WARN(1, "this should never happen\n"); |
6762 | return 1; | |
6763 | } | |
6764 | ||
851ba692 | 6765 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6766 | { |
58fbbf26 KT |
6767 | if (likely(fasteoi)) { |
6768 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6769 | int access_type, offset; | |
6770 | ||
6771 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6772 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6773 | /* | |
6774 | * Sane guest uses MOV to write EOI, with written value | |
6775 | * not cared. So make a short-circuit here by avoiding | |
6776 | * heavy instruction emulation. | |
6777 | */ | |
6778 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6779 | (offset == APIC_EOI)) { | |
6780 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6781 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6782 | } |
6783 | } | |
51d8b661 | 6784 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6785 | } |
6786 | ||
c7c9c56c YZ |
6787 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6788 | { | |
6789 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6790 | int vector = exit_qualification & 0xff; | |
6791 | ||
6792 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6793 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6794 | return 1; | |
6795 | } | |
6796 | ||
83d4c286 YZ |
6797 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6798 | { | |
6799 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6800 | u32 offset = exit_qualification & 0xfff; | |
6801 | ||
6802 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6803 | kvm_apic_write_nodecode(vcpu, offset); | |
6804 | return 1; | |
6805 | } | |
6806 | ||
851ba692 | 6807 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6808 | { |
60637aac | 6809 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6810 | unsigned long exit_qualification; |
e269fb21 JK |
6811 | bool has_error_code = false; |
6812 | u32 error_code = 0; | |
37817f29 | 6813 | u16 tss_selector; |
7f3d35fd | 6814 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6815 | |
6816 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6817 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6818 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6819 | |
6820 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6821 | ||
6822 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6823 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6824 | switch (type) { | |
6825 | case INTR_TYPE_NMI_INTR: | |
6826 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6827 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6828 | break; |
6829 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6830 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6831 | kvm_clear_interrupt_queue(vcpu); |
6832 | break; | |
6833 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6834 | if (vmx->idt_vectoring_info & |
6835 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6836 | has_error_code = true; | |
6837 | error_code = | |
6838 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6839 | } | |
6840 | /* fall through */ | |
64a7ec06 GN |
6841 | case INTR_TYPE_SOFT_EXCEPTION: |
6842 | kvm_clear_exception_queue(vcpu); | |
6843 | break; | |
6844 | default: | |
6845 | break; | |
6846 | } | |
60637aac | 6847 | } |
37817f29 IE |
6848 | tss_selector = exit_qualification; |
6849 | ||
64a7ec06 GN |
6850 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6851 | type != INTR_TYPE_EXT_INTR && | |
6852 | type != INTR_TYPE_NMI_INTR)) | |
6853 | skip_emulated_instruction(vcpu); | |
6854 | ||
7f3d35fd KW |
6855 | if (kvm_task_switch(vcpu, tss_selector, |
6856 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6857 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6858 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6859 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6860 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6861 | return 0; |
acb54517 | 6862 | } |
42dbaa5a | 6863 | |
42dbaa5a JK |
6864 | /* |
6865 | * TODO: What about debug traps on tss switch? | |
6866 | * Are we supposed to inject them and update dr6? | |
6867 | */ | |
6868 | ||
6869 | return 1; | |
37817f29 IE |
6870 | } |
6871 | ||
851ba692 | 6872 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6873 | { |
f9c617f6 | 6874 | unsigned long exit_qualification; |
1439442c | 6875 | gpa_t gpa; |
eebed243 | 6876 | u64 error_code; |
1439442c | 6877 | |
f9c617f6 | 6878 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6879 | |
0be9c7a8 GN |
6880 | /* |
6881 | * EPT violation happened while executing iret from NMI, | |
6882 | * "blocked by NMI" bit has to be set before next VM entry. | |
6883 | * There are errata that may cause this bit to not be set: | |
6884 | * AAK134, BY25. | |
6885 | */ | |
bcd1c294 | 6886 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
d02fcf50 | 6887 | enable_vnmi && |
bcd1c294 | 6888 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
6889 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6890 | ||
1439442c | 6891 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6892 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6893 | |
27959a44 | 6894 | /* Is it a read fault? */ |
ab22a473 | 6895 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
6896 | ? PFERR_USER_MASK : 0; |
6897 | /* Is it a write fault? */ | |
ab22a473 | 6898 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
6899 | ? PFERR_WRITE_MASK : 0; |
6900 | /* Is it a fetch fault? */ | |
ab22a473 | 6901 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
6902 | ? PFERR_FETCH_MASK : 0; |
6903 | /* ept page table entry is present? */ | |
6904 | error_code |= (exit_qualification & | |
6905 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
6906 | EPT_VIOLATION_EXECUTABLE)) | |
6907 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 6908 | |
eebed243 PB |
6909 | error_code |= (exit_qualification & 0x100) != 0 ? |
6910 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 6911 | |
25d92081 | 6912 | vcpu->arch.exit_qualification = exit_qualification; |
4f5982a5 | 6913 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6914 | } |
6915 | ||
851ba692 | 6916 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6917 | { |
f735d4af | 6918 | int ret; |
68f89400 MT |
6919 | gpa_t gpa; |
6920 | ||
9034e6e8 PB |
6921 | /* |
6922 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
6923 | * nGPA here instead of the required GPA. | |
6924 | */ | |
68f89400 | 6925 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
6926 | if (!is_guest_mode(vcpu) && |
6927 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 6928 | trace_kvm_fast_mmio(gpa); |
60165b0a VK |
6929 | /* |
6930 | * Doing kvm_skip_emulated_instruction() depends on undefined | |
6931 | * behavior: Intel's manual doesn't mandate | |
6932 | * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG | |
6933 | * occurs and while on real hardware it was observed to be set, | |
6934 | * other hypervisors (namely Hyper-V) don't set it, we end up | |
6935 | * advancing IP with some random value. Disable fast mmio when | |
6936 | * running nested and keep it for real hardware in hope that | |
6937 | * VM_EXIT_INSTRUCTION_LEN will always be set correctly. | |
6938 | */ | |
6939 | if (!static_cpu_has(X86_FEATURE_HYPERVISOR)) | |
6940 | return kvm_skip_emulated_instruction(vcpu); | |
6941 | else | |
6942 | return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP, | |
6943 | NULL, 0) == EMULATE_DONE; | |
68c3b4d1 | 6944 | } |
68f89400 | 6945 | |
e08d26f0 PB |
6946 | ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
6947 | if (ret >= 0) | |
6948 | return ret; | |
ce88decf XG |
6949 | |
6950 | /* It is the real ept misconfig */ | |
f735d4af | 6951 | WARN_ON(1); |
68f89400 | 6952 | |
851ba692 AK |
6953 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6954 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6955 | |
6956 | return 0; | |
6957 | } | |
6958 | ||
851ba692 | 6959 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 6960 | { |
d02fcf50 | 6961 | WARN_ON_ONCE(!enable_vnmi); |
47c0152e PB |
6962 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6963 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 6964 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 6965 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6966 | |
6967 | return 1; | |
6968 | } | |
6969 | ||
80ced186 | 6970 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6971 | { |
8b3079a5 AK |
6972 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6973 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6974 | int ret = 1; |
49e9d557 AK |
6975 | u32 cpu_exec_ctrl; |
6976 | bool intr_window_requested; | |
b8405c18 | 6977 | unsigned count = 130; |
49e9d557 AK |
6978 | |
6979 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6980 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6981 | |
98eb2f8b | 6982 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6983 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6984 | return handle_interrupt_window(&vmx->vcpu); |
6985 | ||
72875d8a | 6986 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
6987 | return 1; |
6988 | ||
9b8ae637 | 6989 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 6990 | |
ac0a48c3 | 6991 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6992 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6993 | ret = 0; |
6994 | goto out; | |
6995 | } | |
1d5a4d9b | 6996 | |
299f0328 SC |
6997 | if (err != EMULATE_DONE) |
6998 | goto emulation_error; | |
6999 | ||
7000 | if (vmx->emulation_required && !vmx->rmode.vm86_active && | |
7001 | vcpu->arch.exception.pending) | |
7002 | goto emulation_error; | |
ea953ef0 | 7003 | |
8d76c49e GN |
7004 | if (vcpu->arch.halt_request) { |
7005 | vcpu->arch.halt_request = 0; | |
5cb56059 | 7006 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
7007 | goto out; |
7008 | } | |
7009 | ||
ea953ef0 | 7010 | if (signal_pending(current)) |
80ced186 | 7011 | goto out; |
ea953ef0 MG |
7012 | if (need_resched()) |
7013 | schedule(); | |
7014 | } | |
7015 | ||
80ced186 MG |
7016 | out: |
7017 | return ret; | |
299f0328 SC |
7018 | |
7019 | emulation_error: | |
7020 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7021 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7022 | vcpu->run->internal.ndata = 0; | |
7023 | return 0; | |
ea953ef0 MG |
7024 | } |
7025 | ||
b4a2d31d RK |
7026 | static int __grow_ple_window(int val) |
7027 | { | |
7028 | if (ple_window_grow < 1) | |
7029 | return ple_window; | |
7030 | ||
7031 | val = min(val, ple_window_actual_max); | |
7032 | ||
7033 | if (ple_window_grow < ple_window) | |
7034 | val *= ple_window_grow; | |
7035 | else | |
7036 | val += ple_window_grow; | |
7037 | ||
7038 | return val; | |
7039 | } | |
7040 | ||
7041 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
7042 | { | |
7043 | if (modifier < 1) | |
7044 | return ple_window; | |
7045 | ||
7046 | if (modifier < ple_window) | |
7047 | val /= modifier; | |
7048 | else | |
7049 | val -= modifier; | |
7050 | ||
7051 | return max(val, minimum); | |
7052 | } | |
7053 | ||
7054 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
7055 | { | |
7056 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7057 | int old = vmx->ple_window; | |
7058 | ||
7059 | vmx->ple_window = __grow_ple_window(old); | |
7060 | ||
7061 | if (vmx->ple_window != old) | |
7062 | vmx->ple_window_dirty = true; | |
7b46268d RK |
7063 | |
7064 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
7065 | } |
7066 | ||
7067 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
7068 | { | |
7069 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7070 | int old = vmx->ple_window; | |
7071 | ||
7072 | vmx->ple_window = __shrink_ple_window(old, | |
7073 | ple_window_shrink, ple_window); | |
7074 | ||
7075 | if (vmx->ple_window != old) | |
7076 | vmx->ple_window_dirty = true; | |
7b46268d RK |
7077 | |
7078 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
7079 | } |
7080 | ||
7081 | /* | |
7082 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
7083 | * ple_window_max. (See __grow_ple_window for the reason.) | |
7084 | * This prevents overflows, because ple_window_max is int. | |
7085 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
7086 | * this process. | |
7087 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
7088 | */ | |
7089 | static void update_ple_window_actual_max(void) | |
7090 | { | |
7091 | ple_window_actual_max = | |
7092 | __shrink_ple_window(max(ple_window_max, ple_window), | |
7093 | ple_window_grow, INT_MIN); | |
7094 | } | |
7095 | ||
bf9f6ac8 FW |
7096 | /* |
7097 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
7098 | */ | |
7099 | static void wakeup_handler(void) | |
7100 | { | |
7101 | struct kvm_vcpu *vcpu; | |
7102 | int cpu = smp_processor_id(); | |
7103 | ||
7104 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
7105 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
7106 | blocked_vcpu_list) { | |
7107 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
7108 | ||
7109 | if (pi_test_on(pi_desc) == 1) | |
7110 | kvm_vcpu_kick(vcpu); | |
7111 | } | |
7112 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
7113 | } | |
7114 | ||
f160c7b7 JS |
7115 | void vmx_enable_tdp(void) |
7116 | { | |
7117 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
7118 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
7119 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
7120 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
7121 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 7122 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
7123 | |
7124 | ept_set_mmio_spte_mask(); | |
7125 | kvm_enable_tdp(); | |
7126 | } | |
7127 | ||
f2c7648d TC |
7128 | static __init int hardware_setup(void) |
7129 | { | |
4b0be90f | 7130 | int r = -ENOMEM, i; |
34a1cd60 TC |
7131 | |
7132 | rdmsrl_safe(MSR_EFER, &host_efer); | |
7133 | ||
7134 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
7135 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
7136 | ||
23611332 RK |
7137 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
7138 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
7139 | if (!vmx_bitmap[i]) | |
7140 | goto out; | |
7141 | } | |
34a1cd60 | 7142 | |
34a1cd60 TC |
7143 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
7144 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
7145 | ||
34a1cd60 | 7146 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
34a1cd60 TC |
7147 | |
7148 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
7149 | ||
34a1cd60 TC |
7150 | if (setup_vmcs_config(&vmcs_config) < 0) { |
7151 | r = -EIO; | |
23611332 | 7152 | goto out; |
baa03522 | 7153 | } |
f2c7648d TC |
7154 | |
7155 | if (boot_cpu_has(X86_FEATURE_NX)) | |
7156 | kvm_enable_efer_bits(EFER_NX); | |
7157 | ||
08d839c4 WL |
7158 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
7159 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 7160 | enable_vpid = 0; |
08d839c4 | 7161 | |
f2c7648d TC |
7162 | if (!cpu_has_vmx_shadow_vmcs()) |
7163 | enable_shadow_vmcs = 0; | |
7164 | if (enable_shadow_vmcs) | |
7165 | init_vmcs_shadow_fields(); | |
7166 | ||
7167 | if (!cpu_has_vmx_ept() || | |
42aa53b4 | 7168 | !cpu_has_vmx_ept_4levels() || |
f5f51586 | 7169 | !cpu_has_vmx_ept_mt_wb() || |
8ad8182e | 7170 | !cpu_has_vmx_invept_global()) |
f2c7648d | 7171 | enable_ept = 0; |
f2c7648d | 7172 | |
fce6ac4c | 7173 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) |
f2c7648d TC |
7174 | enable_ept_ad_bits = 0; |
7175 | ||
8ad8182e | 7176 | if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) |
f2c7648d TC |
7177 | enable_unrestricted_guest = 0; |
7178 | ||
ad15a296 | 7179 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
7180 | flexpriority_enabled = 0; |
7181 | ||
d02fcf50 PB |
7182 | if (!cpu_has_virtual_nmis()) |
7183 | enable_vnmi = 0; | |
7184 | ||
ad15a296 PB |
7185 | /* |
7186 | * set_apic_access_page_addr() is used to reload apic access | |
7187 | * page upon invalidation. No need to do anything if not | |
7188 | * using the APIC_ACCESS_ADDR VMCS field. | |
7189 | */ | |
7190 | if (!flexpriority_enabled) | |
f2c7648d | 7191 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
7192 | |
7193 | if (!cpu_has_vmx_tpr_shadow()) | |
7194 | kvm_x86_ops->update_cr8_intercept = NULL; | |
7195 | ||
7196 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
7197 | kvm_disable_largepages(); | |
7198 | ||
0f107682 | 7199 | if (!cpu_has_vmx_ple()) { |
f2c7648d | 7200 | ple_gap = 0; |
0f107682 WL |
7201 | ple_window = 0; |
7202 | ple_window_grow = 0; | |
7203 | ple_window_max = 0; | |
7204 | ple_window_shrink = 0; | |
7205 | } | |
f2c7648d | 7206 | |
76dfafd5 | 7207 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 7208 | enable_apicv = 0; |
76dfafd5 PB |
7209 | kvm_x86_ops->sync_pir_to_irr = NULL; |
7210 | } | |
f2c7648d | 7211 | |
64903d61 HZ |
7212 | if (cpu_has_vmx_tsc_scaling()) { |
7213 | kvm_has_tsc_control = true; | |
7214 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
7215 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
7216 | } | |
7217 | ||
04bb92e4 WL |
7218 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
7219 | ||
f160c7b7 JS |
7220 | if (enable_ept) |
7221 | vmx_enable_tdp(); | |
7222 | else | |
baa03522 TC |
7223 | kvm_disable_tdp(); |
7224 | ||
7225 | update_ple_window_actual_max(); | |
7226 | ||
843e4330 KH |
7227 | /* |
7228 | * Only enable PML when hardware supports PML feature, and both EPT | |
7229 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
7230 | */ | |
7231 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
7232 | enable_pml = 0; | |
7233 | ||
7234 | if (!enable_pml) { | |
7235 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
7236 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
7237 | kvm_x86_ops->flush_log_dirty = NULL; | |
7238 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
7239 | } | |
7240 | ||
64672c95 YJ |
7241 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
7242 | u64 vmx_msr; | |
7243 | ||
7244 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
7245 | cpu_preemption_timer_multi = | |
7246 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
7247 | } else { | |
7248 | kvm_x86_ops->set_hv_timer = NULL; | |
7249 | kvm_x86_ops->cancel_hv_timer = NULL; | |
7250 | } | |
7251 | ||
bf9f6ac8 FW |
7252 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
7253 | ||
c45dcc71 AR |
7254 | kvm_mce_cap_supported |= MCG_LMCE_P; |
7255 | ||
f2c7648d | 7256 | return alloc_kvm_area(); |
34a1cd60 | 7257 | |
34a1cd60 | 7258 | out: |
23611332 RK |
7259 | for (i = 0; i < VMX_BITMAP_NR; i++) |
7260 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
7261 | |
7262 | return r; | |
f2c7648d TC |
7263 | } |
7264 | ||
7265 | static __exit void hardware_unsetup(void) | |
7266 | { | |
23611332 RK |
7267 | int i; |
7268 | ||
7269 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
7270 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 7271 | |
f2c7648d TC |
7272 | free_kvm_area(); |
7273 | } | |
7274 | ||
4b8d54f9 ZE |
7275 | /* |
7276 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
7277 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
7278 | */ | |
9fb41ba8 | 7279 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 7280 | { |
b4a2d31d RK |
7281 | if (ple_gap) |
7282 | grow_ple_window(vcpu); | |
7283 | ||
de63ad4c LM |
7284 | /* |
7285 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
7286 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
7287 | * never set PAUSE_EXITING and just set PLE if supported, | |
7288 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
7289 | */ | |
7290 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 7291 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
7292 | } |
7293 | ||
87c00572 | 7294 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 7295 | { |
6affcbed | 7296 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
7297 | } |
7298 | ||
87c00572 GS |
7299 | static int handle_mwait(struct kvm_vcpu *vcpu) |
7300 | { | |
7301 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
7302 | return handle_nop(vcpu); | |
7303 | } | |
7304 | ||
45ec368c JM |
7305 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
7306 | { | |
7307 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7308 | return 1; | |
7309 | } | |
7310 | ||
5f3d45e7 MD |
7311 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
7312 | { | |
7313 | return 1; | |
7314 | } | |
7315 | ||
87c00572 GS |
7316 | static int handle_monitor(struct kvm_vcpu *vcpu) |
7317 | { | |
7318 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
7319 | return handle_nop(vcpu); | |
7320 | } | |
7321 | ||
0658fbaa ACL |
7322 | /* |
7323 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
7324 | * set the success or error code of an emulated VMX instruction, as specified | |
7325 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
7326 | */ | |
7327 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
7328 | { | |
7329 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
7330 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7331 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
7332 | } | |
7333 | ||
7334 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
7335 | { | |
7336 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7337 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
7338 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7339 | | X86_EFLAGS_CF); | |
7340 | } | |
7341 | ||
145c28dd | 7342 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
7343 | u32 vm_instruction_error) |
7344 | { | |
7345 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
7346 | /* | |
7347 | * failValid writes the error number to the current VMCS, which | |
7348 | * can't be done there isn't a current VMCS. | |
7349 | */ | |
7350 | nested_vmx_failInvalid(vcpu); | |
7351 | return; | |
7352 | } | |
7353 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7354 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7355 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7356 | | X86_EFLAGS_ZF); | |
7357 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
7358 | /* | |
7359 | * We don't need to force a shadow sync because | |
7360 | * VM_INSTRUCTION_ERROR is not shadowed | |
7361 | */ | |
7362 | } | |
145c28dd | 7363 | |
ff651cb6 WV |
7364 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
7365 | { | |
7366 | /* TODO: not to reset guest simply here. */ | |
7367 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 7368 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
7369 | } |
7370 | ||
f4124500 JK |
7371 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
7372 | { | |
7373 | struct vcpu_vmx *vmx = | |
7374 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
7375 | ||
7376 | vmx->nested.preemption_timer_expired = true; | |
7377 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
7378 | kvm_vcpu_kick(&vmx->vcpu); | |
7379 | ||
7380 | return HRTIMER_NORESTART; | |
7381 | } | |
7382 | ||
19677e32 BD |
7383 | /* |
7384 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
7385 | * exit caused by such an instruction (run by a guest hypervisor). | |
7386 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
7387 | * #UD or #GP. | |
7388 | */ | |
7389 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
7390 | unsigned long exit_qualification, | |
f9eb4af6 | 7391 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 7392 | { |
f9eb4af6 EK |
7393 | gva_t off; |
7394 | bool exn; | |
7395 | struct kvm_segment s; | |
7396 | ||
19677e32 BD |
7397 | /* |
7398 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
7399 | * Execution", on an exit, vmx_instruction_info holds most of the | |
7400 | * addressing components of the operand. Only the displacement part | |
7401 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
7402 | * For how an actual address is calculated from all these components, | |
7403 | * refer to Vol. 1, "Operand Addressing". | |
7404 | */ | |
7405 | int scaling = vmx_instruction_info & 3; | |
7406 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
7407 | bool is_reg = vmx_instruction_info & (1u << 10); | |
7408 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
7409 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
7410 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
7411 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
7412 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
7413 | ||
7414 | if (is_reg) { | |
7415 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7416 | return 1; | |
7417 | } | |
7418 | ||
7419 | /* Addr = segment_base + offset */ | |
7420 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 7421 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 7422 | if (base_is_valid) |
f9eb4af6 | 7423 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 7424 | if (index_is_valid) |
f9eb4af6 EK |
7425 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
7426 | vmx_get_segment(vcpu, &s, seg_reg); | |
7427 | *ret = s.base + off; | |
19677e32 BD |
7428 | |
7429 | if (addr_size == 1) /* 32 bit */ | |
7430 | *ret &= 0xffffffff; | |
7431 | ||
f9eb4af6 EK |
7432 | /* Checks for #GP/#SS exceptions. */ |
7433 | exn = false; | |
ff30ef40 QC |
7434 | if (is_long_mode(vcpu)) { |
7435 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
7436 | * non-canonical form. This is the only check on the memory | |
7437 | * destination for long mode! | |
7438 | */ | |
fd8cb433 | 7439 | exn = is_noncanonical_address(*ret, vcpu); |
ff30ef40 | 7440 | } else if (is_protmode(vcpu)) { |
f9eb4af6 EK |
7441 | /* Protected mode: apply checks for segment validity in the |
7442 | * following order: | |
7443 | * - segment type check (#GP(0) may be thrown) | |
7444 | * - usability check (#GP(0)/#SS(0)) | |
7445 | * - limit check (#GP(0)/#SS(0)) | |
7446 | */ | |
7447 | if (wr) | |
7448 | /* #GP(0) if the destination operand is located in a | |
7449 | * read-only data segment or any code segment. | |
7450 | */ | |
7451 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7452 | else | |
7453 | /* #GP(0) if the source operand is located in an | |
7454 | * execute-only code segment | |
7455 | */ | |
7456 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7457 | if (exn) { |
7458 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7459 | return 1; | |
7460 | } | |
f9eb4af6 EK |
7461 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7462 | */ | |
7463 | exn = (s.unusable != 0); | |
7464 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
7465 | * operand is outside the segment limit. | |
7466 | */ | |
7467 | exn = exn || (off + sizeof(u64) > s.limit); | |
7468 | } | |
7469 | if (exn) { | |
7470 | kvm_queue_exception_e(vcpu, | |
7471 | seg_reg == VCPU_SREG_SS ? | |
7472 | SS_VECTOR : GP_VECTOR, | |
7473 | 0); | |
7474 | return 1; | |
7475 | } | |
7476 | ||
19677e32 BD |
7477 | return 0; |
7478 | } | |
7479 | ||
cbf71279 | 7480 | static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) |
3573e22c BD |
7481 | { |
7482 | gva_t gva; | |
3573e22c | 7483 | struct x86_exception e; |
3573e22c BD |
7484 | |
7485 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7486 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7487 | return 1; |
7488 | ||
40d2dba3 | 7489 | if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) { |
3573e22c BD |
7490 | kvm_inject_page_fault(vcpu, &e); |
7491 | return 1; | |
7492 | } | |
7493 | ||
3573e22c BD |
7494 | return 0; |
7495 | } | |
7496 | ||
e29acc55 JM |
7497 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
7498 | { | |
7499 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7500 | struct vmcs *shadow_vmcs; | |
b6d7026d | 7501 | int r; |
e29acc55 | 7502 | |
b6d7026d PB |
7503 | r = alloc_loaded_vmcs(&vmx->nested.vmcs02); |
7504 | if (r < 0) | |
8819227c | 7505 | goto out_vmcs02; |
8819227c | 7506 | |
e29acc55 JM |
7507 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); |
7508 | if (!vmx->nested.cached_vmcs12) | |
7509 | goto out_cached_vmcs12; | |
7510 | ||
7511 | if (enable_shadow_vmcs) { | |
7512 | shadow_vmcs = alloc_vmcs(); | |
7513 | if (!shadow_vmcs) | |
7514 | goto out_shadow_vmcs; | |
7515 | /* mark vmcs as shadow */ | |
7516 | shadow_vmcs->revision_id |= (1u << 31); | |
7517 | /* init shadow vmcs */ | |
7518 | vmcs_clear(shadow_vmcs); | |
7519 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7520 | } | |
7521 | ||
e29acc55 JM |
7522 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
7523 | HRTIMER_MODE_REL_PINNED); | |
7524 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7525 | ||
7526 | vmx->nested.vmxon = true; | |
7527 | return 0; | |
7528 | ||
7529 | out_shadow_vmcs: | |
7530 | kfree(vmx->nested.cached_vmcs12); | |
7531 | ||
7532 | out_cached_vmcs12: | |
8819227c JM |
7533 | free_loaded_vmcs(&vmx->nested.vmcs02); |
7534 | ||
7535 | out_vmcs02: | |
e29acc55 JM |
7536 | return -ENOMEM; |
7537 | } | |
7538 | ||
ec378aee NHE |
7539 | /* |
7540 | * Emulate the VMXON instruction. | |
7541 | * Currently, we just remember that VMX is active, and do not save or even | |
7542 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7543 | * do not currently need to store anything in that guest-allocated memory | |
7544 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7545 | * argument is different from the VMXON pointer (which the spec says they do). | |
7546 | */ | |
7547 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7548 | { | |
e29acc55 | 7549 | int ret; |
cbf71279 RK |
7550 | gpa_t vmptr; |
7551 | struct page *page; | |
ec378aee | 7552 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7553 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7554 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7555 | |
70f3aac9 JM |
7556 | /* |
7557 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7558 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7559 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7560 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7561 | * have already been checked by hardware, prior to the VM-exit for | |
7562 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7563 | * that bit set to 1 in non-root mode. | |
ec378aee | 7564 | */ |
70f3aac9 | 7565 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7566 | kvm_queue_exception(vcpu, UD_VECTOR); |
7567 | return 1; | |
7568 | } | |
7569 | ||
a325262f FW |
7570 | /* CPL=0 must be checked manually. */ |
7571 | if (vmx_get_cpl(vcpu)) { | |
7572 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7573 | return 1; | |
7574 | } | |
7575 | ||
145c28dd AG |
7576 | if (vmx->nested.vmxon) { |
7577 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7578 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7579 | } |
b3897a49 | 7580 | |
3b84080b | 7581 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7582 | != VMXON_NEEDED_FEATURES) { |
7583 | kvm_inject_gp(vcpu, 0); | |
7584 | return 1; | |
7585 | } | |
7586 | ||
cbf71279 | 7587 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
21e7fbe7 | 7588 | return 1; |
cbf71279 RK |
7589 | |
7590 | /* | |
7591 | * SDM 3: 24.11.5 | |
7592 | * The first 4 bytes of VMXON region contain the supported | |
7593 | * VMCS revision identifier | |
7594 | * | |
7595 | * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; | |
7596 | * which replaces physical address width with 32 | |
7597 | */ | |
7598 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { | |
7599 | nested_vmx_failInvalid(vcpu); | |
7600 | return kvm_skip_emulated_instruction(vcpu); | |
7601 | } | |
7602 | ||
5e2f30b7 DH |
7603 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7604 | if (is_error_page(page)) { | |
cbf71279 RK |
7605 | nested_vmx_failInvalid(vcpu); |
7606 | return kvm_skip_emulated_instruction(vcpu); | |
7607 | } | |
7608 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
7609 | kunmap(page); | |
53a70daf | 7610 | kvm_release_page_clean(page); |
cbf71279 RK |
7611 | nested_vmx_failInvalid(vcpu); |
7612 | return kvm_skip_emulated_instruction(vcpu); | |
7613 | } | |
7614 | kunmap(page); | |
53a70daf | 7615 | kvm_release_page_clean(page); |
cbf71279 RK |
7616 | |
7617 | vmx->nested.vmxon_ptr = vmptr; | |
e29acc55 JM |
7618 | ret = enter_vmx_operation(vcpu); |
7619 | if (ret) | |
7620 | return ret; | |
ec378aee | 7621 | |
a25eb114 | 7622 | nested_vmx_succeed(vcpu); |
6affcbed | 7623 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7624 | } |
7625 | ||
7626 | /* | |
7627 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7628 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7629 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7630 | * Note that many of these exceptions have priority over VM exits, so they |
7631 | * don't have to be checked again here. | |
ec378aee NHE |
7632 | */ |
7633 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7634 | { | |
a325262f FW |
7635 | if (vmx_get_cpl(vcpu)) { |
7636 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7637 | return 0; | |
7638 | } | |
7639 | ||
70f3aac9 | 7640 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7641 | kvm_queue_exception(vcpu, UD_VECTOR); |
7642 | return 0; | |
7643 | } | |
ec378aee NHE |
7644 | return 1; |
7645 | } | |
7646 | ||
8ca44e88 DM |
7647 | static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) |
7648 | { | |
7649 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS); | |
7650 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
7651 | } | |
7652 | ||
e7953d7f AG |
7653 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7654 | { | |
9a2a05b9 PB |
7655 | if (vmx->nested.current_vmptr == -1ull) |
7656 | return; | |
7657 | ||
012f83cb | 7658 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7659 | /* copy to memory all shadowed fields in case |
7660 | they were modified */ | |
7661 | copy_shadow_to_vmcs12(vmx); | |
7662 | vmx->nested.sync_shadow_vmcs = false; | |
8ca44e88 | 7663 | vmx_disable_shadow_vmcs(vmx); |
012f83cb | 7664 | } |
705699a1 | 7665 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7666 | |
7667 | /* Flush VMCS12 to guest memory */ | |
9f744c59 PB |
7668 | kvm_vcpu_write_guest_page(&vmx->vcpu, |
7669 | vmx->nested.current_vmptr >> PAGE_SHIFT, | |
7670 | vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); | |
4f2777bc | 7671 | |
9a2a05b9 | 7672 | vmx->nested.current_vmptr = -1ull; |
e7953d7f AG |
7673 | } |
7674 | ||
ec378aee NHE |
7675 | /* |
7676 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7677 | * just stops using VMX. | |
7678 | */ | |
7679 | static void free_nested(struct vcpu_vmx *vmx) | |
7680 | { | |
b7455825 | 7681 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) |
ec378aee | 7682 | return; |
9a2a05b9 | 7683 | |
ec378aee | 7684 | vmx->nested.vmxon = false; |
b7455825 | 7685 | vmx->nested.smm.vmxon = false; |
5c614b35 | 7686 | free_vpid(vmx->nested.vpid02); |
8ca44e88 DM |
7687 | vmx->nested.posted_intr_nv = -1; |
7688 | vmx->nested.current_vmptr = -1ull; | |
355f4fb1 | 7689 | if (enable_shadow_vmcs) { |
8ca44e88 | 7690 | vmx_disable_shadow_vmcs(vmx); |
355f4fb1 JM |
7691 | vmcs_clear(vmx->vmcs01.shadow_vmcs); |
7692 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7693 | vmx->vmcs01.shadow_vmcs = NULL; | |
7694 | } | |
4f2777bc | 7695 | kfree(vmx->nested.cached_vmcs12); |
8819227c | 7696 | /* Unpin physical memory we referred to in the vmcs02 */ |
fe3ef05c | 7697 | if (vmx->nested.apic_access_page) { |
53a70daf | 7698 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 7699 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7700 | } |
a7c0b07d | 7701 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 7702 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 7703 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7704 | } |
705699a1 WV |
7705 | if (vmx->nested.pi_desc_page) { |
7706 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 7707 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
7708 | vmx->nested.pi_desc_page = NULL; |
7709 | vmx->nested.pi_desc = NULL; | |
7710 | } | |
ff2f6fe9 | 7711 | |
8819227c | 7712 | free_loaded_vmcs(&vmx->nested.vmcs02); |
ec378aee NHE |
7713 | } |
7714 | ||
7715 | /* Emulate the VMXOFF instruction */ | |
7716 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7717 | { | |
7718 | if (!nested_vmx_check_permission(vcpu)) | |
7719 | return 1; | |
7720 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7721 | nested_vmx_succeed(vcpu); |
6affcbed | 7722 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7723 | } |
7724 | ||
27d6c865 NHE |
7725 | /* Emulate the VMCLEAR instruction */ |
7726 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7727 | { | |
7728 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7729 | u32 zero = 0; |
27d6c865 | 7730 | gpa_t vmptr; |
27d6c865 NHE |
7731 | |
7732 | if (!nested_vmx_check_permission(vcpu)) | |
7733 | return 1; | |
7734 | ||
cbf71279 | 7735 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
27d6c865 | 7736 | return 1; |
27d6c865 | 7737 | |
cbf71279 RK |
7738 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7739 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
7740 | return kvm_skip_emulated_instruction(vcpu); | |
7741 | } | |
7742 | ||
7743 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7744 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); | |
7745 | return kvm_skip_emulated_instruction(vcpu); | |
7746 | } | |
7747 | ||
9a2a05b9 | 7748 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7749 | nested_release_vmcs12(vmx); |
27d6c865 | 7750 | |
587d7e72 JM |
7751 | kvm_vcpu_write_guest(vcpu, |
7752 | vmptr + offsetof(struct vmcs12, launch_state), | |
7753 | &zero, sizeof(zero)); | |
27d6c865 | 7754 | |
27d6c865 | 7755 | nested_vmx_succeed(vcpu); |
6affcbed | 7756 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7757 | } |
7758 | ||
cd232ad0 NHE |
7759 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7760 | ||
7761 | /* Emulate the VMLAUNCH instruction */ | |
7762 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7763 | { | |
7764 | return nested_vmx_run(vcpu, true); | |
7765 | } | |
7766 | ||
7767 | /* Emulate the VMRESUME instruction */ | |
7768 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7769 | { | |
7770 | ||
7771 | return nested_vmx_run(vcpu, false); | |
7772 | } | |
7773 | ||
49f705c5 NHE |
7774 | /* |
7775 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7776 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7777 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7778 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7779 | * 64-bit fields are to be returned). | |
7780 | */ | |
a2ae9df7 PB |
7781 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7782 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7783 | { |
7784 | short offset = vmcs_field_to_offset(field); | |
7785 | char *p; | |
7786 | ||
7787 | if (offset < 0) | |
a2ae9df7 | 7788 | return offset; |
49f705c5 NHE |
7789 | |
7790 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7791 | ||
7792 | switch (vmcs_field_type(field)) { | |
7793 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7794 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7795 | return 0; |
49f705c5 NHE |
7796 | case VMCS_FIELD_TYPE_U16: |
7797 | *ret = *((u16 *)p); | |
a2ae9df7 | 7798 | return 0; |
49f705c5 NHE |
7799 | case VMCS_FIELD_TYPE_U32: |
7800 | *ret = *((u32 *)p); | |
a2ae9df7 | 7801 | return 0; |
49f705c5 NHE |
7802 | case VMCS_FIELD_TYPE_U64: |
7803 | *ret = *((u64 *)p); | |
a2ae9df7 | 7804 | return 0; |
49f705c5 | 7805 | default: |
a2ae9df7 PB |
7806 | WARN_ON(1); |
7807 | return -ENOENT; | |
49f705c5 NHE |
7808 | } |
7809 | } | |
7810 | ||
20b97fea | 7811 | |
a2ae9df7 PB |
7812 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7813 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7814 | short offset = vmcs_field_to_offset(field); |
7815 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7816 | if (offset < 0) | |
a2ae9df7 | 7817 | return offset; |
20b97fea AG |
7818 | |
7819 | switch (vmcs_field_type(field)) { | |
7820 | case VMCS_FIELD_TYPE_U16: | |
7821 | *(u16 *)p = field_value; | |
a2ae9df7 | 7822 | return 0; |
20b97fea AG |
7823 | case VMCS_FIELD_TYPE_U32: |
7824 | *(u32 *)p = field_value; | |
a2ae9df7 | 7825 | return 0; |
20b97fea AG |
7826 | case VMCS_FIELD_TYPE_U64: |
7827 | *(u64 *)p = field_value; | |
a2ae9df7 | 7828 | return 0; |
20b97fea AG |
7829 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7830 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7831 | return 0; |
20b97fea | 7832 | default: |
a2ae9df7 PB |
7833 | WARN_ON(1); |
7834 | return -ENOENT; | |
20b97fea AG |
7835 | } |
7836 | ||
7837 | } | |
7838 | ||
16f5b903 AG |
7839 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7840 | { | |
7841 | int i; | |
7842 | unsigned long field; | |
7843 | u64 field_value; | |
355f4fb1 | 7844 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7845 | const unsigned long *fields = shadow_read_write_fields; |
7846 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7847 | |
282da870 JK |
7848 | preempt_disable(); |
7849 | ||
16f5b903 AG |
7850 | vmcs_load(shadow_vmcs); |
7851 | ||
7852 | for (i = 0; i < num_fields; i++) { | |
7853 | field = fields[i]; | |
7854 | switch (vmcs_field_type(field)) { | |
7855 | case VMCS_FIELD_TYPE_U16: | |
7856 | field_value = vmcs_read16(field); | |
7857 | break; | |
7858 | case VMCS_FIELD_TYPE_U32: | |
7859 | field_value = vmcs_read32(field); | |
7860 | break; | |
7861 | case VMCS_FIELD_TYPE_U64: | |
7862 | field_value = vmcs_read64(field); | |
7863 | break; | |
7864 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7865 | field_value = vmcs_readl(field); | |
7866 | break; | |
a2ae9df7 PB |
7867 | default: |
7868 | WARN_ON(1); | |
7869 | continue; | |
16f5b903 AG |
7870 | } |
7871 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7872 | } | |
7873 | ||
7874 | vmcs_clear(shadow_vmcs); | |
7875 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7876 | |
7877 | preempt_enable(); | |
16f5b903 AG |
7878 | } |
7879 | ||
c3114420 AG |
7880 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7881 | { | |
c2bae893 MK |
7882 | const unsigned long *fields[] = { |
7883 | shadow_read_write_fields, | |
7884 | shadow_read_only_fields | |
c3114420 | 7885 | }; |
c2bae893 | 7886 | const int max_fields[] = { |
c3114420 AG |
7887 | max_shadow_read_write_fields, |
7888 | max_shadow_read_only_fields | |
7889 | }; | |
7890 | int i, q; | |
7891 | unsigned long field; | |
7892 | u64 field_value = 0; | |
355f4fb1 | 7893 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7894 | |
7895 | vmcs_load(shadow_vmcs); | |
7896 | ||
c2bae893 | 7897 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7898 | for (i = 0; i < max_fields[q]; i++) { |
7899 | field = fields[q][i]; | |
7900 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7901 | ||
7902 | switch (vmcs_field_type(field)) { | |
7903 | case VMCS_FIELD_TYPE_U16: | |
7904 | vmcs_write16(field, (u16)field_value); | |
7905 | break; | |
7906 | case VMCS_FIELD_TYPE_U32: | |
7907 | vmcs_write32(field, (u32)field_value); | |
7908 | break; | |
7909 | case VMCS_FIELD_TYPE_U64: | |
7910 | vmcs_write64(field, (u64)field_value); | |
7911 | break; | |
7912 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7913 | vmcs_writel(field, (long)field_value); | |
7914 | break; | |
a2ae9df7 PB |
7915 | default: |
7916 | WARN_ON(1); | |
7917 | break; | |
c3114420 AG |
7918 | } |
7919 | } | |
7920 | } | |
7921 | ||
7922 | vmcs_clear(shadow_vmcs); | |
7923 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7924 | } | |
7925 | ||
49f705c5 NHE |
7926 | /* |
7927 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7928 | * used before) all generate the same failure when it is missing. | |
7929 | */ | |
7930 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7931 | { | |
7932 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7933 | if (vmx->nested.current_vmptr == -1ull) { | |
7934 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
7935 | return 0; |
7936 | } | |
7937 | return 1; | |
7938 | } | |
7939 | ||
7940 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7941 | { | |
7942 | unsigned long field; | |
7943 | u64 field_value; | |
7944 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7945 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7946 | gva_t gva = 0; | |
7947 | ||
eb277562 | 7948 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7949 | return 1; |
7950 | ||
6affcbed KH |
7951 | if (!nested_vmx_check_vmcs12(vcpu)) |
7952 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
7953 | |
7954 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7955 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7956 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7957 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 7958 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7959 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7960 | } |
7961 | /* | |
7962 | * Now copy part of this value to register or memory, as requested. | |
7963 | * Note that the number of bits actually copied is 32 or 64 depending | |
7964 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7965 | */ | |
7966 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7967 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7968 | field_value); |
7969 | } else { | |
7970 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7971 | vmx_instruction_info, true, &gva)) |
49f705c5 | 7972 | return 1; |
a325262f | 7973 | /* _system ok, nested_vmx_check_permission has verified cpl=0 */ |
40d2dba3 PB |
7974 | kvm_write_guest_virt_system(vcpu, gva, &field_value, |
7975 | (is_long_mode(vcpu) ? 8 : 4), NULL); | |
49f705c5 NHE |
7976 | } |
7977 | ||
7978 | nested_vmx_succeed(vcpu); | |
6affcbed | 7979 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7980 | } |
7981 | ||
7982 | ||
7983 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7984 | { | |
7985 | unsigned long field; | |
7986 | gva_t gva; | |
7987 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7988 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7989 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7990 | * mode, and eventually we need to write that into a field of several | |
7991 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7992 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7993 | * bits into the vmcs12 field. |
7994 | */ | |
7995 | u64 field_value = 0; | |
7996 | struct x86_exception e; | |
7997 | ||
eb277562 | 7998 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7999 | return 1; |
8000 | ||
6affcbed KH |
8001 | if (!nested_vmx_check_vmcs12(vcpu)) |
8002 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 8003 | |
49f705c5 | 8004 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 8005 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
8006 | (((vmx_instruction_info) >> 3) & 0xf)); |
8007 | else { | |
8008 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8009 | vmx_instruction_info, false, &gva)) |
49f705c5 | 8010 | return 1; |
40d2dba3 PB |
8011 | if (kvm_read_guest_virt(vcpu, gva, &field_value, |
8012 | (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { | |
49f705c5 NHE |
8013 | kvm_inject_page_fault(vcpu, &e); |
8014 | return 1; | |
8015 | } | |
8016 | } | |
8017 | ||
8018 | ||
27e6fb5d | 8019 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
8020 | if (vmcs_field_readonly(field)) { |
8021 | nested_vmx_failValid(vcpu, | |
8022 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 8023 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8024 | } |
8025 | ||
a2ae9df7 | 8026 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 8027 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 8028 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8029 | } |
8030 | ||
8031 | nested_vmx_succeed(vcpu); | |
6affcbed | 8032 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8033 | } |
8034 | ||
a8bc284e JM |
8035 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
8036 | { | |
8037 | vmx->nested.current_vmptr = vmptr; | |
8038 | if (enable_shadow_vmcs) { | |
8039 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
8040 | SECONDARY_EXEC_SHADOW_VMCS); | |
8041 | vmcs_write64(VMCS_LINK_POINTER, | |
8042 | __pa(vmx->vmcs01.shadow_vmcs)); | |
8043 | vmx->nested.sync_shadow_vmcs = true; | |
8044 | } | |
8045 | } | |
8046 | ||
63846663 NHE |
8047 | /* Emulate the VMPTRLD instruction */ |
8048 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
8049 | { | |
8050 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 8051 | gpa_t vmptr; |
63846663 NHE |
8052 | |
8053 | if (!nested_vmx_check_permission(vcpu)) | |
8054 | return 1; | |
8055 | ||
cbf71279 | 8056 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
63846663 | 8057 | return 1; |
63846663 | 8058 | |
cbf71279 RK |
8059 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
8060 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
8061 | return kvm_skip_emulated_instruction(vcpu); | |
8062 | } | |
8063 | ||
8064 | if (vmptr == vmx->nested.vmxon_ptr) { | |
8065 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); | |
8066 | return kvm_skip_emulated_instruction(vcpu); | |
8067 | } | |
8068 | ||
63846663 NHE |
8069 | if (vmx->nested.current_vmptr != vmptr) { |
8070 | struct vmcs12 *new_vmcs12; | |
8071 | struct page *page; | |
5e2f30b7 DH |
8072 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
8073 | if (is_error_page(page)) { | |
63846663 | 8074 | nested_vmx_failInvalid(vcpu); |
6affcbed | 8075 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
8076 | } |
8077 | new_vmcs12 = kmap(page); | |
8078 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
8079 | kunmap(page); | |
53a70daf | 8080 | kvm_release_page_clean(page); |
63846663 NHE |
8081 | nested_vmx_failValid(vcpu, |
8082 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 8083 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 8084 | } |
63846663 | 8085 | |
9a2a05b9 | 8086 | nested_release_vmcs12(vmx); |
4f2777bc DM |
8087 | /* |
8088 | * Load VMCS12 from guest memory since it is not already | |
8089 | * cached. | |
8090 | */ | |
9f744c59 PB |
8091 | memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); |
8092 | kunmap(page); | |
53a70daf | 8093 | kvm_release_page_clean(page); |
9f744c59 | 8094 | |
a8bc284e | 8095 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
8096 | } |
8097 | ||
8098 | nested_vmx_succeed(vcpu); | |
6affcbed | 8099 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
8100 | } |
8101 | ||
6a4d7550 NHE |
8102 | /* Emulate the VMPTRST instruction */ |
8103 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
8104 | { | |
8105 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8106 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8107 | gva_t vmcs_gva; | |
8108 | struct x86_exception e; | |
8109 | ||
8110 | if (!nested_vmx_check_permission(vcpu)) | |
8111 | return 1; | |
8112 | ||
8113 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8114 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 | 8115 | return 1; |
a325262f | 8116 | /* *_system ok, nested_vmx_check_permission has verified cpl=0 */ |
40d2dba3 PB |
8117 | if (kvm_write_guest_virt_system(vcpu, vmcs_gva, |
8118 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
8119 | sizeof(u64), &e)) { | |
6a4d7550 NHE |
8120 | kvm_inject_page_fault(vcpu, &e); |
8121 | return 1; | |
8122 | } | |
8123 | nested_vmx_succeed(vcpu); | |
6affcbed | 8124 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
8125 | } |
8126 | ||
bfd0a56b NHE |
8127 | /* Emulate the INVEPT instruction */ |
8128 | static int handle_invept(struct kvm_vcpu *vcpu) | |
8129 | { | |
b9c237bb | 8130 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
8131 | u32 vmx_instruction_info, types; |
8132 | unsigned long type; | |
8133 | gva_t gva; | |
8134 | struct x86_exception e; | |
8135 | struct { | |
8136 | u64 eptp, gpa; | |
8137 | } operand; | |
bfd0a56b | 8138 | |
b9c237bb WV |
8139 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
8140 | SECONDARY_EXEC_ENABLE_EPT) || | |
8141 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
8142 | kvm_queue_exception(vcpu, UD_VECTOR); |
8143 | return 1; | |
8144 | } | |
8145 | ||
8146 | if (!nested_vmx_check_permission(vcpu)) | |
8147 | return 1; | |
8148 | ||
bfd0a56b | 8149 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 8150 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 8151 | |
b9c237bb | 8152 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 8153 | |
85c856b3 | 8154 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
8155 | nested_vmx_failValid(vcpu, |
8156 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8157 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
8158 | } |
8159 | ||
8160 | /* According to the Intel VMX instruction reference, the memory | |
8161 | * operand is read even if it isn't needed (e.g., for type==global) | |
8162 | */ | |
8163 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 8164 | vmx_instruction_info, false, &gva)) |
bfd0a56b | 8165 | return 1; |
40d2dba3 | 8166 | if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { |
bfd0a56b NHE |
8167 | kvm_inject_page_fault(vcpu, &e); |
8168 | return 1; | |
8169 | } | |
8170 | ||
8171 | switch (type) { | |
bfd0a56b | 8172 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
8173 | /* |
8174 | * TODO: track mappings and invalidate | |
8175 | * single context requests appropriately | |
8176 | */ | |
8177 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 8178 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 8179 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
8180 | nested_vmx_succeed(vcpu); |
8181 | break; | |
8182 | default: | |
8183 | BUG_ON(1); | |
8184 | break; | |
8185 | } | |
8186 | ||
6affcbed | 8187 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
8188 | } |
8189 | ||
a642fc30 PM |
8190 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
8191 | { | |
99b83ac8 WL |
8192 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8193 | u32 vmx_instruction_info; | |
8194 | unsigned long type, types; | |
8195 | gva_t gva; | |
8196 | struct x86_exception e; | |
40352605 JM |
8197 | struct { |
8198 | u64 vpid; | |
8199 | u64 gla; | |
8200 | } operand; | |
99b83ac8 WL |
8201 | |
8202 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
8203 | SECONDARY_EXEC_ENABLE_VPID) || | |
8204 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
8205 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8206 | return 1; | |
8207 | } | |
8208 | ||
8209 | if (!nested_vmx_check_permission(vcpu)) | |
8210 | return 1; | |
8211 | ||
8212 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8213 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
8214 | ||
bcdde302 JD |
8215 | types = (vmx->nested.nested_vmx_vpid_caps & |
8216 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 8217 | |
85c856b3 | 8218 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
8219 | nested_vmx_failValid(vcpu, |
8220 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8221 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8222 | } |
8223 | ||
8224 | /* according to the intel vmx instruction reference, the memory | |
8225 | * operand is read even if it isn't needed (e.g., for type==global) | |
8226 | */ | |
8227 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
8228 | vmx_instruction_info, false, &gva)) | |
8229 | return 1; | |
40d2dba3 | 8230 | if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { |
99b83ac8 WL |
8231 | kvm_inject_page_fault(vcpu, &e); |
8232 | return 1; | |
8233 | } | |
40352605 JM |
8234 | if (operand.vpid >> 16) { |
8235 | nested_vmx_failValid(vcpu, | |
8236 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
8237 | return kvm_skip_emulated_instruction(vcpu); | |
8238 | } | |
99b83ac8 WL |
8239 | |
8240 | switch (type) { | |
bcdde302 | 8241 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
fd8cb433 | 8242 | if (is_noncanonical_address(operand.gla, vcpu)) { |
40352605 JM |
8243 | nested_vmx_failValid(vcpu, |
8244 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
8245 | return kvm_skip_emulated_instruction(vcpu); | |
8246 | } | |
8247 | /* fall through */ | |
ef697a71 | 8248 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 | 8249 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
40352605 | 8250 | if (!operand.vpid) { |
bcdde302 JD |
8251 | nested_vmx_failValid(vcpu, |
8252 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8253 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
8254 | } |
8255 | break; | |
99b83ac8 | 8256 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
8257 | break; |
8258 | default: | |
bcdde302 | 8259 | WARN_ON_ONCE(1); |
6affcbed | 8260 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8261 | } |
8262 | ||
bcdde302 JD |
8263 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02); |
8264 | nested_vmx_succeed(vcpu); | |
8265 | ||
6affcbed | 8266 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
8267 | } |
8268 | ||
843e4330 KH |
8269 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
8270 | { | |
8271 | unsigned long exit_qualification; | |
8272 | ||
8273 | trace_kvm_pml_full(vcpu->vcpu_id); | |
8274 | ||
8275 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8276 | ||
8277 | /* | |
8278 | * PML buffer FULL happened while executing iret from NMI, | |
8279 | * "blocked by NMI" bit has to be set before next VM entry. | |
8280 | */ | |
8281 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
d02fcf50 | 8282 | enable_vnmi && |
843e4330 KH |
8283 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
8284 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
8285 | GUEST_INTR_STATE_NMI); | |
8286 | ||
8287 | /* | |
8288 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
8289 | * here.., and there's no userspace involvement needed for PML. | |
8290 | */ | |
8291 | return 1; | |
8292 | } | |
8293 | ||
64672c95 YJ |
8294 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
8295 | { | |
8296 | kvm_lapic_expired_hv_timer(vcpu); | |
8297 | return 1; | |
8298 | } | |
8299 | ||
41ab9372 BD |
8300 | static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) |
8301 | { | |
8302 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
41ab9372 BD |
8303 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
8304 | ||
8305 | /* Check for memory type validity */ | |
bb97a016 DH |
8306 | switch (address & VMX_EPTP_MT_MASK) { |
8307 | case VMX_EPTP_MT_UC: | |
41ab9372 BD |
8308 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT)) |
8309 | return false; | |
8310 | break; | |
bb97a016 | 8311 | case VMX_EPTP_MT_WB: |
41ab9372 BD |
8312 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT)) |
8313 | return false; | |
8314 | break; | |
8315 | default: | |
8316 | return false; | |
8317 | } | |
8318 | ||
bb97a016 DH |
8319 | /* only 4 levels page-walk length are valid */ |
8320 | if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4) | |
41ab9372 BD |
8321 | return false; |
8322 | ||
8323 | /* Reserved bits should not be set */ | |
8324 | if (address >> maxphyaddr || ((address >> 7) & 0x1f)) | |
8325 | return false; | |
8326 | ||
8327 | /* AD, if set, should be supported */ | |
bb97a016 | 8328 | if (address & VMX_EPTP_AD_ENABLE_BIT) { |
41ab9372 BD |
8329 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT)) |
8330 | return false; | |
8331 | } | |
8332 | ||
8333 | return true; | |
8334 | } | |
8335 | ||
8336 | static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, | |
8337 | struct vmcs12 *vmcs12) | |
8338 | { | |
8339 | u32 index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8340 | u64 address; | |
8341 | bool accessed_dirty; | |
8342 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; | |
8343 | ||
8344 | if (!nested_cpu_has_eptp_switching(vmcs12) || | |
8345 | !nested_cpu_has_ept(vmcs12)) | |
8346 | return 1; | |
8347 | ||
8348 | if (index >= VMFUNC_EPTP_ENTRIES) | |
8349 | return 1; | |
8350 | ||
8351 | ||
8352 | if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, | |
8353 | &address, index * 8, 8)) | |
8354 | return 1; | |
8355 | ||
bb97a016 | 8356 | accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); |
41ab9372 BD |
8357 | |
8358 | /* | |
8359 | * If the (L2) guest does a vmfunc to the currently | |
8360 | * active ept pointer, we don't have to do anything else | |
8361 | */ | |
8362 | if (vmcs12->ept_pointer != address) { | |
8363 | if (!valid_ept_address(vcpu, address)) | |
8364 | return 1; | |
8365 | ||
8366 | kvm_mmu_unload(vcpu); | |
8367 | mmu->ept_ad = accessed_dirty; | |
8368 | mmu->base_role.ad_disabled = !accessed_dirty; | |
8369 | vmcs12->ept_pointer = address; | |
8370 | /* | |
8371 | * TODO: Check what's the correct approach in case | |
8372 | * mmu reload fails. Currently, we just let the next | |
8373 | * reload potentially fail | |
8374 | */ | |
8375 | kvm_mmu_reload(vcpu); | |
8376 | } | |
8377 | ||
8378 | return 0; | |
8379 | } | |
8380 | ||
2a499e49 BD |
8381 | static int handle_vmfunc(struct kvm_vcpu *vcpu) |
8382 | { | |
27c42a1b BD |
8383 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8384 | struct vmcs12 *vmcs12; | |
8385 | u32 function = vcpu->arch.regs[VCPU_REGS_RAX]; | |
8386 | ||
8387 | /* | |
8388 | * VMFUNC is only supported for nested guests, but we always enable the | |
8389 | * secondary control for simplicity; for non-nested mode, fake that we | |
8390 | * didn't by injecting #UD. | |
8391 | */ | |
8392 | if (!is_guest_mode(vcpu)) { | |
8393 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8394 | return 1; | |
8395 | } | |
8396 | ||
8397 | vmcs12 = get_vmcs12(vcpu); | |
8398 | if ((vmcs12->vm_function_control & (1 << function)) == 0) | |
8399 | goto fail; | |
41ab9372 BD |
8400 | |
8401 | switch (function) { | |
8402 | case 0: | |
8403 | if (nested_vmx_eptp_switching(vcpu, vmcs12)) | |
8404 | goto fail; | |
8405 | break; | |
8406 | default: | |
8407 | goto fail; | |
8408 | } | |
8409 | return kvm_skip_emulated_instruction(vcpu); | |
27c42a1b BD |
8410 | |
8411 | fail: | |
8412 | nested_vmx_vmexit(vcpu, vmx->exit_reason, | |
8413 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8414 | vmcs_readl(EXIT_QUALIFICATION)); | |
2a499e49 BD |
8415 | return 1; |
8416 | } | |
8417 | ||
6aa8b732 AK |
8418 | /* |
8419 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
8420 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
8421 | * to be done to userspace and return 0. | |
8422 | */ | |
772e0318 | 8423 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
8424 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
8425 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 8426 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 8427 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 8428 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
8429 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
8430 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
8431 | [EXIT_REASON_CPUID] = handle_cpuid, | |
8432 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
8433 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
8434 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
8435 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 8436 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 8437 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 8438 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 8439 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 8440 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 8441 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 8442 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 8443 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 8444 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 8445 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 8446 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
8447 | [EXIT_REASON_VMOFF] = handle_vmoff, |
8448 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
8449 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
8450 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 8451 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 8452 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 8453 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 8454 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 8455 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 8456 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
8457 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
8458 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 8459 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 8460 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 8461 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 8462 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 8463 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 8464 | [EXIT_REASON_INVVPID] = handle_invvpid, |
45ec368c | 8465 | [EXIT_REASON_RDRAND] = handle_invalid_op, |
75f4fc8d | 8466 | [EXIT_REASON_RDSEED] = handle_invalid_op, |
f53cd63c WL |
8467 | [EXIT_REASON_XSAVES] = handle_xsaves, |
8468 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 8469 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
2a499e49 | 8470 | [EXIT_REASON_VMFUNC] = handle_vmfunc, |
64672c95 | 8471 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
8472 | }; |
8473 | ||
8474 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 8475 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 8476 | |
908a7bdd JK |
8477 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
8478 | struct vmcs12 *vmcs12) | |
8479 | { | |
8480 | unsigned long exit_qualification; | |
8481 | gpa_t bitmap, last_bitmap; | |
8482 | unsigned int port; | |
8483 | int size; | |
8484 | u8 b; | |
8485 | ||
908a7bdd | 8486 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 8487 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
8488 | |
8489 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8490 | ||
8491 | port = exit_qualification >> 16; | |
8492 | size = (exit_qualification & 7) + 1; | |
8493 | ||
8494 | last_bitmap = (gpa_t)-1; | |
8495 | b = -1; | |
8496 | ||
8497 | while (size > 0) { | |
8498 | if (port < 0x8000) | |
8499 | bitmap = vmcs12->io_bitmap_a; | |
8500 | else if (port < 0x10000) | |
8501 | bitmap = vmcs12->io_bitmap_b; | |
8502 | else | |
1d804d07 | 8503 | return true; |
908a7bdd JK |
8504 | bitmap += (port & 0x7fff) / 8; |
8505 | ||
8506 | if (last_bitmap != bitmap) | |
54bf36aa | 8507 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8508 | return true; |
908a7bdd | 8509 | if (b & (1 << (port & 7))) |
1d804d07 | 8510 | return true; |
908a7bdd JK |
8511 | |
8512 | port++; | |
8513 | size--; | |
8514 | last_bitmap = bitmap; | |
8515 | } | |
8516 | ||
1d804d07 | 8517 | return false; |
908a7bdd JK |
8518 | } |
8519 | ||
644d711a NHE |
8520 | /* |
8521 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8522 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8523 | * disinterest in the current event (read or write a specific MSR) by using an | |
8524 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8525 | */ | |
8526 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8527 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8528 | { | |
8529 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8530 | gpa_t bitmap; | |
8531 | ||
cbd29cb6 | 8532 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8533 | return true; |
644d711a NHE |
8534 | |
8535 | /* | |
8536 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8537 | * for the four combinations of read/write and low/high MSR numbers. | |
8538 | * First we need to figure out which of the four to use: | |
8539 | */ | |
8540 | bitmap = vmcs12->msr_bitmap; | |
8541 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8542 | bitmap += 2048; | |
8543 | if (msr_index >= 0xc0000000) { | |
8544 | msr_index -= 0xc0000000; | |
8545 | bitmap += 1024; | |
8546 | } | |
8547 | ||
8548 | /* Then read the msr_index'th bit from this bitmap: */ | |
8549 | if (msr_index < 1024*8) { | |
8550 | unsigned char b; | |
54bf36aa | 8551 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8552 | return true; |
644d711a NHE |
8553 | return 1 & (b >> (msr_index & 7)); |
8554 | } else | |
1d804d07 | 8555 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8556 | } |
8557 | ||
8558 | /* | |
8559 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8560 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8561 | * intercept (via guest_host_mask etc.) the current event. | |
8562 | */ | |
8563 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8564 | struct vmcs12 *vmcs12) | |
8565 | { | |
8566 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8567 | int cr = exit_qualification & 15; | |
e1d39b17 JS |
8568 | int reg; |
8569 | unsigned long val; | |
644d711a NHE |
8570 | |
8571 | switch ((exit_qualification >> 4) & 3) { | |
8572 | case 0: /* mov to cr */ | |
e1d39b17 JS |
8573 | reg = (exit_qualification >> 8) & 15; |
8574 | val = kvm_register_readl(vcpu, reg); | |
644d711a NHE |
8575 | switch (cr) { |
8576 | case 0: | |
8577 | if (vmcs12->cr0_guest_host_mask & | |
8578 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8579 | return true; |
644d711a NHE |
8580 | break; |
8581 | case 3: | |
8582 | if ((vmcs12->cr3_target_count >= 1 && | |
8583 | vmcs12->cr3_target_value0 == val) || | |
8584 | (vmcs12->cr3_target_count >= 2 && | |
8585 | vmcs12->cr3_target_value1 == val) || | |
8586 | (vmcs12->cr3_target_count >= 3 && | |
8587 | vmcs12->cr3_target_value2 == val) || | |
8588 | (vmcs12->cr3_target_count >= 4 && | |
8589 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8590 | return false; |
644d711a | 8591 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8592 | return true; |
644d711a NHE |
8593 | break; |
8594 | case 4: | |
8595 | if (vmcs12->cr4_guest_host_mask & | |
8596 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8597 | return true; |
644d711a NHE |
8598 | break; |
8599 | case 8: | |
8600 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8601 | return true; |
644d711a NHE |
8602 | break; |
8603 | } | |
8604 | break; | |
8605 | case 2: /* clts */ | |
8606 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8607 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8608 | return true; |
644d711a NHE |
8609 | break; |
8610 | case 1: /* mov from cr */ | |
8611 | switch (cr) { | |
8612 | case 3: | |
8613 | if (vmcs12->cpu_based_vm_exec_control & | |
8614 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8615 | return true; |
644d711a NHE |
8616 | break; |
8617 | case 8: | |
8618 | if (vmcs12->cpu_based_vm_exec_control & | |
8619 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8620 | return true; |
644d711a NHE |
8621 | break; |
8622 | } | |
8623 | break; | |
8624 | case 3: /* lmsw */ | |
8625 | /* | |
8626 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8627 | * cr0. Other attempted changes are ignored, with no exit. | |
8628 | */ | |
e1d39b17 | 8629 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
644d711a NHE |
8630 | if (vmcs12->cr0_guest_host_mask & 0xe & |
8631 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8632 | return true; |
644d711a NHE |
8633 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8634 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8635 | (val & 0x1)) | |
1d804d07 | 8636 | return true; |
644d711a NHE |
8637 | break; |
8638 | } | |
1d804d07 | 8639 | return false; |
644d711a NHE |
8640 | } |
8641 | ||
8642 | /* | |
8643 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8644 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8645 | * when in is_guest_mode (L2). | |
8646 | */ | |
7313c698 | 8647 | static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) |
644d711a | 8648 | { |
644d711a NHE |
8649 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8650 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8651 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8652 | ||
4f350c6d JM |
8653 | if (vmx->nested.nested_run_pending) |
8654 | return false; | |
8655 | ||
8656 | if (unlikely(vmx->fail)) { | |
8657 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, | |
8658 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
8659 | return true; | |
8660 | } | |
542060ea | 8661 | |
c9f04407 DM |
8662 | /* |
8663 | * The host physical addresses of some pages of guest memory | |
8819227c JM |
8664 | * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC |
8665 | * Page). The CPU may write to these pages via their host | |
8666 | * physical address while L2 is running, bypassing any | |
8667 | * address-translation-based dirty tracking (e.g. EPT write | |
8668 | * protection). | |
c9f04407 DM |
8669 | * |
8670 | * Mark them dirty on every exit from L2 to prevent them from | |
8671 | * getting out of sync with dirty tracking. | |
8672 | */ | |
8673 | nested_mark_vmcs12_pages_dirty(vcpu); | |
8674 | ||
4f350c6d JM |
8675 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8676 | vmcs_readl(EXIT_QUALIFICATION), | |
8677 | vmx->idt_vectoring_info, | |
8678 | intr_info, | |
8679 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8680 | KVM_ISA_VMX); | |
644d711a NHE |
8681 | |
8682 | switch (exit_reason) { | |
8683 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8684 | if (is_nmi(intr_info)) |
1d804d07 | 8685 | return false; |
644d711a | 8686 | else if (is_page_fault(intr_info)) |
52a5c155 | 8687 | return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; |
e504c909 | 8688 | else if (is_no_device(intr_info) && |
ccf9844e | 8689 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8690 | return false; |
6f05485d JK |
8691 | else if (is_debug(intr_info) && |
8692 | vcpu->guest_debug & | |
8693 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8694 | return false; | |
8695 | else if (is_breakpoint(intr_info) && | |
8696 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8697 | return false; | |
644d711a NHE |
8698 | return vmcs12->exception_bitmap & |
8699 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8700 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8701 | return false; |
644d711a | 8702 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8703 | return true; |
644d711a | 8704 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8705 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8706 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8707 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8708 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8709 | return true; |
644d711a | 8710 | case EXIT_REASON_CPUID: |
1d804d07 | 8711 | return true; |
644d711a NHE |
8712 | case EXIT_REASON_HLT: |
8713 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8714 | case EXIT_REASON_INVD: | |
1d804d07 | 8715 | return true; |
644d711a NHE |
8716 | case EXIT_REASON_INVLPG: |
8717 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8718 | case EXIT_REASON_RDPMC: | |
8719 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 | 8720 | case EXIT_REASON_RDRAND: |
736fdf72 | 8721 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); |
a5f46457 | 8722 | case EXIT_REASON_RDSEED: |
736fdf72 | 8723 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); |
b3a2a907 | 8724 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8725 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8726 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8727 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8728 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8729 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8730 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8731 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8732 | /* |
8733 | * VMX instructions trap unconditionally. This allows L1 to | |
8734 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8735 | */ | |
1d804d07 | 8736 | return true; |
644d711a NHE |
8737 | case EXIT_REASON_CR_ACCESS: |
8738 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8739 | case EXIT_REASON_DR_ACCESS: | |
8740 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8741 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8742 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8743 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8744 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8745 | case EXIT_REASON_MSR_READ: |
8746 | case EXIT_REASON_MSR_WRITE: | |
8747 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8748 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8749 | return true; |
644d711a NHE |
8750 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8751 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8752 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8753 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8754 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8755 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8756 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8757 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8758 | nested_cpu_has2(vmcs12, | |
8759 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8760 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8761 | return false; |
644d711a | 8762 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8763 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8764 | case EXIT_REASON_APIC_ACCESS: |
8765 | return nested_cpu_has2(vmcs12, | |
8766 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8767 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8768 | case EXIT_REASON_EOI_INDUCED: |
8769 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8770 | return true; |
644d711a | 8771 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8772 | /* |
8773 | * L0 always deals with the EPT violation. If nested EPT is | |
8774 | * used, and the nested mmu code discovers that the address is | |
8775 | * missing in the guest EPT table (EPT12), the EPT violation | |
8776 | * will be injected with nested_ept_inject_page_fault() | |
8777 | */ | |
1d804d07 | 8778 | return false; |
644d711a | 8779 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8780 | /* |
8781 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8782 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8783 | * (EPT on EPT). So any problems with the structure of the | |
8784 | * table is L0's fault. | |
8785 | */ | |
1d804d07 | 8786 | return false; |
90a2db6d PB |
8787 | case EXIT_REASON_INVPCID: |
8788 | return | |
8789 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && | |
8790 | nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
644d711a NHE |
8791 | case EXIT_REASON_WBINVD: |
8792 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8793 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8794 | return true; |
81dc01f7 WL |
8795 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8796 | /* | |
8797 | * This should never happen, since it is not possible to | |
8798 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8799 | * If if it were, XSS would have to be checked against | |
8800 | * the XSS exit bitmap in vmcs12. | |
8801 | */ | |
8802 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8803 | case EXIT_REASON_PREEMPTION_TIMER: |
8804 | return false; | |
ab007cc9 | 8805 | case EXIT_REASON_PML_FULL: |
03efce6f | 8806 | /* We emulate PML support to L1. */ |
ab007cc9 | 8807 | return false; |
2a499e49 BD |
8808 | case EXIT_REASON_VMFUNC: |
8809 | /* VM functions are emulated through L2->L0 vmexits. */ | |
8810 | return false; | |
644d711a | 8811 | default: |
1d804d07 | 8812 | return true; |
644d711a NHE |
8813 | } |
8814 | } | |
8815 | ||
7313c698 PB |
8816 | static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason) |
8817 | { | |
8818 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8819 | ||
8820 | /* | |
8821 | * At this point, the exit interruption info in exit_intr_info | |
8822 | * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT | |
8823 | * we need to query the in-kernel LAPIC. | |
8824 | */ | |
8825 | WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT); | |
8826 | if ((exit_intr_info & | |
8827 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
8828 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) { | |
8829 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8830 | vmcs12->vm_exit_intr_error_code = | |
8831 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
8832 | } | |
8833 | ||
8834 | nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, | |
8835 | vmcs_readl(EXIT_QUALIFICATION)); | |
8836 | return 1; | |
8837 | } | |
8838 | ||
586f9607 AK |
8839 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8840 | { | |
8841 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8842 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8843 | } | |
8844 | ||
a3eaa864 | 8845 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8846 | { |
a3eaa864 KH |
8847 | if (vmx->pml_pg) { |
8848 | __free_page(vmx->pml_pg); | |
8849 | vmx->pml_pg = NULL; | |
8850 | } | |
843e4330 KH |
8851 | } |
8852 | ||
54bf36aa | 8853 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8854 | { |
54bf36aa | 8855 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8856 | u64 *pml_buf; |
8857 | u16 pml_idx; | |
8858 | ||
8859 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8860 | ||
8861 | /* Do nothing if PML buffer is empty */ | |
8862 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8863 | return; | |
8864 | ||
8865 | /* PML index always points to next available PML buffer entity */ | |
8866 | if (pml_idx >= PML_ENTITY_NUM) | |
8867 | pml_idx = 0; | |
8868 | else | |
8869 | pml_idx++; | |
8870 | ||
8871 | pml_buf = page_address(vmx->pml_pg); | |
8872 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8873 | u64 gpa; | |
8874 | ||
8875 | gpa = pml_buf[pml_idx]; | |
8876 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8877 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8878 | } |
8879 | ||
8880 | /* reset PML index */ | |
8881 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8882 | } | |
8883 | ||
8884 | /* | |
8885 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8886 | * Called before reporting dirty_bitmap to userspace. | |
8887 | */ | |
8888 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8889 | { | |
8890 | int i; | |
8891 | struct kvm_vcpu *vcpu; | |
8892 | /* | |
8893 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8894 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8895 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8896 | * buffer. | |
8897 | */ | |
8898 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8899 | kvm_vcpu_kick(vcpu); | |
8900 | } | |
8901 | ||
4eb64dce PB |
8902 | static void vmx_dump_sel(char *name, uint32_t sel) |
8903 | { | |
8904 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8905 | name, vmcs_read16(sel), |
4eb64dce PB |
8906 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8907 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8908 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8909 | } | |
8910 | ||
8911 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8912 | { | |
8913 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8914 | name, vmcs_read32(limit), | |
8915 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8916 | } | |
8917 | ||
8918 | static void dump_vmcs(void) | |
8919 | { | |
8920 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8921 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8922 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8923 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8924 | u32 secondary_exec_control = 0; | |
8925 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8926 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8927 | int i, n; |
8928 | ||
8929 | if (cpu_has_secondary_exec_ctrls()) | |
8930 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8931 | ||
8932 | pr_err("*** Guest State ***\n"); | |
8933 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8934 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8935 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8936 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8937 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8938 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8939 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8940 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8941 | { | |
845c5b40 PB |
8942 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8943 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8944 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8945 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8946 | } |
8947 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8948 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8949 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8950 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8951 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8952 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8953 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8954 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8955 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8956 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8957 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8958 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8959 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8960 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8961 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8962 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8963 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8964 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8965 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8966 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8967 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8968 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8969 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8970 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8971 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8972 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8973 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8974 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8975 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8976 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8977 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8978 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8979 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8980 | pr_err("InterruptStatus = %04x\n", | |
8981 | vmcs_read16(GUEST_INTR_STATUS)); | |
8982 | ||
8983 | pr_err("*** Host State ***\n"); | |
8984 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8985 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8986 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8987 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8988 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8989 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8990 | vmcs_read16(HOST_TR_SELECTOR)); | |
8991 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8992 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8993 | vmcs_readl(HOST_TR_BASE)); | |
8994 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8995 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8996 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8997 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8998 | vmcs_readl(HOST_CR4)); | |
8999 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
9000 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
9001 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
9002 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
9003 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
9004 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
9005 | vmcs_read64(HOST_IA32_EFER), | |
9006 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 9007 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
9008 | pr_err("PerfGlobCtl = 0x%016llx\n", |
9009 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
9010 | |
9011 | pr_err("*** Control State ***\n"); | |
9012 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
9013 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
9014 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
9015 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
9016 | vmcs_read32(EXCEPTION_BITMAP), | |
9017 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
9018 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
9019 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
9020 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
9021 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
9022 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
9023 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
9024 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9025 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
9026 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
9027 | pr_err(" reason=%08x qualification=%016lx\n", | |
9028 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
9029 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
9030 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
9031 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 9032 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 9033 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
9034 | pr_err("TSC Multiplier = 0x%016llx\n", |
9035 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
9036 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
9037 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
9038 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
9039 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
9040 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 9041 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
9042 | n = vmcs_read32(CR3_TARGET_COUNT); |
9043 | for (i = 0; i + 1 < n; i += 4) | |
9044 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
9045 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
9046 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
9047 | if (i < n) | |
9048 | pr_err("CR3 target%u=%016lx\n", | |
9049 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
9050 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
9051 | pr_err("PLE Gap=%08x Window=%08x\n", | |
9052 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
9053 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
9054 | pr_err("Virtual processor ID = 0x%04x\n", | |
9055 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
9056 | } | |
9057 | ||
6aa8b732 AK |
9058 | /* |
9059 | * The guest has exited. See if we can fix it or if we need userspace | |
9060 | * assistance. | |
9061 | */ | |
851ba692 | 9062 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 9063 | { |
29bd8a78 | 9064 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 9065 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 9066 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 9067 | |
8b89fe1f PB |
9068 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
9069 | ||
843e4330 KH |
9070 | /* |
9071 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
9072 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
9073 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
9074 | * mode as if vcpus is in root mode, the PML buffer must has been | |
9075 | * flushed already. | |
9076 | */ | |
9077 | if (enable_pml) | |
54bf36aa | 9078 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 9079 | |
80ced186 | 9080 | /* If guest state is invalid, start emulating */ |
14168786 | 9081 | if (vmx->emulation_required) |
80ced186 | 9082 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 9083 | |
7313c698 PB |
9084 | if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) |
9085 | return nested_vmx_reflect_vmexit(vcpu, exit_reason); | |
644d711a | 9086 | |
5120702e | 9087 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 9088 | dump_vmcs(); |
5120702e MG |
9089 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
9090 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
9091 | = exit_reason; | |
9092 | return 0; | |
9093 | } | |
9094 | ||
29bd8a78 | 9095 | if (unlikely(vmx->fail)) { |
851ba692 AK |
9096 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
9097 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
9098 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
9099 | return 0; | |
9100 | } | |
6aa8b732 | 9101 | |
b9bf6882 XG |
9102 | /* |
9103 | * Note: | |
9104 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
9105 | * delivery event since it indicates guest is accessing MMIO. | |
9106 | * The vm-exit can be triggered again after return to guest that | |
9107 | * will cause infinite loop. | |
9108 | */ | |
d77c26fc | 9109 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 9110 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 9111 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 9112 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
9113 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
9114 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9115 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
70bcd708 | 9116 | vcpu->run->internal.ndata = 3; |
b9bf6882 XG |
9117 | vcpu->run->internal.data[0] = vectoring_info; |
9118 | vcpu->run->internal.data[1] = exit_reason; | |
70bcd708 PB |
9119 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
9120 | if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { | |
9121 | vcpu->run->internal.ndata++; | |
9122 | vcpu->run->internal.data[3] = | |
9123 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
9124 | } | |
b9bf6882 XG |
9125 | return 0; |
9126 | } | |
3b86cd99 | 9127 | |
d02fcf50 | 9128 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9129 | vmx->loaded_vmcs->soft_vnmi_blocked)) { |
9130 | if (vmx_interrupt_allowed(vcpu)) { | |
9131 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
9132 | } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && | |
9133 | vcpu->arch.nmi_pending) { | |
9134 | /* | |
9135 | * This CPU don't support us in finding the end of an | |
9136 | * NMI-blocked window if the guest runs with IRQs | |
9137 | * disabled. So we pull the trigger after 1 s of | |
9138 | * futile waiting, but inform the user about this. | |
9139 | */ | |
9140 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
9141 | "state on VCPU %d after 1 s timeout\n", | |
9142 | __func__, vcpu->vcpu_id); | |
9143 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
9144 | } | |
9145 | } | |
9146 | ||
6aa8b732 AK |
9147 | if (exit_reason < kvm_vmx_max_exit_handlers |
9148 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 9149 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 9150 | else { |
6c6c5e03 RK |
9151 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
9152 | exit_reason); | |
2bc19dc3 MT |
9153 | kvm_queue_exception(vcpu, UD_VECTOR); |
9154 | return 1; | |
6aa8b732 | 9155 | } |
6aa8b732 AK |
9156 | } |
9157 | ||
d665f9fc PB |
9158 | /* |
9159 | * Software based L1D cache flush which is used when microcode providing | |
9160 | * the cache control MSR is not loaded. | |
9161 | * | |
9162 | * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to | |
9163 | * flush it is required to read in 64 KiB because the replacement algorithm | |
9164 | * is not exactly LRU. This could be sized at runtime via topology | |
9165 | * information but as all relevant affected CPUs have 32KiB L1D cache size | |
9166 | * there is no point in doing so. | |
9167 | */ | |
9168 | #define L1D_CACHE_ORDER 4 | |
9169 | static void *vmx_l1d_flush_pages; | |
9170 | ||
f0ace387 | 9171 | static void vmx_l1d_flush(struct kvm_vcpu *vcpu) |
d665f9fc PB |
9172 | { |
9173 | int size = PAGE_SIZE << L1D_CACHE_ORDER; | |
f0ace387 PB |
9174 | |
9175 | /* | |
1384247a TG |
9176 | * This code is only executed when the the flush mode is 'cond' or |
9177 | * 'always' | |
f0ace387 | 9178 | */ |
12960b11 | 9179 | if (static_branch_likely(&vmx_l1d_flush_cond)) { |
64947f95 | 9180 | bool flush_l1d; |
bcbe4077 | 9181 | |
07edf60a | 9182 | /* |
64947f95 NS |
9183 | * Clear the per-vcpu flush bit, it gets set again |
9184 | * either from vcpu_run() or from one of the unsafe | |
9185 | * VMEXIT handlers. | |
07edf60a | 9186 | */ |
64947f95 | 9187 | flush_l1d = vcpu->arch.l1tf_flush_l1d; |
ae021965 | 9188 | vcpu->arch.l1tf_flush_l1d = false; |
64947f95 NS |
9189 | |
9190 | /* | |
9191 | * Clear the per-cpu flush bit, it gets set again from | |
9192 | * the interrupt handlers. | |
9193 | */ | |
9194 | flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); | |
9195 | kvm_clear_cpu_l1tf_flush_l1d(); | |
9196 | ||
bcbe4077 NS |
9197 | if (!flush_l1d) |
9198 | return; | |
07edf60a | 9199 | } |
f0ace387 PB |
9200 | |
9201 | vcpu->stat.l1d_flush++; | |
d665f9fc | 9202 | |
8e494dea PB |
9203 | if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { |
9204 | wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); | |
9205 | return; | |
9206 | } | |
9207 | ||
d665f9fc PB |
9208 | asm volatile( |
9209 | /* First ensure the pages are in the TLB */ | |
9210 | "xorl %%eax, %%eax\n" | |
9211 | ".Lpopulate_tlb:\n\t" | |
55bd6950 | 9212 | "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" |
d665f9fc PB |
9213 | "addl $4096, %%eax\n\t" |
9214 | "cmpl %%eax, %[size]\n\t" | |
9215 | "jne .Lpopulate_tlb\n\t" | |
9216 | "xorl %%eax, %%eax\n\t" | |
9217 | "cpuid\n\t" | |
9218 | /* Now fill the cache */ | |
9219 | "xorl %%eax, %%eax\n" | |
9220 | ".Lfill_cache:\n" | |
55bd6950 | 9221 | "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" |
d665f9fc PB |
9222 | "addl $64, %%eax\n\t" |
9223 | "cmpl %%eax, %[size]\n\t" | |
9224 | "jne .Lfill_cache\n\t" | |
9225 | "lfence\n" | |
55bd6950 | 9226 | :: [flush_pages] "r" (vmx_l1d_flush_pages), |
d665f9fc PB |
9227 | [size] "r" (size) |
9228 | : "eax", "ebx", "ecx", "edx"); | |
9229 | } | |
9230 | ||
95ba8273 | 9231 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 9232 | { |
a7c0b07d WL |
9233 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9234 | ||
9235 | if (is_guest_mode(vcpu) && | |
9236 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9237 | return; | |
9238 | ||
95ba8273 | 9239 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
9240 | vmcs_write32(TPR_THRESHOLD, 0); |
9241 | return; | |
9242 | } | |
9243 | ||
95ba8273 | 9244 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
9245 | } |
9246 | ||
8d14695f YZ |
9247 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
9248 | { | |
9249 | u32 sec_exec_control; | |
9250 | ||
dccbfcf5 RK |
9251 | /* Postpone execution until vmcs01 is the current VMCS. */ |
9252 | if (is_guest_mode(vcpu)) { | |
9253 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
9254 | return; | |
9255 | } | |
9256 | ||
f6e90f9e | 9257 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
9258 | return; |
9259 | ||
35754c98 | 9260 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
9261 | return; |
9262 | ||
9263 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9264 | ||
9265 | if (set) { | |
9266 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9267 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
9268 | } else { | |
9269 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
9270 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
5ad2874a | 9271 | vmx_flush_tlb(vcpu); |
8d14695f YZ |
9272 | } |
9273 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
9274 | ||
4b0be90f | 9275 | vmx_update_msr_bitmap(vcpu); |
8d14695f YZ |
9276 | } |
9277 | ||
38b99173 TC |
9278 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
9279 | { | |
9280 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9281 | ||
9282 | /* | |
9283 | * Currently we do not handle the nested case where L2 has an | |
9284 | * APIC access page of its own; that page is still pinned. | |
9285 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
9286 | * L1 prepared an APIC access page for L2. | |
9287 | * | |
9288 | * For the case where L1 and L2 share the same APIC access page | |
9289 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
9290 | * in the vmcs12), this function will only update either the vmcs01 | |
9291 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
9292 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
9293 | * the next L2->L1 exit. | |
9294 | */ | |
9295 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 9296 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 9297 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 9298 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
5ad2874a | 9299 | vmx_flush_tlb(vcpu); |
fb6c8198 | 9300 | } |
38b99173 TC |
9301 | } |
9302 | ||
67c9dddc | 9303 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
9304 | { |
9305 | u16 status; | |
9306 | u8 old; | |
9307 | ||
67c9dddc PB |
9308 | if (max_isr == -1) |
9309 | max_isr = 0; | |
c7c9c56c YZ |
9310 | |
9311 | status = vmcs_read16(GUEST_INTR_STATUS); | |
9312 | old = status >> 8; | |
67c9dddc | 9313 | if (max_isr != old) { |
c7c9c56c | 9314 | status &= 0xff; |
67c9dddc | 9315 | status |= max_isr << 8; |
c7c9c56c YZ |
9316 | vmcs_write16(GUEST_INTR_STATUS, status); |
9317 | } | |
9318 | } | |
9319 | ||
9320 | static void vmx_set_rvi(int vector) | |
9321 | { | |
9322 | u16 status; | |
9323 | u8 old; | |
9324 | ||
4114c27d WW |
9325 | if (vector == -1) |
9326 | vector = 0; | |
9327 | ||
c7c9c56c YZ |
9328 | status = vmcs_read16(GUEST_INTR_STATUS); |
9329 | old = (u8)status & 0xff; | |
9330 | if ((u8)vector != old) { | |
9331 | status &= ~0xff; | |
9332 | status |= (u8)vector; | |
9333 | vmcs_write16(GUEST_INTR_STATUS, status); | |
9334 | } | |
9335 | } | |
9336 | ||
9337 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
9338 | { | |
4114c27d WW |
9339 | if (!is_guest_mode(vcpu)) { |
9340 | vmx_set_rvi(max_irr); | |
9341 | return; | |
9342 | } | |
9343 | ||
c7c9c56c YZ |
9344 | if (max_irr == -1) |
9345 | return; | |
9346 | ||
963fee16 | 9347 | /* |
4114c27d WW |
9348 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
9349 | * handles it. | |
963fee16 | 9350 | */ |
4114c27d | 9351 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
9352 | return; |
9353 | ||
963fee16 | 9354 | /* |
4114c27d | 9355 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
9356 | * is run without virtual interrupt delivery. |
9357 | */ | |
9358 | if (!kvm_event_needs_reinjection(vcpu) && | |
9359 | vmx_interrupt_allowed(vcpu)) { | |
9360 | kvm_queue_interrupt(vcpu, max_irr, false); | |
9361 | vmx_inject_irq(vcpu); | |
9362 | } | |
c7c9c56c YZ |
9363 | } |
9364 | ||
76dfafd5 | 9365 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
9366 | { |
9367 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 9368 | int max_irr; |
810e6def | 9369 | |
76dfafd5 PB |
9370 | WARN_ON(!vcpu->arch.apicv_active); |
9371 | if (pi_test_on(&vmx->pi_desc)) { | |
9372 | pi_clear_on(&vmx->pi_desc); | |
9373 | /* | |
9374 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
9375 | * But on x86 this is just a compiler barrier anyway. | |
9376 | */ | |
9377 | smp_mb__after_atomic(); | |
9378 | max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
9379 | } else { | |
9380 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9381 | } | |
9382 | vmx_hwapic_irr_update(vcpu, max_irr); | |
9383 | return max_irr; | |
810e6def PB |
9384 | } |
9385 | ||
6308630b | 9386 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 9387 | { |
d62caabb | 9388 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
9389 | return; |
9390 | ||
c7c9c56c YZ |
9391 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
9392 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
9393 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
9394 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
9395 | } | |
9396 | ||
967235d3 PB |
9397 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
9398 | { | |
9399 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9400 | ||
9401 | pi_clear_on(&vmx->pi_desc); | |
9402 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
9403 | } | |
9404 | ||
51aa01d1 | 9405 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 9406 | { |
48ae0fb4 JM |
9407 | u32 exit_intr_info = 0; |
9408 | u16 basic_exit_reason = (u16)vmx->exit_reason; | |
00eba012 | 9409 | |
48ae0fb4 JM |
9410 | if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY |
9411 | || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
00eba012 AK |
9412 | return; |
9413 | ||
48ae0fb4 JM |
9414 | if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) |
9415 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9416 | vmx->exit_intr_info = exit_intr_info; | |
a0861c02 | 9417 | |
1261bfa3 WL |
9418 | /* if exit due to PF check for async PF */ |
9419 | if (is_page_fault(exit_intr_info)) | |
9420 | vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); | |
9421 | ||
a0861c02 | 9422 | /* Handle machine checks before interrupts are enabled */ |
48ae0fb4 JM |
9423 | if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY || |
9424 | is_machine_check(exit_intr_info)) | |
a0861c02 AK |
9425 | kvm_machine_check(); |
9426 | ||
20f65983 | 9427 | /* We need to handle NMIs before interrupts are enabled */ |
ef85b673 | 9428 | if (is_nmi(exit_intr_info)) { |
ff9d07a0 | 9429 | kvm_before_handle_nmi(&vmx->vcpu); |
20f65983 | 9430 | asm("int $2"); |
ff9d07a0 ZY |
9431 | kvm_after_handle_nmi(&vmx->vcpu); |
9432 | } | |
51aa01d1 | 9433 | } |
20f65983 | 9434 | |
a547c6db YZ |
9435 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
9436 | { | |
9437 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9438 | ||
a547c6db YZ |
9439 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
9440 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
9441 | unsigned int vector; | |
9442 | unsigned long entry; | |
9443 | gate_desc *desc; | |
9444 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9445 | #ifdef CONFIG_X86_64 | |
9446 | unsigned long tmp; | |
9447 | #endif | |
9448 | ||
9449 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9450 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
64b163fa | 9451 | entry = gate_offset(desc); |
a547c6db YZ |
9452 | asm volatile( |
9453 | #ifdef CONFIG_X86_64 | |
9454 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
9455 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
9456 | "push $%c[ss]\n\t" | |
9457 | "push %[sp]\n\t" | |
9458 | #endif | |
9459 | "pushf\n\t" | |
a547c6db | 9460 | __ASM_SIZE(push) " $%c[cs]\n\t" |
405b60d2 | 9461 | CALL_NOSPEC |
a547c6db YZ |
9462 | : |
9463 | #ifdef CONFIG_X86_64 | |
3f62de5f | 9464 | [sp]"=&r"(tmp), |
a547c6db | 9465 | #endif |
f5caf621 | 9466 | ASM_CALL_CONSTRAINT |
a547c6db | 9467 | : |
405b60d2 | 9468 | THUNK_TARGET(entry), |
a547c6db YZ |
9469 | [ss]"i"(__KERNEL_DS), |
9470 | [cs]"i"(__KERNEL_CS) | |
9471 | ); | |
f2485b3e | 9472 | } |
a547c6db | 9473 | } |
c207aee4 | 9474 | STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); |
a547c6db | 9475 | |
4d5c8a07 | 9476 | static bool vmx_has_emulated_msr(int index) |
6d396b55 | 9477 | { |
4d5c8a07 TL |
9478 | switch (index) { |
9479 | case MSR_IA32_SMBASE: | |
9480 | /* | |
9481 | * We cannot do SMM unless we can run the guest in big | |
9482 | * real mode. | |
9483 | */ | |
9484 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
9485 | case MSR_AMD64_VIRT_SPEC_CTRL: | |
9486 | /* This is AMD only. */ | |
9487 | return false; | |
9488 | default: | |
9489 | return true; | |
9490 | } | |
6d396b55 PB |
9491 | } |
9492 | ||
da8999d3 LJ |
9493 | static bool vmx_mpx_supported(void) |
9494 | { | |
9495 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
9496 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
9497 | } | |
9498 | ||
55412b2e WL |
9499 | static bool vmx_xsaves_supported(void) |
9500 | { | |
9501 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
9502 | SECONDARY_EXEC_XSAVES; | |
9503 | } | |
9504 | ||
51aa01d1 AK |
9505 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
9506 | { | |
c5ca8e57 | 9507 | u32 exit_intr_info; |
51aa01d1 AK |
9508 | bool unblock_nmi; |
9509 | u8 vector; | |
9510 | bool idtv_info_valid; | |
9511 | ||
9512 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 9513 | |
d02fcf50 | 9514 | if (enable_vnmi) { |
8a1b4392 PB |
9515 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9516 | return; | |
9517 | /* | |
9518 | * Can't use vmx->exit_intr_info since we're not sure what | |
9519 | * the exit reason is. | |
9520 | */ | |
9521 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9522 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
9523 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9524 | /* | |
9525 | * SDM 3: 27.7.1.2 (September 2008) | |
9526 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
9527 | * a guest IRET fault. | |
9528 | * SDM 3: 23.2.2 (September 2008) | |
9529 | * Bit 12 is undefined in any of the following cases: | |
9530 | * If the VM exit sets the valid bit in the IDT-vectoring | |
9531 | * information field. | |
9532 | * If the VM exit is due to a double fault. | |
9533 | */ | |
9534 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
9535 | vector != DF_VECTOR && !idtv_info_valid) | |
9536 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
9537 | GUEST_INTR_STATE_NMI); | |
9538 | else | |
9539 | vmx->loaded_vmcs->nmi_known_unmasked = | |
9540 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
9541 | & GUEST_INTR_STATE_NMI); | |
9542 | } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) | |
9543 | vmx->loaded_vmcs->vnmi_blocked_time += | |
9544 | ktime_to_ns(ktime_sub(ktime_get(), | |
9545 | vmx->loaded_vmcs->entry_time)); | |
51aa01d1 AK |
9546 | } |
9547 | ||
3ab66e8a | 9548 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
9549 | u32 idt_vectoring_info, |
9550 | int instr_len_field, | |
9551 | int error_code_field) | |
51aa01d1 | 9552 | { |
51aa01d1 AK |
9553 | u8 vector; |
9554 | int type; | |
9555 | bool idtv_info_valid; | |
9556 | ||
9557 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 9558 | |
3ab66e8a JK |
9559 | vcpu->arch.nmi_injected = false; |
9560 | kvm_clear_exception_queue(vcpu); | |
9561 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
9562 | |
9563 | if (!idtv_info_valid) | |
9564 | return; | |
9565 | ||
3ab66e8a | 9566 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 9567 | |
668f612f AK |
9568 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
9569 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 9570 | |
64a7ec06 | 9571 | switch (type) { |
37b96e98 | 9572 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 9573 | vcpu->arch.nmi_injected = true; |
668f612f | 9574 | /* |
7b4a25cb | 9575 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
9576 | * Clear bit "block by NMI" before VM entry if a NMI |
9577 | * delivery faulted. | |
668f612f | 9578 | */ |
3ab66e8a | 9579 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 9580 | break; |
37b96e98 | 9581 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 9582 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
9583 | /* fall through */ |
9584 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 9585 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 9586 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 9587 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 9588 | } else |
851eb667 | 9589 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 9590 | break; |
66fd3f7f | 9591 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 9592 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 9593 | /* fall through */ |
37b96e98 | 9594 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 9595 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
9596 | break; |
9597 | default: | |
9598 | break; | |
f7d9238f | 9599 | } |
cf393f75 AK |
9600 | } |
9601 | ||
83422e17 AK |
9602 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
9603 | { | |
3ab66e8a | 9604 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
9605 | VM_EXIT_INSTRUCTION_LEN, |
9606 | IDT_VECTORING_ERROR_CODE); | |
9607 | } | |
9608 | ||
b463a6f7 AK |
9609 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
9610 | { | |
3ab66e8a | 9611 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
9612 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
9613 | VM_ENTRY_INSTRUCTION_LEN, | |
9614 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
9615 | ||
9616 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9617 | } | |
9618 | ||
d7cd9796 GN |
9619 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
9620 | { | |
9621 | int i, nr_msrs; | |
9622 | struct perf_guest_switch_msr *msrs; | |
9623 | ||
9624 | msrs = perf_guest_get_msrs(&nr_msrs); | |
9625 | ||
9626 | if (!msrs) | |
9627 | return; | |
9628 | ||
9629 | for (i = 0; i < nr_msrs; i++) | |
9630 | if (msrs[i].host == msrs[i].guest) | |
9631 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
9632 | else | |
9633 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
129ce7ac | 9634 | msrs[i].host, false); |
d7cd9796 GN |
9635 | } |
9636 | ||
33365e7a | 9637 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
9638 | { |
9639 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9640 | u64 tscl; | |
9641 | u32 delta_tsc; | |
9642 | ||
9643 | if (vmx->hv_deadline_tsc == -1) | |
9644 | return; | |
9645 | ||
9646 | tscl = rdtsc(); | |
9647 | if (vmx->hv_deadline_tsc > tscl) | |
9648 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
9649 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
9650 | cpu_preemption_timer_multi); | |
9651 | else | |
9652 | delta_tsc = 0; | |
9653 | ||
9654 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
9655 | } | |
9656 | ||
a3b5ba49 | 9657 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 9658 | { |
a2fa3e9f | 9659 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d6e41f11 | 9660 | unsigned long debugctlmsr, cr3, cr4; |
104f226b | 9661 | |
8a1b4392 | 9662 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
d02fcf50 | 9663 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9664 | vmx->loaded_vmcs->soft_vnmi_blocked)) |
9665 | vmx->loaded_vmcs->entry_time = ktime_get(); | |
9666 | ||
104f226b AK |
9667 | /* Don't enter VMX if guest state is invalid, let the exit handler |
9668 | start emulation until we arrive back to a valid state */ | |
14168786 | 9669 | if (vmx->emulation_required) |
104f226b AK |
9670 | return; |
9671 | ||
a7653ecd RK |
9672 | if (vmx->ple_window_dirty) { |
9673 | vmx->ple_window_dirty = false; | |
9674 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
9675 | } | |
9676 | ||
012f83cb AG |
9677 | if (vmx->nested.sync_shadow_vmcs) { |
9678 | copy_vmcs12_to_shadow(vmx); | |
9679 | vmx->nested.sync_shadow_vmcs = false; | |
9680 | } | |
9681 | ||
104f226b AK |
9682 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9683 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9684 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9685 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9686 | ||
d6e41f11 | 9687 | cr3 = __get_current_cr3_fast(); |
44889942 | 9688 | if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) { |
d6e41f11 | 9689 | vmcs_writel(HOST_CR3, cr3); |
44889942 | 9690 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
d6e41f11 AL |
9691 | } |
9692 | ||
1e02ce4c | 9693 | cr4 = cr4_read_shadow(); |
44889942 | 9694 | if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) { |
d974baa3 | 9695 | vmcs_writel(HOST_CR4, cr4); |
44889942 | 9696 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 AL |
9697 | } |
9698 | ||
104f226b AK |
9699 | /* When single-stepping over STI and MOV SS, we must clear the |
9700 | * corresponding interruptibility bits in the guest state. Otherwise | |
9701 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9702 | * exceptions being set, but that's not correct for the guest debugging | |
9703 | * case. */ | |
9704 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9705 | vmx_set_interrupt_shadow(vcpu, 0); | |
9706 | ||
b9dd21e1 PB |
9707 | if (static_cpu_has(X86_FEATURE_PKU) && |
9708 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && | |
9709 | vcpu->arch.pkru != vmx->host_pkru) | |
9710 | __write_pkru(vcpu->arch.pkru); | |
1be0e61c | 9711 | |
d7cd9796 | 9712 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 9713 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 9714 | |
64672c95 YJ |
9715 | vmx_arm_hv_timer(vcpu); |
9716 | ||
74469996 KA |
9717 | /* |
9718 | * If this vCPU has touched SPEC_CTRL, restore the guest's value if | |
9719 | * it's non-zero. Since vmentry is serialising on affected CPUs, there | |
9720 | * is no need to worry about the conditional branch over the wrmsr | |
9721 | * being speculatively taken. | |
9722 | */ | |
692b5d07 | 9723 | x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); |
74469996 | 9724 | |
d462b819 | 9725 | vmx->__launched = vmx->loaded_vmcs->launched; |
f0ace387 | 9726 | |
bcbe4077 NS |
9727 | if (static_branch_unlikely(&vmx_l1d_should_flush)) |
9728 | vmx_l1d_flush(vcpu); | |
f0ace387 | 9729 | |
104f226b | 9730 | asm( |
6aa8b732 | 9731 | /* Store host registers */ |
b188c81f AK |
9732 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9733 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9734 | "push %%" _ASM_CX " \n\t" | |
9735 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9736 | "je 1f \n\t" |
b188c81f | 9737 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 9738 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9739 | "1: \n\t" |
d3edefc0 | 9740 | /* Reload cr2 if changed */ |
b188c81f AK |
9741 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9742 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9743 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 9744 | "je 2f \n\t" |
b188c81f | 9745 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 9746 | "2: \n\t" |
6aa8b732 | 9747 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 9748 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 9749 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9750 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9751 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9752 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9753 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9754 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9755 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9756 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9757 | "mov %c[r8](%0), %%r8 \n\t" |
9758 | "mov %c[r9](%0), %%r9 \n\t" | |
9759 | "mov %c[r10](%0), %%r10 \n\t" | |
9760 | "mov %c[r11](%0), %%r11 \n\t" | |
9761 | "mov %c[r12](%0), %%r12 \n\t" | |
9762 | "mov %c[r13](%0), %%r13 \n\t" | |
9763 | "mov %c[r14](%0), %%r14 \n\t" | |
9764 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9765 | #endif |
b188c81f | 9766 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9767 | |
6aa8b732 | 9768 | /* Enter guest mode */ |
83287ea4 | 9769 | "jne 1f \n\t" |
4ecac3fd | 9770 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9771 | "jmp 2f \n\t" |
9772 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9773 | "2: " | |
6aa8b732 | 9774 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9775 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9776 | "pop %0 \n\t" |
0cb5b306 | 9777 | "setbe %c[fail](%0)\n\t" |
b188c81f AK |
9778 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9779 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9780 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9781 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9782 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9783 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9784 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9785 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9786 | "mov %%r8, %c[r8](%0) \n\t" |
9787 | "mov %%r9, %c[r9](%0) \n\t" | |
9788 | "mov %%r10, %c[r10](%0) \n\t" | |
9789 | "mov %%r11, %c[r11](%0) \n\t" | |
9790 | "mov %%r12, %c[r12](%0) \n\t" | |
9791 | "mov %%r13, %c[r13](%0) \n\t" | |
9792 | "mov %%r14, %c[r14](%0) \n\t" | |
9793 | "mov %%r15, %c[r15](%0) \n\t" | |
0cb5b306 JM |
9794 | "xor %%r8d, %%r8d \n\t" |
9795 | "xor %%r9d, %%r9d \n\t" | |
9796 | "xor %%r10d, %%r10d \n\t" | |
9797 | "xor %%r11d, %%r11d \n\t" | |
9798 | "xor %%r12d, %%r12d \n\t" | |
9799 | "xor %%r13d, %%r13d \n\t" | |
9800 | "xor %%r14d, %%r14d \n\t" | |
9801 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 9802 | #endif |
b188c81f AK |
9803 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9804 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9805 | |
0cb5b306 JM |
9806 | "xor %%eax, %%eax \n\t" |
9807 | "xor %%ebx, %%ebx \n\t" | |
9808 | "xor %%esi, %%esi \n\t" | |
9809 | "xor %%edi, %%edi \n\t" | |
b188c81f | 9810 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
83287ea4 AK |
9811 | ".pushsection .rodata \n\t" |
9812 | ".global vmx_return \n\t" | |
9813 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9814 | ".popsection" | |
e08aa78a | 9815 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 9816 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9817 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9818 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9819 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9820 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9821 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9822 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9823 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9824 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9825 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9826 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9827 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9828 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9829 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9830 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9831 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9832 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9833 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9834 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9835 | #endif |
40712fae AK |
9836 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9837 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9838 | : "cc", "memory" |
9839 | #ifdef CONFIG_X86_64 | |
b188c81f | 9840 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 9841 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
9842 | #else |
9843 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
9844 | #endif |
9845 | ); | |
6aa8b732 | 9846 | |
74469996 KA |
9847 | /* |
9848 | * We do not use IBRS in the kernel. If this vCPU has used the | |
9849 | * SPEC_CTRL MSR it may have left it on; save the value and | |
9850 | * turn it off. This is much more efficient than blindly adding | |
9851 | * it to the atomic save/restore list. Especially as the former | |
9852 | * (Saving guest MSRs on vmexit) doesn't even exist in KVM. | |
9853 | * | |
9854 | * For non-nested case: | |
9855 | * If the L01 MSR bitmap does not intercept the MSR, then we need to | |
9856 | * save it. | |
9857 | * | |
9858 | * For nested case: | |
9859 | * If the L02 MSR bitmap does not intercept the MSR, then we need to | |
9860 | * save it. | |
9861 | */ | |
481ab71e | 9862 | if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) |
f471d71b | 9863 | vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); |
74469996 | 9864 | |
692b5d07 | 9865 | x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); |
74469996 | 9866 | |
117cc7a9 DW |
9867 | /* Eliminate branch target predictions from guest mode */ |
9868 | vmexit_fill_RSB(); | |
9869 | ||
2a7921b7 GN |
9870 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
9871 | if (debugctlmsr) | |
9872 | update_debugctlmsr(debugctlmsr); | |
9873 | ||
aa67f609 AK |
9874 | #ifndef CONFIG_X86_64 |
9875 | /* | |
9876 | * The sysexit path does not restore ds/es, so we must set them to | |
9877 | * a reasonable value ourselves. | |
9878 | * | |
9879 | * We can't defer this to vmx_load_host_state() since that function | |
9880 | * may be executed in interrupt context, which saves and restore segments | |
9881 | * around it, nullifying its effect. | |
9882 | */ | |
9883 | loadsegment(ds, __USER_DS); | |
9884 | loadsegment(es, __USER_DS); | |
9885 | #endif | |
9886 | ||
6de4f3ad | 9887 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9888 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9889 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9890 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9891 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9892 | vcpu->arch.regs_dirty = 0; |
9893 | ||
1be0e61c XG |
9894 | /* |
9895 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9896 | * back on host, so it is safe to read guest PKRU from current | |
9897 | * XSAVE. | |
9898 | */ | |
b9dd21e1 PB |
9899 | if (static_cpu_has(X86_FEATURE_PKU) && |
9900 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { | |
9901 | vcpu->arch.pkru = __read_pkru(); | |
9902 | if (vcpu->arch.pkru != vmx->host_pkru) | |
1be0e61c | 9903 | __write_pkru(vmx->host_pkru); |
1be0e61c XG |
9904 | } |
9905 | ||
e0b890d3 GN |
9906 | /* |
9907 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9908 | * we did not inject a still-pending event to L1 now because of | |
9909 | * nested_run_pending, we need to re-enable this bit. | |
9910 | */ | |
9911 | if (vmx->nested.nested_run_pending) | |
9912 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9913 | ||
9914 | vmx->nested.nested_run_pending = 0; | |
b060ca3b JM |
9915 | vmx->idt_vectoring_info = 0; |
9916 | ||
9917 | vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); | |
9918 | if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) | |
9919 | return; | |
9920 | ||
9921 | vmx->loaded_vmcs->launched = 1; | |
9922 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
e0b890d3 | 9923 | |
51aa01d1 AK |
9924 | vmx_complete_atomic_exit(vmx); |
9925 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9926 | vmx_complete_interrupts(vmx); |
6aa8b732 | 9927 | } |
c207aee4 | 9928 | STACK_FRAME_NON_STANDARD(vmx_vcpu_run); |
6aa8b732 | 9929 | |
1279a6b1 | 9930 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
9931 | { |
9932 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9933 | int cpu; | |
9934 | ||
1279a6b1 | 9935 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
9936 | return; |
9937 | ||
9938 | cpu = get_cpu(); | |
1279a6b1 | 9939 | vmx->loaded_vmcs = vmcs; |
4fa7734c PB |
9940 | vmx_vcpu_put(vcpu); |
9941 | vmx_vcpu_load(vcpu, cpu); | |
4fa7734c PB |
9942 | put_cpu(); |
9943 | } | |
9944 | ||
2f1fe811 JM |
9945 | /* |
9946 | * Ensure that the current vmcs of the logical processor is the | |
9947 | * vmcs01 of the vcpu before calling free_nested(). | |
9948 | */ | |
9949 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9950 | { | |
9951 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9952 | int r; | |
9953 | ||
9954 | r = vcpu_load(vcpu); | |
9955 | BUG_ON(r); | |
1279a6b1 | 9956 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
9957 | free_nested(vmx); |
9958 | vcpu_put(vcpu); | |
9959 | } | |
9960 | ||
6aa8b732 AK |
9961 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9962 | { | |
fb3f0f51 RR |
9963 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9964 | ||
843e4330 | 9965 | if (enable_pml) |
a3eaa864 | 9966 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9967 | free_vpid(vmx->vpid); |
4fa7734c | 9968 | leave_guest_mode(vcpu); |
2f1fe811 | 9969 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 9970 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9971 | kfree(vmx->guest_msrs); |
9972 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9973 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9974 | } |
9975 | ||
fb3f0f51 | 9976 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9977 | { |
fb3f0f51 | 9978 | int err; |
c16f862d | 9979 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
4b0be90f | 9980 | unsigned long *msr_bitmap; |
15ad7146 | 9981 | int cpu; |
6aa8b732 | 9982 | |
a2fa3e9f | 9983 | if (!vmx) |
fb3f0f51 RR |
9984 | return ERR_PTR(-ENOMEM); |
9985 | ||
991e7a0e | 9986 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9987 | |
fb3f0f51 RR |
9988 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9989 | if (err) | |
9990 | goto free_vcpu; | |
965b58a5 | 9991 | |
4e59516a PF |
9992 | err = -ENOMEM; |
9993 | ||
9994 | /* | |
9995 | * If PML is turned on, failure on enabling PML just results in failure | |
9996 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9997 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9998 | * for the guest, etc. | |
9999 | */ | |
10000 | if (enable_pml) { | |
10001 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
10002 | if (!vmx->pml_pg) | |
10003 | goto uninit_vcpu; | |
10004 | } | |
10005 | ||
a2fa3e9f | 10006 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
10007 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
10008 | > PAGE_SIZE); | |
0123be42 | 10009 | |
4e59516a PF |
10010 | if (!vmx->guest_msrs) |
10011 | goto free_pml; | |
965b58a5 | 10012 | |
b6d7026d PB |
10013 | err = alloc_loaded_vmcs(&vmx->vmcs01); |
10014 | if (err < 0) | |
fb3f0f51 | 10015 | goto free_msrs; |
a2fa3e9f | 10016 | |
4b0be90f PB |
10017 | msr_bitmap = vmx->vmcs01.msr_bitmap; |
10018 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); | |
10019 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); | |
10020 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); | |
10021 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); | |
10022 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); | |
10023 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); | |
10024 | vmx->msr_bitmap_mode = 0; | |
10025 | ||
b6d7026d | 10026 | vmx->loaded_vmcs = &vmx->vmcs01; |
15ad7146 AK |
10027 | cpu = get_cpu(); |
10028 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 10029 | vmx->vcpu.cpu = cpu; |
12d79917 | 10030 | vmx_vcpu_setup(vmx); |
fb3f0f51 | 10031 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 10032 | put_cpu(); |
35754c98 | 10033 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
10034 | err = alloc_apic_access_page(kvm); |
10035 | if (err) | |
5e4a0b3c | 10036 | goto free_vmcs; |
a63cb560 | 10037 | } |
fb3f0f51 | 10038 | |
b927a3ce | 10039 | if (enable_ept) { |
f51770ed TC |
10040 | err = init_rmode_identity_map(kvm); |
10041 | if (err) | |
93ea5388 | 10042 | goto free_vmcs; |
b927a3ce | 10043 | } |
b7ebfb05 | 10044 | |
5c614b35 | 10045 | if (nested) { |
b9c237bb | 10046 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
10047 | vmx->nested.vpid02 = allocate_vpid(); |
10048 | } | |
b9c237bb | 10049 | |
705699a1 | 10050 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 | 10051 | vmx->nested.current_vmptr = -1ull; |
a9d30f33 | 10052 | |
37e4c997 HZ |
10053 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
10054 | ||
31afb2ea PB |
10055 | /* |
10056 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR | |
10057 | * or POSTED_INTR_WAKEUP_VECTOR. | |
10058 | */ | |
10059 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; | |
10060 | vmx->pi_desc.sn = 1; | |
10061 | ||
fb3f0f51 RR |
10062 | return &vmx->vcpu; |
10063 | ||
10064 | free_vmcs: | |
5c614b35 | 10065 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 10066 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 10067 | free_msrs: |
fb3f0f51 | 10068 | kfree(vmx->guest_msrs); |
4e59516a PF |
10069 | free_pml: |
10070 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
10071 | uninit_vcpu: |
10072 | kvm_vcpu_uninit(&vmx->vcpu); | |
10073 | free_vcpu: | |
991e7a0e | 10074 | free_vpid(vmx->vpid); |
a4770347 | 10075 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 10076 | return ERR_PTR(err); |
6aa8b732 AK |
10077 | } |
10078 | ||
24fcb53c JK |
10079 | #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n" |
10080 | #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n" | |
275b72a9 KRW |
10081 | |
10082 | static int vmx_vm_init(struct kvm *kvm) | |
10083 | { | |
24fcb53c JK |
10084 | if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { |
10085 | switch (l1tf_mitigation) { | |
10086 | case L1TF_MITIGATION_OFF: | |
10087 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
10088 | /* 'I explicitly don't care' is set */ | |
10089 | break; | |
10090 | case L1TF_MITIGATION_FLUSH: | |
10091 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
10092 | case L1TF_MITIGATION_FULL: | |
10093 | /* | |
10094 | * Warn upon starting the first VM in a potentially | |
10095 | * insecure environment. | |
10096 | */ | |
10097 | if (cpu_smt_control == CPU_SMT_ENABLED) | |
10098 | pr_warn_once(L1TF_MSG_SMT); | |
10099 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) | |
10100 | pr_warn_once(L1TF_MSG_L1D); | |
10101 | break; | |
10102 | case L1TF_MITIGATION_FULL_FORCE: | |
10103 | /* Flush is enforced */ | |
10104 | break; | |
275b72a9 | 10105 | } |
275b72a9 KRW |
10106 | } |
10107 | return 0; | |
10108 | } | |
10109 | ||
002c7f7c YS |
10110 | static void __init vmx_check_processor_compat(void *rtn) |
10111 | { | |
10112 | struct vmcs_config vmcs_conf; | |
10113 | ||
10114 | *(int *)rtn = 0; | |
10115 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
10116 | *(int *)rtn = -EIO; | |
10117 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
10118 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
10119 | smp_processor_id()); | |
10120 | *(int *)rtn = -EIO; | |
10121 | } | |
10122 | } | |
10123 | ||
4b12f0de | 10124 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 10125 | { |
b18d5431 XG |
10126 | u8 cache; |
10127 | u64 ipat = 0; | |
4b12f0de | 10128 | |
522c68c4 | 10129 | /* For VT-d and EPT combination |
606decd6 | 10130 | * 1. MMIO: always map as UC |
522c68c4 SY |
10131 | * 2. EPT with VT-d: |
10132 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 10133 | * result, try to trust guest. |
522c68c4 SY |
10134 | * b. VT-d with snooping control feature: snooping control feature of |
10135 | * VT-d engine can guarantee the cache correctness. Just set it | |
10136 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 10137 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
10138 | * consistent with host MTRR |
10139 | */ | |
606decd6 PB |
10140 | if (is_mmio) { |
10141 | cache = MTRR_TYPE_UNCACHABLE; | |
10142 | goto exit; | |
10143 | } | |
10144 | ||
10145 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
10146 | ipat = VMX_EPT_IPAT_BIT; |
10147 | cache = MTRR_TYPE_WRBACK; | |
10148 | goto exit; | |
10149 | } | |
10150 | ||
10151 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
10152 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 10153 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
10154 | cache = MTRR_TYPE_WRBACK; |
10155 | else | |
10156 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
10157 | goto exit; |
10158 | } | |
10159 | ||
ff53604b | 10160 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
10161 | |
10162 | exit: | |
10163 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
10164 | } |
10165 | ||
17cc3935 | 10166 | static int vmx_get_lpage_level(void) |
344f414f | 10167 | { |
878403b7 SY |
10168 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
10169 | return PT_DIRECTORY_LEVEL; | |
10170 | else | |
10171 | /* For shadow and EPT supported 1GB page */ | |
10172 | return PT_PDPE_LEVEL; | |
344f414f JR |
10173 | } |
10174 | ||
feda805f XG |
10175 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
10176 | { | |
10177 | /* | |
10178 | * These bits in the secondary execution controls field | |
10179 | * are dynamic, the others are mostly based on the hypervisor | |
10180 | * architecture and the guest's CPUID. Do not touch the | |
10181 | * dynamic bits. | |
10182 | */ | |
10183 | u32 mask = | |
10184 | SECONDARY_EXEC_SHADOW_VMCS | | |
10185 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
10186 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
10187 | ||
10188 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
10189 | ||
10190 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
10191 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
10192 | } | |
10193 | ||
8322ebbb DM |
10194 | /* |
10195 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
10196 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
10197 | */ | |
10198 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
10199 | { | |
10200 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10201 | struct kvm_cpuid_entry2 *entry; | |
10202 | ||
10203 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
10204 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
10205 | ||
10206 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
10207 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
10208 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
10209 | } while (0) | |
10210 | ||
10211 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
10212 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
10213 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
10214 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
10215 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
10216 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
10217 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
10218 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
10219 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
10220 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
10221 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
10222 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
10223 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
10224 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
10225 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
10226 | ||
10227 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
10228 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
10229 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
10230 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
10231 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
c4ad77e0 | 10232 | cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); |
8322ebbb DM |
10233 | |
10234 | #undef cr4_fixed1_update | |
10235 | } | |
10236 | ||
0e851880 SY |
10237 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
10238 | { | |
4e47c7a6 | 10239 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4e47c7a6 | 10240 | |
80154d77 PB |
10241 | if (cpu_has_secondary_exec_ctrls()) { |
10242 | vmx_compute_secondary_exec_control(vmx); | |
10243 | vmcs_set_secondary_exec_control(vmx->secondary_exec_control); | |
ad756a16 | 10244 | } |
8b3e34e4 | 10245 | |
37e4c997 HZ |
10246 | if (nested_vmx_allowed(vcpu)) |
10247 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
10248 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
10249 | else | |
10250 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
10251 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
10252 | |
10253 | if (nested_vmx_allowed(vcpu)) | |
10254 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
10255 | } |
10256 | ||
d4330ef2 JR |
10257 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
10258 | { | |
7b8050f5 NHE |
10259 | if (func == 1 && nested) |
10260 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
10261 | } |
10262 | ||
25d92081 YZ |
10263 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
10264 | struct x86_exception *fault) | |
10265 | { | |
533558bc | 10266 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
c5f983f6 | 10267 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
533558bc | 10268 | u32 exit_reason; |
c5f983f6 | 10269 | unsigned long exit_qualification = vcpu->arch.exit_qualification; |
25d92081 | 10270 | |
c5f983f6 BD |
10271 | if (vmx->nested.pml_full) { |
10272 | exit_reason = EXIT_REASON_PML_FULL; | |
10273 | vmx->nested.pml_full = false; | |
10274 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; | |
10275 | } else if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 10276 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 10277 | else |
533558bc | 10278 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
c5f983f6 BD |
10279 | |
10280 | nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); | |
25d92081 YZ |
10281 | vmcs12->guest_physical_address = fault->address; |
10282 | } | |
10283 | ||
995f00a6 PF |
10284 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) |
10285 | { | |
bb97a016 | 10286 | return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT; |
995f00a6 PF |
10287 | } |
10288 | ||
155a97a3 NHE |
10289 | /* Callbacks for nested_ept_init_mmu_context: */ |
10290 | ||
10291 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
10292 | { | |
10293 | /* return the page table to be shadowed - in our case, EPT12 */ | |
10294 | return get_vmcs12(vcpu)->ept_pointer; | |
10295 | } | |
10296 | ||
ae1e2d10 | 10297 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 10298 | { |
ad896af0 | 10299 | WARN_ON(mmu_is_nested(vcpu)); |
a057e0e2 | 10300 | if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu))) |
ae1e2d10 PB |
10301 | return 1; |
10302 | ||
10303 | kvm_mmu_unload(vcpu); | |
ad896af0 | 10304 | kvm_init_shadow_ept_mmu(vcpu, |
b9c237bb | 10305 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
ae1e2d10 | 10306 | VMX_EPT_EXECUTE_ONLY_BIT, |
a057e0e2 | 10307 | nested_ept_ad_enabled(vcpu)); |
155a97a3 NHE |
10308 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
10309 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
10310 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
10311 | ||
10312 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 10313 | return 0; |
155a97a3 NHE |
10314 | } |
10315 | ||
10316 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
10317 | { | |
10318 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
10319 | } | |
10320 | ||
19d5f10b EK |
10321 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
10322 | u16 error_code) | |
10323 | { | |
10324 | bool inequality, bit; | |
10325 | ||
10326 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
10327 | inequality = | |
10328 | (error_code & vmcs12->page_fault_error_code_mask) != | |
10329 | vmcs12->page_fault_error_code_match; | |
10330 | return inequality ^ bit; | |
10331 | } | |
10332 | ||
feaf0c7d GN |
10333 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
10334 | struct x86_exception *fault) | |
10335 | { | |
10336 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
10337 | ||
10338 | WARN_ON(!is_guest_mode(vcpu)); | |
10339 | ||
305d0ab4 WL |
10340 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && |
10341 | !to_vmx(vcpu)->nested.nested_run_pending) { | |
b96fb439 PB |
10342 | vmcs12->vm_exit_intr_error_code = fault->error_code; |
10343 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10344 | PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | | |
10345 | INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, | |
10346 | fault->address); | |
7313c698 | 10347 | } else { |
feaf0c7d | 10348 | kvm_inject_page_fault(vcpu, fault); |
7313c698 | 10349 | } |
feaf0c7d GN |
10350 | } |
10351 | ||
6beb7bd5 JM |
10352 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, |
10353 | struct vmcs12 *vmcs12); | |
10354 | ||
10355 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
10356 | struct vmcs12 *vmcs12) |
10357 | { | |
10358 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5e2f30b7 | 10359 | struct page *page; |
6beb7bd5 | 10360 | u64 hpa; |
a2bcba50 WL |
10361 | |
10362 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
10363 | /* |
10364 | * Translate L1 physical address to host physical | |
10365 | * address for vmcs02. Keep the page pinned, so this | |
10366 | * physical address remains valid. We keep a reference | |
10367 | * to it so we can release it later. | |
10368 | */ | |
5e2f30b7 | 10369 | if (vmx->nested.apic_access_page) { /* shouldn't happen */ |
53a70daf | 10370 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
5e2f30b7 DH |
10371 | vmx->nested.apic_access_page = NULL; |
10372 | } | |
10373 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
10374 | /* |
10375 | * If translation failed, no matter: This feature asks | |
10376 | * to exit when accessing the given address, and if it | |
10377 | * can never be accessed, this feature won't do | |
10378 | * anything anyway. | |
10379 | */ | |
5e2f30b7 DH |
10380 | if (!is_error_page(page)) { |
10381 | vmx->nested.apic_access_page = page; | |
6beb7bd5 JM |
10382 | hpa = page_to_phys(vmx->nested.apic_access_page); |
10383 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
10384 | } else { | |
10385 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
10386 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
10387 | } | |
10388 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
10389 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
10390 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
10391 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
10392 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 10393 | } |
a7c0b07d WL |
10394 | |
10395 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5e2f30b7 | 10396 | if (vmx->nested.virtual_apic_page) { /* shouldn't happen */ |
53a70daf | 10397 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
5e2f30b7 DH |
10398 | vmx->nested.virtual_apic_page = NULL; |
10399 | } | |
10400 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr); | |
a7c0b07d WL |
10401 | |
10402 | /* | |
6beb7bd5 JM |
10403 | * If translation failed, VM entry will fail because |
10404 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
10405 | * Failing the vm entry is _not_ what the processor | |
10406 | * does but it's basically the only possibility we | |
10407 | * have. We could still enter the guest if CR8 load | |
10408 | * exits are enabled, CR8 store exits are enabled, and | |
10409 | * virtualize APIC access is disabled; in this case | |
10410 | * the processor would never use the TPR shadow and we | |
10411 | * could simply clear the bit from the execution | |
10412 | * control. But such a configuration is useless, so | |
10413 | * let's keep the code simple. | |
a7c0b07d | 10414 | */ |
5e2f30b7 DH |
10415 | if (!is_error_page(page)) { |
10416 | vmx->nested.virtual_apic_page = page; | |
6beb7bd5 JM |
10417 | hpa = page_to_phys(vmx->nested.virtual_apic_page); |
10418 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
10419 | } | |
a7c0b07d WL |
10420 | } |
10421 | ||
705699a1 | 10422 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10423 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
10424 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 10425 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
5e2f30b7 | 10426 | vmx->nested.pi_desc_page = NULL; |
705699a1 | 10427 | } |
5e2f30b7 DH |
10428 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr); |
10429 | if (is_error_page(page)) | |
6beb7bd5 | 10430 | return; |
5e2f30b7 DH |
10431 | vmx->nested.pi_desc_page = page; |
10432 | vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page); | |
705699a1 WV |
10433 | vmx->nested.pi_desc = |
10434 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
10435 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10436 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
10437 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
10438 | page_to_phys(vmx->nested.pi_desc_page) + | |
10439 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10440 | (PAGE_SIZE - 1))); | |
705699a1 | 10441 | } |
6beb7bd5 JM |
10442 | if (cpu_has_vmx_msr_bitmap() && |
10443 | nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) && | |
10444 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
cf40088f KA |
10445 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
10446 | CPU_BASED_USE_MSR_BITMAPS); | |
6beb7bd5 JM |
10447 | else |
10448 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
10449 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
10450 | } |
10451 | ||
f4124500 JK |
10452 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
10453 | { | |
10454 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
10455 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10456 | ||
10457 | if (vcpu->arch.virtual_tsc_khz == 0) | |
10458 | return; | |
10459 | ||
10460 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
10461 | * hrtimer_start does not guarantee this. */ | |
10462 | if (preemption_timeout <= 1) { | |
10463 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
10464 | return; | |
10465 | } | |
10466 | ||
10467 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10468 | preemption_timeout *= 1000000; | |
10469 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
10470 | hrtimer_start(&vmx->nested.preemption_timer, | |
10471 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
10472 | } | |
10473 | ||
56a20510 JM |
10474 | static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, |
10475 | struct vmcs12 *vmcs12) | |
10476 | { | |
10477 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
10478 | return 0; | |
10479 | ||
10480 | if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) || | |
10481 | !page_address_valid(vcpu, vmcs12->io_bitmap_b)) | |
10482 | return -EINVAL; | |
10483 | ||
10484 | return 0; | |
10485 | } | |
10486 | ||
3af18d9c WV |
10487 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
10488 | struct vmcs12 *vmcs12) | |
10489 | { | |
3af18d9c WV |
10490 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
10491 | return 0; | |
10492 | ||
5fa99cbe | 10493 | if (!page_address_valid(vcpu, vmcs12->msr_bitmap)) |
3af18d9c WV |
10494 | return -EINVAL; |
10495 | ||
10496 | return 0; | |
10497 | } | |
10498 | ||
712b12d7 JM |
10499 | static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, |
10500 | struct vmcs12 *vmcs12) | |
10501 | { | |
10502 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10503 | return 0; | |
10504 | ||
10505 | if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)) | |
10506 | return -EINVAL; | |
10507 | ||
10508 | return 0; | |
10509 | } | |
10510 | ||
3af18d9c WV |
10511 | /* |
10512 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
10513 | * we do not use the hardware. | |
10514 | */ | |
10515 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
10516 | struct vmcs12 *vmcs12) | |
10517 | { | |
82f0dd4b | 10518 | int msr; |
f2b93280 | 10519 | struct page *page; |
d048c098 | 10520 | unsigned long *msr_bitmap_l1; |
4b0be90f | 10521 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap; |
33241bfe | 10522 | /* |
74469996 | 10523 | * pred_cmd & spec_ctrl are trying to verify two things: |
33241bfe AR |
10524 | * |
10525 | * 1. L0 gave a permission to L1 to actually passthrough the MSR. This | |
10526 | * ensures that we do not accidentally generate an L02 MSR bitmap | |
10527 | * from the L12 MSR bitmap that is too permissive. | |
10528 | * 2. That L1 or L2s have actually used the MSR. This avoids | |
10529 | * unnecessarily merging of the bitmap if the MSR is unused. This | |
10530 | * works properly because we only update the L01 MSR bitmap lazily. | |
10531 | * So even if L0 should pass L1 these MSRs, the L01 bitmap is only | |
10532 | * updated to reflect this when L1 (or its L2s) actually write to | |
10533 | * the MSR. | |
10534 | */ | |
cb9138cc KA |
10535 | bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD); |
10536 | bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL); | |
f2b93280 | 10537 | |
33241bfe | 10538 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
74469996 | 10539 | !pred_cmd && !spec_ctrl) |
f2b93280 WV |
10540 | return false; |
10541 | ||
5e2f30b7 DH |
10542 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap); |
10543 | if (is_error_page(page)) | |
f2b93280 | 10544 | return false; |
d048c098 | 10545 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
f2b93280 | 10546 | |
d048c098 RK |
10547 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
10548 | ||
f2b93280 | 10549 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
10550 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
10551 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
10552 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10553 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 10554 | msr, MSR_TYPE_R); |
d048c098 RK |
10555 | |
10556 | nested_vmx_disable_intercept_for_msr( | |
10557 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
10558 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
10559 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 10560 | |
608406e2 | 10561 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 10562 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 10563 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10564 | APIC_BASE_MSR + (APIC_EOI >> 4), |
10565 | MSR_TYPE_W); | |
10566 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10567 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10568 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
10569 | MSR_TYPE_W); | |
10570 | } | |
82f0dd4b | 10571 | } |
33241bfe | 10572 | |
74469996 KA |
10573 | if (spec_ctrl) |
10574 | nested_vmx_disable_intercept_for_msr( | |
10575 | msr_bitmap_l1, msr_bitmap_l0, | |
10576 | MSR_IA32_SPEC_CTRL, | |
10577 | MSR_TYPE_R | MSR_TYPE_W); | |
10578 | ||
33241bfe AR |
10579 | if (pred_cmd) |
10580 | nested_vmx_disable_intercept_for_msr( | |
10581 | msr_bitmap_l1, msr_bitmap_l0, | |
10582 | MSR_IA32_PRED_CMD, | |
10583 | MSR_TYPE_W); | |
10584 | ||
f2b93280 | 10585 | kunmap(page); |
53a70daf | 10586 | kvm_release_page_clean(page); |
f2b93280 WV |
10587 | |
10588 | return true; | |
10589 | } | |
10590 | ||
76a19ac5 KS |
10591 | static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu, |
10592 | struct vmcs12 *vmcs12) | |
10593 | { | |
10594 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && | |
10595 | !page_address_valid(vcpu, vmcs12->apic_access_addr)) | |
10596 | return -EINVAL; | |
10597 | else | |
10598 | return 0; | |
10599 | } | |
10600 | ||
f2b93280 WV |
10601 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, |
10602 | struct vmcs12 *vmcs12) | |
10603 | { | |
82f0dd4b | 10604 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 10605 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
10606 | !nested_cpu_has_vid(vmcs12) && |
10607 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
10608 | return 0; |
10609 | ||
10610 | /* | |
10611 | * If virtualize x2apic mode is enabled, | |
10612 | * virtualize apic access must be disabled. | |
10613 | */ | |
82f0dd4b WV |
10614 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
10615 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
10616 | return -EINVAL; |
10617 | ||
608406e2 WV |
10618 | /* |
10619 | * If virtual interrupt delivery is enabled, | |
10620 | * we must exit on external interrupts. | |
10621 | */ | |
10622 | if (nested_cpu_has_vid(vmcs12) && | |
10623 | !nested_exit_on_intr(vcpu)) | |
10624 | return -EINVAL; | |
10625 | ||
705699a1 WV |
10626 | /* |
10627 | * bits 15:8 should be zero in posted_intr_nv, | |
10628 | * the descriptor address has been already checked | |
10629 | * in nested_get_vmcs12_pages. | |
10630 | */ | |
10631 | if (nested_cpu_has_posted_intr(vmcs12) && | |
10632 | (!nested_cpu_has_vid(vmcs12) || | |
10633 | !nested_exit_intr_ack_set(vcpu) || | |
10634 | vmcs12->posted_intr_nv & 0xff00)) | |
10635 | return -EINVAL; | |
10636 | ||
f2b93280 WV |
10637 | /* tpr shadow is needed by all apicv features. */ |
10638 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10639 | return -EINVAL; | |
10640 | ||
10641 | return 0; | |
3af18d9c WV |
10642 | } |
10643 | ||
e9ac033e EK |
10644 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
10645 | unsigned long count_field, | |
92d71bc6 | 10646 | unsigned long addr_field) |
ff651cb6 | 10647 | { |
92d71bc6 | 10648 | int maxphyaddr; |
e9ac033e EK |
10649 | u64 count, addr; |
10650 | ||
10651 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
10652 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
10653 | WARN_ON(1); | |
10654 | return -EINVAL; | |
10655 | } | |
10656 | if (count == 0) | |
10657 | return 0; | |
92d71bc6 | 10658 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
10659 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
10660 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 10661 | pr_debug_ratelimited( |
e9ac033e EK |
10662 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
10663 | addr_field, maxphyaddr, count, addr); | |
10664 | return -EINVAL; | |
10665 | } | |
10666 | return 0; | |
10667 | } | |
10668 | ||
10669 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
10670 | struct vmcs12 *vmcs12) | |
10671 | { | |
e9ac033e EK |
10672 | if (vmcs12->vm_exit_msr_load_count == 0 && |
10673 | vmcs12->vm_exit_msr_store_count == 0 && | |
10674 | vmcs12->vm_entry_msr_load_count == 0) | |
10675 | return 0; /* Fast path */ | |
e9ac033e | 10676 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 10677 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 10678 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 10679 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 10680 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 10681 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
10682 | return -EINVAL; |
10683 | return 0; | |
10684 | } | |
10685 | ||
c5f983f6 BD |
10686 | static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, |
10687 | struct vmcs12 *vmcs12) | |
10688 | { | |
10689 | u64 address = vmcs12->pml_address; | |
10690 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
10691 | ||
10692 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { | |
10693 | if (!nested_cpu_has_ept(vmcs12) || | |
10694 | !IS_ALIGNED(address, 4096) || | |
10695 | address >> maxphyaddr) | |
10696 | return -EINVAL; | |
10697 | } | |
10698 | ||
10699 | return 0; | |
10700 | } | |
10701 | ||
e9ac033e EK |
10702 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, |
10703 | struct vmx_msr_entry *e) | |
10704 | { | |
10705 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 10706 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
10707 | return -EINVAL; |
10708 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
10709 | e->index == MSR_IA32_UCODE_REV) | |
10710 | return -EINVAL; | |
10711 | if (e->reserved != 0) | |
ff651cb6 WV |
10712 | return -EINVAL; |
10713 | return 0; | |
10714 | } | |
10715 | ||
e9ac033e EK |
10716 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
10717 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
10718 | { |
10719 | if (e->index == MSR_FS_BASE || | |
10720 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
10721 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
10722 | nested_vmx_msr_check_common(vcpu, e)) | |
10723 | return -EINVAL; | |
10724 | return 0; | |
10725 | } | |
10726 | ||
10727 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
10728 | struct vmx_msr_entry *e) | |
10729 | { | |
10730 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
10731 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
10732 | return -EINVAL; |
10733 | return 0; | |
10734 | } | |
10735 | ||
10736 | /* | |
10737 | * Load guest's/host's msr at nested entry/exit. | |
10738 | * return 0 for success, entry index for failure. | |
10739 | */ | |
10740 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10741 | { | |
10742 | u32 i; | |
10743 | struct vmx_msr_entry e; | |
10744 | struct msr_data msr; | |
10745 | ||
10746 | msr.host_initiated = false; | |
10747 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
10748 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
10749 | &e, sizeof(e))) { | |
bbe41b95 | 10750 | pr_debug_ratelimited( |
e9ac033e EK |
10751 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10752 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10753 | goto fail; |
e9ac033e EK |
10754 | } |
10755 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 10756 | pr_debug_ratelimited( |
e9ac033e EK |
10757 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10758 | __func__, i, e.index, e.reserved); | |
10759 | goto fail; | |
10760 | } | |
ff651cb6 WV |
10761 | msr.index = e.index; |
10762 | msr.data = e.value; | |
e9ac033e | 10763 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 10764 | pr_debug_ratelimited( |
e9ac033e EK |
10765 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
10766 | __func__, i, e.index, e.value); | |
ff651cb6 | 10767 | goto fail; |
e9ac033e | 10768 | } |
ff651cb6 WV |
10769 | } |
10770 | return 0; | |
10771 | fail: | |
10772 | return i + 1; | |
10773 | } | |
10774 | ||
10775 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10776 | { | |
10777 | u32 i; | |
10778 | struct vmx_msr_entry e; | |
10779 | ||
10780 | for (i = 0; i < count; i++) { | |
609e36d3 | 10781 | struct msr_data msr_info; |
54bf36aa PB |
10782 | if (kvm_vcpu_read_guest(vcpu, |
10783 | gpa + i * sizeof(e), | |
10784 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 10785 | pr_debug_ratelimited( |
e9ac033e EK |
10786 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10787 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10788 | return -EINVAL; |
e9ac033e EK |
10789 | } |
10790 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 10791 | pr_debug_ratelimited( |
e9ac033e EK |
10792 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10793 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 10794 | return -EINVAL; |
e9ac033e | 10795 | } |
609e36d3 PB |
10796 | msr_info.host_initiated = false; |
10797 | msr_info.index = e.index; | |
10798 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 10799 | pr_debug_ratelimited( |
e9ac033e EK |
10800 | "%s cannot read MSR (%u, 0x%x)\n", |
10801 | __func__, i, e.index); | |
10802 | return -EINVAL; | |
10803 | } | |
54bf36aa PB |
10804 | if (kvm_vcpu_write_guest(vcpu, |
10805 | gpa + i * sizeof(e) + | |
10806 | offsetof(struct vmx_msr_entry, value), | |
10807 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 10808 | pr_debug_ratelimited( |
e9ac033e | 10809 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 10810 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
10811 | return -EINVAL; |
10812 | } | |
ff651cb6 WV |
10813 | } |
10814 | return 0; | |
10815 | } | |
10816 | ||
1dc35dac LP |
10817 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
10818 | { | |
10819 | unsigned long invalid_mask; | |
10820 | ||
10821 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
10822 | return (val & invalid_mask) == 0; | |
10823 | } | |
10824 | ||
9ed38ffa LP |
10825 | /* |
10826 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
10827 | * emulating VM entry into a guest with EPT enabled. | |
10828 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
10829 | * is assigned to entry_failure_code on failure. | |
10830 | */ | |
10831 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 10832 | u32 *entry_failure_code) |
9ed38ffa | 10833 | { |
9ed38ffa | 10834 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 10835 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
10836 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
10837 | return 1; | |
10838 | } | |
10839 | ||
10840 | /* | |
10841 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
10842 | * must not be dereferenced. | |
10843 | */ | |
10844 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
10845 | !nested_ept) { | |
10846 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
10847 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
10848 | return 1; | |
10849 | } | |
10850 | } | |
10851 | ||
10852 | vcpu->arch.cr3 = cr3; | |
10853 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10854 | } | |
10855 | ||
10856 | kvm_mmu_reset_context(vcpu); | |
10857 | return 0; | |
10858 | } | |
10859 | ||
fe3ef05c NHE |
10860 | /* |
10861 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
10862 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 10863 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
10864 | * guest in a way that will both be appropriate to L1's requests, and our |
10865 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
10866 | * function also has additional necessary side-effects, like setting various | |
10867 | * vcpu->arch fields. | |
ee146c1c LP |
10868 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
10869 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 10870 | */ |
ee146c1c | 10871 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
ca0bde28 | 10872 | bool from_vmentry, u32 *entry_failure_code) |
fe3ef05c NHE |
10873 | { |
10874 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
03efce6f | 10875 | u32 exec_control, vmcs12_exec_ctrl; |
fe3ef05c NHE |
10876 | |
10877 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
10878 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
10879 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
10880 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10881 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10882 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10883 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10884 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10885 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
10886 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
10887 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
10888 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10889 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10890 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10891 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10892 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10893 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10894 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10895 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
10896 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
10897 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
10898 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10899 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10900 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10901 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10902 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
10903 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
10904 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
10905 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
10906 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10907 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10908 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10909 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10910 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10911 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10912 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10913 | ||
cf8b84f4 JM |
10914 | if (from_vmentry && |
10915 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
10916 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
10917 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
10918 | } else { | |
10919 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
10920 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
10921 | } | |
cf8b84f4 JM |
10922 | if (from_vmentry) { |
10923 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
10924 | vmcs12->vm_entry_intr_info_field); | |
10925 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
10926 | vmcs12->vm_entry_exception_error_code); | |
10927 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
10928 | vmcs12->vm_entry_instruction_len); | |
10929 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
10930 | vmcs12->guest_interruptibility_info); | |
2d6144e3 WL |
10931 | vmx->loaded_vmcs->nmi_known_unmasked = |
10932 | !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); | |
cf8b84f4 JM |
10933 | } else { |
10934 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
10935 | } | |
fe3ef05c | 10936 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 10937 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
10938 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
10939 | vmcs12->guest_pending_dbg_exceptions); | |
10940 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
10941 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
10942 | ||
81dc01f7 WL |
10943 | if (nested_cpu_has_xsaves(vmcs12)) |
10944 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
10945 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
10946 | ||
f4124500 | 10947 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
10948 | |
10949 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 10950 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
10951 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
10952 | if (vmx->hv_deadline_tsc == -1) | |
10953 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 10954 | |
9314006d | 10955 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 | 10956 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10957 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; |
10958 | vmx->nested.pi_pending = false; | |
06a5524f | 10959 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); |
6beb7bd5 | 10960 | } else { |
705699a1 | 10961 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 10962 | } |
705699a1 | 10963 | |
f4124500 | 10964 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 10965 | |
f4124500 JK |
10966 | vmx->nested.preemption_timer_expired = false; |
10967 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
10968 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 10969 | |
fe3ef05c NHE |
10970 | /* |
10971 | * Whether page-faults are trapped is determined by a combination of | |
10972 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
10973 | * If enable_ept, L0 doesn't care about page faults and we should | |
10974 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
10975 | * care about (at least some) page faults, and because it is not easy | |
10976 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
10977 | * to exit on each and every L2 page fault. This is done by setting | |
10978 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
10979 | * Note that below we don't need special code to set EB.PF beyond the | |
10980 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
10981 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
10982 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
fe3ef05c NHE |
10983 | */ |
10984 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10985 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10986 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10987 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10988 | ||
10989 | if (cpu_has_secondary_exec_ctrls()) { | |
80154d77 | 10990 | exec_control = vmx->secondary_exec_control; |
e2821620 | 10991 | |
fe3ef05c | 10992 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 10993 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
90a2db6d | 10994 | SECONDARY_EXEC_ENABLE_INVPCID | |
b3a2a907 | 10995 | SECONDARY_EXEC_RDTSCP | |
3db13480 | 10996 | SECONDARY_EXEC_XSAVES | |
696dfd95 | 10997 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
27c42a1b BD |
10998 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
10999 | SECONDARY_EXEC_ENABLE_VMFUNC); | |
fe3ef05c | 11000 | if (nested_cpu_has(vmcs12, |
03efce6f BD |
11001 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { |
11002 | vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & | |
11003 | ~SECONDARY_EXEC_ENABLE_PML; | |
11004 | exec_control |= vmcs12_exec_ctrl; | |
11005 | } | |
fe3ef05c | 11006 | |
27c42a1b BD |
11007 | /* All VMFUNCs are currently emulated through L0 vmexits. */ |
11008 | if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC) | |
11009 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
11010 | ||
608406e2 WV |
11011 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
11012 | vmcs_write64(EOI_EXIT_BITMAP0, | |
11013 | vmcs12->eoi_exit_bitmap0); | |
11014 | vmcs_write64(EOI_EXIT_BITMAP1, | |
11015 | vmcs12->eoi_exit_bitmap1); | |
11016 | vmcs_write64(EOI_EXIT_BITMAP2, | |
11017 | vmcs12->eoi_exit_bitmap2); | |
11018 | vmcs_write64(EOI_EXIT_BITMAP3, | |
11019 | vmcs12->eoi_exit_bitmap3); | |
11020 | vmcs_write16(GUEST_INTR_STATUS, | |
11021 | vmcs12->guest_intr_status); | |
11022 | } | |
11023 | ||
6beb7bd5 JM |
11024 | /* |
11025 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
11026 | * nested_get_vmcs12_pages will either fix it up or | |
11027 | * remove the VM execution control. | |
11028 | */ | |
11029 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
11030 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
11031 | ||
fe3ef05c NHE |
11032 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
11033 | } | |
11034 | ||
11035 | ||
11036 | /* | |
11037 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
11038 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
11039 | * Other fields are different per CPU, and will be set later when | |
11040 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
11041 | */ | |
a547c6db | 11042 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 11043 | |
83bafef1 JM |
11044 | /* |
11045 | * Set the MSR load/store lists to match L0's settings. | |
11046 | */ | |
11047 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
6e3dedb6 KRW |
11048 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); |
11049 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); | |
11050 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); | |
11051 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); | |
83bafef1 | 11052 | |
fe3ef05c NHE |
11053 | /* |
11054 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
11055 | * entry, but only if the current (host) sp changed from the value | |
11056 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
11057 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
11058 | * here we just force the write to happen on entry. | |
11059 | */ | |
11060 | vmx->host_rsp = 0; | |
11061 | ||
11062 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
11063 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
11064 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
11065 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
11066 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 11067 | |
6beb7bd5 JM |
11068 | /* |
11069 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
11070 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
11071 | * will result in a VM entry failure. | |
11072 | */ | |
a7c0b07d | 11073 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 11074 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d | 11075 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
51aa68e7 JM |
11076 | } else { |
11077 | #ifdef CONFIG_X86_64 | |
11078 | exec_control |= CPU_BASED_CR8_LOAD_EXITING | | |
11079 | CPU_BASED_CR8_STORE_EXITING; | |
11080 | #endif | |
a7c0b07d WL |
11081 | } |
11082 | ||
fe3ef05c | 11083 | /* |
3af18d9c | 11084 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
11085 | * Rather, exit every time. |
11086 | */ | |
fe3ef05c NHE |
11087 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
11088 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
11089 | ||
11090 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
11091 | ||
11092 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
11093 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
11094 | * trap. Note that CR0.TS also needs updating - we do this later. | |
11095 | */ | |
11096 | update_exception_bitmap(vcpu); | |
11097 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
11098 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
11099 | ||
8049d651 NHE |
11100 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
11101 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
11102 | * bits are further modified by vmx_set_efer() below. | |
11103 | */ | |
f4124500 | 11104 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
11105 | |
11106 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
11107 | * emulated by vmx_set_efer(), below. | |
11108 | */ | |
2961e876 | 11109 | vm_entry_controls_init(vmx, |
8049d651 NHE |
11110 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
11111 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
11112 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
11113 | ||
cf8b84f4 JM |
11114 | if (from_vmentry && |
11115 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 11116 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 11117 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 11118 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 11119 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 11120 | } |
fe3ef05c NHE |
11121 | |
11122 | set_cr4_guest_host_mask(vmx); | |
11123 | ||
cf8b84f4 JM |
11124 | if (from_vmentry && |
11125 | vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) | |
36be0b9d PB |
11126 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); |
11127 | ||
f7f5542f KA |
11128 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
11129 | ||
c95ba92a PF |
11130 | if (kvm_has_tsc_control) |
11131 | decache_tsc_multiplier(vmx); | |
fe3ef05c | 11132 | |
4b0be90f PB |
11133 | if (cpu_has_vmx_msr_bitmap()) |
11134 | vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); | |
11135 | ||
fe3ef05c NHE |
11136 | if (enable_vpid) { |
11137 | /* | |
5c614b35 WL |
11138 | * There is no direct mapping between vpid02 and vpid12, the |
11139 | * vpid02 is per-vCPU for L0 and reused while the value of | |
11140 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
11141 | * The vpid12 is allocated by L1 for L2, so it will not | |
11142 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
11143 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 11144 | */ |
5c614b35 WL |
11145 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
11146 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
11147 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
11148 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
11149 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
11150 | } | |
11151 | } else { | |
11152 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
11153 | vmx_flush_tlb(vcpu); | |
11154 | } | |
11155 | ||
fe3ef05c NHE |
11156 | } |
11157 | ||
1fb883bb LP |
11158 | if (enable_pml) { |
11159 | /* | |
11160 | * Conceptually we want to copy the PML address and index from | |
11161 | * vmcs01 here, and then back to vmcs01 on nested vmexit. But, | |
11162 | * since we always flush the log on each vmexit, this happens | |
11163 | * to be equivalent to simply resetting the fields in vmcs02. | |
11164 | */ | |
11165 | ASSERT(vmx->pml_pg); | |
11166 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
11167 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
11168 | } | |
11169 | ||
155a97a3 | 11170 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
11171 | if (nested_ept_init_mmu_context(vcpu)) { |
11172 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
11173 | return 1; | |
11174 | } | |
fb6c8198 JM |
11175 | } else if (nested_cpu_has2(vmcs12, |
11176 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
5ad2874a | 11177 | vmx_flush_tlb(vcpu); |
155a97a3 NHE |
11178 | } |
11179 | ||
fe3ef05c | 11180 | /* |
bd7e5b08 PB |
11181 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
11182 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
11183 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
11184 | * the specifications by L1; It's not enough to take | |
11185 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
11186 | * have more bits than L1 expected. | |
11187 | */ | |
11188 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
11189 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
11190 | ||
11191 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
11192 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
11193 | ||
cf8b84f4 JM |
11194 | if (from_vmentry && |
11195 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
11196 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
11197 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
11198 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
11199 | else | |
11200 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11201 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
11202 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11203 | ||
9ed38ffa | 11204 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 11205 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
11206 | entry_failure_code)) |
11207 | return 1; | |
7ca29de2 | 11208 | |
feaf0c7d GN |
11209 | if (!enable_ept) |
11210 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
11211 | ||
3633cfc3 NHE |
11212 | /* |
11213 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
11214 | */ | |
11215 | if (enable_ept) { | |
11216 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
11217 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
11218 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
11219 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
11220 | } | |
11221 | ||
fe3ef05c NHE |
11222 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
11223 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 11224 | return 0; |
fe3ef05c NHE |
11225 | } |
11226 | ||
ca0bde28 | 11227 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 11228 | { |
cd232ad0 | 11229 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 11230 | |
6dfacadd | 11231 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
11232 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
11233 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 11234 | |
56a20510 JM |
11235 | if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12)) |
11236 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11237 | ||
ca0bde28 JM |
11238 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
11239 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 11240 | |
76a19ac5 KS |
11241 | if (nested_vmx_check_apic_access_controls(vcpu, vmcs12)) |
11242 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11243 | ||
712b12d7 JM |
11244 | if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12)) |
11245 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11246 | ||
ca0bde28 JM |
11247 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
11248 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 11249 | |
ca0bde28 JM |
11250 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
11251 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 11252 | |
c5f983f6 BD |
11253 | if (nested_vmx_check_pml_controls(vcpu, vmcs12)) |
11254 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11255 | ||
7c177938 | 11256 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 11257 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 11258 | vmx->nested.nested_vmx_procbased_ctls_high) || |
2e5b0bd9 JM |
11259 | (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
11260 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
11261 | vmx->nested.nested_vmx_secondary_ctls_low, | |
11262 | vmx->nested.nested_vmx_secondary_ctls_high)) || | |
7c177938 | 11263 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
11264 | vmx->nested.nested_vmx_pinbased_ctls_low, |
11265 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 11266 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 11267 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 11268 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 11269 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 11270 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 11271 | vmx->nested.nested_vmx_entry_ctls_high)) |
ca0bde28 | 11272 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 11273 | |
41ab9372 BD |
11274 | if (nested_cpu_has_vmfunc(vmcs12)) { |
11275 | if (vmcs12->vm_function_control & | |
11276 | ~vmx->nested.nested_vmx_vmfunc_controls) | |
11277 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11278 | ||
11279 | if (nested_cpu_has_eptp_switching(vmcs12)) { | |
11280 | if (!nested_cpu_has_ept(vmcs12) || | |
11281 | !page_address_valid(vcpu, vmcs12->eptp_list_address)) | |
11282 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11283 | } | |
11284 | } | |
27c42a1b | 11285 | |
c7c2c709 JM |
11286 | if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) |
11287 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11288 | ||
3899152c | 11289 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 11290 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
11291 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
11292 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
11293 | ||
11294 | return 0; | |
11295 | } | |
11296 | ||
11297 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11298 | u32 *exit_qual) | |
11299 | { | |
11300 | bool ia32e; | |
11301 | ||
11302 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 11303 | |
3899152c | 11304 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 11305 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 11306 | return 1; |
ca0bde28 JM |
11307 | |
11308 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
11309 | vmcs12->vmcs_link_pointer != -1ull) { | |
11310 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 11311 | return 1; |
7c177938 NHE |
11312 | } |
11313 | ||
384bb783 | 11314 | /* |
cb0c8cda | 11315 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
11316 | * are performed on the field for the IA32_EFER MSR: |
11317 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
11318 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
11319 | * the IA-32e mode guest VM-exit control. It must also be identical | |
11320 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
11321 | * CR0.PG) is 1. | |
11322 | */ | |
ca0bde28 JM |
11323 | if (to_vmx(vcpu)->nested.nested_run_pending && |
11324 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
11325 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
11326 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
11327 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
11328 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 11329 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 11330 | return 1; |
384bb783 JK |
11331 | } |
11332 | ||
11333 | /* | |
11334 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
11335 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
11336 | * the values of the LMA and LME bits in the field must each be that of | |
11337 | * the host address-space size VM-exit control. | |
11338 | */ | |
11339 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
11340 | ia32e = (vmcs12->vm_exit_controls & | |
11341 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
11342 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
11343 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 11344 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 11345 | return 1; |
ca0bde28 JM |
11346 | } |
11347 | ||
f1b026a3 WL |
11348 | if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && |
11349 | (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) || | |
11350 | (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))) | |
11351 | return 1; | |
11352 | ||
ca0bde28 JM |
11353 | return 0; |
11354 | } | |
11355 | ||
858e25c0 JM |
11356 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
11357 | { | |
11358 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11359 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
858e25c0 JM |
11360 | u32 msr_entry_idx; |
11361 | u32 exit_qual; | |
f7f5542f | 11362 | int r; |
858e25c0 | 11363 | |
858e25c0 JM |
11364 | enter_guest_mode(vcpu); |
11365 | ||
11366 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
11367 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11368 | ||
8819227c | 11369 | vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); |
858e25c0 JM |
11370 | vmx_segment_cache_clear(vmx); |
11371 | ||
f7f5542f KA |
11372 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
11373 | vcpu->arch.tsc_offset += vmcs12->tsc_offset; | |
11374 | ||
11375 | r = EXIT_REASON_INVALID_STATE; | |
11376 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) | |
11377 | goto fail; | |
858e25c0 JM |
11378 | |
11379 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
11380 | ||
f7f5542f | 11381 | r = EXIT_REASON_MSR_LOAD_FAIL; |
858e25c0 JM |
11382 | msr_entry_idx = nested_vmx_load_msr(vcpu, |
11383 | vmcs12->vm_entry_msr_load_addr, | |
11384 | vmcs12->vm_entry_msr_load_count); | |
f7f5542f KA |
11385 | if (msr_entry_idx) |
11386 | goto fail; | |
858e25c0 | 11387 | |
858e25c0 JM |
11388 | /* |
11389 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
11390 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
11391 | * returned as far as L1 is concerned. It will only return (and set | |
11392 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
11393 | */ | |
11394 | return 0; | |
f7f5542f KA |
11395 | |
11396 | fail: | |
11397 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) | |
11398 | vcpu->arch.tsc_offset -= vmcs12->tsc_offset; | |
11399 | leave_guest_mode(vcpu); | |
11400 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); | |
11401 | nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual); | |
11402 | return 1; | |
858e25c0 JM |
11403 | } |
11404 | ||
ca0bde28 JM |
11405 | /* |
11406 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
11407 | * for running an L2 nested guest. | |
11408 | */ | |
11409 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
11410 | { | |
11411 | struct vmcs12 *vmcs12; | |
11412 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
b3f1dfb6 | 11413 | u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); |
ca0bde28 JM |
11414 | u32 exit_qual; |
11415 | int ret; | |
11416 | ||
11417 | if (!nested_vmx_check_permission(vcpu)) | |
11418 | return 1; | |
11419 | ||
11420 | if (!nested_vmx_check_vmcs12(vcpu)) | |
11421 | goto out; | |
11422 | ||
11423 | vmcs12 = get_vmcs12(vcpu); | |
11424 | ||
11425 | if (enable_shadow_vmcs) | |
11426 | copy_shadow_to_vmcs12(vmx); | |
11427 | ||
11428 | /* | |
11429 | * The nested entry process starts with enforcing various prerequisites | |
11430 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
11431 | * they fail: As the SDM explains, some conditions should cause the | |
11432 | * instruction to fail, while others will cause the instruction to seem | |
11433 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
11434 | * To speed up the normal (success) code path, we should avoid checking | |
11435 | * for misconfigurations which will anyway be caught by the processor | |
11436 | * when using the merged vmcs02. | |
11437 | */ | |
b3f1dfb6 JM |
11438 | if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) { |
11439 | nested_vmx_failValid(vcpu, | |
11440 | VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); | |
11441 | goto out; | |
11442 | } | |
11443 | ||
ca0bde28 JM |
11444 | if (vmcs12->launch_state == launch) { |
11445 | nested_vmx_failValid(vcpu, | |
11446 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
11447 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
11448 | goto out; | |
11449 | } | |
11450 | ||
11451 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
11452 | if (ret) { | |
11453 | nested_vmx_failValid(vcpu, ret); | |
11454 | goto out; | |
11455 | } | |
11456 | ||
11457 | /* | |
11458 | * After this point, the trap flag no longer triggers a singlestep trap | |
11459 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
11460 | * This is not 100% correct; for performance reasons, we delegate most | |
11461 | * of the checks on host state to the processor. If those fail, | |
11462 | * the singlestep trap is missed. | |
11463 | */ | |
11464 | skip_emulated_instruction(vcpu); | |
11465 | ||
11466 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
11467 | if (ret) { | |
11468 | nested_vmx_entry_failure(vcpu, vmcs12, | |
11469 | EXIT_REASON_INVALID_STATE, exit_qual); | |
11470 | return 1; | |
384bb783 JK |
11471 | } |
11472 | ||
7c177938 NHE |
11473 | /* |
11474 | * We're finally done with prerequisite checking, and can start with | |
11475 | * the nested entry. | |
11476 | */ | |
11477 | ||
858e25c0 JM |
11478 | ret = enter_vmx_non_root_mode(vcpu, true); |
11479 | if (ret) | |
11480 | return ret; | |
ff651cb6 | 11481 | |
f0ace387 PB |
11482 | /* Hide L1D cache contents from the nested guest. */ |
11483 | vmx->vcpu.arch.l1tf_flush_l1d = true; | |
11484 | ||
076381c4 CG |
11485 | /* |
11486 | * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken | |
11487 | * by event injection, halt vcpu. | |
11488 | */ | |
11489 | if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) && | |
11490 | !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) | |
5cb56059 | 11491 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 11492 | |
7af40ad3 JK |
11493 | vmx->nested.nested_run_pending = 1; |
11494 | ||
cd232ad0 | 11495 | return 1; |
eb277562 KH |
11496 | |
11497 | out: | |
6affcbed | 11498 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
11499 | } |
11500 | ||
4704d0be NHE |
11501 | /* |
11502 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
11503 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
11504 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
11505 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
11506 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
11507 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
11508 | * didn't trap the bit, because if L1 did, so would L0). | |
11509 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
11510 | * been modified by L2, and L1 knows it. So just leave the old value of | |
11511 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
11512 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
11513 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
11514 | * changed these bits, and therefore they need to be updated, but L0 | |
11515 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
11516 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
11517 | */ | |
11518 | static inline unsigned long | |
11519 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11520 | { | |
11521 | return | |
11522 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
11523 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
11524 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
11525 | vcpu->arch.cr0_guest_owned_bits)); | |
11526 | } | |
11527 | ||
11528 | static inline unsigned long | |
11529 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11530 | { | |
11531 | return | |
11532 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
11533 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
11534 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
11535 | vcpu->arch.cr4_guest_owned_bits)); | |
11536 | } | |
11537 | ||
5f3d5799 JK |
11538 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
11539 | struct vmcs12 *vmcs12) | |
11540 | { | |
11541 | u32 idt_vectoring; | |
11542 | unsigned int nr; | |
11543 | ||
664f8e26 | 11544 | if (vcpu->arch.exception.injected) { |
5f3d5799 JK |
11545 | nr = vcpu->arch.exception.nr; |
11546 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11547 | ||
11548 | if (kvm_exception_is_soft(nr)) { | |
11549 | vmcs12->vm_exit_instruction_len = | |
11550 | vcpu->arch.event_exit_inst_len; | |
11551 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
11552 | } else | |
11553 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
11554 | ||
11555 | if (vcpu->arch.exception.has_error_code) { | |
11556 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
11557 | vmcs12->idt_vectoring_error_code = | |
11558 | vcpu->arch.exception.error_code; | |
11559 | } | |
11560 | ||
11561 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 11562 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
11563 | vmcs12->idt_vectoring_info_field = |
11564 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
11565 | } else if (vcpu->arch.interrupt.pending) { | |
11566 | nr = vcpu->arch.interrupt.nr; | |
11567 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11568 | ||
11569 | if (vcpu->arch.interrupt.soft) { | |
11570 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
11571 | vmcs12->vm_entry_instruction_len = | |
11572 | vcpu->arch.event_exit_inst_len; | |
11573 | } else | |
11574 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
11575 | ||
11576 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
11577 | } | |
11578 | } | |
11579 | ||
b6b8a145 JK |
11580 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
11581 | { | |
11582 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
bfcf83b1 | 11583 | unsigned long exit_qual; |
917dc606 LA |
11584 | bool block_nested_events = |
11585 | vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); | |
acc9ab60 | 11586 | |
bfcf83b1 WL |
11587 | if (vcpu->arch.exception.pending && |
11588 | nested_vmx_check_exception(vcpu, &exit_qual)) { | |
917dc606 | 11589 | if (block_nested_events) |
bfcf83b1 WL |
11590 | return -EBUSY; |
11591 | nested_vmx_inject_exception_vmexit(vcpu, exit_qual); | |
bfcf83b1 WL |
11592 | return 0; |
11593 | } | |
11594 | ||
f4124500 JK |
11595 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
11596 | vmx->nested.preemption_timer_expired) { | |
917dc606 | 11597 | if (block_nested_events) |
f4124500 JK |
11598 | return -EBUSY; |
11599 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
11600 | return 0; | |
11601 | } | |
11602 | ||
b6b8a145 | 11603 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
917dc606 | 11604 | if (block_nested_events) |
b6b8a145 JK |
11605 | return -EBUSY; |
11606 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
11607 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
11608 | INTR_INFO_VALID_MASK, 0); | |
11609 | /* | |
11610 | * The NMI-triggered VM exit counts as injection: | |
11611 | * clear this one and block further NMIs. | |
11612 | */ | |
11613 | vcpu->arch.nmi_pending = 0; | |
11614 | vmx_set_nmi_mask(vcpu, true); | |
11615 | return 0; | |
11616 | } | |
11617 | ||
11618 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
11619 | nested_exit_on_intr(vcpu)) { | |
917dc606 | 11620 | if (block_nested_events) |
b6b8a145 JK |
11621 | return -EBUSY; |
11622 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 11623 | return 0; |
b6b8a145 JK |
11624 | } |
11625 | ||
6342c50a DH |
11626 | vmx_complete_nested_posted_interrupt(vcpu); |
11627 | return 0; | |
b6b8a145 JK |
11628 | } |
11629 | ||
f4124500 JK |
11630 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
11631 | { | |
11632 | ktime_t remaining = | |
11633 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
11634 | u64 value; | |
11635 | ||
11636 | if (ktime_to_ns(remaining) <= 0) | |
11637 | return 0; | |
11638 | ||
11639 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
11640 | do_div(value, 1000000); | |
11641 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
11642 | } | |
11643 | ||
4704d0be | 11644 | /* |
cf8b84f4 JM |
11645 | * Update the guest state fields of vmcs12 to reflect changes that |
11646 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
11647 | * VM-entry controls is also updated, since this is really a guest | |
11648 | * state bit.) | |
4704d0be | 11649 | */ |
cf8b84f4 | 11650 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 11651 | { |
4704d0be NHE |
11652 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
11653 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
11654 | ||
4704d0be NHE |
11655 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
11656 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
11657 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
11658 | ||
11659 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
11660 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
11661 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
11662 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
11663 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
11664 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
11665 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
11666 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
11667 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
11668 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
11669 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
11670 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
11671 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
11672 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
11673 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
11674 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
11675 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
11676 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
11677 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
11678 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
11679 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
11680 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
11681 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
11682 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
11683 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
11684 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
11685 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
11686 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
11687 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
11688 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
11689 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
11690 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
11691 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
11692 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
11693 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
11694 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
11695 | ||
4704d0be NHE |
11696 | vmcs12->guest_interruptibility_info = |
11697 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
11698 | vmcs12->guest_pending_dbg_exceptions = | |
11699 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
11700 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11701 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
11702 | else | |
11703 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 11704 | |
f4124500 JK |
11705 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
11706 | if (vmcs12->vm_exit_controls & | |
11707 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
11708 | vmcs12->vmx_preemption_timer_value = | |
11709 | vmx_get_preemption_timer_value(vcpu); | |
11710 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
11711 | } | |
7854cbca | 11712 | |
3633cfc3 NHE |
11713 | /* |
11714 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
11715 | * own CR3 without exiting. If it has changed it, we must keep it. | |
11716 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
11717 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
11718 | * | |
11719 | * Additionally, restore L2's PDPTR to vmcs12. | |
11720 | */ | |
11721 | if (enable_ept) { | |
f3531054 | 11722 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
11723 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
11724 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
11725 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
11726 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
11727 | } | |
11728 | ||
d281e13b | 11729 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
119a9c01 | 11730 | |
608406e2 WV |
11731 | if (nested_cpu_has_vid(vmcs12)) |
11732 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
11733 | ||
c18911a2 JK |
11734 | vmcs12->vm_entry_controls = |
11735 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 11736 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 11737 | |
2996fca0 JK |
11738 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
11739 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
11740 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11741 | } | |
11742 | ||
4704d0be NHE |
11743 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
11744 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 11745 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 11746 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
11747 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
11748 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
11749 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
11750 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
11751 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 11752 | if (kvm_mpx_supported()) |
36be0b9d | 11753 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
cf8b84f4 JM |
11754 | } |
11755 | ||
11756 | /* | |
11757 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
11758 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
11759 | * and this function updates it to reflect the changes to the guest state while | |
11760 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
11761 | * without going back to L1), and to reflect the exit reason. | |
11762 | * Note that we do not have to copy here all VMCS fields, just those that | |
11763 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
11764 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
11765 | * which already writes to vmcs12 directly. | |
11766 | */ | |
11767 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11768 | u32 exit_reason, u32 exit_intr_info, | |
11769 | unsigned long exit_qualification) | |
11770 | { | |
11771 | /* update guest state fields: */ | |
11772 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
11773 | |
11774 | /* update exit information fields: */ | |
11775 | ||
533558bc JK |
11776 | vmcs12->vm_exit_reason = exit_reason; |
11777 | vmcs12->exit_qualification = exit_qualification; | |
533558bc | 11778 | vmcs12->vm_exit_intr_info = exit_intr_info; |
7313c698 | 11779 | |
5f3d5799 | 11780 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
11781 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
11782 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
11783 | ||
5f3d5799 | 11784 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
7cdc2d62 JM |
11785 | vmcs12->launch_state = 1; |
11786 | ||
5f3d5799 JK |
11787 | /* vm_entry_intr_info_field is cleared on exit. Emulate this |
11788 | * instead of reading the real value. */ | |
4704d0be | 11789 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
11790 | |
11791 | /* | |
11792 | * Transfer the event that L0 or L1 may wanted to inject into | |
11793 | * L2 to IDT_VECTORING_INFO_FIELD. | |
11794 | */ | |
11795 | vmcs12_save_pending_event(vcpu, vmcs12); | |
11796 | } | |
11797 | ||
11798 | /* | |
11799 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
11800 | * preserved above and would only end up incorrectly in L1. | |
11801 | */ | |
11802 | vcpu->arch.nmi_injected = false; | |
11803 | kvm_clear_exception_queue(vcpu); | |
11804 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
11805 | } |
11806 | ||
5af41573 WL |
11807 | static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu, |
11808 | struct vmcs12 *vmcs12) | |
11809 | { | |
11810 | u32 entry_failure_code; | |
11811 | ||
11812 | nested_ept_uninit_mmu_context(vcpu); | |
11813 | ||
11814 | /* | |
11815 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
11816 | * couldn't have changed. | |
11817 | */ | |
11818 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
11819 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
11820 | ||
11821 | if (!enable_ept) | |
11822 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
11823 | } | |
11824 | ||
4704d0be NHE |
11825 | /* |
11826 | * A part of what we need to when the nested L2 guest exits and we want to | |
11827 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
11828 | * in vmcs12. | |
11829 | * This function is to be called not only on normal nested exit, but also on | |
11830 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
11831 | * Failures During or After Loading Guest State"). | |
11832 | * This function should be called when the active VMCS is L1's (vmcs01). | |
11833 | */ | |
733568f9 JK |
11834 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
11835 | struct vmcs12 *vmcs12) | |
4704d0be | 11836 | { |
21feb4eb ACL |
11837 | struct kvm_segment seg; |
11838 | ||
4704d0be NHE |
11839 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
11840 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 11841 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
11842 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
11843 | else | |
11844 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11845 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11846 | ||
11847 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
11848 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 11849 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
11850 | /* |
11851 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
11852 | * actually changed, because vmx_set_cr0 refers to efer set above. |
11853 | * | |
11854 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
11855 | * (KVM doesn't change it); | |
4704d0be | 11856 | */ |
bd7e5b08 | 11857 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 11858 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 11859 | |
bd7e5b08 | 11860 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be | 11861 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
8eb3f87d | 11862 | vmx_set_cr4(vcpu, vmcs12->host_cr4); |
4704d0be | 11863 | |
5af41573 | 11864 | load_vmcs12_mmu_host_state(vcpu, vmcs12); |
feaf0c7d | 11865 | |
4704d0be NHE |
11866 | if (enable_vpid) { |
11867 | /* | |
11868 | * Trivially support vpid by letting L2s share their parent | |
11869 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
11870 | * each L2 its own vpid and exposing the vpid feature to L1. | |
11871 | */ | |
11872 | vmx_flush_tlb(vcpu); | |
11873 | } | |
06a5524f WV |
11874 | /* Restore posted intr vector. */ |
11875 | if (nested_cpu_has_posted_intr(vmcs12)) | |
11876 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); | |
4704d0be NHE |
11877 | |
11878 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
11879 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
11880 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
11881 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
11882 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
21f2d551 LP |
11883 | vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); |
11884 | vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); | |
4704d0be | 11885 | |
36be0b9d PB |
11886 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
11887 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
11888 | vmcs_write64(GUEST_BNDCFGS, 0); | |
11889 | ||
44811c02 | 11890 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 11891 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
11892 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
11893 | } | |
4704d0be NHE |
11894 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
11895 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
11896 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 11897 | |
21feb4eb ACL |
11898 | /* Set L1 segment info according to Intel SDM |
11899 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
11900 | seg = (struct kvm_segment) { | |
11901 | .base = 0, | |
11902 | .limit = 0xFFFFFFFF, | |
11903 | .selector = vmcs12->host_cs_selector, | |
11904 | .type = 11, | |
11905 | .present = 1, | |
11906 | .s = 1, | |
11907 | .g = 1 | |
11908 | }; | |
11909 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
11910 | seg.l = 1; | |
11911 | else | |
11912 | seg.db = 1; | |
11913 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
11914 | seg = (struct kvm_segment) { | |
11915 | .base = 0, | |
11916 | .limit = 0xFFFFFFFF, | |
11917 | .type = 3, | |
11918 | .present = 1, | |
11919 | .s = 1, | |
11920 | .db = 1, | |
11921 | .g = 1 | |
11922 | }; | |
11923 | seg.selector = vmcs12->host_ds_selector; | |
11924 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
11925 | seg.selector = vmcs12->host_es_selector; | |
11926 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
11927 | seg.selector = vmcs12->host_ss_selector; | |
11928 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
11929 | seg.selector = vmcs12->host_fs_selector; | |
11930 | seg.base = vmcs12->host_fs_base; | |
11931 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
11932 | seg.selector = vmcs12->host_gs_selector; | |
11933 | seg.base = vmcs12->host_gs_base; | |
11934 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
11935 | seg = (struct kvm_segment) { | |
205befd9 | 11936 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
11937 | .limit = 0x67, |
11938 | .selector = vmcs12->host_tr_selector, | |
11939 | .type = 11, | |
11940 | .present = 1 | |
11941 | }; | |
11942 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
11943 | ||
503cd0c5 JK |
11944 | kvm_set_dr(vcpu, 7, 0x400); |
11945 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 11946 | |
3af18d9c | 11947 | if (cpu_has_vmx_msr_bitmap()) |
4b0be90f | 11948 | vmx_update_msr_bitmap(vcpu); |
3af18d9c | 11949 | |
ff651cb6 WV |
11950 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
11951 | vmcs12->vm_exit_msr_load_count)) | |
11952 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
11953 | } |
11954 | ||
11955 | /* | |
11956 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
11957 | * and modify vmcs12 to make it see what it would expect to see there if | |
11958 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
11959 | */ | |
533558bc JK |
11960 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
11961 | u32 exit_intr_info, | |
11962 | unsigned long exit_qualification) | |
4704d0be NHE |
11963 | { |
11964 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
11965 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
11966 | ||
5f3d5799 JK |
11967 | /* trying to cancel vmlaunch/vmresume is a bug */ |
11968 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
11969 | ||
4f350c6d JM |
11970 | /* |
11971 | * The only expected VM-instruction error is "VM entry with | |
11972 | * invalid control field(s)." Anything else indicates a | |
11973 | * problem with L0. | |
11974 | */ | |
11975 | WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) != | |
11976 | VMXERR_ENTRY_INVALID_CONTROL_FIELD)); | |
11977 | ||
4704d0be | 11978 | leave_guest_mode(vcpu); |
4704d0be | 11979 | |
f7f5542f KA |
11980 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
11981 | vcpu->arch.tsc_offset -= vmcs12->tsc_offset; | |
11982 | ||
4f350c6d | 11983 | if (likely(!vmx->fail)) { |
72e9cbdb LP |
11984 | if (exit_reason == -1) |
11985 | sync_vmcs12(vcpu, vmcs12); | |
11986 | else | |
11987 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, | |
11988 | exit_qualification); | |
ff651cb6 | 11989 | |
4f350c6d JM |
11990 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
11991 | vmcs12->vm_exit_msr_store_count)) | |
11992 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
11993 | } | |
cf3215d9 | 11994 | |
1279a6b1 | 11995 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
8391ce44 PB |
11996 | vm_entry_controls_reset_shadow(vmx); |
11997 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
11998 | vmx_segment_cache_clear(vmx); |
11999 | ||
9314006d | 12000 | /* Update any VMCS fields that might have changed while L2 ran */ |
6e3dedb6 KRW |
12001 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); |
12002 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); | |
ea26e4ec | 12003 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
12004 | if (vmx->hv_deadline_tsc == -1) |
12005 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12006 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
12007 | else | |
12008 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12009 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
12010 | if (kvm_has_tsc_control) |
12011 | decache_tsc_multiplier(vmx); | |
4704d0be | 12012 | |
dccbfcf5 RK |
12013 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
12014 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
12015 | vmx_set_virtual_x2apic_mode(vcpu, | |
12016 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
fb6c8198 JM |
12017 | } else if (!nested_cpu_has_ept(vmcs12) && |
12018 | nested_cpu_has2(vmcs12, | |
12019 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
5ad2874a | 12020 | vmx_flush_tlb(vcpu); |
dccbfcf5 | 12021 | } |
4704d0be NHE |
12022 | |
12023 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
12024 | vmx->host_rsp = 0; | |
12025 | ||
12026 | /* Unpin physical memory we referred to in vmcs02 */ | |
12027 | if (vmx->nested.apic_access_page) { | |
53a70daf | 12028 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 12029 | vmx->nested.apic_access_page = NULL; |
4704d0be | 12030 | } |
a7c0b07d | 12031 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 12032 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 12033 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 12034 | } |
705699a1 WV |
12035 | if (vmx->nested.pi_desc_page) { |
12036 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 12037 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
12038 | vmx->nested.pi_desc_page = NULL; |
12039 | vmx->nested.pi_desc = NULL; | |
12040 | } | |
4704d0be | 12041 | |
38b99173 TC |
12042 | /* |
12043 | * We are now running in L2, mmu_notifier will force to reload the | |
12044 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
12045 | */ | |
c83b6d15 | 12046 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 12047 | |
72e9cbdb | 12048 | if (enable_shadow_vmcs && exit_reason != -1) |
012f83cb | 12049 | vmx->nested.sync_shadow_vmcs = true; |
b6b8a145 JK |
12050 | |
12051 | /* in case we halted in L2 */ | |
12052 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4f350c6d JM |
12053 | |
12054 | if (likely(!vmx->fail)) { | |
12055 | /* | |
12056 | * TODO: SDM says that with acknowledge interrupt on | |
12057 | * exit, bit 31 of the VM-exit interrupt information | |
12058 | * (valid interrupt) is always set to 1 on | |
12059 | * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't | |
12060 | * need kvm_cpu_has_interrupt(). See the commit | |
12061 | * message for details. | |
12062 | */ | |
12063 | if (nested_exit_intr_ack_set(vcpu) && | |
12064 | exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && | |
12065 | kvm_cpu_has_interrupt(vcpu)) { | |
12066 | int irq = kvm_cpu_get_interrupt(vcpu); | |
12067 | WARN_ON(irq < 0); | |
12068 | vmcs12->vm_exit_intr_info = irq | | |
12069 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
12070 | } | |
12071 | ||
72e9cbdb LP |
12072 | if (exit_reason != -1) |
12073 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, | |
12074 | vmcs12->exit_qualification, | |
12075 | vmcs12->idt_vectoring_info_field, | |
12076 | vmcs12->vm_exit_intr_info, | |
12077 | vmcs12->vm_exit_intr_error_code, | |
12078 | KVM_ISA_VMX); | |
4f350c6d JM |
12079 | |
12080 | load_vmcs12_host_state(vcpu, vmcs12); | |
12081 | ||
12082 | return; | |
12083 | } | |
12084 | ||
12085 | /* | |
12086 | * After an early L2 VM-entry failure, we're now back | |
12087 | * in L1 which thinks it just finished a VMLAUNCH or | |
12088 | * VMRESUME instruction, so we need to set the failure | |
12089 | * flag and the VM-instruction error field of the VMCS | |
12090 | * accordingly. | |
12091 | */ | |
12092 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
5af41573 WL |
12093 | |
12094 | load_vmcs12_mmu_host_state(vcpu, vmcs12); | |
12095 | ||
4f350c6d JM |
12096 | /* |
12097 | * The emulated instruction was already skipped in | |
12098 | * nested_vmx_run, but the updated RIP was never | |
12099 | * written back to the vmcs01. | |
12100 | */ | |
12101 | skip_emulated_instruction(vcpu); | |
12102 | vmx->fail = 0; | |
4704d0be NHE |
12103 | } |
12104 | ||
42124925 JK |
12105 | /* |
12106 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
12107 | */ | |
12108 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
12109 | { | |
2f707d97 WL |
12110 | if (is_guest_mode(vcpu)) { |
12111 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 12112 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 12113 | } |
42124925 JK |
12114 | free_nested(to_vmx(vcpu)); |
12115 | } | |
12116 | ||
7c177938 NHE |
12117 | /* |
12118 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
12119 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
12120 | * lists the acceptable exit-reason and exit-qualification parameters). | |
12121 | * It should only be called before L2 actually succeeded to run, and when | |
12122 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
12123 | */ | |
12124 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
12125 | struct vmcs12 *vmcs12, | |
12126 | u32 reason, unsigned long qualification) | |
12127 | { | |
12128 | load_vmcs12_host_state(vcpu, vmcs12); | |
12129 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
12130 | vmcs12->exit_qualification = qualification; | |
12131 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
12132 | if (enable_shadow_vmcs) |
12133 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
12134 | } |
12135 | ||
8a76d7f2 JR |
12136 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
12137 | struct x86_instruction_info *info, | |
12138 | enum x86_intercept_stage stage) | |
12139 | { | |
12140 | return X86EMUL_CONTINUE; | |
12141 | } | |
12142 | ||
64672c95 YJ |
12143 | #ifdef CONFIG_X86_64 |
12144 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
12145 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
12146 | u64 divisor, u64 *result) | |
12147 | { | |
12148 | u64 low = a << shift, high = a >> (64 - shift); | |
12149 | ||
12150 | /* To avoid the overflow on divq */ | |
12151 | if (high >= divisor) | |
12152 | return 1; | |
12153 | ||
12154 | /* Low hold the result, high hold rem which is discarded */ | |
12155 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
12156 | "rm" (divisor), "0" (low), "1" (high)); | |
12157 | *result = low; | |
12158 | ||
12159 | return 0; | |
12160 | } | |
12161 | ||
12162 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
12163 | { | |
12164 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
12165 | u64 tscl = rdtsc(); |
12166 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
12167 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
12168 | |
12169 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
12170 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
12171 | u64_shl_div_u64(delta_tsc, | |
12172 | kvm_tsc_scaling_ratio_frac_bits, | |
12173 | vcpu->arch.tsc_scaling_ratio, | |
12174 | &delta_tsc)) | |
12175 | return -ERANGE; | |
12176 | ||
12177 | /* | |
12178 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
12179 | * we can't use the preemption timer. | |
12180 | * It's possible that it fits on later vmentries, but checking | |
12181 | * on every vmentry is costly so we just use an hrtimer. | |
12182 | */ | |
12183 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
12184 | return -ERANGE; | |
12185 | ||
12186 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
12187 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12188 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c8533544 WL |
12189 | |
12190 | return delta_tsc == 0; | |
64672c95 YJ |
12191 | } |
12192 | ||
12193 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
12194 | { | |
12195 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12196 | vmx->hv_deadline_tsc = -1; | |
12197 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12198 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
12199 | } | |
12200 | #endif | |
12201 | ||
48d89b92 | 12202 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 12203 | { |
b4a2d31d RK |
12204 | if (ple_gap) |
12205 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
12206 | } |
12207 | ||
843e4330 KH |
12208 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
12209 | struct kvm_memory_slot *slot) | |
12210 | { | |
12211 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
12212 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
12213 | } | |
12214 | ||
12215 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
12216 | struct kvm_memory_slot *slot) | |
12217 | { | |
12218 | kvm_mmu_slot_set_dirty(kvm, slot); | |
12219 | } | |
12220 | ||
12221 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
12222 | { | |
12223 | kvm_flush_pml_buffers(kvm); | |
12224 | } | |
12225 | ||
c5f983f6 BD |
12226 | static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) |
12227 | { | |
12228 | struct vmcs12 *vmcs12; | |
12229 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12230 | gpa_t gpa; | |
12231 | struct page *page = NULL; | |
12232 | u64 *pml_address; | |
12233 | ||
12234 | if (is_guest_mode(vcpu)) { | |
12235 | WARN_ON_ONCE(vmx->nested.pml_full); | |
12236 | ||
12237 | /* | |
12238 | * Check if PML is enabled for the nested guest. | |
12239 | * Whether eptp bit 6 is set is already checked | |
12240 | * as part of A/D emulation. | |
12241 | */ | |
12242 | vmcs12 = get_vmcs12(vcpu); | |
12243 | if (!nested_cpu_has_pml(vmcs12)) | |
12244 | return 0; | |
12245 | ||
4769886b | 12246 | if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { |
c5f983f6 BD |
12247 | vmx->nested.pml_full = true; |
12248 | return 1; | |
12249 | } | |
12250 | ||
12251 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; | |
12252 | ||
5e2f30b7 DH |
12253 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); |
12254 | if (is_error_page(page)) | |
c5f983f6 BD |
12255 | return 0; |
12256 | ||
12257 | pml_address = kmap(page); | |
12258 | pml_address[vmcs12->guest_pml_index--] = gpa; | |
12259 | kunmap(page); | |
53a70daf | 12260 | kvm_release_page_clean(page); |
c5f983f6 BD |
12261 | } |
12262 | ||
12263 | return 0; | |
12264 | } | |
12265 | ||
843e4330 KH |
12266 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, |
12267 | struct kvm_memory_slot *memslot, | |
12268 | gfn_t offset, unsigned long mask) | |
12269 | { | |
12270 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
12271 | } | |
12272 | ||
cd39e117 PB |
12273 | static void __pi_post_block(struct kvm_vcpu *vcpu) |
12274 | { | |
12275 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
12276 | struct pi_desc old, new; | |
12277 | unsigned int dest; | |
cd39e117 PB |
12278 | |
12279 | do { | |
12280 | old.control = new.control = pi_desc->control; | |
8b306e2f PB |
12281 | WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, |
12282 | "Wakeup handler not enabled while the VCPU is blocked\n"); | |
cd39e117 PB |
12283 | |
12284 | dest = cpu_physical_id(vcpu->cpu); | |
12285 | ||
12286 | if (x2apic_enabled()) | |
12287 | new.ndst = dest; | |
12288 | else | |
12289 | new.ndst = (dest << 8) & 0xFF00; | |
12290 | ||
cd39e117 PB |
12291 | /* set 'NV' to 'notification vector' */ |
12292 | new.nv = POSTED_INTR_VECTOR; | |
c0a1666b PB |
12293 | } while (cmpxchg64(&pi_desc->control, old.control, |
12294 | new.control) != old.control); | |
cd39e117 | 12295 | |
8b306e2f PB |
12296 | if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { |
12297 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
cd39e117 | 12298 | list_del(&vcpu->blocked_vcpu_list); |
8b306e2f | 12299 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); |
cd39e117 PB |
12300 | vcpu->pre_pcpu = -1; |
12301 | } | |
12302 | } | |
12303 | ||
bf9f6ac8 FW |
12304 | /* |
12305 | * This routine does the following things for vCPU which is going | |
12306 | * to be blocked if VT-d PI is enabled. | |
12307 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
12308 | * we can find the right vCPU to wake up. | |
12309 | * - Change the Posted-interrupt descriptor as below: | |
12310 | * 'NDST' <-- vcpu->pre_pcpu | |
12311 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
12312 | * - If 'ON' is set during this process, which means at least one | |
12313 | * interrupt is posted for this vCPU, we cannot block it, in | |
12314 | * this case, return 1, otherwise, return 0. | |
12315 | * | |
12316 | */ | |
bc22512b | 12317 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 | 12318 | { |
bf9f6ac8 FW |
12319 | unsigned int dest; |
12320 | struct pi_desc old, new; | |
12321 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
12322 | ||
12323 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
12324 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
12325 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
12326 | return 0; |
12327 | ||
8b306e2f PB |
12328 | WARN_ON(irqs_disabled()); |
12329 | local_irq_disable(); | |
12330 | if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { | |
12331 | vcpu->pre_pcpu = vcpu->cpu; | |
12332 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
12333 | list_add_tail(&vcpu->blocked_vcpu_list, | |
12334 | &per_cpu(blocked_vcpu_on_cpu, | |
12335 | vcpu->pre_pcpu)); | |
12336 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
12337 | } | |
bf9f6ac8 FW |
12338 | |
12339 | do { | |
12340 | old.control = new.control = pi_desc->control; | |
12341 | ||
bf9f6ac8 FW |
12342 | WARN((pi_desc->sn == 1), |
12343 | "Warning: SN field of posted-interrupts " | |
12344 | "is set before blocking\n"); | |
12345 | ||
12346 | /* | |
12347 | * Since vCPU can be preempted during this process, | |
12348 | * vcpu->cpu could be different with pre_pcpu, we | |
12349 | * need to set pre_pcpu as the destination of wakeup | |
12350 | * notification event, then we can find the right vCPU | |
12351 | * to wakeup in wakeup handler if interrupts happen | |
12352 | * when the vCPU is in blocked state. | |
12353 | */ | |
12354 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
12355 | ||
12356 | if (x2apic_enabled()) | |
12357 | new.ndst = dest; | |
12358 | else | |
12359 | new.ndst = (dest << 8) & 0xFF00; | |
12360 | ||
12361 | /* set 'NV' to 'wakeup vector' */ | |
12362 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
c0a1666b PB |
12363 | } while (cmpxchg64(&pi_desc->control, old.control, |
12364 | new.control) != old.control); | |
bf9f6ac8 | 12365 | |
8b306e2f PB |
12366 | /* We should not block the vCPU if an interrupt is posted for it. */ |
12367 | if (pi_test_on(pi_desc) == 1) | |
12368 | __pi_post_block(vcpu); | |
12369 | ||
12370 | local_irq_enable(); | |
12371 | return (vcpu->pre_pcpu == -1); | |
bf9f6ac8 FW |
12372 | } |
12373 | ||
bc22512b YJ |
12374 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
12375 | { | |
12376 | if (pi_pre_block(vcpu)) | |
12377 | return 1; | |
12378 | ||
64672c95 YJ |
12379 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
12380 | kvm_lapic_switch_to_sw_timer(vcpu); | |
12381 | ||
bc22512b YJ |
12382 | return 0; |
12383 | } | |
12384 | ||
12385 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 | 12386 | { |
8b306e2f | 12387 | if (vcpu->pre_pcpu == -1) |
bf9f6ac8 FW |
12388 | return; |
12389 | ||
8b306e2f PB |
12390 | WARN_ON(irqs_disabled()); |
12391 | local_irq_disable(); | |
cd39e117 | 12392 | __pi_post_block(vcpu); |
8b306e2f | 12393 | local_irq_enable(); |
bf9f6ac8 FW |
12394 | } |
12395 | ||
bc22512b YJ |
12396 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
12397 | { | |
64672c95 YJ |
12398 | if (kvm_x86_ops->set_hv_timer) |
12399 | kvm_lapic_switch_to_hv_timer(vcpu); | |
12400 | ||
bc22512b YJ |
12401 | pi_post_block(vcpu); |
12402 | } | |
12403 | ||
efc64404 FW |
12404 | /* |
12405 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
12406 | * | |
12407 | * @kvm: kvm | |
12408 | * @host_irq: host irq of the interrupt | |
12409 | * @guest_irq: gsi of the interrupt | |
12410 | * @set: set or unset PI | |
12411 | * returns 0 on success, < 0 on failure | |
12412 | */ | |
12413 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
12414 | uint32_t guest_irq, bool set) | |
12415 | { | |
12416 | struct kvm_kernel_irq_routing_entry *e; | |
12417 | struct kvm_irq_routing_table *irq_rt; | |
12418 | struct kvm_lapic_irq irq; | |
12419 | struct kvm_vcpu *vcpu; | |
12420 | struct vcpu_data vcpu_info; | |
3a8b0677 | 12421 | int idx, ret = 0; |
efc64404 FW |
12422 | |
12423 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
12424 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
12425 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
12426 | return 0; |
12427 | ||
12428 | idx = srcu_read_lock(&kvm->irq_srcu); | |
12429 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
3a8b0677 JS |
12430 | if (guest_irq >= irq_rt->nr_rt_entries || |
12431 | hlist_empty(&irq_rt->map[guest_irq])) { | |
12432 | pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", | |
12433 | guest_irq, irq_rt->nr_rt_entries); | |
12434 | goto out; | |
12435 | } | |
efc64404 FW |
12436 | |
12437 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
12438 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
12439 | continue; | |
12440 | /* | |
12441 | * VT-d PI cannot support posting multicast/broadcast | |
12442 | * interrupts to a vCPU, we still use interrupt remapping | |
12443 | * for these kind of interrupts. | |
12444 | * | |
12445 | * For lowest-priority interrupts, we only support | |
12446 | * those with single CPU as the destination, e.g. user | |
12447 | * configures the interrupts via /proc/irq or uses | |
12448 | * irqbalance to make the interrupts single-CPU. | |
12449 | * | |
12450 | * We will support full lowest-priority interrupt later. | |
12451 | */ | |
12452 | ||
37131313 | 12453 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
12454 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
12455 | /* | |
12456 | * Make sure the IRTE is in remapped mode if | |
12457 | * we don't handle it in posted mode. | |
12458 | */ | |
12459 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
12460 | if (ret < 0) { | |
12461 | printk(KERN_INFO | |
12462 | "failed to back to remapped mode, irq: %u\n", | |
12463 | host_irq); | |
12464 | goto out; | |
12465 | } | |
12466 | ||
efc64404 | 12467 | continue; |
23a1c257 | 12468 | } |
efc64404 FW |
12469 | |
12470 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
12471 | vcpu_info.vector = irq.vector; | |
12472 | ||
4edf01c6 | 12473 | trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, |
efc64404 FW |
12474 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
12475 | ||
12476 | if (set) | |
12477 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
dc91f2eb | 12478 | else |
efc64404 | 12479 | ret = irq_set_vcpu_affinity(host_irq, NULL); |
efc64404 FW |
12480 | |
12481 | if (ret < 0) { | |
12482 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
12483 | __func__); | |
12484 | goto out; | |
12485 | } | |
12486 | } | |
12487 | ||
12488 | ret = 0; | |
12489 | out: | |
12490 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
12491 | return ret; | |
12492 | } | |
12493 | ||
c45dcc71 AR |
12494 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
12495 | { | |
12496 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
12497 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
12498 | FEATURE_CONTROL_LMCE; | |
12499 | else | |
12500 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
12501 | ~FEATURE_CONTROL_LMCE; | |
12502 | } | |
12503 | ||
72d7b374 LP |
12504 | static int vmx_smi_allowed(struct kvm_vcpu *vcpu) |
12505 | { | |
72e9cbdb LP |
12506 | /* we need a nested vmexit to enter SMM, postpone if run is pending */ |
12507 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
12508 | return 0; | |
72d7b374 LP |
12509 | return 1; |
12510 | } | |
12511 | ||
0234bf88 LP |
12512 | static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
12513 | { | |
72e9cbdb LP |
12514 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12515 | ||
12516 | vmx->nested.smm.guest_mode = is_guest_mode(vcpu); | |
12517 | if (vmx->nested.smm.guest_mode) | |
12518 | nested_vmx_vmexit(vcpu, -1, 0, 0); | |
12519 | ||
12520 | vmx->nested.smm.vmxon = vmx->nested.vmxon; | |
12521 | vmx->nested.vmxon = false; | |
0234bf88 LP |
12522 | return 0; |
12523 | } | |
12524 | ||
12525 | static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
12526 | { | |
72e9cbdb LP |
12527 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12528 | int ret; | |
12529 | ||
12530 | if (vmx->nested.smm.vmxon) { | |
12531 | vmx->nested.vmxon = true; | |
12532 | vmx->nested.smm.vmxon = false; | |
12533 | } | |
12534 | ||
12535 | if (vmx->nested.smm.guest_mode) { | |
12536 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
12537 | ret = enter_vmx_non_root_mode(vcpu, false); | |
12538 | vcpu->arch.hflags |= HF_SMM_MASK; | |
12539 | if (ret) | |
12540 | return ret; | |
12541 | ||
12542 | vmx->nested.smm.guest_mode = false; | |
12543 | } | |
0234bf88 LP |
12544 | return 0; |
12545 | } | |
12546 | ||
cc3d967f LP |
12547 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
12548 | { | |
12549 | return 0; | |
12550 | } | |
12551 | ||
404f6aac | 12552 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
12553 | .cpu_has_kvm_support = cpu_has_kvm_support, |
12554 | .disabled_by_bios = vmx_disabled_by_bios, | |
12555 | .hardware_setup = hardware_setup, | |
12556 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 12557 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
12558 | .hardware_enable = hardware_enable, |
12559 | .hardware_disable = hardware_disable, | |
04547156 | 12560 | .cpu_has_accelerated_tpr = report_flexpriority, |
4d5c8a07 | 12561 | .has_emulated_msr = vmx_has_emulated_msr, |
6aa8b732 | 12562 | |
275b72a9 KRW |
12563 | .vm_init = vmx_vm_init, |
12564 | ||
6aa8b732 AK |
12565 | .vcpu_create = vmx_create_vcpu, |
12566 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 12567 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 12568 | |
04d2cc77 | 12569 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
12570 | .vcpu_load = vmx_vcpu_load, |
12571 | .vcpu_put = vmx_vcpu_put, | |
12572 | ||
a96036b8 | 12573 | .update_bp_intercept = update_exception_bitmap, |
ab1bebf8 | 12574 | .get_msr_feature = vmx_get_msr_feature, |
6aa8b732 AK |
12575 | .get_msr = vmx_get_msr, |
12576 | .set_msr = vmx_set_msr, | |
12577 | .get_segment_base = vmx_get_segment_base, | |
12578 | .get_segment = vmx_get_segment, | |
12579 | .set_segment = vmx_set_segment, | |
2e4d2653 | 12580 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 12581 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 12582 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 12583 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 12584 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 12585 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
12586 | .set_cr3 = vmx_set_cr3, |
12587 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 12588 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
12589 | .get_idt = vmx_get_idt, |
12590 | .set_idt = vmx_set_idt, | |
12591 | .get_gdt = vmx_get_gdt, | |
12592 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
12593 | .get_dr6 = vmx_get_dr6, |
12594 | .set_dr6 = vmx_set_dr6, | |
020df079 | 12595 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 12596 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 12597 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
12598 | .get_rflags = vmx_get_rflags, |
12599 | .set_rflags = vmx_set_rflags, | |
be94f6b7 | 12600 | |
6aa8b732 | 12601 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 12602 | |
6aa8b732 | 12603 | .run = vmx_vcpu_run, |
6062d012 | 12604 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 12605 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
12606 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
12607 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 12608 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 12609 | .set_irq = vmx_inject_irq, |
95ba8273 | 12610 | .set_nmi = vmx_inject_nmi, |
298101da | 12611 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 12612 | .cancel_injection = vmx_cancel_injection, |
78646121 | 12613 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 12614 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
12615 | .get_nmi_mask = vmx_get_nmi_mask, |
12616 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
12617 | .enable_nmi_window = enable_nmi_window, |
12618 | .enable_irq_window = enable_irq_window, | |
12619 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 12620 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 12621 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
12622 | .get_enable_apicv = vmx_get_enable_apicv, |
12623 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 12624 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 12625 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
12626 | .hwapic_irr_update = vmx_hwapic_irr_update, |
12627 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
12628 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
12629 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 12630 | |
cbc94022 | 12631 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 12632 | .get_tdp_level = get_ept_level, |
4b12f0de | 12633 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 12634 | |
586f9607 | 12635 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 12636 | |
17cc3935 | 12637 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
12638 | |
12639 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
12640 | |
12641 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 12642 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
12643 | |
12644 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
12645 | |
12646 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 12647 | |
f7f5542f | 12648 | .read_l1_tsc_offset = vmx_read_l1_tsc_offset, |
99e3e30a | 12649 | .write_tsc_offset = vmx_write_tsc_offset, |
1c97f0a0 JR |
12650 | |
12651 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
12652 | |
12653 | .check_intercept = vmx_check_intercept, | |
a547c6db | 12654 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 12655 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 12656 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
12657 | |
12658 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
12659 | |
12660 | .sched_in = vmx_sched_in, | |
843e4330 KH |
12661 | |
12662 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
12663 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
12664 | .flush_log_dirty = vmx_flush_log_dirty, | |
12665 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
c5f983f6 | 12666 | .write_log_dirty = vmx_write_pml_buffer, |
25462f7f | 12667 | |
bf9f6ac8 FW |
12668 | .pre_block = vmx_pre_block, |
12669 | .post_block = vmx_post_block, | |
12670 | ||
25462f7f | 12671 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
12672 | |
12673 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
12674 | |
12675 | #ifdef CONFIG_X86_64 | |
12676 | .set_hv_timer = vmx_set_hv_timer, | |
12677 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
12678 | #endif | |
c45dcc71 AR |
12679 | |
12680 | .setup_mce = vmx_setup_mce, | |
0234bf88 | 12681 | |
72d7b374 | 12682 | .smi_allowed = vmx_smi_allowed, |
0234bf88 LP |
12683 | .pre_enter_smm = vmx_pre_enter_smm, |
12684 | .pre_leave_smm = vmx_pre_leave_smm, | |
cc3d967f | 12685 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
12686 | }; |
12687 | ||
b9cfedcd | 12688 | static void vmx_cleanup_l1d_flush(void) |
d665f9fc PB |
12689 | { |
12690 | if (vmx_l1d_flush_pages) { | |
12691 | free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); | |
12692 | vmx_l1d_flush_pages = NULL; | |
12693 | } | |
b9cfedcd TG |
12694 | /* Restore state so sysfs ignores VMX */ |
12695 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; | |
1749555e KRW |
12696 | } |
12697 | ||
1ead4979 TG |
12698 | static void vmx_exit(void) |
12699 | { | |
12700 | #ifdef CONFIG_KEXEC_CORE | |
12701 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); | |
12702 | synchronize_rcu(); | |
12703 | #endif | |
12704 | ||
12705 | kvm_exit(); | |
12706 | ||
12707 | vmx_cleanup_l1d_flush(); | |
12708 | } | |
12709 | module_exit(vmx_exit) | |
12710 | ||
6aa8b732 AK |
12711 | static int __init vmx_init(void) |
12712 | { | |
1749555e KRW |
12713 | int r; |
12714 | ||
1ead4979 TG |
12715 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
12716 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
d665f9fc PB |
12717 | if (r) |
12718 | return r; | |
1749555e | 12719 | |
1ead4979 | 12720 | /* |
2bcd5b01 TG |
12721 | * Must be called after kvm_init() so enable_ept is properly set |
12722 | * up. Hand the parameter mitigation value in which was stored in | |
12723 | * the pre module init parser. If no parameter was given, it will | |
12724 | * contain 'auto' which will be turned into the default 'cond' | |
12725 | * mitigation mode. | |
1ead4979 | 12726 | */ |
2bcd5b01 TG |
12727 | if (boot_cpu_has(X86_BUG_L1TF)) { |
12728 | r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); | |
12729 | if (r) { | |
12730 | vmx_exit(); | |
12731 | return r; | |
12732 | } | |
d665f9fc | 12733 | } |
25c5f225 | 12734 | |
2965faa5 | 12735 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
12736 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
12737 | crash_vmclear_local_loaded_vmcss); | |
12738 | #endif | |
12739 | ||
fdef3ad1 | 12740 | return 0; |
6aa8b732 | 12741 | } |
6aa8b732 | 12742 | module_init(vmx_init) |