]>
Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba MW |
30 | #include <linux/kernel.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/pci.h> | |
be7b6275 | 35 | #include <linux/poison.h> |
c3bfe717 | 36 | #include <linux/ptrace.h> |
b60503ba MW |
37 | #include <linux/sched.h> |
38 | #include <linux/slab.h> | |
e1e5e564 | 39 | #include <linux/t10-pi.h> |
b60503ba | 40 | #include <linux/types.h> |
1d277a63 | 41 | #include <linux/pr.h> |
5d0f6131 | 42 | #include <scsi/sg.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
9d99a8dd | 46 | #include <uapi/linux/nvme_ioctl.h> |
f11bb3e2 CH |
47 | #include "nvme.h" |
48 | ||
b3fffdef | 49 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 50 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 51 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
52 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
53 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 54 | |
21d34711 | 55 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
56 | module_param(admin_timeout, byte, 0644); |
57 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 58 | |
bd67608a MW |
59 | unsigned char nvme_io_timeout = 30; |
60 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 61 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 62 | |
5fd4ce1b | 63 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
64 | module_param(shutdown_timeout, byte, 0644); |
65 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
66 | ||
b3fffdef KB |
67 | static int nvme_char_major; |
68 | module_param(nvme_char_major, int, 0); | |
69 | ||
58ffacb5 MW |
70 | static int use_threaded_interrupts; |
71 | module_param(use_threaded_interrupts, int, 0); | |
72 | ||
8ffaadf7 JD |
73 | static bool use_cmb_sqes = true; |
74 | module_param(use_cmb_sqes, bool, 0644); | |
75 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
76 | ||
1fa6aead MW |
77 | static LIST_HEAD(dev_list); |
78 | static struct task_struct *nvme_thread; | |
9a6b9458 | 79 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 80 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 81 | |
b3fffdef KB |
82 | static struct class *nvme_class; |
83 | ||
1c63dc66 CH |
84 | struct nvme_dev; |
85 | struct nvme_queue; | |
d4f6c3ab | 86 | struct nvme_iod; |
1c63dc66 | 87 | |
90667892 | 88 | static int __nvme_reset(struct nvme_dev *dev); |
4cc06521 | 89 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 90 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
d4f6c3ab | 91 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); |
3cf519b5 | 92 | static void nvme_dead_ctrl(struct nvme_dev *dev); |
d4b4ff8e | 93 | |
4d115420 KB |
94 | struct async_cmd_info { |
95 | struct kthread_work work; | |
96 | struct kthread_worker *worker; | |
a4aea562 | 97 | struct request *req; |
4d115420 KB |
98 | u32 result; |
99 | int status; | |
100 | void *ctx; | |
101 | }; | |
1fa6aead | 102 | |
1c63dc66 CH |
103 | /* |
104 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
105 | */ | |
106 | struct nvme_dev { | |
107 | struct list_head node; | |
108 | struct nvme_queue **queues; | |
109 | struct blk_mq_tag_set tagset; | |
110 | struct blk_mq_tag_set admin_tagset; | |
111 | u32 __iomem *dbs; | |
112 | struct device *dev; | |
113 | struct dma_pool *prp_page_pool; | |
114 | struct dma_pool *prp_small_pool; | |
115 | unsigned queue_count; | |
116 | unsigned online_queues; | |
117 | unsigned max_qid; | |
118 | int q_depth; | |
119 | u32 db_stride; | |
1c63dc66 CH |
120 | struct msix_entry *entry; |
121 | void __iomem *bar; | |
1c63dc66 CH |
122 | struct work_struct reset_work; |
123 | struct work_struct probe_work; | |
124 | struct work_struct scan_work; | |
125 | bool subsystem; | |
1c63dc66 CH |
126 | void __iomem *cmb; |
127 | dma_addr_t cmb_dma_addr; | |
128 | u64 cmb_size; | |
129 | u32 cmbsz; | |
130 | ||
131 | struct nvme_ctrl ctrl; | |
132 | }; | |
133 | ||
134 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
135 | { | |
136 | return container_of(ctrl, struct nvme_dev, ctrl); | |
137 | } | |
138 | ||
b60503ba MW |
139 | /* |
140 | * An NVM Express queue. Each device has at least two (one for admin | |
141 | * commands and one for I/O commands). | |
142 | */ | |
143 | struct nvme_queue { | |
144 | struct device *q_dmadev; | |
091b6092 | 145 | struct nvme_dev *dev; |
3193f07b | 146 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
147 | spinlock_t q_lock; |
148 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 149 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 150 | volatile struct nvme_completion *cqes; |
42483228 | 151 | struct blk_mq_tags **tags; |
b60503ba MW |
152 | dma_addr_t sq_dma_addr; |
153 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
154 | u32 __iomem *q_db; |
155 | u16 q_depth; | |
6222d172 | 156 | s16 cq_vector; |
b60503ba MW |
157 | u16 sq_head; |
158 | u16 sq_tail; | |
159 | u16 cq_head; | |
c30341dc | 160 | u16 qid; |
e9539f47 MW |
161 | u8 cq_phase; |
162 | u8 cqe_seen; | |
4d115420 | 163 | struct async_cmd_info cmdinfo; |
b60503ba MW |
164 | }; |
165 | ||
71bd150c CH |
166 | /* |
167 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
168 | * entries. You can't see it in this data structure because C doesn't let | |
169 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
170 | * allocated to store the PRP list. | |
171 | */ | |
172 | struct nvme_iod { | |
173 | unsigned long private; /* For the use of the submitter of the I/O */ | |
174 | int npages; /* In the PRP list. 0 means small pool in use */ | |
175 | int offset; /* Of PRP list */ | |
176 | int nents; /* Used in scatterlist */ | |
177 | int length; /* Of data, in bytes */ | |
178 | dma_addr_t first_dma; | |
179 | struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ | |
180 | struct scatterlist sg[0]; | |
181 | }; | |
182 | ||
b60503ba MW |
183 | /* |
184 | * Check we didin't inadvertently grow the command struct | |
185 | */ | |
186 | static inline void _nvme_check_size(void) | |
187 | { | |
188 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
191 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
192 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 193 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 194 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
195 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
196 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
197 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
198 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 199 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
200 | } |
201 | ||
edd10d33 | 202 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
203 | struct nvme_completion *); |
204 | ||
e85248e5 | 205 | struct nvme_cmd_info { |
c2f5b650 MW |
206 | nvme_completion_fn fn; |
207 | void *ctx; | |
c30341dc | 208 | int aborted; |
a4aea562 | 209 | struct nvme_queue *nvmeq; |
ac3dd5bd | 210 | struct nvme_iod iod[0]; |
e85248e5 MW |
211 | }; |
212 | ||
ac3dd5bd JA |
213 | /* |
214 | * Max size of iod being embedded in the request payload | |
215 | */ | |
216 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 217 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
fda631ff | 218 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
219 | |
220 | /* | |
221 | * Will slightly overestimate the number of pages needed. This is OK | |
222 | * as it only leads to a small amount of wasted memory for the lifetime of | |
223 | * the I/O. | |
224 | */ | |
225 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
226 | { | |
5fd4ce1b CH |
227 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
228 | dev->ctrl.page_size); | |
ac3dd5bd JA |
229 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
230 | } | |
231 | ||
232 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
233 | { | |
234 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
235 | ||
236 | ret += sizeof(struct nvme_iod); | |
237 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
238 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
a4aea562 MB |
243 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
244 | unsigned int hctx_idx) | |
e85248e5 | 245 | { |
a4aea562 MB |
246 | struct nvme_dev *dev = data; |
247 | struct nvme_queue *nvmeq = dev->queues[0]; | |
248 | ||
42483228 KB |
249 | WARN_ON(hctx_idx != 0); |
250 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
251 | WARN_ON(nvmeq->tags); | |
252 | ||
a4aea562 | 253 | hctx->driver_data = nvmeq; |
42483228 | 254 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 255 | return 0; |
e85248e5 MW |
256 | } |
257 | ||
4af0e21c KB |
258 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
259 | { | |
260 | struct nvme_queue *nvmeq = hctx->driver_data; | |
261 | ||
262 | nvmeq->tags = NULL; | |
263 | } | |
264 | ||
a4aea562 MB |
265 | static int nvme_admin_init_request(void *data, struct request *req, |
266 | unsigned int hctx_idx, unsigned int rq_idx, | |
267 | unsigned int numa_node) | |
22404274 | 268 | { |
a4aea562 MB |
269 | struct nvme_dev *dev = data; |
270 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
271 | struct nvme_queue *nvmeq = dev->queues[0]; | |
272 | ||
273 | BUG_ON(!nvmeq); | |
274 | cmd->nvmeq = nvmeq; | |
275 | return 0; | |
22404274 KB |
276 | } |
277 | ||
a4aea562 MB |
278 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
279 | unsigned int hctx_idx) | |
b60503ba | 280 | { |
a4aea562 | 281 | struct nvme_dev *dev = data; |
42483228 | 282 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 283 | |
42483228 KB |
284 | if (!nvmeq->tags) |
285 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 286 | |
42483228 | 287 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
288 | hctx->driver_data = nvmeq; |
289 | return 0; | |
b60503ba MW |
290 | } |
291 | ||
a4aea562 MB |
292 | static int nvme_init_request(void *data, struct request *req, |
293 | unsigned int hctx_idx, unsigned int rq_idx, | |
294 | unsigned int numa_node) | |
b60503ba | 295 | { |
a4aea562 MB |
296 | struct nvme_dev *dev = data; |
297 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
298 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
299 | ||
300 | BUG_ON(!nvmeq); | |
301 | cmd->nvmeq = nvmeq; | |
302 | return 0; | |
303 | } | |
304 | ||
305 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
306 | nvme_completion_fn handler) | |
307 | { | |
308 | cmd->fn = handler; | |
309 | cmd->ctx = ctx; | |
310 | cmd->aborted = 0; | |
c917dfe5 | 311 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
312 | } |
313 | ||
ac3dd5bd JA |
314 | static void *iod_get_private(struct nvme_iod *iod) |
315 | { | |
316 | return (void *) (iod->private & ~0x1UL); | |
317 | } | |
318 | ||
319 | /* | |
320 | * If bit 0 is set, the iod is embedded in the request payload. | |
321 | */ | |
322 | static bool iod_should_kfree(struct nvme_iod *iod) | |
323 | { | |
fda631ff | 324 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
325 | } |
326 | ||
c2f5b650 MW |
327 | /* Special values must be less than 0x1000 */ |
328 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
329 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
330 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
331 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 332 | |
edd10d33 | 333 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
334 | struct nvme_completion *cqe) |
335 | { | |
336 | if (ctx == CMD_CTX_CANCELLED) | |
337 | return; | |
c2f5b650 | 338 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 339 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
340 | "completed id %d twice on queue %d\n", |
341 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
342 | return; | |
343 | } | |
344 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 345 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
346 | "invalid id %d completed on queue %d\n", |
347 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
348 | return; | |
349 | } | |
edd10d33 | 350 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
351 | } |
352 | ||
a4aea562 | 353 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 354 | { |
c2f5b650 | 355 | void *ctx; |
b60503ba | 356 | |
859361a2 | 357 | if (fn) |
a4aea562 MB |
358 | *fn = cmd->fn; |
359 | ctx = cmd->ctx; | |
360 | cmd->fn = special_completion; | |
361 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 362 | return ctx; |
b60503ba MW |
363 | } |
364 | ||
a4aea562 MB |
365 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
366 | struct nvme_completion *cqe) | |
3c0cf138 | 367 | { |
a4aea562 MB |
368 | u32 result = le32_to_cpup(&cqe->result); |
369 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
370 | ||
371 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
1c63dc66 | 372 | ++nvmeq->dev->ctrl.event_limit; |
a5768aa8 KB |
373 | if (status != NVME_SC_SUCCESS) |
374 | return; | |
375 | ||
376 | switch (result & 0xff07) { | |
377 | case NVME_AER_NOTICE_NS_CHANGED: | |
378 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
379 | schedule_work(&nvmeq->dev->scan_work); | |
380 | default: | |
381 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
382 | } | |
b60503ba MW |
383 | } |
384 | ||
a4aea562 MB |
385 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
386 | struct nvme_completion *cqe) | |
5a92e700 | 387 | { |
a4aea562 MB |
388 | struct request *req = ctx; |
389 | ||
390 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
391 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 392 | |
42483228 | 393 | blk_mq_free_request(req); |
a51afb54 | 394 | |
a4aea562 | 395 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
1c63dc66 | 396 | ++nvmeq->dev->ctrl.abort_limit; |
5a92e700 KB |
397 | } |
398 | ||
a4aea562 MB |
399 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
400 | struct nvme_completion *cqe) | |
b60503ba | 401 | { |
a4aea562 MB |
402 | struct async_cmd_info *cmdinfo = ctx; |
403 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
404 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
405 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 406 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
407 | } |
408 | ||
a4aea562 MB |
409 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
410 | unsigned int tag) | |
b60503ba | 411 | { |
42483228 | 412 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 413 | |
a4aea562 | 414 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
415 | } |
416 | ||
a4aea562 MB |
417 | /* |
418 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
419 | */ | |
420 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
421 | nvme_completion_fn *fn) | |
4f5099af | 422 | { |
a4aea562 MB |
423 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
424 | void *ctx; | |
425 | if (tag >= nvmeq->q_depth) { | |
426 | *fn = special_completion; | |
427 | return CMD_CTX_INVALID; | |
428 | } | |
429 | if (fn) | |
430 | *fn = cmd->fn; | |
431 | ctx = cmd->ctx; | |
432 | cmd->fn = special_completion; | |
433 | cmd->ctx = CMD_CTX_COMPLETED; | |
434 | return ctx; | |
b60503ba MW |
435 | } |
436 | ||
437 | /** | |
714a7a22 | 438 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
439 | * @nvmeq: The queue to use |
440 | * @cmd: The command to send | |
441 | * | |
442 | * Safe to use from interrupt context | |
443 | */ | |
e3f879bf SB |
444 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
445 | struct nvme_command *cmd) | |
b60503ba | 446 | { |
a4aea562 MB |
447 | u16 tail = nvmeq->sq_tail; |
448 | ||
8ffaadf7 JD |
449 | if (nvmeq->sq_cmds_io) |
450 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
451 | else | |
452 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
453 | ||
b60503ba MW |
454 | if (++tail == nvmeq->q_depth) |
455 | tail = 0; | |
7547881d | 456 | writel(tail, nvmeq->q_db); |
b60503ba | 457 | nvmeq->sq_tail = tail; |
b60503ba MW |
458 | } |
459 | ||
e3f879bf | 460 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
a4aea562 MB |
461 | { |
462 | unsigned long flags; | |
a4aea562 | 463 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
e3f879bf | 464 | __nvme_submit_cmd(nvmeq, cmd); |
a4aea562 | 465 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); |
a4aea562 MB |
466 | } |
467 | ||
eca18b23 | 468 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 469 | { |
eca18b23 | 470 | return ((void *)iod) + iod->offset; |
e025344c SMM |
471 | } |
472 | ||
ac3dd5bd JA |
473 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
474 | unsigned nseg, unsigned long private) | |
eca18b23 | 475 | { |
ac3dd5bd JA |
476 | iod->private = private; |
477 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
478 | iod->npages = -1; | |
479 | iod->length = nbytes; | |
480 | iod->nents = 0; | |
eca18b23 | 481 | } |
b60503ba | 482 | |
eca18b23 | 483 | static struct nvme_iod * |
ac3dd5bd JA |
484 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
485 | unsigned long priv, gfp_t gfp) | |
b60503ba | 486 | { |
eca18b23 | 487 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 488 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
489 | sizeof(struct scatterlist) * nseg, gfp); |
490 | ||
ac3dd5bd JA |
491 | if (iod) |
492 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
493 | |
494 | return iod; | |
b60503ba MW |
495 | } |
496 | ||
ac3dd5bd JA |
497 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
498 | gfp_t gfp) | |
499 | { | |
500 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
501 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
502 | struct nvme_iod *iod; |
503 | ||
504 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
505 | size <= NVME_INT_BYTES(dev)) { | |
506 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
507 | ||
508 | iod = cmd->iod; | |
ac3dd5bd | 509 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 510 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
511 | return iod; |
512 | } | |
513 | ||
514 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
515 | (unsigned long) rq, gfp); | |
516 | } | |
517 | ||
d29ec824 | 518 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 519 | { |
5fd4ce1b | 520 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 MW |
521 | int i; |
522 | __le64 **list = iod_list(iod); | |
523 | dma_addr_t prp_dma = iod->first_dma; | |
524 | ||
525 | if (iod->npages == 0) | |
526 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
527 | for (i = 0; i < iod->npages; i++) { | |
528 | __le64 *prp_list = list[i]; | |
529 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
530 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
531 | prp_dma = next_prp_dma; | |
532 | } | |
ac3dd5bd JA |
533 | |
534 | if (iod_should_kfree(iod)) | |
535 | kfree(iod); | |
b60503ba MW |
536 | } |
537 | ||
52b68d7e | 538 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
539 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
540 | { | |
541 | if (be32_to_cpu(pi->ref_tag) == v) | |
542 | pi->ref_tag = cpu_to_be32(p); | |
543 | } | |
544 | ||
545 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
546 | { | |
547 | if (be32_to_cpu(pi->ref_tag) == p) | |
548 | pi->ref_tag = cpu_to_be32(v); | |
549 | } | |
550 | ||
551 | /** | |
552 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
553 | * | |
554 | * The virtual start sector is the one that was originally submitted by the | |
555 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
556 | * start sector may be different. Remap protection information to match the | |
557 | * physical LBA on writes, and back to the original seed on reads. | |
558 | * | |
559 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
560 | */ | |
561 | static void nvme_dif_remap(struct request *req, | |
562 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
563 | { | |
564 | struct nvme_ns *ns = req->rq_disk->private_data; | |
565 | struct bio_integrity_payload *bip; | |
566 | struct t10_pi_tuple *pi; | |
567 | void *p, *pmap; | |
568 | u32 i, nlb, ts, phys, virt; | |
569 | ||
570 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
571 | return; | |
572 | ||
573 | bip = bio_integrity(req->bio); | |
574 | if (!bip) | |
575 | return; | |
576 | ||
577 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
578 | |
579 | p = pmap; | |
580 | virt = bip_get_seed(bip); | |
581 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
582 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 583 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
584 | |
585 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
586 | pi = (struct t10_pi_tuple *)p; | |
587 | dif_swap(phys, virt, pi); | |
588 | p += ts; | |
589 | } | |
590 | kunmap_atomic(pmap); | |
591 | } | |
52b68d7e KB |
592 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
593 | static void nvme_dif_remap(struct request *req, | |
594 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
595 | { | |
596 | } | |
597 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
598 | { | |
599 | } | |
600 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
601 | { | |
602 | } | |
52b68d7e KB |
603 | #endif |
604 | ||
a4aea562 | 605 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
606 | struct nvme_completion *cqe) |
607 | { | |
eca18b23 | 608 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 609 | struct request *req = iod_get_private(iod); |
a4aea562 | 610 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
b60503ba | 611 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
81c04b94 | 612 | int error = 0; |
b60503ba | 613 | |
edd10d33 | 614 | if (unlikely(status)) { |
a4aea562 MB |
615 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
616 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
617 | unsigned long flags; |
618 | ||
d4f6c3ab CH |
619 | nvme_unmap_data(nvmeq->dev, iod); |
620 | ||
a4aea562 | 621 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
622 | spin_lock_irqsave(req->q->queue_lock, flags); |
623 | if (!blk_queue_stopped(req->q)) | |
624 | blk_mq_kick_requeue_list(req->q); | |
625 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
d4f6c3ab | 626 | return; |
edd10d33 | 627 | } |
f4829a9b | 628 | |
d29ec824 | 629 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
17188bb4 | 630 | if (cmd_rq->ctx == CMD_CTX_CANCELLED) |
81c04b94 CH |
631 | error = -EINTR; |
632 | else | |
633 | error = status; | |
d29ec824 | 634 | } else { |
81c04b94 | 635 | error = nvme_error_status(status); |
d29ec824 | 636 | } |
f4829a9b CH |
637 | } |
638 | ||
a0a931d6 KB |
639 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
640 | u32 result = le32_to_cpup(&cqe->result); | |
641 | req->special = (void *)(uintptr_t)result; | |
642 | } | |
a4aea562 MB |
643 | |
644 | if (cmd_rq->aborted) | |
e75ec752 | 645 | dev_warn(nvmeq->dev->dev, |
a4aea562 | 646 | "completing aborted command with status:%04x\n", |
81c04b94 | 647 | error); |
a4aea562 | 648 | |
d4f6c3ab CH |
649 | nvme_unmap_data(nvmeq->dev, iod); |
650 | blk_mq_complete_request(req, error); | |
b60503ba MW |
651 | } |
652 | ||
69d2b571 CH |
653 | static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
654 | int total_len) | |
ff22b54f | 655 | { |
99802a7a | 656 | struct dma_pool *pool; |
eca18b23 MW |
657 | int length = total_len; |
658 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
659 | int dma_len = sg_dma_len(sg); |
660 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 661 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 662 | int offset = dma_addr & (page_size - 1); |
e025344c | 663 | __le64 *prp_list; |
eca18b23 | 664 | __le64 **list = iod_list(iod); |
e025344c | 665 | dma_addr_t prp_dma; |
eca18b23 | 666 | int nprps, i; |
ff22b54f | 667 | |
1d090624 | 668 | length -= (page_size - offset); |
ff22b54f | 669 | if (length <= 0) |
69d2b571 | 670 | return true; |
ff22b54f | 671 | |
1d090624 | 672 | dma_len -= (page_size - offset); |
ff22b54f | 673 | if (dma_len) { |
1d090624 | 674 | dma_addr += (page_size - offset); |
ff22b54f MW |
675 | } else { |
676 | sg = sg_next(sg); | |
677 | dma_addr = sg_dma_address(sg); | |
678 | dma_len = sg_dma_len(sg); | |
679 | } | |
680 | ||
1d090624 | 681 | if (length <= page_size) { |
edd10d33 | 682 | iod->first_dma = dma_addr; |
69d2b571 | 683 | return true; |
e025344c SMM |
684 | } |
685 | ||
1d090624 | 686 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
687 | if (nprps <= (256 / 8)) { |
688 | pool = dev->prp_small_pool; | |
eca18b23 | 689 | iod->npages = 0; |
99802a7a MW |
690 | } else { |
691 | pool = dev->prp_page_pool; | |
eca18b23 | 692 | iod->npages = 1; |
99802a7a MW |
693 | } |
694 | ||
69d2b571 | 695 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 696 | if (!prp_list) { |
edd10d33 | 697 | iod->first_dma = dma_addr; |
eca18b23 | 698 | iod->npages = -1; |
69d2b571 | 699 | return false; |
b77954cb | 700 | } |
eca18b23 MW |
701 | list[0] = prp_list; |
702 | iod->first_dma = prp_dma; | |
e025344c SMM |
703 | i = 0; |
704 | for (;;) { | |
1d090624 | 705 | if (i == page_size >> 3) { |
e025344c | 706 | __le64 *old_prp_list = prp_list; |
69d2b571 | 707 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 708 | if (!prp_list) |
69d2b571 | 709 | return false; |
eca18b23 | 710 | list[iod->npages++] = prp_list; |
7523d834 MW |
711 | prp_list[0] = old_prp_list[i - 1]; |
712 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
713 | i = 1; | |
e025344c SMM |
714 | } |
715 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
716 | dma_len -= page_size; |
717 | dma_addr += page_size; | |
718 | length -= page_size; | |
e025344c SMM |
719 | if (length <= 0) |
720 | break; | |
721 | if (dma_len > 0) | |
722 | continue; | |
723 | BUG_ON(dma_len < 0); | |
724 | sg = sg_next(sg); | |
725 | dma_addr = sg_dma_address(sg); | |
726 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
727 | } |
728 | ||
69d2b571 | 729 | return true; |
ff22b54f MW |
730 | } |
731 | ||
ba1ca37e CH |
732 | static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, |
733 | struct nvme_command *cmnd) | |
d29ec824 | 734 | { |
ba1ca37e CH |
735 | struct request *req = iod_get_private(iod); |
736 | struct request_queue *q = req->q; | |
737 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
738 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
739 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
740 | ||
741 | sg_init_table(iod->sg, req->nr_phys_segments); | |
742 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
743 | if (!iod->nents) | |
744 | goto out; | |
745 | ||
746 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
747 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
748 | goto out; | |
749 | ||
750 | if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) | |
751 | goto out_unmap; | |
752 | ||
753 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
754 | if (blk_integrity_rq(req)) { | |
755 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
756 | goto out_unmap; | |
757 | ||
758 | sg_init_table(iod->meta_sg, 1); | |
759 | if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) | |
760 | goto out_unmap; | |
d29ec824 | 761 | |
ba1ca37e CH |
762 | if (rq_data_dir(req)) |
763 | nvme_dif_remap(req, nvme_dif_prep); | |
764 | ||
765 | if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) | |
766 | goto out_unmap; | |
d29ec824 CH |
767 | } |
768 | ||
ba1ca37e CH |
769 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
770 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
771 | if (blk_integrity_rq(req)) | |
772 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
773 | return BLK_MQ_RQ_QUEUE_OK; | |
774 | ||
775 | out_unmap: | |
776 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
777 | out: | |
778 | return ret; | |
d29ec824 CH |
779 | } |
780 | ||
d4f6c3ab CH |
781 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) |
782 | { | |
783 | struct request *req = iod_get_private(iod); | |
784 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
785 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
786 | ||
787 | if (iod->nents) { | |
788 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
789 | if (blk_integrity_rq(req)) { | |
790 | if (!rq_data_dir(req)) | |
791 | nvme_dif_remap(req, nvme_dif_complete); | |
792 | dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); | |
793 | } | |
794 | } | |
795 | ||
796 | nvme_free_iod(dev, iod); | |
797 | } | |
798 | ||
a4aea562 MB |
799 | /* |
800 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
801 | * worth having a special pool for these or additional cases to handle freeing | |
802 | * the iod. | |
803 | */ | |
ba1ca37e CH |
804 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
805 | struct nvme_iod *iod, struct nvme_command *cmnd) | |
0e5e4f0e | 806 | { |
ba1ca37e CH |
807 | struct request *req = iod_get_private(iod); |
808 | struct nvme_dsm_range *range; | |
809 | ||
810 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
811 | &iod->first_dma); | |
812 | if (!range) | |
813 | return BLK_MQ_RQ_QUEUE_BUSY; | |
814 | iod_list(iod)[0] = (__le64 *)range; | |
815 | iod->npages = 0; | |
0e5e4f0e | 816 | |
0e5e4f0e | 817 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
818 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
819 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 820 | |
ba1ca37e CH |
821 | memset(cmnd, 0, sizeof(*cmnd)); |
822 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
823 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
824 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
825 | cmnd->dsm.nr = 0; | |
826 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
827 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
828 | } |
829 | ||
d29ec824 CH |
830 | /* |
831 | * NOTE: ns is NULL when called on the admin queue. | |
832 | */ | |
a4aea562 MB |
833 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
834 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 835 | { |
a4aea562 MB |
836 | struct nvme_ns *ns = hctx->queue->queuedata; |
837 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 838 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
839 | struct request *req = bd->rq; |
840 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 841 | struct nvme_iod *iod; |
ba1ca37e CH |
842 | struct nvme_command cmnd; |
843 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 844 | |
e1e5e564 KB |
845 | /* |
846 | * If formated with metadata, require the block layer provide a buffer | |
847 | * unless this namespace is formated such that the metadata can be | |
848 | * stripped/generated by the controller with PRACT=1. | |
849 | */ | |
d29ec824 | 850 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
851 | if (!(ns->pi_type && ns->ms == 8) && |
852 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
f4829a9b | 853 | blk_mq_complete_request(req, -EFAULT); |
e1e5e564 KB |
854 | return BLK_MQ_RQ_QUEUE_OK; |
855 | } | |
856 | } | |
857 | ||
d29ec824 | 858 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 859 | if (!iod) |
fe54303e | 860 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 861 | |
a4aea562 | 862 | if (req->cmd_flags & REQ_DISCARD) { |
ba1ca37e CH |
863 | ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); |
864 | } else { | |
865 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
866 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
867 | else if (req->cmd_flags & REQ_FLUSH) | |
868 | nvme_setup_flush(ns, &cmnd); | |
869 | else | |
870 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 871 | |
ba1ca37e CH |
872 | if (req->nr_phys_segments) |
873 | ret = nvme_map_data(dev, iod, &cmnd); | |
edd10d33 | 874 | } |
1974b1ae | 875 | |
ba1ca37e CH |
876 | if (ret) |
877 | goto out; | |
878 | ||
879 | cmnd.common.command_id = req->tag; | |
9af8785a | 880 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 881 | |
ba1ca37e CH |
882 | spin_lock_irq(&nvmeq->q_lock); |
883 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
884 | nvme_process_cq(nvmeq); |
885 | spin_unlock_irq(&nvmeq->q_lock); | |
886 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 887 | out: |
d29ec824 | 888 | nvme_free_iod(dev, iod); |
ba1ca37e | 889 | return ret; |
b60503ba MW |
890 | } |
891 | ||
a0fa9647 | 892 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 893 | { |
82123460 | 894 | u16 head, phase; |
b60503ba | 895 | |
b60503ba | 896 | head = nvmeq->cq_head; |
82123460 | 897 | phase = nvmeq->cq_phase; |
b60503ba MW |
898 | |
899 | for (;;) { | |
c2f5b650 MW |
900 | void *ctx; |
901 | nvme_completion_fn fn; | |
b60503ba | 902 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 903 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
904 | break; |
905 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
906 | if (++head == nvmeq->q_depth) { | |
907 | head = 0; | |
82123460 | 908 | phase = !phase; |
b60503ba | 909 | } |
a0fa9647 JA |
910 | if (tag && *tag == cqe.command_id) |
911 | *tag = -1; | |
a4aea562 | 912 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 913 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
914 | } |
915 | ||
916 | /* If the controller ignores the cq head doorbell and continuously | |
917 | * writes to the queue, it is theoretically possible to wrap around | |
918 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
919 | * requires that 0.1% of your interrupts are handled, so this isn't | |
920 | * a big problem. | |
921 | */ | |
82123460 | 922 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 923 | return; |
b60503ba | 924 | |
604e8c8d KB |
925 | if (likely(nvmeq->cq_vector >= 0)) |
926 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 927 | nvmeq->cq_head = head; |
82123460 | 928 | nvmeq->cq_phase = phase; |
b60503ba | 929 | |
e9539f47 | 930 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
931 | } |
932 | ||
933 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
934 | { | |
935 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
936 | } |
937 | ||
938 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
939 | { |
940 | irqreturn_t result; | |
941 | struct nvme_queue *nvmeq = data; | |
942 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
943 | nvme_process_cq(nvmeq); |
944 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
945 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
946 | spin_unlock(&nvmeq->q_lock); |
947 | return result; | |
948 | } | |
949 | ||
950 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
951 | { | |
952 | struct nvme_queue *nvmeq = data; | |
953 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
954 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
955 | return IRQ_NONE; | |
956 | return IRQ_WAKE_THREAD; | |
957 | } | |
958 | ||
a0fa9647 JA |
959 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
960 | { | |
961 | struct nvme_queue *nvmeq = hctx->driver_data; | |
962 | ||
963 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
964 | nvmeq->cq_phase) { | |
965 | spin_lock_irq(&nvmeq->q_lock); | |
966 | __nvme_process_cq(nvmeq, &tag); | |
967 | spin_unlock_irq(&nvmeq->q_lock); | |
968 | ||
969 | if (tag == -1) | |
970 | return 1; | |
971 | } | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
a4aea562 MB |
976 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
977 | { | |
978 | struct nvme_queue *nvmeq = dev->queues[0]; | |
979 | struct nvme_command c; | |
980 | struct nvme_cmd_info *cmd_info; | |
981 | struct request *req; | |
982 | ||
1c63dc66 | 983 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 984 | BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); |
9f173b33 DC |
985 | if (IS_ERR(req)) |
986 | return PTR_ERR(req); | |
a4aea562 | 987 | |
c917dfe5 | 988 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 989 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 990 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
991 | |
992 | memset(&c, 0, sizeof(c)); | |
993 | c.common.opcode = nvme_admin_async_event; | |
994 | c.common.command_id = req->tag; | |
995 | ||
42483228 | 996 | blk_mq_free_request(req); |
e3f879bf SB |
997 | __nvme_submit_cmd(nvmeq, &c); |
998 | return 0; | |
a4aea562 MB |
999 | } |
1000 | ||
1001 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
1002 | struct nvme_command *cmd, |
1003 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
1004 | { | |
a4aea562 MB |
1005 | struct nvme_queue *nvmeq = dev->queues[0]; |
1006 | struct request *req; | |
1007 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1008 | |
1c63dc66 | 1009 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); |
9f173b33 DC |
1010 | if (IS_ERR(req)) |
1011 | return PTR_ERR(req); | |
a4aea562 MB |
1012 | |
1013 | req->timeout = timeout; | |
1014 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1015 | cmdinfo->req = req; | |
1016 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1017 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1018 | |
1019 | cmd->common.command_id = req->tag; | |
1020 | ||
e3f879bf SB |
1021 | nvme_submit_cmd(nvmeq, cmd); |
1022 | return 0; | |
4d115420 KB |
1023 | } |
1024 | ||
b60503ba MW |
1025 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1026 | { | |
b60503ba MW |
1027 | struct nvme_command c; |
1028 | ||
1029 | memset(&c, 0, sizeof(c)); | |
1030 | c.delete_queue.opcode = opcode; | |
1031 | c.delete_queue.qid = cpu_to_le16(id); | |
1032 | ||
1c63dc66 | 1033 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1034 | } |
1035 | ||
1036 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1037 | struct nvme_queue *nvmeq) | |
1038 | { | |
b60503ba MW |
1039 | struct nvme_command c; |
1040 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1041 | ||
d29ec824 CH |
1042 | /* |
1043 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1044 | * is attached to the request. | |
1045 | */ | |
b60503ba MW |
1046 | memset(&c, 0, sizeof(c)); |
1047 | c.create_cq.opcode = nvme_admin_create_cq; | |
1048 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1049 | c.create_cq.cqid = cpu_to_le16(qid); | |
1050 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1051 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1052 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1053 | ||
1c63dc66 | 1054 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1055 | } |
1056 | ||
1057 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1058 | struct nvme_queue *nvmeq) | |
1059 | { | |
b60503ba MW |
1060 | struct nvme_command c; |
1061 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1062 | ||
d29ec824 CH |
1063 | /* |
1064 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1065 | * is attached to the request. | |
1066 | */ | |
b60503ba MW |
1067 | memset(&c, 0, sizeof(c)); |
1068 | c.create_sq.opcode = nvme_admin_create_sq; | |
1069 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1070 | c.create_sq.sqid = cpu_to_le16(qid); | |
1071 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1072 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1073 | c.create_sq.cqid = cpu_to_le16(qid); | |
1074 | ||
1c63dc66 | 1075 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1076 | } |
1077 | ||
1078 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1079 | { | |
1080 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1081 | } | |
1082 | ||
1083 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1084 | { | |
1085 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1086 | } | |
1087 | ||
c30341dc | 1088 | /** |
a4aea562 | 1089 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1090 | * |
1091 | * Schedule controller reset if the command was already aborted once before and | |
1092 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1093 | */ | |
a4aea562 | 1094 | static void nvme_abort_req(struct request *req) |
c30341dc | 1095 | { |
a4aea562 MB |
1096 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1097 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1098 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1099 | struct request *abort_req; |
1100 | struct nvme_cmd_info *abort_cmd; | |
1101 | struct nvme_command cmd; | |
c30341dc | 1102 | |
a4aea562 | 1103 | if (!nvmeq->qid || cmd_rq->aborted) { |
90667892 CH |
1104 | spin_lock(&dev_list_lock); |
1105 | if (!__nvme_reset(dev)) { | |
1106 | dev_warn(dev->dev, | |
1107 | "I/O %d QID %d timeout, reset controller\n", | |
1108 | req->tag, nvmeq->qid); | |
1109 | } | |
1110 | spin_unlock(&dev_list_lock); | |
c30341dc KB |
1111 | return; |
1112 | } | |
1113 | ||
1c63dc66 | 1114 | if (!dev->ctrl.abort_limit) |
c30341dc KB |
1115 | return; |
1116 | ||
1c63dc66 | 1117 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1118 | BLK_MQ_REQ_NOWAIT); |
9f173b33 | 1119 | if (IS_ERR(abort_req)) |
c30341dc KB |
1120 | return; |
1121 | ||
a4aea562 MB |
1122 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1123 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1124 | ||
c30341dc KB |
1125 | memset(&cmd, 0, sizeof(cmd)); |
1126 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1127 | cmd.abort.cid = req->tag; |
c30341dc | 1128 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1129 | cmd.abort.command_id = abort_req->tag; |
c30341dc | 1130 | |
1c63dc66 | 1131 | --dev->ctrl.abort_limit; |
a4aea562 | 1132 | cmd_rq->aborted = 1; |
c30341dc | 1133 | |
a4aea562 | 1134 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1135 | nvmeq->qid); |
e3f879bf | 1136 | nvme_submit_cmd(dev->queues[0], &cmd); |
c30341dc KB |
1137 | } |
1138 | ||
42483228 | 1139 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1140 | { |
a4aea562 MB |
1141 | struct nvme_queue *nvmeq = data; |
1142 | void *ctx; | |
1143 | nvme_completion_fn fn; | |
1144 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1145 | struct nvme_completion cqe; |
1146 | ||
1147 | if (!blk_mq_request_started(req)) | |
1148 | return; | |
a09115b2 | 1149 | |
a4aea562 | 1150 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1151 | |
a4aea562 MB |
1152 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1153 | return; | |
1154 | ||
cef6a948 KB |
1155 | if (blk_queue_dying(req->q)) |
1156 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1157 | else | |
1158 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1159 | ||
1160 | ||
a4aea562 MB |
1161 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1162 | req->tag, nvmeq->qid); | |
1163 | ctx = cancel_cmd_info(cmd, &fn); | |
1164 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1165 | } |
1166 | ||
a4aea562 | 1167 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1168 | { |
a4aea562 MB |
1169 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1170 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1171 | ||
1172 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1173 | nvmeq->qid); | |
7a509a6b | 1174 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1175 | nvme_abort_req(req); |
7a509a6b | 1176 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1177 | |
07836e65 KB |
1178 | /* |
1179 | * The aborted req will be completed on receiving the abort req. | |
1180 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1181 | * as the device then is in a faulty state. | |
1182 | */ | |
1183 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1184 | } |
22404274 | 1185 | |
a4aea562 MB |
1186 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1187 | { | |
9e866774 MW |
1188 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1189 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1190 | if (nvmeq->sq_cmds) |
1191 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1192 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1193 | kfree(nvmeq); | |
1194 | } | |
1195 | ||
a1a5ef99 | 1196 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1197 | { |
1198 | int i; | |
1199 | ||
a1a5ef99 | 1200 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1201 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1202 | dev->queue_count--; |
a4aea562 | 1203 | dev->queues[i] = NULL; |
f435c282 | 1204 | nvme_free_queue(nvmeq); |
121c7ad4 | 1205 | } |
22404274 KB |
1206 | } |
1207 | ||
4d115420 KB |
1208 | /** |
1209 | * nvme_suspend_queue - put queue into suspended state | |
1210 | * @nvmeq - queue to suspend | |
4d115420 KB |
1211 | */ |
1212 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1213 | { |
2b25d981 | 1214 | int vector; |
b60503ba | 1215 | |
a09115b2 | 1216 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1217 | if (nvmeq->cq_vector == -1) { |
1218 | spin_unlock_irq(&nvmeq->q_lock); | |
1219 | return 1; | |
1220 | } | |
1221 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1222 | nvmeq->dev->online_queues--; |
2b25d981 | 1223 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1224 | spin_unlock_irq(&nvmeq->q_lock); |
1225 | ||
1c63dc66 CH |
1226 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1227 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1228 | |
aba2080f MW |
1229 | irq_set_affinity_hint(vector, NULL); |
1230 | free_irq(vector, nvmeq); | |
b60503ba | 1231 | |
4d115420 KB |
1232 | return 0; |
1233 | } | |
b60503ba | 1234 | |
4d115420 KB |
1235 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1236 | { | |
22404274 | 1237 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1238 | if (nvmeq->tags && *nvmeq->tags) |
1239 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1240 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1241 | } |
1242 | ||
4d115420 KB |
1243 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1244 | { | |
a4aea562 | 1245 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1246 | |
1247 | if (!nvmeq) | |
1248 | return; | |
1249 | if (nvme_suspend_queue(nvmeq)) | |
1250 | return; | |
1251 | ||
0e53d180 KB |
1252 | /* Don't tell the adapter to delete the admin queue. |
1253 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1254 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1255 | adapter_delete_sq(dev, qid); |
1256 | adapter_delete_cq(dev, qid); | |
1257 | } | |
07836e65 KB |
1258 | |
1259 | spin_lock_irq(&nvmeq->q_lock); | |
1260 | nvme_process_cq(nvmeq); | |
1261 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1262 | } |
1263 | ||
8ffaadf7 JD |
1264 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1265 | int entry_size) | |
1266 | { | |
1267 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1268 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1269 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1270 | |
1271 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1272 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1273 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1274 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1275 | |
1276 | /* | |
1277 | * Ensure the reduced q_depth is above some threshold where it | |
1278 | * would be better to map queues in system memory with the | |
1279 | * original depth | |
1280 | */ | |
1281 | if (q_depth < 64) | |
1282 | return -ENOMEM; | |
1283 | } | |
1284 | ||
1285 | return q_depth; | |
1286 | } | |
1287 | ||
1288 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1289 | int qid, int depth) | |
1290 | { | |
1291 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1292 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1293 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1294 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1295 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1296 | } else { | |
1297 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1298 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1299 | if (!nvmeq->sq_cmds) | |
1300 | return -ENOMEM; | |
1301 | } | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
b60503ba | 1306 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1307 | int depth) |
b60503ba | 1308 | { |
a4aea562 | 1309 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1310 | if (!nvmeq) |
1311 | return NULL; | |
1312 | ||
e75ec752 | 1313 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1314 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1315 | if (!nvmeq->cqes) |
1316 | goto free_nvmeq; | |
b60503ba | 1317 | |
8ffaadf7 | 1318 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1319 | goto free_cqdma; |
1320 | ||
e75ec752 | 1321 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1322 | nvmeq->dev = dev; |
3193f07b | 1323 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1324 | dev->ctrl.instance, qid); |
b60503ba MW |
1325 | spin_lock_init(&nvmeq->q_lock); |
1326 | nvmeq->cq_head = 0; | |
82123460 | 1327 | nvmeq->cq_phase = 1; |
b80d5ccc | 1328 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1329 | nvmeq->q_depth = depth; |
c30341dc | 1330 | nvmeq->qid = qid; |
758dd7fd | 1331 | nvmeq->cq_vector = -1; |
a4aea562 | 1332 | dev->queues[qid] = nvmeq; |
b60503ba | 1333 | |
36a7e993 JD |
1334 | /* make sure queue descriptor is set before queue count, for kthread */ |
1335 | mb(); | |
1336 | dev->queue_count++; | |
1337 | ||
b60503ba MW |
1338 | return nvmeq; |
1339 | ||
1340 | free_cqdma: | |
e75ec752 | 1341 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1342 | nvmeq->cq_dma_addr); |
1343 | free_nvmeq: | |
1344 | kfree(nvmeq); | |
1345 | return NULL; | |
1346 | } | |
1347 | ||
3001082c MW |
1348 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1349 | const char *name) | |
1350 | { | |
58ffacb5 MW |
1351 | if (use_threaded_interrupts) |
1352 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1353 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1354 | name, nvmeq); |
3001082c | 1355 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1356 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1357 | } |
1358 | ||
22404274 | 1359 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1360 | { |
22404274 | 1361 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1362 | |
7be50e93 | 1363 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1364 | nvmeq->sq_tail = 0; |
1365 | nvmeq->cq_head = 0; | |
1366 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1367 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1368 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1369 | dev->online_queues++; |
7be50e93 | 1370 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1371 | } |
1372 | ||
1373 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1374 | { | |
1375 | struct nvme_dev *dev = nvmeq->dev; | |
1376 | int result; | |
3f85d50b | 1377 | |
2b25d981 | 1378 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1379 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1380 | if (result < 0) | |
22404274 | 1381 | return result; |
b60503ba MW |
1382 | |
1383 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1384 | if (result < 0) | |
1385 | goto release_cq; | |
1386 | ||
3193f07b | 1387 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1388 | if (result < 0) |
1389 | goto release_sq; | |
1390 | ||
22404274 | 1391 | nvme_init_queue(nvmeq, qid); |
22404274 | 1392 | return result; |
b60503ba MW |
1393 | |
1394 | release_sq: | |
1395 | adapter_delete_sq(dev, qid); | |
1396 | release_cq: | |
1397 | adapter_delete_cq(dev, qid); | |
22404274 | 1398 | return result; |
b60503ba MW |
1399 | } |
1400 | ||
a4aea562 | 1401 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1402 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1403 | .map_queue = blk_mq_map_queue, |
1404 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1405 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1406 | .init_request = nvme_admin_init_request, |
1407 | .timeout = nvme_timeout, | |
1408 | }; | |
1409 | ||
1410 | static struct blk_mq_ops nvme_mq_ops = { | |
1411 | .queue_rq = nvme_queue_rq, | |
1412 | .map_queue = blk_mq_map_queue, | |
1413 | .init_hctx = nvme_init_hctx, | |
1414 | .init_request = nvme_init_request, | |
1415 | .timeout = nvme_timeout, | |
a0fa9647 | 1416 | .poll = nvme_poll, |
a4aea562 MB |
1417 | }; |
1418 | ||
ea191d2f KB |
1419 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1420 | { | |
1c63dc66 CH |
1421 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1422 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1423 | blk_mq_free_tag_set(&dev->admin_tagset); |
1424 | } | |
1425 | } | |
1426 | ||
a4aea562 MB |
1427 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1428 | { | |
1c63dc66 | 1429 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1430 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1431 | dev->admin_tagset.nr_hw_queues = 1; | |
1432 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1433 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1434 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1435 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1436 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1437 | dev->admin_tagset.driver_data = dev; |
1438 | ||
1439 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1440 | return -ENOMEM; | |
1441 | ||
1c63dc66 CH |
1442 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1443 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1444 | blk_mq_free_tag_set(&dev->admin_tagset); |
1445 | return -ENOMEM; | |
1446 | } | |
1c63dc66 | 1447 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1448 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1449 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1450 | return -ENODEV; |
1451 | } | |
0fb59cbc | 1452 | } else |
1c63dc66 | 1453 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1454 | |
1455 | return 0; | |
1456 | } | |
1457 | ||
8d85fce7 | 1458 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1459 | { |
ba47e386 | 1460 | int result; |
b60503ba | 1461 | u32 aqa; |
7a67cbea | 1462 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1463 | struct nvme_queue *nvmeq; |
1464 | ||
7a67cbea | 1465 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1466 | NVME_CAP_NSSRC(cap) : 0; |
1467 | ||
7a67cbea CH |
1468 | if (dev->subsystem && |
1469 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1470 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1471 | |
5fd4ce1b | 1472 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1473 | if (result < 0) |
1474 | return result; | |
b60503ba | 1475 | |
a4aea562 | 1476 | nvmeq = dev->queues[0]; |
cd638946 | 1477 | if (!nvmeq) { |
2b25d981 | 1478 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1479 | if (!nvmeq) |
1480 | return -ENOMEM; | |
cd638946 | 1481 | } |
b60503ba MW |
1482 | |
1483 | aqa = nvmeq->q_depth - 1; | |
1484 | aqa |= aqa << 16; | |
1485 | ||
7a67cbea CH |
1486 | writel(aqa, dev->bar + NVME_REG_AQA); |
1487 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1488 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1489 | |
5fd4ce1b | 1490 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1491 | if (result) |
a4aea562 MB |
1492 | goto free_nvmeq; |
1493 | ||
2b25d981 | 1494 | nvmeq->cq_vector = 0; |
3193f07b | 1495 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1496 | if (result) { |
1497 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1498 | goto free_nvmeq; |
758dd7fd | 1499 | } |
025c557a | 1500 | |
b60503ba | 1501 | return result; |
a4aea562 | 1502 | |
a4aea562 MB |
1503 | free_nvmeq: |
1504 | nvme_free_queues(dev, 0); | |
1505 | return result; | |
b60503ba MW |
1506 | } |
1507 | ||
81f03fed JD |
1508 | static int nvme_subsys_reset(struct nvme_dev *dev) |
1509 | { | |
1510 | if (!dev->subsystem) | |
1511 | return -ENOTTY; | |
1512 | ||
7a67cbea | 1513 | writel(0x4E564D65, dev->bar + NVME_REG_NSSR); /* "NVMe" */ |
81f03fed JD |
1514 | return 0; |
1515 | } | |
1516 | ||
1fa6aead MW |
1517 | static int nvme_kthread(void *data) |
1518 | { | |
d4b4ff8e | 1519 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1520 | |
1521 | while (!kthread_should_stop()) { | |
564a232c | 1522 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1523 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1524 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1525 | int i; |
7a67cbea | 1526 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 KB |
1527 | |
1528 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
1529 | csts & NVME_CSTS_CFS) { | |
90667892 CH |
1530 | if (!__nvme_reset(dev)) { |
1531 | dev_warn(dev->dev, | |
1532 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1533 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1534 | } |
d4b4ff8e KB |
1535 | continue; |
1536 | } | |
1fa6aead | 1537 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1538 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1539 | if (!nvmeq) |
1540 | continue; | |
1fa6aead | 1541 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1542 | nvme_process_cq(nvmeq); |
6fccf938 | 1543 | |
1c63dc66 | 1544 | while (i == 0 && dev->ctrl.event_limit > 0) { |
a4aea562 | 1545 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 | 1546 | break; |
1c63dc66 | 1547 | dev->ctrl.event_limit--; |
6fccf938 | 1548 | } |
1fa6aead MW |
1549 | spin_unlock_irq(&nvmeq->q_lock); |
1550 | } | |
1551 | } | |
1552 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1553 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1554 | } |
1555 | return 0; | |
1556 | } | |
1557 | ||
2659e57b CH |
1558 | /* |
1559 | * Create I/O queues. Failing to create an I/O queue is not an issue, | |
1560 | * we can continue with less than the desired amount of queues, and | |
1561 | * even a controller without I/O queues an still be used to issue | |
1562 | * admin commands. This might be useful to upgrade a buggy firmware | |
1563 | * for example. | |
1564 | */ | |
42f61420 KB |
1565 | static void nvme_create_io_queues(struct nvme_dev *dev) |
1566 | { | |
a4aea562 | 1567 | unsigned i; |
42f61420 | 1568 | |
a4aea562 | 1569 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 1570 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
1571 | break; |
1572 | ||
a4aea562 | 1573 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2659e57b CH |
1574 | if (nvme_create_queue(dev->queues[i], i)) { |
1575 | nvme_free_queues(dev, i); | |
42f61420 | 1576 | break; |
2659e57b | 1577 | } |
42f61420 KB |
1578 | } |
1579 | ||
b3b06812 | 1580 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1581 | { |
1582 | int status; | |
1583 | u32 result; | |
b3b06812 | 1584 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1585 | |
1c63dc66 | 1586 | status = nvme_set_features(&dev->ctrl, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1587 | &result); |
27e8166c MW |
1588 | if (status < 0) |
1589 | return status; | |
1590 | if (status > 0) { | |
e75ec752 | 1591 | dev_err(dev->dev, "Could not set queue count (%d)\n", status); |
badc34d4 | 1592 | return 0; |
27e8166c | 1593 | } |
b60503ba MW |
1594 | return min(result & 0xffff, result >> 16) + 1; |
1595 | } | |
1596 | ||
8ffaadf7 JD |
1597 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1598 | { | |
1599 | u64 szu, size, offset; | |
1600 | u32 cmbloc; | |
1601 | resource_size_t bar_size; | |
1602 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1603 | void __iomem *cmb; | |
1604 | dma_addr_t dma_addr; | |
1605 | ||
1606 | if (!use_cmb_sqes) | |
1607 | return NULL; | |
1608 | ||
7a67cbea | 1609 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1610 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1611 | return NULL; | |
1612 | ||
7a67cbea | 1613 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1614 | |
1615 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1616 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1617 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1618 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1619 | ||
1620 | if (offset > bar_size) | |
1621 | return NULL; | |
1622 | ||
1623 | /* | |
1624 | * Controllers may support a CMB size larger than their BAR, | |
1625 | * for example, due to being behind a bridge. Reduce the CMB to | |
1626 | * the reported size of the BAR | |
1627 | */ | |
1628 | if (size > bar_size - offset) | |
1629 | size = bar_size - offset; | |
1630 | ||
1631 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1632 | cmb = ioremap_wc(dma_addr, size); | |
1633 | if (!cmb) | |
1634 | return NULL; | |
1635 | ||
1636 | dev->cmb_dma_addr = dma_addr; | |
1637 | dev->cmb_size = size; | |
1638 | return cmb; | |
1639 | } | |
1640 | ||
1641 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1642 | { | |
1643 | if (dev->cmb) { | |
1644 | iounmap(dev->cmb); | |
1645 | dev->cmb = NULL; | |
1646 | } | |
1647 | } | |
1648 | ||
9d713c2b KB |
1649 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1650 | { | |
b80d5ccc | 1651 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1652 | } |
1653 | ||
8d85fce7 | 1654 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1655 | { |
a4aea562 | 1656 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1657 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1658 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1659 | |
42f61420 | 1660 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 1661 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 1662 | if (result <= 0) |
1b23484b | 1663 | return result; |
b348b7d5 MW |
1664 | if (result < nr_io_queues) |
1665 | nr_io_queues = result; | |
b60503ba | 1666 | |
8ffaadf7 JD |
1667 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1668 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1669 | sizeof(struct nvme_command)); | |
1670 | if (result > 0) | |
1671 | dev->q_depth = result; | |
1672 | else | |
1673 | nvme_release_cmb(dev); | |
1674 | } | |
1675 | ||
9d713c2b KB |
1676 | size = db_bar_size(dev, nr_io_queues); |
1677 | if (size > 8192) { | |
f1938f6e | 1678 | iounmap(dev->bar); |
9d713c2b KB |
1679 | do { |
1680 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1681 | if (dev->bar) | |
1682 | break; | |
1683 | if (!--nr_io_queues) | |
1684 | return -ENOMEM; | |
1685 | size = db_bar_size(dev, nr_io_queues); | |
1686 | } while (1); | |
7a67cbea | 1687 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1688 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1689 | } |
1690 | ||
9d713c2b | 1691 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1692 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1693 | |
e32efbfc JA |
1694 | /* |
1695 | * If we enable msix early due to not intx, disable it again before | |
1696 | * setting up the full range we need. | |
1697 | */ | |
1698 | if (!pdev->irq) | |
1699 | pci_disable_msix(pdev); | |
1700 | ||
be577fab | 1701 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1702 | dev->entry[i].entry = i; |
be577fab AG |
1703 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1704 | if (vecs < 0) { | |
1705 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1706 | if (vecs < 0) { | |
1707 | vecs = 1; | |
1708 | } else { | |
1709 | for (i = 0; i < vecs; i++) | |
1710 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1711 | } |
1712 | } | |
1713 | ||
063a8096 MW |
1714 | /* |
1715 | * Should investigate if there's a performance win from allocating | |
1716 | * more queues than interrupt vectors; it might allow the submission | |
1717 | * path to scale better, even if the receive path is limited by the | |
1718 | * number of interrupts. | |
1719 | */ | |
1720 | nr_io_queues = vecs; | |
42f61420 | 1721 | dev->max_qid = nr_io_queues; |
063a8096 | 1722 | |
3193f07b | 1723 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1724 | if (result) { |
1725 | adminq->cq_vector = -1; | |
22404274 | 1726 | goto free_queues; |
758dd7fd | 1727 | } |
1b23484b | 1728 | |
cd638946 | 1729 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1730 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 1731 | nvme_create_io_queues(dev); |
9ecdc946 | 1732 | |
22404274 | 1733 | return 0; |
b60503ba | 1734 | |
22404274 | 1735 | free_queues: |
a1a5ef99 | 1736 | nvme_free_queues(dev, 1); |
22404274 | 1737 | return result; |
b60503ba MW |
1738 | } |
1739 | ||
bda4e0fb KB |
1740 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1741 | { | |
1742 | struct nvme_queue *nvmeq; | |
1743 | int i; | |
1744 | ||
1745 | for (i = 0; i < dev->online_queues; i++) { | |
1746 | nvmeq = dev->queues[i]; | |
1747 | ||
1748 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1749 | continue; | |
1750 | ||
1751 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1752 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1753 | } | |
1754 | } | |
1755 | ||
a5768aa8 KB |
1756 | static void nvme_dev_scan(struct work_struct *work) |
1757 | { | |
1758 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1759 | |
1760 | if (!dev->tagset.tags) | |
1761 | return; | |
5bae7f73 | 1762 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1763 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1764 | } |
1765 | ||
422ef0c7 MW |
1766 | /* |
1767 | * Return: error value if an error occurred setting up the queues or calling | |
1768 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1769 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1770 | * failures should be reported. | |
1771 | */ | |
8d85fce7 | 1772 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1773 | { |
5bae7f73 | 1774 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1775 | dev->tagset.ops = &nvme_mq_ops; |
1776 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1777 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1778 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1779 | dev->tagset.queue_depth = | |
a4aea562 | 1780 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1781 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1782 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1783 | dev->tagset.driver_data = dev; | |
b60503ba | 1784 | |
ffe7704d KB |
1785 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1786 | return 0; | |
5bae7f73 | 1787 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1788 | } |
a5768aa8 | 1789 | schedule_work(&dev->scan_work); |
e1e5e564 | 1790 | return 0; |
b60503ba MW |
1791 | } |
1792 | ||
0877cb0d KB |
1793 | static int nvme_dev_map(struct nvme_dev *dev) |
1794 | { | |
42f61420 | 1795 | u64 cap; |
0877cb0d | 1796 | int bars, result = -ENOMEM; |
e75ec752 | 1797 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1798 | |
1799 | if (pci_enable_device_mem(pdev)) | |
1800 | return result; | |
1801 | ||
1802 | dev->entry[0].vector = pdev->irq; | |
1803 | pci_set_master(pdev); | |
1804 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1805 | if (!bars) |
1806 | goto disable_pci; | |
1807 | ||
0877cb0d KB |
1808 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1809 | goto disable_pci; | |
1810 | ||
e75ec752 CH |
1811 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1812 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1813 | goto disable; |
0877cb0d | 1814 | |
0877cb0d KB |
1815 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1816 | if (!dev->bar) | |
1817 | goto disable; | |
e32efbfc | 1818 | |
7a67cbea | 1819 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1820 | result = -ENODEV; |
1821 | goto unmap; | |
1822 | } | |
e32efbfc JA |
1823 | |
1824 | /* | |
1825 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1826 | * MSIX vec for setup. We'll adjust this later. | |
1827 | */ | |
1828 | if (!pdev->irq) { | |
1829 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1830 | if (result < 0) | |
1831 | goto unmap; | |
1832 | } | |
1833 | ||
7a67cbea CH |
1834 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1835 | ||
42f61420 KB |
1836 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1837 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1838 | dev->dbs = dev->bar + 4096; |
1839 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1840 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
1841 | |
1842 | return 0; | |
1843 | ||
0e53d180 KB |
1844 | unmap: |
1845 | iounmap(dev->bar); | |
1846 | dev->bar = NULL; | |
0877cb0d KB |
1847 | disable: |
1848 | pci_release_regions(pdev); | |
1849 | disable_pci: | |
1850 | pci_disable_device(pdev); | |
1851 | return result; | |
1852 | } | |
1853 | ||
1854 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1855 | { | |
e75ec752 CH |
1856 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1857 | ||
1858 | if (pdev->msi_enabled) | |
1859 | pci_disable_msi(pdev); | |
1860 | else if (pdev->msix_enabled) | |
1861 | pci_disable_msix(pdev); | |
0877cb0d KB |
1862 | |
1863 | if (dev->bar) { | |
1864 | iounmap(dev->bar); | |
1865 | dev->bar = NULL; | |
e75ec752 | 1866 | pci_release_regions(pdev); |
0877cb0d KB |
1867 | } |
1868 | ||
e75ec752 CH |
1869 | if (pci_is_enabled(pdev)) |
1870 | pci_disable_device(pdev); | |
0877cb0d KB |
1871 | } |
1872 | ||
4d115420 KB |
1873 | struct nvme_delq_ctx { |
1874 | struct task_struct *waiter; | |
1875 | struct kthread_worker *worker; | |
1876 | atomic_t refcount; | |
1877 | }; | |
1878 | ||
1879 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
1880 | { | |
1881 | dq->waiter = current; | |
1882 | mb(); | |
1883 | ||
1884 | for (;;) { | |
1885 | set_current_state(TASK_KILLABLE); | |
1886 | if (!atomic_read(&dq->refcount)) | |
1887 | break; | |
1888 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
1889 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
1890 | /* |
1891 | * Disable the controller first since we can't trust it | |
1892 | * at this point, but leave the admin queue enabled | |
1893 | * until all queue deletion requests are flushed. | |
1894 | * FIXME: This may take a while if there are more h/w | |
1895 | * queues than admin tags. | |
1896 | */ | |
4d115420 | 1897 | set_current_state(TASK_RUNNING); |
5fd4ce1b | 1898 | nvme_disable_ctrl(&dev->ctrl, |
7a67cbea | 1899 | lo_hi_readq(dev->bar + NVME_REG_CAP)); |
0fb59cbc | 1900 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 1901 | flush_kthread_worker(dq->worker); |
0fb59cbc | 1902 | nvme_disable_queue(dev, 0); |
4d115420 KB |
1903 | return; |
1904 | } | |
1905 | } | |
1906 | set_current_state(TASK_RUNNING); | |
1907 | } | |
1908 | ||
1909 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
1910 | { | |
1911 | atomic_dec(&dq->refcount); | |
1912 | if (dq->waiter) | |
1913 | wake_up_process(dq->waiter); | |
1914 | } | |
1915 | ||
1916 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
1917 | { | |
1918 | atomic_inc(&dq->refcount); | |
1919 | return dq; | |
1920 | } | |
1921 | ||
1922 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
1923 | { | |
1924 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 1925 | nvme_put_dq(dq); |
604e8c8d KB |
1926 | |
1927 | spin_lock_irq(&nvmeq->q_lock); | |
1928 | nvme_process_cq(nvmeq); | |
1929 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
1930 | } |
1931 | ||
1932 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
1933 | kthread_work_func_t fn) | |
1934 | { | |
1935 | struct nvme_command c; | |
1936 | ||
1937 | memset(&c, 0, sizeof(c)); | |
1938 | c.delete_queue.opcode = opcode; | |
1939 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1940 | ||
1941 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
1942 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
1943 | ADMIN_TIMEOUT); | |
4d115420 KB |
1944 | } |
1945 | ||
1946 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
1947 | { | |
1948 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1949 | cmdinfo.work); | |
1950 | nvme_del_queue_end(nvmeq); | |
1951 | } | |
1952 | ||
1953 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
1954 | { | |
1955 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
1956 | nvme_del_cq_work_handler); | |
1957 | } | |
1958 | ||
1959 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
1960 | { | |
1961 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1962 | cmdinfo.work); | |
1963 | int status = nvmeq->cmdinfo.status; | |
1964 | ||
1965 | if (!status) | |
1966 | status = nvme_delete_cq(nvmeq); | |
1967 | if (status) | |
1968 | nvme_del_queue_end(nvmeq); | |
1969 | } | |
1970 | ||
1971 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
1972 | { | |
1973 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
1974 | nvme_del_sq_work_handler); | |
1975 | } | |
1976 | ||
1977 | static void nvme_del_queue_start(struct kthread_work *work) | |
1978 | { | |
1979 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1980 | cmdinfo.work); | |
4d115420 KB |
1981 | if (nvme_delete_sq(nvmeq)) |
1982 | nvme_del_queue_end(nvmeq); | |
1983 | } | |
1984 | ||
1985 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1986 | { | |
1987 | int i; | |
1988 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
1989 | struct nvme_delq_ctx dq; | |
1990 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 1991 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
1992 | |
1993 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 1994 | dev_err(dev->dev, |
4d115420 KB |
1995 | "Failed to create queue del task\n"); |
1996 | for (i = dev->queue_count - 1; i > 0; i--) | |
1997 | nvme_disable_queue(dev, i); | |
1998 | return; | |
1999 | } | |
2000 | ||
2001 | dq.waiter = NULL; | |
2002 | atomic_set(&dq.refcount, 0); | |
2003 | dq.worker = &worker; | |
2004 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2005 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2006 | |
2007 | if (nvme_suspend_queue(nvmeq)) | |
2008 | continue; | |
2009 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2010 | nvmeq->cmdinfo.worker = dq.worker; | |
2011 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2012 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2013 | } | |
2014 | nvme_wait_dq(&dq, dev); | |
2015 | kthread_stop(kworker_task); | |
2016 | } | |
2017 | ||
b9afca3e DM |
2018 | /* |
2019 | * Remove the node from the device list and check | |
2020 | * for whether or not we need to stop the nvme_thread. | |
2021 | */ | |
2022 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2023 | { | |
2024 | struct task_struct *tmp = NULL; | |
2025 | ||
2026 | spin_lock(&dev_list_lock); | |
2027 | list_del_init(&dev->node); | |
2028 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2029 | tmp = nvme_thread; | |
2030 | nvme_thread = NULL; | |
2031 | } | |
2032 | spin_unlock(&dev_list_lock); | |
2033 | ||
2034 | if (tmp) | |
2035 | kthread_stop(tmp); | |
2036 | } | |
2037 | ||
c9d3bf88 KB |
2038 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2039 | { | |
2040 | struct nvme_ns *ns; | |
2041 | ||
5bae7f73 | 2042 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
2043 | blk_mq_freeze_queue_start(ns->queue); |
2044 | ||
cddcd72b | 2045 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2046 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2047 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2048 | |
2049 | blk_mq_cancel_requeue_work(ns->queue); | |
2050 | blk_mq_stop_hw_queues(ns->queue); | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2055 | { | |
2056 | struct nvme_ns *ns; | |
2057 | ||
5bae7f73 | 2058 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
2059 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); |
2060 | blk_mq_unfreeze_queue(ns->queue); | |
2061 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2062 | blk_mq_kick_requeue_list(ns->queue); | |
2063 | } | |
2064 | } | |
2065 | ||
f0b50732 | 2066 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2067 | { |
22404274 | 2068 | int i; |
7c1b2450 | 2069 | u32 csts = -1; |
22404274 | 2070 | |
b9afca3e | 2071 | nvme_dev_list_remove(dev); |
1fa6aead | 2072 | |
c9d3bf88 KB |
2073 | if (dev->bar) { |
2074 | nvme_freeze_queues(dev); | |
7a67cbea | 2075 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 2076 | } |
7c1b2450 | 2077 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2078 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2079 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2080 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2081 | } |
2082 | } else { | |
2083 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 2084 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
2085 | nvme_disable_queue(dev, 0); |
2086 | } | |
f0b50732 | 2087 | nvme_dev_unmap(dev); |
07836e65 KB |
2088 | |
2089 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2090 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2091 | } |
2092 | ||
091b6092 MW |
2093 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2094 | { | |
e75ec752 | 2095 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2096 | PAGE_SIZE, PAGE_SIZE, 0); |
2097 | if (!dev->prp_page_pool) | |
2098 | return -ENOMEM; | |
2099 | ||
99802a7a | 2100 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2101 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2102 | 256, 256, 0); |
2103 | if (!dev->prp_small_pool) { | |
2104 | dma_pool_destroy(dev->prp_page_pool); | |
2105 | return -ENOMEM; | |
2106 | } | |
091b6092 MW |
2107 | return 0; |
2108 | } | |
2109 | ||
2110 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2111 | { | |
2112 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2113 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2114 | } |
2115 | ||
cd58ad7d QSA |
2116 | static DEFINE_IDA(nvme_instance_ida); |
2117 | ||
2118 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2119 | { |
cd58ad7d QSA |
2120 | int instance, error; |
2121 | ||
2122 | do { | |
2123 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2124 | return -ENODEV; | |
2125 | ||
2126 | spin_lock(&dev_list_lock); | |
2127 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2128 | spin_unlock(&dev_list_lock); | |
2129 | } while (error == -EAGAIN); | |
2130 | ||
2131 | if (error) | |
2132 | return -ENODEV; | |
2133 | ||
1c63dc66 | 2134 | dev->ctrl.instance = instance; |
cd58ad7d | 2135 | return 0; |
b60503ba MW |
2136 | } |
2137 | ||
2138 | static void nvme_release_instance(struct nvme_dev *dev) | |
2139 | { | |
cd58ad7d | 2140 | spin_lock(&dev_list_lock); |
1c63dc66 | 2141 | ida_remove(&nvme_instance_ida, dev->ctrl.instance); |
cd58ad7d | 2142 | spin_unlock(&dev_list_lock); |
b60503ba MW |
2143 | } |
2144 | ||
1673f1f0 | 2145 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2146 | { |
1673f1f0 | 2147 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2148 | |
e75ec752 | 2149 | put_device(dev->dev); |
5bae7f73 | 2150 | put_device(ctrl->device); |
285dffc9 | 2151 | nvme_release_instance(dev); |
4af0e21c KB |
2152 | if (dev->tagset.tags) |
2153 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2154 | if (dev->ctrl.admin_q) |
2155 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
2156 | kfree(dev->queues); |
2157 | kfree(dev->entry); | |
2158 | kfree(dev); | |
2159 | } | |
2160 | ||
2161 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2162 | { | |
b3fffdef KB |
2163 | struct nvme_dev *dev; |
2164 | int instance = iminor(inode); | |
2165 | int ret = -ENODEV; | |
2166 | ||
2167 | spin_lock(&dev_list_lock); | |
2168 | list_for_each_entry(dev, &dev_list, node) { | |
1c63dc66 CH |
2169 | if (dev->ctrl.instance == instance) { |
2170 | if (!dev->ctrl.admin_q) { | |
2e1d8448 KB |
2171 | ret = -EWOULDBLOCK; |
2172 | break; | |
2173 | } | |
1673f1f0 | 2174 | if (!kref_get_unless_zero(&dev->ctrl.kref)) |
b3fffdef KB |
2175 | break; |
2176 | f->private_data = dev; | |
2177 | ret = 0; | |
2178 | break; | |
2179 | } | |
2180 | } | |
2181 | spin_unlock(&dev_list_lock); | |
2182 | ||
2183 | return ret; | |
5e82e952 KB |
2184 | } |
2185 | ||
2186 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2187 | { | |
2188 | struct nvme_dev *dev = f->private_data; | |
1673f1f0 | 2189 | nvme_put_ctrl(&dev->ctrl); |
5e82e952 KB |
2190 | return 0; |
2191 | } | |
2192 | ||
2193 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2194 | { | |
2195 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2196 | struct nvme_ns *ns; |
2197 | ||
5e82e952 KB |
2198 | switch (cmd) { |
2199 | case NVME_IOCTL_ADMIN_CMD: | |
1c63dc66 | 2200 | return nvme_user_cmd(&dev->ctrl, NULL, (void __user *)arg); |
7963e521 | 2201 | case NVME_IOCTL_IO_CMD: |
5bae7f73 | 2202 | if (list_empty(&dev->ctrl.namespaces)) |
a4aea562 | 2203 | return -ENOTTY; |
5bae7f73 | 2204 | ns = list_first_entry(&dev->ctrl.namespaces, struct nvme_ns, list); |
1c63dc66 | 2205 | return nvme_user_cmd(&dev->ctrl, ns, (void __user *)arg); |
4cc06521 KB |
2206 | case NVME_IOCTL_RESET: |
2207 | dev_warn(dev->dev, "resetting controller\n"); | |
2208 | return nvme_reset(dev); | |
81f03fed JD |
2209 | case NVME_IOCTL_SUBSYS_RESET: |
2210 | return nvme_subsys_reset(dev); | |
5e82e952 KB |
2211 | default: |
2212 | return -ENOTTY; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | static const struct file_operations nvme_dev_fops = { | |
2217 | .owner = THIS_MODULE, | |
2218 | .open = nvme_dev_open, | |
2219 | .release = nvme_dev_release, | |
2220 | .unlocked_ioctl = nvme_dev_ioctl, | |
2221 | .compat_ioctl = nvme_dev_ioctl, | |
2222 | }; | |
2223 | ||
3cf519b5 | 2224 | static void nvme_probe_work(struct work_struct *work) |
f0b50732 | 2225 | { |
3cf519b5 | 2226 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); |
b9afca3e | 2227 | bool start_thread = false; |
3cf519b5 | 2228 | int result; |
f0b50732 KB |
2229 | |
2230 | result = nvme_dev_map(dev); | |
2231 | if (result) | |
3cf519b5 | 2232 | goto out; |
f0b50732 KB |
2233 | |
2234 | result = nvme_configure_admin_queue(dev); | |
2235 | if (result) | |
2236 | goto unmap; | |
2237 | ||
2238 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2239 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2240 | start_thread = true; | |
2241 | nvme_thread = NULL; | |
2242 | } | |
f0b50732 KB |
2243 | list_add(&dev->node, &dev_list); |
2244 | spin_unlock(&dev_list_lock); | |
2245 | ||
b9afca3e DM |
2246 | if (start_thread) { |
2247 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2248 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2249 | } else |
2250 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2251 | ||
2252 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
2253 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2254 | goto disable; | |
2255 | } | |
a4aea562 MB |
2256 | |
2257 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
2258 | result = nvme_alloc_admin_tags(dev); |
2259 | if (result) | |
2260 | goto disable; | |
b9afca3e | 2261 | |
ce4541f4 CH |
2262 | result = nvme_init_identify(&dev->ctrl); |
2263 | if (result) | |
2264 | goto free_tags; | |
2265 | ||
f0b50732 | 2266 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2267 | if (result) |
0fb59cbc | 2268 | goto free_tags; |
f0b50732 | 2269 | |
1c63dc66 | 2270 | dev->ctrl.event_limit = 1; |
3cf519b5 | 2271 | |
2659e57b CH |
2272 | /* |
2273 | * Keep the controller around but remove all namespaces if we don't have | |
2274 | * any working I/O queue. | |
2275 | */ | |
3cf519b5 CH |
2276 | if (dev->online_queues < 2) { |
2277 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 2278 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 CH |
2279 | } else { |
2280 | nvme_unfreeze_queues(dev); | |
2281 | nvme_dev_add(dev); | |
2282 | } | |
2283 | ||
2284 | return; | |
f0b50732 | 2285 | |
0fb59cbc KB |
2286 | free_tags: |
2287 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2288 | blk_put_queue(dev->ctrl.admin_q); |
2289 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2290 | dev->queues[0]->tags = NULL; |
f0b50732 | 2291 | disable: |
a1a5ef99 | 2292 | nvme_disable_queue(dev, 0); |
b9afca3e | 2293 | nvme_dev_list_remove(dev); |
f0b50732 KB |
2294 | unmap: |
2295 | nvme_dev_unmap(dev); | |
3cf519b5 CH |
2296 | out: |
2297 | if (!work_busy(&dev->reset_work)) | |
2298 | nvme_dead_ctrl(dev); | |
f0b50732 KB |
2299 | } |
2300 | ||
9a6b9458 KB |
2301 | static int nvme_remove_dead_ctrl(void *arg) |
2302 | { | |
2303 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 2304 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2305 | |
2306 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2307 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 2308 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2309 | return 0; |
2310 | } | |
2311 | ||
de3eff2b KB |
2312 | static void nvme_dead_ctrl(struct nvme_dev *dev) |
2313 | { | |
2314 | dev_warn(dev->dev, "Device failed to resume\n"); | |
1673f1f0 | 2315 | kref_get(&dev->ctrl.kref); |
de3eff2b | 2316 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", |
1c63dc66 | 2317 | dev->ctrl.instance))) { |
de3eff2b KB |
2318 | dev_err(dev->dev, |
2319 | "Failed to start controller remove task\n"); | |
1673f1f0 | 2320 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
2321 | } |
2322 | } | |
2323 | ||
77b50d9e | 2324 | static void nvme_reset_work(struct work_struct *ws) |
9a6b9458 | 2325 | { |
77b50d9e | 2326 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
ffe7704d KB |
2327 | bool in_probe = work_busy(&dev->probe_work); |
2328 | ||
9a6b9458 | 2329 | nvme_dev_shutdown(dev); |
ffe7704d KB |
2330 | |
2331 | /* Synchronize with device probe so that work will see failure status | |
2332 | * and exit gracefully without trying to schedule another reset */ | |
2333 | flush_work(&dev->probe_work); | |
2334 | ||
2335 | /* Fail this device if reset occured during probe to avoid | |
2336 | * infinite initialization loops. */ | |
2337 | if (in_probe) { | |
de3eff2b | 2338 | nvme_dead_ctrl(dev); |
ffe7704d | 2339 | return; |
9a6b9458 | 2340 | } |
ffe7704d KB |
2341 | /* Schedule device resume asynchronously so the reset work is available |
2342 | * to cleanup errors that may occur during reinitialization */ | |
2343 | schedule_work(&dev->probe_work); | |
9a6b9458 KB |
2344 | } |
2345 | ||
90667892 | 2346 | static int __nvme_reset(struct nvme_dev *dev) |
9ca97374 | 2347 | { |
90667892 CH |
2348 | if (work_pending(&dev->reset_work)) |
2349 | return -EBUSY; | |
2350 | list_del_init(&dev->node); | |
2351 | queue_work(nvme_workq, &dev->reset_work); | |
2352 | return 0; | |
9ca97374 TH |
2353 | } |
2354 | ||
4cc06521 KB |
2355 | static int nvme_reset(struct nvme_dev *dev) |
2356 | { | |
90667892 | 2357 | int ret; |
4cc06521 | 2358 | |
1c63dc66 | 2359 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
2360 | return -ENODEV; |
2361 | ||
2362 | spin_lock(&dev_list_lock); | |
90667892 | 2363 | ret = __nvme_reset(dev); |
4cc06521 KB |
2364 | spin_unlock(&dev_list_lock); |
2365 | ||
2366 | if (!ret) { | |
2367 | flush_work(&dev->reset_work); | |
ffe7704d | 2368 | flush_work(&dev->probe_work); |
4cc06521 KB |
2369 | return 0; |
2370 | } | |
2371 | ||
2372 | return ret; | |
2373 | } | |
2374 | ||
2375 | static ssize_t nvme_sysfs_reset(struct device *dev, | |
2376 | struct device_attribute *attr, const char *buf, | |
2377 | size_t count) | |
2378 | { | |
2379 | struct nvme_dev *ndev = dev_get_drvdata(dev); | |
2380 | int ret; | |
2381 | ||
2382 | ret = nvme_reset(ndev); | |
2383 | if (ret < 0) | |
2384 | return ret; | |
2385 | ||
2386 | return count; | |
2387 | } | |
2388 | static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset); | |
2389 | ||
1c63dc66 CH |
2390 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
2391 | { | |
2392 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
2393 | return 0; | |
2394 | } | |
2395 | ||
5fd4ce1b CH |
2396 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
2397 | { | |
2398 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2399 | return 0; | |
2400 | } | |
2401 | ||
7fd8930f CH |
2402 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2403 | { | |
2404 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2405 | return 0; | |
2406 | } | |
2407 | ||
5bae7f73 CH |
2408 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2409 | { | |
2410 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2411 | ||
2412 | return !dev->bar || dev->online_queues < 2; | |
2413 | } | |
2414 | ||
1c63dc66 CH |
2415 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2416 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2417 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2418 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2419 | .io_incapable = nvme_pci_io_incapable, |
1673f1f0 | 2420 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2421 | }; |
2422 | ||
8d85fce7 | 2423 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2424 | { |
a4aea562 | 2425 | int node, result = -ENOMEM; |
b60503ba MW |
2426 | struct nvme_dev *dev; |
2427 | ||
a4aea562 MB |
2428 | node = dev_to_node(&pdev->dev); |
2429 | if (node == NUMA_NO_NODE) | |
2430 | set_dev_node(&pdev->dev, 0); | |
2431 | ||
2432 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2433 | if (!dev) |
2434 | return -ENOMEM; | |
a4aea562 MB |
2435 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2436 | GFP_KERNEL, node); | |
b60503ba MW |
2437 | if (!dev->entry) |
2438 | goto free; | |
a4aea562 MB |
2439 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2440 | GFP_KERNEL, node); | |
b60503ba MW |
2441 | if (!dev->queues) |
2442 | goto free; | |
2443 | ||
5bae7f73 | 2444 | INIT_LIST_HEAD(&dev->ctrl.namespaces); |
77b50d9e | 2445 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
e75ec752 | 2446 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2447 | pci_set_drvdata(pdev, dev); |
1c63dc66 CH |
2448 | |
2449 | dev->ctrl.ops = &nvme_pci_ctrl_ops; | |
2450 | dev->ctrl.dev = dev->dev; | |
106198ed | 2451 | dev->ctrl.quirks = id->driver_data; |
1c63dc66 | 2452 | |
cd58ad7d QSA |
2453 | result = nvme_set_instance(dev); |
2454 | if (result) | |
a96d4f5c | 2455 | goto put_pci; |
b60503ba | 2456 | |
091b6092 MW |
2457 | result = nvme_setup_prp_pools(dev); |
2458 | if (result) | |
0877cb0d | 2459 | goto release; |
091b6092 | 2460 | |
1673f1f0 | 2461 | kref_init(&dev->ctrl.kref); |
5bae7f73 | 2462 | dev->ctrl.device = device_create(nvme_class, &pdev->dev, |
1c63dc66 CH |
2463 | MKDEV(nvme_char_major, dev->ctrl.instance), |
2464 | dev, "nvme%d", dev->ctrl.instance); | |
5bae7f73 CH |
2465 | if (IS_ERR(dev->ctrl.device)) { |
2466 | result = PTR_ERR(dev->ctrl.device); | |
2e1d8448 | 2467 | goto release_pools; |
b3fffdef | 2468 | } |
5bae7f73 CH |
2469 | get_device(dev->ctrl.device); |
2470 | dev_set_drvdata(dev->ctrl.device, dev); | |
4cc06521 | 2471 | |
5bae7f73 | 2472 | result = device_create_file(dev->ctrl.device, &dev_attr_reset_controller); |
4cc06521 KB |
2473 | if (result) |
2474 | goto put_dev; | |
740216fc | 2475 | |
e6e96d73 | 2476 | INIT_LIST_HEAD(&dev->node); |
a5768aa8 | 2477 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
3cf519b5 | 2478 | INIT_WORK(&dev->probe_work, nvme_probe_work); |
2e1d8448 | 2479 | schedule_work(&dev->probe_work); |
b60503ba MW |
2480 | return 0; |
2481 | ||
4cc06521 | 2482 | put_dev: |
1c63dc66 | 2483 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance)); |
5bae7f73 | 2484 | put_device(dev->ctrl.device); |
0877cb0d | 2485 | release_pools: |
091b6092 | 2486 | nvme_release_prp_pools(dev); |
0877cb0d KB |
2487 | release: |
2488 | nvme_release_instance(dev); | |
a96d4f5c | 2489 | put_pci: |
e75ec752 | 2490 | put_device(dev->dev); |
b60503ba MW |
2491 | free: |
2492 | kfree(dev->queues); | |
2493 | kfree(dev->entry); | |
2494 | kfree(dev); | |
2495 | return result; | |
2496 | } | |
2497 | ||
f0d54a54 KB |
2498 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2499 | { | |
a6739479 | 2500 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2501 | |
a6739479 KB |
2502 | if (prepare) |
2503 | nvme_dev_shutdown(dev); | |
2504 | else | |
0a7385ad | 2505 | schedule_work(&dev->probe_work); |
f0d54a54 KB |
2506 | } |
2507 | ||
09ece142 KB |
2508 | static void nvme_shutdown(struct pci_dev *pdev) |
2509 | { | |
2510 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2511 | nvme_dev_shutdown(dev); | |
2512 | } | |
2513 | ||
8d85fce7 | 2514 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2515 | { |
2516 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2517 | |
2518 | spin_lock(&dev_list_lock); | |
2519 | list_del_init(&dev->node); | |
2520 | spin_unlock(&dev_list_lock); | |
2521 | ||
2522 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 2523 | flush_work(&dev->probe_work); |
9a6b9458 | 2524 | flush_work(&dev->reset_work); |
a5768aa8 | 2525 | flush_work(&dev->scan_work); |
5bae7f73 CH |
2526 | device_remove_file(dev->ctrl.device, &dev_attr_reset_controller); |
2527 | nvme_remove_namespaces(&dev->ctrl); | |
3399a3f7 | 2528 | nvme_dev_shutdown(dev); |
a4aea562 | 2529 | nvme_dev_remove_admin(dev); |
1c63dc66 | 2530 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance)); |
a1a5ef99 | 2531 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2532 | nvme_release_cmb(dev); |
9a6b9458 | 2533 | nvme_release_prp_pools(dev); |
1673f1f0 | 2534 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2535 | } |
2536 | ||
2537 | /* These functions are yet to be implemented */ | |
2538 | #define nvme_error_detected NULL | |
2539 | #define nvme_dump_registers NULL | |
2540 | #define nvme_link_reset NULL | |
2541 | #define nvme_slot_reset NULL | |
2542 | #define nvme_error_resume NULL | |
cd638946 | 2543 | |
671a6018 | 2544 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2545 | static int nvme_suspend(struct device *dev) |
2546 | { | |
2547 | struct pci_dev *pdev = to_pci_dev(dev); | |
2548 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2549 | ||
2550 | nvme_dev_shutdown(ndev); | |
2551 | return 0; | |
2552 | } | |
2553 | ||
2554 | static int nvme_resume(struct device *dev) | |
2555 | { | |
2556 | struct pci_dev *pdev = to_pci_dev(dev); | |
2557 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2558 | |
0a7385ad | 2559 | schedule_work(&ndev->probe_work); |
9a6b9458 | 2560 | return 0; |
cd638946 | 2561 | } |
671a6018 | 2562 | #endif |
cd638946 KB |
2563 | |
2564 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2565 | |
1d352035 | 2566 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2567 | .error_detected = nvme_error_detected, |
2568 | .mmio_enabled = nvme_dump_registers, | |
2569 | .link_reset = nvme_link_reset, | |
2570 | .slot_reset = nvme_slot_reset, | |
2571 | .resume = nvme_error_resume, | |
f0d54a54 | 2572 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2573 | }; |
2574 | ||
2575 | /* Move to pci_ids.h later */ | |
2576 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2577 | ||
6eb0d698 | 2578 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2579 | { PCI_VDEVICE(INTEL, 0x0953), |
2580 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
b60503ba | 2581 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2582 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2583 | { 0, } |
2584 | }; | |
2585 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2586 | ||
2587 | static struct pci_driver nvme_driver = { | |
2588 | .name = "nvme", | |
2589 | .id_table = nvme_id_table, | |
2590 | .probe = nvme_probe, | |
8d85fce7 | 2591 | .remove = nvme_remove, |
09ece142 | 2592 | .shutdown = nvme_shutdown, |
cd638946 KB |
2593 | .driver = { |
2594 | .pm = &nvme_dev_pm_ops, | |
2595 | }, | |
b60503ba MW |
2596 | .err_handler = &nvme_err_handler, |
2597 | }; | |
2598 | ||
2599 | static int __init nvme_init(void) | |
2600 | { | |
0ac13140 | 2601 | int result; |
1fa6aead | 2602 | |
b9afca3e | 2603 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2604 | |
9a6b9458 KB |
2605 | nvme_workq = create_singlethread_workqueue("nvme"); |
2606 | if (!nvme_workq) | |
b9afca3e | 2607 | return -ENOMEM; |
9a6b9458 | 2608 | |
5bae7f73 | 2609 | result = nvme_core_init(); |
5c42ea16 | 2610 | if (result < 0) |
9a6b9458 | 2611 | goto kill_workq; |
b60503ba | 2612 | |
b3fffdef KB |
2613 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
2614 | &nvme_dev_fops); | |
2615 | if (result < 0) | |
2616 | goto unregister_blkdev; | |
2617 | else if (result > 0) | |
2618 | nvme_char_major = result; | |
2619 | ||
2620 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
c727040b AK |
2621 | if (IS_ERR(nvme_class)) { |
2622 | result = PTR_ERR(nvme_class); | |
b3fffdef | 2623 | goto unregister_chrdev; |
c727040b | 2624 | } |
b3fffdef | 2625 | |
f3db22fe KB |
2626 | result = pci_register_driver(&nvme_driver); |
2627 | if (result) | |
b3fffdef | 2628 | goto destroy_class; |
1fa6aead | 2629 | return 0; |
b60503ba | 2630 | |
b3fffdef KB |
2631 | destroy_class: |
2632 | class_destroy(nvme_class); | |
2633 | unregister_chrdev: | |
2634 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 2635 | unregister_blkdev: |
5bae7f73 | 2636 | nvme_core_exit(); |
9a6b9458 KB |
2637 | kill_workq: |
2638 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2639 | return result; |
2640 | } | |
2641 | ||
2642 | static void __exit nvme_exit(void) | |
2643 | { | |
2644 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2645 | nvme_core_exit(); |
9a6b9458 | 2646 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
2647 | class_destroy(nvme_class); |
2648 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 2649 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2650 | _nvme_check_size(); |
b60503ba MW |
2651 | } |
2652 | ||
2653 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2654 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2655 | MODULE_VERSION("1.0"); |
b60503ba MW |
2656 | module_init(nvme_init); |
2657 | module_exit(nvme_exit); |