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Commit | Line | Data |
---|---|---|
327d8e4e AJ |
1 | /* |
2 | * OpenPOWER Palmetto BMC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
da34e65c | 13 | #include "qapi/error.h" |
12ec8bd5 | 14 | #include "hw/arm/boot.h" |
fca9ca1b | 15 | #include "hw/arm/aspeed.h" |
00442402 | 16 | #include "hw/arm/aspeed_soc.h" |
c0216b94 | 17 | #include "hw/arm/aspeed_eeprom.h" |
3ec75e39 | 18 | #include "hw/i2c/i2c_mux_pca954x.h" |
93198b6c | 19 | #include "hw/i2c/smbus_eeprom.h" |
044475f3 | 20 | #include "hw/misc/pca9552.h" |
9618ebae | 21 | #include "hw/nvram/eeprom_at24c.h" |
5e9ae4b1 | 22 | #include "hw/sensor/tmp105.h" |
7cfbde5e | 23 | #include "hw/misc/led.h" |
a27bd6c7 | 24 | #include "hw/qdev-properties.h" |
e1ad9bc4 | 25 | #include "sysemu/block-backend.h" |
fa699e80 | 26 | #include "sysemu/reset.h" |
d769a1da CLG |
27 | #include "hw/loader.h" |
28 | #include "qemu/error-report.h" | |
a9df9622 | 29 | #include "qemu/units.h" |
66c895b8 | 30 | #include "hw/qdev-clock.h" |
d2b3eaef | 31 | #include "sysemu/sysemu.h" |
327d8e4e | 32 | |
74fb1f38 | 33 | static struct arm_boot_info aspeed_board_binfo = { |
b033271f | 34 | .board_id = -1, /* device-tree-only board */ |
327d8e4e AJ |
35 | }; |
36 | ||
612b219a | 37 | struct AspeedMachineState { |
888b2b03 PMD |
38 | /* Private */ |
39 | MachineState parent_obj; | |
40 | /* Public */ | |
41 | ||
ff90606f | 42 | AspeedSoCState soc; |
262259ea | 43 | MemoryRegion boot_rom; |
888b2b03 | 44 | bool mmio_exec; |
f65f6ad5 | 45 | uint32_t uart_chosen; |
9820e52f CLG |
46 | char *fmc_model; |
47 | char *spi_model; | |
ea066d39 | 48 | }; |
327d8e4e | 49 | |
1e2c22c9 CLG |
50 | /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ |
51 | #if HOST_LONG_BITS == 32 | |
52 | #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) | |
53 | #else | |
54 | #define ASPEED_RAM_SIZE(sz) (sz) | |
55 | #endif | |
56 | ||
ef17f836 | 57 | /* Palmetto hardware value: 0x120CE416 */ |
8da33ef7 CLG |
58 | #define PALMETTO_BMC_HW_STRAP1 ( \ |
59 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ | |
60 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ | |
61 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
62 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
63 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
64 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
65 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
66 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
67 | SCU_HW_STRAP_SPI_WIDTH | \ | |
68 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
69 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
70 | ||
40a38df5 ES |
71 | /* TODO: Find the actual hardware value */ |
72 | #define SUPERMICROX11_BMC_HW_STRAP1 ( \ | |
73 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ | |
74 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ | |
75 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
76 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
77 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
78 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
79 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
80 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
81 | SCU_HW_STRAP_SPI_WIDTH | \ | |
82 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
83 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
84 | ||
47936597 GR |
85 | /* TODO: Find the actual hardware value */ |
86 | #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ | |
87 | AST2500_HW_STRAP1_DEFAULTS | \ | |
88 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
89 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
90 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
91 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
92 | SCU_HW_STRAP_SPI_WIDTH | \ | |
93 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) | |
94 | ||
ef17f836 | 95 | /* AST2500 evb hardware value: 0xF100C2E6 */ |
9a7c1750 CLG |
96 | #define AST2500_EVB_HW_STRAP1 (( \ |
97 | AST2500_HW_STRAP1_DEFAULTS | \ | |
98 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
99 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
100 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
101 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
102 | SCU_HW_STRAP_MAC1_RGMII | \ | |
103 | SCU_HW_STRAP_MAC0_RGMII) & \ | |
104 | ~SCU_HW_STRAP_2ND_BOOT_WDT) | |
105 | ||
ef17f836 CLG |
106 | /* Romulus hardware value: 0xF10AD206 */ |
107 | #define ROMULUS_BMC_HW_STRAP1 ( \ | |
108 | AST2500_HW_STRAP1_DEFAULTS | \ | |
109 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
110 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
111 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
112 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
113 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
114 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
115 | ||
143b040f PW |
116 | /* Sonorapass hardware value: 0xF100D216 */ |
117 | #define SONORAPASS_BMC_HW_STRAP1 ( \ | |
118 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
119 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
120 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
121 | SCU_AST2500_HW_STRAP_RESERVED28 | \ | |
122 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
123 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
124 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
125 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ | |
126 | SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ | |
127 | SCU_HW_STRAP_VGA_BIOS_ROM | \ | |
128 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
129 | SCU_AST2500_HW_STRAP_RESERVED1) | |
130 | ||
95f068c8 JW |
131 | #define G220A_BMC_HW_STRAP1 ( \ |
132 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
133 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
134 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
135 | SCU_AST2500_HW_STRAP_RESERVED28 | \ | |
136 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
137 | SCU_HW_STRAP_2ND_BOOT_WDT | \ | |
138 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
139 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
140 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ | |
141 | SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ | |
142 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ | |
143 | SCU_AST2500_HW_STRAP_RESERVED1) | |
144 | ||
82b6a3f6 JW |
145 | /* FP5280G2 hardware value: 0XF100D286 */ |
146 | #define FP5280G2_BMC_HW_STRAP1 ( \ | |
147 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
148 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
149 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
150 | SCU_AST2500_HW_STRAP_RESERVED28 | \ | |
151 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
152 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
153 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
154 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ | |
155 | SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ | |
156 | SCU_HW_STRAP_MAC1_RGMII | \ | |
157 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
158 | SCU_AST2500_HW_STRAP_RESERVED1) | |
159 | ||
62c2c2eb CLG |
160 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ |
161 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | |
162 | ||
9cccb912 PV |
163 | /* Quanta-Q71l hardware value */ |
164 | #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ | |
165 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ | |
166 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ | |
167 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
168 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ | |
169 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
170 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ | |
171 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
172 | SCU_HW_STRAP_SPI_WIDTH | \ | |
173 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ | |
174 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
175 | ||
ccc2c418 CLG |
176 | /* AST2600 evb hardware value */ |
177 | #define AST2600_EVB_HW_STRAP1 0x000000C0 | |
178 | #define AST2600_EVB_HW_STRAP2 0x00000003 | |
179 | ||
63ceb818 CLG |
180 | /* Tacoma hardware value */ |
181 | #define TACOMA_BMC_HW_STRAP1 0x00000000 | |
7582591a | 182 | #define TACOMA_BMC_HW_STRAP2 0x00000040 |
63ceb818 | 183 | |
58e52bdb | 184 | /* Rainier hardware value: (QEMU prototype) */ |
b6d1df64 JS |
185 | #define RAINIER_BMC_HW_STRAP1 0x00422016 |
186 | #define RAINIER_BMC_HW_STRAP2 0x80000848 | |
58e52bdb | 187 | |
febbe308 PD |
188 | /* Fuji hardware value */ |
189 | #define FUJI_BMC_HW_STRAP1 0x00000000 | |
190 | #define FUJI_BMC_HW_STRAP2 0x00000000 | |
191 | ||
a20c54b1 PW |
192 | /* Bletchley hardware value */ |
193 | /* TODO: Leave same as EVB for now. */ | |
194 | #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 | |
195 | #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 | |
196 | ||
fb6b3c8d JHY |
197 | /* Qualcomm DC-SCM hardware value */ |
198 | #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 | |
199 | #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 | |
200 | ||
9bb6d140 JS |
201 | #define AST_SMP_MAILBOX_BASE 0x1e6e2180 |
202 | #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) | |
203 | #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) | |
204 | #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) | |
205 | #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) | |
206 | #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) | |
207 | #define AST_SMP_MBOX_GOSIGN 0xabbaab00 | |
208 | ||
209 | static void aspeed_write_smpboot(ARMCPU *cpu, | |
210 | const struct arm_boot_info *info) | |
211 | { | |
902bba54 CLG |
212 | AddressSpace *as = arm_boot_address_space(cpu, info); |
213 | static const ARMInsnFixup poll_mailbox_ready[] = { | |
9bb6d140 JS |
214 | /* |
215 | * r2 = per-cpu go sign value | |
216 | * r1 = AST_SMP_MBOX_FIELD_ENTRY | |
217 | * r0 = AST_SMP_MBOX_FIELD_GOSIGN | |
218 | */ | |
902bba54 CLG |
219 | { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ |
220 | { 0xe21000ff }, /* ands r0, r0, #255 */ | |
221 | { 0xe59f201c }, /* ldr r2, [pc, #28] */ | |
222 | { 0xe1822000 }, /* orr r2, r2, r0 */ | |
223 | ||
224 | { 0xe59f1018 }, /* ldr r1, [pc, #24] */ | |
225 | { 0xe59f0018 }, /* ldr r0, [pc, #24] */ | |
226 | ||
227 | { 0xe320f002 }, /* wfe */ | |
228 | { 0xe5904000 }, /* ldr r4, [r0] */ | |
229 | { 0xe1520004 }, /* cmp r2, r4 */ | |
230 | { 0x1afffffb }, /* bne <wfe> */ | |
231 | { 0xe591f000 }, /* ldr pc, [r1] */ | |
232 | { AST_SMP_MBOX_GOSIGN }, | |
233 | { AST_SMP_MBOX_FIELD_ENTRY }, | |
234 | { AST_SMP_MBOX_FIELD_GOSIGN }, | |
235 | { 0, FIXUP_TERMINATOR } | |
9bb6d140 | 236 | }; |
902bba54 | 237 | static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; |
9bb6d140 | 238 | |
902bba54 CLG |
239 | arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, |
240 | poll_mailbox_ready, fixupcontext); | |
9bb6d140 JS |
241 | } |
242 | ||
243 | static void aspeed_reset_secondary(ARMCPU *cpu, | |
244 | const struct arm_boot_info *info) | |
245 | { | |
246 | AddressSpace *as = arm_boot_address_space(cpu, info); | |
247 | CPUState *cs = CPU(cpu); | |
248 | ||
249 | /* info->smp_bootreg_addr */ | |
250 | address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, | |
251 | MEMTXATTRS_UNSPECIFIED, NULL); | |
252 | cpu_set_pc(cs, info->smp_loader_start); | |
253 | } | |
254 | ||
8b744a6a | 255 | static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, |
d769a1da CLG |
256 | Error **errp) |
257 | { | |
05e6e40a | 258 | g_autofree void *storage = NULL; |
0c7209be CLG |
259 | int64_t size; |
260 | ||
261 | /* The block backend size should have already been 'validated' by | |
262 | * the creation of the m25p80 object. | |
263 | */ | |
264 | size = blk_getlength(blk); | |
265 | if (size <= 0) { | |
266 | error_setg(errp, "failed to get flash size"); | |
267 | return; | |
268 | } | |
d769a1da | 269 | |
0c7209be CLG |
270 | if (rom_size > size) { |
271 | rom_size = size; | |
d769a1da CLG |
272 | } |
273 | ||
05e6e40a | 274 | storage = g_malloc0(rom_size); |
a9262f55 | 275 | if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { |
d769a1da CLG |
276 | error_setg(errp, "failed to read the initial flash content"); |
277 | return; | |
278 | } | |
279 | ||
280 | rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); | |
d769a1da CLG |
281 | } |
282 | ||
8b744a6a CLG |
283 | /* |
284 | * Create a ROM and copy the flash contents at the expected address | |
285 | * (0x0). Boots faster than execute-in-place. | |
286 | */ | |
262259ea | 287 | static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, |
8b744a6a CLG |
288 | uint64_t rom_size) |
289 | { | |
262259ea | 290 | AspeedSoCState *soc = &bmc->soc; |
8b744a6a | 291 | |
262259ea | 292 | memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, |
8b744a6a CLG |
293 | &error_abort); |
294 | memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, | |
262259ea | 295 | &bmc->boot_rom, 1); |
8b744a6a CLG |
296 | write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); |
297 | } | |
298 | ||
1099ad10 | 299 | void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
9bd4ac61 | 300 | unsigned int count, int unit0) |
e1ad9bc4 | 301 | { |
179b2058 PW |
302 | int i; |
303 | ||
304 | if (!flashtype) { | |
305 | return; | |
306 | } | |
e1ad9bc4 | 307 | |
9bd4ac61 | 308 | for (i = 0; i < count; ++i) { |
8ec239f2 | 309 | DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); |
e1ad9bc4 | 310 | qemu_irq cs_line; |
a7d78bef | 311 | DeviceState *dev; |
e1ad9bc4 | 312 | |
a7d78bef | 313 | dev = qdev_new(flashtype); |
e1ad9bc4 | 314 | if (dinfo) { |
a7d78bef | 315 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
e1ad9bc4 | 316 | } |
a7d78bef | 317 | qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); |
e1ad9bc4 | 318 | |
a7d78bef | 319 | cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); |
b22a2d40 | 320 | qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); |
e1ad9bc4 CLG |
321 | } |
322 | } | |
323 | ||
a29e3e12 AJ |
324 | static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) |
325 | { | |
326 | DeviceState *card; | |
327 | ||
756f739b PMD |
328 | if (!dinfo) { |
329 | return; | |
a29e3e12 | 330 | } |
756f739b PMD |
331 | card = qdev_new(TYPE_SD_CARD); |
332 | qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), | |
333 | &error_fatal); | |
3e80f690 MA |
334 | qdev_realize_and_unref(card, |
335 | qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | |
336 | &error_fatal); | |
a29e3e12 AJ |
337 | } |
338 | ||
d2b3eaef PD |
339 | static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) |
340 | { | |
341 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); | |
342 | AspeedSoCState *s = &bmc->soc; | |
343 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
f65f6ad5 | 344 | int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; |
d2b3eaef | 345 | |
f65f6ad5 | 346 | aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); |
d2b3eaef | 347 | for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { |
f65f6ad5 | 348 | if (uart == uart_chosen) { |
d2b3eaef PD |
349 | continue; |
350 | } | |
351 | aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); | |
352 | } | |
353 | } | |
354 | ||
baa4732b | 355 | static void aspeed_machine_init(MachineState *machine) |
327d8e4e | 356 | { |
888b2b03 | 357 | AspeedMachineState *bmc = ASPEED_MACHINE(machine); |
baa4732b | 358 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
b033271f | 359 | AspeedSoCClass *sc; |
2bea128c | 360 | int i; |
d3bad7e7 | 361 | NICInfo *nd = &nd_table[0]; |
327d8e4e | 362 | |
9fc7fc4d | 363 | object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); |
327d8e4e | 364 | |
b033271f CLG |
365 | sc = ASPEED_SOC_GET_CLASS(&bmc->soc); |
366 | ||
533eb415 | 367 | /* |
346160cb CLG |
368 | * This will error out if the RAM size is not supported by the |
369 | * memory controller of the SoC. | |
533eb415 | 370 | */ |
6e504a98 | 371 | object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, |
533eb415 IM |
372 | &error_fatal); |
373 | ||
d3bad7e7 CLG |
374 | for (i = 0; i < sc->macs_num; i++) { |
375 | if ((amc->macs_mask & (1 << i)) && nd->used) { | |
376 | qemu_check_nic_model(nd, TYPE_FTGMAC100); | |
377 | qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); | |
378 | nd++; | |
379 | } | |
380 | } | |
381 | ||
5325cc34 | 382 | object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, |
87e79af0 | 383 | &error_abort); |
5325cc34 | 384 | object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, |
ccc2c418 | 385 | &error_abort); |
4dd9d554 PD |
386 | object_property_set_link(OBJECT(&bmc->soc), "memory", |
387 | OBJECT(get_system_memory()), &error_abort); | |
5325cc34 | 388 | object_property_set_link(OBJECT(&bmc->soc), "dram", |
0df2d9a6 | 389 | OBJECT(machine->ram), &error_abort); |
b6e70d1d JS |
390 | if (machine->kernel_filename) { |
391 | /* | |
392 | * When booting with a -kernel command line there is no u-boot | |
393 | * that runs to unlock the SCU. In this case set the default to | |
394 | * be unlocked as the kernel expects | |
395 | */ | |
5325cc34 MA |
396 | object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", |
397 | ASPEED_SCU_PROT_KEY, &error_abort); | |
b6e70d1d | 398 | } |
d2b3eaef | 399 | connect_serial_hds_to_uarts(bmc); |
ce189ab2 | 400 | qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); |
327d8e4e | 401 | |
8ec239f2 MA |
402 | aspeed_board_init_flashes(&bmc->soc.fmc, |
403 | bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, | |
9bd4ac61 | 404 | amc->num_cs, 0); |
8ec239f2 MA |
405 | aspeed_board_init_flashes(&bmc->soc.spi[0], |
406 | bmc->spi_model ? bmc->spi_model : amc->spi_model, | |
9bd4ac61 | 407 | 1, amc->num_cs); |
74fb1f38 | 408 | |
b7f1a0cb | 409 | if (machine->kernel_filename && sc->num_cpus > 1) { |
9bb6d140 JS |
410 | /* With no u-boot we must set up a boot stub for the secondary CPU */ |
411 | MemoryRegion *smpboot = g_new(MemoryRegion, 1); | |
f489960d | 412 | memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", |
9bb6d140 JS |
413 | 0x80, &error_abort); |
414 | memory_region_add_subregion(get_system_memory(), | |
415 | AST_SMP_MAILBOX_BASE, smpboot); | |
416 | ||
417 | aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; | |
418 | aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; | |
419 | aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; | |
420 | } | |
421 | ||
6e504a98 | 422 | aspeed_board_binfo.ram_size = machine->ram_size; |
347df6f8 | 423 | aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; |
e1ad9bc4 | 424 | |
baa4732b CLG |
425 | if (amc->i2c_init) { |
426 | amc->i2c_init(bmc); | |
2cf6cb50 CLG |
427 | } |
428 | ||
0e2c24c6 | 429 | for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { |
8ec239f2 MA |
430 | sdhci_attach_drive(&bmc->soc.sdhci.slots[i], |
431 | drive_get(IF_SD, 0, i)); | |
a29e3e12 | 432 | } |
2bea128c | 433 | |
a29e3e12 | 434 | if (bmc->soc.emmc.num_slots) { |
8ec239f2 MA |
435 | sdhci_attach_drive(&bmc->soc.emmc.slots[0], |
436 | drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); | |
2bea128c EJ |
437 | } |
438 | ||
8b744a6a CLG |
439 | if (!bmc->mmio_exec) { |
440 | DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0); | |
441 | ||
442 | if (mtd0) { | |
443 | uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot); | |
262259ea | 444 | aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size); |
8b744a6a CLG |
445 | } |
446 | } | |
447 | ||
2744ece8 | 448 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); |
74fb1f38 | 449 | } |
b033271f | 450 | |
612b219a | 451 | static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) |
2cf6cb50 CLG |
452 | { |
453 | AspeedSoCState *soc = &bmc->soc; | |
a87e81b9 | 454 | DeviceState *dev; |
3d165f12 | 455 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
2cf6cb50 CLG |
456 | |
457 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | |
458 | * enough to provide basic RTC features. Alarms will be missing */ | |
1373b15b | 459 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); |
a87e81b9 | 460 | |
7a204cbd | 461 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, |
3d165f12 CLG |
462 | eeprom_buf); |
463 | ||
a87e81b9 | 464 | /* add a TMP423 temperature sensor */ |
1373b15b PMD |
465 | dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), |
466 | "tmp423", 0x4c)); | |
5325cc34 MA |
467 | object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); |
468 | object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | |
469 | object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | |
470 | object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); | |
2cf6cb50 CLG |
471 | } |
472 | ||
9cccb912 PV |
473 | static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) |
474 | { | |
475 | AspeedSoCState *soc = &bmc->soc; | |
476 | ||
477 | /* | |
478 | * The quanta-q71l platform expects tmp75s which are compatible with | |
479 | * tmp105s. | |
480 | */ | |
481 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); | |
482 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); | |
483 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); | |
484 | ||
485 | /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ | |
486 | /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ | |
487 | /* TODO: Add Memory Riser i2c mux and eeproms. */ | |
488 | ||
3ec75e39 PV |
489 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); |
490 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); | |
491 | ||
9cccb912 | 492 | /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ |
3ec75e39 PV |
493 | |
494 | /* i2c-7 */ | |
495 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); | |
9cccb912 PV |
496 | /* - i2c@0: pmbus@59 */ |
497 | /* - i2c@1: pmbus@58 */ | |
498 | /* - i2c@2: pmbus@58 */ | |
499 | /* - i2c@3: pmbus@59 */ | |
3ec75e39 | 500 | |
9cccb912 PV |
501 | /* TODO: i2c-7: Add PDB FRU eeprom@52 */ |
502 | /* TODO: i2c-8: Add BMC FRU eeprom@50 */ | |
503 | } | |
504 | ||
612b219a | 505 | static void ast2500_evb_i2c_init(AspeedMachineState *bmc) |
2cf6cb50 CLG |
506 | { |
507 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 CLG |
508 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
509 | ||
7a204cbd | 510 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, |
3d165f12 | 511 | eeprom_buf); |
2cf6cb50 CLG |
512 | |
513 | /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ | |
1373b15b | 514 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), |
044475f3 | 515 | TYPE_TMP105, 0x4d); |
2cf6cb50 CLG |
516 | } |
517 | ||
612b219a | 518 | static void ast2600_evb_i2c_init(AspeedMachineState *bmc) |
ccc2c418 | 519 | { |
52bcd997 HC |
520 | AspeedSoCState *soc = &bmc->soc; |
521 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | |
522 | ||
523 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, | |
524 | eeprom_buf); | |
525 | ||
526 | /* LM75 is compatible with TMP105 driver */ | |
527 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), | |
528 | TYPE_TMP105, 0x4d); | |
ccc2c418 CLG |
529 | } |
530 | ||
34f73a81 KP |
531 | static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) |
532 | { | |
533 | AspeedSoCState *soc = &bmc->soc; | |
534 | ||
535 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); | |
536 | at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, | |
537 | yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); | |
0a1f86ba KP |
538 | /* TMP421 */ |
539 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); | |
540 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); | |
541 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); | |
542 | ||
34f73a81 KP |
543 | } |
544 | ||
612b219a | 545 | static void romulus_bmc_i2c_init(AspeedMachineState *bmc) |
6c4567c7 CLG |
546 | { |
547 | AspeedSoCState *soc = &bmc->soc; | |
548 | ||
549 | /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is | |
550 | * good enough */ | |
1373b15b | 551 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); |
6c4567c7 CLG |
552 | } |
553 | ||
6c323aba KP |
554 | static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) |
555 | { | |
556 | AspeedSoCState *soc = &bmc->soc; | |
557 | ||
558 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); | |
559 | at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, | |
560 | tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); | |
a09d357d KP |
561 | /* TMP421 */ |
562 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); | |
563 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); | |
564 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); | |
6c323aba KP |
565 | } |
566 | ||
f4aec252 CLG |
567 | static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) |
568 | { | |
569 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), | |
570 | TYPE_PCA9552, addr); | |
571 | } | |
572 | ||
612b219a | 573 | static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) |
143b040f PW |
574 | { |
575 | AspeedSoCState *soc = &bmc->soc; | |
576 | ||
577 | /* bus 2 : */ | |
1373b15b PMD |
578 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); |
579 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); | |
143b040f PW |
580 | /* bus 2 : pca9546 @ 0x73 */ |
581 | ||
582 | /* bus 3 : pca9548 @ 0x70 */ | |
583 | ||
584 | /* bus 4 : */ | |
585 | uint8_t *eeprom4_54 = g_malloc0(8 * 1024); | |
7a204cbd | 586 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, |
143b040f PW |
587 | eeprom4_54); |
588 | /* PCA9539 @ 0x76, but PCA9552 is compatible */ | |
f4aec252 | 589 | create_pca9552(soc, 4, 0x76); |
143b040f | 590 | /* PCA9539 @ 0x77, but PCA9552 is compatible */ |
f4aec252 | 591 | create_pca9552(soc, 4, 0x77); |
143b040f PW |
592 | |
593 | /* bus 6 : */ | |
1373b15b PMD |
594 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); |
595 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); | |
143b040f PW |
596 | /* bus 6 : pca9546 @ 0x73 */ |
597 | ||
598 | /* bus 8 : */ | |
599 | uint8_t *eeprom8_56 = g_malloc0(8 * 1024); | |
7a204cbd | 600 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, |
143b040f | 601 | eeprom8_56); |
f4aec252 CLG |
602 | create_pca9552(soc, 8, 0x60); |
603 | create_pca9552(soc, 8, 0x61); | |
143b040f PW |
604 | /* bus 8 : adc128d818 @ 0x1d */ |
605 | /* bus 8 : adc128d818 @ 0x1f */ | |
606 | ||
607 | /* | |
608 | * bus 13 : pca9548 @ 0x71 | |
609 | * - channel 3: | |
610 | * - tmm421 @ 0x4c | |
611 | * - tmp421 @ 0x4e | |
612 | * - tmp421 @ 0x4f | |
613 | */ | |
614 | ||
615 | } | |
616 | ||
612b219a | 617 | static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) |
62c2c2eb | 618 | { |
7cfbde5e PMD |
619 | static const struct { |
620 | unsigned gpio_id; | |
621 | LEDColor color; | |
622 | const char *description; | |
623 | bool gpio_polarity; | |
624 | } pca1_leds[] = { | |
625 | {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, | |
626 | {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, | |
627 | {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, | |
628 | }; | |
62c2c2eb | 629 | AspeedSoCState *soc = &bmc->soc; |
3d165f12 | 630 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
15ce12cf | 631 | DeviceState *dev; |
7cfbde5e | 632 | LEDState *led; |
62c2c2eb | 633 | |
63ceb818 | 634 | /* Bus 3: TODO bmp280@77 */ |
db437ca6 | 635 | dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); |
15ce12cf | 636 | qdev_prop_set_string(dev, "description", "pca1"); |
2616f572 PMD |
637 | i2c_slave_realize_and_unref(I2C_SLAVE(dev), |
638 | aspeed_i2c_get_bus(&soc->i2c, 3), | |
639 | &error_fatal); | |
8c9a61d7 | 640 | |
7cfbde5e PMD |
641 | for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { |
642 | led = led_create_simple(OBJECT(bmc), | |
643 | pca1_leds[i].gpio_polarity, | |
644 | pca1_leds[i].color, | |
645 | pca1_leds[i].description); | |
646 | qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, | |
647 | qdev_get_gpio_in(DEVICE(led), 0)); | |
648 | } | |
b61ea6e7 | 649 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); |
2a75e8c3 | 650 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); |
1373b15b PMD |
651 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); |
652 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); | |
62c2c2eb CLG |
653 | |
654 | /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ | |
1373b15b | 655 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, |
044475f3 | 656 | 0x4a); |
6c4567c7 CLG |
657 | |
658 | /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is | |
659 | * good enough */ | |
1373b15b | 660 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); |
3d165f12 | 661 | |
7a204cbd | 662 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, |
3d165f12 | 663 | eeprom_buf); |
db437ca6 | 664 | dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); |
15ce12cf | 665 | qdev_prop_set_string(dev, "description", "pca0"); |
2616f572 PMD |
666 | i2c_slave_realize_and_unref(I2C_SLAVE(dev), |
667 | aspeed_i2c_get_bus(&soc->i2c, 11), | |
668 | &error_fatal); | |
63ceb818 | 669 | /* Bus 11: TODO ucd90160@64 */ |
62c2c2eb CLG |
670 | } |
671 | ||
95f068c8 JW |
672 | static void g220a_bmc_i2c_init(AspeedMachineState *bmc) |
673 | { | |
674 | AspeedSoCState *soc = &bmc->soc; | |
675 | DeviceState *dev; | |
676 | ||
677 | dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), | |
678 | "emc1413", 0x4c)); | |
679 | object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | |
680 | object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | |
681 | object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | |
682 | ||
683 | dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), | |
684 | "emc1413", 0x4c)); | |
685 | object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | |
686 | object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | |
687 | object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | |
688 | ||
689 | dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), | |
690 | "emc1413", 0x4c)); | |
691 | object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | |
692 | object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | |
693 | object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | |
6f5f6507 JW |
694 | |
695 | static uint8_t eeprom_buf[2 * 1024] = { | |
696 | 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, | |
697 | 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, | |
698 | 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, | |
699 | 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, | |
700 | 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, | |
701 | 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, | |
702 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, | |
703 | }; | |
704 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, | |
705 | eeprom_buf); | |
95f068c8 JW |
706 | } |
707 | ||
82b6a3f6 JW |
708 | static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) |
709 | { | |
710 | AspeedSoCState *soc = &bmc->soc; | |
711 | I2CSlave *i2c_mux; | |
712 | ||
713 | /* The at24c256 */ | |
714 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); | |
715 | ||
716 | /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ | |
717 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, | |
718 | 0x48); | |
719 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, | |
720 | 0x49); | |
721 | ||
722 | i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), | |
723 | "pca9546", 0x70); | |
724 | /* It expects a TMP112 but a TMP105 is compatible */ | |
725 | i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, | |
726 | 0x4a); | |
727 | ||
728 | /* It expects a ds3232 but a ds1338 is good enough */ | |
729 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); | |
730 | ||
731 | /* It expects a pca9555 but a pca9552 is compatible */ | |
f4aec252 | 732 | create_pca9552(soc, 8, 0x30); |
82b6a3f6 JW |
733 | } |
734 | ||
58e52bdb CLG |
735 | static void rainier_bmc_i2c_init(AspeedMachineState *bmc) |
736 | { | |
737 | AspeedSoCState *soc = &bmc->soc; | |
fa6d98c0 JS |
738 | I2CSlave *i2c_mux; |
739 | ||
9077e09a | 740 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); |
58e52bdb | 741 | |
f4aec252 | 742 | create_pca9552(soc, 3, 0x61); |
bcb122f8 | 743 | |
58e52bdb CLG |
744 | /* The rainier expects a TMP275 but a TMP105 is compatible */ |
745 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, | |
746 | 0x48); | |
747 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, | |
748 | 0x49); | |
749 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, | |
750 | 0x4a); | |
fa6d98c0 JS |
751 | i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), |
752 | "pca9546", 0x70); | |
9077e09a PD |
753 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
754 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); | |
755 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); | |
f4aec252 | 756 | create_pca9552(soc, 4, 0x60); |
58e52bdb CLG |
757 | |
758 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, | |
759 | 0x48); | |
760 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, | |
761 | 0x49); | |
f4aec252 CLG |
762 | create_pca9552(soc, 5, 0x60); |
763 | create_pca9552(soc, 5, 0x61); | |
fa6d98c0 JS |
764 | i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), |
765 | "pca9546", 0x70); | |
9077e09a PD |
766 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
767 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); | |
58e52bdb CLG |
768 | |
769 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, | |
770 | 0x48); | |
771 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, | |
772 | 0x4a); | |
773 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, | |
774 | 0x4b); | |
fa6d98c0 JS |
775 | i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), |
776 | "pca9546", 0x70); | |
9077e09a PD |
777 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
778 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); | |
779 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); | |
780 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); | |
58e52bdb | 781 | |
f4aec252 CLG |
782 | create_pca9552(soc, 7, 0x30); |
783 | create_pca9552(soc, 7, 0x31); | |
784 | create_pca9552(soc, 7, 0x32); | |
785 | create_pca9552(soc, 7, 0x33); | |
f4aec252 CLG |
786 | create_pca9552(soc, 7, 0x60); |
787 | create_pca9552(soc, 7, 0x61); | |
b61ea6e7 | 788 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); |
58e52bdb CLG |
789 | /* Bus 7: TODO si7021-a20@20 */ |
790 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, | |
791 | 0x48); | |
2a75e8c3 | 792 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); |
9077e09a PD |
793 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); |
794 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); | |
58e52bdb CLG |
795 | |
796 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, | |
797 | 0x48); | |
798 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, | |
799 | 0x4a); | |
be85508f NP |
800 | at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, |
801 | 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); | |
802 | at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, | |
803 | 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); | |
f4aec252 CLG |
804 | create_pca9552(soc, 8, 0x60); |
805 | create_pca9552(soc, 8, 0x61); | |
58e52bdb CLG |
806 | /* Bus 8: ucd90320@11 */ |
807 | /* Bus 8: ucd90320@b */ | |
808 | /* Bus 8: ucd90320@c */ | |
809 | ||
810 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); | |
811 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); | |
9077e09a | 812 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); |
58e52bdb CLG |
813 | |
814 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); | |
815 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); | |
9077e09a | 816 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); |
58e52bdb CLG |
817 | |
818 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, | |
819 | 0x48); | |
820 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, | |
821 | 0x49); | |
fa6d98c0 JS |
822 | i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), |
823 | "pca9546", 0x70); | |
9077e09a PD |
824 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
825 | at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); | |
f4aec252 | 826 | create_pca9552(soc, 11, 0x60); |
fa6d98c0 JS |
827 | |
828 | ||
9077e09a | 829 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); |
f4aec252 | 830 | create_pca9552(soc, 13, 0x60); |
fa6d98c0 | 831 | |
9077e09a | 832 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); |
f4aec252 | 833 | create_pca9552(soc, 14, 0x60); |
fa6d98c0 | 834 | |
9077e09a | 835 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); |
f4aec252 | 836 | create_pca9552(soc, 15, 0x60); |
58e52bdb CLG |
837 | } |
838 | ||
febbe308 PD |
839 | static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, |
840 | I2CBus **channels) | |
841 | { | |
842 | I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); | |
843 | for (int i = 0; i < 8; i++) { | |
844 | channels[i] = pca954x_i2c_get_bus(mux, i); | |
845 | } | |
846 | } | |
847 | ||
848 | #define TYPE_LM75 TYPE_TMP105 | |
849 | #define TYPE_TMP75 TYPE_TMP105 | |
850 | #define TYPE_TMP422 "tmp422" | |
851 | ||
852 | static void fuji_bmc_i2c_init(AspeedMachineState *bmc) | |
853 | { | |
854 | AspeedSoCState *soc = &bmc->soc; | |
855 | I2CBus *i2c[144] = {}; | |
856 | ||
857 | for (int i = 0; i < 16; i++) { | |
858 | i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); | |
859 | } | |
860 | I2CBus *i2c180 = i2c[2]; | |
861 | I2CBus *i2c480 = i2c[8]; | |
862 | I2CBus *i2c600 = i2c[11]; | |
863 | ||
864 | get_pca9548_channels(i2c180, 0x70, &i2c[16]); | |
865 | get_pca9548_channels(i2c480, 0x70, &i2c[24]); | |
866 | /* NOTE: The device tree skips [32, 40) in the alias numbering */ | |
867 | get_pca9548_channels(i2c600, 0x77, &i2c[40]); | |
868 | get_pca9548_channels(i2c[24], 0x71, &i2c[48]); | |
869 | get_pca9548_channels(i2c[25], 0x72, &i2c[56]); | |
870 | get_pca9548_channels(i2c[26], 0x76, &i2c[64]); | |
871 | get_pca9548_channels(i2c[27], 0x76, &i2c[72]); | |
872 | for (int i = 0; i < 8; i++) { | |
873 | get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); | |
874 | } | |
875 | ||
876 | i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); | |
877 | i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); | |
878 | ||
ef0eb67e SS |
879 | /* |
880 | * EEPROM 24c64 size is 64Kbits or 8 Kbytes | |
881 | * 24c02 size is 2Kbits or 256 bytes | |
882 | */ | |
883 | at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); | |
884 | at24c_eeprom_init(i2c[20], 0x50, 256); | |
885 | at24c_eeprom_init(i2c[22], 0x52, 256); | |
febbe308 PD |
886 | |
887 | i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); | |
888 | i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); | |
889 | i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); | |
890 | i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); | |
891 | ||
ef0eb67e | 892 | at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); |
febbe308 PD |
893 | i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); |
894 | ||
895 | i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); | |
ef0eb67e | 896 | at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); |
febbe308 PD |
897 | i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); |
898 | i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); | |
899 | ||
900 | i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); | |
901 | i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); | |
902 | ||
ef0eb67e | 903 | at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); |
febbe308 PD |
904 | i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); |
905 | i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); | |
ef0eb67e SS |
906 | at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); |
907 | at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); | |
908 | at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); | |
909 | at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); | |
febbe308 | 910 | |
ef0eb67e | 911 | at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); |
febbe308 PD |
912 | i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); |
913 | i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); | |
ef0eb67e SS |
914 | at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); |
915 | at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); | |
916 | at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); | |
917 | at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); | |
918 | at24c_eeprom_init(i2c[28], 0x50, 256); | |
febbe308 PD |
919 | |
920 | for (int i = 0; i < 8; i++) { | |
9077e09a | 921 | at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); |
febbe308 PD |
922 | i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); |
923 | i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); | |
924 | i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); | |
925 | } | |
926 | } | |
927 | ||
a20c54b1 PW |
928 | #define TYPE_TMP421 "tmp421" |
929 | ||
930 | static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) | |
931 | { | |
932 | AspeedSoCState *soc = &bmc->soc; | |
933 | I2CBus *i2c[13] = {}; | |
934 | for (int i = 0; i < 13; i++) { | |
935 | if ((i == 8) || (i == 11)) { | |
936 | continue; | |
937 | } | |
938 | i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); | |
939 | } | |
940 | ||
941 | /* Bus 0 - 5 all have the same config. */ | |
942 | for (int i = 0; i < 6; i++) { | |
943 | /* Missing model: ti,ina230 @ 0x45 */ | |
944 | /* Missing model: mps,mp5023 @ 0x40 */ | |
945 | i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); | |
946 | /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ | |
947 | i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); | |
948 | i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); | |
949 | /* Missing model: fsc,fusb302 @ 0x22 */ | |
950 | } | |
951 | ||
952 | /* Bus 6 */ | |
953 | at24c_eeprom_init(i2c[6], 0x56, 65536); | |
954 | /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ | |
955 | i2c_slave_create_simple(i2c[6], "ds1338", 0x51); | |
956 | ||
957 | ||
958 | /* Bus 7 */ | |
959 | at24c_eeprom_init(i2c[7], 0x54, 65536); | |
960 | ||
961 | /* Bus 9 */ | |
962 | i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); | |
963 | ||
964 | /* Bus 10 */ | |
965 | i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); | |
966 | /* Missing model: ti,hdc1080 @ 0x40 */ | |
967 | i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); | |
968 | ||
969 | /* Bus 12 */ | |
970 | /* Missing model: adi,adm1278 @ 0x11 */ | |
971 | i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); | |
972 | i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); | |
973 | i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); | |
974 | } | |
975 | ||
fa699e80 PD |
976 | static void fby35_i2c_init(AspeedMachineState *bmc) |
977 | { | |
978 | AspeedSoCState *soc = &bmc->soc; | |
979 | I2CBus *i2c[16]; | |
980 | ||
981 | for (int i = 0; i < 16; i++) { | |
982 | i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); | |
983 | } | |
984 | ||
985 | i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); | |
986 | i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); | |
987 | /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ | |
988 | i2c_slave_create_simple(i2c[11], "adm1272", 0x44); | |
989 | i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); | |
990 | i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); | |
991 | ||
9077e09a PD |
992 | at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); |
993 | at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); | |
c0216b94 PD |
994 | at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, |
995 | fby35_nic_fruid_len); | |
996 | at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, | |
997 | fby35_bb_fruid_len); | |
998 | at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, | |
999 | fby35_bmc_fruid_len); | |
fa699e80 PD |
1000 | |
1001 | /* | |
1002 | * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on | |
1003 | * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on | |
1004 | * each. | |
1005 | */ | |
1006 | } | |
1007 | ||
fb6b3c8d JHY |
1008 | static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) |
1009 | { | |
1010 | AspeedSoCState *soc = &bmc->soc; | |
1011 | ||
1012 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); | |
1013 | } | |
1014 | ||
ece4cccd GG |
1015 | static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) |
1016 | { | |
1017 | AspeedSoCState *soc = &bmc->soc; | |
2a7a5d5c | 1018 | I2CSlave *therm_mux, *cpuvr_mux; |
ece4cccd GG |
1019 | |
1020 | /* Create the generic DC-SCM hardware */ | |
1021 | qcom_dc_scm_bmc_i2c_init(bmc); | |
1022 | ||
1023 | /* Now create the Firework specific hardware */ | |
2a75e8c3 | 1024 | |
2a7a5d5c JHY |
1025 | /* I2C7 CPUVR MUX */ |
1026 | cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), | |
1027 | "pca9546", 0x70); | |
1028 | i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); | |
1029 | i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); | |
1030 | i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); | |
1031 | i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); | |
1032 | ||
cfc68f16 MK |
1033 | /* I2C8 Thermal Diodes*/ |
1034 | therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), | |
1035 | "pca9548", 0x70); | |
1036 | i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); | |
1037 | i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); | |
1038 | i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); | |
1039 | i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); | |
1040 | i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); | |
1041 | ||
2a75e8c3 MK |
1042 | /* I2C9 Fan Controller (MAX31785) */ |
1043 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); | |
1044 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); | |
ece4cccd GG |
1045 | } |
1046 | ||
1a15311a CLG |
1047 | static bool aspeed_get_mmio_exec(Object *obj, Error **errp) |
1048 | { | |
1049 | return ASPEED_MACHINE(obj)->mmio_exec; | |
1050 | } | |
1051 | ||
1052 | static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) | |
1053 | { | |
1054 | ASPEED_MACHINE(obj)->mmio_exec = value; | |
1055 | } | |
1056 | ||
1057 | static void aspeed_machine_instance_init(Object *obj) | |
1058 | { | |
1059 | ASPEED_MACHINE(obj)->mmio_exec = false; | |
1060 | } | |
1061 | ||
9820e52f CLG |
1062 | static char *aspeed_get_fmc_model(Object *obj, Error **errp) |
1063 | { | |
1064 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); | |
1065 | return g_strdup(bmc->fmc_model); | |
1066 | } | |
1067 | ||
1068 | static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) | |
1069 | { | |
1070 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); | |
1071 | ||
1072 | g_free(bmc->fmc_model); | |
1073 | bmc->fmc_model = g_strdup(value); | |
1074 | } | |
1075 | ||
1076 | static char *aspeed_get_spi_model(Object *obj, Error **errp) | |
1077 | { | |
1078 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); | |
1079 | return g_strdup(bmc->spi_model); | |
1080 | } | |
1081 | ||
1082 | static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) | |
1083 | { | |
1084 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); | |
1085 | ||
1086 | g_free(bmc->spi_model); | |
1087 | bmc->spi_model = g_strdup(value); | |
1088 | } | |
1089 | ||
f65f6ad5 CLG |
1090 | static char *aspeed_get_bmc_console(Object *obj, Error **errp) |
1091 | { | |
1092 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); | |
1093 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); | |
1094 | int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; | |
1095 | ||
1096 | return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1); | |
1097 | } | |
1098 | ||
1099 | static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) | |
1100 | { | |
1101 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); | |
1102 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); | |
1103 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); | |
1104 | int val; | |
1105 | ||
1106 | if (sscanf(value, "uart%u", &val) != 1) { | |
1107 | error_setg(errp, "Bad value for \"uart\" property"); | |
1108 | return; | |
1109 | } | |
1110 | ||
1111 | /* The number of UART depends on the SoC */ | |
1112 | if (val < 1 || val > sc->uarts_num) { | |
1113 | error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num); | |
1114 | return; | |
1115 | } | |
1116 | bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1; | |
1117 | } | |
1118 | ||
1a15311a CLG |
1119 | static void aspeed_machine_class_props_init(ObjectClass *oc) |
1120 | { | |
1121 | object_class_property_add_bool(oc, "execute-in-place", | |
1122 | aspeed_get_mmio_exec, | |
d2623129 | 1123 | aspeed_set_mmio_exec); |
1a15311a | 1124 | object_class_property_set_description(oc, "execute-in-place", |
7eecec7d | 1125 | "boot directly from CE0 flash device"); |
9820e52f | 1126 | |
f65f6ad5 CLG |
1127 | object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, |
1128 | aspeed_set_bmc_console); | |
1129 | object_class_property_set_description(oc, "bmc-console", | |
1130 | "Change the default UART to \"uartX\""); | |
1131 | ||
9820e52f CLG |
1132 | object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, |
1133 | aspeed_set_fmc_model); | |
1134 | object_class_property_set_description(oc, "fmc-model", | |
1135 | "Change the FMC Flash model"); | |
1136 | object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, | |
1137 | aspeed_set_spi_model); | |
1138 | object_class_property_set_description(oc, "spi-model", | |
1139 | "Change the SPI Flash model"); | |
1a15311a CLG |
1140 | } |
1141 | ||
b7f1a0cb CLG |
1142 | static int aspeed_soc_num_cpus(const char *soc_name) |
1143 | { | |
1144 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); | |
1145 | return sc->num_cpus; | |
1146 | } | |
1147 | ||
fca9ca1b | 1148 | static void aspeed_machine_class_init(ObjectClass *oc, void *data) |
62c2c2eb CLG |
1149 | { |
1150 | MachineClass *mc = MACHINE_CLASS(oc); | |
d3bad7e7 | 1151 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
62c2c2eb | 1152 | |
fca9ca1b | 1153 | mc->init = aspeed_machine_init; |
62c2c2eb CLG |
1154 | mc->no_floppy = 1; |
1155 | mc->no_cdrom = 1; | |
1156 | mc->no_parallel = 1; | |
afcbaed6 | 1157 | mc->default_ram_id = "ram"; |
d3bad7e7 | 1158 | amc->macs_mask = ASPEED_MAC0_ON; |
5d63d0c7 | 1159 | amc->uart_default = ASPEED_DEV_UART5; |
1a15311a CLG |
1160 | |
1161 | aspeed_machine_class_props_init(oc); | |
62c2c2eb CLG |
1162 | } |
1163 | ||
baa4732b CLG |
1164 | static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) |
1165 | { | |
1166 | MachineClass *mc = MACHINE_CLASS(oc); | |
1167 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1168 | ||
1169 | mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; | |
1170 | amc->soc_name = "ast2400-a1"; | |
1171 | amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; | |
1172 | amc->fmc_model = "n25q256a"; | |
70322913 | 1173 | amc->spi_model = "mx25l25635f"; |
baa4732b CLG |
1174 | amc->num_cs = 1; |
1175 | amc->i2c_init = palmetto_bmc_i2c_init; | |
1176 | mc->default_ram_size = 256 * MiB; | |
b7f1a0cb CLG |
1177 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1178 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
1179 | }; |
1180 | ||
9cccb912 PV |
1181 | static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) |
1182 | { | |
1183 | MachineClass *mc = MACHINE_CLASS(oc); | |
1184 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1185 | ||
1186 | mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; | |
1187 | amc->soc_name = "ast2400-a1"; | |
1188 | amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; | |
1189 | amc->fmc_model = "n25q256a"; | |
1190 | amc->spi_model = "mx25l25635e"; | |
1191 | amc->num_cs = 1; | |
1192 | amc->i2c_init = quanta_q71l_bmc_i2c_init; | |
1193 | mc->default_ram_size = 128 * MiB; | |
1194 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1195 | aspeed_soc_num_cpus(amc->soc_name); | |
1196 | } | |
1197 | ||
40a38df5 ES |
1198 | static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, |
1199 | void *data) | |
1200 | { | |
1201 | MachineClass *mc = MACHINE_CLASS(oc); | |
1202 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1203 | ||
1204 | mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; | |
1205 | amc->soc_name = "ast2400-a1"; | |
1206 | amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; | |
1207 | amc->fmc_model = "mx25l25635e"; | |
1208 | amc->spi_model = "mx25l25635e"; | |
1209 | amc->num_cs = 1; | |
1210 | amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; | |
1211 | amc->i2c_init = palmetto_bmc_i2c_init; | |
1212 | mc->default_ram_size = 256 * MiB; | |
1213 | } | |
1214 | ||
47936597 GR |
1215 | static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, |
1216 | void *data) | |
1217 | { | |
1218 | MachineClass *mc = MACHINE_CLASS(oc); | |
1219 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1220 | ||
1221 | mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; | |
1222 | amc->soc_name = "ast2500-a1"; | |
1223 | amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; | |
1224 | amc->fmc_model = "mx25l25635e"; | |
1225 | amc->spi_model = "mx25l25635e"; | |
1226 | amc->num_cs = 1; | |
1227 | amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; | |
1228 | amc->i2c_init = palmetto_bmc_i2c_init; | |
1229 | mc->default_ram_size = 512 * MiB; | |
1230 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1231 | aspeed_soc_num_cpus(amc->soc_name); | |
1232 | } | |
1233 | ||
baa4732b CLG |
1234 | static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) |
1235 | { | |
1236 | MachineClass *mc = MACHINE_CLASS(oc); | |
1237 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1238 | ||
1239 | mc->desc = "Aspeed AST2500 EVB (ARM1176)"; | |
1240 | amc->soc_name = "ast2500-a1"; | |
1241 | amc->hw_strap1 = AST2500_EVB_HW_STRAP1; | |
753abfc4 | 1242 | amc->fmc_model = "mx25l25635e"; |
70322913 | 1243 | amc->spi_model = "mx25l25635f"; |
baa4732b CLG |
1244 | amc->num_cs = 1; |
1245 | amc->i2c_init = ast2500_evb_i2c_init; | |
1246 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
1247 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1248 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
1249 | }; |
1250 | ||
34f73a81 KP |
1251 | static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) |
1252 | { | |
1253 | MachineClass *mc = MACHINE_CLASS(oc); | |
1254 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1255 | ||
1256 | mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; | |
1257 | amc->soc_name = "ast2500-a1"; | |
1258 | amc->hw_strap1 = AST2500_EVB_HW_STRAP1; | |
1259 | amc->hw_strap2 = 0; | |
1260 | amc->fmc_model = "n25q256a"; | |
1261 | amc->spi_model = "mx25l25635e"; | |
1262 | amc->num_cs = 2; | |
1263 | amc->i2c_init = yosemitev2_bmc_i2c_init; | |
1264 | mc->default_ram_size = 512 * MiB; | |
1265 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1266 | aspeed_soc_num_cpus(amc->soc_name); | |
1267 | }; | |
1268 | ||
baa4732b CLG |
1269 | static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) |
1270 | { | |
1271 | MachineClass *mc = MACHINE_CLASS(oc); | |
1272 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1273 | ||
1274 | mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; | |
1275 | amc->soc_name = "ast2500-a1"; | |
1276 | amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; | |
1277 | amc->fmc_model = "n25q256a"; | |
1278 | amc->spi_model = "mx66l1g45g"; | |
1279 | amc->num_cs = 2; | |
1280 | amc->i2c_init = romulus_bmc_i2c_init; | |
1281 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
1282 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1283 | aspeed_soc_num_cpus(amc->soc_name); | |
fca9ca1b CLG |
1284 | }; |
1285 | ||
6c323aba KP |
1286 | static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) |
1287 | { | |
1288 | MachineClass *mc = MACHINE_CLASS(oc); | |
1289 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1290 | ||
1291 | mc->desc = "Facebook Tiogapass BMC (ARM1176)"; | |
1292 | amc->soc_name = "ast2500-a1"; | |
1293 | amc->hw_strap1 = AST2500_EVB_HW_STRAP1; | |
1294 | amc->hw_strap2 = 0; | |
1295 | amc->fmc_model = "n25q256a"; | |
1296 | amc->spi_model = "mx25l25635e"; | |
1297 | amc->num_cs = 2; | |
1298 | amc->i2c_init = tiogapass_bmc_i2c_init; | |
1299 | mc->default_ram_size = 1 * GiB; | |
1300 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1301 | aspeed_soc_num_cpus(amc->soc_name); | |
1302 | aspeed_soc_num_cpus(amc->soc_name); | |
1303 | }; | |
1304 | ||
143b040f PW |
1305 | static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) |
1306 | { | |
1307 | MachineClass *mc = MACHINE_CLASS(oc); | |
1308 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1309 | ||
1310 | mc->desc = "OCP SonoraPass BMC (ARM1176)"; | |
1311 | amc->soc_name = "ast2500-a1"; | |
1312 | amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; | |
1313 | amc->fmc_model = "mx66l1g45g"; | |
1314 | amc->spi_model = "mx66l1g45g"; | |
1315 | amc->num_cs = 2; | |
1316 | amc->i2c_init = sonorapass_bmc_i2c_init; | |
1317 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
1318 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1319 | aspeed_soc_num_cpus(amc->soc_name); | |
143b040f PW |
1320 | }; |
1321 | ||
baa4732b CLG |
1322 | static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) |
1323 | { | |
1324 | MachineClass *mc = MACHINE_CLASS(oc); | |
1325 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1326 | ||
1327 | mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; | |
1328 | amc->soc_name = "ast2500-a1"; | |
1329 | amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; | |
70322913 | 1330 | amc->fmc_model = "mx25l25635f"; |
baa4732b CLG |
1331 | amc->spi_model = "mx66l1g45g"; |
1332 | amc->num_cs = 2; | |
1333 | amc->i2c_init = witherspoon_bmc_i2c_init; | |
1334 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
1335 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1336 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
1337 | }; |
1338 | ||
1339 | static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) | |
1340 | { | |
1341 | MachineClass *mc = MACHINE_CLASS(oc); | |
1342 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1343 | ||
f548f201 | 1344 | mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; |
c5811bb3 | 1345 | amc->soc_name = "ast2600-a3"; |
baa4732b CLG |
1346 | amc->hw_strap1 = AST2600_EVB_HW_STRAP1; |
1347 | amc->hw_strap2 = AST2600_EVB_HW_STRAP2; | |
753abfc4 | 1348 | amc->fmc_model = "mx66u51235f"; |
baa4732b CLG |
1349 | amc->spi_model = "mx66u51235f"; |
1350 | amc->num_cs = 1; | |
29193286 GR |
1351 | amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | |
1352 | ASPEED_MAC3_ON; | |
baa4732b CLG |
1353 | amc->i2c_init = ast2600_evb_i2c_init; |
1354 | mc->default_ram_size = 1 * GiB; | |
b7f1a0cb CLG |
1355 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1356 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
1357 | }; |
1358 | ||
63ceb818 CLG |
1359 | static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) |
1360 | { | |
1361 | MachineClass *mc = MACHINE_CLASS(oc); | |
1362 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1363 | ||
f548f201 | 1364 | mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; |
c5811bb3 | 1365 | amc->soc_name = "ast2600-a3"; |
63ceb818 CLG |
1366 | amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; |
1367 | amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; | |
1368 | amc->fmc_model = "mx66l1g45g"; | |
1369 | amc->spi_model = "mx66l1g45g"; | |
1370 | amc->num_cs = 2; | |
d3bad7e7 | 1371 | amc->macs_mask = ASPEED_MAC2_ON; |
63ceb818 CLG |
1372 | amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ |
1373 | mc->default_ram_size = 1 * GiB; | |
b7f1a0cb CLG |
1374 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1375 | aspeed_soc_num_cpus(amc->soc_name); | |
63ceb818 CLG |
1376 | }; |
1377 | ||
95f068c8 JW |
1378 | static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) |
1379 | { | |
1380 | MachineClass *mc = MACHINE_CLASS(oc); | |
1381 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1382 | ||
1383 | mc->desc = "Bytedance G220A BMC (ARM1176)"; | |
1384 | amc->soc_name = "ast2500-a1"; | |
1385 | amc->hw_strap1 = G220A_BMC_HW_STRAP1; | |
1386 | amc->fmc_model = "n25q512a"; | |
1387 | amc->spi_model = "mx25l25635e"; | |
1388 | amc->num_cs = 2; | |
5bb825c8 | 1389 | amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; |
95f068c8 JW |
1390 | amc->i2c_init = g220a_bmc_i2c_init; |
1391 | mc->default_ram_size = 1024 * MiB; | |
1392 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1393 | aspeed_soc_num_cpus(amc->soc_name); | |
1394 | }; | |
1395 | ||
82b6a3f6 JW |
1396 | static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) |
1397 | { | |
1398 | MachineClass *mc = MACHINE_CLASS(oc); | |
1399 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1400 | ||
1401 | mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; | |
1402 | amc->soc_name = "ast2500-a1"; | |
1403 | amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; | |
1404 | amc->fmc_model = "n25q512a"; | |
1405 | amc->spi_model = "mx25l25635e"; | |
1406 | amc->num_cs = 2; | |
1407 | amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; | |
1408 | amc->i2c_init = fp5280g2_bmc_i2c_init; | |
1409 | mc->default_ram_size = 512 * MiB; | |
1410 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1411 | aspeed_soc_num_cpus(amc->soc_name); | |
1412 | }; | |
1413 | ||
58e52bdb CLG |
1414 | static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) |
1415 | { | |
1416 | MachineClass *mc = MACHINE_CLASS(oc); | |
1417 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1418 | ||
f548f201 | 1419 | mc->desc = "IBM Rainier BMC (Cortex-A7)"; |
c5811bb3 | 1420 | amc->soc_name = "ast2600-a3"; |
58e52bdb CLG |
1421 | amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; |
1422 | amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; | |
1423 | amc->fmc_model = "mx66l1g45g"; | |
1424 | amc->spi_model = "mx66l1g45g"; | |
1425 | amc->num_cs = 2; | |
1426 | amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; | |
1427 | amc->i2c_init = rainier_bmc_i2c_init; | |
1428 | mc->default_ram_size = 1 * GiB; | |
1429 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1430 | aspeed_soc_num_cpus(amc->soc_name); | |
1431 | }; | |
1432 | ||
1e2c22c9 | 1433 | #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) |
febbe308 PD |
1434 | |
1435 | static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) | |
1436 | { | |
1437 | MachineClass *mc = MACHINE_CLASS(oc); | |
1438 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1439 | ||
1440 | mc->desc = "Facebook Fuji BMC (Cortex-A7)"; | |
1441 | amc->soc_name = "ast2600-a3"; | |
1442 | amc->hw_strap1 = FUJI_BMC_HW_STRAP1; | |
1443 | amc->hw_strap2 = FUJI_BMC_HW_STRAP2; | |
1444 | amc->fmc_model = "mx66l1g45g"; | |
1445 | amc->spi_model = "mx66l1g45g"; | |
1446 | amc->num_cs = 2; | |
1447 | amc->macs_mask = ASPEED_MAC3_ON; | |
1448 | amc->i2c_init = fuji_bmc_i2c_init; | |
1449 | amc->uart_default = ASPEED_DEV_UART1; | |
1450 | mc->default_ram_size = FUJI_BMC_RAM_SIZE; | |
1451 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1452 | aspeed_soc_num_cpus(amc->soc_name); | |
1453 | }; | |
1454 | ||
1e2c22c9 | 1455 | #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) |
104bdaff | 1456 | |
a20c54b1 PW |
1457 | static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) |
1458 | { | |
1459 | MachineClass *mc = MACHINE_CLASS(oc); | |
1460 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1461 | ||
1462 | mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; | |
1463 | amc->soc_name = "ast2600-a3"; | |
1464 | amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; | |
1465 | amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; | |
1466 | amc->fmc_model = "w25q01jvq"; | |
1467 | amc->spi_model = NULL; | |
1468 | amc->num_cs = 2; | |
1469 | amc->macs_mask = ASPEED_MAC2_ON; | |
1470 | amc->i2c_init = bletchley_bmc_i2c_init; | |
104bdaff | 1471 | mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; |
a20c54b1 PW |
1472 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
1473 | aspeed_soc_num_cpus(amc->soc_name); | |
1474 | } | |
1475 | ||
7966d70f | 1476 | static void fby35_reset(MachineState *state, ShutdownCause reason) |
fa699e80 PD |
1477 | { |
1478 | AspeedMachineState *bmc = ASPEED_MACHINE(state); | |
1479 | AspeedGPIOState *gpio = &bmc->soc.gpio; | |
1480 | ||
7966d70f | 1481 | qemu_devices_reset(reason); |
fa699e80 | 1482 | |
f0418558 | 1483 | /* Board ID: 7 (Class-1, 4 slots) */ |
fa699e80 PD |
1484 | object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); |
1485 | object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); | |
1486 | object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); | |
1487 | object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); | |
f0418558 PD |
1488 | |
1489 | /* Slot presence pins, inverse polarity. (False means present) */ | |
1490 | object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); | |
1491 | object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); | |
1492 | object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); | |
1493 | object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); | |
1494 | ||
1495 | /* Slot 12v power pins, normal polarity. (True means powered-on) */ | |
1496 | object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); | |
1497 | object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); | |
1498 | object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); | |
1499 | object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); | |
fa699e80 PD |
1500 | } |
1501 | ||
1502 | static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) | |
1503 | { | |
1504 | MachineClass *mc = MACHINE_CLASS(oc); | |
1505 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1506 | ||
1507 | mc->desc = "Facebook fby35 BMC (Cortex-A7)"; | |
1508 | mc->reset = fby35_reset; | |
1509 | amc->fmc_model = "mx66l1g45g"; | |
1510 | amc->num_cs = 2; | |
1511 | amc->macs_mask = ASPEED_MAC3_ON; | |
1512 | amc->i2c_init = fby35_i2c_init; | |
1513 | /* FIXME: Replace this macro with something more general */ | |
1514 | mc->default_ram_size = FUJI_BMC_RAM_SIZE; | |
1515 | } | |
1516 | ||
66c895b8 JL |
1517 | #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) |
1518 | /* Main SYSCLK frequency in Hz (200MHz) */ | |
1519 | #define SYSCLK_FRQ 200000000ULL | |
1520 | ||
1521 | static void aspeed_minibmc_machine_init(MachineState *machine) | |
1522 | { | |
1523 | AspeedMachineState *bmc = ASPEED_MACHINE(machine); | |
1524 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); | |
1525 | Clock *sysclk; | |
1526 | ||
1527 | sysclk = clock_new(OBJECT(machine), "SYSCLK"); | |
1528 | clock_set_hz(sysclk, SYSCLK_FRQ); | |
1529 | ||
1530 | object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); | |
1531 | qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); | |
1532 | ||
4dd9d554 PD |
1533 | object_property_set_link(OBJECT(&bmc->soc), "memory", |
1534 | OBJECT(get_system_memory()), &error_abort); | |
d2b3eaef | 1535 | connect_serial_hds_to_uarts(bmc); |
66c895b8 JL |
1536 | qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); |
1537 | ||
1538 | aspeed_board_init_flashes(&bmc->soc.fmc, | |
1539 | bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, | |
1540 | amc->num_cs, | |
1541 | 0); | |
1542 | ||
1543 | aspeed_board_init_flashes(&bmc->soc.spi[0], | |
1544 | bmc->spi_model ? bmc->spi_model : amc->spi_model, | |
1545 | amc->num_cs, amc->num_cs); | |
1546 | ||
1547 | aspeed_board_init_flashes(&bmc->soc.spi[1], | |
1548 | bmc->spi_model ? bmc->spi_model : amc->spi_model, | |
1549 | amc->num_cs, (amc->num_cs * 2)); | |
1550 | ||
1551 | if (amc->i2c_init) { | |
1552 | amc->i2c_init(bmc); | |
1553 | } | |
1554 | ||
1555 | armv7m_load_kernel(ARM_CPU(first_cpu), | |
1556 | machine->kernel_filename, | |
761c532a | 1557 | 0, |
66c895b8 JL |
1558 | AST1030_INTERNAL_FLASH_SIZE); |
1559 | } | |
1560 | ||
4c70ab16 TL |
1561 | static void ast1030_evb_i2c_init(AspeedMachineState *bmc) |
1562 | { | |
1563 | AspeedSoCState *soc = &bmc->soc; | |
1564 | ||
673d8215 | 1565 | /* U10 24C08 connects to SDA/SCL Group 1 by default */ |
4c70ab16 TL |
1566 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
1567 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); | |
1568 | ||
1569 | /* U11 LM75 connects to SDA/SCL Group 2 by default */ | |
1570 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); | |
1571 | } | |
1572 | ||
66c895b8 JL |
1573 | static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, |
1574 | void *data) | |
1575 | { | |
1576 | MachineClass *mc = MACHINE_CLASS(oc); | |
1577 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1578 | ||
1579 | mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; | |
1580 | amc->soc_name = "ast1030-a1"; | |
1581 | amc->hw_strap1 = 0; | |
1582 | amc->hw_strap2 = 0; | |
1583 | mc->init = aspeed_minibmc_machine_init; | |
4c70ab16 | 1584 | amc->i2c_init = ast1030_evb_i2c_init; |
66c895b8 JL |
1585 | mc->default_ram_size = 0; |
1586 | mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; | |
1587 | amc->fmc_model = "sst25vf032b"; | |
1588 | amc->spi_model = "sst25vf032b"; | |
1589 | amc->num_cs = 2; | |
1590 | amc->macs_mask = 0; | |
1591 | } | |
1592 | ||
fb6b3c8d JHY |
1593 | static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, |
1594 | void *data) | |
1595 | { | |
1596 | MachineClass *mc = MACHINE_CLASS(oc); | |
1597 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1598 | ||
1599 | mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; | |
1600 | amc->soc_name = "ast2600-a3"; | |
1601 | amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; | |
1602 | amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; | |
1603 | amc->fmc_model = "n25q512a"; | |
1604 | amc->spi_model = "n25q512a"; | |
1605 | amc->num_cs = 2; | |
1606 | amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; | |
1607 | amc->i2c_init = qcom_dc_scm_bmc_i2c_init; | |
1608 | mc->default_ram_size = 1 * GiB; | |
1609 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1610 | aspeed_soc_num_cpus(amc->soc_name); | |
1611 | }; | |
1612 | ||
ece4cccd GG |
1613 | static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, |
1614 | void *data) | |
1615 | { | |
1616 | MachineClass *mc = MACHINE_CLASS(oc); | |
1617 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
1618 | ||
1619 | mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; | |
1620 | amc->soc_name = "ast2600-a3"; | |
1621 | amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; | |
1622 | amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; | |
1623 | amc->fmc_model = "n25q512a"; | |
1624 | amc->spi_model = "n25q512a"; | |
1625 | amc->num_cs = 2; | |
1626 | amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; | |
1627 | amc->i2c_init = qcom_dc_scm_firework_i2c_init; | |
1628 | mc->default_ram_size = 1 * GiB; | |
1629 | mc->default_cpus = mc->min_cpus = mc->max_cpus = | |
1630 | aspeed_soc_num_cpus(amc->soc_name); | |
1631 | }; | |
1632 | ||
baa4732b | 1633 | static const TypeInfo aspeed_machine_types[] = { |
fca9ca1b | 1634 | { |
baa4732b CLG |
1635 | .name = MACHINE_TYPE_NAME("palmetto-bmc"), |
1636 | .parent = TYPE_ASPEED_MACHINE, | |
1637 | .class_init = aspeed_machine_palmetto_class_init, | |
40a38df5 ES |
1638 | }, { |
1639 | .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), | |
1640 | .parent = TYPE_ASPEED_MACHINE, | |
1641 | .class_init = aspeed_machine_supermicrox11_bmc_class_init, | |
47936597 GR |
1642 | }, { |
1643 | .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), | |
1644 | .parent = TYPE_ASPEED_MACHINE, | |
1645 | .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, | |
fca9ca1b | 1646 | }, { |
baa4732b CLG |
1647 | .name = MACHINE_TYPE_NAME("ast2500-evb"), |
1648 | .parent = TYPE_ASPEED_MACHINE, | |
1649 | .class_init = aspeed_machine_ast2500_evb_class_init, | |
fca9ca1b | 1650 | }, { |
baa4732b CLG |
1651 | .name = MACHINE_TYPE_NAME("romulus-bmc"), |
1652 | .parent = TYPE_ASPEED_MACHINE, | |
1653 | .class_init = aspeed_machine_romulus_class_init, | |
143b040f PW |
1654 | }, { |
1655 | .name = MACHINE_TYPE_NAME("sonorapass-bmc"), | |
1656 | .parent = TYPE_ASPEED_MACHINE, | |
1657 | .class_init = aspeed_machine_sonorapass_class_init, | |
fca9ca1b | 1658 | }, { |
baa4732b CLG |
1659 | .name = MACHINE_TYPE_NAME("witherspoon-bmc"), |
1660 | .parent = TYPE_ASPEED_MACHINE, | |
1661 | .class_init = aspeed_machine_witherspoon_class_init, | |
ccc2c418 | 1662 | }, { |
baa4732b CLG |
1663 | .name = MACHINE_TYPE_NAME("ast2600-evb"), |
1664 | .parent = TYPE_ASPEED_MACHINE, | |
1665 | .class_init = aspeed_machine_ast2600_evb_class_init, | |
34f73a81 KP |
1666 | }, { |
1667 | .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), | |
1668 | .parent = TYPE_ASPEED_MACHINE, | |
1669 | .class_init = aspeed_machine_yosemitev2_class_init, | |
63ceb818 CLG |
1670 | }, { |
1671 | .name = MACHINE_TYPE_NAME("tacoma-bmc"), | |
1672 | .parent = TYPE_ASPEED_MACHINE, | |
1673 | .class_init = aspeed_machine_tacoma_class_init, | |
6c323aba KP |
1674 | }, { |
1675 | .name = MACHINE_TYPE_NAME("tiogapass-bmc"), | |
1676 | .parent = TYPE_ASPEED_MACHINE, | |
1677 | .class_init = aspeed_machine_tiogapass_class_init, | |
95f068c8 JW |
1678 | }, { |
1679 | .name = MACHINE_TYPE_NAME("g220a-bmc"), | |
1680 | .parent = TYPE_ASPEED_MACHINE, | |
1681 | .class_init = aspeed_machine_g220a_class_init, | |
fb6b3c8d JHY |
1682 | }, { |
1683 | .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), | |
1684 | .parent = TYPE_ASPEED_MACHINE, | |
1685 | .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, | |
ece4cccd GG |
1686 | }, { |
1687 | .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), | |
1688 | .parent = TYPE_ASPEED_MACHINE, | |
1689 | .class_init = aspeed_machine_qcom_firework_class_init, | |
82b6a3f6 JW |
1690 | }, { |
1691 | .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), | |
1692 | .parent = TYPE_ASPEED_MACHINE, | |
1693 | .class_init = aspeed_machine_fp5280g2_class_init, | |
9cccb912 PV |
1694 | }, { |
1695 | .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), | |
1696 | .parent = TYPE_ASPEED_MACHINE, | |
1697 | .class_init = aspeed_machine_quanta_q71l_class_init, | |
58e52bdb CLG |
1698 | }, { |
1699 | .name = MACHINE_TYPE_NAME("rainier-bmc"), | |
1700 | .parent = TYPE_ASPEED_MACHINE, | |
1701 | .class_init = aspeed_machine_rainier_class_init, | |
febbe308 PD |
1702 | }, { |
1703 | .name = MACHINE_TYPE_NAME("fuji-bmc"), | |
1704 | .parent = TYPE_ASPEED_MACHINE, | |
1705 | .class_init = aspeed_machine_fuji_class_init, | |
a20c54b1 PW |
1706 | }, { |
1707 | .name = MACHINE_TYPE_NAME("bletchley-bmc"), | |
1708 | .parent = TYPE_ASPEED_MACHINE, | |
1709 | .class_init = aspeed_machine_bletchley_class_init, | |
fa699e80 PD |
1710 | }, { |
1711 | .name = MACHINE_TYPE_NAME("fby35-bmc"), | |
1712 | .parent = MACHINE_TYPE_NAME("ast2600-evb"), | |
1713 | .class_init = aspeed_machine_fby35_class_init, | |
66c895b8 JL |
1714 | }, { |
1715 | .name = MACHINE_TYPE_NAME("ast1030-evb"), | |
1716 | .parent = TYPE_ASPEED_MACHINE, | |
1717 | .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, | |
baa4732b CLG |
1718 | }, { |
1719 | .name = TYPE_ASPEED_MACHINE, | |
1720 | .parent = TYPE_MACHINE, | |
888b2b03 | 1721 | .instance_size = sizeof(AspeedMachineState), |
1a15311a | 1722 | .instance_init = aspeed_machine_instance_init, |
baa4732b CLG |
1723 | .class_size = sizeof(AspeedMachineClass), |
1724 | .class_init = aspeed_machine_class_init, | |
1725 | .abstract = true, | |
fca9ca1b | 1726 | } |
baa4732b | 1727 | }; |
74fb1f38 | 1728 | |
baa4732b | 1729 | DEFINE_TYPES(aspeed_machine_types) |