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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
29bd7231 | 25 | #include "qemu/error-report.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
83c9f4ca PB |
29 | #include "hw/hw.h" |
30 | #include "hw/pci/pci.h" | |
4272ad40 | 31 | #include "hw/pci/pci_bridge.h" |
6864fa38 | 32 | #include "hw/pci/pci_bus.h" |
0ea833c2 | 33 | #include "hw/pci/pci_host.h" |
9b301794 | 34 | #include "hw/pci-host/sabre.h" |
0d09e41a PB |
35 | #include "hw/i386/pc.h" |
36 | #include "hw/char/serial.h" | |
bb3d5ea8 | 37 | #include "hw/char/parallel.h" |
0d09e41a PB |
38 | #include "hw/timer/m48t59.h" |
39 | #include "hw/block/fdc.h" | |
1422e32d | 40 | #include "net/net.h" |
1de7afc9 | 41 | #include "qemu/timer.h" |
9c17d615 | 42 | #include "sysemu/sysemu.h" |
83c9f4ca | 43 | #include "hw/boards.h" |
c6363bae | 44 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 45 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 46 | #include "hw/sparc/sparc64.h" |
0d09e41a | 47 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca PB |
48 | #include "hw/sysbus.h" |
49 | #include "hw/ide.h" | |
6864fa38 | 50 | #include "hw/ide/pci.h" |
83c9f4ca | 51 | #include "hw/loader.h" |
ca20cf32 | 52 | #include "elf.h" |
69520948 | 53 | #include "trace.h" |
f348b6d1 | 54 | #include "qemu/cutils.h" |
3475187d | 55 | |
83469015 FB |
56 | #define KERNEL_LOAD_ADDR 0x00404000 |
57 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 58 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 59 | #define PROM_VADDR 0x000ffd00000ULL |
5795162a MCA |
60 | #define PBM_SPECIAL_BASE 0x1fe00000000ULL |
61 | #define PBM_MEM_BASE 0x1ff00000000ULL | |
62 | #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) | |
f930d07e | 63 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 64 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 65 | #define MAX_IDE_BUS 2 |
3cce6243 | 66 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
67 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
68 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
69 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 70 | |
852e82f3 | 71 | #define IVEC_MAX 0x40 |
9d926598 | 72 | |
c7ba218d | 73 | struct hwdef { |
905fdcb5 | 74 | uint16_t machine_id; |
e87231d4 BS |
75 | uint64_t prom_addr; |
76 | uint64_t console_serial_base; | |
c7ba218d BS |
77 | }; |
78 | ||
c5e6fb7e | 79 | typedef struct EbusState { |
ad6856e8 MCA |
80 | /*< private >*/ |
81 | PCIDevice parent_obj; | |
82 | ||
8c40b8d9 | 83 | ISABus *isa_bus; |
4b10c8d7 | 84 | qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; |
0fe22ffb | 85 | uint64_t console_serial_base; |
c5e6fb7e AK |
86 | MemoryRegion bar0; |
87 | MemoryRegion bar1; | |
88 | } EbusState; | |
89 | ||
ad6856e8 MCA |
90 | #define TYPE_EBUS "ebus" |
91 | #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) | |
92 | ||
ddcd5531 GA |
93 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
94 | Error **errp) | |
81864572 | 95 | { |
48779e50 | 96 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
97 | } |
98 | ||
31688246 | 99 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
100 | const char *arch, ram_addr_t RAM_size, |
101 | const char *boot_devices, | |
102 | uint32_t kernel_image, uint32_t kernel_size, | |
103 | const char *cmdline, | |
104 | uint32_t initrd_image, uint32_t initrd_size, | |
105 | uint32_t NVRAM_image, | |
106 | int width, int height, int depth, | |
107 | const uint8_t *macaddr) | |
83469015 | 108 | { |
66508601 | 109 | unsigned int i; |
2024c014 | 110 | int sysp_end; |
d2c63fc1 | 111 | uint8_t image[0x1ff0]; |
31688246 | 112 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
113 | |
114 | memset(image, '\0', sizeof(image)); | |
115 | ||
2024c014 TH |
116 | /* OpenBIOS nvram variables partition */ |
117 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
83469015 | 118 | |
2024c014 TH |
119 | /* Free space partition */ |
120 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 121 | |
0d31cb99 BS |
122 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
123 | ||
31688246 HP |
124 | for (i = 0; i < sizeof(image); i++) { |
125 | (k->write)(nvram, i, image[i]); | |
126 | } | |
66508601 | 127 | |
83469015 | 128 | return 0; |
3475187d | 129 | } |
5f2bf0fe BS |
130 | |
131 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
132 | const char *initrd_filename, | |
133 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
134 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
135 | uint64_t *kernel_entry) | |
636aa70a BS |
136 | { |
137 | int linux_boot; | |
138 | unsigned int i; | |
139 | long kernel_size; | |
6908d9ce | 140 | uint8_t *ptr; |
5f2bf0fe | 141 | uint64_t kernel_top; |
636aa70a BS |
142 | |
143 | linux_boot = (kernel_filename != NULL); | |
144 | ||
145 | kernel_size = 0; | |
146 | if (linux_boot) { | |
ca20cf32 BS |
147 | int bswap_needed; |
148 | ||
149 | #ifdef BSWAP_NEEDED | |
150 | bswap_needed = 1; | |
151 | #else | |
152 | bswap_needed = 0; | |
153 | #endif | |
5f2bf0fe | 154 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
7ef295ea | 155 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); |
5f2bf0fe BS |
156 | if (kernel_size < 0) { |
157 | *kernel_addr = KERNEL_LOAD_ADDR; | |
158 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 159 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
160 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
161 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
162 | } |
163 | if (kernel_size < 0) { | |
636aa70a BS |
164 | kernel_size = load_image_targphys(kernel_filename, |
165 | KERNEL_LOAD_ADDR, | |
166 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 167 | } |
636aa70a | 168 | if (kernel_size < 0) { |
29bd7231 | 169 | error_report("could not load kernel '%s'", kernel_filename); |
636aa70a BS |
170 | exit(1); |
171 | } | |
5f2bf0fe | 172 | /* load initrd above kernel */ |
636aa70a BS |
173 | *initrd_size = 0; |
174 | if (initrd_filename) { | |
5f2bf0fe BS |
175 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
176 | ||
636aa70a | 177 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
178 | *initrd_addr, |
179 | RAM_size - *initrd_addr); | |
180 | if ((int)*initrd_size < 0) { | |
29bd7231 AF |
181 | error_report("could not load initial ram disk '%s'", |
182 | initrd_filename); | |
636aa70a BS |
183 | exit(1); |
184 | } | |
185 | } | |
186 | if (*initrd_size > 0) { | |
187 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 188 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 189 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 190 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 191 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
192 | break; |
193 | } | |
194 | } | |
195 | } | |
196 | } | |
197 | return kernel_size; | |
198 | } | |
3475187d | 199 | |
e87231d4 | 200 | typedef struct ResetData { |
403d7a2d | 201 | SPARCCPU *cpu; |
44a99354 | 202 | uint64_t prom_addr; |
e87231d4 BS |
203 | } ResetData; |
204 | ||
25c5d5ac MCA |
205 | #define TYPE_SUN4U_POWER "power" |
206 | #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) | |
207 | ||
208 | typedef struct PowerDevice { | |
209 | SysBusDevice parent_obj; | |
210 | ||
211 | MemoryRegion power_mmio; | |
212 | } PowerDevice; | |
213 | ||
214 | /* Power */ | |
215 | static void power_mem_write(void *opaque, hwaddr addr, | |
216 | uint64_t val, unsigned size) | |
217 | { | |
218 | /* According to a real Ultra 5, bit 24 controls the power */ | |
219 | if (val & 0x1000000) { | |
220 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
221 | } | |
222 | } | |
223 | ||
224 | static const MemoryRegionOps power_mem_ops = { | |
225 | .write = power_mem_write, | |
226 | .endianness = DEVICE_NATIVE_ENDIAN, | |
227 | .valid = { | |
228 | .min_access_size = 4, | |
229 | .max_access_size = 4, | |
230 | }, | |
231 | }; | |
232 | ||
233 | static void power_realize(DeviceState *dev, Error **errp) | |
234 | { | |
235 | PowerDevice *d = SUN4U_POWER(dev); | |
236 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
237 | ||
238 | memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, | |
239 | "power", sizeof(uint32_t)); | |
240 | ||
241 | sysbus_init_mmio(sbd, &d->power_mmio); | |
242 | } | |
243 | ||
244 | static void power_class_init(ObjectClass *klass, void *data) | |
245 | { | |
246 | DeviceClass *dc = DEVICE_CLASS(klass); | |
247 | ||
248 | dc->realize = power_realize; | |
249 | } | |
250 | ||
251 | static const TypeInfo power_info = { | |
252 | .name = TYPE_SUN4U_POWER, | |
253 | .parent = TYPE_SYS_BUS_DEVICE, | |
254 | .instance_size = sizeof(PowerDevice), | |
255 | .class_init = power_class_init, | |
256 | }; | |
257 | ||
4b10c8d7 | 258 | static void ebus_isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 259 | { |
4b10c8d7 MCA |
260 | EbusState *s = EBUS(opaque); |
261 | qemu_irq irq = s->isa_bus_irqs[n]; | |
262 | ||
263 | /* Pass ISA bus IRQs onto their gpio equivalent */ | |
69520948 | 264 | trace_ebus_isa_irq_handler(n, level); |
4b10c8d7 MCA |
265 | if (irq) { |
266 | qemu_set_irq(irq, level); | |
361dea40 | 267 | } |
1387fe4a BS |
268 | } |
269 | ||
c190ea07 | 270 | /* EBUS (Eight bit bus) bridge */ |
ad6856e8 | 271 | static void ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 272 | { |
ad6856e8 | 273 | EbusState *s = EBUS(pci_dev); |
25c5d5ac | 274 | SysBusDevice *sbd; |
0fe22ffb | 275 | DeviceState *dev; |
c796edda | 276 | qemu_irq *isa_irq; |
0fe22ffb MCA |
277 | DriveInfo *fd[MAX_FD]; |
278 | int i; | |
c5e6fb7e | 279 | |
8c40b8d9 MCA |
280 | s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
281 | pci_address_space_io(pci_dev), errp); | |
282 | if (!s->isa_bus) { | |
283 | error_setg(errp, "unable to instantiate EBUS ISA bus"); | |
d10e5432 MA |
284 | return; |
285 | } | |
c5e6fb7e | 286 | |
4b10c8d7 MCA |
287 | /* ISA bus */ |
288 | isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); | |
c796edda | 289 | isa_bus_irqs(s->isa_bus, isa_irq); |
4b10c8d7 MCA |
290 | qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", |
291 | ISA_NUM_IRQS); | |
c796edda | 292 | |
0fe22ffb MCA |
293 | /* Serial ports */ |
294 | i = 0; | |
295 | if (s->console_serial_base) { | |
296 | serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, | |
297 | 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); | |
298 | i++; | |
299 | } | |
300 | serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); | |
301 | ||
302 | /* Parallel ports */ | |
303 | parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); | |
304 | ||
305 | /* Keyboard */ | |
306 | isa_create_simple(s->isa_bus, "i8042"); | |
307 | ||
308 | /* Floppy */ | |
309 | for (i = 0; i < MAX_FD; i++) { | |
310 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
311 | } | |
312 | dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); | |
313 | if (fd[0]) { | |
314 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
315 | &error_abort); | |
316 | } | |
317 | if (fd[1]) { | |
318 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
319 | &error_abort); | |
320 | } | |
321 | qdev_prop_set_uint32(dev, "dma", -1); | |
322 | qdev_init_nofail(dev); | |
323 | ||
25c5d5ac MCA |
324 | /* Power */ |
325 | dev = qdev_create(NULL, TYPE_SUN4U_POWER); | |
326 | qdev_init_nofail(dev); | |
327 | sbd = SYS_BUS_DEVICE(dev); | |
328 | memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, | |
329 | sysbus_mmio_get_region(sbd, 0)); | |
330 | ||
0fe22ffb | 331 | /* PCI */ |
c5e6fb7e AK |
332 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
333 | pci_dev->config[0x05] = 0x00; | |
334 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
335 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
336 | pci_dev->config[0x09] = 0x00; // programming i/f | |
337 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
338 | ||
0a70e094 PB |
339 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
340 | 0, 0x1000000); | |
e824b2cc | 341 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 342 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
25c5d5ac | 343 | 0, 0x8000); |
a1cf8be5 | 344 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
345 | } |
346 | ||
0fe22ffb MCA |
347 | static Property ebus_properties[] = { |
348 | DEFINE_PROP_UINT64("console-serial-base", EbusState, | |
349 | console_serial_base, 0), | |
350 | DEFINE_PROP_END_OF_LIST(), | |
351 | }; | |
352 | ||
40021f08 AL |
353 | static void ebus_class_init(ObjectClass *klass, void *data) |
354 | { | |
355 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
0fe22ffb | 356 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 357 | |
ad6856e8 | 358 | k->realize = ebus_realize; |
40021f08 AL |
359 | k->vendor_id = PCI_VENDOR_ID_SUN; |
360 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
361 | k->revision = 0x01; | |
362 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
0fe22ffb | 363 | dc->props = ebus_properties; |
40021f08 AL |
364 | } |
365 | ||
8c43a6f0 | 366 | static const TypeInfo ebus_info = { |
ad6856e8 | 367 | .name = TYPE_EBUS, |
39bffca2 | 368 | .parent = TYPE_PCI_DEVICE, |
39bffca2 | 369 | .class_init = ebus_class_init, |
ad6856e8 | 370 | .instance_size = sizeof(EbusState), |
fd3b02c8 EH |
371 | .interfaces = (InterfaceInfo[]) { |
372 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
373 | { }, | |
374 | }, | |
53e3c4f9 BS |
375 | }; |
376 | ||
13575cf6 AF |
377 | #define TYPE_OPENPROM "openprom" |
378 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
379 | ||
d4edce38 | 380 | typedef struct PROMState { |
13575cf6 AF |
381 | SysBusDevice parent_obj; |
382 | ||
d4edce38 AK |
383 | MemoryRegion prom; |
384 | } PROMState; | |
385 | ||
409dbce5 AJ |
386 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
387 | { | |
a8170e5e | 388 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
389 | return addr + *base_addr - PROM_VADDR; |
390 | } | |
391 | ||
1baffa46 | 392 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 393 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
394 | { |
395 | DeviceState *dev; | |
396 | SysBusDevice *s; | |
397 | char *filename; | |
398 | int ret; | |
399 | ||
13575cf6 | 400 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 401 | qdev_init_nofail(dev); |
1356b98d | 402 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
403 | |
404 | sysbus_mmio_map(s, 0, addr); | |
405 | ||
406 | /* load boot prom */ | |
407 | if (bios_name == NULL) { | |
408 | bios_name = PROM_FILENAME; | |
409 | } | |
410 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
411 | if (filename) { | |
409dbce5 | 412 | ret = load_elf(filename, translate_prom_address, &addr, |
7ef295ea | 413 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
414 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
415 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
416 | } | |
7267c094 | 417 | g_free(filename); |
1baffa46 BS |
418 | } else { |
419 | ret = -1; | |
420 | } | |
421 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 422 | error_report("could not load prom '%s'", bios_name); |
1baffa46 BS |
423 | exit(1); |
424 | } | |
425 | } | |
426 | ||
78fb261d | 427 | static void prom_init1(Object *obj) |
1baffa46 | 428 | { |
78fb261d XZ |
429 | PROMState *s = OPENPROM(obj); |
430 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
1baffa46 | 431 | |
1cfe48c1 | 432 | memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, |
f8ed85ac | 433 | &error_fatal); |
c5705a77 | 434 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 435 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 436 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
437 | } |
438 | ||
999e12bb AL |
439 | static Property prom_properties[] = { |
440 | {/* end of property list */}, | |
441 | }; | |
442 | ||
443 | static void prom_class_init(ObjectClass *klass, void *data) | |
444 | { | |
39bffca2 | 445 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 446 | |
39bffca2 | 447 | dc->props = prom_properties; |
999e12bb AL |
448 | } |
449 | ||
8c43a6f0 | 450 | static const TypeInfo prom_info = { |
13575cf6 | 451 | .name = TYPE_OPENPROM, |
39bffca2 AL |
452 | .parent = TYPE_SYS_BUS_DEVICE, |
453 | .instance_size = sizeof(PROMState), | |
454 | .class_init = prom_class_init, | |
78fb261d | 455 | .instance_init = prom_init1, |
1baffa46 BS |
456 | }; |
457 | ||
bda42033 | 458 | |
88c034d5 AF |
459 | #define TYPE_SUN4U_MEMORY "memory" |
460 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
461 | ||
462 | typedef struct RamDevice { | |
463 | SysBusDevice parent_obj; | |
464 | ||
d4edce38 | 465 | MemoryRegion ram; |
04843626 | 466 | uint64_t size; |
bda42033 BS |
467 | } RamDevice; |
468 | ||
469 | /* System RAM */ | |
78fb261d | 470 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 471 | { |
88c034d5 | 472 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 473 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 474 | |
1cfe48c1 | 475 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 476 | &error_fatal); |
c5705a77 | 477 | vmstate_register_ram_global(&d->ram); |
78fb261d | 478 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
479 | } |
480 | ||
a8170e5e | 481 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
482 | { |
483 | DeviceState *dev; | |
484 | SysBusDevice *s; | |
485 | RamDevice *d; | |
486 | ||
487 | /* allocate RAM */ | |
88c034d5 | 488 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 489 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 490 | |
88c034d5 | 491 | d = SUN4U_RAM(dev); |
bda42033 | 492 | d->size = RAM_size; |
e23a1b33 | 493 | qdev_init_nofail(dev); |
bda42033 BS |
494 | |
495 | sysbus_mmio_map(s, 0, addr); | |
496 | } | |
497 | ||
999e12bb AL |
498 | static Property ram_properties[] = { |
499 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
500 | DEFINE_PROP_END_OF_LIST(), | |
501 | }; | |
502 | ||
503 | static void ram_class_init(ObjectClass *klass, void *data) | |
504 | { | |
39bffca2 | 505 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 506 | |
78fb261d | 507 | dc->realize = ram_realize; |
39bffca2 | 508 | dc->props = ram_properties; |
999e12bb AL |
509 | } |
510 | ||
8c43a6f0 | 511 | static const TypeInfo ram_info = { |
88c034d5 | 512 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
513 | .parent = TYPE_SYS_BUS_DEVICE, |
514 | .instance_size = sizeof(RamDevice), | |
515 | .class_init = ram_class_init, | |
bda42033 BS |
516 | }; |
517 | ||
38bc50f7 | 518 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 519 | MachineState *machine, |
7b833f5b BS |
520 | const struct hwdef *hwdef) |
521 | { | |
f9d1465f | 522 | SPARCCPU *cpu; |
31688246 | 523 | Nvram *nvram; |
7b833f5b | 524 | unsigned int i; |
5f2bf0fe | 525 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
5795162a | 526 | SabreState *sabre; |
311f2b7a | 527 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 528 | PCIDevice *ebus, *pci_dev; |
f3b18f35 | 529 | SysBusDevice *s; |
f455e98c | 530 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
aea5b071 | 531 | DeviceState *iommu, *dev; |
a88b362c | 532 | FWCfgState *fw_cfg; |
8d932971 | 533 | NICInfo *nd; |
6864fa38 MCA |
534 | MACAddr macaddr; |
535 | bool onboard_nic; | |
7b833f5b | 536 | |
7b833f5b | 537 | /* init CPUs */ |
58530461 | 538 | cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); |
7b833f5b | 539 | |
aea5b071 MCA |
540 | /* IOMMU */ |
541 | iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); | |
542 | qdev_init_nofail(iommu); | |
543 | ||
bda42033 | 544 | /* set up devices */ |
3ef96221 | 545 | ram_init(0, machine->ram_size); |
3475187d | 546 | |
1baffa46 | 547 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 548 | |
b14dcaf4 | 549 | /* Init sabre (PCI host bridge) */ |
5795162a MCA |
550 | sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); |
551 | qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); | |
552 | qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); | |
553 | object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", | |
554 | &error_abort); | |
555 | qdev_init_nofail(DEVICE(sabre)); | |
2a4d6af5 MCA |
556 | |
557 | /* Wire up PCI interrupts to CPU */ | |
558 | for (i = 0; i < IVEC_MAX; i++) { | |
5795162a | 559 | qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, |
2a4d6af5 MCA |
560 | qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); |
561 | } | |
562 | ||
5795162a MCA |
563 | pci_bus = PCI_HOST_BRIDGE(sabre)->bus; |
564 | pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); | |
565 | pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); | |
83469015 | 566 | |
5795162a | 567 | /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is |
6864fa38 MCA |
568 | reserved (leaving no slots free after on-board devices) however slots |
569 | 0-3 are free on busB */ | |
570 | pci_bus->slot_reserved_mask = 0xfffffffc; | |
571 | pci_busA->slot_reserved_mask = 0xfffffff1; | |
572 | pci_busB->slot_reserved_mask = 0xfffffff0; | |
573 | ||
ad6856e8 | 574 | ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); |
0fe22ffb MCA |
575 | qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", |
576 | hwdef->console_serial_base); | |
6864fa38 MCA |
577 | qdev_init_nofail(DEVICE(ebus)); |
578 | ||
5795162a | 579 | /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ |
4b10c8d7 | 580 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, |
5795162a | 581 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); |
4b10c8d7 | 582 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, |
5795162a | 583 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); |
4b10c8d7 | 584 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, |
5795162a | 585 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); |
4b10c8d7 | 586 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, |
5795162a | 587 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); |
4b10c8d7 | 588 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, |
5795162a | 589 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); |
4b10c8d7 | 590 | |
6864fa38 MCA |
591 | pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); |
592 | ||
593 | memset(&macaddr, 0, sizeof(MACAddr)); | |
594 | onboard_nic = false; | |
8d932971 MCA |
595 | for (i = 0; i < nb_nics; i++) { |
596 | nd = &nd_table[i]; | |
597 | ||
6864fa38 MCA |
598 | if (!nd->model || strcmp(nd->model, "sunhme") == 0) { |
599 | if (!onboard_nic) { | |
600 | pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), | |
601 | true, "sunhme"); | |
602 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); | |
603 | onboard_nic = true; | |
604 | } else { | |
bcf9e2c2 | 605 | pci_dev = pci_create(pci_busB, -1, "sunhme"); |
6864fa38 | 606 | } |
8d932971 | 607 | } else { |
bcf9e2c2 | 608 | pci_dev = pci_create(pci_busB, -1, nd->model); |
8d932971 | 609 | } |
6864fa38 MCA |
610 | |
611 | dev = &pci_dev->qdev; | |
612 | qdev_set_nic_properties(dev, nd); | |
613 | qdev_init_nofail(dev); | |
614 | } | |
615 | ||
616 | /* If we don't have an onboard NIC, grab a default MAC address so that | |
617 | * we have a valid machine id */ | |
618 | if (!onboard_nic) { | |
619 | qemu_macaddr_default_if_unset(&macaddr); | |
8d932971 | 620 | } |
83469015 | 621 | |
d8f94e1b | 622 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
e4bcb14c | 623 | |
6864fa38 MCA |
624 | pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); |
625 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); | |
626 | qdev_init_nofail(&pci_dev->qdev); | |
627 | pci_ide_create_devs(pci_dev, hd); | |
3b898dda | 628 | |
f3b18f35 MCA |
629 | /* Map NVRAM into I/O (ebus) space */ |
630 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
631 | s = SYS_BUS_DEVICE(nvram); | |
07c84741 | 632 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 MCA |
633 | sysbus_mmio_get_region(s, 0)); |
634 | ||
636aa70a | 635 | initrd_size = 0; |
5f2bf0fe | 636 | initrd_addr = 0; |
3ef96221 MA |
637 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
638 | machine->initrd_filename, | |
5f2bf0fe BS |
639 | ram_size, &initrd_size, &initrd_addr, |
640 | &kernel_addr, &kernel_entry); | |
636aa70a | 641 | |
3ef96221 MA |
642 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
643 | machine->boot_order, | |
5f2bf0fe | 644 | kernel_addr, kernel_size, |
3ef96221 | 645 | machine->kernel_cmdline, |
5f2bf0fe | 646 | initrd_addr, initrd_size, |
0d31cb99 BS |
647 | /* XXX: need an option to load a NVRAM image */ |
648 | 0, | |
649 | graphic_width, graphic_height, graphic_depth, | |
6864fa38 | 650 | (uint8_t *)&macaddr); |
83469015 | 651 | |
d6acc8a5 MCA |
652 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
653 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
07c84741 | 654 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); |
d6acc8a5 | 655 | qdev_init_nofail(dev); |
07c84741 | 656 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
657 | &FW_CFG_IO(dev)->comb_iomem); |
658 | ||
659 | fw_cfg = FW_CFG(dev); | |
5836d168 | 660 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 661 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
662 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
663 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
664 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
665 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 666 | if (machine->kernel_cmdline) { |
9c9b0512 | 667 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
668 | strlen(machine->kernel_cmdline) + 1); |
669 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 670 | } else { |
9c9b0512 | 671 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 672 | } |
5f2bf0fe BS |
673 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
674 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 675 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
676 | |
677 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
678 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
679 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
680 | ||
513f789f | 681 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
682 | } |
683 | ||
905fdcb5 BS |
684 | enum { |
685 | sun4u_id = 0, | |
686 | sun4v_id = 64, | |
687 | }; | |
688 | ||
c7ba218d BS |
689 | static const struct hwdef hwdefs[] = { |
690 | /* Sun4u generic PC-like machine */ | |
691 | { | |
905fdcb5 | 692 | .machine_id = sun4u_id, |
e87231d4 BS |
693 | .prom_addr = 0x1fff0000000ULL, |
694 | .console_serial_base = 0, | |
c7ba218d BS |
695 | }, |
696 | /* Sun4v generic PC-like machine */ | |
697 | { | |
905fdcb5 | 698 | .machine_id = sun4v_id, |
e87231d4 BS |
699 | .prom_addr = 0x1fff0000000ULL, |
700 | .console_serial_base = 0, | |
701 | }, | |
c7ba218d BS |
702 | }; |
703 | ||
704 | /* Sun4u hardware initialisation */ | |
3ef96221 | 705 | static void sun4u_init(MachineState *machine) |
5f072e1f | 706 | { |
3ef96221 | 707 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
708 | } |
709 | ||
710 | /* Sun4v hardware initialisation */ | |
3ef96221 | 711 | static void sun4v_init(MachineState *machine) |
5f072e1f | 712 | { |
3ef96221 | 713 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
714 | } |
715 | ||
8a661aea | 716 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 717 | { |
8a661aea AF |
718 | MachineClass *mc = MACHINE_CLASS(oc); |
719 | ||
e264d29d EH |
720 | mc->desc = "Sun4u platform"; |
721 | mc->init = sun4u_init; | |
2059839b | 722 | mc->block_default_type = IF_IDE; |
e264d29d EH |
723 | mc->max_cpus = 1; /* XXX for now */ |
724 | mc->is_default = 1; | |
725 | mc->default_boot_order = "c"; | |
58530461 | 726 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); |
e264d29d | 727 | } |
c7ba218d | 728 | |
8a661aea AF |
729 | static const TypeInfo sun4u_type = { |
730 | .name = MACHINE_TYPE_NAME("sun4u"), | |
731 | .parent = TYPE_MACHINE, | |
732 | .class_init = sun4u_class_init, | |
733 | }; | |
e87231d4 | 734 | |
8a661aea | 735 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 736 | { |
8a661aea AF |
737 | MachineClass *mc = MACHINE_CLASS(oc); |
738 | ||
e264d29d EH |
739 | mc->desc = "Sun4v platform"; |
740 | mc->init = sun4v_init; | |
2059839b | 741 | mc->block_default_type = IF_IDE; |
e264d29d EH |
742 | mc->max_cpus = 1; /* XXX for now */ |
743 | mc->default_boot_order = "c"; | |
58530461 | 744 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); |
e264d29d EH |
745 | } |
746 | ||
8a661aea AF |
747 | static const TypeInfo sun4v_type = { |
748 | .name = MACHINE_TYPE_NAME("sun4v"), | |
749 | .parent = TYPE_MACHINE, | |
750 | .class_init = sun4v_class_init, | |
751 | }; | |
e264d29d | 752 | |
83f7d43a AF |
753 | static void sun4u_register_types(void) |
754 | { | |
25c5d5ac | 755 | type_register_static(&power_info); |
83f7d43a AF |
756 | type_register_static(&ebus_info); |
757 | type_register_static(&prom_info); | |
758 | type_register_static(&ram_info); | |
83f7d43a | 759 | |
8a661aea AF |
760 | type_register_static(&sun4u_type); |
761 | type_register_static(&sun4v_type); | |
8a661aea AF |
762 | } |
763 | ||
83f7d43a | 764 | type_init(sun4u_register_types) |