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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
4771d756 PB |
26 | #include "qemu-common.h" |
27 | #include "cpu.h" | |
83c9f4ca PB |
28 | #include "hw/hw.h" |
29 | #include "hw/pci/pci.h" | |
4272ad40 | 30 | #include "hw/pci/pci_bridge.h" |
6864fa38 | 31 | #include "hw/pci/pci_bus.h" |
0ea833c2 | 32 | #include "hw/pci/pci_host.h" |
0d09e41a PB |
33 | #include "hw/pci-host/apb.h" |
34 | #include "hw/i386/pc.h" | |
35 | #include "hw/char/serial.h" | |
36 | #include "hw/timer/m48t59.h" | |
37 | #include "hw/block/fdc.h" | |
1422e32d | 38 | #include "net/net.h" |
1de7afc9 | 39 | #include "qemu/timer.h" |
9c17d615 | 40 | #include "sysemu/sysemu.h" |
83c9f4ca | 41 | #include "hw/boards.h" |
c6363bae | 42 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 43 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 44 | #include "hw/sparc/sparc64.h" |
0d09e41a | 45 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca PB |
46 | #include "hw/sysbus.h" |
47 | #include "hw/ide.h" | |
6864fa38 | 48 | #include "hw/ide/pci.h" |
83c9f4ca | 49 | #include "hw/loader.h" |
ca20cf32 | 50 | #include "elf.h" |
69520948 | 51 | #include "trace.h" |
f348b6d1 | 52 | #include "qemu/cutils.h" |
3475187d | 53 | |
83469015 FB |
54 | #define KERNEL_LOAD_ADDR 0x00404000 |
55 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 56 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 57 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 58 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e | 59 | #define APB_MEM_BASE 0x1ff00000000ULL |
d63baf92 | 60 | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
f930d07e | 61 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 62 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 63 | #define MAX_IDE_BUS 2 |
3cce6243 | 64 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
65 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
66 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
67 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 68 | |
852e82f3 | 69 | #define IVEC_MAX 0x40 |
9d926598 | 70 | |
c7ba218d | 71 | struct hwdef { |
905fdcb5 | 72 | uint16_t machine_id; |
e87231d4 BS |
73 | uint64_t prom_addr; |
74 | uint64_t console_serial_base; | |
c7ba218d BS |
75 | }; |
76 | ||
c5e6fb7e | 77 | typedef struct EbusState { |
ad6856e8 MCA |
78 | /*< private >*/ |
79 | PCIDevice parent_obj; | |
80 | ||
8c40b8d9 | 81 | ISABus *isa_bus; |
4b10c8d7 | 82 | qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; |
0fe22ffb | 83 | uint64_t console_serial_base; |
c5e6fb7e AK |
84 | MemoryRegion bar0; |
85 | MemoryRegion bar1; | |
86 | } EbusState; | |
87 | ||
ad6856e8 MCA |
88 | #define TYPE_EBUS "ebus" |
89 | #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) | |
90 | ||
57146941 | 91 | void DMA_init(ISABus *bus, int high_page_enable) |
4556bd8b BS |
92 | { |
93 | } | |
94 | ||
ddcd5531 GA |
95 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
96 | Error **errp) | |
81864572 | 97 | { |
48779e50 | 98 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
99 | } |
100 | ||
31688246 | 101 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
102 | const char *arch, ram_addr_t RAM_size, |
103 | const char *boot_devices, | |
104 | uint32_t kernel_image, uint32_t kernel_size, | |
105 | const char *cmdline, | |
106 | uint32_t initrd_image, uint32_t initrd_size, | |
107 | uint32_t NVRAM_image, | |
108 | int width, int height, int depth, | |
109 | const uint8_t *macaddr) | |
83469015 | 110 | { |
66508601 | 111 | unsigned int i; |
2024c014 | 112 | int sysp_end; |
d2c63fc1 | 113 | uint8_t image[0x1ff0]; |
31688246 | 114 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
115 | |
116 | memset(image, '\0', sizeof(image)); | |
117 | ||
2024c014 TH |
118 | /* OpenBIOS nvram variables partition */ |
119 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
83469015 | 120 | |
2024c014 TH |
121 | /* Free space partition */ |
122 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 123 | |
0d31cb99 BS |
124 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
125 | ||
31688246 HP |
126 | for (i = 0; i < sizeof(image); i++) { |
127 | (k->write)(nvram, i, image[i]); | |
128 | } | |
66508601 | 129 | |
83469015 | 130 | return 0; |
3475187d | 131 | } |
5f2bf0fe BS |
132 | |
133 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
134 | const char *initrd_filename, | |
135 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
136 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
137 | uint64_t *kernel_entry) | |
636aa70a BS |
138 | { |
139 | int linux_boot; | |
140 | unsigned int i; | |
141 | long kernel_size; | |
6908d9ce | 142 | uint8_t *ptr; |
5f2bf0fe | 143 | uint64_t kernel_top; |
636aa70a BS |
144 | |
145 | linux_boot = (kernel_filename != NULL); | |
146 | ||
147 | kernel_size = 0; | |
148 | if (linux_boot) { | |
ca20cf32 BS |
149 | int bswap_needed; |
150 | ||
151 | #ifdef BSWAP_NEEDED | |
152 | bswap_needed = 1; | |
153 | #else | |
154 | bswap_needed = 0; | |
155 | #endif | |
5f2bf0fe | 156 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
7ef295ea | 157 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); |
5f2bf0fe BS |
158 | if (kernel_size < 0) { |
159 | *kernel_addr = KERNEL_LOAD_ADDR; | |
160 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 161 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
162 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
163 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
164 | } |
165 | if (kernel_size < 0) { | |
636aa70a BS |
166 | kernel_size = load_image_targphys(kernel_filename, |
167 | KERNEL_LOAD_ADDR, | |
168 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 169 | } |
636aa70a BS |
170 | if (kernel_size < 0) { |
171 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
172 | kernel_filename); | |
173 | exit(1); | |
174 | } | |
5f2bf0fe | 175 | /* load initrd above kernel */ |
636aa70a BS |
176 | *initrd_size = 0; |
177 | if (initrd_filename) { | |
5f2bf0fe BS |
178 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
179 | ||
636aa70a | 180 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
181 | *initrd_addr, |
182 | RAM_size - *initrd_addr); | |
183 | if ((int)*initrd_size < 0) { | |
636aa70a BS |
184 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
185 | initrd_filename); | |
186 | exit(1); | |
187 | } | |
188 | } | |
189 | if (*initrd_size > 0) { | |
190 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 191 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 192 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 193 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 194 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
195 | break; |
196 | } | |
197 | } | |
198 | } | |
199 | } | |
200 | return kernel_size; | |
201 | } | |
3475187d | 202 | |
e87231d4 | 203 | typedef struct ResetData { |
403d7a2d | 204 | SPARCCPU *cpu; |
44a99354 | 205 | uint64_t prom_addr; |
e87231d4 BS |
206 | } ResetData; |
207 | ||
4b10c8d7 | 208 | static void ebus_isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 209 | { |
4b10c8d7 MCA |
210 | EbusState *s = EBUS(opaque); |
211 | qemu_irq irq = s->isa_bus_irqs[n]; | |
212 | ||
213 | /* Pass ISA bus IRQs onto their gpio equivalent */ | |
69520948 | 214 | trace_ebus_isa_irq_handler(n, level); |
4b10c8d7 MCA |
215 | if (irq) { |
216 | qemu_set_irq(irq, level); | |
361dea40 | 217 | } |
1387fe4a BS |
218 | } |
219 | ||
c190ea07 | 220 | /* EBUS (Eight bit bus) bridge */ |
ad6856e8 | 221 | static void ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 222 | { |
ad6856e8 | 223 | EbusState *s = EBUS(pci_dev); |
0fe22ffb | 224 | DeviceState *dev; |
c796edda | 225 | qemu_irq *isa_irq; |
0fe22ffb MCA |
226 | DriveInfo *fd[MAX_FD]; |
227 | int i; | |
c5e6fb7e | 228 | |
8c40b8d9 MCA |
229 | s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
230 | pci_address_space_io(pci_dev), errp); | |
231 | if (!s->isa_bus) { | |
232 | error_setg(errp, "unable to instantiate EBUS ISA bus"); | |
d10e5432 MA |
233 | return; |
234 | } | |
c5e6fb7e | 235 | |
4b10c8d7 MCA |
236 | /* ISA bus */ |
237 | isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); | |
c796edda | 238 | isa_bus_irqs(s->isa_bus, isa_irq); |
4b10c8d7 MCA |
239 | qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", |
240 | ISA_NUM_IRQS); | |
c796edda | 241 | |
0fe22ffb MCA |
242 | /* Serial ports */ |
243 | i = 0; | |
244 | if (s->console_serial_base) { | |
245 | serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, | |
246 | 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); | |
247 | i++; | |
248 | } | |
249 | serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); | |
250 | ||
251 | /* Parallel ports */ | |
252 | parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); | |
253 | ||
254 | /* Keyboard */ | |
255 | isa_create_simple(s->isa_bus, "i8042"); | |
256 | ||
257 | /* Floppy */ | |
258 | for (i = 0; i < MAX_FD; i++) { | |
259 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
260 | } | |
261 | dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); | |
262 | if (fd[0]) { | |
263 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
264 | &error_abort); | |
265 | } | |
266 | if (fd[1]) { | |
267 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
268 | &error_abort); | |
269 | } | |
270 | qdev_prop_set_uint32(dev, "dma", -1); | |
271 | qdev_init_nofail(dev); | |
272 | ||
273 | /* PCI */ | |
c5e6fb7e AK |
274 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
275 | pci_dev->config[0x05] = 0x00; | |
276 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
277 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
278 | pci_dev->config[0x09] = 0x00; // programming i/f | |
279 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
280 | ||
0a70e094 PB |
281 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
282 | 0, 0x1000000); | |
e824b2cc | 283 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 284 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
f3b18f35 | 285 | 0, 0x4000); |
a1cf8be5 | 286 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
287 | } |
288 | ||
0fe22ffb MCA |
289 | static Property ebus_properties[] = { |
290 | DEFINE_PROP_UINT64("console-serial-base", EbusState, | |
291 | console_serial_base, 0), | |
292 | DEFINE_PROP_END_OF_LIST(), | |
293 | }; | |
294 | ||
40021f08 AL |
295 | static void ebus_class_init(ObjectClass *klass, void *data) |
296 | { | |
297 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
0fe22ffb | 298 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 299 | |
ad6856e8 | 300 | k->realize = ebus_realize; |
40021f08 AL |
301 | k->vendor_id = PCI_VENDOR_ID_SUN; |
302 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
303 | k->revision = 0x01; | |
304 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
0fe22ffb | 305 | dc->props = ebus_properties; |
40021f08 AL |
306 | } |
307 | ||
8c43a6f0 | 308 | static const TypeInfo ebus_info = { |
ad6856e8 | 309 | .name = TYPE_EBUS, |
39bffca2 | 310 | .parent = TYPE_PCI_DEVICE, |
39bffca2 | 311 | .class_init = ebus_class_init, |
ad6856e8 | 312 | .instance_size = sizeof(EbusState), |
fd3b02c8 EH |
313 | .interfaces = (InterfaceInfo[]) { |
314 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
315 | { }, | |
316 | }, | |
53e3c4f9 BS |
317 | }; |
318 | ||
13575cf6 AF |
319 | #define TYPE_OPENPROM "openprom" |
320 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
321 | ||
d4edce38 | 322 | typedef struct PROMState { |
13575cf6 AF |
323 | SysBusDevice parent_obj; |
324 | ||
d4edce38 AK |
325 | MemoryRegion prom; |
326 | } PROMState; | |
327 | ||
409dbce5 AJ |
328 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
329 | { | |
a8170e5e | 330 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
331 | return addr + *base_addr - PROM_VADDR; |
332 | } | |
333 | ||
1baffa46 | 334 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 335 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
336 | { |
337 | DeviceState *dev; | |
338 | SysBusDevice *s; | |
339 | char *filename; | |
340 | int ret; | |
341 | ||
13575cf6 | 342 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 343 | qdev_init_nofail(dev); |
1356b98d | 344 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
345 | |
346 | sysbus_mmio_map(s, 0, addr); | |
347 | ||
348 | /* load boot prom */ | |
349 | if (bios_name == NULL) { | |
350 | bios_name = PROM_FILENAME; | |
351 | } | |
352 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
353 | if (filename) { | |
409dbce5 | 354 | ret = load_elf(filename, translate_prom_address, &addr, |
7ef295ea | 355 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
356 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
357 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
358 | } | |
7267c094 | 359 | g_free(filename); |
1baffa46 BS |
360 | } else { |
361 | ret = -1; | |
362 | } | |
363 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
364 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
365 | exit(1); | |
366 | } | |
367 | } | |
368 | ||
78fb261d | 369 | static void prom_init1(Object *obj) |
1baffa46 | 370 | { |
78fb261d XZ |
371 | PROMState *s = OPENPROM(obj); |
372 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
1baffa46 | 373 | |
1cfe48c1 | 374 | memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, |
f8ed85ac | 375 | &error_fatal); |
c5705a77 | 376 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 377 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 378 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
379 | } |
380 | ||
999e12bb AL |
381 | static Property prom_properties[] = { |
382 | {/* end of property list */}, | |
383 | }; | |
384 | ||
385 | static void prom_class_init(ObjectClass *klass, void *data) | |
386 | { | |
39bffca2 | 387 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 388 | |
39bffca2 | 389 | dc->props = prom_properties; |
999e12bb AL |
390 | } |
391 | ||
8c43a6f0 | 392 | static const TypeInfo prom_info = { |
13575cf6 | 393 | .name = TYPE_OPENPROM, |
39bffca2 AL |
394 | .parent = TYPE_SYS_BUS_DEVICE, |
395 | .instance_size = sizeof(PROMState), | |
396 | .class_init = prom_class_init, | |
78fb261d | 397 | .instance_init = prom_init1, |
1baffa46 BS |
398 | }; |
399 | ||
bda42033 | 400 | |
88c034d5 AF |
401 | #define TYPE_SUN4U_MEMORY "memory" |
402 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
403 | ||
404 | typedef struct RamDevice { | |
405 | SysBusDevice parent_obj; | |
406 | ||
d4edce38 | 407 | MemoryRegion ram; |
04843626 | 408 | uint64_t size; |
bda42033 BS |
409 | } RamDevice; |
410 | ||
411 | /* System RAM */ | |
78fb261d | 412 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 413 | { |
88c034d5 | 414 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 415 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 416 | |
1cfe48c1 | 417 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 418 | &error_fatal); |
c5705a77 | 419 | vmstate_register_ram_global(&d->ram); |
78fb261d | 420 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
421 | } |
422 | ||
a8170e5e | 423 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
424 | { |
425 | DeviceState *dev; | |
426 | SysBusDevice *s; | |
427 | RamDevice *d; | |
428 | ||
429 | /* allocate RAM */ | |
88c034d5 | 430 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 431 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 432 | |
88c034d5 | 433 | d = SUN4U_RAM(dev); |
bda42033 | 434 | d->size = RAM_size; |
e23a1b33 | 435 | qdev_init_nofail(dev); |
bda42033 BS |
436 | |
437 | sysbus_mmio_map(s, 0, addr); | |
438 | } | |
439 | ||
999e12bb AL |
440 | static Property ram_properties[] = { |
441 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
442 | DEFINE_PROP_END_OF_LIST(), | |
443 | }; | |
444 | ||
445 | static void ram_class_init(ObjectClass *klass, void *data) | |
446 | { | |
39bffca2 | 447 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 448 | |
78fb261d | 449 | dc->realize = ram_realize; |
39bffca2 | 450 | dc->props = ram_properties; |
999e12bb AL |
451 | } |
452 | ||
8c43a6f0 | 453 | static const TypeInfo ram_info = { |
88c034d5 | 454 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
455 | .parent = TYPE_SYS_BUS_DEVICE, |
456 | .instance_size = sizeof(RamDevice), | |
457 | .class_init = ram_class_init, | |
bda42033 BS |
458 | }; |
459 | ||
38bc50f7 | 460 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 461 | MachineState *machine, |
7b833f5b BS |
462 | const struct hwdef *hwdef) |
463 | { | |
f9d1465f | 464 | SPARCCPU *cpu; |
31688246 | 465 | Nvram *nvram; |
7b833f5b | 466 | unsigned int i; |
5f2bf0fe | 467 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
b14dcaf4 | 468 | SabreState *apb; |
311f2b7a | 469 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 470 | PCIDevice *ebus, *pci_dev; |
f3b18f35 | 471 | SysBusDevice *s; |
f455e98c | 472 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
aea5b071 | 473 | DeviceState *iommu, *dev; |
a88b362c | 474 | FWCfgState *fw_cfg; |
8d932971 | 475 | NICInfo *nd; |
6864fa38 MCA |
476 | MACAddr macaddr; |
477 | bool onboard_nic; | |
7b833f5b | 478 | |
7b833f5b | 479 | /* init CPUs */ |
58530461 | 480 | cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); |
7b833f5b | 481 | |
aea5b071 MCA |
482 | /* IOMMU */ |
483 | iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); | |
484 | qdev_init_nofail(iommu); | |
485 | ||
bda42033 | 486 | /* set up devices */ |
3ef96221 | 487 | ram_init(0, machine->ram_size); |
3475187d | 488 | |
1baffa46 | 489 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 490 | |
b14dcaf4 MCA |
491 | /* Init sabre (PCI host bridge) */ |
492 | apb = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); | |
cacd0580 MCA |
493 | qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); |
494 | qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); | |
aea5b071 | 495 | object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort); |
cacd0580 | 496 | qdev_init_nofail(DEVICE(apb)); |
2a4d6af5 MCA |
497 | |
498 | /* Wire up PCI interrupts to CPU */ | |
499 | for (i = 0; i < IVEC_MAX; i++) { | |
500 | qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i, | |
501 | qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); | |
502 | } | |
503 | ||
588978c0 | 504 | pci_bus = PCI_HOST_BRIDGE(apb)->bus; |
4272ad40 MCA |
505 | pci_busA = pci_bridge_get_sec_bus(apb->bridgeA); |
506 | pci_busB = pci_bridge_get_sec_bus(apb->bridgeB); | |
83469015 | 507 | |
6864fa38 MCA |
508 | /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is |
509 | reserved (leaving no slots free after on-board devices) however slots | |
510 | 0-3 are free on busB */ | |
511 | pci_bus->slot_reserved_mask = 0xfffffffc; | |
512 | pci_busA->slot_reserved_mask = 0xfffffff1; | |
513 | pci_busB->slot_reserved_mask = 0xfffffff0; | |
514 | ||
ad6856e8 | 515 | ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); |
0fe22ffb MCA |
516 | qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", |
517 | hwdef->console_serial_base); | |
6864fa38 MCA |
518 | qdev_init_nofail(DEVICE(ebus)); |
519 | ||
4b10c8d7 MCA |
520 | /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */ |
521 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, | |
522 | qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ)); | |
523 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, | |
524 | qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ)); | |
525 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, | |
526 | qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ)); | |
527 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, | |
528 | qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ)); | |
529 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, | |
530 | qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ)); | |
531 | ||
6864fa38 MCA |
532 | pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); |
533 | ||
534 | memset(&macaddr, 0, sizeof(MACAddr)); | |
535 | onboard_nic = false; | |
8d932971 MCA |
536 | for (i = 0; i < nb_nics; i++) { |
537 | nd = &nd_table[i]; | |
538 | ||
6864fa38 MCA |
539 | if (!nd->model || strcmp(nd->model, "sunhme") == 0) { |
540 | if (!onboard_nic) { | |
541 | pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), | |
542 | true, "sunhme"); | |
543 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); | |
544 | onboard_nic = true; | |
545 | } else { | |
bcf9e2c2 | 546 | pci_dev = pci_create(pci_busB, -1, "sunhme"); |
6864fa38 | 547 | } |
8d932971 | 548 | } else { |
bcf9e2c2 | 549 | pci_dev = pci_create(pci_busB, -1, nd->model); |
8d932971 | 550 | } |
6864fa38 MCA |
551 | |
552 | dev = &pci_dev->qdev; | |
553 | qdev_set_nic_properties(dev, nd); | |
554 | qdev_init_nofail(dev); | |
555 | } | |
556 | ||
557 | /* If we don't have an onboard NIC, grab a default MAC address so that | |
558 | * we have a valid machine id */ | |
559 | if (!onboard_nic) { | |
560 | qemu_macaddr_default_if_unset(&macaddr); | |
8d932971 | 561 | } |
83469015 | 562 | |
d8f94e1b | 563 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
e4bcb14c | 564 | |
6864fa38 MCA |
565 | pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); |
566 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); | |
567 | qdev_init_nofail(&pci_dev->qdev); | |
568 | pci_ide_create_devs(pci_dev, hd); | |
3b898dda | 569 | |
f3b18f35 MCA |
570 | /* Map NVRAM into I/O (ebus) space */ |
571 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
572 | s = SYS_BUS_DEVICE(nvram); | |
07c84741 | 573 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 MCA |
574 | sysbus_mmio_get_region(s, 0)); |
575 | ||
636aa70a | 576 | initrd_size = 0; |
5f2bf0fe | 577 | initrd_addr = 0; |
3ef96221 MA |
578 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
579 | machine->initrd_filename, | |
5f2bf0fe BS |
580 | ram_size, &initrd_size, &initrd_addr, |
581 | &kernel_addr, &kernel_entry); | |
636aa70a | 582 | |
3ef96221 MA |
583 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
584 | machine->boot_order, | |
5f2bf0fe | 585 | kernel_addr, kernel_size, |
3ef96221 | 586 | machine->kernel_cmdline, |
5f2bf0fe | 587 | initrd_addr, initrd_size, |
0d31cb99 BS |
588 | /* XXX: need an option to load a NVRAM image */ |
589 | 0, | |
590 | graphic_width, graphic_height, graphic_depth, | |
6864fa38 | 591 | (uint8_t *)&macaddr); |
83469015 | 592 | |
d6acc8a5 MCA |
593 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
594 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
07c84741 | 595 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); |
d6acc8a5 | 596 | qdev_init_nofail(dev); |
07c84741 | 597 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
598 | &FW_CFG_IO(dev)->comb_iomem); |
599 | ||
600 | fw_cfg = FW_CFG(dev); | |
5836d168 | 601 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 602 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
603 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
604 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
605 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
606 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 607 | if (machine->kernel_cmdline) { |
9c9b0512 | 608 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
609 | strlen(machine->kernel_cmdline) + 1); |
610 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 611 | } else { |
9c9b0512 | 612 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 613 | } |
5f2bf0fe BS |
614 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
615 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 616 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
617 | |
618 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
619 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
620 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
621 | ||
513f789f | 622 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
623 | } |
624 | ||
905fdcb5 BS |
625 | enum { |
626 | sun4u_id = 0, | |
627 | sun4v_id = 64, | |
628 | }; | |
629 | ||
c7ba218d BS |
630 | static const struct hwdef hwdefs[] = { |
631 | /* Sun4u generic PC-like machine */ | |
632 | { | |
905fdcb5 | 633 | .machine_id = sun4u_id, |
e87231d4 BS |
634 | .prom_addr = 0x1fff0000000ULL, |
635 | .console_serial_base = 0, | |
c7ba218d BS |
636 | }, |
637 | /* Sun4v generic PC-like machine */ | |
638 | { | |
905fdcb5 | 639 | .machine_id = sun4v_id, |
e87231d4 BS |
640 | .prom_addr = 0x1fff0000000ULL, |
641 | .console_serial_base = 0, | |
642 | }, | |
c7ba218d BS |
643 | }; |
644 | ||
645 | /* Sun4u hardware initialisation */ | |
3ef96221 | 646 | static void sun4u_init(MachineState *machine) |
5f072e1f | 647 | { |
3ef96221 | 648 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
649 | } |
650 | ||
651 | /* Sun4v hardware initialisation */ | |
3ef96221 | 652 | static void sun4v_init(MachineState *machine) |
5f072e1f | 653 | { |
3ef96221 | 654 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
655 | } |
656 | ||
8a661aea | 657 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 658 | { |
8a661aea AF |
659 | MachineClass *mc = MACHINE_CLASS(oc); |
660 | ||
e264d29d EH |
661 | mc->desc = "Sun4u platform"; |
662 | mc->init = sun4u_init; | |
2059839b | 663 | mc->block_default_type = IF_IDE; |
e264d29d EH |
664 | mc->max_cpus = 1; /* XXX for now */ |
665 | mc->is_default = 1; | |
666 | mc->default_boot_order = "c"; | |
58530461 | 667 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); |
e264d29d | 668 | } |
c7ba218d | 669 | |
8a661aea AF |
670 | static const TypeInfo sun4u_type = { |
671 | .name = MACHINE_TYPE_NAME("sun4u"), | |
672 | .parent = TYPE_MACHINE, | |
673 | .class_init = sun4u_class_init, | |
674 | }; | |
e87231d4 | 675 | |
8a661aea | 676 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 677 | { |
8a661aea AF |
678 | MachineClass *mc = MACHINE_CLASS(oc); |
679 | ||
e264d29d EH |
680 | mc->desc = "Sun4v platform"; |
681 | mc->init = sun4v_init; | |
2059839b | 682 | mc->block_default_type = IF_IDE; |
e264d29d EH |
683 | mc->max_cpus = 1; /* XXX for now */ |
684 | mc->default_boot_order = "c"; | |
58530461 | 685 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); |
e264d29d EH |
686 | } |
687 | ||
8a661aea AF |
688 | static const TypeInfo sun4v_type = { |
689 | .name = MACHINE_TYPE_NAME("sun4v"), | |
690 | .parent = TYPE_MACHINE, | |
691 | .class_init = sun4v_class_init, | |
692 | }; | |
e264d29d | 693 | |
83f7d43a AF |
694 | static void sun4u_register_types(void) |
695 | { | |
696 | type_register_static(&ebus_info); | |
697 | type_register_static(&prom_info); | |
698 | type_register_static(&ram_info); | |
83f7d43a | 699 | |
8a661aea AF |
700 | type_register_static(&sun4u_type); |
701 | type_register_static(&sun4v_type); | |
8a661aea AF |
702 | } |
703 | ||
83f7d43a | 704 | type_init(sun4u_register_types) |