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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
29bd7231 | 25 | #include "qemu/error-report.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
83c9f4ca PB |
29 | #include "hw/hw.h" |
30 | #include "hw/pci/pci.h" | |
4272ad40 | 31 | #include "hw/pci/pci_bridge.h" |
6864fa38 | 32 | #include "hw/pci/pci_bus.h" |
0ea833c2 | 33 | #include "hw/pci/pci_host.h" |
9b301794 | 34 | #include "hw/pci-host/sabre.h" |
0d09e41a PB |
35 | #include "hw/i386/pc.h" |
36 | #include "hw/char/serial.h" | |
bb3d5ea8 | 37 | #include "hw/char/parallel.h" |
0d09e41a | 38 | #include "hw/timer/m48t59.h" |
47973a2d | 39 | #include "hw/input/i8042.h" |
0d09e41a | 40 | #include "hw/block/fdc.h" |
1422e32d | 41 | #include "net/net.h" |
1de7afc9 | 42 | #include "qemu/timer.h" |
9c17d615 | 43 | #include "sysemu/sysemu.h" |
83c9f4ca | 44 | #include "hw/boards.h" |
c6363bae | 45 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 46 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 47 | #include "hw/sparc/sparc64.h" |
0d09e41a | 48 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca PB |
49 | #include "hw/sysbus.h" |
50 | #include "hw/ide.h" | |
6864fa38 | 51 | #include "hw/ide/pci.h" |
83c9f4ca | 52 | #include "hw/loader.h" |
ca20cf32 | 53 | #include "elf.h" |
69520948 | 54 | #include "trace.h" |
f348b6d1 | 55 | #include "qemu/cutils.h" |
3475187d | 56 | |
83469015 FB |
57 | #define KERNEL_LOAD_ADDR 0x00404000 |
58 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 59 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 60 | #define PROM_VADDR 0x000ffd00000ULL |
5795162a MCA |
61 | #define PBM_SPECIAL_BASE 0x1fe00000000ULL |
62 | #define PBM_MEM_BASE 0x1ff00000000ULL | |
63 | #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) | |
f930d07e | 64 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 65 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 66 | #define MAX_IDE_BUS 2 |
3cce6243 | 67 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
68 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
69 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
70 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 71 | |
852e82f3 | 72 | #define IVEC_MAX 0x40 |
9d926598 | 73 | |
c7ba218d | 74 | struct hwdef { |
905fdcb5 | 75 | uint16_t machine_id; |
e87231d4 BS |
76 | uint64_t prom_addr; |
77 | uint64_t console_serial_base; | |
c7ba218d BS |
78 | }; |
79 | ||
c5e6fb7e | 80 | typedef struct EbusState { |
ad6856e8 MCA |
81 | /*< private >*/ |
82 | PCIDevice parent_obj; | |
83 | ||
8c40b8d9 | 84 | ISABus *isa_bus; |
4b10c8d7 | 85 | qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; |
0fe22ffb | 86 | uint64_t console_serial_base; |
c5e6fb7e AK |
87 | MemoryRegion bar0; |
88 | MemoryRegion bar1; | |
89 | } EbusState; | |
90 | ||
ad6856e8 MCA |
91 | #define TYPE_EBUS "ebus" |
92 | #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) | |
93 | ||
ddcd5531 GA |
94 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
95 | Error **errp) | |
81864572 | 96 | { |
48779e50 | 97 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
98 | } |
99 | ||
31688246 | 100 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
101 | const char *arch, ram_addr_t RAM_size, |
102 | const char *boot_devices, | |
103 | uint32_t kernel_image, uint32_t kernel_size, | |
104 | const char *cmdline, | |
105 | uint32_t initrd_image, uint32_t initrd_size, | |
106 | uint32_t NVRAM_image, | |
107 | int width, int height, int depth, | |
108 | const uint8_t *macaddr) | |
83469015 | 109 | { |
66508601 | 110 | unsigned int i; |
2024c014 | 111 | int sysp_end; |
d2c63fc1 | 112 | uint8_t image[0x1ff0]; |
31688246 | 113 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
114 | |
115 | memset(image, '\0', sizeof(image)); | |
116 | ||
2024c014 TH |
117 | /* OpenBIOS nvram variables partition */ |
118 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
83469015 | 119 | |
2024c014 TH |
120 | /* Free space partition */ |
121 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 122 | |
0d31cb99 BS |
123 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
124 | ||
31688246 HP |
125 | for (i = 0; i < sizeof(image); i++) { |
126 | (k->write)(nvram, i, image[i]); | |
127 | } | |
66508601 | 128 | |
83469015 | 129 | return 0; |
3475187d | 130 | } |
5f2bf0fe BS |
131 | |
132 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
133 | const char *initrd_filename, | |
134 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
135 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
136 | uint64_t *kernel_entry) | |
636aa70a BS |
137 | { |
138 | int linux_boot; | |
139 | unsigned int i; | |
140 | long kernel_size; | |
6908d9ce | 141 | uint8_t *ptr; |
5f2bf0fe | 142 | uint64_t kernel_top; |
636aa70a BS |
143 | |
144 | linux_boot = (kernel_filename != NULL); | |
145 | ||
146 | kernel_size = 0; | |
147 | if (linux_boot) { | |
ca20cf32 BS |
148 | int bswap_needed; |
149 | ||
150 | #ifdef BSWAP_NEEDED | |
151 | bswap_needed = 1; | |
152 | #else | |
153 | bswap_needed = 0; | |
154 | #endif | |
5f2bf0fe | 155 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
7ef295ea | 156 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); |
5f2bf0fe BS |
157 | if (kernel_size < 0) { |
158 | *kernel_addr = KERNEL_LOAD_ADDR; | |
159 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 160 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
161 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
162 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
163 | } |
164 | if (kernel_size < 0) { | |
636aa70a BS |
165 | kernel_size = load_image_targphys(kernel_filename, |
166 | KERNEL_LOAD_ADDR, | |
167 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 168 | } |
636aa70a | 169 | if (kernel_size < 0) { |
29bd7231 | 170 | error_report("could not load kernel '%s'", kernel_filename); |
636aa70a BS |
171 | exit(1); |
172 | } | |
5f2bf0fe | 173 | /* load initrd above kernel */ |
636aa70a BS |
174 | *initrd_size = 0; |
175 | if (initrd_filename) { | |
5f2bf0fe BS |
176 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
177 | ||
636aa70a | 178 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
179 | *initrd_addr, |
180 | RAM_size - *initrd_addr); | |
181 | if ((int)*initrd_size < 0) { | |
29bd7231 AF |
182 | error_report("could not load initial ram disk '%s'", |
183 | initrd_filename); | |
636aa70a BS |
184 | exit(1); |
185 | } | |
186 | } | |
187 | if (*initrd_size > 0) { | |
188 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 189 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 190 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 191 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 192 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
193 | break; |
194 | } | |
195 | } | |
196 | } | |
197 | } | |
198 | return kernel_size; | |
199 | } | |
3475187d | 200 | |
e87231d4 | 201 | typedef struct ResetData { |
403d7a2d | 202 | SPARCCPU *cpu; |
44a99354 | 203 | uint64_t prom_addr; |
e87231d4 BS |
204 | } ResetData; |
205 | ||
25c5d5ac MCA |
206 | #define TYPE_SUN4U_POWER "power" |
207 | #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) | |
208 | ||
209 | typedef struct PowerDevice { | |
210 | SysBusDevice parent_obj; | |
211 | ||
212 | MemoryRegion power_mmio; | |
213 | } PowerDevice; | |
214 | ||
215 | /* Power */ | |
216 | static void power_mem_write(void *opaque, hwaddr addr, | |
217 | uint64_t val, unsigned size) | |
218 | { | |
219 | /* According to a real Ultra 5, bit 24 controls the power */ | |
220 | if (val & 0x1000000) { | |
221 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
222 | } | |
223 | } | |
224 | ||
225 | static const MemoryRegionOps power_mem_ops = { | |
226 | .write = power_mem_write, | |
227 | .endianness = DEVICE_NATIVE_ENDIAN, | |
228 | .valid = { | |
229 | .min_access_size = 4, | |
230 | .max_access_size = 4, | |
231 | }, | |
232 | }; | |
233 | ||
234 | static void power_realize(DeviceState *dev, Error **errp) | |
235 | { | |
236 | PowerDevice *d = SUN4U_POWER(dev); | |
237 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
238 | ||
239 | memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, | |
240 | "power", sizeof(uint32_t)); | |
241 | ||
242 | sysbus_init_mmio(sbd, &d->power_mmio); | |
243 | } | |
244 | ||
245 | static void power_class_init(ObjectClass *klass, void *data) | |
246 | { | |
247 | DeviceClass *dc = DEVICE_CLASS(klass); | |
248 | ||
249 | dc->realize = power_realize; | |
250 | } | |
251 | ||
252 | static const TypeInfo power_info = { | |
253 | .name = TYPE_SUN4U_POWER, | |
254 | .parent = TYPE_SYS_BUS_DEVICE, | |
255 | .instance_size = sizeof(PowerDevice), | |
256 | .class_init = power_class_init, | |
257 | }; | |
258 | ||
4b10c8d7 | 259 | static void ebus_isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 260 | { |
4b10c8d7 MCA |
261 | EbusState *s = EBUS(opaque); |
262 | qemu_irq irq = s->isa_bus_irqs[n]; | |
263 | ||
264 | /* Pass ISA bus IRQs onto their gpio equivalent */ | |
69520948 | 265 | trace_ebus_isa_irq_handler(n, level); |
4b10c8d7 MCA |
266 | if (irq) { |
267 | qemu_set_irq(irq, level); | |
361dea40 | 268 | } |
1387fe4a BS |
269 | } |
270 | ||
c190ea07 | 271 | /* EBUS (Eight bit bus) bridge */ |
ad6856e8 | 272 | static void ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 273 | { |
ad6856e8 | 274 | EbusState *s = EBUS(pci_dev); |
25c5d5ac | 275 | SysBusDevice *sbd; |
0fe22ffb | 276 | DeviceState *dev; |
c796edda | 277 | qemu_irq *isa_irq; |
0fe22ffb MCA |
278 | DriveInfo *fd[MAX_FD]; |
279 | int i; | |
c5e6fb7e | 280 | |
8c40b8d9 MCA |
281 | s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
282 | pci_address_space_io(pci_dev), errp); | |
283 | if (!s->isa_bus) { | |
284 | error_setg(errp, "unable to instantiate EBUS ISA bus"); | |
d10e5432 MA |
285 | return; |
286 | } | |
c5e6fb7e | 287 | |
4b10c8d7 MCA |
288 | /* ISA bus */ |
289 | isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); | |
c796edda | 290 | isa_bus_irqs(s->isa_bus, isa_irq); |
4b10c8d7 MCA |
291 | qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", |
292 | ISA_NUM_IRQS); | |
c796edda | 293 | |
0fe22ffb MCA |
294 | /* Serial ports */ |
295 | i = 0; | |
296 | if (s->console_serial_base) { | |
297 | serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, | |
9bca0edb | 298 | 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); |
0fe22ffb MCA |
299 | i++; |
300 | } | |
def337ff | 301 | serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); |
0fe22ffb MCA |
302 | |
303 | /* Parallel ports */ | |
304 | parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); | |
305 | ||
306 | /* Keyboard */ | |
307 | isa_create_simple(s->isa_bus, "i8042"); | |
308 | ||
309 | /* Floppy */ | |
310 | for (i = 0; i < MAX_FD; i++) { | |
311 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
312 | } | |
313 | dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); | |
314 | if (fd[0]) { | |
315 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
316 | &error_abort); | |
317 | } | |
318 | if (fd[1]) { | |
319 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
320 | &error_abort); | |
321 | } | |
322 | qdev_prop_set_uint32(dev, "dma", -1); | |
323 | qdev_init_nofail(dev); | |
324 | ||
25c5d5ac MCA |
325 | /* Power */ |
326 | dev = qdev_create(NULL, TYPE_SUN4U_POWER); | |
327 | qdev_init_nofail(dev); | |
328 | sbd = SYS_BUS_DEVICE(dev); | |
329 | memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, | |
330 | sysbus_mmio_get_region(sbd, 0)); | |
331 | ||
0fe22ffb | 332 | /* PCI */ |
c5e6fb7e AK |
333 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
334 | pci_dev->config[0x05] = 0x00; | |
335 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
336 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
337 | pci_dev->config[0x09] = 0x00; // programming i/f | |
338 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
339 | ||
0a70e094 PB |
340 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
341 | 0, 0x1000000); | |
e824b2cc | 342 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 343 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
25c5d5ac | 344 | 0, 0x8000); |
a1cf8be5 | 345 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
346 | } |
347 | ||
0fe22ffb MCA |
348 | static Property ebus_properties[] = { |
349 | DEFINE_PROP_UINT64("console-serial-base", EbusState, | |
350 | console_serial_base, 0), | |
351 | DEFINE_PROP_END_OF_LIST(), | |
352 | }; | |
353 | ||
40021f08 AL |
354 | static void ebus_class_init(ObjectClass *klass, void *data) |
355 | { | |
356 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
0fe22ffb | 357 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 358 | |
ad6856e8 | 359 | k->realize = ebus_realize; |
40021f08 AL |
360 | k->vendor_id = PCI_VENDOR_ID_SUN; |
361 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
362 | k->revision = 0x01; | |
363 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
0fe22ffb | 364 | dc->props = ebus_properties; |
40021f08 AL |
365 | } |
366 | ||
8c43a6f0 | 367 | static const TypeInfo ebus_info = { |
ad6856e8 | 368 | .name = TYPE_EBUS, |
39bffca2 | 369 | .parent = TYPE_PCI_DEVICE, |
39bffca2 | 370 | .class_init = ebus_class_init, |
ad6856e8 | 371 | .instance_size = sizeof(EbusState), |
fd3b02c8 EH |
372 | .interfaces = (InterfaceInfo[]) { |
373 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
374 | { }, | |
375 | }, | |
53e3c4f9 BS |
376 | }; |
377 | ||
13575cf6 AF |
378 | #define TYPE_OPENPROM "openprom" |
379 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
380 | ||
d4edce38 | 381 | typedef struct PROMState { |
13575cf6 AF |
382 | SysBusDevice parent_obj; |
383 | ||
d4edce38 AK |
384 | MemoryRegion prom; |
385 | } PROMState; | |
386 | ||
409dbce5 AJ |
387 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
388 | { | |
a8170e5e | 389 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
390 | return addr + *base_addr - PROM_VADDR; |
391 | } | |
392 | ||
1baffa46 | 393 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 394 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
395 | { |
396 | DeviceState *dev; | |
397 | SysBusDevice *s; | |
398 | char *filename; | |
399 | int ret; | |
400 | ||
13575cf6 | 401 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 402 | qdev_init_nofail(dev); |
1356b98d | 403 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
404 | |
405 | sysbus_mmio_map(s, 0, addr); | |
406 | ||
407 | /* load boot prom */ | |
408 | if (bios_name == NULL) { | |
409 | bios_name = PROM_FILENAME; | |
410 | } | |
411 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
412 | if (filename) { | |
409dbce5 | 413 | ret = load_elf(filename, translate_prom_address, &addr, |
7ef295ea | 414 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
415 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
416 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
417 | } | |
7267c094 | 418 | g_free(filename); |
1baffa46 BS |
419 | } else { |
420 | ret = -1; | |
421 | } | |
422 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 423 | error_report("could not load prom '%s'", bios_name); |
1baffa46 BS |
424 | exit(1); |
425 | } | |
426 | } | |
427 | ||
92b19880 | 428 | static void prom_realize(DeviceState *ds, Error **errp) |
1baffa46 | 429 | { |
92b19880 TH |
430 | PROMState *s = OPENPROM(ds); |
431 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
432 | Error *local_err = NULL; | |
433 | ||
434 | memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", | |
435 | PROM_SIZE_MAX, &local_err); | |
436 | if (local_err) { | |
437 | error_propagate(errp, local_err); | |
438 | return; | |
439 | } | |
1baffa46 | 440 | |
c5705a77 | 441 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 442 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 443 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
444 | } |
445 | ||
999e12bb AL |
446 | static Property prom_properties[] = { |
447 | {/* end of property list */}, | |
448 | }; | |
449 | ||
450 | static void prom_class_init(ObjectClass *klass, void *data) | |
451 | { | |
39bffca2 | 452 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 453 | |
39bffca2 | 454 | dc->props = prom_properties; |
92b19880 | 455 | dc->realize = prom_realize; |
999e12bb AL |
456 | } |
457 | ||
8c43a6f0 | 458 | static const TypeInfo prom_info = { |
13575cf6 | 459 | .name = TYPE_OPENPROM, |
39bffca2 AL |
460 | .parent = TYPE_SYS_BUS_DEVICE, |
461 | .instance_size = sizeof(PROMState), | |
462 | .class_init = prom_class_init, | |
1baffa46 BS |
463 | }; |
464 | ||
bda42033 | 465 | |
88c034d5 AF |
466 | #define TYPE_SUN4U_MEMORY "memory" |
467 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
468 | ||
469 | typedef struct RamDevice { | |
470 | SysBusDevice parent_obj; | |
471 | ||
d4edce38 | 472 | MemoryRegion ram; |
04843626 | 473 | uint64_t size; |
bda42033 BS |
474 | } RamDevice; |
475 | ||
476 | /* System RAM */ | |
78fb261d | 477 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 478 | { |
88c034d5 | 479 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 480 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 481 | |
1cfe48c1 | 482 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 483 | &error_fatal); |
c5705a77 | 484 | vmstate_register_ram_global(&d->ram); |
78fb261d | 485 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
486 | } |
487 | ||
a8170e5e | 488 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
489 | { |
490 | DeviceState *dev; | |
491 | SysBusDevice *s; | |
492 | RamDevice *d; | |
493 | ||
494 | /* allocate RAM */ | |
88c034d5 | 495 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 496 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 497 | |
88c034d5 | 498 | d = SUN4U_RAM(dev); |
bda42033 | 499 | d->size = RAM_size; |
e23a1b33 | 500 | qdev_init_nofail(dev); |
bda42033 BS |
501 | |
502 | sysbus_mmio_map(s, 0, addr); | |
503 | } | |
504 | ||
999e12bb AL |
505 | static Property ram_properties[] = { |
506 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
507 | DEFINE_PROP_END_OF_LIST(), | |
508 | }; | |
509 | ||
510 | static void ram_class_init(ObjectClass *klass, void *data) | |
511 | { | |
39bffca2 | 512 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 513 | |
78fb261d | 514 | dc->realize = ram_realize; |
39bffca2 | 515 | dc->props = ram_properties; |
999e12bb AL |
516 | } |
517 | ||
8c43a6f0 | 518 | static const TypeInfo ram_info = { |
88c034d5 | 519 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
520 | .parent = TYPE_SYS_BUS_DEVICE, |
521 | .instance_size = sizeof(RamDevice), | |
522 | .class_init = ram_class_init, | |
bda42033 BS |
523 | }; |
524 | ||
38bc50f7 | 525 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 526 | MachineState *machine, |
7b833f5b BS |
527 | const struct hwdef *hwdef) |
528 | { | |
f9d1465f | 529 | SPARCCPU *cpu; |
31688246 | 530 | Nvram *nvram; |
7b833f5b | 531 | unsigned int i; |
5f2bf0fe | 532 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
5795162a | 533 | SabreState *sabre; |
311f2b7a | 534 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 535 | PCIDevice *ebus, *pci_dev; |
f3b18f35 | 536 | SysBusDevice *s; |
f455e98c | 537 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
aea5b071 | 538 | DeviceState *iommu, *dev; |
a88b362c | 539 | FWCfgState *fw_cfg; |
8d932971 | 540 | NICInfo *nd; |
6864fa38 MCA |
541 | MACAddr macaddr; |
542 | bool onboard_nic; | |
7b833f5b | 543 | |
7b833f5b | 544 | /* init CPUs */ |
58530461 | 545 | cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); |
7b833f5b | 546 | |
aea5b071 MCA |
547 | /* IOMMU */ |
548 | iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); | |
549 | qdev_init_nofail(iommu); | |
550 | ||
bda42033 | 551 | /* set up devices */ |
3ef96221 | 552 | ram_init(0, machine->ram_size); |
3475187d | 553 | |
1baffa46 | 554 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 555 | |
b14dcaf4 | 556 | /* Init sabre (PCI host bridge) */ |
5795162a MCA |
557 | sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); |
558 | qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); | |
559 | qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); | |
560 | object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", | |
561 | &error_abort); | |
562 | qdev_init_nofail(DEVICE(sabre)); | |
2a4d6af5 MCA |
563 | |
564 | /* Wire up PCI interrupts to CPU */ | |
565 | for (i = 0; i < IVEC_MAX; i++) { | |
5795162a | 566 | qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, |
2a4d6af5 MCA |
567 | qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); |
568 | } | |
569 | ||
5795162a MCA |
570 | pci_bus = PCI_HOST_BRIDGE(sabre)->bus; |
571 | pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); | |
572 | pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); | |
83469015 | 573 | |
5795162a | 574 | /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is |
6864fa38 MCA |
575 | reserved (leaving no slots free after on-board devices) however slots |
576 | 0-3 are free on busB */ | |
577 | pci_bus->slot_reserved_mask = 0xfffffffc; | |
578 | pci_busA->slot_reserved_mask = 0xfffffff1; | |
579 | pci_busB->slot_reserved_mask = 0xfffffff0; | |
580 | ||
ad6856e8 | 581 | ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); |
0fe22ffb MCA |
582 | qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", |
583 | hwdef->console_serial_base); | |
6864fa38 MCA |
584 | qdev_init_nofail(DEVICE(ebus)); |
585 | ||
5795162a | 586 | /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ |
4b10c8d7 | 587 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, |
5795162a | 588 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); |
4b10c8d7 | 589 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, |
5795162a | 590 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); |
4b10c8d7 | 591 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, |
5795162a | 592 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); |
4b10c8d7 | 593 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, |
5795162a | 594 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); |
4b10c8d7 | 595 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, |
5795162a | 596 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); |
4b10c8d7 | 597 | |
6864fa38 MCA |
598 | pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); |
599 | ||
600 | memset(&macaddr, 0, sizeof(MACAddr)); | |
601 | onboard_nic = false; | |
8d932971 MCA |
602 | for (i = 0; i < nb_nics; i++) { |
603 | nd = &nd_table[i]; | |
604 | ||
6864fa38 MCA |
605 | if (!nd->model || strcmp(nd->model, "sunhme") == 0) { |
606 | if (!onboard_nic) { | |
607 | pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), | |
608 | true, "sunhme"); | |
609 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); | |
610 | onboard_nic = true; | |
611 | } else { | |
bcf9e2c2 | 612 | pci_dev = pci_create(pci_busB, -1, "sunhme"); |
6864fa38 | 613 | } |
8d932971 | 614 | } else { |
bcf9e2c2 | 615 | pci_dev = pci_create(pci_busB, -1, nd->model); |
8d932971 | 616 | } |
6864fa38 MCA |
617 | |
618 | dev = &pci_dev->qdev; | |
619 | qdev_set_nic_properties(dev, nd); | |
620 | qdev_init_nofail(dev); | |
621 | } | |
622 | ||
623 | /* If we don't have an onboard NIC, grab a default MAC address so that | |
624 | * we have a valid machine id */ | |
625 | if (!onboard_nic) { | |
626 | qemu_macaddr_default_if_unset(&macaddr); | |
8d932971 | 627 | } |
83469015 | 628 | |
d8f94e1b | 629 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
e4bcb14c | 630 | |
6864fa38 MCA |
631 | pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); |
632 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); | |
633 | qdev_init_nofail(&pci_dev->qdev); | |
634 | pci_ide_create_devs(pci_dev, hd); | |
3b898dda | 635 | |
f3b18f35 MCA |
636 | /* Map NVRAM into I/O (ebus) space */ |
637 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
638 | s = SYS_BUS_DEVICE(nvram); | |
07c84741 | 639 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 MCA |
640 | sysbus_mmio_get_region(s, 0)); |
641 | ||
636aa70a | 642 | initrd_size = 0; |
5f2bf0fe | 643 | initrd_addr = 0; |
3ef96221 MA |
644 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
645 | machine->initrd_filename, | |
5f2bf0fe BS |
646 | ram_size, &initrd_size, &initrd_addr, |
647 | &kernel_addr, &kernel_entry); | |
636aa70a | 648 | |
3ef96221 MA |
649 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
650 | machine->boot_order, | |
5f2bf0fe | 651 | kernel_addr, kernel_size, |
3ef96221 | 652 | machine->kernel_cmdline, |
5f2bf0fe | 653 | initrd_addr, initrd_size, |
0d31cb99 BS |
654 | /* XXX: need an option to load a NVRAM image */ |
655 | 0, | |
656 | graphic_width, graphic_height, graphic_depth, | |
6864fa38 | 657 | (uint8_t *)&macaddr); |
83469015 | 658 | |
d6acc8a5 MCA |
659 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
660 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
07c84741 | 661 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); |
d6acc8a5 | 662 | qdev_init_nofail(dev); |
07c84741 | 663 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
664 | &FW_CFG_IO(dev)->comb_iomem); |
665 | ||
666 | fw_cfg = FW_CFG(dev); | |
5836d168 | 667 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 668 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
669 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
670 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
671 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
672 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 673 | if (machine->kernel_cmdline) { |
9c9b0512 | 674 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
675 | strlen(machine->kernel_cmdline) + 1); |
676 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 677 | } else { |
9c9b0512 | 678 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 679 | } |
5f2bf0fe BS |
680 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
681 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 682 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
683 | |
684 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
685 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
686 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
687 | ||
513f789f | 688 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
689 | } |
690 | ||
905fdcb5 BS |
691 | enum { |
692 | sun4u_id = 0, | |
693 | sun4v_id = 64, | |
694 | }; | |
695 | ||
c7ba218d BS |
696 | static const struct hwdef hwdefs[] = { |
697 | /* Sun4u generic PC-like machine */ | |
698 | { | |
905fdcb5 | 699 | .machine_id = sun4u_id, |
e87231d4 BS |
700 | .prom_addr = 0x1fff0000000ULL, |
701 | .console_serial_base = 0, | |
c7ba218d BS |
702 | }, |
703 | /* Sun4v generic PC-like machine */ | |
704 | { | |
905fdcb5 | 705 | .machine_id = sun4v_id, |
e87231d4 BS |
706 | .prom_addr = 0x1fff0000000ULL, |
707 | .console_serial_base = 0, | |
708 | }, | |
c7ba218d BS |
709 | }; |
710 | ||
711 | /* Sun4u hardware initialisation */ | |
3ef96221 | 712 | static void sun4u_init(MachineState *machine) |
5f072e1f | 713 | { |
3ef96221 | 714 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
715 | } |
716 | ||
717 | /* Sun4v hardware initialisation */ | |
3ef96221 | 718 | static void sun4v_init(MachineState *machine) |
5f072e1f | 719 | { |
3ef96221 | 720 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
721 | } |
722 | ||
8a661aea | 723 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 724 | { |
8a661aea AF |
725 | MachineClass *mc = MACHINE_CLASS(oc); |
726 | ||
e264d29d EH |
727 | mc->desc = "Sun4u platform"; |
728 | mc->init = sun4u_init; | |
2059839b | 729 | mc->block_default_type = IF_IDE; |
e264d29d EH |
730 | mc->max_cpus = 1; /* XXX for now */ |
731 | mc->is_default = 1; | |
732 | mc->default_boot_order = "c"; | |
58530461 | 733 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); |
e264d29d | 734 | } |
c7ba218d | 735 | |
8a661aea AF |
736 | static const TypeInfo sun4u_type = { |
737 | .name = MACHINE_TYPE_NAME("sun4u"), | |
738 | .parent = TYPE_MACHINE, | |
739 | .class_init = sun4u_class_init, | |
740 | }; | |
e87231d4 | 741 | |
8a661aea | 742 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 743 | { |
8a661aea AF |
744 | MachineClass *mc = MACHINE_CLASS(oc); |
745 | ||
e264d29d EH |
746 | mc->desc = "Sun4v platform"; |
747 | mc->init = sun4v_init; | |
2059839b | 748 | mc->block_default_type = IF_IDE; |
e264d29d EH |
749 | mc->max_cpus = 1; /* XXX for now */ |
750 | mc->default_boot_order = "c"; | |
58530461 | 751 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); |
e264d29d EH |
752 | } |
753 | ||
8a661aea AF |
754 | static const TypeInfo sun4v_type = { |
755 | .name = MACHINE_TYPE_NAME("sun4v"), | |
756 | .parent = TYPE_MACHINE, | |
757 | .class_init = sun4v_class_init, | |
758 | }; | |
e264d29d | 759 | |
83f7d43a AF |
760 | static void sun4u_register_types(void) |
761 | { | |
25c5d5ac | 762 | type_register_static(&power_info); |
83f7d43a AF |
763 | type_register_static(&ebus_info); |
764 | type_register_static(&prom_info); | |
765 | type_register_static(&ram_info); | |
83f7d43a | 766 | |
8a661aea AF |
767 | type_register_static(&sun4u_type); |
768 | type_register_static(&sun4v_type); | |
8a661aea AF |
769 | } |
770 | ||
83f7d43a | 771 | type_init(sun4u_register_types) |