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target-i386: Filter out unsupported features at realize time
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
c6dc6f63 26
1de7afc9
PB		 27#include "qemu/option.h"
28#include "qemu/config-file.h"
7b1b5d19 29#include "qapi/qmp/qerror.h"
c6dc6f63 30
7b1b5d19 31#include "qapi/visitor.h"
9c17d615 32#include "sysemu/arch_init.h"
71ad61d3 33
28f52cc0
VR		 34#include "hyperv.h"
35
65dee380 36#include "hw/hw.h"
b834b508 37#if defined(CONFIG_KVM)
ef8621b1 38#include <linux/kvm_para.h>
b834b508 39#endif
65dee380 40
9c17d615 41#include "sysemu/sysemu.h"
bdeec802
IM		 42#ifndef CONFIG_USER_ONLY
43#include "hw/xen.h"
44#include "hw/sysbus.h"
449994eb 45#include "hw/apic_internal.h"
bdeec802
IM		 46#endif
47
c6dc6f63
AP		 48/* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61};
62static const char *ext_feature_name[] = {
f370be3c 63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 64 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 65 "tm2", "ssse3", "cid", NULL,
e117f772 66 "fma", "cx16", "xtpr", "pdcm",
434acb81 67 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 69 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 70 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 71};
3b671a40
EH		 72/* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
c6dc6f63 77static const char *ext2_feature_name[] = {
3b671a40
EH		 78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 85 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 86};
87static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 90 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 95 NULL, NULL, NULL, NULL,
96};
97
98static const char *kvm_feature_name[] = {
c3d39807
DS		 99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 107};
108
296acb64
JR		 109static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118};
119
a9321a4d 120static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125};
126
8b4beddc
EH		 127const char *get_register_name_32(unsigned int reg)
128{
129 static const char *reg_names[CPU_NB_REGS32] = {
130 [R_EAX] = "EAX",
131 [R_ECX] = "ECX",
132 [R_EDX] = "EDX",
133 [R_EBX] = "EBX",
134 [R_ESP] = "ESP",
135 [R_EBP] = "EBP",
136 [R_ESI] = "ESI",
137 [R_EDI] = "EDI",
138 };
139
140 if (reg > CPU_NB_REGS32) {
141 return NULL;
142 }
143 return reg_names[reg];
144}
145
c6dc6f63
AP		 146/* collects per-function cpuid data
147 */
148typedef struct model_features_t {
149 uint32_t *guest_feat;
150 uint32_t *host_feat;
c6dc6f63
AP		 151 const char **flag_names;
152 uint32_t cpuid;
8b4beddc
EH		 153 int reg;
154} model_features_t;
c6dc6f63
AP		 155
156int check_cpuid = 0;
157int enforce_cpuid = 0;
158
dc59944b
MT		 159#if defined(CONFIG_KVM)
160static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
161 (1 << KVM_FEATURE_NOP_IO_DELAY) |
162 (1 << KVM_FEATURE_MMU_OP) |
163 (1 << KVM_FEATURE_CLOCKSOURCE2) |
164 (1 << KVM_FEATURE_ASYNC_PF) |
165 (1 << KVM_FEATURE_STEAL_TIME) |
166 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
167static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
168#else
169static uint32_t kvm_default_features = 0;
170static const uint32_t kvm_pv_eoi_features = 0;
171#endif
172
173void enable_kvm_pv_eoi(void)
174{
175 kvm_default_features |= kvm_pv_eoi_features;
176}
177
bb44e0d1
JK		 178void host_cpuid(uint32_t function, uint32_t count,
179 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 180{
181#if defined(CONFIG_KVM)
a1fd24af
AL		 182 uint32_t vec[4];
183
184#ifdef __x86_64__
185 asm volatile("cpuid"
186 : "=a"(vec[0]), "=b"(vec[1]),
187 "=c"(vec[2]), "=d"(vec[3])
188 : "0"(function), "c"(count) : "cc");
189#else
190 asm volatile("pusha \n\t"
191 "cpuid \n\t"
192 "mov %%eax, 0(%2) \n\t"
193 "mov %%ebx, 4(%2) \n\t"
194 "mov %%ecx, 8(%2) \n\t"
195 "mov %%edx, 12(%2) \n\t"
196 "popa"
197 : : "a"(function), "c"(count), "S"(vec)
198 : "memory", "cc");
199#endif
200
bdde476a 201 if (eax)
a1fd24af 202 *eax = vec[0];
bdde476a 203 if (ebx)
a1fd24af 204 *ebx = vec[1];
bdde476a 205 if (ecx)
a1fd24af 206 *ecx = vec[2];
bdde476a 207 if (edx)
a1fd24af 208 *edx = vec[3];
bdde476a
AP		 209#endif
210}
c6dc6f63
AP		 211
212#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
213
214/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
215 * a substring. ex if !NULL points to the first char after a substring,
216 * otherwise the string is assumed to sized by a terminating nul.
217 * Return lexical ordering of *s1:*s2.
218 */
219static int sstrcmp(const char *s1, const char *e1, const char *s2,
220 const char *e2)
221{
222 for (;;) {
223 if (!*s1 || !*s2 || *s1 != *s2)
224 return (*s1 - *s2);
225 ++s1, ++s2;
226 if (s1 == e1 && s2 == e2)
227 return (0);
228 else if (s1 == e1)
229 return (*s2);
230 else if (s2 == e2)
231 return (*s1);
232 }
233}
234
235/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
236 * '|' delimited (possibly empty) strings in which case search for a match
237 * within the alternatives proceeds left to right. Return 0 for success,
238 * non-zero otherwise.
239 */
240static int altcmp(const char *s, const char *e, const char *altstr)
241{
242 const char *p, *q;
243
244 for (q = p = altstr; ; ) {
245 while (*p && *p != '|')
246 ++p;
247 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
248 return (0);
249 if (!*p)
250 return (1);
251 else
252 q = ++p;
253 }
254}
255
256/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 257 * *pval and return true, otherwise return false
c6dc6f63 258 */
e41e0fc6
JK		 259static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
260 const char **featureset)
c6dc6f63
AP		 261{
262 uint32_t mask;
263 const char **ppc;
e41e0fc6 264 bool found = false;
c6dc6f63 265
e41e0fc6 266 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 267 if (*ppc && !altcmp(s, e, *ppc)) {
268 *pval |= mask;
e41e0fc6 269 found = true;
c6dc6f63 270 }
e41e0fc6
JK		 271 }
272 return found;
c6dc6f63
AP		 273}
274
275static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
276 uint32_t *ext_features,
277 uint32_t *ext2_features,
278 uint32_t *ext3_features,
296acb64 279 uint32_t *kvm_features,
a9321a4d
PA		 280 uint32_t *svm_features,
281 uint32_t *cpuid_7_0_ebx_features)
c6dc6f63
AP		 282{
283 if (!lookup_feature(features, flagname, NULL, feature_name) &&
284 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
285 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
286 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64 287 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
a9321a4d
PA		 288 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
289 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
290 cpuid_7_0_ebx_feature_name))
c6dc6f63
AP		 291 fprintf(stderr, "CPU feature %s not found\n", flagname);
292}
293
294typedef struct x86_def_t {
295 struct x86_def_t *next;
296 const char *name;
297 uint32_t level;
298 uint32_t vendor1, vendor2, vendor3;
299 int family;
300 int model;
301 int stepping;
b862d1fe 302 int tsc_khz;
296acb64
JR		 303 uint32_t features, ext_features, ext2_features, ext3_features;
304 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 305 uint32_t xlevel;
306 char model_id[48];
307 int vendor_override;
b3baa152
BW		 308 /* Store the results of Centaur's CPUID instructions */
309 uint32_t ext4_features;
310 uint32_t xlevel2;
13526728
EH		 311 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
312 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 313} x86_def_t;
314
315#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
316#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
317 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
318#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
319 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
320 CPUID_PSE36 | CPUID_FXSR)
321#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
322#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
323 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
324 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
325 CPUID_PAE | CPUID_SEP | CPUID_APIC)
326
551a2dec
AP		 327#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
328 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
329 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
330 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
331 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 332 /* partly implemented:
333 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
334 CPUID_PSE36 (needed for Solaris) */
335 /* missing:
336 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 337#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 338 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 339 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 340 /* missing:
341 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 342 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 343#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 344 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
345 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 346 /* missing:
347 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 348#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
349 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 350#define TCG_SVM_FEATURES 0
a9321a4d 351#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 352
c6dc6f63
AP		 353/* maintains list of cpu model definitions
354 */
355static x86_def_t *x86_defs = {NULL};
356
357/* built-in cpu model definitions (deprecated)
358 */
359static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 360 {
361 .name = "qemu64",
362 .level = 4,
363 .vendor1 = CPUID_VENDOR_AMD_1,
364 .vendor2 = CPUID_VENDOR_AMD_2,
365 .vendor3 = CPUID_VENDOR_AMD_3,
366 .family = 6,
367 .model = 2,
368 .stepping = 3,
369 .features = PPRO_FEATURES |
c6dc6f63 370 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 371 CPUID_PSE36,
372 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
375 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
376 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
377 .xlevel = 0x8000000A,
c6dc6f63
AP		 378 },
379 {
380 .name = "phenom",
381 .level = 5,
382 .vendor1 = CPUID_VENDOR_AMD_1,
383 .vendor2 = CPUID_VENDOR_AMD_2,
384 .vendor3 = CPUID_VENDOR_AMD_3,
385 .family = 16,
386 .model = 2,
387 .stepping = 3,
c6dc6f63
AP		 388 .features = PPRO_FEATURES |
389 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 390 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 391 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
392 CPUID_EXT_POPCNT,
60032ac0 393 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 394 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
395 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 396 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 397 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
398 CPUID_EXT3_CR8LEG,
399 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
400 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
401 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
402 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 403 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 404 .xlevel = 0x8000001A,
405 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
406 },
407 {
408 .name = "core2duo",
409 .level = 10,
410 .family = 6,
411 .model = 15,
412 .stepping = 11,
c6dc6f63
AP		 413 .features = PPRO_FEATURES |
414 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 415 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
416 CPUID_HT | CPUID_TM | CPUID_PBE,
417 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
418 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
419 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 420 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
421 .ext3_features = CPUID_EXT3_LAHF_LM,
422 .xlevel = 0x80000008,
423 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
424 },
425 {
426 .name = "kvm64",
427 .level = 5,
428 .vendor1 = CPUID_VENDOR_INTEL_1,
429 .vendor2 = CPUID_VENDOR_INTEL_2,
430 .vendor3 = CPUID_VENDOR_INTEL_3,
431 .family = 15,
432 .model = 6,
433 .stepping = 1,
434 /* Missing: CPUID_VME, CPUID_HT */
435 .features = PPRO_FEATURES |
436 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
437 CPUID_PSE36,
438 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
439 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
440 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 441 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 442 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
443 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
444 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
445 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
446 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
447 .ext3_features = 0,
448 .xlevel = 0x80000008,
449 .model_id = "Common KVM processor"
450 },
c6dc6f63
AP		 451 {
452 .name = "qemu32",
453 .level = 4,
454 .family = 6,
455 .model = 3,
456 .stepping = 3,
457 .features = PPRO_FEATURES,
458 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 459 .xlevel = 0x80000004,
c6dc6f63 460 },
eafaf1e5
AP		 461 {
462 .name = "kvm32",
463 .level = 5,
464 .family = 15,
465 .model = 6,
466 .stepping = 1,
467 .features = PPRO_FEATURES |
468 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
469 .ext_features = CPUID_EXT_SSE3,
60032ac0 470 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 471 .ext3_features = 0,
472 .xlevel = 0x80000008,
473 .model_id = "Common 32-bit KVM processor"
474 },
c6dc6f63
AP		 475 {
476 .name = "coreduo",
477 .level = 10,
478 .family = 6,
479 .model = 14,
480 .stepping = 8,
c6dc6f63 481 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 482 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
483 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
484 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
485 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 486 .ext2_features = CPUID_EXT2_NX,
487 .xlevel = 0x80000008,
488 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
489 },
490 {
491 .name = "486",
58012d66 492 .level = 1,
c6dc6f63
AP		 493 .family = 4,
494 .model = 0,
495 .stepping = 0,
496 .features = I486_FEATURES,
497 .xlevel = 0,
498 },
499 {
500 .name = "pentium",
501 .level = 1,
502 .family = 5,
503 .model = 4,
504 .stepping = 3,
505 .features = PENTIUM_FEATURES,
506 .xlevel = 0,
507 },
508 {
509 .name = "pentium2",
510 .level = 2,
511 .family = 6,
512 .model = 5,
513 .stepping = 2,
514 .features = PENTIUM2_FEATURES,
515 .xlevel = 0,
516 },
517 {
518 .name = "pentium3",
519 .level = 2,
520 .family = 6,
521 .model = 7,
522 .stepping = 3,
523 .features = PENTIUM3_FEATURES,
524 .xlevel = 0,
525 },
526 {
527 .name = "athlon",
528 .level = 2,
529 .vendor1 = CPUID_VENDOR_AMD_1,
530 .vendor2 = CPUID_VENDOR_AMD_2,
531 .vendor3 = CPUID_VENDOR_AMD_3,
532 .family = 6,
533 .model = 2,
534 .stepping = 3,
60032ac0
EH		 535 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
536 CPUID_MCA,
537 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
538 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 539 .xlevel = 0x80000008,
c6dc6f63
AP		 540 },
541 {
542 .name = "n270",
543 /* original is on level 10 */
544 .level = 5,
545 .family = 6,
546 .model = 28,
547 .stepping = 2,
548 .features = PPRO_FEATURES |
8560efed
AJ		 549 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
550 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 551 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 552 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
553 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 554 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
555 CPUID_EXT2_NX,
8560efed 556 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 557 .xlevel = 0x8000000A,
558 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
559 },
3eca4642
EH		 560 {
561 .name = "Conroe",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
575 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
576 .ext3_features = CPUID_EXT3_LAHF_LM,
577 .xlevel = 0x8000000A,
578 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
579 },
580 {
581 .name = "Penryn",
582 .level = 2,
583 .vendor1 = CPUID_VENDOR_INTEL_1,
584 .vendor2 = CPUID_VENDOR_INTEL_2,
585 .vendor3 = CPUID_VENDOR_INTEL_3,
586 .family = 6,
587 .model = 2,
588 .stepping = 3,
589 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
590 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
591 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
592 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
593 CPUID_DE | CPUID_FP87,
594 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
595 CPUID_EXT_SSE3,
596 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
597 .ext3_features = CPUID_EXT3_LAHF_LM,
598 .xlevel = 0x8000000A,
599 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
600 },
601 {
602 .name = "Nehalem",
603 .level = 2,
604 .vendor1 = CPUID_VENDOR_INTEL_1,
605 .vendor2 = CPUID_VENDOR_INTEL_2,
606 .vendor3 = CPUID_VENDOR_INTEL_3,
607 .family = 6,
608 .model = 2,
609 .stepping = 3,
610 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
611 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
612 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
613 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
614 CPUID_DE | CPUID_FP87,
615 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
616 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
617 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
618 .ext3_features = CPUID_EXT3_LAHF_LM,
619 .xlevel = 0x8000000A,
620 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
621 },
622 {
623 .name = "Westmere",
624 .level = 11,
625 .vendor1 = CPUID_VENDOR_INTEL_1,
626 .vendor2 = CPUID_VENDOR_INTEL_2,
627 .vendor3 = CPUID_VENDOR_INTEL_3,
628 .family = 6,
629 .model = 44,
630 .stepping = 1,
631 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
632 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
633 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
634 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
635 CPUID_DE | CPUID_FP87,
636 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
637 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
638 CPUID_EXT_SSE3,
639 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
640 .ext3_features = CPUID_EXT3_LAHF_LM,
641 .xlevel = 0x8000000A,
642 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
643 },
644 {
645 .name = "SandyBridge",
646 .level = 0xd,
647 .vendor1 = CPUID_VENDOR_INTEL_1,
648 .vendor2 = CPUID_VENDOR_INTEL_2,
649 .vendor3 = CPUID_VENDOR_INTEL_3,
650 .family = 6,
651 .model = 42,
652 .stepping = 1,
653 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
654 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
655 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
656 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
657 CPUID_DE | CPUID_FP87,
658 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
659 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
660 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
661 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
662 CPUID_EXT_SSE3,
663 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
664 CPUID_EXT2_SYSCALL,
665 .ext3_features = CPUID_EXT3_LAHF_LM,
666 .xlevel = 0x8000000A,
667 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
668 },
37507094
EH		 669 {
670 .name = "Haswell",
671 .level = 0xd,
672 .vendor1 = CPUID_VENDOR_INTEL_1,
673 .vendor2 = CPUID_VENDOR_INTEL_2,
674 .vendor3 = CPUID_VENDOR_INTEL_3,
675 .family = 6,
676 .model = 60,
677 .stepping = 1,
678 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
679 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 680 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 681 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
682 CPUID_DE | CPUID_FP87,
683 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
684 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
685 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
686 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
687 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
688 CPUID_EXT_PCID,
80ae4160
EH		 689 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
690 CPUID_EXT2_SYSCALL,
37507094
EH		 691 .ext3_features = CPUID_EXT3_LAHF_LM,
692 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
693 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
694 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
695 CPUID_7_0_EBX_RTM,
696 .xlevel = 0x8000000A,
697 .model_id = "Intel Core Processor (Haswell)",
698 },
3eca4642
EH		 699 {
700 .name = "Opteron_G1",
701 .level = 5,
702 .vendor1 = CPUID_VENDOR_AMD_1,
703 .vendor2 = CPUID_VENDOR_AMD_2,
704 .vendor3 = CPUID_VENDOR_AMD_3,
705 .family = 15,
706 .model = 6,
707 .stepping = 1,
708 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
709 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
710 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
711 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
712 CPUID_DE | CPUID_FP87,
713 .ext_features = CPUID_EXT_SSE3,
714 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
715 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
716 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
717 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
718 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
719 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
720 .xlevel = 0x80000008,
721 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
722 },
723 {
724 .name = "Opteron_G2",
725 .level = 5,
726 .vendor1 = CPUID_VENDOR_AMD_1,
727 .vendor2 = CPUID_VENDOR_AMD_2,
728 .vendor3 = CPUID_VENDOR_AMD_3,
729 .family = 15,
730 .model = 6,
731 .stepping = 1,
732 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
733 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
734 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
735 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
736 CPUID_DE | CPUID_FP87,
737 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
738 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
739 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
740 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
741 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
742 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
743 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
744 CPUID_EXT2_DE | CPUID_EXT2_FPU,
745 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
746 .xlevel = 0x80000008,
747 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
748 },
749 {
750 .name = "Opteron_G3",
751 .level = 5,
752 .vendor1 = CPUID_VENDOR_AMD_1,
753 .vendor2 = CPUID_VENDOR_AMD_2,
754 .vendor3 = CPUID_VENDOR_AMD_3,
755 .family = 15,
756 .model = 6,
757 .stepping = 1,
758 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
759 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
760 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
761 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
762 CPUID_DE | CPUID_FP87,
763 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
764 CPUID_EXT_SSE3,
765 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
766 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
767 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
768 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
769 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
770 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
771 CPUID_EXT2_DE | CPUID_EXT2_FPU,
772 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
773 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
774 .xlevel = 0x80000008,
775 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
776 },
777 {
778 .name = "Opteron_G4",
779 .level = 0xd,
780 .vendor1 = CPUID_VENDOR_AMD_1,
781 .vendor2 = CPUID_VENDOR_AMD_2,
782 .vendor3 = CPUID_VENDOR_AMD_3,
783 .family = 21,
784 .model = 1,
785 .stepping = 2,
786 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
787 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
788 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
789 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
790 CPUID_DE | CPUID_FP87,
791 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
792 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
793 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
794 CPUID_EXT_SSE3,
795 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
796 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
797 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
798 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
799 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
800 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
801 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
802 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
803 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
804 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
805 CPUID_EXT3_LAHF_LM,
806 .xlevel = 0x8000001A,
807 .model_id = "AMD Opteron 62xx class CPU",
808 },
021941b9
AP		 809 {
810 .name = "Opteron_G5",
811 .level = 0xd,
812 .vendor1 = CPUID_VENDOR_AMD_1,
813 .vendor2 = CPUID_VENDOR_AMD_2,
814 .vendor3 = CPUID_VENDOR_AMD_3,
815 .family = 21,
816 .model = 2,
817 .stepping = 0,
818 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
819 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
820 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
821 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
822 CPUID_DE | CPUID_FP87,
823 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
824 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
825 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
826 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
827 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
828 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
829 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
830 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
831 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
832 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
833 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
834 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
835 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
836 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
837 CPUID_EXT3_LAHF_LM,
838 .xlevel = 0x8000001A,
839 .model_id = "AMD Opteron 63xx class CPU",
840 },
c6dc6f63
AP		 841};
842
e4ab0d6b 843#ifdef CONFIG_KVM
c6dc6f63
AP		 844static int cpu_x86_fill_model_id(char *str)
845{
846 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
847 int i;
848
849 for (i = 0; i < 3; i++) {
850 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
851 memcpy(str + i * 16 + 0, &eax, 4);
852 memcpy(str + i * 16 + 4, &ebx, 4);
853 memcpy(str + i * 16 + 8, &ecx, 4);
854 memcpy(str + i * 16 + 12, &edx, 4);
855 }
856 return 0;
857}
e4ab0d6b 858#endif
c6dc6f63 859
6e746f30
EH		 860/* Fill a x86_def_t struct with information about the host CPU, and
861 * the CPU features supported by the host hardware + host kernel
862 *
863 * This function may be called only if KVM is enabled.
864 */
865static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 866{
e4ab0d6b 867#ifdef CONFIG_KVM
12869995 868 KVMState *s = kvm_state;
c6dc6f63
AP		 869 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
870
6e746f30
EH		 871 assert(kvm_enabled());
872
c6dc6f63
AP		 873 x86_cpu_def->name = "host";
874 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 875 x86_cpu_def->vendor1 = ebx;
876 x86_cpu_def->vendor2 = edx;
877 x86_cpu_def->vendor3 = ecx;
878
879 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
880 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
881 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
882 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 883
12869995
EH		 884 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
885 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
886 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 887
6e746f30 888 if (x86_cpu_def->level >= 7) {
12869995
EH		 889 x86_cpu_def->cpuid_7_0_ebx_features =
890 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 891 } else {
892 x86_cpu_def->cpuid_7_0_ebx_features = 0;
893 }
894
12869995
EH		 895 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
896 x86_cpu_def->ext2_features =
897 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
898 x86_cpu_def->ext3_features =
899 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 900
c6dc6f63
AP		 901 cpu_x86_fill_model_id(x86_cpu_def->model_id);
902 x86_cpu_def->vendor_override = 0;
903
b3baa152
BW		 904 /* Call Centaur's CPUID instruction. */
905 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
906 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
907 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
908 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 909 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152
BW		 910 if (eax >= 0xC0000001) {
911 /* Support VIA max extended level */
912 x86_cpu_def->xlevel2 = eax;
913 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 914 x86_cpu_def->ext4_features =
915 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152
BW		 916 }
917 }
296acb64 918
fcb93c03
EH		 919 /* Other KVM-specific feature fields: */
920 x86_cpu_def->svm_features =
921 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 922 x86_cpu_def->kvm_features =
923 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 924
e4ab0d6b 925#endif /* CONFIG_KVM */
c6dc6f63
AP		 926}
927
928static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
929{
930 int i;
931
932 for (i = 0; i < 32; ++i)
933 if (1 << i & mask) {
8b4beddc
EH		 934 const char *reg = get_register_name_32(f->reg);
935 assert(reg);
936 fprintf(stderr, "warning: host doesn't support requested feature: "
937 "CPUID.%02XH:%s%s%s [bit %d]\n",
938 f->cpuid, reg,
939 f->flag_names[i] ? "." : "",
940 f->flag_names[i] ? f->flag_names[i] : "", i);
c6dc6f63
AP		 941 break;
942 }
943 return 0;
944}
945
946/* best effort attempt to inform user requested cpu flags aren't making
e8beac00 947 * their way to the guest.
6e746f30
EH		 948 *
949 * This function may be called only if KVM is enabled.
c6dc6f63 950 */
6e746f30 951static int kvm_check_features_against_host(x86_def_t *guest_def)
c6dc6f63
AP		 952{
953 x86_def_t host_def;
954 uint32_t mask;
955 int rv, i;
956 struct model_features_t ft[] = {
957 {&guest_def->features, &host_def.features,
e8beac00 958 feature_name, 0x00000001, R_EDX},
c6dc6f63 959 {&guest_def->ext_features, &host_def.ext_features,
e8beac00 960 ext_feature_name, 0x00000001, R_ECX},
c6dc6f63 961 {&guest_def->ext2_features, &host_def.ext2_features,
e8beac00 962 ext2_feature_name, 0x80000001, R_EDX},
c6dc6f63 963 {&guest_def->ext3_features, &host_def.ext3_features,
e8beac00 964 ext3_feature_name, 0x80000001, R_ECX}
8b4beddc 965 };
c6dc6f63 966
6e746f30
EH		 967 assert(kvm_enabled());
968
969 kvm_cpu_fill_host(&host_def);
66fe09ee 970 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63 971 for (mask = 1; mask; mask <<= 1)
e8beac00 972 if (*ft[i].guest_feat & mask &&
c6dc6f63
AP		 973 !(*ft[i].host_feat & mask)) {
974 unavailable_host_feature(&ft[i], mask);
975 rv = 1;
976 }
977 return rv;
978}
979
95b8519d
AF		 980static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
981 const char *name, Error **errp)
982{
983 X86CPU *cpu = X86_CPU(obj);
984 CPUX86State *env = &cpu->env;
985 int64_t value;
986
987 value = (env->cpuid_version >> 8) & 0xf;
988 if (value == 0xf) {
989 value += (env->cpuid_version >> 20) & 0xff;
990 }
991 visit_type_int(v, &value, name, errp);
992}
993
71ad61d3
AF		 994static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
995 const char *name, Error **errp)
ed5e1ec3 996{
71ad61d3
AF		 997 X86CPU *cpu = X86_CPU(obj);
998 CPUX86State *env = &cpu->env;
999 const int64_t min = 0;
1000 const int64_t max = 0xff + 0xf;
1001 int64_t value;
1002
1003 visit_type_int(v, &value, name, errp);
1004 if (error_is_set(errp)) {
1005 return;
1006 }
1007 if (value < min || value > max) {
1008 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1009 name ? name : "null", value, min, max);
1010 return;
1011 }
1012
ed5e1ec3 1013 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1014 if (value > 0x0f) {
1015 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1016 } else {
71ad61d3 1017 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1018 }
1019}
1020
67e30c83
AF		 1021static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1022 const char *name, Error **errp)
1023{
1024 X86CPU *cpu = X86_CPU(obj);
1025 CPUX86State *env = &cpu->env;
1026 int64_t value;
1027
1028 value = (env->cpuid_version >> 4) & 0xf;
1029 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1030 visit_type_int(v, &value, name, errp);
1031}
1032
c5291a4f
AF		 1033static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1034 const char *name, Error **errp)
b0704cbd 1035{
c5291a4f
AF		 1036 X86CPU *cpu = X86_CPU(obj);
1037 CPUX86State *env = &cpu->env;
1038 const int64_t min = 0;
1039 const int64_t max = 0xff;
1040 int64_t value;
1041
1042 visit_type_int(v, &value, name, errp);
1043 if (error_is_set(errp)) {
1044 return;
1045 }
1046 if (value < min || value > max) {
1047 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1048 name ? name : "null", value, min, max);
1049 return;
1050 }
1051
b0704cbd 1052 env->cpuid_version &= ~0xf00f0;
c5291a4f 1053 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1054}
1055
35112e41
AF		 1056static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1057 void *opaque, const char *name,
1058 Error **errp)
1059{
1060 X86CPU *cpu = X86_CPU(obj);
1061 CPUX86State *env = &cpu->env;
1062 int64_t value;
1063
1064 value = env->cpuid_version & 0xf;
1065 visit_type_int(v, &value, name, errp);
1066}
1067
036e2222
AF		 1068static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1069 void *opaque, const char *name,
1070 Error **errp)
38c3dc46 1071{
036e2222
AF		 1072 X86CPU *cpu = X86_CPU(obj);
1073 CPUX86State *env = &cpu->env;
1074 const int64_t min = 0;
1075 const int64_t max = 0xf;
1076 int64_t value;
1077
1078 visit_type_int(v, &value, name, errp);
1079 if (error_is_set(errp)) {
1080 return;
1081 }
1082 if (value < min || value > max) {
1083 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1084 name ? name : "null", value, min, max);
1085 return;
1086 }
1087
38c3dc46 1088 env->cpuid_version &= ~0xf;
036e2222 1089 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1090}
1091
8e1898bf
AF		 1092static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1093 const char *name, Error **errp)
1094{
1095 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1096
fa029887 1097 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1098}
1099
1100static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1101 const char *name, Error **errp)
1102{
1103 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1104
fa029887 1105 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1106}
1107
16b93aa8
AF		 1108static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1109 const char *name, Error **errp)
1110{
1111 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1112
fa029887 1113 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1114}
1115
1116static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1117 const char *name, Error **errp)
1118{
1119 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1120
fa029887 1121 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1122}
1123
d480e1af
AF		 1124static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1125{
1126 X86CPU *cpu = X86_CPU(obj);
1127 CPUX86State *env = &cpu->env;
1128 char *value;
1129 int i;
1130
9df694ee 1131 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1132 for (i = 0; i < 4; i++) {
1133 value[i ] = env->cpuid_vendor1 >> (8 * i);
1134 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1135 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1136 }
9df694ee 1137 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1138 return value;
1139}
1140
1141static void x86_cpuid_set_vendor(Object *obj, const char *value,
1142 Error **errp)
1143{
1144 X86CPU *cpu = X86_CPU(obj);
1145 CPUX86State *env = &cpu->env;
1146 int i;
1147
9df694ee 1148 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1149 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1150 "vendor", value);
1151 return;
1152 }
1153
1154 env->cpuid_vendor1 = 0;
1155 env->cpuid_vendor2 = 0;
1156 env->cpuid_vendor3 = 0;
1157 for (i = 0; i < 4; i++) {
1158 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1159 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1160 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1161 }
1162 env->cpuid_vendor_override = 1;
1163}
1164
63e886eb
AF		 1165static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1166{
1167 X86CPU *cpu = X86_CPU(obj);
1168 CPUX86State *env = &cpu->env;
1169 char *value;
1170 int i;
1171
1172 value = g_malloc(48 + 1);
1173 for (i = 0; i < 48; i++) {
1174 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1175 }
1176 value[48] = '\0';
1177 return value;
1178}
1179
938d4c25
AF		 1180static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1181 Error **errp)
dcce6675 1182{
938d4c25
AF		 1183 X86CPU *cpu = X86_CPU(obj);
1184 CPUX86State *env = &cpu->env;
dcce6675
AF		 1185 int c, len, i;
1186
1187 if (model_id == NULL) {
1188 model_id = "";
1189 }
1190 len = strlen(model_id);
d0a6acf4 1191 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1192 for (i = 0; i < 48; i++) {
1193 if (i >= len) {
1194 c = '\0';
1195 } else {
1196 c = (uint8_t)model_id[i];
1197 }
1198 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1199 }
1200}
1201
89e48965
AF		 1202static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1203 const char *name, Error **errp)
1204{
1205 X86CPU *cpu = X86_CPU(obj);
1206 int64_t value;
1207
1208 value = cpu->env.tsc_khz * 1000;
1209 visit_type_int(v, &value, name, errp);
1210}
1211
1212static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1213 const char *name, Error **errp)
1214{
1215 X86CPU *cpu = X86_CPU(obj);
1216 const int64_t min = 0;
2e84849a 1217 const int64_t max = INT64_MAX;
89e48965
AF		 1218 int64_t value;
1219
1220 visit_type_int(v, &value, name, errp);
1221 if (error_is_set(errp)) {
1222 return;
1223 }
1224 if (value < min || value > max) {
1225 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1226 name ? name : "null", value, min, max);
1227 return;
1228 }
1229
1230 cpu->env.tsc_khz = value / 1000;
1231}
1232
8f961357 1233static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1234{
c6dc6f63
AP		 1235 x86_def_t *def;
1236
9f3fb565
EH		 1237 for (def = x86_defs; def; def = def->next) {
1238 if (name && !strcmp(name, def->name)) {
c6dc6f63 1239 break;
9f3fb565
EH		 1240 }
1241 }
04c5b17a 1242 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
6e746f30 1243 kvm_cpu_fill_host(x86_cpu_def);
c6dc6f63 1244 } else if (!def) {
8f961357 1245 return -1;
c6dc6f63
AP		 1246 } else {
1247 memcpy(x86_cpu_def, def, sizeof(*def));
1248 }
1249
8f961357
EH		 1250 return 0;
1251}
1252
1253/* Parse "+feature,-feature,feature=foo" CPU feature string
1254 */
1255static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1256{
1257 unsigned int i;
1258 char *featurestr; /* Single 'key=value" string being parsed */
1259 /* Features to be added */
1260 uint32_t plus_features = 0, plus_ext_features = 0;
1261 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1262 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1263 uint32_t plus_7_0_ebx_features = 0;
1264 /* Features to be removed */
1265 uint32_t minus_features = 0, minus_ext_features = 0;
1266 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1267 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1268 uint32_t minus_7_0_ebx_features = 0;
1269 uint32_t numvalue;
1270
c6dc6f63 1271 add_flagname_to_bitmaps("hypervisor", &plus_features,
a9321a4d
PA		 1272 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1273 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
c6dc6f63 1274
8f961357 1275 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1276
1277 while (featurestr) {
1278 char *val;
1279 if (featurestr[0] == '+') {
296acb64
JR		 1280 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1281 &plus_ext_features, &plus_ext2_features,
1282 &plus_ext3_features, &plus_kvm_features,
a9321a4d 1283 &plus_svm_features, &plus_7_0_ebx_features);
c6dc6f63 1284 } else if (featurestr[0] == '-') {
296acb64
JR		 1285 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1286 &minus_ext_features, &minus_ext2_features,
1287 &minus_ext3_features, &minus_kvm_features,
a9321a4d 1288 &minus_svm_features, &minus_7_0_ebx_features);
c6dc6f63
AP		 1289 } else if ((val = strchr(featurestr, '='))) {
1290 *val = 0; val++;
1291 if (!strcmp(featurestr, "family")) {
1292 char *err;
1293 numvalue = strtoul(val, &err, 0);
a88a677f 1294 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1295 fprintf(stderr, "bad numerical value %s\n", val);
1296 goto error;
1297 }
1298 x86_cpu_def->family = numvalue;
1299 } else if (!strcmp(featurestr, "model")) {
1300 char *err;
1301 numvalue = strtoul(val, &err, 0);
1302 if (!*val || *err || numvalue > 0xff) {
1303 fprintf(stderr, "bad numerical value %s\n", val);
1304 goto error;
1305 }
1306 x86_cpu_def->model = numvalue;
1307 } else if (!strcmp(featurestr, "stepping")) {
1308 char *err;
1309 numvalue = strtoul(val, &err, 0);
1310 if (!*val || *err || numvalue > 0xf) {
1311 fprintf(stderr, "bad numerical value %s\n", val);
1312 goto error;
1313 }
1314 x86_cpu_def->stepping = numvalue ;
1315 } else if (!strcmp(featurestr, "level")) {
1316 char *err;
1317 numvalue = strtoul(val, &err, 0);
1318 if (!*val || *err) {
1319 fprintf(stderr, "bad numerical value %s\n", val);
1320 goto error;
1321 }
1322 x86_cpu_def->level = numvalue;
1323 } else if (!strcmp(featurestr, "xlevel")) {
1324 char *err;
1325 numvalue = strtoul(val, &err, 0);
1326 if (!*val || *err) {
1327 fprintf(stderr, "bad numerical value %s\n", val);
1328 goto error;
1329 }
1330 if (numvalue < 0x80000000) {
2f7a21c4 1331 numvalue += 0x80000000;
c6dc6f63
AP		 1332 }
1333 x86_cpu_def->xlevel = numvalue;
1334 } else if (!strcmp(featurestr, "vendor")) {
1335 if (strlen(val) != 12) {
1336 fprintf(stderr, "vendor string must be 12 chars long\n");
1337 goto error;
1338 }
1339 x86_cpu_def->vendor1 = 0;
1340 x86_cpu_def->vendor2 = 0;
1341 x86_cpu_def->vendor3 = 0;
1342 for(i = 0; i < 4; i++) {
1343 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1344 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1345 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1346 }
1347 x86_cpu_def->vendor_override = 1;
1348 } else if (!strcmp(featurestr, "model_id")) {
1349 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1350 val);
b862d1fe
JR		 1351 } else if (!strcmp(featurestr, "tsc_freq")) {
1352 int64_t tsc_freq;
1353 char *err;
1354
1355 tsc_freq = strtosz_suffix_unit(val, &err,
1356 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1357 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1358 fprintf(stderr, "bad numerical value %s\n", val);
1359 goto error;
1360 }
1361 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1362 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1363 char *err;
1364 numvalue = strtoul(val, &err, 0);
1365 if (!*val || *err) {
1366 fprintf(stderr, "bad numerical value %s\n", val);
1367 goto error;
1368 }
1369 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1370 } else {
1371 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1372 goto error;
1373 }
1374 } else if (!strcmp(featurestr, "check")) {
1375 check_cpuid = 1;
1376 } else if (!strcmp(featurestr, "enforce")) {
1377 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1378 } else if (!strcmp(featurestr, "hv_relaxed")) {
1379 hyperv_enable_relaxed_timing(true);
1380 } else if (!strcmp(featurestr, "hv_vapic")) {
1381 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1382 } else {
1383 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1384 goto error;
1385 }
1386 featurestr = strtok(NULL, ",");
1387 }
1388 x86_cpu_def->features |= plus_features;
1389 x86_cpu_def->ext_features |= plus_ext_features;
1390 x86_cpu_def->ext2_features |= plus_ext2_features;
1391 x86_cpu_def->ext3_features |= plus_ext3_features;
1392 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1393 x86_cpu_def->svm_features |= plus_svm_features;
a9321a4d 1394 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
c6dc6f63
AP		 1395 x86_cpu_def->features &= ~minus_features;
1396 x86_cpu_def->ext_features &= ~minus_ext_features;
1397 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1398 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1399 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1400 x86_cpu_def->svm_features &= ~minus_svm_features;
a9321a4d 1401 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
6e746f30
EH		 1402 if (check_cpuid && kvm_enabled()) {
1403 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
c6dc6f63
AP		 1404 goto error;
1405 }
c6dc6f63
AP		 1406 return 0;
1407
1408error:
c6dc6f63
AP		 1409 return -1;
1410}
1411
1412/* generate a composite string into buf of all cpuid names in featureset
1413 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1414 * if flags, suppress names undefined in featureset.
1415 */
1416static void listflags(char *buf, int bufsize, uint32_t fbits,
1417 const char **featureset, uint32_t flags)
1418{
1419 const char **p = &featureset[31];
1420 char *q, *b, bit;
1421 int nc;
1422
1423 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1424 *buf = '\0';
1425 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1426 if (fbits & 1 << bit && (*p || !flags)) {
1427 if (*p)
1428 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1429 else
1430 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1431 if (bufsize <= nc) {
1432 if (b) {
1433 memcpy(b, "...", sizeof("..."));
1434 }
1435 return;
1436 }
1437 q += nc;
1438 bufsize -= nc;
1439 }
1440}
1441
e916cbf8
PM		 1442/* generate CPU information. */
1443void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1444{
c6dc6f63
AP		 1445 x86_def_t *def;
1446 char buf[256];
1447
c6dc6f63 1448 for (def = x86_defs; def; def = def->next) {
c04321b3 1449 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1450 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1451 }
ed2c54d4
AP		 1452 if (kvm_enabled()) {
1453 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1454 }
6cdf8854
PM		 1455 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1456 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1457 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1458 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1459 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1460 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1461 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1462 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1463 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1464}
1465
76b64a7a 1466CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1467{
1468 CpuDefinitionInfoList *cpu_list = NULL;
1469 x86_def_t *def;
1470
1471 for (def = x86_defs; def; def = def->next) {
1472 CpuDefinitionInfoList *entry;
1473 CpuDefinitionInfo *info;
1474
1475 info = g_malloc0(sizeof(*info));
1476 info->name = g_strdup(def->name);
1477
1478 entry = g_malloc0(sizeof(*entry));
1479 entry->value = info;
1480 entry->next = cpu_list;
1481 cpu_list = entry;
1482 }
1483
1484 return cpu_list;
1485}
1486
bc74b7db
EH		 1487#ifdef CONFIG_KVM
1488static void filter_features_for_kvm(X86CPU *cpu)
1489{
1490 CPUX86State *env = &cpu->env;
1491 KVMState *s = kvm_state;
1492
b8091f24
EH		 1493 env->cpuid_features &=
1494 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1495 env->cpuid_ext_features &=
1496 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1497 env->cpuid_ext2_features &=
1498 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1499 env->cpuid_ext3_features &=
1500 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1501 env->cpuid_svm_features &=
1502 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1503 env->cpuid_7_0_ebx_features &=
1504 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1505 env->cpuid_kvm_features &=
b8091f24
EH		 1506 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1507 env->cpuid_ext4_features &=
1508 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1509
1510}
1511#endif
1512
61dcd775 1513int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1514{
61dcd775 1515 CPUX86State *env = &cpu->env;
c6dc6f63 1516 x86_def_t def1, *def = &def1;
71ad61d3 1517 Error *error = NULL;
8f961357
EH		 1518 char *name, *features;
1519 gchar **model_pieces;
c6dc6f63 1520
db0ad1ba
JR		 1521 memset(def, 0, sizeof(*def));
1522
8f961357
EH		 1523 model_pieces = g_strsplit(cpu_model, ",", 2);
1524 if (!model_pieces[0]) {
1525 goto error;
1526 }
1527 name = model_pieces[0];
1528 features = model_pieces[1];
1529
1530 if (cpu_x86_find_by_name(def, name) < 0) {
1531 goto error;
1532 }
1533
1534 if (cpu_x86_parse_featurestr(def, features) < 0) {
1535 goto error;
1536 }
c6dc6f63
AP		 1537 if (def->vendor1) {
1538 env->cpuid_vendor1 = def->vendor1;
1539 env->cpuid_vendor2 = def->vendor2;
1540 env->cpuid_vendor3 = def->vendor3;
1541 } else {
1542 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1543 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1544 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1545 }
1546 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1547 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1548 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1549 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1550 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1551 env->cpuid_features = def->features;
c6dc6f63
AP		 1552 env->cpuid_ext_features = def->ext_features;
1553 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1554 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1555 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1556 env->cpuid_kvm_features = def->kvm_features;
296acb64 1557 env->cpuid_svm_features = def->svm_features;
b3baa152 1558 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1559 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1560 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1561 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1562 "tsc-frequency", &error);
3b671a40
EH		 1563
1564 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1565 * CPUID[1].EDX.
1566 */
1567 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1568 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1569 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1570 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1571 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1572 }
1573
938d4c25 1574 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
18eb473f
IM		 1575 if (error) {
1576 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1577 error_free(error);
8f961357 1578 goto error;
71ad61d3 1579 }
8f961357
EH		 1580
1581 g_strfreev(model_pieces);
c6dc6f63 1582 return 0;
8f961357
EH		 1583error:
1584 g_strfreev(model_pieces);
1585 return -1;
c6dc6f63
AP		 1586}
1587
1588#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1589
0e26b7b8
BS		 1590void cpu_clear_apic_feature(CPUX86State *env)
1591{
1592 env->cpuid_features &= ~CPUID_APIC;
1593}
1594
c6dc6f63
AP		 1595#endif /* !CONFIG_USER_ONLY */
1596
c04321b3 1597/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1598 */
1599void x86_cpudef_setup(void)
1600{
93bfef4c
CV		 1601 int i, j;
1602 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1603
1604 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1605 x86_def_t *def = &builtin_x86_defs[i];
1606 def->next = x86_defs;
93bfef4c
CV		 1607
1608 /* Look for specific "cpudef" models that */
09faecf2 1609 /* have the QEMU version in .model_id */
93bfef4c 1610 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1611 if (strcmp(model_with_versions[j], def->name) == 0) {
1612 pstrcpy(def->model_id, sizeof(def->model_id),
1613 "QEMU Virtual CPU version ");
1614 pstrcat(def->model_id, sizeof(def->model_id),
1615 qemu_get_version());
93bfef4c
CV		 1616 break;
1617 }
1618 }
1619
bc3e1291 1620 x86_defs = def;
c6dc6f63 1621 }
c6dc6f63
AP		 1622}
1623
c6dc6f63
AP		 1624static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1625 uint32_t *ecx, uint32_t *edx)
1626{
1627 *ebx = env->cpuid_vendor1;
1628 *edx = env->cpuid_vendor2;
1629 *ecx = env->cpuid_vendor3;
1630
1631 /* sysenter isn't supported on compatibility mode on AMD, syscall
1632 * isn't supported in compatibility mode on Intel.
1633 * Normally we advertise the actual cpu vendor, but you can override
1634 * this if you want to use KVM's sysenter/syscall emulation
1635 * in compatibility mode and when doing cross vendor migration
1636 */
89354998 1637 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1638 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1639 }
1640}
1641
1642void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1643 uint32_t *eax, uint32_t *ebx,
1644 uint32_t *ecx, uint32_t *edx)
1645{
a60f24b5
AF		 1646 X86CPU *cpu = x86_env_get_cpu(env);
1647 CPUState *cs = CPU(cpu);
1648
c6dc6f63
AP		 1649 /* test if maximum index reached */
1650 if (index & 0x80000000) {
b3baa152
BW		 1651 if (index > env->cpuid_xlevel) {
1652 if (env->cpuid_xlevel2 > 0) {
1653 /* Handle the Centaur's CPUID instruction. */
1654 if (index > env->cpuid_xlevel2) {
1655 index = env->cpuid_xlevel2;
1656 } else if (index < 0xC0000000) {
1657 index = env->cpuid_xlevel;
1658 }
1659 } else {
57f26ae7
EH		 1660 /* Intel documentation states that invalid EAX input will
1661 * return the same information as EAX=cpuid_level
1662 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1663 */
1664 index = env->cpuid_level;
b3baa152
BW		 1665 }
1666 }
c6dc6f63
AP		 1667 } else {
1668 if (index > env->cpuid_level)
1669 index = env->cpuid_level;
1670 }
1671
1672 switch(index) {
1673 case 0:
1674 *eax = env->cpuid_level;
1675 get_cpuid_vendor(env, ebx, ecx, edx);
1676 break;
1677 case 1:
1678 *eax = env->cpuid_version;
1679 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1680 *ecx = env->cpuid_ext_features;
1681 *edx = env->cpuid_features;
1682 if (env->nr_cores * env->nr_threads > 1) {
1683 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1684 *edx |= 1 << 28; /* HTT bit */
1685 }
1686 break;
1687 case 2:
1688 /* cache info: needed for Pentium Pro compatibility */
1689 *eax = 1;
1690 *ebx = 0;
1691 *ecx = 0;
1692 *edx = 0x2c307d;
1693 break;
1694 case 4:
1695 /* cache info: needed for Core compatibility */
1696 if (env->nr_cores > 1) {
2f7a21c4 1697 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1698 } else {
2f7a21c4 1699 *eax = 0;
c6dc6f63
AP		 1700 }
1701 switch (count) {
1702 case 0: /* L1 dcache info */
1703 *eax |= 0x0000121;
1704 *ebx = 0x1c0003f;
1705 *ecx = 0x000003f;
1706 *edx = 0x0000001;
1707 break;
1708 case 1: /* L1 icache info */
1709 *eax |= 0x0000122;
1710 *ebx = 0x1c0003f;
1711 *ecx = 0x000003f;
1712 *edx = 0x0000001;
1713 break;
1714 case 2: /* L2 cache info */
1715 *eax |= 0x0000143;
1716 if (env->nr_threads > 1) {
1717 *eax |= (env->nr_threads - 1) << 14;
1718 }
1719 *ebx = 0x3c0003f;
1720 *ecx = 0x0000fff;
1721 *edx = 0x0000001;
1722 break;
1723 default: /* end of info */
1724 *eax = 0;
1725 *ebx = 0;
1726 *ecx = 0;
1727 *edx = 0;
1728 break;
1729 }
1730 break;
1731 case 5:
1732 /* mwait info: needed for Core compatibility */
1733 *eax = 0; /* Smallest monitor-line size in bytes */
1734 *ebx = 0; /* Largest monitor-line size in bytes */
1735 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1736 *edx = 0;
1737 break;
1738 case 6:
1739 /* Thermal and Power Leaf */
1740 *eax = 0;
1741 *ebx = 0;
1742 *ecx = 0;
1743 *edx = 0;
1744 break;
f7911686 1745 case 7:
13526728
EH		 1746 /* Structured Extended Feature Flags Enumeration Leaf */
1747 if (count == 0) {
1748 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1749 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1750 *ecx = 0; /* Reserved */
1751 *edx = 0; /* Reserved */
f7911686
YW		 1752 } else {
1753 *eax = 0;
1754 *ebx = 0;
1755 *ecx = 0;
1756 *edx = 0;
1757 }
1758 break;
c6dc6f63
AP		 1759 case 9:
1760 /* Direct Cache Access Information Leaf */
1761 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1762 *ebx = 0;
1763 *ecx = 0;
1764 *edx = 0;
1765 break;
1766 case 0xA:
1767 /* Architectural Performance Monitoring Leaf */
a0fa8208 1768 if (kvm_enabled()) {
a60f24b5 1769 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1770
1771 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1772 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1773 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1774 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1775 } else {
1776 *eax = 0;
1777 *ebx = 0;
1778 *ecx = 0;
1779 *edx = 0;
1780 }
c6dc6f63 1781 break;
51e49430
SY		 1782 case 0xD:
1783 /* Processor Extended State */
1784 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1785 *eax = 0;
1786 *ebx = 0;
1787 *ecx = 0;
1788 *edx = 0;
1789 break;
1790 }
1791 if (kvm_enabled()) {
a60f24b5 1792 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1793
1794 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1795 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1796 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1797 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1798 } else {
1799 *eax = 0;
1800 *ebx = 0;
1801 *ecx = 0;
1802 *edx = 0;
1803 }
1804 break;
c6dc6f63
AP		 1805 case 0x80000000:
1806 *eax = env->cpuid_xlevel;
1807 *ebx = env->cpuid_vendor1;
1808 *edx = env->cpuid_vendor2;
1809 *ecx = env->cpuid_vendor3;
1810 break;
1811 case 0x80000001:
1812 *eax = env->cpuid_version;
1813 *ebx = 0;
1814 *ecx = env->cpuid_ext3_features;
1815 *edx = env->cpuid_ext2_features;
1816
1817 /* The Linux kernel checks for the CMPLegacy bit and
1818 * discards multiple thread information if it is set.
1819 * So dont set it here for Intel to make Linux guests happy.
1820 */
1821 if (env->nr_cores * env->nr_threads > 1) {
1822 uint32_t tebx, tecx, tedx;
1823 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1824 if (tebx != CPUID_VENDOR_INTEL_1 ||
1825 tedx != CPUID_VENDOR_INTEL_2 ||
1826 tecx != CPUID_VENDOR_INTEL_3) {
1827 *ecx |= 1 << 1; /* CmpLegacy bit */
1828 }
1829 }
c6dc6f63
AP		 1830 break;
1831 case 0x80000002:
1832 case 0x80000003:
1833 case 0x80000004:
1834 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1835 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1836 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1837 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1838 break;
1839 case 0x80000005:
1840 /* cache info (L1 cache) */
1841 *eax = 0x01ff01ff;
1842 *ebx = 0x01ff01ff;
1843 *ecx = 0x40020140;
1844 *edx = 0x40020140;
1845 break;
1846 case 0x80000006:
1847 /* cache info (L2 cache) */
1848 *eax = 0;
1849 *ebx = 0x42004200;
1850 *ecx = 0x02008140;
1851 *edx = 0;
1852 break;
1853 case 0x80000008:
1854 /* virtual & phys address size in low 2 bytes. */
1855/* XXX: This value must match the one used in the MMU code. */
1856 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1857 /* 64 bit processor */
1858/* XXX: The physical address space is limited to 42 bits in exec.c. */
1859 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1860 } else {
1861 if (env->cpuid_features & CPUID_PSE36)
1862 *eax = 0x00000024; /* 36 bits physical */
1863 else
1864 *eax = 0x00000020; /* 32 bits physical */
1865 }
1866 *ebx = 0;
1867 *ecx = 0;
1868 *edx = 0;
1869 if (env->nr_cores * env->nr_threads > 1) {
1870 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1871 }
1872 break;
1873 case 0x8000000A:
9f3fb565
EH		 1874 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1875 *eax = 0x00000001; /* SVM Revision */
1876 *ebx = 0x00000010; /* nr of ASIDs */
1877 *ecx = 0;
1878 *edx = env->cpuid_svm_features; /* optional features */
1879 } else {
1880 *eax = 0;
1881 *ebx = 0;
1882 *ecx = 0;
1883 *edx = 0;
1884 }
c6dc6f63 1885 break;
b3baa152
BW		 1886 case 0xC0000000:
1887 *eax = env->cpuid_xlevel2;
1888 *ebx = 0;
1889 *ecx = 0;
1890 *edx = 0;
1891 break;
1892 case 0xC0000001:
1893 /* Support for VIA CPU's CPUID instruction */
1894 *eax = env->cpuid_version;
1895 *ebx = 0;
1896 *ecx = 0;
1897 *edx = env->cpuid_ext4_features;
1898 break;
1899 case 0xC0000002:
1900 case 0xC0000003:
1901 case 0xC0000004:
1902 /* Reserved for the future, and now filled with zero */
1903 *eax = 0;
1904 *ebx = 0;
1905 *ecx = 0;
1906 *edx = 0;
1907 break;
c6dc6f63
AP		 1908 default:
1909 /* reserved values: zero */
1910 *eax = 0;
1911 *ebx = 0;
1912 *ecx = 0;
1913 *edx = 0;
1914 break;
1915 }
1916}
5fd2087a
AF		 1917
1918/* CPUClass::reset() */
1919static void x86_cpu_reset(CPUState *s)
1920{
1921 X86CPU *cpu = X86_CPU(s);
1922 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1923 CPUX86State *env = &cpu->env;
c1958aea
AF		 1924 int i;
1925
1926 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1927 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
6fd2a026 1928 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1929 }
5fd2087a
AF		 1930
1931 xcc->parent_reset(s);
1932
c1958aea
AF		 1933
1934 memset(env, 0, offsetof(CPUX86State, breakpoints));
1935
1936 tlb_flush(env, 1);
1937
1938 env->old_exception = -1;
1939
1940 /* init to reset state */
1941
1942#ifdef CONFIG_SOFTMMU
1943 env->hflags |= HF_SOFTMMU_MASK;
1944#endif
1945 env->hflags2 |= HF2_GIF_MASK;
1946
1947 cpu_x86_update_cr0(env, 0x60000010);
1948 env->a20_mask = ~0x0;
1949 env->smbase = 0x30000;
1950
1951 env->idt.limit = 0xffff;
1952 env->gdt.limit = 0xffff;
1953 env->ldt.limit = 0xffff;
1954 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1955 env->tr.limit = 0xffff;
1956 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1957
1958 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1959 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1960 DESC_R_MASK | DESC_A_MASK);
1961 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1962 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1963 DESC_A_MASK);
1964 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1965 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1966 DESC_A_MASK);
1967 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1968 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1969 DESC_A_MASK);
1970 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1971 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1972 DESC_A_MASK);
1973 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1974 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1975 DESC_A_MASK);
1976
1977 env->eip = 0xfff0;
1978 env->regs[R_EDX] = env->cpuid_version;
1979
1980 env->eflags = 0x2;
1981
1982 /* FPU init */
1983 for (i = 0; i < 8; i++) {
1984 env->fptags[i] = 1;
1985 }
1986 env->fpuc = 0x37f;
1987
1988 env->mxcsr = 0x1f80;
1989
1990 env->pat = 0x0007040600070406ULL;
1991 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1992
1993 memset(env->dr, 0, sizeof(env->dr));
1994 env->dr[6] = DR6_FIXED_1;
1995 env->dr[7] = DR7_FIXED_1;
1996 cpu_breakpoint_remove_all(env, BP_CPU);
1997 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1998
1999#if !defined(CONFIG_USER_ONLY)
2000 /* We hard-wire the BSP to the first CPU. */
2001 if (env->cpu_index == 0) {
2002 apic_designate_bsp(env->apic_state);
2003 }
2004
2005 env->halted = !cpu_is_bsp(cpu);
2006#endif
5fd2087a
AF		 2007}
2008
dd673288
IM		 2009#ifndef CONFIG_USER_ONLY
2010bool cpu_is_bsp(X86CPU *cpu)
2011{
2012 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2013}
65dee380
IM		 2014
2015/* TODO: remove me, when reset over QOM tree is implemented */
2016static void x86_cpu_machine_reset_cb(void *opaque)
2017{
2018 X86CPU *cpu = opaque;
2019 cpu_reset(CPU(cpu));
2020}
dd673288
IM		 2021#endif
2022
de024815
AF		 2023static void mce_init(X86CPU *cpu)
2024{
2025 CPUX86State *cenv = &cpu->env;
2026 unsigned int bank;
2027
2028 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2029 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2030 (CPUID_MCE | CPUID_MCA)) {
2031 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2032 cenv->mcg_ctl = ~(uint64_t)0;
2033 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2034 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2035 }
2036 }
2037}
2038
bdeec802
IM		 2039#define MSI_ADDR_BASE 0xfee00000
2040
2041#ifndef CONFIG_USER_ONLY
2042static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2043{
2044 static int apic_mapped;
2045 CPUX86State *env = &cpu->env;
449994eb 2046 APICCommonState *apic;
bdeec802
IM		 2047 const char *apic_type = "apic";
2048
2049 if (kvm_irqchip_in_kernel()) {
2050 apic_type = "kvm-apic";
2051 } else if (xen_enabled()) {
2052 apic_type = "xen-apic";
2053 }
2054
2055 env->apic_state = qdev_try_create(NULL, apic_type);
2056 if (env->apic_state == NULL) {
2057 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2058 return;
2059 }
2060
2061 object_property_add_child(OBJECT(cpu), "apic",
2062 OBJECT(env->apic_state), NULL);
2063 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2064 /* TODO: convert to link<> */
449994eb 2065 apic = APIC_COMMON(env->apic_state);
60671e58 2066 apic->cpu = cpu;
bdeec802
IM		 2067
2068 if (qdev_init(env->apic_state)) {
2069 error_setg(errp, "APIC device '%s' could not be initialized",
2070 object_get_typename(OBJECT(env->apic_state)));
2071 return;
2072 }
2073
2074 /* XXX: mapping more APICs at the same memory location */
2075 if (apic_mapped == 0) {
2076 /* NOTE: the APIC is directly connected to the CPU - it is not
2077 on the global memory bus. */
2078 /* XXX: what if the base changes? */
2079 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2080 apic_mapped = 1;
2081 }
2082}
2083#endif
2084
7a059953
AF		 2085void x86_cpu_realize(Object *obj, Error **errp)
2086{
2087 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2088 CPUX86State *env = &cpu->env;
2089
2090 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2091 env->cpuid_level = 7;
2092 }
7a059953 2093
4586f157
IM		 2094 if (!kvm_enabled()) {
2095 env->cpuid_features &= TCG_FEATURES;
2096 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2097 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2098#ifdef TARGET_X86_64
2099 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2100#endif
2101 );
2102 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2103 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2104 } else {
2105#ifdef CONFIG_KVM
2106 filter_features_for_kvm(cpu);
2107#endif
2108 }
2109
65dee380
IM		 2110#ifndef CONFIG_USER_ONLY
2111 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2112
2113 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2114 x86_cpu_apic_init(cpu, errp);
2115 if (error_is_set(errp)) {
2116 return;
2117 }
2118 }
65dee380
IM		 2119#endif
2120
7a059953
AF		 2121 mce_init(cpu);
2122 qemu_init_vcpu(&cpu->env);
65dee380 2123 cpu_reset(CPU(cpu));
7a059953
AF		 2124}
2125
de024815
AF		 2126static void x86_cpu_initfn(Object *obj)
2127{
2128 X86CPU *cpu = X86_CPU(obj);
2129 CPUX86State *env = &cpu->env;
d65e9815 2130 static int inited;
de024815
AF		 2131
2132 cpu_exec_init(env);
71ad61d3
AF		 2133
2134 object_property_add(obj, "family", "int",
95b8519d 2135 x86_cpuid_version_get_family,
71ad61d3 2136 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2137 object_property_add(obj, "model", "int",
67e30c83 2138 x86_cpuid_version_get_model,
c5291a4f 2139 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2140 object_property_add(obj, "stepping", "int",
35112e41 2141 x86_cpuid_version_get_stepping,
036e2222 2142 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2143 object_property_add(obj, "level", "int",
2144 x86_cpuid_get_level,
2145 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2146 object_property_add(obj, "xlevel", "int",
2147 x86_cpuid_get_xlevel,
2148 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2149 object_property_add_str(obj, "vendor",
2150 x86_cpuid_get_vendor,
2151 x86_cpuid_set_vendor, NULL);
938d4c25 2152 object_property_add_str(obj, "model-id",
63e886eb 2153 x86_cpuid_get_model_id,
938d4c25 2154 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2155 object_property_add(obj, "tsc-frequency", "int",
2156 x86_cpuid_get_tsc_freq,
2157 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2158
de024815 2159 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 2160
2161 /* init various static tables used in TCG mode */
2162 if (tcg_enabled() && !inited) {
2163 inited = 1;
2164 optimize_flags_init();
2165#ifndef CONFIG_USER_ONLY
2166 cpu_set_debug_excp_handler(breakpoint_handler);
2167#endif
2168 }
de024815
AF		 2169}
2170
5fd2087a
AF		 2171static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2172{
2173 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2174 CPUClass *cc = CPU_CLASS(oc);
2175
2176 xcc->parent_reset = cc->reset;
2177 cc->reset = x86_cpu_reset;
2178}
2179
2180static const TypeInfo x86_cpu_type_info = {
2181 .name = TYPE_X86_CPU,
2182 .parent = TYPE_CPU,
2183 .instance_size = sizeof(X86CPU),
de024815 2184 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2185 .abstract = false,
2186 .class_size = sizeof(X86CPUClass),
2187 .class_init = x86_cpu_common_class_init,
2188};
2189
2190static void x86_cpu_register_types(void)
2191{
2192 type_register_static(&x86_cpu_type_info);
2193}
2194
2195type_init(x86_cpu_register_types)
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