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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba MW |
30 | #include <linux/kernel.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/pci.h> | |
be7b6275 | 35 | #include <linux/poison.h> |
c3bfe717 | 36 | #include <linux/ptrace.h> |
b60503ba MW |
37 | #include <linux/sched.h> |
38 | #include <linux/slab.h> | |
e1e5e564 | 39 | #include <linux/t10-pi.h> |
b60503ba | 40 | #include <linux/types.h> |
2f8e2c87 | 41 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 42 | #include <asm/unaligned.h> |
797a796a | 43 | |
f11bb3e2 CH |
44 | #include "nvme.h" |
45 | ||
9d43cf64 | 46 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 47 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
48 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
49 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 50 | |
21d34711 | 51 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
52 | module_param(admin_timeout, byte, 0644); |
53 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 54 | |
bd67608a MW |
55 | unsigned char nvme_io_timeout = 30; |
56 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 57 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 58 | |
5fd4ce1b | 59 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
60 | module_param(shutdown_timeout, byte, 0644); |
61 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
62 | ||
58ffacb5 MW |
63 | static int use_threaded_interrupts; |
64 | module_param(use_threaded_interrupts, int, 0); | |
65 | ||
8ffaadf7 JD |
66 | static bool use_cmb_sqes = true; |
67 | module_param(use_cmb_sqes, bool, 0644); | |
68 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
69 | ||
1fa6aead MW |
70 | static LIST_HEAD(dev_list); |
71 | static struct task_struct *nvme_thread; | |
9a6b9458 | 72 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 73 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 74 | |
1c63dc66 CH |
75 | struct nvme_dev; |
76 | struct nvme_queue; | |
d4f6c3ab | 77 | struct nvme_iod; |
1c63dc66 | 78 | |
90667892 | 79 | static int __nvme_reset(struct nvme_dev *dev); |
4cc06521 | 80 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 81 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
d4f6c3ab | 82 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); |
3cf519b5 | 83 | static void nvme_dead_ctrl(struct nvme_dev *dev); |
d4b4ff8e | 84 | |
4d115420 KB |
85 | struct async_cmd_info { |
86 | struct kthread_work work; | |
87 | struct kthread_worker *worker; | |
a4aea562 | 88 | struct request *req; |
4d115420 KB |
89 | u32 result; |
90 | int status; | |
91 | void *ctx; | |
92 | }; | |
1fa6aead | 93 | |
1c63dc66 CH |
94 | /* |
95 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
96 | */ | |
97 | struct nvme_dev { | |
98 | struct list_head node; | |
99 | struct nvme_queue **queues; | |
100 | struct blk_mq_tag_set tagset; | |
101 | struct blk_mq_tag_set admin_tagset; | |
102 | u32 __iomem *dbs; | |
103 | struct device *dev; | |
104 | struct dma_pool *prp_page_pool; | |
105 | struct dma_pool *prp_small_pool; | |
106 | unsigned queue_count; | |
107 | unsigned online_queues; | |
108 | unsigned max_qid; | |
109 | int q_depth; | |
110 | u32 db_stride; | |
1c63dc66 CH |
111 | struct msix_entry *entry; |
112 | void __iomem *bar; | |
1c63dc66 CH |
113 | struct work_struct reset_work; |
114 | struct work_struct probe_work; | |
115 | struct work_struct scan_work; | |
116 | bool subsystem; | |
1c63dc66 CH |
117 | void __iomem *cmb; |
118 | dma_addr_t cmb_dma_addr; | |
119 | u64 cmb_size; | |
120 | u32 cmbsz; | |
121 | ||
122 | struct nvme_ctrl ctrl; | |
123 | }; | |
124 | ||
125 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
126 | { | |
127 | return container_of(ctrl, struct nvme_dev, ctrl); | |
128 | } | |
129 | ||
b60503ba MW |
130 | /* |
131 | * An NVM Express queue. Each device has at least two (one for admin | |
132 | * commands and one for I/O commands). | |
133 | */ | |
134 | struct nvme_queue { | |
135 | struct device *q_dmadev; | |
091b6092 | 136 | struct nvme_dev *dev; |
3193f07b | 137 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
138 | spinlock_t q_lock; |
139 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 140 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 141 | volatile struct nvme_completion *cqes; |
42483228 | 142 | struct blk_mq_tags **tags; |
b60503ba MW |
143 | dma_addr_t sq_dma_addr; |
144 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
145 | u32 __iomem *q_db; |
146 | u16 q_depth; | |
6222d172 | 147 | s16 cq_vector; |
b60503ba MW |
148 | u16 sq_head; |
149 | u16 sq_tail; | |
150 | u16 cq_head; | |
c30341dc | 151 | u16 qid; |
e9539f47 MW |
152 | u8 cq_phase; |
153 | u8 cqe_seen; | |
4d115420 | 154 | struct async_cmd_info cmdinfo; |
b60503ba MW |
155 | }; |
156 | ||
71bd150c CH |
157 | /* |
158 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
159 | * entries. You can't see it in this data structure because C doesn't let | |
160 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
161 | * allocated to store the PRP list. | |
162 | */ | |
163 | struct nvme_iod { | |
164 | unsigned long private; /* For the use of the submitter of the I/O */ | |
165 | int npages; /* In the PRP list. 0 means small pool in use */ | |
166 | int offset; /* Of PRP list */ | |
167 | int nents; /* Used in scatterlist */ | |
168 | int length; /* Of data, in bytes */ | |
169 | dma_addr_t first_dma; | |
170 | struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ | |
171 | struct scatterlist sg[0]; | |
172 | }; | |
173 | ||
b60503ba MW |
174 | /* |
175 | * Check we didin't inadvertently grow the command struct | |
176 | */ | |
177 | static inline void _nvme_check_size(void) | |
178 | { | |
179 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
180 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
181 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
182 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
183 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 184 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 185 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
186 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
187 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
188 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 190 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
191 | } |
192 | ||
edd10d33 | 193 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
194 | struct nvme_completion *); |
195 | ||
e85248e5 | 196 | struct nvme_cmd_info { |
c2f5b650 MW |
197 | nvme_completion_fn fn; |
198 | void *ctx; | |
c30341dc | 199 | int aborted; |
a4aea562 | 200 | struct nvme_queue *nvmeq; |
ac3dd5bd | 201 | struct nvme_iod iod[0]; |
e85248e5 MW |
202 | }; |
203 | ||
ac3dd5bd JA |
204 | /* |
205 | * Max size of iod being embedded in the request payload | |
206 | */ | |
207 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 208 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
fda631ff | 209 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
210 | |
211 | /* | |
212 | * Will slightly overestimate the number of pages needed. This is OK | |
213 | * as it only leads to a small amount of wasted memory for the lifetime of | |
214 | * the I/O. | |
215 | */ | |
216 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
217 | { | |
5fd4ce1b CH |
218 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
219 | dev->ctrl.page_size); | |
ac3dd5bd JA |
220 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
221 | } | |
222 | ||
223 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
224 | { | |
225 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
226 | ||
227 | ret += sizeof(struct nvme_iod); | |
228 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
229 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
a4aea562 MB |
234 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
235 | unsigned int hctx_idx) | |
e85248e5 | 236 | { |
a4aea562 MB |
237 | struct nvme_dev *dev = data; |
238 | struct nvme_queue *nvmeq = dev->queues[0]; | |
239 | ||
42483228 KB |
240 | WARN_ON(hctx_idx != 0); |
241 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
242 | WARN_ON(nvmeq->tags); | |
243 | ||
a4aea562 | 244 | hctx->driver_data = nvmeq; |
42483228 | 245 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 246 | return 0; |
e85248e5 MW |
247 | } |
248 | ||
4af0e21c KB |
249 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
250 | { | |
251 | struct nvme_queue *nvmeq = hctx->driver_data; | |
252 | ||
253 | nvmeq->tags = NULL; | |
254 | } | |
255 | ||
a4aea562 MB |
256 | static int nvme_admin_init_request(void *data, struct request *req, |
257 | unsigned int hctx_idx, unsigned int rq_idx, | |
258 | unsigned int numa_node) | |
22404274 | 259 | { |
a4aea562 MB |
260 | struct nvme_dev *dev = data; |
261 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
262 | struct nvme_queue *nvmeq = dev->queues[0]; | |
263 | ||
264 | BUG_ON(!nvmeq); | |
265 | cmd->nvmeq = nvmeq; | |
266 | return 0; | |
22404274 KB |
267 | } |
268 | ||
a4aea562 MB |
269 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
270 | unsigned int hctx_idx) | |
b60503ba | 271 | { |
a4aea562 | 272 | struct nvme_dev *dev = data; |
42483228 | 273 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 274 | |
42483228 KB |
275 | if (!nvmeq->tags) |
276 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 277 | |
42483228 | 278 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
279 | hctx->driver_data = nvmeq; |
280 | return 0; | |
b60503ba MW |
281 | } |
282 | ||
a4aea562 MB |
283 | static int nvme_init_request(void *data, struct request *req, |
284 | unsigned int hctx_idx, unsigned int rq_idx, | |
285 | unsigned int numa_node) | |
b60503ba | 286 | { |
a4aea562 MB |
287 | struct nvme_dev *dev = data; |
288 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
289 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
290 | ||
291 | BUG_ON(!nvmeq); | |
292 | cmd->nvmeq = nvmeq; | |
293 | return 0; | |
294 | } | |
295 | ||
296 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
297 | nvme_completion_fn handler) | |
298 | { | |
299 | cmd->fn = handler; | |
300 | cmd->ctx = ctx; | |
301 | cmd->aborted = 0; | |
c917dfe5 | 302 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
303 | } |
304 | ||
ac3dd5bd JA |
305 | static void *iod_get_private(struct nvme_iod *iod) |
306 | { | |
307 | return (void *) (iod->private & ~0x1UL); | |
308 | } | |
309 | ||
310 | /* | |
311 | * If bit 0 is set, the iod is embedded in the request payload. | |
312 | */ | |
313 | static bool iod_should_kfree(struct nvme_iod *iod) | |
314 | { | |
fda631ff | 315 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
316 | } |
317 | ||
c2f5b650 MW |
318 | /* Special values must be less than 0x1000 */ |
319 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
320 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
321 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
322 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 323 | |
edd10d33 | 324 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
325 | struct nvme_completion *cqe) |
326 | { | |
327 | if (ctx == CMD_CTX_CANCELLED) | |
328 | return; | |
c2f5b650 | 329 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 330 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
331 | "completed id %d twice on queue %d\n", |
332 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
333 | return; | |
334 | } | |
335 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 336 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
337 | "invalid id %d completed on queue %d\n", |
338 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
339 | return; | |
340 | } | |
edd10d33 | 341 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
342 | } |
343 | ||
a4aea562 | 344 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 345 | { |
c2f5b650 | 346 | void *ctx; |
b60503ba | 347 | |
859361a2 | 348 | if (fn) |
a4aea562 MB |
349 | *fn = cmd->fn; |
350 | ctx = cmd->ctx; | |
351 | cmd->fn = special_completion; | |
352 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 353 | return ctx; |
b60503ba MW |
354 | } |
355 | ||
a4aea562 MB |
356 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
357 | struct nvme_completion *cqe) | |
3c0cf138 | 358 | { |
a4aea562 MB |
359 | u32 result = le32_to_cpup(&cqe->result); |
360 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
361 | ||
362 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
1c63dc66 | 363 | ++nvmeq->dev->ctrl.event_limit; |
a5768aa8 KB |
364 | if (status != NVME_SC_SUCCESS) |
365 | return; | |
366 | ||
367 | switch (result & 0xff07) { | |
368 | case NVME_AER_NOTICE_NS_CHANGED: | |
369 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
370 | schedule_work(&nvmeq->dev->scan_work); | |
371 | default: | |
372 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
373 | } | |
b60503ba MW |
374 | } |
375 | ||
a4aea562 MB |
376 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
377 | struct nvme_completion *cqe) | |
5a92e700 | 378 | { |
a4aea562 MB |
379 | struct request *req = ctx; |
380 | ||
381 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
382 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 383 | |
42483228 | 384 | blk_mq_free_request(req); |
a51afb54 | 385 | |
a4aea562 | 386 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
1c63dc66 | 387 | ++nvmeq->dev->ctrl.abort_limit; |
5a92e700 KB |
388 | } |
389 | ||
a4aea562 MB |
390 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
391 | struct nvme_completion *cqe) | |
b60503ba | 392 | { |
a4aea562 MB |
393 | struct async_cmd_info *cmdinfo = ctx; |
394 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
395 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
396 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 397 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
398 | } |
399 | ||
a4aea562 MB |
400 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
401 | unsigned int tag) | |
b60503ba | 402 | { |
42483228 | 403 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 404 | |
a4aea562 | 405 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
406 | } |
407 | ||
a4aea562 MB |
408 | /* |
409 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
410 | */ | |
411 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
412 | nvme_completion_fn *fn) | |
4f5099af | 413 | { |
a4aea562 MB |
414 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
415 | void *ctx; | |
416 | if (tag >= nvmeq->q_depth) { | |
417 | *fn = special_completion; | |
418 | return CMD_CTX_INVALID; | |
419 | } | |
420 | if (fn) | |
421 | *fn = cmd->fn; | |
422 | ctx = cmd->ctx; | |
423 | cmd->fn = special_completion; | |
424 | cmd->ctx = CMD_CTX_COMPLETED; | |
425 | return ctx; | |
b60503ba MW |
426 | } |
427 | ||
428 | /** | |
714a7a22 | 429 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
430 | * @nvmeq: The queue to use |
431 | * @cmd: The command to send | |
432 | * | |
433 | * Safe to use from interrupt context | |
434 | */ | |
e3f879bf SB |
435 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
436 | struct nvme_command *cmd) | |
b60503ba | 437 | { |
a4aea562 MB |
438 | u16 tail = nvmeq->sq_tail; |
439 | ||
8ffaadf7 JD |
440 | if (nvmeq->sq_cmds_io) |
441 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
442 | else | |
443 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
444 | ||
b60503ba MW |
445 | if (++tail == nvmeq->q_depth) |
446 | tail = 0; | |
7547881d | 447 | writel(tail, nvmeq->q_db); |
b60503ba | 448 | nvmeq->sq_tail = tail; |
b60503ba MW |
449 | } |
450 | ||
e3f879bf | 451 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
a4aea562 MB |
452 | { |
453 | unsigned long flags; | |
a4aea562 | 454 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
e3f879bf | 455 | __nvme_submit_cmd(nvmeq, cmd); |
a4aea562 | 456 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); |
a4aea562 MB |
457 | } |
458 | ||
eca18b23 | 459 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 460 | { |
eca18b23 | 461 | return ((void *)iod) + iod->offset; |
e025344c SMM |
462 | } |
463 | ||
ac3dd5bd JA |
464 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
465 | unsigned nseg, unsigned long private) | |
eca18b23 | 466 | { |
ac3dd5bd JA |
467 | iod->private = private; |
468 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
469 | iod->npages = -1; | |
470 | iod->length = nbytes; | |
471 | iod->nents = 0; | |
eca18b23 | 472 | } |
b60503ba | 473 | |
eca18b23 | 474 | static struct nvme_iod * |
ac3dd5bd JA |
475 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
476 | unsigned long priv, gfp_t gfp) | |
b60503ba | 477 | { |
eca18b23 | 478 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 479 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
480 | sizeof(struct scatterlist) * nseg, gfp); |
481 | ||
ac3dd5bd JA |
482 | if (iod) |
483 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
484 | |
485 | return iod; | |
b60503ba MW |
486 | } |
487 | ||
ac3dd5bd JA |
488 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
489 | gfp_t gfp) | |
490 | { | |
491 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
492 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
493 | struct nvme_iod *iod; |
494 | ||
495 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
496 | size <= NVME_INT_BYTES(dev)) { | |
497 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
498 | ||
499 | iod = cmd->iod; | |
ac3dd5bd | 500 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 501 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
502 | return iod; |
503 | } | |
504 | ||
505 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
506 | (unsigned long) rq, gfp); | |
507 | } | |
508 | ||
d29ec824 | 509 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 510 | { |
5fd4ce1b | 511 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 MW |
512 | int i; |
513 | __le64 **list = iod_list(iod); | |
514 | dma_addr_t prp_dma = iod->first_dma; | |
515 | ||
516 | if (iod->npages == 0) | |
517 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
518 | for (i = 0; i < iod->npages; i++) { | |
519 | __le64 *prp_list = list[i]; | |
520 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
521 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
522 | prp_dma = next_prp_dma; | |
523 | } | |
ac3dd5bd JA |
524 | |
525 | if (iod_should_kfree(iod)) | |
526 | kfree(iod); | |
b60503ba MW |
527 | } |
528 | ||
52b68d7e | 529 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
530 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
531 | { | |
532 | if (be32_to_cpu(pi->ref_tag) == v) | |
533 | pi->ref_tag = cpu_to_be32(p); | |
534 | } | |
535 | ||
536 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
537 | { | |
538 | if (be32_to_cpu(pi->ref_tag) == p) | |
539 | pi->ref_tag = cpu_to_be32(v); | |
540 | } | |
541 | ||
542 | /** | |
543 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
544 | * | |
545 | * The virtual start sector is the one that was originally submitted by the | |
546 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
547 | * start sector may be different. Remap protection information to match the | |
548 | * physical LBA on writes, and back to the original seed on reads. | |
549 | * | |
550 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
551 | */ | |
552 | static void nvme_dif_remap(struct request *req, | |
553 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
554 | { | |
555 | struct nvme_ns *ns = req->rq_disk->private_data; | |
556 | struct bio_integrity_payload *bip; | |
557 | struct t10_pi_tuple *pi; | |
558 | void *p, *pmap; | |
559 | u32 i, nlb, ts, phys, virt; | |
560 | ||
561 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
562 | return; | |
563 | ||
564 | bip = bio_integrity(req->bio); | |
565 | if (!bip) | |
566 | return; | |
567 | ||
568 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
569 | |
570 | p = pmap; | |
571 | virt = bip_get_seed(bip); | |
572 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
573 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 574 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
575 | |
576 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
577 | pi = (struct t10_pi_tuple *)p; | |
578 | dif_swap(phys, virt, pi); | |
579 | p += ts; | |
580 | } | |
581 | kunmap_atomic(pmap); | |
582 | } | |
52b68d7e KB |
583 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
584 | static void nvme_dif_remap(struct request *req, | |
585 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
586 | { | |
587 | } | |
588 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
589 | { | |
590 | } | |
591 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
592 | { | |
593 | } | |
52b68d7e KB |
594 | #endif |
595 | ||
a4aea562 | 596 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
597 | struct nvme_completion *cqe) |
598 | { | |
eca18b23 | 599 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 600 | struct request *req = iod_get_private(iod); |
a4aea562 | 601 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
b60503ba | 602 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
81c04b94 | 603 | int error = 0; |
b60503ba | 604 | |
edd10d33 | 605 | if (unlikely(status)) { |
a4aea562 MB |
606 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
607 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
608 | unsigned long flags; |
609 | ||
d4f6c3ab CH |
610 | nvme_unmap_data(nvmeq->dev, iod); |
611 | ||
a4aea562 | 612 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
613 | spin_lock_irqsave(req->q->queue_lock, flags); |
614 | if (!blk_queue_stopped(req->q)) | |
615 | blk_mq_kick_requeue_list(req->q); | |
616 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
d4f6c3ab | 617 | return; |
edd10d33 | 618 | } |
f4829a9b | 619 | |
d29ec824 | 620 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
17188bb4 | 621 | if (cmd_rq->ctx == CMD_CTX_CANCELLED) |
81c04b94 CH |
622 | error = -EINTR; |
623 | else | |
624 | error = status; | |
d29ec824 | 625 | } else { |
81c04b94 | 626 | error = nvme_error_status(status); |
d29ec824 | 627 | } |
f4829a9b CH |
628 | } |
629 | ||
a0a931d6 KB |
630 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
631 | u32 result = le32_to_cpup(&cqe->result); | |
632 | req->special = (void *)(uintptr_t)result; | |
633 | } | |
a4aea562 MB |
634 | |
635 | if (cmd_rq->aborted) | |
e75ec752 | 636 | dev_warn(nvmeq->dev->dev, |
a4aea562 | 637 | "completing aborted command with status:%04x\n", |
81c04b94 | 638 | error); |
a4aea562 | 639 | |
d4f6c3ab CH |
640 | nvme_unmap_data(nvmeq->dev, iod); |
641 | blk_mq_complete_request(req, error); | |
b60503ba MW |
642 | } |
643 | ||
69d2b571 CH |
644 | static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
645 | int total_len) | |
ff22b54f | 646 | { |
99802a7a | 647 | struct dma_pool *pool; |
eca18b23 MW |
648 | int length = total_len; |
649 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
650 | int dma_len = sg_dma_len(sg); |
651 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 652 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 653 | int offset = dma_addr & (page_size - 1); |
e025344c | 654 | __le64 *prp_list; |
eca18b23 | 655 | __le64 **list = iod_list(iod); |
e025344c | 656 | dma_addr_t prp_dma; |
eca18b23 | 657 | int nprps, i; |
ff22b54f | 658 | |
1d090624 | 659 | length -= (page_size - offset); |
ff22b54f | 660 | if (length <= 0) |
69d2b571 | 661 | return true; |
ff22b54f | 662 | |
1d090624 | 663 | dma_len -= (page_size - offset); |
ff22b54f | 664 | if (dma_len) { |
1d090624 | 665 | dma_addr += (page_size - offset); |
ff22b54f MW |
666 | } else { |
667 | sg = sg_next(sg); | |
668 | dma_addr = sg_dma_address(sg); | |
669 | dma_len = sg_dma_len(sg); | |
670 | } | |
671 | ||
1d090624 | 672 | if (length <= page_size) { |
edd10d33 | 673 | iod->first_dma = dma_addr; |
69d2b571 | 674 | return true; |
e025344c SMM |
675 | } |
676 | ||
1d090624 | 677 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
678 | if (nprps <= (256 / 8)) { |
679 | pool = dev->prp_small_pool; | |
eca18b23 | 680 | iod->npages = 0; |
99802a7a MW |
681 | } else { |
682 | pool = dev->prp_page_pool; | |
eca18b23 | 683 | iod->npages = 1; |
99802a7a MW |
684 | } |
685 | ||
69d2b571 | 686 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 687 | if (!prp_list) { |
edd10d33 | 688 | iod->first_dma = dma_addr; |
eca18b23 | 689 | iod->npages = -1; |
69d2b571 | 690 | return false; |
b77954cb | 691 | } |
eca18b23 MW |
692 | list[0] = prp_list; |
693 | iod->first_dma = prp_dma; | |
e025344c SMM |
694 | i = 0; |
695 | for (;;) { | |
1d090624 | 696 | if (i == page_size >> 3) { |
e025344c | 697 | __le64 *old_prp_list = prp_list; |
69d2b571 | 698 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 699 | if (!prp_list) |
69d2b571 | 700 | return false; |
eca18b23 | 701 | list[iod->npages++] = prp_list; |
7523d834 MW |
702 | prp_list[0] = old_prp_list[i - 1]; |
703 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
704 | i = 1; | |
e025344c SMM |
705 | } |
706 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
707 | dma_len -= page_size; |
708 | dma_addr += page_size; | |
709 | length -= page_size; | |
e025344c SMM |
710 | if (length <= 0) |
711 | break; | |
712 | if (dma_len > 0) | |
713 | continue; | |
714 | BUG_ON(dma_len < 0); | |
715 | sg = sg_next(sg); | |
716 | dma_addr = sg_dma_address(sg); | |
717 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
718 | } |
719 | ||
69d2b571 | 720 | return true; |
ff22b54f MW |
721 | } |
722 | ||
ba1ca37e CH |
723 | static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, |
724 | struct nvme_command *cmnd) | |
d29ec824 | 725 | { |
ba1ca37e CH |
726 | struct request *req = iod_get_private(iod); |
727 | struct request_queue *q = req->q; | |
728 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
729 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
730 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
731 | ||
732 | sg_init_table(iod->sg, req->nr_phys_segments); | |
733 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
734 | if (!iod->nents) | |
735 | goto out; | |
736 | ||
737 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
738 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
739 | goto out; | |
740 | ||
741 | if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) | |
742 | goto out_unmap; | |
743 | ||
744 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
745 | if (blk_integrity_rq(req)) { | |
746 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
747 | goto out_unmap; | |
748 | ||
749 | sg_init_table(iod->meta_sg, 1); | |
750 | if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) | |
751 | goto out_unmap; | |
d29ec824 | 752 | |
ba1ca37e CH |
753 | if (rq_data_dir(req)) |
754 | nvme_dif_remap(req, nvme_dif_prep); | |
755 | ||
756 | if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) | |
757 | goto out_unmap; | |
d29ec824 CH |
758 | } |
759 | ||
ba1ca37e CH |
760 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
761 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
762 | if (blk_integrity_rq(req)) | |
763 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
764 | return BLK_MQ_RQ_QUEUE_OK; | |
765 | ||
766 | out_unmap: | |
767 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
768 | out: | |
769 | return ret; | |
d29ec824 CH |
770 | } |
771 | ||
d4f6c3ab CH |
772 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) |
773 | { | |
774 | struct request *req = iod_get_private(iod); | |
775 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
776 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
777 | ||
778 | if (iod->nents) { | |
779 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
780 | if (blk_integrity_rq(req)) { | |
781 | if (!rq_data_dir(req)) | |
782 | nvme_dif_remap(req, nvme_dif_complete); | |
783 | dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); | |
784 | } | |
785 | } | |
786 | ||
787 | nvme_free_iod(dev, iod); | |
788 | } | |
789 | ||
a4aea562 MB |
790 | /* |
791 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
792 | * worth having a special pool for these or additional cases to handle freeing | |
793 | * the iod. | |
794 | */ | |
ba1ca37e CH |
795 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
796 | struct nvme_iod *iod, struct nvme_command *cmnd) | |
0e5e4f0e | 797 | { |
ba1ca37e CH |
798 | struct request *req = iod_get_private(iod); |
799 | struct nvme_dsm_range *range; | |
800 | ||
801 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
802 | &iod->first_dma); | |
803 | if (!range) | |
804 | return BLK_MQ_RQ_QUEUE_BUSY; | |
805 | iod_list(iod)[0] = (__le64 *)range; | |
806 | iod->npages = 0; | |
0e5e4f0e | 807 | |
0e5e4f0e | 808 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
809 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
810 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 811 | |
ba1ca37e CH |
812 | memset(cmnd, 0, sizeof(*cmnd)); |
813 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
814 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
815 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
816 | cmnd->dsm.nr = 0; | |
817 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
818 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
819 | } |
820 | ||
d29ec824 CH |
821 | /* |
822 | * NOTE: ns is NULL when called on the admin queue. | |
823 | */ | |
a4aea562 MB |
824 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
825 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 826 | { |
a4aea562 MB |
827 | struct nvme_ns *ns = hctx->queue->queuedata; |
828 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 829 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
830 | struct request *req = bd->rq; |
831 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 832 | struct nvme_iod *iod; |
ba1ca37e CH |
833 | struct nvme_command cmnd; |
834 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 835 | |
e1e5e564 KB |
836 | /* |
837 | * If formated with metadata, require the block layer provide a buffer | |
838 | * unless this namespace is formated such that the metadata can be | |
839 | * stripped/generated by the controller with PRACT=1. | |
840 | */ | |
d29ec824 | 841 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
842 | if (!(ns->pi_type && ns->ms == 8) && |
843 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
f4829a9b | 844 | blk_mq_complete_request(req, -EFAULT); |
e1e5e564 KB |
845 | return BLK_MQ_RQ_QUEUE_OK; |
846 | } | |
847 | } | |
848 | ||
d29ec824 | 849 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 850 | if (!iod) |
fe54303e | 851 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 852 | |
a4aea562 | 853 | if (req->cmd_flags & REQ_DISCARD) { |
ba1ca37e CH |
854 | ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); |
855 | } else { | |
856 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
857 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
858 | else if (req->cmd_flags & REQ_FLUSH) | |
859 | nvme_setup_flush(ns, &cmnd); | |
860 | else | |
861 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 862 | |
ba1ca37e CH |
863 | if (req->nr_phys_segments) |
864 | ret = nvme_map_data(dev, iod, &cmnd); | |
edd10d33 | 865 | } |
1974b1ae | 866 | |
ba1ca37e CH |
867 | if (ret) |
868 | goto out; | |
869 | ||
870 | cmnd.common.command_id = req->tag; | |
9af8785a | 871 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 872 | |
ba1ca37e CH |
873 | spin_lock_irq(&nvmeq->q_lock); |
874 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
875 | nvme_process_cq(nvmeq); |
876 | spin_unlock_irq(&nvmeq->q_lock); | |
877 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 878 | out: |
d29ec824 | 879 | nvme_free_iod(dev, iod); |
ba1ca37e | 880 | return ret; |
b60503ba MW |
881 | } |
882 | ||
a0fa9647 | 883 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 884 | { |
82123460 | 885 | u16 head, phase; |
b60503ba | 886 | |
b60503ba | 887 | head = nvmeq->cq_head; |
82123460 | 888 | phase = nvmeq->cq_phase; |
b60503ba MW |
889 | |
890 | for (;;) { | |
c2f5b650 MW |
891 | void *ctx; |
892 | nvme_completion_fn fn; | |
b60503ba | 893 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 894 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
895 | break; |
896 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
897 | if (++head == nvmeq->q_depth) { | |
898 | head = 0; | |
82123460 | 899 | phase = !phase; |
b60503ba | 900 | } |
a0fa9647 JA |
901 | if (tag && *tag == cqe.command_id) |
902 | *tag = -1; | |
a4aea562 | 903 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 904 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
905 | } |
906 | ||
907 | /* If the controller ignores the cq head doorbell and continuously | |
908 | * writes to the queue, it is theoretically possible to wrap around | |
909 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
910 | * requires that 0.1% of your interrupts are handled, so this isn't | |
911 | * a big problem. | |
912 | */ | |
82123460 | 913 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 914 | return; |
b60503ba | 915 | |
604e8c8d KB |
916 | if (likely(nvmeq->cq_vector >= 0)) |
917 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 918 | nvmeq->cq_head = head; |
82123460 | 919 | nvmeq->cq_phase = phase; |
b60503ba | 920 | |
e9539f47 | 921 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
922 | } |
923 | ||
924 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
925 | { | |
926 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
927 | } |
928 | ||
929 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
930 | { |
931 | irqreturn_t result; | |
932 | struct nvme_queue *nvmeq = data; | |
933 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
934 | nvme_process_cq(nvmeq); |
935 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
936 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
937 | spin_unlock(&nvmeq->q_lock); |
938 | return result; | |
939 | } | |
940 | ||
941 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
942 | { | |
943 | struct nvme_queue *nvmeq = data; | |
944 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
945 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
946 | return IRQ_NONE; | |
947 | return IRQ_WAKE_THREAD; | |
948 | } | |
949 | ||
a0fa9647 JA |
950 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
951 | { | |
952 | struct nvme_queue *nvmeq = hctx->driver_data; | |
953 | ||
954 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
955 | nvmeq->cq_phase) { | |
956 | spin_lock_irq(&nvmeq->q_lock); | |
957 | __nvme_process_cq(nvmeq, &tag); | |
958 | spin_unlock_irq(&nvmeq->q_lock); | |
959 | ||
960 | if (tag == -1) | |
961 | return 1; | |
962 | } | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
a4aea562 MB |
967 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
968 | { | |
969 | struct nvme_queue *nvmeq = dev->queues[0]; | |
970 | struct nvme_command c; | |
971 | struct nvme_cmd_info *cmd_info; | |
972 | struct request *req; | |
973 | ||
1c63dc66 | 974 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 975 | BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); |
9f173b33 DC |
976 | if (IS_ERR(req)) |
977 | return PTR_ERR(req); | |
a4aea562 | 978 | |
c917dfe5 | 979 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 980 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 981 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
982 | |
983 | memset(&c, 0, sizeof(c)); | |
984 | c.common.opcode = nvme_admin_async_event; | |
985 | c.common.command_id = req->tag; | |
986 | ||
42483228 | 987 | blk_mq_free_request(req); |
e3f879bf SB |
988 | __nvme_submit_cmd(nvmeq, &c); |
989 | return 0; | |
a4aea562 MB |
990 | } |
991 | ||
992 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
993 | struct nvme_command *cmd, |
994 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
995 | { | |
a4aea562 MB |
996 | struct nvme_queue *nvmeq = dev->queues[0]; |
997 | struct request *req; | |
998 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 999 | |
1c63dc66 | 1000 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); |
9f173b33 DC |
1001 | if (IS_ERR(req)) |
1002 | return PTR_ERR(req); | |
a4aea562 MB |
1003 | |
1004 | req->timeout = timeout; | |
1005 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1006 | cmdinfo->req = req; | |
1007 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1008 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1009 | |
1010 | cmd->common.command_id = req->tag; | |
1011 | ||
e3f879bf SB |
1012 | nvme_submit_cmd(nvmeq, cmd); |
1013 | return 0; | |
4d115420 KB |
1014 | } |
1015 | ||
b60503ba MW |
1016 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1017 | { | |
b60503ba MW |
1018 | struct nvme_command c; |
1019 | ||
1020 | memset(&c, 0, sizeof(c)); | |
1021 | c.delete_queue.opcode = opcode; | |
1022 | c.delete_queue.qid = cpu_to_le16(id); | |
1023 | ||
1c63dc66 | 1024 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1025 | } |
1026 | ||
1027 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1028 | struct nvme_queue *nvmeq) | |
1029 | { | |
b60503ba MW |
1030 | struct nvme_command c; |
1031 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1032 | ||
d29ec824 CH |
1033 | /* |
1034 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1035 | * is attached to the request. | |
1036 | */ | |
b60503ba MW |
1037 | memset(&c, 0, sizeof(c)); |
1038 | c.create_cq.opcode = nvme_admin_create_cq; | |
1039 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1040 | c.create_cq.cqid = cpu_to_le16(qid); | |
1041 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1042 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1043 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1044 | ||
1c63dc66 | 1045 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1046 | } |
1047 | ||
1048 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1049 | struct nvme_queue *nvmeq) | |
1050 | { | |
b60503ba MW |
1051 | struct nvme_command c; |
1052 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1053 | ||
d29ec824 CH |
1054 | /* |
1055 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1056 | * is attached to the request. | |
1057 | */ | |
b60503ba MW |
1058 | memset(&c, 0, sizeof(c)); |
1059 | c.create_sq.opcode = nvme_admin_create_sq; | |
1060 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1061 | c.create_sq.sqid = cpu_to_le16(qid); | |
1062 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1063 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1064 | c.create_sq.cqid = cpu_to_le16(qid); | |
1065 | ||
1c63dc66 | 1066 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1067 | } |
1068 | ||
1069 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1070 | { | |
1071 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1072 | } | |
1073 | ||
1074 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1075 | { | |
1076 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1077 | } | |
1078 | ||
c30341dc | 1079 | /** |
a4aea562 | 1080 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1081 | * |
1082 | * Schedule controller reset if the command was already aborted once before and | |
1083 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1084 | */ | |
a4aea562 | 1085 | static void nvme_abort_req(struct request *req) |
c30341dc | 1086 | { |
a4aea562 MB |
1087 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1088 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1089 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1090 | struct request *abort_req; |
1091 | struct nvme_cmd_info *abort_cmd; | |
1092 | struct nvme_command cmd; | |
c30341dc | 1093 | |
a4aea562 | 1094 | if (!nvmeq->qid || cmd_rq->aborted) { |
90667892 CH |
1095 | spin_lock(&dev_list_lock); |
1096 | if (!__nvme_reset(dev)) { | |
1097 | dev_warn(dev->dev, | |
1098 | "I/O %d QID %d timeout, reset controller\n", | |
1099 | req->tag, nvmeq->qid); | |
1100 | } | |
1101 | spin_unlock(&dev_list_lock); | |
c30341dc KB |
1102 | return; |
1103 | } | |
1104 | ||
1c63dc66 | 1105 | if (!dev->ctrl.abort_limit) |
c30341dc KB |
1106 | return; |
1107 | ||
1c63dc66 | 1108 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1109 | BLK_MQ_REQ_NOWAIT); |
9f173b33 | 1110 | if (IS_ERR(abort_req)) |
c30341dc KB |
1111 | return; |
1112 | ||
a4aea562 MB |
1113 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1114 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1115 | ||
c30341dc KB |
1116 | memset(&cmd, 0, sizeof(cmd)); |
1117 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1118 | cmd.abort.cid = req->tag; |
c30341dc | 1119 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1120 | cmd.abort.command_id = abort_req->tag; |
c30341dc | 1121 | |
1c63dc66 | 1122 | --dev->ctrl.abort_limit; |
a4aea562 | 1123 | cmd_rq->aborted = 1; |
c30341dc | 1124 | |
a4aea562 | 1125 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1126 | nvmeq->qid); |
e3f879bf | 1127 | nvme_submit_cmd(dev->queues[0], &cmd); |
c30341dc KB |
1128 | } |
1129 | ||
42483228 | 1130 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1131 | { |
a4aea562 MB |
1132 | struct nvme_queue *nvmeq = data; |
1133 | void *ctx; | |
1134 | nvme_completion_fn fn; | |
1135 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1136 | struct nvme_completion cqe; |
1137 | ||
1138 | if (!blk_mq_request_started(req)) | |
1139 | return; | |
a09115b2 | 1140 | |
a4aea562 | 1141 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1142 | |
a4aea562 MB |
1143 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1144 | return; | |
1145 | ||
cef6a948 KB |
1146 | if (blk_queue_dying(req->q)) |
1147 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1148 | else | |
1149 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1150 | ||
1151 | ||
a4aea562 MB |
1152 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1153 | req->tag, nvmeq->qid); | |
1154 | ctx = cancel_cmd_info(cmd, &fn); | |
1155 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1156 | } |
1157 | ||
a4aea562 | 1158 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1159 | { |
a4aea562 MB |
1160 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1161 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1162 | ||
1163 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1164 | nvmeq->qid); | |
7a509a6b | 1165 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1166 | nvme_abort_req(req); |
7a509a6b | 1167 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1168 | |
07836e65 KB |
1169 | /* |
1170 | * The aborted req will be completed on receiving the abort req. | |
1171 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1172 | * as the device then is in a faulty state. | |
1173 | */ | |
1174 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1175 | } |
22404274 | 1176 | |
a4aea562 MB |
1177 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1178 | { | |
9e866774 MW |
1179 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1180 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1181 | if (nvmeq->sq_cmds) |
1182 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1183 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1184 | kfree(nvmeq); | |
1185 | } | |
1186 | ||
a1a5ef99 | 1187 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1188 | { |
1189 | int i; | |
1190 | ||
a1a5ef99 | 1191 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1192 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1193 | dev->queue_count--; |
a4aea562 | 1194 | dev->queues[i] = NULL; |
f435c282 | 1195 | nvme_free_queue(nvmeq); |
121c7ad4 | 1196 | } |
22404274 KB |
1197 | } |
1198 | ||
4d115420 KB |
1199 | /** |
1200 | * nvme_suspend_queue - put queue into suspended state | |
1201 | * @nvmeq - queue to suspend | |
4d115420 KB |
1202 | */ |
1203 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1204 | { |
2b25d981 | 1205 | int vector; |
b60503ba | 1206 | |
a09115b2 | 1207 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1208 | if (nvmeq->cq_vector == -1) { |
1209 | spin_unlock_irq(&nvmeq->q_lock); | |
1210 | return 1; | |
1211 | } | |
1212 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1213 | nvmeq->dev->online_queues--; |
2b25d981 | 1214 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1215 | spin_unlock_irq(&nvmeq->q_lock); |
1216 | ||
1c63dc66 CH |
1217 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1218 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1219 | |
aba2080f MW |
1220 | irq_set_affinity_hint(vector, NULL); |
1221 | free_irq(vector, nvmeq); | |
b60503ba | 1222 | |
4d115420 KB |
1223 | return 0; |
1224 | } | |
b60503ba | 1225 | |
4d115420 KB |
1226 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1227 | { | |
22404274 | 1228 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1229 | if (nvmeq->tags && *nvmeq->tags) |
1230 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1231 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1232 | } |
1233 | ||
4d115420 KB |
1234 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1235 | { | |
a4aea562 | 1236 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1237 | |
1238 | if (!nvmeq) | |
1239 | return; | |
1240 | if (nvme_suspend_queue(nvmeq)) | |
1241 | return; | |
1242 | ||
0e53d180 KB |
1243 | /* Don't tell the adapter to delete the admin queue. |
1244 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1245 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1246 | adapter_delete_sq(dev, qid); |
1247 | adapter_delete_cq(dev, qid); | |
1248 | } | |
07836e65 KB |
1249 | |
1250 | spin_lock_irq(&nvmeq->q_lock); | |
1251 | nvme_process_cq(nvmeq); | |
1252 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1253 | } |
1254 | ||
8ffaadf7 JD |
1255 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1256 | int entry_size) | |
1257 | { | |
1258 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1259 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1260 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1261 | |
1262 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1263 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1264 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1265 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1266 | |
1267 | /* | |
1268 | * Ensure the reduced q_depth is above some threshold where it | |
1269 | * would be better to map queues in system memory with the | |
1270 | * original depth | |
1271 | */ | |
1272 | if (q_depth < 64) | |
1273 | return -ENOMEM; | |
1274 | } | |
1275 | ||
1276 | return q_depth; | |
1277 | } | |
1278 | ||
1279 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1280 | int qid, int depth) | |
1281 | { | |
1282 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1283 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1284 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1285 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1286 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1287 | } else { | |
1288 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1289 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1290 | if (!nvmeq->sq_cmds) | |
1291 | return -ENOMEM; | |
1292 | } | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
b60503ba | 1297 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1298 | int depth) |
b60503ba | 1299 | { |
a4aea562 | 1300 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1301 | if (!nvmeq) |
1302 | return NULL; | |
1303 | ||
e75ec752 | 1304 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1305 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1306 | if (!nvmeq->cqes) |
1307 | goto free_nvmeq; | |
b60503ba | 1308 | |
8ffaadf7 | 1309 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1310 | goto free_cqdma; |
1311 | ||
e75ec752 | 1312 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1313 | nvmeq->dev = dev; |
3193f07b | 1314 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1315 | dev->ctrl.instance, qid); |
b60503ba MW |
1316 | spin_lock_init(&nvmeq->q_lock); |
1317 | nvmeq->cq_head = 0; | |
82123460 | 1318 | nvmeq->cq_phase = 1; |
b80d5ccc | 1319 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1320 | nvmeq->q_depth = depth; |
c30341dc | 1321 | nvmeq->qid = qid; |
758dd7fd | 1322 | nvmeq->cq_vector = -1; |
a4aea562 | 1323 | dev->queues[qid] = nvmeq; |
b60503ba | 1324 | |
36a7e993 JD |
1325 | /* make sure queue descriptor is set before queue count, for kthread */ |
1326 | mb(); | |
1327 | dev->queue_count++; | |
1328 | ||
b60503ba MW |
1329 | return nvmeq; |
1330 | ||
1331 | free_cqdma: | |
e75ec752 | 1332 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1333 | nvmeq->cq_dma_addr); |
1334 | free_nvmeq: | |
1335 | kfree(nvmeq); | |
1336 | return NULL; | |
1337 | } | |
1338 | ||
3001082c MW |
1339 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1340 | const char *name) | |
1341 | { | |
58ffacb5 MW |
1342 | if (use_threaded_interrupts) |
1343 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1344 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1345 | name, nvmeq); |
3001082c | 1346 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1347 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1348 | } |
1349 | ||
22404274 | 1350 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1351 | { |
22404274 | 1352 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1353 | |
7be50e93 | 1354 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1355 | nvmeq->sq_tail = 0; |
1356 | nvmeq->cq_head = 0; | |
1357 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1358 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1359 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1360 | dev->online_queues++; |
7be50e93 | 1361 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1362 | } |
1363 | ||
1364 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1365 | { | |
1366 | struct nvme_dev *dev = nvmeq->dev; | |
1367 | int result; | |
3f85d50b | 1368 | |
2b25d981 | 1369 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1370 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1371 | if (result < 0) | |
22404274 | 1372 | return result; |
b60503ba MW |
1373 | |
1374 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1375 | if (result < 0) | |
1376 | goto release_cq; | |
1377 | ||
3193f07b | 1378 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1379 | if (result < 0) |
1380 | goto release_sq; | |
1381 | ||
22404274 | 1382 | nvme_init_queue(nvmeq, qid); |
22404274 | 1383 | return result; |
b60503ba MW |
1384 | |
1385 | release_sq: | |
1386 | adapter_delete_sq(dev, qid); | |
1387 | release_cq: | |
1388 | adapter_delete_cq(dev, qid); | |
22404274 | 1389 | return result; |
b60503ba MW |
1390 | } |
1391 | ||
a4aea562 | 1392 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1393 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1394 | .map_queue = blk_mq_map_queue, |
1395 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1396 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1397 | .init_request = nvme_admin_init_request, |
1398 | .timeout = nvme_timeout, | |
1399 | }; | |
1400 | ||
1401 | static struct blk_mq_ops nvme_mq_ops = { | |
1402 | .queue_rq = nvme_queue_rq, | |
1403 | .map_queue = blk_mq_map_queue, | |
1404 | .init_hctx = nvme_init_hctx, | |
1405 | .init_request = nvme_init_request, | |
1406 | .timeout = nvme_timeout, | |
a0fa9647 | 1407 | .poll = nvme_poll, |
a4aea562 MB |
1408 | }; |
1409 | ||
ea191d2f KB |
1410 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1411 | { | |
1c63dc66 CH |
1412 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1413 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1414 | blk_mq_free_tag_set(&dev->admin_tagset); |
1415 | } | |
1416 | } | |
1417 | ||
a4aea562 MB |
1418 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1419 | { | |
1c63dc66 | 1420 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1421 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1422 | dev->admin_tagset.nr_hw_queues = 1; | |
1423 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1424 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1425 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1426 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1427 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1428 | dev->admin_tagset.driver_data = dev; |
1429 | ||
1430 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1431 | return -ENOMEM; | |
1432 | ||
1c63dc66 CH |
1433 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1434 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1435 | blk_mq_free_tag_set(&dev->admin_tagset); |
1436 | return -ENOMEM; | |
1437 | } | |
1c63dc66 | 1438 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1439 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1440 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1441 | return -ENODEV; |
1442 | } | |
0fb59cbc | 1443 | } else |
1c63dc66 | 1444 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
8d85fce7 | 1449 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1450 | { |
ba47e386 | 1451 | int result; |
b60503ba | 1452 | u32 aqa; |
7a67cbea | 1453 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1454 | struct nvme_queue *nvmeq; |
1455 | ||
7a67cbea | 1456 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1457 | NVME_CAP_NSSRC(cap) : 0; |
1458 | ||
7a67cbea CH |
1459 | if (dev->subsystem && |
1460 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1461 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1462 | |
5fd4ce1b | 1463 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1464 | if (result < 0) |
1465 | return result; | |
b60503ba | 1466 | |
a4aea562 | 1467 | nvmeq = dev->queues[0]; |
cd638946 | 1468 | if (!nvmeq) { |
2b25d981 | 1469 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1470 | if (!nvmeq) |
1471 | return -ENOMEM; | |
cd638946 | 1472 | } |
b60503ba MW |
1473 | |
1474 | aqa = nvmeq->q_depth - 1; | |
1475 | aqa |= aqa << 16; | |
1476 | ||
7a67cbea CH |
1477 | writel(aqa, dev->bar + NVME_REG_AQA); |
1478 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1479 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1480 | |
5fd4ce1b | 1481 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1482 | if (result) |
a4aea562 MB |
1483 | goto free_nvmeq; |
1484 | ||
2b25d981 | 1485 | nvmeq->cq_vector = 0; |
3193f07b | 1486 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1487 | if (result) { |
1488 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1489 | goto free_nvmeq; |
758dd7fd | 1490 | } |
025c557a | 1491 | |
b60503ba | 1492 | return result; |
a4aea562 | 1493 | |
a4aea562 MB |
1494 | free_nvmeq: |
1495 | nvme_free_queues(dev, 0); | |
1496 | return result; | |
b60503ba MW |
1497 | } |
1498 | ||
1fa6aead MW |
1499 | static int nvme_kthread(void *data) |
1500 | { | |
d4b4ff8e | 1501 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1502 | |
1503 | while (!kthread_should_stop()) { | |
564a232c | 1504 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1505 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1506 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1507 | int i; |
7a67cbea | 1508 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 KB |
1509 | |
1510 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
1511 | csts & NVME_CSTS_CFS) { | |
90667892 CH |
1512 | if (!__nvme_reset(dev)) { |
1513 | dev_warn(dev->dev, | |
1514 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1515 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1516 | } |
d4b4ff8e KB |
1517 | continue; |
1518 | } | |
1fa6aead | 1519 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1520 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1521 | if (!nvmeq) |
1522 | continue; | |
1fa6aead | 1523 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1524 | nvme_process_cq(nvmeq); |
6fccf938 | 1525 | |
1c63dc66 | 1526 | while (i == 0 && dev->ctrl.event_limit > 0) { |
a4aea562 | 1527 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 | 1528 | break; |
1c63dc66 | 1529 | dev->ctrl.event_limit--; |
6fccf938 | 1530 | } |
1fa6aead MW |
1531 | spin_unlock_irq(&nvmeq->q_lock); |
1532 | } | |
1533 | } | |
1534 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1535 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1536 | } |
1537 | return 0; | |
1538 | } | |
1539 | ||
2659e57b CH |
1540 | /* |
1541 | * Create I/O queues. Failing to create an I/O queue is not an issue, | |
1542 | * we can continue with less than the desired amount of queues, and | |
1543 | * even a controller without I/O queues an still be used to issue | |
1544 | * admin commands. This might be useful to upgrade a buggy firmware | |
1545 | * for example. | |
1546 | */ | |
42f61420 KB |
1547 | static void nvme_create_io_queues(struct nvme_dev *dev) |
1548 | { | |
a4aea562 | 1549 | unsigned i; |
42f61420 | 1550 | |
a4aea562 | 1551 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 1552 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
1553 | break; |
1554 | ||
a4aea562 | 1555 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2659e57b CH |
1556 | if (nvme_create_queue(dev->queues[i], i)) { |
1557 | nvme_free_queues(dev, i); | |
42f61420 | 1558 | break; |
2659e57b | 1559 | } |
42f61420 KB |
1560 | } |
1561 | ||
8ffaadf7 JD |
1562 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1563 | { | |
1564 | u64 szu, size, offset; | |
1565 | u32 cmbloc; | |
1566 | resource_size_t bar_size; | |
1567 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1568 | void __iomem *cmb; | |
1569 | dma_addr_t dma_addr; | |
1570 | ||
1571 | if (!use_cmb_sqes) | |
1572 | return NULL; | |
1573 | ||
7a67cbea | 1574 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1575 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1576 | return NULL; | |
1577 | ||
7a67cbea | 1578 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1579 | |
1580 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1581 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1582 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1583 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1584 | ||
1585 | if (offset > bar_size) | |
1586 | return NULL; | |
1587 | ||
1588 | /* | |
1589 | * Controllers may support a CMB size larger than their BAR, | |
1590 | * for example, due to being behind a bridge. Reduce the CMB to | |
1591 | * the reported size of the BAR | |
1592 | */ | |
1593 | if (size > bar_size - offset) | |
1594 | size = bar_size - offset; | |
1595 | ||
1596 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1597 | cmb = ioremap_wc(dma_addr, size); | |
1598 | if (!cmb) | |
1599 | return NULL; | |
1600 | ||
1601 | dev->cmb_dma_addr = dma_addr; | |
1602 | dev->cmb_size = size; | |
1603 | return cmb; | |
1604 | } | |
1605 | ||
1606 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1607 | { | |
1608 | if (dev->cmb) { | |
1609 | iounmap(dev->cmb); | |
1610 | dev->cmb = NULL; | |
1611 | } | |
1612 | } | |
1613 | ||
9d713c2b KB |
1614 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1615 | { | |
b80d5ccc | 1616 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1617 | } |
1618 | ||
8d85fce7 | 1619 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1620 | { |
a4aea562 | 1621 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1622 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1623 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1624 | |
42f61420 | 1625 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1626 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1627 | if (result < 0) | |
1b23484b | 1628 | return result; |
9a0be7ab CH |
1629 | |
1630 | /* | |
1631 | * Degraded controllers might return an error when setting the queue | |
1632 | * count. We still want to be able to bring them online and offer | |
1633 | * access to the admin queue, as that might be only way to fix them up. | |
1634 | */ | |
1635 | if (result > 0) { | |
1636 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1637 | nr_io_queues = 0; | |
1638 | result = 0; | |
1639 | } | |
b60503ba | 1640 | |
8ffaadf7 JD |
1641 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1642 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1643 | sizeof(struct nvme_command)); | |
1644 | if (result > 0) | |
1645 | dev->q_depth = result; | |
1646 | else | |
1647 | nvme_release_cmb(dev); | |
1648 | } | |
1649 | ||
9d713c2b KB |
1650 | size = db_bar_size(dev, nr_io_queues); |
1651 | if (size > 8192) { | |
f1938f6e | 1652 | iounmap(dev->bar); |
9d713c2b KB |
1653 | do { |
1654 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1655 | if (dev->bar) | |
1656 | break; | |
1657 | if (!--nr_io_queues) | |
1658 | return -ENOMEM; | |
1659 | size = db_bar_size(dev, nr_io_queues); | |
1660 | } while (1); | |
7a67cbea | 1661 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1662 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1663 | } |
1664 | ||
9d713c2b | 1665 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1666 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1667 | |
e32efbfc JA |
1668 | /* |
1669 | * If we enable msix early due to not intx, disable it again before | |
1670 | * setting up the full range we need. | |
1671 | */ | |
1672 | if (!pdev->irq) | |
1673 | pci_disable_msix(pdev); | |
1674 | ||
be577fab | 1675 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1676 | dev->entry[i].entry = i; |
be577fab AG |
1677 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1678 | if (vecs < 0) { | |
1679 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1680 | if (vecs < 0) { | |
1681 | vecs = 1; | |
1682 | } else { | |
1683 | for (i = 0; i < vecs; i++) | |
1684 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1685 | } |
1686 | } | |
1687 | ||
063a8096 MW |
1688 | /* |
1689 | * Should investigate if there's a performance win from allocating | |
1690 | * more queues than interrupt vectors; it might allow the submission | |
1691 | * path to scale better, even if the receive path is limited by the | |
1692 | * number of interrupts. | |
1693 | */ | |
1694 | nr_io_queues = vecs; | |
42f61420 | 1695 | dev->max_qid = nr_io_queues; |
063a8096 | 1696 | |
3193f07b | 1697 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1698 | if (result) { |
1699 | adminq->cq_vector = -1; | |
22404274 | 1700 | goto free_queues; |
758dd7fd | 1701 | } |
1b23484b | 1702 | |
cd638946 | 1703 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1704 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 1705 | nvme_create_io_queues(dev); |
9ecdc946 | 1706 | |
22404274 | 1707 | return 0; |
b60503ba | 1708 | |
22404274 | 1709 | free_queues: |
a1a5ef99 | 1710 | nvme_free_queues(dev, 1); |
22404274 | 1711 | return result; |
b60503ba MW |
1712 | } |
1713 | ||
bda4e0fb KB |
1714 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1715 | { | |
1716 | struct nvme_queue *nvmeq; | |
1717 | int i; | |
1718 | ||
1719 | for (i = 0; i < dev->online_queues; i++) { | |
1720 | nvmeq = dev->queues[i]; | |
1721 | ||
1722 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1723 | continue; | |
1724 | ||
1725 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1726 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1727 | } | |
1728 | } | |
1729 | ||
a5768aa8 KB |
1730 | static void nvme_dev_scan(struct work_struct *work) |
1731 | { | |
1732 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1733 | |
1734 | if (!dev->tagset.tags) | |
1735 | return; | |
5bae7f73 | 1736 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1737 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1738 | } |
1739 | ||
422ef0c7 MW |
1740 | /* |
1741 | * Return: error value if an error occurred setting up the queues or calling | |
1742 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1743 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1744 | * failures should be reported. | |
1745 | */ | |
8d85fce7 | 1746 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1747 | { |
5bae7f73 | 1748 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1749 | dev->tagset.ops = &nvme_mq_ops; |
1750 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1751 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1752 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1753 | dev->tagset.queue_depth = | |
a4aea562 | 1754 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1755 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1756 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1757 | dev->tagset.driver_data = dev; | |
b60503ba | 1758 | |
ffe7704d KB |
1759 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1760 | return 0; | |
5bae7f73 | 1761 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1762 | } |
a5768aa8 | 1763 | schedule_work(&dev->scan_work); |
e1e5e564 | 1764 | return 0; |
b60503ba MW |
1765 | } |
1766 | ||
0877cb0d KB |
1767 | static int nvme_dev_map(struct nvme_dev *dev) |
1768 | { | |
42f61420 | 1769 | u64 cap; |
0877cb0d | 1770 | int bars, result = -ENOMEM; |
e75ec752 | 1771 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1772 | |
1773 | if (pci_enable_device_mem(pdev)) | |
1774 | return result; | |
1775 | ||
1776 | dev->entry[0].vector = pdev->irq; | |
1777 | pci_set_master(pdev); | |
1778 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1779 | if (!bars) |
1780 | goto disable_pci; | |
1781 | ||
0877cb0d KB |
1782 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1783 | goto disable_pci; | |
1784 | ||
e75ec752 CH |
1785 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1786 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1787 | goto disable; |
0877cb0d | 1788 | |
0877cb0d KB |
1789 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1790 | if (!dev->bar) | |
1791 | goto disable; | |
e32efbfc | 1792 | |
7a67cbea | 1793 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1794 | result = -ENODEV; |
1795 | goto unmap; | |
1796 | } | |
e32efbfc JA |
1797 | |
1798 | /* | |
1799 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1800 | * MSIX vec for setup. We'll adjust this later. | |
1801 | */ | |
1802 | if (!pdev->irq) { | |
1803 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1804 | if (result < 0) | |
1805 | goto unmap; | |
1806 | } | |
1807 | ||
7a67cbea CH |
1808 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1809 | ||
42f61420 KB |
1810 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1811 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1812 | dev->dbs = dev->bar + 4096; |
1813 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1814 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
1815 | |
1816 | return 0; | |
1817 | ||
0e53d180 KB |
1818 | unmap: |
1819 | iounmap(dev->bar); | |
1820 | dev->bar = NULL; | |
0877cb0d KB |
1821 | disable: |
1822 | pci_release_regions(pdev); | |
1823 | disable_pci: | |
1824 | pci_disable_device(pdev); | |
1825 | return result; | |
1826 | } | |
1827 | ||
1828 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1829 | { | |
e75ec752 CH |
1830 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1831 | ||
1832 | if (pdev->msi_enabled) | |
1833 | pci_disable_msi(pdev); | |
1834 | else if (pdev->msix_enabled) | |
1835 | pci_disable_msix(pdev); | |
0877cb0d KB |
1836 | |
1837 | if (dev->bar) { | |
1838 | iounmap(dev->bar); | |
1839 | dev->bar = NULL; | |
e75ec752 | 1840 | pci_release_regions(pdev); |
0877cb0d KB |
1841 | } |
1842 | ||
e75ec752 CH |
1843 | if (pci_is_enabled(pdev)) |
1844 | pci_disable_device(pdev); | |
0877cb0d KB |
1845 | } |
1846 | ||
4d115420 KB |
1847 | struct nvme_delq_ctx { |
1848 | struct task_struct *waiter; | |
1849 | struct kthread_worker *worker; | |
1850 | atomic_t refcount; | |
1851 | }; | |
1852 | ||
1853 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
1854 | { | |
1855 | dq->waiter = current; | |
1856 | mb(); | |
1857 | ||
1858 | for (;;) { | |
1859 | set_current_state(TASK_KILLABLE); | |
1860 | if (!atomic_read(&dq->refcount)) | |
1861 | break; | |
1862 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
1863 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
1864 | /* |
1865 | * Disable the controller first since we can't trust it | |
1866 | * at this point, but leave the admin queue enabled | |
1867 | * until all queue deletion requests are flushed. | |
1868 | * FIXME: This may take a while if there are more h/w | |
1869 | * queues than admin tags. | |
1870 | */ | |
4d115420 | 1871 | set_current_state(TASK_RUNNING); |
5fd4ce1b | 1872 | nvme_disable_ctrl(&dev->ctrl, |
7a67cbea | 1873 | lo_hi_readq(dev->bar + NVME_REG_CAP)); |
0fb59cbc | 1874 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 1875 | flush_kthread_worker(dq->worker); |
0fb59cbc | 1876 | nvme_disable_queue(dev, 0); |
4d115420 KB |
1877 | return; |
1878 | } | |
1879 | } | |
1880 | set_current_state(TASK_RUNNING); | |
1881 | } | |
1882 | ||
1883 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
1884 | { | |
1885 | atomic_dec(&dq->refcount); | |
1886 | if (dq->waiter) | |
1887 | wake_up_process(dq->waiter); | |
1888 | } | |
1889 | ||
1890 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
1891 | { | |
1892 | atomic_inc(&dq->refcount); | |
1893 | return dq; | |
1894 | } | |
1895 | ||
1896 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
1897 | { | |
1898 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 1899 | nvme_put_dq(dq); |
604e8c8d KB |
1900 | |
1901 | spin_lock_irq(&nvmeq->q_lock); | |
1902 | nvme_process_cq(nvmeq); | |
1903 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
1904 | } |
1905 | ||
1906 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
1907 | kthread_work_func_t fn) | |
1908 | { | |
1909 | struct nvme_command c; | |
1910 | ||
1911 | memset(&c, 0, sizeof(c)); | |
1912 | c.delete_queue.opcode = opcode; | |
1913 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1914 | ||
1915 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
1916 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
1917 | ADMIN_TIMEOUT); | |
4d115420 KB |
1918 | } |
1919 | ||
1920 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
1921 | { | |
1922 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1923 | cmdinfo.work); | |
1924 | nvme_del_queue_end(nvmeq); | |
1925 | } | |
1926 | ||
1927 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
1928 | { | |
1929 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
1930 | nvme_del_cq_work_handler); | |
1931 | } | |
1932 | ||
1933 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
1934 | { | |
1935 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1936 | cmdinfo.work); | |
1937 | int status = nvmeq->cmdinfo.status; | |
1938 | ||
1939 | if (!status) | |
1940 | status = nvme_delete_cq(nvmeq); | |
1941 | if (status) | |
1942 | nvme_del_queue_end(nvmeq); | |
1943 | } | |
1944 | ||
1945 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
1946 | { | |
1947 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
1948 | nvme_del_sq_work_handler); | |
1949 | } | |
1950 | ||
1951 | static void nvme_del_queue_start(struct kthread_work *work) | |
1952 | { | |
1953 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1954 | cmdinfo.work); | |
4d115420 KB |
1955 | if (nvme_delete_sq(nvmeq)) |
1956 | nvme_del_queue_end(nvmeq); | |
1957 | } | |
1958 | ||
1959 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1960 | { | |
1961 | int i; | |
1962 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
1963 | struct nvme_delq_ctx dq; | |
1964 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 1965 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
1966 | |
1967 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 1968 | dev_err(dev->dev, |
4d115420 KB |
1969 | "Failed to create queue del task\n"); |
1970 | for (i = dev->queue_count - 1; i > 0; i--) | |
1971 | nvme_disable_queue(dev, i); | |
1972 | return; | |
1973 | } | |
1974 | ||
1975 | dq.waiter = NULL; | |
1976 | atomic_set(&dq.refcount, 0); | |
1977 | dq.worker = &worker; | |
1978 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 1979 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
1980 | |
1981 | if (nvme_suspend_queue(nvmeq)) | |
1982 | continue; | |
1983 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
1984 | nvmeq->cmdinfo.worker = dq.worker; | |
1985 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
1986 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
1987 | } | |
1988 | nvme_wait_dq(&dq, dev); | |
1989 | kthread_stop(kworker_task); | |
1990 | } | |
1991 | ||
b9afca3e DM |
1992 | /* |
1993 | * Remove the node from the device list and check | |
1994 | * for whether or not we need to stop the nvme_thread. | |
1995 | */ | |
1996 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1997 | { | |
1998 | struct task_struct *tmp = NULL; | |
1999 | ||
2000 | spin_lock(&dev_list_lock); | |
2001 | list_del_init(&dev->node); | |
2002 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2003 | tmp = nvme_thread; | |
2004 | nvme_thread = NULL; | |
2005 | } | |
2006 | spin_unlock(&dev_list_lock); | |
2007 | ||
2008 | if (tmp) | |
2009 | kthread_stop(tmp); | |
2010 | } | |
2011 | ||
c9d3bf88 KB |
2012 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2013 | { | |
2014 | struct nvme_ns *ns; | |
2015 | ||
5bae7f73 | 2016 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
2017 | blk_mq_freeze_queue_start(ns->queue); |
2018 | ||
cddcd72b | 2019 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2020 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2021 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2022 | |
2023 | blk_mq_cancel_requeue_work(ns->queue); | |
2024 | blk_mq_stop_hw_queues(ns->queue); | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2029 | { | |
2030 | struct nvme_ns *ns; | |
2031 | ||
5bae7f73 | 2032 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
2033 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); |
2034 | blk_mq_unfreeze_queue(ns->queue); | |
2035 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2036 | blk_mq_kick_requeue_list(ns->queue); | |
2037 | } | |
2038 | } | |
2039 | ||
f0b50732 | 2040 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2041 | { |
22404274 | 2042 | int i; |
7c1b2450 | 2043 | u32 csts = -1; |
22404274 | 2044 | |
b9afca3e | 2045 | nvme_dev_list_remove(dev); |
1fa6aead | 2046 | |
c9d3bf88 KB |
2047 | if (dev->bar) { |
2048 | nvme_freeze_queues(dev); | |
7a67cbea | 2049 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 2050 | } |
7c1b2450 | 2051 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2052 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2053 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2054 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2055 | } |
2056 | } else { | |
2057 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 2058 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
2059 | nvme_disable_queue(dev, 0); |
2060 | } | |
f0b50732 | 2061 | nvme_dev_unmap(dev); |
07836e65 KB |
2062 | |
2063 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2064 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2065 | } |
2066 | ||
091b6092 MW |
2067 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2068 | { | |
e75ec752 | 2069 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2070 | PAGE_SIZE, PAGE_SIZE, 0); |
2071 | if (!dev->prp_page_pool) | |
2072 | return -ENOMEM; | |
2073 | ||
99802a7a | 2074 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2075 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2076 | 256, 256, 0); |
2077 | if (!dev->prp_small_pool) { | |
2078 | dma_pool_destroy(dev->prp_page_pool); | |
2079 | return -ENOMEM; | |
2080 | } | |
091b6092 MW |
2081 | return 0; |
2082 | } | |
2083 | ||
2084 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2085 | { | |
2086 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2087 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2088 | } |
2089 | ||
1673f1f0 | 2090 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2091 | { |
1673f1f0 | 2092 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2093 | |
e75ec752 | 2094 | put_device(dev->dev); |
4af0e21c KB |
2095 | if (dev->tagset.tags) |
2096 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2097 | if (dev->ctrl.admin_q) |
2098 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
2099 | kfree(dev->queues); |
2100 | kfree(dev->entry); | |
2101 | kfree(dev); | |
2102 | } | |
2103 | ||
3cf519b5 | 2104 | static void nvme_probe_work(struct work_struct *work) |
f0b50732 | 2105 | { |
3cf519b5 | 2106 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); |
b9afca3e | 2107 | bool start_thread = false; |
3cf519b5 | 2108 | int result; |
f0b50732 KB |
2109 | |
2110 | result = nvme_dev_map(dev); | |
2111 | if (result) | |
3cf519b5 | 2112 | goto out; |
f0b50732 KB |
2113 | |
2114 | result = nvme_configure_admin_queue(dev); | |
2115 | if (result) | |
2116 | goto unmap; | |
2117 | ||
2118 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2119 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2120 | start_thread = true; | |
2121 | nvme_thread = NULL; | |
2122 | } | |
f0b50732 KB |
2123 | list_add(&dev->node, &dev_list); |
2124 | spin_unlock(&dev_list_lock); | |
2125 | ||
b9afca3e DM |
2126 | if (start_thread) { |
2127 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2128 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2129 | } else |
2130 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2131 | ||
2132 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
2133 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2134 | goto disable; | |
2135 | } | |
a4aea562 MB |
2136 | |
2137 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
2138 | result = nvme_alloc_admin_tags(dev); |
2139 | if (result) | |
2140 | goto disable; | |
b9afca3e | 2141 | |
ce4541f4 CH |
2142 | result = nvme_init_identify(&dev->ctrl); |
2143 | if (result) | |
2144 | goto free_tags; | |
2145 | ||
f0b50732 | 2146 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2147 | if (result) |
0fb59cbc | 2148 | goto free_tags; |
f0b50732 | 2149 | |
1c63dc66 | 2150 | dev->ctrl.event_limit = 1; |
3cf519b5 | 2151 | |
2659e57b CH |
2152 | /* |
2153 | * Keep the controller around but remove all namespaces if we don't have | |
2154 | * any working I/O queue. | |
2155 | */ | |
3cf519b5 CH |
2156 | if (dev->online_queues < 2) { |
2157 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 2158 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 CH |
2159 | } else { |
2160 | nvme_unfreeze_queues(dev); | |
2161 | nvme_dev_add(dev); | |
2162 | } | |
2163 | ||
2164 | return; | |
f0b50732 | 2165 | |
0fb59cbc KB |
2166 | free_tags: |
2167 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2168 | blk_put_queue(dev->ctrl.admin_q); |
2169 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2170 | dev->queues[0]->tags = NULL; |
f0b50732 | 2171 | disable: |
a1a5ef99 | 2172 | nvme_disable_queue(dev, 0); |
b9afca3e | 2173 | nvme_dev_list_remove(dev); |
f0b50732 KB |
2174 | unmap: |
2175 | nvme_dev_unmap(dev); | |
3cf519b5 CH |
2176 | out: |
2177 | if (!work_busy(&dev->reset_work)) | |
2178 | nvme_dead_ctrl(dev); | |
f0b50732 KB |
2179 | } |
2180 | ||
9a6b9458 KB |
2181 | static int nvme_remove_dead_ctrl(void *arg) |
2182 | { | |
2183 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 2184 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2185 | |
2186 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2187 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 2188 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2189 | return 0; |
2190 | } | |
2191 | ||
de3eff2b KB |
2192 | static void nvme_dead_ctrl(struct nvme_dev *dev) |
2193 | { | |
2194 | dev_warn(dev->dev, "Device failed to resume\n"); | |
1673f1f0 | 2195 | kref_get(&dev->ctrl.kref); |
de3eff2b | 2196 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", |
1c63dc66 | 2197 | dev->ctrl.instance))) { |
de3eff2b KB |
2198 | dev_err(dev->dev, |
2199 | "Failed to start controller remove task\n"); | |
1673f1f0 | 2200 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
2201 | } |
2202 | } | |
2203 | ||
77b50d9e | 2204 | static void nvme_reset_work(struct work_struct *ws) |
9a6b9458 | 2205 | { |
77b50d9e | 2206 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
ffe7704d KB |
2207 | bool in_probe = work_busy(&dev->probe_work); |
2208 | ||
9a6b9458 | 2209 | nvme_dev_shutdown(dev); |
ffe7704d KB |
2210 | |
2211 | /* Synchronize with device probe so that work will see failure status | |
2212 | * and exit gracefully without trying to schedule another reset */ | |
2213 | flush_work(&dev->probe_work); | |
2214 | ||
2215 | /* Fail this device if reset occured during probe to avoid | |
2216 | * infinite initialization loops. */ | |
2217 | if (in_probe) { | |
de3eff2b | 2218 | nvme_dead_ctrl(dev); |
ffe7704d | 2219 | return; |
9a6b9458 | 2220 | } |
ffe7704d KB |
2221 | /* Schedule device resume asynchronously so the reset work is available |
2222 | * to cleanup errors that may occur during reinitialization */ | |
2223 | schedule_work(&dev->probe_work); | |
9a6b9458 KB |
2224 | } |
2225 | ||
90667892 | 2226 | static int __nvme_reset(struct nvme_dev *dev) |
9ca97374 | 2227 | { |
90667892 CH |
2228 | if (work_pending(&dev->reset_work)) |
2229 | return -EBUSY; | |
2230 | list_del_init(&dev->node); | |
2231 | queue_work(nvme_workq, &dev->reset_work); | |
2232 | return 0; | |
9ca97374 TH |
2233 | } |
2234 | ||
4cc06521 KB |
2235 | static int nvme_reset(struct nvme_dev *dev) |
2236 | { | |
90667892 | 2237 | int ret; |
4cc06521 | 2238 | |
1c63dc66 | 2239 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
2240 | return -ENODEV; |
2241 | ||
2242 | spin_lock(&dev_list_lock); | |
90667892 | 2243 | ret = __nvme_reset(dev); |
4cc06521 KB |
2244 | spin_unlock(&dev_list_lock); |
2245 | ||
2246 | if (!ret) { | |
2247 | flush_work(&dev->reset_work); | |
ffe7704d | 2248 | flush_work(&dev->probe_work); |
4cc06521 KB |
2249 | return 0; |
2250 | } | |
2251 | ||
2252 | return ret; | |
2253 | } | |
2254 | ||
1c63dc66 CH |
2255 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
2256 | { | |
2257 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
2258 | return 0; | |
2259 | } | |
2260 | ||
5fd4ce1b CH |
2261 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
2262 | { | |
2263 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2264 | return 0; | |
2265 | } | |
2266 | ||
7fd8930f CH |
2267 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2268 | { | |
2269 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2270 | return 0; | |
2271 | } | |
2272 | ||
5bae7f73 CH |
2273 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2274 | { | |
2275 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2276 | ||
2277 | return !dev->bar || dev->online_queues < 2; | |
2278 | } | |
2279 | ||
f3ca80fc CH |
2280 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2281 | { | |
2282 | return nvme_reset(to_nvme_dev(ctrl)); | |
2283 | } | |
2284 | ||
1c63dc66 CH |
2285 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2286 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2287 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2288 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2289 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2290 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2291 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2292 | }; |
2293 | ||
8d85fce7 | 2294 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2295 | { |
a4aea562 | 2296 | int node, result = -ENOMEM; |
b60503ba MW |
2297 | struct nvme_dev *dev; |
2298 | ||
a4aea562 MB |
2299 | node = dev_to_node(&pdev->dev); |
2300 | if (node == NUMA_NO_NODE) | |
2301 | set_dev_node(&pdev->dev, 0); | |
2302 | ||
2303 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2304 | if (!dev) |
2305 | return -ENOMEM; | |
a4aea562 MB |
2306 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2307 | GFP_KERNEL, node); | |
b60503ba MW |
2308 | if (!dev->entry) |
2309 | goto free; | |
a4aea562 MB |
2310 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2311 | GFP_KERNEL, node); | |
b60503ba MW |
2312 | if (!dev->queues) |
2313 | goto free; | |
2314 | ||
e75ec752 | 2315 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2316 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2317 | |
f3ca80fc CH |
2318 | INIT_LIST_HEAD(&dev->node); |
2319 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
2320 | INIT_WORK(&dev->probe_work, nvme_probe_work); | |
2321 | INIT_WORK(&dev->reset_work, nvme_reset_work); | |
1c63dc66 | 2322 | |
f3ca80fc | 2323 | result = nvme_setup_prp_pools(dev); |
cd58ad7d | 2324 | if (result) |
a96d4f5c | 2325 | goto put_pci; |
b60503ba | 2326 | |
f3ca80fc CH |
2327 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2328 | id->driver_data); | |
091b6092 | 2329 | if (result) |
2e1d8448 | 2330 | goto release_pools; |
740216fc | 2331 | |
2e1d8448 | 2332 | schedule_work(&dev->probe_work); |
b60503ba MW |
2333 | return 0; |
2334 | ||
0877cb0d | 2335 | release_pools: |
091b6092 | 2336 | nvme_release_prp_pools(dev); |
a96d4f5c | 2337 | put_pci: |
e75ec752 | 2338 | put_device(dev->dev); |
b60503ba MW |
2339 | free: |
2340 | kfree(dev->queues); | |
2341 | kfree(dev->entry); | |
2342 | kfree(dev); | |
2343 | return result; | |
2344 | } | |
2345 | ||
f0d54a54 KB |
2346 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2347 | { | |
a6739479 | 2348 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2349 | |
a6739479 KB |
2350 | if (prepare) |
2351 | nvme_dev_shutdown(dev); | |
2352 | else | |
0a7385ad | 2353 | schedule_work(&dev->probe_work); |
f0d54a54 KB |
2354 | } |
2355 | ||
09ece142 KB |
2356 | static void nvme_shutdown(struct pci_dev *pdev) |
2357 | { | |
2358 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2359 | nvme_dev_shutdown(dev); | |
2360 | } | |
2361 | ||
8d85fce7 | 2362 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2363 | { |
2364 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2365 | |
2366 | spin_lock(&dev_list_lock); | |
2367 | list_del_init(&dev->node); | |
2368 | spin_unlock(&dev_list_lock); | |
2369 | ||
2370 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 2371 | flush_work(&dev->probe_work); |
9a6b9458 | 2372 | flush_work(&dev->reset_work); |
a5768aa8 | 2373 | flush_work(&dev->scan_work); |
5bae7f73 | 2374 | nvme_remove_namespaces(&dev->ctrl); |
3399a3f7 | 2375 | nvme_dev_shutdown(dev); |
a4aea562 | 2376 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2377 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2378 | nvme_release_cmb(dev); |
9a6b9458 | 2379 | nvme_release_prp_pools(dev); |
1673f1f0 | 2380 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2381 | } |
2382 | ||
2383 | /* These functions are yet to be implemented */ | |
2384 | #define nvme_error_detected NULL | |
2385 | #define nvme_dump_registers NULL | |
2386 | #define nvme_link_reset NULL | |
2387 | #define nvme_slot_reset NULL | |
2388 | #define nvme_error_resume NULL | |
cd638946 | 2389 | |
671a6018 | 2390 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2391 | static int nvme_suspend(struct device *dev) |
2392 | { | |
2393 | struct pci_dev *pdev = to_pci_dev(dev); | |
2394 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2395 | ||
2396 | nvme_dev_shutdown(ndev); | |
2397 | return 0; | |
2398 | } | |
2399 | ||
2400 | static int nvme_resume(struct device *dev) | |
2401 | { | |
2402 | struct pci_dev *pdev = to_pci_dev(dev); | |
2403 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2404 | |
0a7385ad | 2405 | schedule_work(&ndev->probe_work); |
9a6b9458 | 2406 | return 0; |
cd638946 | 2407 | } |
671a6018 | 2408 | #endif |
cd638946 KB |
2409 | |
2410 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2411 | |
1d352035 | 2412 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2413 | .error_detected = nvme_error_detected, |
2414 | .mmio_enabled = nvme_dump_registers, | |
2415 | .link_reset = nvme_link_reset, | |
2416 | .slot_reset = nvme_slot_reset, | |
2417 | .resume = nvme_error_resume, | |
f0d54a54 | 2418 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2419 | }; |
2420 | ||
2421 | /* Move to pci_ids.h later */ | |
2422 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2423 | ||
6eb0d698 | 2424 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2425 | { PCI_VDEVICE(INTEL, 0x0953), |
2426 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
b60503ba | 2427 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2428 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2429 | { 0, } |
2430 | }; | |
2431 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2432 | ||
2433 | static struct pci_driver nvme_driver = { | |
2434 | .name = "nvme", | |
2435 | .id_table = nvme_id_table, | |
2436 | .probe = nvme_probe, | |
8d85fce7 | 2437 | .remove = nvme_remove, |
09ece142 | 2438 | .shutdown = nvme_shutdown, |
cd638946 KB |
2439 | .driver = { |
2440 | .pm = &nvme_dev_pm_ops, | |
2441 | }, | |
b60503ba MW |
2442 | .err_handler = &nvme_err_handler, |
2443 | }; | |
2444 | ||
2445 | static int __init nvme_init(void) | |
2446 | { | |
0ac13140 | 2447 | int result; |
1fa6aead | 2448 | |
b9afca3e | 2449 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2450 | |
9a6b9458 KB |
2451 | nvme_workq = create_singlethread_workqueue("nvme"); |
2452 | if (!nvme_workq) | |
b9afca3e | 2453 | return -ENOMEM; |
9a6b9458 | 2454 | |
5bae7f73 | 2455 | result = nvme_core_init(); |
5c42ea16 | 2456 | if (result < 0) |
9a6b9458 | 2457 | goto kill_workq; |
b60503ba | 2458 | |
f3db22fe KB |
2459 | result = pci_register_driver(&nvme_driver); |
2460 | if (result) | |
f3ca80fc | 2461 | goto core_exit; |
1fa6aead | 2462 | return 0; |
b60503ba | 2463 | |
f3ca80fc | 2464 | core_exit: |
5bae7f73 | 2465 | nvme_core_exit(); |
9a6b9458 KB |
2466 | kill_workq: |
2467 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2468 | return result; |
2469 | } | |
2470 | ||
2471 | static void __exit nvme_exit(void) | |
2472 | { | |
2473 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2474 | nvme_core_exit(); |
9a6b9458 | 2475 | destroy_workqueue(nvme_workq); |
b9afca3e | 2476 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2477 | _nvme_check_size(); |
b60503ba MW |
2478 | } |
2479 | ||
2480 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2481 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2482 | MODULE_VERSION("1.0"); |
b60503ba MW |
2483 | module_init(nvme_init); |
2484 | module_exit(nvme_exit); |