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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
a1726e30 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
56d7640a | 7 | This program and the accompanying materials\r |
49ba9447 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
5133d1f1 | 25 | #include <Library/BaseLib.h>\r |
49ba9447 | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
77ba993c | 29 | #include <Library/MemoryAllocationLib.h>\r |
30 | #include <Library/PcdLib.h>\r | |
49ba9447 | 31 | #include <Library/PciLib.h>\r |
32 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 33 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 34 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 35 | #include <Library/ResourcePublicationLib.h>\r |
36 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 37 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 38 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 39 | #include <OvmfPlatforms.h>\r |
49ba9447 | 40 | \r |
41 | #include "Platform.h"\r | |
3ca15914 | 42 | #include "Cmos.h"\r |
49ba9447 | 43 | \r |
44 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
45 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 46 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 47 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 48 | { EfiRuntimeServicesData, 0x024 },\r |
49 | { EfiRuntimeServicesCode, 0x030 },\r | |
50 | { EfiBootServicesCode, 0x180 },\r | |
51 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 52 | { EfiMaxMemoryType, 0x000 }\r |
53 | };\r | |
54 | \r | |
55 | \r | |
9ed65b10 | 56 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
57 | {\r | |
58 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
59 | &gEfiPeiMasterBootModePpiGuid,\r | |
60 | NULL\r | |
61 | }\r | |
62 | };\r | |
63 | \r | |
64 | \r | |
589756c7 PA |
65 | UINT16 mHostBridgeDevId;\r |
66 | \r | |
979420df JJ |
67 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
68 | \r | |
7cdba634 JJ |
69 | BOOLEAN mS3Supported = FALSE;\r |
70 | \r | |
45a70db3 | 71 | UINT32 mMaxCpuCount;\r |
979420df | 72 | \r |
49ba9447 | 73 | VOID\r |
74 | AddIoMemoryBaseSizeHob (\r | |
75 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
76 | UINT64 MemorySize\r | |
77 | )\r | |
78 | {\r | |
991d9563 | 79 | BuildResourceDescriptorHob (\r |
80 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 81 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
82 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
83 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 84 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 85 | MemoryBase,\r |
86 | MemorySize\r | |
87 | );\r | |
88 | }\r | |
89 | \r | |
eec7d420 | 90 | VOID\r |
91 | AddReservedMemoryBaseSizeHob (\r | |
92 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
93 | UINT64 MemorySize,\r |
94 | BOOLEAN Cacheable\r | |
eec7d420 | 95 | )\r |
96 | {\r | |
97 | BuildResourceDescriptorHob (\r | |
98 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
99 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
100 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
101 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
102 | (Cacheable ?\r |
103 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
104 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
105 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
106 | 0\r | |
107 | ) |\r | |
eec7d420 | 108 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
109 | MemoryBase,\r | |
110 | MemorySize\r | |
111 | );\r | |
112 | }\r | |
49ba9447 | 113 | \r |
114 | VOID\r | |
115 | AddIoMemoryRangeHob (\r | |
116 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
117 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
118 | )\r | |
119 | {\r | |
120 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
121 | }\r | |
122 | \r | |
123 | \r | |
124 | VOID\r | |
125 | AddMemoryBaseSizeHob (\r | |
126 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
127 | UINT64 MemorySize\r | |
128 | )\r | |
129 | {\r | |
991d9563 | 130 | BuildResourceDescriptorHob (\r |
131 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 132 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
133 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
134 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
136 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
137 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 138 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 139 | MemoryBase,\r |
140 | MemorySize\r | |
141 | );\r | |
142 | }\r | |
143 | \r | |
144 | \r | |
145 | VOID\r | |
146 | AddMemoryRangeHob (\r | |
147 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
148 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
149 | )\r | |
150 | {\r | |
151 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
152 | }\r | |
153 | \r | |
c0e10976 | 154 | \r |
bb6a9a93 | 155 | VOID\r |
4b455f7b | 156 | MemMapInitialization (\r |
bb6a9a93 WL |
157 | VOID\r |
158 | )\r | |
159 | {\r | |
32e083c7 LE |
160 | UINT64 PciIoBase;\r |
161 | UINT64 PciIoSize;\r | |
162 | RETURN_STATUS PcdStatus;\r | |
c4df7fd0 LE |
163 | \r |
164 | PciIoBase = 0xC000;\r | |
165 | PciIoSize = 0x4000;\r | |
166 | \r | |
bb6a9a93 WL |
167 | //\r |
168 | // Create Memory Type Information HOB\r | |
169 | //\r | |
170 | BuildGuidDataHob (\r | |
171 | &gEfiMemoryTypeInformationGuid,\r | |
172 | mDefaultMemoryTypeInformation,\r | |
173 | sizeof(mDefaultMemoryTypeInformation)\r | |
174 | );\r | |
175 | \r | |
bb6a9a93 WL |
176 | //\r |
177 | // Video memory + Legacy BIOS region\r | |
178 | //\r | |
179 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
180 | \r | |
4b455f7b JJ |
181 | if (!mXen) {\r |
182 | UINT32 TopOfLowRam;\r | |
7b8fe635 | 183 | UINT64 PciExBarBase;\r |
c68d3a69 | 184 | UINT32 PciBase;\r |
03845e90 | 185 | UINT32 PciSize;\r |
c68d3a69 | 186 | \r |
4b455f7b | 187 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
02d6f4ce | 188 | PciExBarBase = 0;\r |
c68d3a69 LE |
189 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
190 | //\r | |
7b8fe635 LE |
191 | // The MMCONFIG area is expected to fall between the top of low RAM and\r |
192 | // the base of the 32-bit PCI host aperture.\r | |
c68d3a69 | 193 | //\r |
7b8fe635 LE |
194 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r |
195 | ASSERT (TopOfLowRam <= PciExBarBase);\r | |
196 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r | |
197 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r | |
c68d3a69 LE |
198 | } else {\r |
199 | PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r | |
200 | }\r | |
49ba9447 | 201 | \r |
4b455f7b JJ |
202 | //\r |
203 | // address purpose size\r | |
204 | // ------------ -------- -------------------------\r | |
205 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
206 | // 0xFC000000 gap 44 MB\r | |
207 | // 0xFEC00000 IO-APIC 4 KB\r | |
208 | // 0xFEC01000 gap 1020 KB\r | |
209 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
210 | // 0xFED00400 gap 111 KB\r |
211 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
212 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
213 | // 0xFEE00000 LAPIC 1 MB\r |
214 | //\r | |
03845e90 LE |
215 | PciSize = 0xFC000000 - PciBase;\r |
216 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r | |
32e083c7 LE |
217 | PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r |
218 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
219 | PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r | |
220 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
221 | \r | |
4b455f7b JJ |
222 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
223 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
224 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
225 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
7b8fe635 LE |
226 | //\r |
227 | // Note: there should be an\r | |
228 | //\r | |
229 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
230 | //\r | |
231 | // call below, just like the one above for RCBA. However, Linux insists\r | |
232 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
233 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
234 | // in the memory map wherever the MCFG ACPI table points to.\r | |
235 | //\r | |
236 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
237 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
238 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
239 | // [...]". (Emphasis added here.)\r | |
240 | //\r | |
241 | // Normally we add memory resource descriptor HOBs in\r | |
242 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
243 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
244 | // is most definitely not RAM; so, as an exception, cover it with\r | |
245 | // uncacheable reserved memory right here.\r | |
246 | //\r | |
247 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
248 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
249 | EfiReservedMemoryType);\r | |
90721ba5 | 250 | }\r |
4b455f7b | 251 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
bba734ab LE |
252 | \r |
253 | //\r | |
254 | // On Q35, the IO Port space is available for PCI resource allocations from\r | |
255 | // 0x6000 up.\r | |
256 | //\r | |
257 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
258 | PciIoBase = 0x6000;\r | |
259 | PciIoSize = 0xA000;\r | |
260 | ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r | |
261 | }\r | |
4b455f7b | 262 | }\r |
c4df7fd0 LE |
263 | \r |
264 | //\r | |
265 | // Add PCI IO Port space available for PCI resource allocations.\r | |
266 | //\r | |
267 | BuildResourceDescriptorHob (\r | |
268 | EFI_RESOURCE_IO,\r | |
269 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
270 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
271 | PciIoBase,\r | |
272 | PciIoSize\r | |
273 | );\r | |
32e083c7 LE |
274 | PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r |
275 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
276 | PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r | |
277 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
49ba9447 | 278 | }\r |
279 | \r | |
ab081a50 LE |
280 | EFI_STATUS\r |
281 | GetNamedFwCfgBoolean (\r | |
282 | IN CHAR8 *FwCfgFileName,\r | |
283 | OUT BOOLEAN *Setting\r | |
284 | )\r | |
285 | {\r | |
286 | EFI_STATUS Status;\r | |
287 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
288 | UINTN FwCfgSize;\r | |
289 | UINT8 Value[3];\r | |
290 | \r | |
291 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
292 | if (EFI_ERROR (Status)) {\r | |
293 | return Status;\r | |
294 | }\r | |
295 | if (FwCfgSize > sizeof Value) {\r | |
296 | return EFI_BAD_BUFFER_SIZE;\r | |
297 | }\r | |
298 | QemuFwCfgSelectItem (FwCfgItem);\r | |
299 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
300 | \r | |
301 | if ((FwCfgSize == 1) ||\r | |
302 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
303 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
304 | switch (Value[0]) {\r | |
305 | case '0':\r | |
306 | case 'n':\r | |
307 | case 'N':\r | |
308 | *Setting = FALSE;\r | |
309 | return EFI_SUCCESS;\r | |
310 | \r | |
311 | case '1':\r | |
312 | case 'y':\r | |
313 | case 'Y':\r | |
314 | *Setting = TRUE;\r | |
315 | return EFI_SUCCESS;\r | |
316 | \r | |
317 | default:\r | |
318 | break;\r | |
319 | }\r | |
320 | }\r | |
321 | return EFI_PROTOCOL_ERROR;\r | |
322 | }\r | |
323 | \r | |
324 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
325 | do { \\r | |
32e083c7 LE |
326 | BOOLEAN Setting; \\r |
327 | RETURN_STATUS PcdStatus; \\r | |
ab081a50 LE |
328 | \\r |
329 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
330 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
32e083c7 LE |
331 | PcdStatus = PcdSetBoolS (TokenName, Setting); \\r |
332 | ASSERT_RETURN_ERROR (PcdStatus); \\r | |
ab081a50 LE |
333 | } \\r |
334 | } while (0)\r | |
335 | \r | |
336 | VOID\r | |
337 | NoexecDxeInitialization (\r | |
338 | VOID\r | |
339 | )\r | |
340 | {\r | |
341 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
342 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
343 | }\r | |
49ba9447 | 344 | \r |
7b8fe635 LE |
345 | VOID\r |
346 | PciExBarInitialization (\r | |
347 | VOID\r | |
348 | )\r | |
349 | {\r | |
350 | union {\r | |
351 | UINT64 Uint64;\r | |
352 | UINT32 Uint32[2];\r | |
353 | } PciExBarBase;\r | |
354 | \r | |
355 | //\r | |
356 | // We only support the 256MB size for the MMCONFIG area:\r | |
357 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
358 | //\r | |
359 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
360 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
361 | //\r | |
362 | // Note that (b) also ensures that the minimum address width we have\r | |
363 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
364 | // for DXE's page tables to cover the MMCONFIG area.\r | |
365 | //\r | |
366 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
367 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
368 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
369 | \r | |
370 | //\r | |
371 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
372 | //\r | |
373 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
374 | \r | |
375 | //\r | |
376 | // Program the high register. Then program the low register, setting the\r | |
377 | // MMCONFIG area size and enabling decoding at once.\r | |
378 | //\r | |
379 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
380 | PciWrite32 (\r | |
381 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
382 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
383 | );\r | |
384 | }\r | |
385 | \r | |
49ba9447 | 386 | VOID\r |
387 | MiscInitialization (\r | |
0e20a186 | 388 | VOID\r |
49ba9447 | 389 | )\r |
390 | {\r | |
32e083c7 LE |
391 | UINTN PmCmd;\r |
392 | UINTN Pmba;\r | |
393 | UINT32 PmbaAndVal;\r | |
394 | UINT32 PmbaOrVal;\r | |
395 | UINTN AcpiCtlReg;\r | |
396 | UINT8 AcpiEnBit;\r | |
397 | RETURN_STATUS PcdStatus;\r | |
97380beb | 398 | \r |
49ba9447 | 399 | //\r |
400 | // Disable A20 Mask\r | |
401 | //\r | |
55cdb67a | 402 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 403 | \r |
404 | //\r | |
86a14b0a LE |
405 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
406 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
407 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 408 | //\r |
86a14b0a | 409 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 410 | \r |
97380beb | 411 | //\r |
589756c7 | 412 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 413 | //\r |
589756c7 | 414 | switch (mHostBridgeDevId) {\r |
97380beb | 415 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 416 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 | 417 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
1466b76f LE |
418 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r |
419 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
da372167 LE |
420 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r |
421 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
422 | break;\r |
423 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 424 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 | 425 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
1466b76f LE |
426 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r |
427 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
bc9d05d6 LE |
428 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r |
429 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
430 | break;\r |
431 | default:\r | |
432 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 433 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
434 | ASSERT (FALSE);\r |
435 | return;\r | |
436 | }\r | |
32e083c7 LE |
437 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
438 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
97380beb | 439 | \r |
0e20a186 | 440 | //\r |
e2ab3f81 GS |
441 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
442 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
443 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 444 | //\r |
e2ab3f81 | 445 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 446 | //\r |
e2ab3f81 | 447 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 448 | // 1. set PMBA\r |
eec7d420 | 449 | //\r |
1466b76f | 450 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r |
931a0c74 | 451 | \r |
452 | //\r | |
453 | // 2. set PCICMD/IOSE\r | |
454 | //\r | |
97380beb | 455 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 456 | \r |
457 | //\r | |
e2ab3f81 | 458 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 459 | //\r |
e2ab3f81 | 460 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 461 | }\r |
90721ba5 PA |
462 | \r |
463 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
464 | //\r | |
465 | // Set Root Complex Register Block BAR\r | |
466 | //\r | |
467 | PciWrite32 (\r | |
468 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
469 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
470 | );\r | |
7b8fe635 LE |
471 | \r |
472 | //\r | |
473 | // Set PCI Express Register Range Base Address\r | |
474 | //\r | |
475 | PciExBarInitialization ();\r | |
90721ba5 | 476 | }\r |
49ba9447 | 477 | }\r |
478 | \r | |
479 | \r | |
9ed65b10 | 480 | VOID\r |
481 | BootModeInitialization (\r | |
8f5ca05b | 482 | VOID\r |
9ed65b10 | 483 | )\r |
484 | {\r | |
8f5ca05b LE |
485 | EFI_STATUS Status;\r |
486 | \r | |
487 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 488 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 489 | }\r |
9be75189 | 490 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 491 | \r |
979420df | 492 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 493 | ASSERT_EFI_ERROR (Status);\r |
494 | \r | |
495 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
496 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 497 | }\r |
498 | \r | |
499 | \r | |
77ba993c | 500 | VOID\r |
501 | ReserveEmuVariableNvStore (\r | |
502 | )\r | |
503 | {\r | |
504 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
32e083c7 | 505 | RETURN_STATUS PcdStatus;\r |
77ba993c | 506 | \r |
507 | //\r | |
508 | // Allocate storage for NV variables early on so it will be\r | |
509 | // at a consistent address. Since VM memory is preserved\r | |
510 | // across reboots, this allows the NV variable storage to survive\r | |
511 | // a VM reboot.\r | |
512 | //\r | |
513 | VariableStore =\r | |
514 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
9edb2933 | 515 | AllocateAlignedRuntimePages (\r |
cce992ac WL |
516 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r |
517 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
27f58ea1 | 518 | );\r |
77ba993c | 519 | DEBUG ((EFI_D_INFO,\r |
520 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
521 | VariableStore,\r | |
29a3f139 | 522 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 523 | ));\r |
32e083c7 LE |
524 | PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r |
525 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
77ba993c | 526 | }\r |
527 | \r | |
528 | \r | |
3ca15914 | 529 | VOID\r |
530 | DebugDumpCmos (\r | |
531 | VOID\r | |
532 | )\r | |
533 | {\r | |
6394c35a | 534 | UINT32 Loop;\r |
3ca15914 | 535 | \r |
536 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
537 | \r | |
538 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
539 | if ((Loop % 0x10) == 0) {\r | |
540 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
541 | }\r | |
542 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
543 | if ((Loop % 0x10) == 0xf) {\r | |
544 | DEBUG ((EFI_D_INFO, "\n"));\r | |
545 | }\r | |
546 | }\r | |
547 | }\r | |
548 | \r | |
549 | \r | |
5133d1f1 LE |
550 | VOID\r |
551 | S3Verification (\r | |
552 | VOID\r | |
553 | )\r | |
554 | {\r | |
555 | #if defined (MDE_CPU_X64)\r | |
556 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
557 | DEBUG ((EFI_D_ERROR,\r | |
558 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
559 | DEBUG ((EFI_D_ERROR,\r | |
560 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
561 | __FUNCTION__));\r | |
562 | DEBUG ((EFI_D_ERROR,\r | |
563 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
564 | ASSERT (FALSE);\r | |
565 | CpuDeadLoop ();\r | |
566 | }\r | |
567 | #endif\r | |
568 | }\r | |
569 | \r | |
570 | \r | |
45a70db3 LE |
571 | /**\r |
572 | Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r | |
573 | Set the mMaxCpuCount variable.\r | |
574 | **/\r | |
575 | VOID\r | |
576 | MaxCpuCountInitialization (\r | |
577 | VOID\r | |
578 | )\r | |
579 | {\r | |
580 | UINT16 ProcessorCount;\r | |
581 | RETURN_STATUS PcdStatus;\r | |
582 | \r | |
583 | QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r | |
584 | ProcessorCount = QemuFwCfgRead16 ();\r | |
585 | //\r | |
586 | // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r | |
587 | // from the PCD default. No change to PCDs.\r | |
588 | //\r | |
589 | if (ProcessorCount == 0) {\r | |
590 | mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r | |
591 | return;\r | |
592 | }\r | |
593 | //\r | |
594 | // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r | |
595 | //\r | |
596 | mMaxCpuCount = ProcessorCount;\r | |
597 | //\r | |
598 | // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r | |
599 | // to wait, in the initial AP bringup, exactly as long as it takes for all of\r | |
600 | // the APs to report in. For this, we set the longest representable timeout\r | |
601 | // (approx. 71 minutes).\r | |
602 | //\r | |
603 | PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r | |
604 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
605 | PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r | |
606 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
607 | DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r | |
608 | ProcessorCount));\r | |
609 | }\r | |
610 | \r | |
611 | \r | |
49ba9447 | 612 | /**\r |
613 | Perform Platform PEI initialization.\r | |
614 | \r | |
615 | @param FileHandle Handle of the file being invoked.\r | |
616 | @param PeiServices Describes the list of possible PEI Services.\r | |
617 | \r | |
618 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
619 | \r | |
620 | **/\r | |
621 | EFI_STATUS\r | |
622 | EFIAPI\r | |
623 | InitializePlatform (\r | |
624 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
625 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
626 | )\r | |
627 | {\r | |
a1726e30 SZ |
628 | EFI_STATUS Status;\r |
629 | \r | |
49ba9447 | 630 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r |
631 | \r | |
3ca15914 | 632 | DebugDumpCmos ();\r |
633 | \r | |
b98b4941 | 634 | XenDetect ();\r |
c7ea55b9 | 635 | \r |
7cdba634 JJ |
636 | if (QemuFwCfgS3Enabled ()) {\r |
637 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
638 | mS3Supported = TRUE;\r | |
a1726e30 SZ |
639 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r |
640 | ASSERT_EFI_ERROR (Status);\r | |
7cdba634 JJ |
641 | }\r |
642 | \r | |
5133d1f1 | 643 | S3Verification ();\r |
869b17cc | 644 | BootModeInitialization ();\r |
bc89fe48 | 645 | AddressWidthInitialization ();\r |
45a70db3 | 646 | MaxCpuCountInitialization ();\r |
869b17cc | 647 | \r |
f76e9eba JJ |
648 | PublishPeiMemory ();\r |
649 | \r | |
2818c158 | 650 | InitializeRamRegions ();\r |
49ba9447 | 651 | \r |
b621bb0a | 652 | if (mXen) {\r |
c7ea55b9 | 653 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 654 | InitializeXen ();\r |
c7ea55b9 | 655 | }\r |
eec7d420 | 656 | \r |
589756c7 PA |
657 | //\r |
658 | // Query Host Bridge DID\r | |
659 | //\r | |
660 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
661 | \r | |
bd386eaf JJ |
662 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
663 | ReserveEmuVariableNvStore ();\r | |
bd386eaf | 664 | PeiFvInitialization ();\r |
bd386eaf | 665 | MemMapInitialization ();\r |
ab081a50 | 666 | NoexecDxeInitialization ();\r |
bd386eaf | 667 | }\r |
49ba9447 | 668 | \r |
0e20a186 | 669 | MiscInitialization ();\r |
dbab9949 | 670 | InstallFeatureControlCallback ();\r |
49ba9447 | 671 | \r |
672 | return EFI_SUCCESS;\r | |
673 | }\r |