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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
a1726e30 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
56d7640a | 7 | This program and the accompanying materials\r |
49ba9447 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
5133d1f1 | 25 | #include <Library/BaseLib.h>\r |
49ba9447 | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
77ba993c | 29 | #include <Library/MemoryAllocationLib.h>\r |
30 | #include <Library/PcdLib.h>\r | |
49ba9447 | 31 | #include <Library/PciLib.h>\r |
32 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 33 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 34 | #include <Library/QemuFwCfgLib.h>\r |
687f7521 | 35 | #include <Library/QemuFwCfgS3Lib.h>\r |
49ba9447 | 36 | #include <Library/ResourcePublicationLib.h>\r |
37 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 38 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 39 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 40 | #include <OvmfPlatforms.h>\r |
49ba9447 | 41 | \r |
42 | #include "Platform.h"\r | |
3ca15914 | 43 | #include "Cmos.h"\r |
49ba9447 | 44 | \r |
45 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
46 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 47 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 48 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 49 | { EfiRuntimeServicesData, 0x024 },\r |
50 | { EfiRuntimeServicesCode, 0x030 },\r | |
51 | { EfiBootServicesCode, 0x180 },\r | |
52 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 53 | { EfiMaxMemoryType, 0x000 }\r |
54 | };\r | |
55 | \r | |
56 | \r | |
9ed65b10 | 57 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
58 | {\r | |
59 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
60 | &gEfiPeiMasterBootModePpiGuid,\r | |
61 | NULL\r | |
62 | }\r | |
63 | };\r | |
64 | \r | |
65 | \r | |
589756c7 PA |
66 | UINT16 mHostBridgeDevId;\r |
67 | \r | |
979420df JJ |
68 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
69 | \r | |
7cdba634 JJ |
70 | BOOLEAN mS3Supported = FALSE;\r |
71 | \r | |
45a70db3 | 72 | UINT32 mMaxCpuCount;\r |
979420df | 73 | \r |
49ba9447 | 74 | VOID\r |
75 | AddIoMemoryBaseSizeHob (\r | |
76 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
77 | UINT64 MemorySize\r | |
78 | )\r | |
79 | {\r | |
991d9563 | 80 | BuildResourceDescriptorHob (\r |
81 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 82 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
83 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
84 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 85 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 86 | MemoryBase,\r |
87 | MemorySize\r | |
88 | );\r | |
89 | }\r | |
90 | \r | |
eec7d420 | 91 | VOID\r |
92 | AddReservedMemoryBaseSizeHob (\r | |
93 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
94 | UINT64 MemorySize,\r |
95 | BOOLEAN Cacheable\r | |
eec7d420 | 96 | )\r |
97 | {\r | |
98 | BuildResourceDescriptorHob (\r | |
99 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
100 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
101 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
102 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
103 | (Cacheable ?\r |
104 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
105 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
106 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
107 | 0\r | |
108 | ) |\r | |
eec7d420 | 109 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
110 | MemoryBase,\r | |
111 | MemorySize\r | |
112 | );\r | |
113 | }\r | |
49ba9447 | 114 | \r |
115 | VOID\r | |
116 | AddIoMemoryRangeHob (\r | |
117 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
118 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
119 | )\r | |
120 | {\r | |
121 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
122 | }\r | |
123 | \r | |
124 | \r | |
125 | VOID\r | |
126 | AddMemoryBaseSizeHob (\r | |
127 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
128 | UINT64 MemorySize\r | |
129 | )\r | |
130 | {\r | |
991d9563 | 131 | BuildResourceDescriptorHob (\r |
132 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 133 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
134 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
136 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
137 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
138 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 139 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 140 | MemoryBase,\r |
141 | MemorySize\r | |
142 | );\r | |
143 | }\r | |
144 | \r | |
145 | \r | |
146 | VOID\r | |
147 | AddMemoryRangeHob (\r | |
148 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
149 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
150 | )\r | |
151 | {\r | |
152 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
153 | }\r | |
154 | \r | |
c0e10976 | 155 | \r |
bb6a9a93 | 156 | VOID\r |
4b455f7b | 157 | MemMapInitialization (\r |
bb6a9a93 WL |
158 | VOID\r |
159 | )\r | |
160 | {\r | |
32e083c7 LE |
161 | UINT64 PciIoBase;\r |
162 | UINT64 PciIoSize;\r | |
163 | RETURN_STATUS PcdStatus;\r | |
c4df7fd0 LE |
164 | \r |
165 | PciIoBase = 0xC000;\r | |
166 | PciIoSize = 0x4000;\r | |
167 | \r | |
bb6a9a93 WL |
168 | //\r |
169 | // Create Memory Type Information HOB\r | |
170 | //\r | |
171 | BuildGuidDataHob (\r | |
172 | &gEfiMemoryTypeInformationGuid,\r | |
173 | mDefaultMemoryTypeInformation,\r | |
174 | sizeof(mDefaultMemoryTypeInformation)\r | |
175 | );\r | |
176 | \r | |
bb6a9a93 WL |
177 | //\r |
178 | // Video memory + Legacy BIOS region\r | |
179 | //\r | |
180 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
181 | \r | |
4b455f7b JJ |
182 | if (!mXen) {\r |
183 | UINT32 TopOfLowRam;\r | |
7b8fe635 | 184 | UINT64 PciExBarBase;\r |
c68d3a69 | 185 | UINT32 PciBase;\r |
03845e90 | 186 | UINT32 PciSize;\r |
c68d3a69 | 187 | \r |
4b455f7b | 188 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
02d6f4ce | 189 | PciExBarBase = 0;\r |
c68d3a69 LE |
190 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
191 | //\r | |
7b8fe635 LE |
192 | // The MMCONFIG area is expected to fall between the top of low RAM and\r |
193 | // the base of the 32-bit PCI host aperture.\r | |
c68d3a69 | 194 | //\r |
7b8fe635 LE |
195 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r |
196 | ASSERT (TopOfLowRam <= PciExBarBase);\r | |
197 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r | |
198 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r | |
c68d3a69 LE |
199 | } else {\r |
200 | PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r | |
201 | }\r | |
49ba9447 | 202 | \r |
4b455f7b JJ |
203 | //\r |
204 | // address purpose size\r | |
205 | // ------------ -------- -------------------------\r | |
206 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
207 | // 0xFC000000 gap 44 MB\r | |
208 | // 0xFEC00000 IO-APIC 4 KB\r | |
209 | // 0xFEC01000 gap 1020 KB\r | |
210 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
211 | // 0xFED00400 gap 111 KB\r |
212 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
213 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
214 | // 0xFEE00000 LAPIC 1 MB\r |
215 | //\r | |
03845e90 LE |
216 | PciSize = 0xFC000000 - PciBase;\r |
217 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r | |
32e083c7 LE |
218 | PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r |
219 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
220 | PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r | |
221 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
222 | \r | |
4b455f7b JJ |
223 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
224 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
225 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
226 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
7b8fe635 LE |
227 | //\r |
228 | // Note: there should be an\r | |
229 | //\r | |
230 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
231 | //\r | |
232 | // call below, just like the one above for RCBA. However, Linux insists\r | |
233 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
234 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
235 | // in the memory map wherever the MCFG ACPI table points to.\r | |
236 | //\r | |
237 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
238 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
239 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
240 | // [...]". (Emphasis added here.)\r | |
241 | //\r | |
242 | // Normally we add memory resource descriptor HOBs in\r | |
243 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
244 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
245 | // is most definitely not RAM; so, as an exception, cover it with\r | |
246 | // uncacheable reserved memory right here.\r | |
247 | //\r | |
248 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
249 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
250 | EfiReservedMemoryType);\r | |
90721ba5 | 251 | }\r |
4b455f7b | 252 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
bba734ab LE |
253 | \r |
254 | //\r | |
255 | // On Q35, the IO Port space is available for PCI resource allocations from\r | |
256 | // 0x6000 up.\r | |
257 | //\r | |
258 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
259 | PciIoBase = 0x6000;\r | |
260 | PciIoSize = 0xA000;\r | |
261 | ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r | |
262 | }\r | |
4b455f7b | 263 | }\r |
c4df7fd0 LE |
264 | \r |
265 | //\r | |
266 | // Add PCI IO Port space available for PCI resource allocations.\r | |
267 | //\r | |
268 | BuildResourceDescriptorHob (\r | |
269 | EFI_RESOURCE_IO,\r | |
270 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
271 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
272 | PciIoBase,\r | |
273 | PciIoSize\r | |
274 | );\r | |
32e083c7 LE |
275 | PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r |
276 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
277 | PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r | |
278 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
49ba9447 | 279 | }\r |
280 | \r | |
ab081a50 LE |
281 | EFI_STATUS\r |
282 | GetNamedFwCfgBoolean (\r | |
283 | IN CHAR8 *FwCfgFileName,\r | |
284 | OUT BOOLEAN *Setting\r | |
285 | )\r | |
286 | {\r | |
287 | EFI_STATUS Status;\r | |
288 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
289 | UINTN FwCfgSize;\r | |
290 | UINT8 Value[3];\r | |
291 | \r | |
292 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
293 | if (EFI_ERROR (Status)) {\r | |
294 | return Status;\r | |
295 | }\r | |
296 | if (FwCfgSize > sizeof Value) {\r | |
297 | return EFI_BAD_BUFFER_SIZE;\r | |
298 | }\r | |
299 | QemuFwCfgSelectItem (FwCfgItem);\r | |
300 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
301 | \r | |
302 | if ((FwCfgSize == 1) ||\r | |
303 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
304 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
305 | switch (Value[0]) {\r | |
306 | case '0':\r | |
307 | case 'n':\r | |
308 | case 'N':\r | |
309 | *Setting = FALSE;\r | |
310 | return EFI_SUCCESS;\r | |
311 | \r | |
312 | case '1':\r | |
313 | case 'y':\r | |
314 | case 'Y':\r | |
315 | *Setting = TRUE;\r | |
316 | return EFI_SUCCESS;\r | |
317 | \r | |
318 | default:\r | |
319 | break;\r | |
320 | }\r | |
321 | }\r | |
322 | return EFI_PROTOCOL_ERROR;\r | |
323 | }\r | |
324 | \r | |
325 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
326 | do { \\r | |
32e083c7 LE |
327 | BOOLEAN Setting; \\r |
328 | RETURN_STATUS PcdStatus; \\r | |
ab081a50 LE |
329 | \\r |
330 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
331 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
32e083c7 LE |
332 | PcdStatus = PcdSetBoolS (TokenName, Setting); \\r |
333 | ASSERT_RETURN_ERROR (PcdStatus); \\r | |
ab081a50 LE |
334 | } \\r |
335 | } while (0)\r | |
336 | \r | |
337 | VOID\r | |
338 | NoexecDxeInitialization (\r | |
339 | VOID\r | |
340 | )\r | |
341 | {\r | |
342 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
343 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
344 | }\r | |
49ba9447 | 345 | \r |
7b8fe635 LE |
346 | VOID\r |
347 | PciExBarInitialization (\r | |
348 | VOID\r | |
349 | )\r | |
350 | {\r | |
351 | union {\r | |
352 | UINT64 Uint64;\r | |
353 | UINT32 Uint32[2];\r | |
354 | } PciExBarBase;\r | |
355 | \r | |
356 | //\r | |
357 | // We only support the 256MB size for the MMCONFIG area:\r | |
358 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
359 | //\r | |
360 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
361 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
362 | //\r | |
363 | // Note that (b) also ensures that the minimum address width we have\r | |
364 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
365 | // for DXE's page tables to cover the MMCONFIG area.\r | |
366 | //\r | |
367 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
368 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
369 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
370 | \r | |
371 | //\r | |
372 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
373 | //\r | |
374 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
375 | \r | |
376 | //\r | |
377 | // Program the high register. Then program the low register, setting the\r | |
378 | // MMCONFIG area size and enabling decoding at once.\r | |
379 | //\r | |
380 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
381 | PciWrite32 (\r | |
382 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
383 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
384 | );\r | |
385 | }\r | |
386 | \r | |
49ba9447 | 387 | VOID\r |
388 | MiscInitialization (\r | |
0e20a186 | 389 | VOID\r |
49ba9447 | 390 | )\r |
391 | {\r | |
32e083c7 LE |
392 | UINTN PmCmd;\r |
393 | UINTN Pmba;\r | |
394 | UINT32 PmbaAndVal;\r | |
395 | UINT32 PmbaOrVal;\r | |
396 | UINTN AcpiCtlReg;\r | |
397 | UINT8 AcpiEnBit;\r | |
398 | RETURN_STATUS PcdStatus;\r | |
97380beb | 399 | \r |
49ba9447 | 400 | //\r |
401 | // Disable A20 Mask\r | |
402 | //\r | |
55cdb67a | 403 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 404 | \r |
405 | //\r | |
86a14b0a LE |
406 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
407 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
408 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 409 | //\r |
86a14b0a | 410 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 411 | \r |
97380beb | 412 | //\r |
589756c7 | 413 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 414 | //\r |
589756c7 | 415 | switch (mHostBridgeDevId) {\r |
97380beb | 416 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 417 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 | 418 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
1466b76f LE |
419 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r |
420 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
da372167 LE |
421 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r |
422 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
423 | break;\r |
424 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 425 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 | 426 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
1466b76f LE |
427 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r |
428 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
bc9d05d6 LE |
429 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r |
430 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
431 | break;\r |
432 | default:\r | |
433 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 434 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
435 | ASSERT (FALSE);\r |
436 | return;\r | |
437 | }\r | |
32e083c7 LE |
438 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
439 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
97380beb | 440 | \r |
0e20a186 | 441 | //\r |
e2ab3f81 GS |
442 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
443 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
444 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 445 | //\r |
e2ab3f81 | 446 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 447 | //\r |
e2ab3f81 | 448 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 449 | // 1. set PMBA\r |
eec7d420 | 450 | //\r |
1466b76f | 451 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r |
931a0c74 | 452 | \r |
453 | //\r | |
454 | // 2. set PCICMD/IOSE\r | |
455 | //\r | |
97380beb | 456 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 457 | \r |
458 | //\r | |
e2ab3f81 | 459 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 460 | //\r |
e2ab3f81 | 461 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 462 | }\r |
90721ba5 PA |
463 | \r |
464 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
465 | //\r | |
466 | // Set Root Complex Register Block BAR\r | |
467 | //\r | |
468 | PciWrite32 (\r | |
469 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
470 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
471 | );\r | |
7b8fe635 LE |
472 | \r |
473 | //\r | |
474 | // Set PCI Express Register Range Base Address\r | |
475 | //\r | |
476 | PciExBarInitialization ();\r | |
90721ba5 | 477 | }\r |
49ba9447 | 478 | }\r |
479 | \r | |
480 | \r | |
9ed65b10 | 481 | VOID\r |
482 | BootModeInitialization (\r | |
8f5ca05b | 483 | VOID\r |
9ed65b10 | 484 | )\r |
485 | {\r | |
8f5ca05b LE |
486 | EFI_STATUS Status;\r |
487 | \r | |
488 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 489 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 490 | }\r |
9be75189 | 491 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 492 | \r |
979420df | 493 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 494 | ASSERT_EFI_ERROR (Status);\r |
495 | \r | |
496 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
497 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 498 | }\r |
499 | \r | |
500 | \r | |
77ba993c | 501 | VOID\r |
502 | ReserveEmuVariableNvStore (\r | |
503 | )\r | |
504 | {\r | |
505 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
32e083c7 | 506 | RETURN_STATUS PcdStatus;\r |
77ba993c | 507 | \r |
508 | //\r | |
509 | // Allocate storage for NV variables early on so it will be\r | |
510 | // at a consistent address. Since VM memory is preserved\r | |
511 | // across reboots, this allows the NV variable storage to survive\r | |
512 | // a VM reboot.\r | |
513 | //\r | |
514 | VariableStore =\r | |
515 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
c9e7907d LE |
516 | AllocateRuntimePages (\r |
517 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r | |
27f58ea1 | 518 | );\r |
77ba993c | 519 | DEBUG ((EFI_D_INFO,\r |
c9e7907d | 520 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r |
77ba993c | 521 | VariableStore,\r |
c9e7907d | 522 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 523 | ));\r |
32e083c7 LE |
524 | PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r |
525 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
77ba993c | 526 | }\r |
527 | \r | |
528 | \r | |
3ca15914 | 529 | VOID\r |
530 | DebugDumpCmos (\r | |
531 | VOID\r | |
532 | )\r | |
533 | {\r | |
6394c35a | 534 | UINT32 Loop;\r |
3ca15914 | 535 | \r |
536 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
537 | \r | |
538 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
539 | if ((Loop % 0x10) == 0) {\r | |
540 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
541 | }\r | |
542 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
543 | if ((Loop % 0x10) == 0xf) {\r | |
544 | DEBUG ((EFI_D_INFO, "\n"));\r | |
545 | }\r | |
546 | }\r | |
547 | }\r | |
548 | \r | |
549 | \r | |
5133d1f1 LE |
550 | VOID\r |
551 | S3Verification (\r | |
552 | VOID\r | |
553 | )\r | |
554 | {\r | |
555 | #if defined (MDE_CPU_X64)\r | |
556 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
557 | DEBUG ((EFI_D_ERROR,\r | |
558 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
559 | DEBUG ((EFI_D_ERROR,\r | |
560 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
561 | __FUNCTION__));\r | |
562 | DEBUG ((EFI_D_ERROR,\r | |
563 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
564 | ASSERT (FALSE);\r | |
565 | CpuDeadLoop ();\r | |
566 | }\r | |
567 | #endif\r | |
568 | }\r | |
569 | \r | |
570 | \r | |
45a70db3 LE |
571 | /**\r |
572 | Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r | |
573 | Set the mMaxCpuCount variable.\r | |
574 | **/\r | |
575 | VOID\r | |
576 | MaxCpuCountInitialization (\r | |
577 | VOID\r | |
578 | )\r | |
579 | {\r | |
580 | UINT16 ProcessorCount;\r | |
581 | RETURN_STATUS PcdStatus;\r | |
582 | \r | |
583 | QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r | |
584 | ProcessorCount = QemuFwCfgRead16 ();\r | |
585 | //\r | |
586 | // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r | |
587 | // from the PCD default. No change to PCDs.\r | |
588 | //\r | |
589 | if (ProcessorCount == 0) {\r | |
590 | mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r | |
591 | return;\r | |
592 | }\r | |
593 | //\r | |
594 | // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r | |
595 | //\r | |
596 | mMaxCpuCount = ProcessorCount;\r | |
597 | //\r | |
598 | // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r | |
599 | // to wait, in the initial AP bringup, exactly as long as it takes for all of\r | |
600 | // the APs to report in. For this, we set the longest representable timeout\r | |
601 | // (approx. 71 minutes).\r | |
602 | //\r | |
603 | PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r | |
604 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
605 | PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r | |
606 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
607 | DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r | |
608 | ProcessorCount));\r | |
609 | }\r | |
610 | \r | |
611 | \r | |
49ba9447 | 612 | /**\r |
613 | Perform Platform PEI initialization.\r | |
614 | \r | |
615 | @param FileHandle Handle of the file being invoked.\r | |
616 | @param PeiServices Describes the list of possible PEI Services.\r | |
617 | \r | |
618 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
619 | \r | |
620 | **/\r | |
621 | EFI_STATUS\r | |
622 | EFIAPI\r | |
623 | InitializePlatform (\r | |
624 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
625 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
626 | )\r | |
627 | {\r | |
a1726e30 SZ |
628 | EFI_STATUS Status;\r |
629 | \r | |
7707c9fd | 630 | DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r |
49ba9447 | 631 | \r |
3ca15914 | 632 | DebugDumpCmos ();\r |
633 | \r | |
b98b4941 | 634 | XenDetect ();\r |
c7ea55b9 | 635 | \r |
7cdba634 JJ |
636 | if (QemuFwCfgS3Enabled ()) {\r |
637 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
638 | mS3Supported = TRUE;\r | |
a1726e30 SZ |
639 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r |
640 | ASSERT_EFI_ERROR (Status);\r | |
7cdba634 JJ |
641 | }\r |
642 | \r | |
5133d1f1 | 643 | S3Verification ();\r |
869b17cc | 644 | BootModeInitialization ();\r |
bc89fe48 | 645 | AddressWidthInitialization ();\r |
45a70db3 | 646 | MaxCpuCountInitialization ();\r |
869b17cc | 647 | \r |
d5e06444 LE |
648 | //\r |
649 | // Query Host Bridge DID\r | |
650 | //\r | |
651 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
652 | \r | |
23bfb5c0 LE |
653 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r |
654 | Q35TsegMbytesInitialization ();\r | |
655 | }\r | |
656 | \r | |
f76e9eba JJ |
657 | PublishPeiMemory ();\r |
658 | \r | |
2818c158 | 659 | InitializeRamRegions ();\r |
49ba9447 | 660 | \r |
b621bb0a | 661 | if (mXen) {\r |
c7ea55b9 | 662 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 663 | InitializeXen ();\r |
c7ea55b9 | 664 | }\r |
eec7d420 | 665 | \r |
bd386eaf | 666 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
5e167d7e LE |
667 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
668 | ReserveEmuVariableNvStore ();\r | |
669 | }\r | |
bd386eaf | 670 | PeiFvInitialization ();\r |
bd386eaf | 671 | MemMapInitialization ();\r |
ab081a50 | 672 | NoexecDxeInitialization ();\r |
bd386eaf | 673 | }\r |
49ba9447 | 674 | \r |
13b5d743 | 675 | AmdSevInitialize ();\r |
0e20a186 | 676 | MiscInitialization ();\r |
dbab9949 | 677 | InstallFeatureControlCallback ();\r |
49ba9447 | 678 | \r |
679 | return EFI_SUCCESS;\r | |
680 | }\r |