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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
a1726e30 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
b26f0cf9 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | //\r | |
12 | // The package level header files this module uses\r | |
13 | //\r | |
14 | #include <PiPei.h>\r | |
15 | \r | |
16 | //\r | |
17 | // The Library classes this module consumes\r | |
18 | //\r | |
5133d1f1 | 19 | #include <Library/BaseLib.h>\r |
49ba9447 | 20 | #include <Library/DebugLib.h>\r |
21 | #include <Library/HobLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
77ba993c | 23 | #include <Library/MemoryAllocationLib.h>\r |
24 | #include <Library/PcdLib.h>\r | |
49ba9447 | 25 | #include <Library/PciLib.h>\r |
26 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 27 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 28 | #include <Library/QemuFwCfgLib.h>\r |
687f7521 | 29 | #include <Library/QemuFwCfgS3Lib.h>\r |
b3c1bc1c | 30 | #include <Library/QemuFwCfgSimpleParserLib.h>\r |
49ba9447 | 31 | #include <Library/ResourcePublicationLib.h>\r |
9ed65b10 | 32 | #include <Ppi/MasterBootMode.h>\r |
83357313 | 33 | #include <IndustryStandard/I440FxPiix4.h>\r |
bf02d73e | 34 | #include <IndustryStandard/Microvm.h>\r |
931a0c74 | 35 | #include <IndustryStandard/Pci22.h>\r |
83357313 LE |
36 | #include <IndustryStandard/Q35MchIch9.h>\r |
37 | #include <IndustryStandard/QemuCpuHotplug.h>\r | |
97380beb | 38 | #include <OvmfPlatforms.h>\r |
49ba9447 | 39 | \r |
40 | #include "Platform.h"\r | |
3ca15914 | 41 | #include "Cmos.h"\r |
49ba9447 | 42 | \r |
9ed65b10 | 43 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
44 | {\r | |
45 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
46 | &gEfiPeiMasterBootModePpiGuid,\r | |
47 | NULL\r | |
48 | }\r | |
49 | };\r | |
50 | \r | |
51 | \r | |
589756c7 PA |
52 | UINT16 mHostBridgeDevId;\r |
53 | \r | |
979420df JJ |
54 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
55 | \r | |
7cdba634 JJ |
56 | BOOLEAN mS3Supported = FALSE;\r |
57 | \r | |
45a70db3 | 58 | UINT32 mMaxCpuCount;\r |
979420df | 59 | \r |
49ba9447 | 60 | VOID\r |
61 | AddIoMemoryBaseSizeHob (\r | |
62 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
63 | UINT64 MemorySize\r | |
64 | )\r | |
65 | {\r | |
991d9563 | 66 | BuildResourceDescriptorHob (\r |
67 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 68 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
69 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
70 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 71 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 72 | MemoryBase,\r |
73 | MemorySize\r | |
74 | );\r | |
75 | }\r | |
76 | \r | |
eec7d420 | 77 | VOID\r |
78 | AddReservedMemoryBaseSizeHob (\r | |
79 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
80 | UINT64 MemorySize,\r |
81 | BOOLEAN Cacheable\r | |
eec7d420 | 82 | )\r |
83 | {\r | |
84 | BuildResourceDescriptorHob (\r | |
85 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
86 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
87 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
88 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
89 | (Cacheable ?\r |
90 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
91 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
92 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
93 | 0\r | |
94 | ) |\r | |
eec7d420 | 95 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
96 | MemoryBase,\r | |
97 | MemorySize\r | |
98 | );\r | |
99 | }\r | |
49ba9447 | 100 | \r |
101 | VOID\r | |
102 | AddIoMemoryRangeHob (\r | |
103 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
104 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
105 | )\r | |
106 | {\r | |
107 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
108 | }\r | |
109 | \r | |
110 | \r | |
111 | VOID\r | |
112 | AddMemoryBaseSizeHob (\r | |
113 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
114 | UINT64 MemorySize\r | |
115 | )\r | |
116 | {\r | |
991d9563 | 117 | BuildResourceDescriptorHob (\r |
118 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 119 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
120 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
121 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
122 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
123 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
124 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 125 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 126 | MemoryBase,\r |
127 | MemorySize\r | |
128 | );\r | |
129 | }\r | |
130 | \r | |
131 | \r | |
132 | VOID\r | |
133 | AddMemoryRangeHob (\r | |
134 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
135 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
136 | )\r | |
137 | {\r | |
138 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
139 | }\r | |
140 | \r | |
c0e10976 | 141 | \r |
bb6a9a93 | 142 | VOID\r |
4b455f7b | 143 | MemMapInitialization (\r |
bb6a9a93 WL |
144 | VOID\r |
145 | )\r | |
146 | {\r | |
32e083c7 LE |
147 | UINT64 PciIoBase;\r |
148 | UINT64 PciIoSize;\r | |
149 | RETURN_STATUS PcdStatus;\r | |
d06eb2d1 LE |
150 | UINT32 TopOfLowRam;\r |
151 | UINT64 PciExBarBase;\r | |
152 | UINT32 PciBase;\r | |
153 | UINT32 PciSize;\r | |
c4df7fd0 LE |
154 | \r |
155 | PciIoBase = 0xC000;\r | |
156 | PciIoSize = 0x4000;\r | |
157 | \r | |
bb6a9a93 WL |
158 | //\r |
159 | // Video memory + Legacy BIOS region\r | |
160 | //\r | |
161 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
162 | \r | |
8583b57c | 163 | if (mHostBridgeDevId == 0xffff /* microvm */) {\r |
1d3e89f3 | 164 | AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r |
8583b57c GH |
165 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r |
166 | AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r | |
167 | return;\r | |
168 | }\r | |
169 | \r | |
d06eb2d1 LE |
170 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
171 | PciExBarBase = 0;\r | |
172 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
173 | //\r | |
174 | // The MMCONFIG area is expected to fall between the top of low RAM and\r | |
175 | // the base of the 32-bit PCI host aperture.\r | |
176 | //\r | |
177 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
178 | ASSERT (TopOfLowRam <= PciExBarBase);\r | |
179 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r | |
180 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r | |
181 | } else {\r | |
182 | ASSERT (TopOfLowRam <= mQemuUc32Base);\r | |
183 | PciBase = mQemuUc32Base;\r | |
184 | }\r | |
c68d3a69 | 185 | \r |
d06eb2d1 LE |
186 | //\r |
187 | // address purpose size\r | |
188 | // ------------ -------- -------------------------\r | |
189 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
190 | // 0xFC000000 gap 44 MB\r | |
191 | // 0xFEC00000 IO-APIC 4 KB\r | |
192 | // 0xFEC01000 gap 1020 KB\r | |
193 | // 0xFED00000 HPET 1 KB\r | |
194 | // 0xFED00400 gap 111 KB\r | |
195 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
196 | // 0xFED20000 gap 896 KB\r | |
197 | // 0xFEE00000 LAPIC 1 MB\r | |
198 | //\r | |
199 | PciSize = 0xFC000000 - PciBase;\r | |
200 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r | |
201 | PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r | |
202 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
203 | PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r | |
204 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
49ba9447 | 205 | \r |
d06eb2d1 LE |
206 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
207 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
208 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
209 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
4b455f7b | 210 | //\r |
d06eb2d1 | 211 | // Note: there should be an\r |
bba734ab | 212 | //\r |
d06eb2d1 | 213 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r |
bba734ab | 214 | //\r |
d06eb2d1 LE |
215 | // call below, just like the one above for RCBA. However, Linux insists\r |
216 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
217 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
218 | // in the memory map wherever the MCFG ACPI table points to.\r | |
219 | //\r | |
220 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
221 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
222 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
223 | // [...]". (Emphasis added here.)\r | |
224 | //\r | |
225 | // Normally we add memory resource descriptor HOBs in\r | |
226 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
227 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
228 | // is most definitely not RAM; so, as an exception, cover it with\r | |
229 | // uncacheable reserved memory right here.\r | |
230 | //\r | |
231 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
232 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
233 | EfiReservedMemoryType);\r | |
234 | }\r | |
235 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r | |
236 | \r | |
237 | //\r | |
238 | // On Q35, the IO Port space is available for PCI resource allocations from\r | |
239 | // 0x6000 up.\r | |
240 | //\r | |
241 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
242 | PciIoBase = 0x6000;\r | |
243 | PciIoSize = 0xA000;\r | |
244 | ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r | |
4b455f7b | 245 | }\r |
c4df7fd0 LE |
246 | \r |
247 | //\r | |
248 | // Add PCI IO Port space available for PCI resource allocations.\r | |
249 | //\r | |
250 | BuildResourceDescriptorHob (\r | |
251 | EFI_RESOURCE_IO,\r | |
252 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
253 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
254 | PciIoBase,\r | |
255 | PciIoSize\r | |
256 | );\r | |
32e083c7 LE |
257 | PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r |
258 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
259 | PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r | |
260 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
49ba9447 | 261 | }\r |
262 | \r | |
ab081a50 LE |
263 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r |
264 | do { \\r | |
32e083c7 LE |
265 | BOOLEAN Setting; \\r |
266 | RETURN_STATUS PcdStatus; \\r | |
ab081a50 | 267 | \\r |
b3c1bc1c | 268 | if (!RETURN_ERROR (QemuFwCfgParseBool ( \\r |
ab081a50 | 269 | "opt/ovmf/" #TokenName, &Setting))) { \\r |
32e083c7 LE |
270 | PcdStatus = PcdSetBoolS (TokenName, Setting); \\r |
271 | ASSERT_RETURN_ERROR (PcdStatus); \\r | |
ab081a50 LE |
272 | } \\r |
273 | } while (0)\r | |
274 | \r | |
275 | VOID\r | |
276 | NoexecDxeInitialization (\r | |
277 | VOID\r | |
278 | )\r | |
279 | {\r | |
ab081a50 LE |
280 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r |
281 | }\r | |
49ba9447 | 282 | \r |
7b8fe635 LE |
283 | VOID\r |
284 | PciExBarInitialization (\r | |
285 | VOID\r | |
286 | )\r | |
287 | {\r | |
288 | union {\r | |
289 | UINT64 Uint64;\r | |
290 | UINT32 Uint32[2];\r | |
291 | } PciExBarBase;\r | |
292 | \r | |
293 | //\r | |
294 | // We only support the 256MB size for the MMCONFIG area:\r | |
295 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
296 | //\r | |
297 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
298 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
299 | //\r | |
300 | // Note that (b) also ensures that the minimum address width we have\r | |
301 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
302 | // for DXE's page tables to cover the MMCONFIG area.\r | |
303 | //\r | |
304 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
305 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
306 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
307 | \r | |
308 | //\r | |
309 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
310 | //\r | |
311 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
312 | \r | |
313 | //\r | |
314 | // Program the high register. Then program the low register, setting the\r | |
315 | // MMCONFIG area size and enabling decoding at once.\r | |
316 | //\r | |
317 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
318 | PciWrite32 (\r | |
319 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
320 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
321 | );\r | |
322 | }\r | |
323 | \r | |
49ba9447 | 324 | VOID\r |
325 | MiscInitialization (\r | |
0e20a186 | 326 | VOID\r |
49ba9447 | 327 | )\r |
328 | {\r | |
32e083c7 LE |
329 | UINTN PmCmd;\r |
330 | UINTN Pmba;\r | |
331 | UINT32 PmbaAndVal;\r | |
332 | UINT32 PmbaOrVal;\r | |
333 | UINTN AcpiCtlReg;\r | |
334 | UINT8 AcpiEnBit;\r | |
335 | RETURN_STATUS PcdStatus;\r | |
97380beb | 336 | \r |
49ba9447 | 337 | //\r |
338 | // Disable A20 Mask\r | |
339 | //\r | |
55cdb67a | 340 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 341 | \r |
342 | //\r | |
86a14b0a LE |
343 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
344 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
345 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 346 | //\r |
86a14b0a | 347 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 348 | \r |
97380beb | 349 | //\r |
589756c7 | 350 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 351 | //\r |
589756c7 | 352 | switch (mHostBridgeDevId) {\r |
97380beb | 353 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 354 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 | 355 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
1466b76f LE |
356 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r |
357 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
da372167 LE |
358 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r |
359 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
360 | break;\r |
361 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 362 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 | 363 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
1466b76f LE |
364 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r |
365 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
bc9d05d6 LE |
366 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r |
367 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb | 368 | break;\r |
bf02d73e GH |
369 | case 0xffff: /* microvm */\r |
370 | DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r | |
371 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId,\r | |
372 | MICROVM_PSEUDO_DEVICE_ID);\r | |
373 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
374 | return;\r | |
97380beb | 375 | default:\r |
70d5086c | 376 | DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r |
589756c7 | 377 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
378 | ASSERT (FALSE);\r |
379 | return;\r | |
380 | }\r | |
32e083c7 LE |
381 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
382 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
97380beb | 383 | \r |
0e20a186 | 384 | //\r |
d06eb2d1 LE |
385 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has\r |
386 | // been configured and skip the setup here. This matches the logic in\r | |
387 | // AcpiTimerLibConstructor ().\r | |
0e20a186 | 388 | //\r |
e2ab3f81 | 389 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 390 | //\r |
e2ab3f81 | 391 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 392 | // 1. set PMBA\r |
eec7d420 | 393 | //\r |
1466b76f | 394 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r |
931a0c74 | 395 | \r |
396 | //\r | |
397 | // 2. set PCICMD/IOSE\r | |
398 | //\r | |
97380beb | 399 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 400 | \r |
401 | //\r | |
e2ab3f81 | 402 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 403 | //\r |
e2ab3f81 | 404 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 405 | }\r |
90721ba5 PA |
406 | \r |
407 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
408 | //\r | |
409 | // Set Root Complex Register Block BAR\r | |
410 | //\r | |
411 | PciWrite32 (\r | |
412 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
413 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
414 | );\r | |
7b8fe635 LE |
415 | \r |
416 | //\r | |
417 | // Set PCI Express Register Range Base Address\r | |
418 | //\r | |
419 | PciExBarInitialization ();\r | |
90721ba5 | 420 | }\r |
49ba9447 | 421 | }\r |
422 | \r | |
423 | \r | |
9ed65b10 | 424 | VOID\r |
425 | BootModeInitialization (\r | |
8f5ca05b | 426 | VOID\r |
9ed65b10 | 427 | )\r |
428 | {\r | |
8f5ca05b LE |
429 | EFI_STATUS Status;\r |
430 | \r | |
431 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 432 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 433 | }\r |
9be75189 | 434 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 435 | \r |
979420df | 436 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 437 | ASSERT_EFI_ERROR (Status);\r |
438 | \r | |
439 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
440 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 441 | }\r |
442 | \r | |
443 | \r | |
77ba993c | 444 | VOID\r |
445 | ReserveEmuVariableNvStore (\r | |
446 | )\r | |
447 | {\r | |
448 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
32e083c7 | 449 | RETURN_STATUS PcdStatus;\r |
77ba993c | 450 | \r |
451 | //\r | |
452 | // Allocate storage for NV variables early on so it will be\r | |
453 | // at a consistent address. Since VM memory is preserved\r | |
454 | // across reboots, this allows the NV variable storage to survive\r | |
455 | // a VM reboot.\r | |
456 | //\r | |
457 | VariableStore =\r | |
458 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
c9e7907d LE |
459 | AllocateRuntimePages (\r |
460 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r | |
27f58ea1 | 461 | );\r |
70d5086c | 462 | DEBUG ((DEBUG_INFO,\r |
c9e7907d | 463 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r |
77ba993c | 464 | VariableStore,\r |
c9e7907d | 465 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 466 | ));\r |
32e083c7 LE |
467 | PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r |
468 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
77ba993c | 469 | }\r |
470 | \r | |
471 | \r | |
3ca15914 | 472 | VOID\r |
473 | DebugDumpCmos (\r | |
474 | VOID\r | |
475 | )\r | |
476 | {\r | |
6394c35a | 477 | UINT32 Loop;\r |
3ca15914 | 478 | \r |
70d5086c | 479 | DEBUG ((DEBUG_INFO, "CMOS:\n"));\r |
3ca15914 | 480 | \r |
481 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
482 | if ((Loop % 0x10) == 0) {\r | |
70d5086c | 483 | DEBUG ((DEBUG_INFO, "%02x:", Loop));\r |
3ca15914 | 484 | }\r |
70d5086c | 485 | DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r |
3ca15914 | 486 | if ((Loop % 0x10) == 0xf) {\r |
70d5086c | 487 | DEBUG ((DEBUG_INFO, "\n"));\r |
3ca15914 | 488 | }\r |
489 | }\r | |
490 | }\r | |
491 | \r | |
492 | \r | |
5133d1f1 LE |
493 | VOID\r |
494 | S3Verification (\r | |
495 | VOID\r | |
496 | )\r | |
497 | {\r | |
498 | #if defined (MDE_CPU_X64)\r | |
499 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
70d5086c | 500 | DEBUG ((DEBUG_ERROR,\r |
5133d1f1 | 501 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r |
70d5086c | 502 | DEBUG ((DEBUG_ERROR,\r |
5133d1f1 LE |
503 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r |
504 | __FUNCTION__));\r | |
70d5086c | 505 | DEBUG ((DEBUG_ERROR,\r |
5133d1f1 LE |
506 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r |
507 | ASSERT (FALSE);\r | |
508 | CpuDeadLoop ();\r | |
509 | }\r | |
510 | #endif\r | |
511 | }\r | |
512 | \r | |
513 | \r | |
e0ed7a9b LE |
514 | VOID\r |
515 | Q35BoardVerification (\r | |
516 | VOID\r | |
517 | )\r | |
518 | {\r | |
519 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
520 | return;\r | |
521 | }\r | |
522 | \r | |
523 | DEBUG ((\r | |
524 | DEBUG_ERROR,\r | |
525 | "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r | |
526 | "only DID=0x%04x (Q35) is supported\n",\r | |
527 | __FUNCTION__,\r | |
528 | mHostBridgeDevId,\r | |
529 | INTEL_Q35_MCH_DEVICE_ID\r | |
530 | ));\r | |
531 | ASSERT (FALSE);\r | |
532 | CpuDeadLoop ();\r | |
533 | }\r | |
534 | \r | |
535 | \r | |
45a70db3 | 536 | /**\r |
83357313 LE |
537 | Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r |
538 | them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r | |
45a70db3 LE |
539 | **/\r |
540 | VOID\r | |
541 | MaxCpuCountInitialization (\r | |
542 | VOID\r | |
543 | )\r | |
544 | {\r | |
83357313 | 545 | UINT16 BootCpuCount;\r |
45a70db3 LE |
546 | RETURN_STATUS PcdStatus;\r |
547 | \r | |
45a70db3 | 548 | //\r |
83357313 | 549 | // Try to fetch the boot CPU count.\r |
45a70db3 | 550 | //\r |
83357313 LE |
551 | QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r |
552 | BootCpuCount = QemuFwCfgRead16 ();\r | |
553 | if (BootCpuCount == 0) {\r | |
554 | //\r | |
555 | // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let\r | |
556 | // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or\r | |
557 | // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached\r | |
558 | // first).\r | |
559 | //\r | |
560 | DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));\r | |
45a70db3 | 561 | mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r |
83357313 LE |
562 | } else {\r |
563 | //\r | |
564 | // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to\r | |
565 | // (BootCpuCount - 1) precisely, regardless of timeout.\r | |
566 | //\r | |
567 | // Now try to fetch the possible CPU count.\r | |
568 | //\r | |
569 | UINTN CpuHpBase;\r | |
570 | UINT32 CmdData2;\r | |
571 | \r | |
572 | CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r | |
573 | ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r | |
574 | \r | |
575 | //\r | |
576 | // If only legacy mode is available in the CPU hotplug register block, or\r | |
577 | // the register block is completely missing, then the writes below are\r | |
578 | // no-ops.\r | |
579 | //\r | |
580 | // 1. Switch the hotplug register block to modern mode.\r | |
581 | //\r | |
582 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r | |
583 | //\r | |
584 | // 2. Select a valid CPU for deterministic reading of\r | |
585 | // QEMU_CPUHP_R_CMD_DATA2.\r | |
586 | //\r | |
587 | // CPU#0 is always valid; it is the always present and non-removable\r | |
588 | // BSP.\r | |
589 | //\r | |
590 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r | |
591 | //\r | |
592 | // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to\r | |
593 | // read as zero, and which does not invalidate the selector. (The\r | |
594 | // selector may change, but it must not become invalid.)\r | |
595 | //\r | |
596 | // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.\r | |
597 | //\r | |
598 | IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);\r | |
599 | //\r | |
600 | // 4. Read QEMU_CPUHP_R_CMD_DATA2.\r | |
601 | //\r | |
602 | // If the register block is entirely missing, then this is an unassigned\r | |
603 | // IO read, returning all-bits-one.\r | |
604 | //\r | |
605 | // If only legacy mode is available, then bit#0 stands for CPU#0 in the\r | |
606 | // "CPU present bitmap". CPU#0 is always present.\r | |
607 | //\r | |
608 | // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning\r | |
609 | // all-bits-zero), or it is specified to read as zero after the above\r | |
610 | // steps. Both cases confirm modern mode.\r | |
611 | //\r | |
612 | CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);\r | |
613 | DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));\r | |
614 | if (CmdData2 != 0) {\r | |
615 | //\r | |
616 | // QEMU doesn't support the modern CPU hotplug interface. Assume that the\r | |
617 | // possible CPU count equals the boot CPU count (precluding hotplug).\r | |
618 | //\r | |
619 | DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",\r | |
620 | __FUNCTION__));\r | |
621 | mMaxCpuCount = BootCpuCount;\r | |
622 | } else {\r | |
623 | //\r | |
624 | // Grab the possible CPU count from the modern CPU hotplug interface.\r | |
625 | //\r | |
626 | UINT32 Present, Possible, Selected;\r | |
627 | \r | |
628 | Present = 0;\r | |
629 | Possible = 0;\r | |
630 | \r | |
631 | //\r | |
632 | // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures\r | |
633 | // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,\r | |
634 | // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending\r | |
635 | // hotplug events; therefore, select CPU#0 forcibly.\r | |
636 | //\r | |
637 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r | |
638 | \r | |
639 | do {\r | |
640 | UINT8 CpuStatus;\r | |
641 | \r | |
642 | //\r | |
643 | // Read the status of the currently selected CPU. This will help with a\r | |
644 | // sanity check against "BootCpuCount".\r | |
645 | //\r | |
646 | CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);\r | |
647 | if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {\r | |
648 | ++Present;\r | |
649 | }\r | |
650 | //\r | |
651 | // Attempt to select the next CPU.\r | |
652 | //\r | |
653 | ++Possible;\r | |
654 | IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r | |
655 | //\r | |
656 | // If the selection is successful, then the following read will return\r | |
657 | // the selector (which we know is positive at this point). Otherwise,\r | |
658 | // the read will return 0.\r | |
659 | //\r | |
660 | Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);\r | |
661 | ASSERT (Selected == Possible || Selected == 0);\r | |
662 | } while (Selected > 0);\r | |
663 | \r | |
664 | //\r | |
665 | // Sanity check: fw_cfg and the modern CPU hotplug interface should\r | |
666 | // return the same boot CPU count.\r | |
667 | //\r | |
668 | if (BootCpuCount != Present) {\r | |
669 | DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "\r | |
670 | "Present=%u\n", __FUNCTION__, BootCpuCount, Present));\r | |
671 | //\r | |
672 | // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus\r | |
673 | // platform reset (including S3), was corrected in QEMU commit\r | |
674 | // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added\r | |
675 | // CPUs", 2016-11-16), part of release v2.8.0.\r | |
676 | //\r | |
677 | BootCpuCount = (UINT16)Present;\r | |
678 | }\r | |
679 | \r | |
680 | mMaxCpuCount = Possible;\r | |
681 | }\r | |
45a70db3 | 682 | }\r |
83357313 LE |
683 | \r |
684 | DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,\r | |
685 | BootCpuCount, mMaxCpuCount));\r | |
686 | ASSERT (BootCpuCount <= mMaxCpuCount);\r | |
687 | \r | |
688 | PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);\r | |
45a70db3 | 689 | ASSERT_RETURN_ERROR (PcdStatus);\r |
83357313 | 690 | PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);\r |
45a70db3 | 691 | ASSERT_RETURN_ERROR (PcdStatus);\r |
45a70db3 LE |
692 | }\r |
693 | \r | |
694 | \r | |
49ba9447 | 695 | /**\r |
696 | Perform Platform PEI initialization.\r | |
697 | \r | |
698 | @param FileHandle Handle of the file being invoked.\r | |
699 | @param PeiServices Describes the list of possible PEI Services.\r | |
700 | \r | |
701 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
702 | \r | |
703 | **/\r | |
704 | EFI_STATUS\r | |
705 | EFIAPI\r | |
706 | InitializePlatform (\r | |
707 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
708 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
709 | )\r | |
710 | {\r | |
a1726e30 SZ |
711 | EFI_STATUS Status;\r |
712 | \r | |
7707c9fd | 713 | DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r |
49ba9447 | 714 | \r |
3ca15914 | 715 | DebugDumpCmos ();\r |
716 | \r | |
7cdba634 | 717 | if (QemuFwCfgS3Enabled ()) {\r |
70d5086c | 718 | DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r |
7cdba634 | 719 | mS3Supported = TRUE;\r |
a1726e30 SZ |
720 | Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r |
721 | ASSERT_EFI_ERROR (Status);\r | |
7cdba634 JJ |
722 | }\r |
723 | \r | |
5133d1f1 | 724 | S3Verification ();\r |
869b17cc | 725 | BootModeInitialization ();\r |
bc89fe48 | 726 | AddressWidthInitialization ();\r |
869b17cc | 727 | \r |
d5e06444 LE |
728 | //\r |
729 | // Query Host Bridge DID\r | |
730 | //\r | |
731 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
732 | \r | |
83357313 LE |
733 | MaxCpuCountInitialization ();\r |
734 | \r | |
23bfb5c0 | 735 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r |
e0ed7a9b | 736 | Q35BoardVerification ();\r |
23bfb5c0 | 737 | Q35TsegMbytesInitialization ();\r |
73974f80 | 738 | Q35SmramAtDefaultSmbaseInitialization ();\r |
23bfb5c0 LE |
739 | }\r |
740 | \r | |
f76e9eba JJ |
741 | PublishPeiMemory ();\r |
742 | \r | |
49edde15 LE |
743 | QemuUc32BaseInitialization ();\r |
744 | \r | |
2818c158 | 745 | InitializeRamRegions ();\r |
49ba9447 | 746 | \r |
bd386eaf | 747 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
5e167d7e LE |
748 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
749 | ReserveEmuVariableNvStore ();\r | |
750 | }\r | |
bd386eaf | 751 | PeiFvInitialization ();\r |
d42fdd6f | 752 | MemTypeInfoInitialization ();\r |
bd386eaf | 753 | MemMapInitialization ();\r |
ab081a50 | 754 | NoexecDxeInitialization ();\r |
bd386eaf | 755 | }\r |
49ba9447 | 756 | \r |
d20ae95a | 757 | InstallClearCacheCallback ();\r |
13b5d743 | 758 | AmdSevInitialize ();\r |
0e20a186 | 759 | MiscInitialization ();\r |
dbab9949 | 760 | InstallFeatureControlCallback ();\r |
49ba9447 | 761 | \r |
762 | return EFI_SUCCESS;\r | |
763 | }\r |