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KVM: SVM: implement NEXTRIPsave SVM feature
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
6bc31bdc
AP		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
49#define SVM_FEATURE_SVML (1 << 2)
50#define SVM_FEATURE_NRIP (1 << 3)
51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
ce2ac085 82 u64 vmcb_iopm;
aad42c64 83
cd3ff653
JR		 84 /* A VMEXIT is required but not yet emulated */
85 bool exit_required;
86
aad42c64
JR		 87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read;
89 u16 intercept_cr_write;
90 u16 intercept_dr_read;
91 u16 intercept_dr_write;
92 u32 intercept_exceptions;
93 u64 intercept;
94
e6aa9abd
JR		 95};
96
323c3d80
JR		 97#define MSRPM_OFFSETS 16
98static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
99
6c8166a7
AK		 100struct vcpu_svm {
101 struct kvm_vcpu vcpu;
102 struct vmcb *vmcb;
103 unsigned long vmcb_pa;
104 struct svm_cpu_data *svm_data;
105 uint64_t asid_generation;
106 uint64_t sysenter_esp;
107 uint64_t sysenter_eip;
108
109 u64 next_rip;
110
111 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
112 u64 host_gs_base;
6c8166a7
AK		 113
114 u32 *msrpm;
6c8166a7 115
e6aa9abd 116 struct nested_state nested;
6be7d306
JK		 117
118 bool nmi_singlestep;
66b7138f
JK		 119
120 unsigned int3_injected;
121 unsigned long int3_rip;
6c8166a7
AK		 122};
123
455716fa
JR		 124#define MSR_INVALID 0xffffffffU
125
ac72a9b7
JR		 126static struct svm_direct_access_msrs {
127 u32 index; /* Index of the MSR */
128 bool always; /* True if intercept is always on */
129} direct_access_msrs[] = {
130 { .index = MSR_K6_STAR, .always = true },
131 { .index = MSR_IA32_SYSENTER_CS, .always = true },
132#ifdef CONFIG_X86_64
133 { .index = MSR_GS_BASE, .always = true },
134 { .index = MSR_FS_BASE, .always = true },
135 { .index = MSR_KERNEL_GS_BASE, .always = true },
136 { .index = MSR_LSTAR, .always = true },
137 { .index = MSR_CSTAR, .always = true },
138 { .index = MSR_SYSCALL_MASK, .always = true },
139#endif
140 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
141 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
142 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
143 { .index = MSR_IA32_LASTINTTOIP, .always = false },
144 { .index = MSR_INVALID, .always = false },
145};
146
709ddebf
JR		 147/* enable NPT for AMD64 and X86 with PAE */
148#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
149static bool npt_enabled = true;
150#else
e0231715 151static bool npt_enabled;
709ddebf 152#endif
6c7dac72
JR		 153static int npt = 1;
154
155module_param(npt, int, S_IRUGO);
e3da3acd 156
4b6e4dca 157static int nested = 1;
236de055
AG		 158module_param(nested, int, S_IRUGO);
159
44874f84 160static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 161static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 162
410e4d57 163static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 164static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 165static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 166static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
167 bool has_error_code, u32 error_code);
168
a2fa3e9f
GH		 169static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
170{
fb3f0f51 171 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 172}
173
3d6368ef
AG		 174static inline bool is_nested(struct vcpu_svm *svm)
175{
e6aa9abd 176 return svm->nested.vmcb;
3d6368ef
AG		 177}
178
2af9194d
JR		 179static inline void enable_gif(struct vcpu_svm *svm)
180{
181 svm->vcpu.arch.hflags |= HF_GIF_MASK;
182}
183
184static inline void disable_gif(struct vcpu_svm *svm)
185{
186 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
187}
188
189static inline bool gif_set(struct vcpu_svm *svm)
190{
191 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
192}
193
4866d5e3 194static unsigned long iopm_base;
6aa8b732
AK		 195
196struct kvm_ldttss_desc {
197 u16 limit0;
198 u16 base0;
e0231715
JR		 199 unsigned base1:8, type:5, dpl:2, p:1;
200 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 201 u32 base3;
202 u32 zero1;
203} __attribute__((packed));
204
205struct svm_cpu_data {
206 int cpu;
207
5008fdf5
AK		 208 u64 asid_generation;
209 u32 max_asid;
210 u32 next_asid;
6aa8b732
AK		 211 struct kvm_ldttss_desc *tss_desc;
212
213 struct page *save_area;
214};
215
216static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 217static uint32_t svm_features;
6aa8b732
AK		 218
219struct svm_init_data {
220 int cpu;
221 int r;
222};
223
224static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
225
9d8f549d 226#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 227#define MSRS_RANGE_SIZE 2048
228#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
229
455716fa
JR		 230static u32 svm_msrpm_offset(u32 msr)
231{
232 u32 offset;
233 int i;
234
235 for (i = 0; i < NUM_MSR_MAPS; i++) {
236 if (msr < msrpm_ranges[i] ||
237 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
238 continue;
239
240 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
241 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
242
243 /* Now we have the u8 offset - but need the u32 offset */
244 return offset / 4;
245 }
246
247 /* MSR not in any range */
248 return MSR_INVALID;
249}
250
6aa8b732
AK		 251#define MAX_INST_SIZE 15
252
80b7706e
JR		 253static inline u32 svm_has(u32 feat)
254{
255 return svm_features & feat;
256}
257
6aa8b732
AK		 258static inline void clgi(void)
259{
4ecac3fd 260 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 261}
262
263static inline void stgi(void)
264{
4ecac3fd 265 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 266}
267
268static inline void invlpga(unsigned long addr, u32 asid)
269{
e0231715 270 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 271}
272
6aa8b732
AK		 273static inline void force_new_asid(struct kvm_vcpu *vcpu)
274{
a2fa3e9f 275 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 276}
277
278static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
279{
280 force_new_asid(vcpu);
281}
282
283static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
284{
709ddebf 285 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 286 efer &= ~EFER_LME;
6aa8b732 287
9962d032 288 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 289 vcpu->arch.efer = efer;
6aa8b732
AK		 290}
291
6aa8b732
AK		 292static int is_external_interrupt(u32 info)
293{
294 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
295 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
296}
297
2809f5d2
GC		 298static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
299{
300 struct vcpu_svm *svm = to_svm(vcpu);
301 u32 ret = 0;
302
303 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 304 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 305 return ret & mask;
306}
307
308static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
309{
310 struct vcpu_svm *svm = to_svm(vcpu);
311
312 if (mask == 0)
313 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
314 else
315 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
316
317}
318
6aa8b732
AK		 319static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
320{
a2fa3e9f
GH		 321 struct vcpu_svm *svm = to_svm(vcpu);
322
6bc31bdc
AP		 323 if (svm->vmcb->control.next_rip != 0)
324 svm->next_rip = svm->vmcb->control.next_rip;
325
a2fa3e9f 326 if (!svm->next_rip) {
851ba692 327 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 328 EMULATE_DONE)
329 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 330 return;
331 }
5fdbf976
MT		 332 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
333 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
334 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 335
5fdbf976 336 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 337 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 338}
339
116a4752
JK		 340static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
341 bool has_error_code, u32 error_code)
342{
343 struct vcpu_svm *svm = to_svm(vcpu);
344
e0231715
JR		 345 /*
346 * If we are within a nested VM we'd better #VMEXIT and let the guest
347 * handle the exception
348 */
116a4752
JK		 349 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
350 return;
351
66b7138f
JK		 352 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
353 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
354
355 /*
356 * For guest debugging where we have to reinject #BP if some
357 * INT3 is guest-owned:
358 * Emulate nRIP by moving RIP forward. Will fail if injection
359 * raises a fault that is not intercepted. Still better than
360 * failing in all cases.
361 */
362 skip_emulated_instruction(&svm->vcpu);
363 rip = kvm_rip_read(&svm->vcpu);
364 svm->int3_rip = rip + svm->vmcb->save.cs.base;
365 svm->int3_injected = rip - old_rip;
366 }
367
116a4752
JK		 368 svm->vmcb->control.event_inj = nr
369 | SVM_EVTINJ_VALID
370 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
371 | SVM_EVTINJ_TYPE_EXEPT;
372 svm->vmcb->control.event_inj_err = error_code;
373}
374
6aa8b732
AK		 375static int has_svm(void)
376{
63d1142f 377 const char *msg;
6aa8b732 378
63d1142f 379 if (!cpu_has_svm(&msg)) {
ff81ff10 380 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 381 return 0;
382 }
383
6aa8b732
AK		 384 return 1;
385}
386
387static void svm_hardware_disable(void *garbage)
388{
2c8dceeb 389 cpu_svm_disable();
6aa8b732
AK		 390}
391
10474ae8 392static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 393{
394
0fe1e009 395 struct svm_cpu_data *sd;
6aa8b732 396 uint64_t efer;
89a27f4d 397 struct desc_ptr gdt_descr;
6aa8b732
AK		 398 struct desc_struct *gdt;
399 int me = raw_smp_processor_id();
400
10474ae8
AG		 401 rdmsrl(MSR_EFER, efer);
402 if (efer & EFER_SVME)
403 return -EBUSY;
404
6aa8b732 405 if (!has_svm()) {
e6732a5a
ZA		 406 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
407 me);
10474ae8 408 return -EINVAL;
6aa8b732 409 }
0fe1e009 410 sd = per_cpu(svm_data, me);
6aa8b732 411
0fe1e009 412 if (!sd) {
e6732a5a 413 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 414 me);
10474ae8 415 return -EINVAL;
6aa8b732
AK		 416 }
417
0fe1e009
TH		 418 sd->asid_generation = 1;
419 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
420 sd->next_asid = sd->max_asid + 1;
6aa8b732 421
d6ab1ed4 422 native_store_gdt(&gdt_descr);
89a27f4d 423 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 424 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 425
9962d032 426 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 427
d0316554 428 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 429
430 return 0;
6aa8b732
AK		 431}
432
0da1db75
JR		 433static void svm_cpu_uninit(int cpu)
434{
0fe1e009 435 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 436
0fe1e009 437 if (!sd)
0da1db75
JR		 438 return;
439
440 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 441 __free_page(sd->save_area);
442 kfree(sd);
0da1db75
JR		 443}
444
6aa8b732
AK		 445static int svm_cpu_init(int cpu)
446{
0fe1e009 447 struct svm_cpu_data *sd;
6aa8b732
AK		 448 int r;
449
0fe1e009
TH		 450 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
451 if (!sd)
6aa8b732 452 return -ENOMEM;
0fe1e009
TH		 453 sd->cpu = cpu;
454 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 455 r = -ENOMEM;
0fe1e009 456 if (!sd->save_area)
6aa8b732
AK		 457 goto err_1;
458
0fe1e009 459 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 460
461 return 0;
462
463err_1:
0fe1e009 464 kfree(sd);
6aa8b732
AK		 465 return r;
466
467}
468
ac72a9b7
JR		 469static bool valid_msr_intercept(u32 index)
470{
471 int i;
472
473 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
474 if (direct_access_msrs[i].index == index)
475 return true;
476
477 return false;
478}
479
bfc733a7
RR		 480static void set_msr_interception(u32 *msrpm, unsigned msr,
481 int read, int write)
6aa8b732 482{
455716fa
JR		 483 u8 bit_read, bit_write;
484 unsigned long tmp;
485 u32 offset;
6aa8b732 486
ac72a9b7
JR		 487 /*
488 * If this warning triggers extend the direct_access_msrs list at the
489 * beginning of the file
490 */
491 WARN_ON(!valid_msr_intercept(msr));
492
455716fa
JR		 493 offset = svm_msrpm_offset(msr);
494 bit_read = 2 * (msr & 0x0f);
495 bit_write = 2 * (msr & 0x0f) + 1;
496 tmp = msrpm[offset];
497
498 BUG_ON(offset == MSR_INVALID);
499
500 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
501 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
502
503 msrpm[offset] = tmp;
6aa8b732
AK		 504}
505
f65c229c
JR		 506static void svm_vcpu_init_msrpm(u32 *msrpm)
507{
ac72a9b7
JR		 508 int i;
509
f65c229c
JR		 510 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
511
ac72a9b7
JR		 512 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
513 if (!direct_access_msrs[i].always)
514 continue;
515
516 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
517 }
f65c229c
JR		 518}
519
323c3d80
JR		 520static void add_msr_offset(u32 offset)
521{
522 int i;
523
524 for (i = 0; i < MSRPM_OFFSETS; ++i) {
525
526 /* Offset already in list? */
527 if (msrpm_offsets[i] == offset)
528 return;
529
530 /* Slot used by another offset? */
531 if (msrpm_offsets[i] != MSR_INVALID)
532 continue;
533
534 /* Add offset to list */
535 msrpm_offsets[i] = offset;
536
537 return;
538 }
539
540 /*
541 * If this BUG triggers the msrpm_offsets table has an overflow. Just
542 * increase MSRPM_OFFSETS in this case.
543 */
544 BUG();
545}
546
547static void init_msrpm_offsets(void)
548{
549 int i;
550
551 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
552
553 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
554 u32 offset;
555
556 offset = svm_msrpm_offset(direct_access_msrs[i].index);
557 BUG_ON(offset == MSR_INVALID);
558
559 add_msr_offset(offset);
560 }
561}
562
24e09cbf
JR		 563static void svm_enable_lbrv(struct vcpu_svm *svm)
564{
565 u32 *msrpm = svm->msrpm;
566
567 svm->vmcb->control.lbr_ctl = 1;
568 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
569 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
570 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
571 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
572}
573
574static void svm_disable_lbrv(struct vcpu_svm *svm)
575{
576 u32 *msrpm = svm->msrpm;
577
578 svm->vmcb->control.lbr_ctl = 0;
579 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
580 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
581 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
582 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
583}
584
6aa8b732
AK		 585static __init int svm_hardware_setup(void)
586{
587 int cpu;
588 struct page *iopm_pages;
f65c229c 589 void *iopm_va;
6aa8b732
AK		 590 int r;
591
6aa8b732
AK		 592 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
593
594 if (!iopm_pages)
595 return -ENOMEM;
c8681339
AL		 596
597 iopm_va = page_address(iopm_pages);
598 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 599 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
600
323c3d80
JR		 601 init_msrpm_offsets();
602
50a37eb4
JR		 603 if (boot_cpu_has(X86_FEATURE_NX))
604 kvm_enable_efer_bits(EFER_NX);
605
1b2fd70c
AG		 606 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
607 kvm_enable_efer_bits(EFER_FFXSR);
608
236de055
AG		 609 if (nested) {
610 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
611 kvm_enable_efer_bits(EFER_SVME);
612 }
613
3230bb47 614 for_each_possible_cpu(cpu) {
6aa8b732
AK		 615 r = svm_cpu_init(cpu);
616 if (r)
f65c229c 617 goto err;
6aa8b732 618 }
33bd6a0b
JR		 619
620 svm_features = cpuid_edx(SVM_CPUID_FUNC);
621
e3da3acd
JR		 622 if (!svm_has(SVM_FEATURE_NPT))
623 npt_enabled = false;
624
6c7dac72
JR		 625 if (npt_enabled && !npt) {
626 printk(KERN_INFO "kvm: Nested Paging disabled\n");
627 npt_enabled = false;
628 }
629
18552672 630 if (npt_enabled) {
e3da3acd 631 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 632 kvm_enable_tdp();
5f4cb662
JR		 633 } else
634 kvm_disable_tdp();
e3da3acd 635
6aa8b732
AK		 636 return 0;
637
f65c229c 638err:
6aa8b732
AK		 639 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
640 iopm_base = 0;
641 return r;
642}
643
644static __exit void svm_hardware_unsetup(void)
645{
0da1db75
JR		 646 int cpu;
647
3230bb47 648 for_each_possible_cpu(cpu)
0da1db75
JR		 649 svm_cpu_uninit(cpu);
650
6aa8b732 651 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 652 iopm_base = 0;
6aa8b732
AK		 653}
654
655static void init_seg(struct vmcb_seg *seg)
656{
657 seg->selector = 0;
658 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 659 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 660 seg->limit = 0xffff;
661 seg->base = 0;
662}
663
664static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
665{
666 seg->selector = 0;
667 seg->attrib = SVM_SELECTOR_P_MASK | type;
668 seg->limit = 0xffff;
669 seg->base = 0;
670}
671
e6101a96 672static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 673{
e6101a96
JR		 674 struct vmcb_control_area *control = &svm->vmcb->control;
675 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 676
bff78274
AK		 677 svm->vcpu.fpu_active = 1;
678
e0231715 679 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 680 INTERCEPT_CR3_MASK |
649d6864 681 INTERCEPT_CR4_MASK;
6aa8b732 682
e0231715 683 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 684 INTERCEPT_CR3_MASK |
80a8119c
AK		 685 INTERCEPT_CR4_MASK |
686 INTERCEPT_CR8_MASK;
6aa8b732 687
e0231715 688 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 689 INTERCEPT_DR1_MASK |
690 INTERCEPT_DR2_MASK |
727f5a23
JK		 691 INTERCEPT_DR3_MASK |
692 INTERCEPT_DR4_MASK |
693 INTERCEPT_DR5_MASK |
694 INTERCEPT_DR6_MASK |
695 INTERCEPT_DR7_MASK;
6aa8b732 696
e0231715 697 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 698 INTERCEPT_DR1_MASK |
699 INTERCEPT_DR2_MASK |
700 INTERCEPT_DR3_MASK |
727f5a23 701 INTERCEPT_DR4_MASK |
6aa8b732 702 INTERCEPT_DR5_MASK |
727f5a23 703 INTERCEPT_DR6_MASK |
6aa8b732
AK		 704 INTERCEPT_DR7_MASK;
705
7aa81cc0 706 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 707 (1 << UD_VECTOR) |
708 (1 << MC_VECTOR);
6aa8b732
AK		 709
710
e0231715 711 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 712 (1ULL << INTERCEPT_NMI) |
0152527b 713 (1ULL << INTERCEPT_SMI) |
d225157b 714 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 715 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 716 (1ULL << INTERCEPT_INVD) |
6aa8b732 717 (1ULL << INTERCEPT_HLT) |
a7052897 718 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 719 (1ULL << INTERCEPT_INVLPGA) |
720 (1ULL << INTERCEPT_IOIO_PROT) |
721 (1ULL << INTERCEPT_MSR_PROT) |
722 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 723 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 724 (1ULL << INTERCEPT_VMRUN) |
725 (1ULL << INTERCEPT_VMMCALL) |
726 (1ULL << INTERCEPT_VMLOAD) |
727 (1ULL << INTERCEPT_VMSAVE) |
728 (1ULL << INTERCEPT_STGI) |
729 (1ULL << INTERCEPT_CLGI) |
916ce236 730 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 731 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 732 (1ULL << INTERCEPT_MONITOR) |
733 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 734
735 control->iopm_base_pa = iopm_base;
f65c229c 736 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 737 control->tsc_offset = 0;
6aa8b732
AK		 738 control->int_ctl = V_INTR_MASKING_MASK;
739
740 init_seg(&save->es);
741 init_seg(&save->ss);
742 init_seg(&save->ds);
743 init_seg(&save->fs);
744 init_seg(&save->gs);
745
746 save->cs.selector = 0xf000;
747 /* Executable/Readable Code Segment */
748 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
749 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
750 save->cs.limit = 0xffff;
d92899a0
AK		 751 /*
752 * cs.base should really be 0xffff0000, but vmx can't handle that, so
753 * be consistent with it.
754 *
755 * Replace when we have real mode working for vmx.
756 */
757 save->cs.base = 0xf0000;
6aa8b732
AK		 758
759 save->gdtr.limit = 0xffff;
760 save->idtr.limit = 0xffff;
761
762 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
763 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
764
9962d032 765 save->efer = EFER_SVME;
d77c26fc 766 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 767 save->dr7 = 0x400;
768 save->rflags = 2;
769 save->rip = 0x0000fff0;
5fdbf976 770 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 771
e0231715
JR		 772 /*
773 * This is the guest-visible cr0 value.
18fa000a 774 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 775 */
18fa000a
EH		 776 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
777 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
778
66aee91a 779 save->cr4 = X86_CR4_PAE;
6aa8b732 780 /* rdx = ?? */
709ddebf
JR		 781
782 if (npt_enabled) {
783 /* Setup VMCB for Nested Paging */
784 control->nested_ctl = 1;
a7052897
MT		 785 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
786 (1ULL << INTERCEPT_INVLPG));
709ddebf 787 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 788 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
789 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 790 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 791 save->cr3 = 0;
792 save->cr4 = 0;
793 }
a79d2f18 794 force_new_asid(&svm->vcpu);
1371d904 795
e6aa9abd 796 svm->nested.vmcb = 0;
2af9194d
JR		 797 svm->vcpu.arch.hflags = 0;
798
565d0998
ML		 799 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
800 control->pause_filter_count = 3000;
801 control->intercept |= (1ULL << INTERCEPT_PAUSE);
802 }
803
2af9194d 804 enable_gif(svm);
6aa8b732
AK		 805}
806
e00c8cf2 807static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 808{
809 struct vcpu_svm *svm = to_svm(vcpu);
810
e6101a96 811 init_vmcb(svm);
70433389 812
c5af89b6 813 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 814 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 815 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
816 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 817 }
5fdbf976
MT		 818 vcpu->arch.regs_avail = ~0;
819 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 820
821 return 0;
04d2cc77
AK		 822}
823
fb3f0f51 824static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 825{
a2fa3e9f 826 struct vcpu_svm *svm;
6aa8b732 827 struct page *page;
f65c229c 828 struct page *msrpm_pages;
b286d5d8 829 struct page *hsave_page;
3d6368ef 830 struct page *nested_msrpm_pages;
fb3f0f51 831 int err;
6aa8b732 832
c16f862d 833 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 834 if (!svm) {
835 err = -ENOMEM;
836 goto out;
837 }
838
839 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
840 if (err)
841 goto free_svm;
842
b7af4043 843 err = -ENOMEM;
6aa8b732 844 page = alloc_page(GFP_KERNEL);
b7af4043 845 if (!page)
fb3f0f51 846 goto uninit;
6aa8b732 847
f65c229c
JR		 848 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
849 if (!msrpm_pages)
b7af4043 850 goto free_page1;
3d6368ef
AG		 851
852 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
853 if (!nested_msrpm_pages)
b7af4043 854 goto free_page2;
f65c229c 855
b286d5d8
AG		 856 hsave_page = alloc_page(GFP_KERNEL);
857 if (!hsave_page)
b7af4043
TY		 858 goto free_page3;
859
e6aa9abd 860 svm->nested.hsave = page_address(hsave_page);
b286d5d8 861
b7af4043
TY		 862 svm->msrpm = page_address(msrpm_pages);
863 svm_vcpu_init_msrpm(svm->msrpm);
864
e6aa9abd 865 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 866 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 867
a2fa3e9f
GH		 868 svm->vmcb = page_address(page);
869 clear_page(svm->vmcb);
870 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
871 svm->asid_generation = 0;
e6101a96 872 init_vmcb(svm);
a2fa3e9f 873
fb3f0f51 874 fx_init(&svm->vcpu);
ad312c7c 875 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 876 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 877 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 878
fb3f0f51 879 return &svm->vcpu;
36241b8c 880
b7af4043
TY		 881free_page3:
882 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
883free_page2:
884 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
885free_page1:
886 __free_page(page);
fb3f0f51
RR		 887uninit:
888 kvm_vcpu_uninit(&svm->vcpu);
889free_svm:
a4770347 890 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 891out:
892 return ERR_PTR(err);
6aa8b732
AK		 893}
894
895static void svm_free_vcpu(struct kvm_vcpu *vcpu)
896{
a2fa3e9f
GH		 897 struct vcpu_svm *svm = to_svm(vcpu);
898
fb3f0f51 899 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 900 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 901 __free_page(virt_to_page(svm->nested.hsave));
902 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 903 kvm_vcpu_uninit(vcpu);
a4770347 904 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 905}
906
15ad7146 907static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 908{
a2fa3e9f 909 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 910 int i;
0cc5064d 911
0cc5064d 912 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 913 u64 delta;
0cc5064d 914
953899b6
JR		 915 if (check_tsc_unstable()) {
916 /*
917 * Make sure that the guest sees a monotonically
918 * increasing TSC.
919 */
920 delta = vcpu->arch.host_tsc - native_read_tsc();
921 svm->vmcb->control.tsc_offset += delta;
922 if (is_nested(svm))
923 svm->nested.hsave->control.tsc_offset += delta;
924 }
0cc5064d 925 vcpu->cpu = cpu;
2f599714 926 kvm_migrate_timers(vcpu);
4b656b12 927 svm->asid_generation = 0;
0cc5064d 928 }
94dfbdb3
AL		 929
930 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 931 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 932}
933
934static void svm_vcpu_put(struct kvm_vcpu *vcpu)
935{
a2fa3e9f 936 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 937 int i;
938
e1beb1d3 939 ++vcpu->stat.host_state_reload;
94dfbdb3 940 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 941 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 942
e935d48e 943 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 944}
945
6aa8b732
AK		 946static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
947{
a2fa3e9f 948 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 949}
950
951static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
952{
a2fa3e9f 953 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 954}
955
6de4f3ad
AK		 956static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
957{
958 switch (reg) {
959 case VCPU_EXREG_PDPTR:
960 BUG_ON(!npt_enabled);
961 load_pdptrs(vcpu, vcpu->arch.cr3);
962 break;
963 default:
964 BUG();
965 }
966}
967
f0b85051
AG		 968static void svm_set_vintr(struct vcpu_svm *svm)
969{
970 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
971}
972
973static void svm_clear_vintr(struct vcpu_svm *svm)
974{
975 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
976}
977
6aa8b732
AK		 978static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
979{
a2fa3e9f 980 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 981
982 switch (seg) {
983 case VCPU_SREG_CS: return &save->cs;
984 case VCPU_SREG_DS: return &save->ds;
985 case VCPU_SREG_ES: return &save->es;
986 case VCPU_SREG_FS: return &save->fs;
987 case VCPU_SREG_GS: return &save->gs;
988 case VCPU_SREG_SS: return &save->ss;
989 case VCPU_SREG_TR: return &save->tr;
990 case VCPU_SREG_LDTR: return &save->ldtr;
991 }
992 BUG();
8b6d44c7 993 return NULL;
6aa8b732
AK		 994}
995
996static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
997{
998 struct vmcb_seg *s = svm_seg(vcpu, seg);
999
1000 return s->base;
1001}
1002
1003static void svm_get_segment(struct kvm_vcpu *vcpu,
1004 struct kvm_segment *var, int seg)
1005{
1006 struct vmcb_seg *s = svm_seg(vcpu, seg);
1007
1008 var->base = s->base;
1009 var->limit = s->limit;
1010 var->selector = s->selector;
1011 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1012 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1013 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1014 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1015 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1016 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1017 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1018 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1019
e0231715
JR		 1020 /*
1021 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1022 * for cross vendor migration purposes by "not present"
1023 */
1024 var->unusable = !var->present || (var->type == 0);
1025
1fbdc7a5
AP		 1026 switch (seg) {
1027 case VCPU_SREG_CS:
1028 /*
1029 * SVM always stores 0 for the 'G' bit in the CS selector in
1030 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1031 * Intel's VMENTRY has a check on the 'G' bit.
1032 */
25022acc 1033 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1034 break;
1035 case VCPU_SREG_TR:
1036 /*
1037 * Work around a bug where the busy flag in the tr selector
1038 * isn't exposed
1039 */
c0d09828 1040 var->type |= 0x2;
1fbdc7a5
AP		 1041 break;
1042 case VCPU_SREG_DS:
1043 case VCPU_SREG_ES:
1044 case VCPU_SREG_FS:
1045 case VCPU_SREG_GS:
1046 /*
1047 * The accessed bit must always be set in the segment
1048 * descriptor cache, although it can be cleared in the
1049 * descriptor, the cached bit always remains at 1. Since
1050 * Intel has a check on this, set it here to support
1051 * cross-vendor migration.
1052 */
1053 if (!var->unusable)
1054 var->type |= 0x1;
1055 break;
b586eb02 1056 case VCPU_SREG_SS:
e0231715
JR		 1057 /*
1058 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1059 * descriptor is left as 1, although the whole segment has
1060 * been made unusable. Clear it here to pass an Intel VMX
1061 * entry check when cross vendor migrating.
1062 */
1063 if (var->unusable)
1064 var->db = 0;
1065 break;
1fbdc7a5 1066 }
6aa8b732
AK		 1067}
1068
2e4d2653
IE		 1069static int svm_get_cpl(struct kvm_vcpu *vcpu)
1070{
1071 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1072
1073 return save->cpl;
1074}
1075
89a27f4d 1076static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1077{
a2fa3e9f
GH		 1078 struct vcpu_svm *svm = to_svm(vcpu);
1079
89a27f4d
GN		 1080 dt->size = svm->vmcb->save.idtr.limit;
1081 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1082}
1083
89a27f4d 1084static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1085{
a2fa3e9f
GH		 1086 struct vcpu_svm *svm = to_svm(vcpu);
1087
89a27f4d
GN		 1088 svm->vmcb->save.idtr.limit = dt->size;
1089 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1090}
1091
89a27f4d 1092static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1093{
a2fa3e9f
GH		 1094 struct vcpu_svm *svm = to_svm(vcpu);
1095
89a27f4d
GN		 1096 dt->size = svm->vmcb->save.gdtr.limit;
1097 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1098}
1099
89a27f4d 1100static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1101{
a2fa3e9f
GH		 1102 struct vcpu_svm *svm = to_svm(vcpu);
1103
89a27f4d
GN		 1104 svm->vmcb->save.gdtr.limit = dt->size;
1105 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1106}
1107
e8467fda
AK		 1108static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1109{
1110}
1111
25c4c276 1112static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1113{
1114}
1115
d225157b
AK		 1116static void update_cr0_intercept(struct vcpu_svm *svm)
1117{
66a562f7 1118 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1119 ulong gcr0 = svm->vcpu.arch.cr0;
1120 u64 *hcr0 = &svm->vmcb->save.cr0;
1121
1122 if (!svm->vcpu.fpu_active)
1123 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1124 else
1125 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1126 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1127
1128
1129 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1130 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1131 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1132 if (is_nested(svm)) {
1133 struct vmcb *hsave = svm->nested.hsave;
1134
1135 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1136 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1137 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1138 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1139 }
d225157b
AK		 1140 } else {
1141 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1142 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1143 if (is_nested(svm)) {
1144 struct vmcb *hsave = svm->nested.hsave;
1145
1146 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1147 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1148 }
d225157b
AK		 1149 }
1150}
1151
6aa8b732
AK		 1152static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1153{
a2fa3e9f
GH		 1154 struct vcpu_svm *svm = to_svm(vcpu);
1155
7f5d8b56
JR		 1156 if (is_nested(svm)) {
1157 /*
1158 * We are here because we run in nested mode, the host kvm
1159 * intercepts cr0 writes but the l1 hypervisor does not.
1160 * But the L1 hypervisor may intercept selective cr0 writes.
1161 * This needs to be checked here.
1162 */
1163 unsigned long old, new;
1164
1165 /* Remove bits that would trigger a real cr0 write intercept */
1166 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1167 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1168
1169 if (old == new) {
1170 /* cr0 write with ts and mp unchanged */
1171 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1172 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1173 return;
1174 }
1175 }
1176
05b3e0c2 1177#ifdef CONFIG_X86_64
f6801dff 1178 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1179 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1180 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1181 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1182 }
1183
d77c26fc 1184 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1185 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1186 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1187 }
1188 }
1189#endif
ad312c7c 1190 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1191
1192 if (!npt_enabled)
1193 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1194
1195 if (!vcpu->fpu_active)
334df50a 1196 cr0 |= X86_CR0_TS;
709ddebf
JR		 1197 /*
1198 * re-enable caching here because the QEMU bios
1199 * does not do it - this results in some delay at
1200 * reboot
1201 */
1202 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1203 svm->vmcb->save.cr0 = cr0;
d225157b 1204 update_cr0_intercept(svm);
6aa8b732
AK		 1205}
1206
1207static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1208{
6394b649 1209 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1210 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1211
1212 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1213 force_new_asid(vcpu);
6394b649 1214
ec077263
JR		 1215 vcpu->arch.cr4 = cr4;
1216 if (!npt_enabled)
1217 cr4 |= X86_CR4_PAE;
6394b649 1218 cr4 |= host_cr4_mce;
ec077263 1219 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1220}
1221
1222static void svm_set_segment(struct kvm_vcpu *vcpu,
1223 struct kvm_segment *var, int seg)
1224{
a2fa3e9f 1225 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1226 struct vmcb_seg *s = svm_seg(vcpu, seg);
1227
1228 s->base = var->base;
1229 s->limit = var->limit;
1230 s->selector = var->selector;
1231 if (var->unusable)
1232 s->attrib = 0;
1233 else {
1234 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1235 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1236 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1237 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1238 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1239 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1240 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1241 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1242 }
1243 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1244 svm->vmcb->save.cpl
1245 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1246 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1247
1248}
1249
44c11430 1250static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1251{
d0bfb940
JK		 1252 struct vcpu_svm *svm = to_svm(vcpu);
1253
d0bfb940
JK		 1254 svm->vmcb->control.intercept_exceptions &=
1255 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1256
6be7d306 1257 if (svm->nmi_singlestep)
44c11430
GN		 1258 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1259
d0bfb940
JK		 1260 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1261 if (vcpu->guest_debug &
1262 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1263 svm->vmcb->control.intercept_exceptions |=
1264 1 << DB_VECTOR;
1265 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1266 svm->vmcb->control.intercept_exceptions |=
1267 1 << BP_VECTOR;
1268 } else
1269 vcpu->guest_debug = 0;
44c11430
GN		 1270}
1271
355be0b9 1272static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1273{
44c11430
GN		 1274 struct vcpu_svm *svm = to_svm(vcpu);
1275
ae675ef0
JK		 1276 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1277 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1278 else
1279 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1280
355be0b9 1281 update_db_intercept(vcpu);
6aa8b732
AK		 1282}
1283
1284static void load_host_msrs(struct kvm_vcpu *vcpu)
1285{
94dfbdb3 1286#ifdef CONFIG_X86_64
a2fa3e9f 1287 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1288#endif
6aa8b732
AK		 1289}
1290
1291static void save_host_msrs(struct kvm_vcpu *vcpu)
1292{
94dfbdb3 1293#ifdef CONFIG_X86_64
a2fa3e9f 1294 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1295#endif
6aa8b732
AK		 1296}
1297
0fe1e009 1298static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1299{
0fe1e009
TH		 1300 if (sd->next_asid > sd->max_asid) {
1301 ++sd->asid_generation;
1302 sd->next_asid = 1;
a2fa3e9f 1303 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1304 }
1305
0fe1e009
TH		 1306 svm->asid_generation = sd->asid_generation;
1307 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1308}
1309
c76de350 1310static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1311{
42dbaa5a 1312 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1313
1314 switch (dr) {
1315 case 0 ... 3:
c76de350 1316 *dest = vcpu->arch.db[dr];
42dbaa5a 1317 break;
c76de350
JK		 1318 case 4:
1319 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1320 return EMULATE_FAIL; /* will re-inject UD */
1321 /* fall through */
42dbaa5a
JK		 1322 case 6:
1323 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1324 *dest = vcpu->arch.dr6;
42dbaa5a 1325 else
c76de350 1326 *dest = svm->vmcb->save.dr6;
42dbaa5a 1327 break;
c76de350
JK		 1328 case 5:
1329 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1330 return EMULATE_FAIL; /* will re-inject UD */
1331 /* fall through */
42dbaa5a
JK		 1332 case 7:
1333 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1334 *dest = vcpu->arch.dr7;
42dbaa5a 1335 else
c76de350 1336 *dest = svm->vmcb->save.dr7;
42dbaa5a 1337 break;
42dbaa5a
JK		 1338 }
1339
c76de350 1340 return EMULATE_DONE;
6aa8b732
AK		 1341}
1342
c76de350 1343static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1344{
a2fa3e9f
GH		 1345 struct vcpu_svm *svm = to_svm(vcpu);
1346
6aa8b732
AK		 1347 switch (dr) {
1348 case 0 ... 3:
42dbaa5a
JK		 1349 vcpu->arch.db[dr] = value;
1350 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1351 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1352 break;
1353 case 4:
1354 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1355 return EMULATE_FAIL; /* will re-inject UD */
1356 /* fall through */
42dbaa5a 1357 case 6:
42dbaa5a 1358 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1359 break;
1360 case 5:
1361 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1362 return EMULATE_FAIL; /* will re-inject UD */
1363 /* fall through */
42dbaa5a 1364 case 7:
42dbaa5a
JK		 1365 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1366 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1367 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1368 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1369 }
c76de350 1370 break;
6aa8b732 1371 }
c76de350
JK		 1372
1373 return EMULATE_DONE;
6aa8b732
AK		 1374}
1375
851ba692 1376static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1377{
6aa8b732
AK		 1378 u64 fault_address;
1379 u32 error_code;
6aa8b732 1380
a2fa3e9f
GH		 1381 fault_address = svm->vmcb->control.exit_info_2;
1382 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1383
229456fc 1384 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1385 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1386 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1387 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1388}
1389
851ba692 1390static int db_interception(struct vcpu_svm *svm)
d0bfb940 1391{
851ba692
AK		 1392 struct kvm_run *kvm_run = svm->vcpu.run;
1393
d0bfb940 1394 if (!(svm->vcpu.guest_debug &
44c11430 1395 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1396 !svm->nmi_singlestep) {
d0bfb940
JK		 1397 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1398 return 1;
1399 }
44c11430 1400
6be7d306
JK		 1401 if (svm->nmi_singlestep) {
1402 svm->nmi_singlestep = false;
44c11430
GN		 1403 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1404 svm->vmcb->save.rflags &=
1405 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1406 update_db_intercept(&svm->vcpu);
1407 }
1408
1409 if (svm->vcpu.guest_debug &
e0231715 1410 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1411 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1412 kvm_run->debug.arch.pc =
1413 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1414 kvm_run->debug.arch.exception = DB_VECTOR;
1415 return 0;
1416 }
1417
1418 return 1;
d0bfb940
JK		 1419}
1420
851ba692 1421static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1422{
851ba692
AK		 1423 struct kvm_run *kvm_run = svm->vcpu.run;
1424
d0bfb940
JK		 1425 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1426 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1427 kvm_run->debug.arch.exception = BP_VECTOR;
1428 return 0;
1429}
1430
851ba692 1431static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1432{
1433 int er;
1434
851ba692 1435 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1436 if (er != EMULATE_DONE)
7ee5d940 1437 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1438 return 1;
1439}
1440
6b52d186 1441static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1442{
6b52d186 1443 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1444 u32 excp;
1445
1446 if (is_nested(svm)) {
1447 u32 h_excp, n_excp;
1448
1449 h_excp = svm->nested.hsave->control.intercept_exceptions;
1450 n_excp = svm->nested.intercept_exceptions;
1451 h_excp &= ~(1 << NM_VECTOR);
1452 excp = h_excp | n_excp;
1453 } else {
1454 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1455 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1456 }
1457
1458 svm->vmcb->control.intercept_exceptions = excp;
1459
e756fc62 1460 svm->vcpu.fpu_active = 1;
d225157b 1461 update_cr0_intercept(svm);
6b52d186 1462}
a2fa3e9f 1463
6b52d186
AK		 1464static int nm_interception(struct vcpu_svm *svm)
1465{
1466 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1467 return 1;
7807fa6c
AL		 1468}
1469
851ba692 1470static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1471{
1472 /*
1473 * On an #MC intercept the MCE handler is not called automatically in
1474 * the host. So do it by hand here.
1475 */
1476 asm volatile (
1477 "int $0x12\n");
1478 /* not sure if we ever come back to this point */
1479
1480 return 1;
1481}
1482
851ba692 1483static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1484{
851ba692
AK		 1485 struct kvm_run *kvm_run = svm->vcpu.run;
1486
46fe4ddd
JR		 1487 /*
1488 * VMCB is undefined after a SHUTDOWN intercept
1489 * so reinitialize it.
1490 */
a2fa3e9f 1491 clear_page(svm->vmcb);
e6101a96 1492 init_vmcb(svm);
46fe4ddd
JR		 1493
1494 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1495 return 0;
1496}
1497
851ba692 1498static int io_interception(struct vcpu_svm *svm)
6aa8b732 1499{
cf8f70bf 1500 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1501 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1502 int size, in, string;
039576c0 1503 unsigned port;
6aa8b732 1504
e756fc62 1505 ++svm->vcpu.stat.io_exits;
e70669ab 1506 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1507 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf
GN		 1508 if (string || in)
1509 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1510
039576c0
AK		 1511 port = io_info >> 16;
1512 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1513 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1514 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1515
1516 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1517}
1518
851ba692 1519static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1520{
1521 return 1;
1522}
1523
851ba692 1524static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1525{
1526 ++svm->vcpu.stat.irq_exits;
1527 return 1;
1528}
1529
851ba692 1530static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1531{
1532 return 1;
1533}
1534
851ba692 1535static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1536{
5fdbf976 1537 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1538 skip_emulated_instruction(&svm->vcpu);
1539 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1540}
1541
851ba692 1542static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1543{
5fdbf976 1544 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1545 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1546 kvm_emulate_hypercall(&svm->vcpu);
1547 return 1;
02e235bc
AK		 1548}
1549
c0725420
AG		 1550static int nested_svm_check_permissions(struct vcpu_svm *svm)
1551{
f6801dff 1552 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1553 || !is_paging(&svm->vcpu)) {
1554 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1555 return 1;
1556 }
1557
1558 if (svm->vmcb->save.cpl) {
1559 kvm_inject_gp(&svm->vcpu, 0);
1560 return 1;
1561 }
1562
1563 return 0;
1564}
1565
cf74a78b
AG		 1566static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1567 bool has_error_code, u32 error_code)
1568{
b8e88bc8
JR		 1569 int vmexit;
1570
0295ad7d
JR		 1571 if (!is_nested(svm))
1572 return 0;
cf74a78b 1573
0295ad7d
JR		 1574 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1575 svm->vmcb->control.exit_code_hi = 0;
1576 svm->vmcb->control.exit_info_1 = error_code;
1577 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1578
b8e88bc8
JR		 1579 vmexit = nested_svm_intercept(svm);
1580 if (vmexit == NESTED_EXIT_DONE)
1581 svm->nested.exit_required = true;
1582
1583 return vmexit;
cf74a78b
AG		 1584}
1585
8fe54654
JR		 1586/* This function returns true if it is save to enable the irq window */
1587static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1588{
26666957 1589 if (!is_nested(svm))
8fe54654 1590 return true;
cf74a78b 1591
26666957 1592 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1593 return true;
cf74a78b 1594
26666957 1595 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1596 return false;
cf74a78b 1597
197717d5
JR		 1598 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1599 svm->vmcb->control.exit_info_1 = 0;
1600 svm->vmcb->control.exit_info_2 = 0;
26666957 1601
cd3ff653
JR		 1602 if (svm->nested.intercept & 1ULL) {
1603 /*
1604 * The #vmexit can't be emulated here directly because this
1605 * code path runs with irqs and preemtion disabled. A
1606 * #vmexit emulation might sleep. Only signal request for
1607 * the #vmexit here.
1608 */
1609 svm->nested.exit_required = true;
236649de 1610 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1611 return false;
cf74a78b
AG		 1612 }
1613
8fe54654 1614 return true;
cf74a78b
AG		 1615}
1616
887f500c
JR		 1617/* This function returns true if it is save to enable the nmi window */
1618static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1619{
1620 if (!is_nested(svm))
1621 return true;
1622
1623 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1624 return true;
1625
1626 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1627 svm->nested.exit_required = true;
1628
1629 return false;
1630}
1631
7597f129 1632static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1633{
1634 struct page *page;
1635
6c3bd3d7
JR		 1636 might_sleep();
1637
34f80cfa 1638 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1639 if (is_error_page(page))
1640 goto error;
1641
7597f129
JR		 1642 *_page = page;
1643
1644 return kmap(page);
34f80cfa
JR		 1645
1646error:
1647 kvm_release_page_clean(page);
1648 kvm_inject_gp(&svm->vcpu, 0);
1649
1650 return NULL;
1651}
1652
7597f129 1653static void nested_svm_unmap(struct page *page)
34f80cfa 1654{
7597f129 1655 kunmap(page);
34f80cfa
JR		 1656 kvm_release_page_dirty(page);
1657}
1658
ce2ac085
JR		 1659static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1660{
1661 unsigned port;
1662 u8 val, bit;
1663 u64 gpa;
1664
1665 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1666 return NESTED_EXIT_HOST;
1667
1668 port = svm->vmcb->control.exit_info_1 >> 16;
1669 gpa = svm->nested.vmcb_iopm + (port / 8);
1670 bit = port % 8;
1671 val = 0;
1672
1673 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1674 val &= (1 << bit);
1675
1676 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1677}
1678
d2477826 1679static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1680{
0d6b3537
JR		 1681 u32 offset, msr, value;
1682 int write, mask;
4c2161ae 1683
3d62d9aa 1684 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1685 return NESTED_EXIT_HOST;
3d62d9aa 1686
0d6b3537
JR		 1687 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1688 offset = svm_msrpm_offset(msr);
1689 write = svm->vmcb->control.exit_info_1 & 1;
1690 mask = 1 << ((2 * (msr & 0xf)) + write);
4c2161ae 1691
0d6b3537
JR		 1692 if (offset == MSR_INVALID)
1693 return NESTED_EXIT_DONE;
3d62d9aa 1694
0d6b3537
JR		 1695 /* Offset is in 32 bit units but need in 8 bit units */
1696 offset *= 4;
1697
1698 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1699 return NESTED_EXIT_DONE;
1700
1701 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1702}
1703
410e4d57 1704static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1705{
cf74a78b 1706 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1707
410e4d57
JR		 1708 switch (exit_code) {
1709 case SVM_EXIT_INTR:
1710 case SVM_EXIT_NMI:
1711 return NESTED_EXIT_HOST;
410e4d57 1712 case SVM_EXIT_NPF:
e0231715 1713 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1714 if (npt_enabled)
1715 return NESTED_EXIT_HOST;
1716 break;
410e4d57 1717 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1718 /* When we're shadowing, trap PFs */
410e4d57
JR		 1719 if (!npt_enabled)
1720 return NESTED_EXIT_HOST;
1721 break;
66a562f7
JR		 1722 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1723 nm_interception(svm);
1724 break;
410e4d57
JR		 1725 default:
1726 break;
cf74a78b
AG		 1727 }
1728
410e4d57
JR		 1729 return NESTED_EXIT_CONTINUE;
1730}
1731
1732/*
1733 * If this function returns true, this #vmexit was already handled
1734 */
b8e88bc8 1735static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1736{
1737 u32 exit_code = svm->vmcb->control.exit_code;
1738 int vmexit = NESTED_EXIT_HOST;
1739
cf74a78b 1740 switch (exit_code) {
9c4e40b9 1741 case SVM_EXIT_MSR:
3d62d9aa 1742 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1743 break;
ce2ac085
JR		 1744 case SVM_EXIT_IOIO:
1745 vmexit = nested_svm_intercept_ioio(svm);
1746 break;
cf74a78b
AG		 1747 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1748 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1749 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1750 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1751 break;
1752 }
1753 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1754 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1755 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1756 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1757 break;
1758 }
1759 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1760 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1761 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1762 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1763 break;
1764 }
1765 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1766 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1767 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1768 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1769 break;
1770 }
1771 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1772 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1773 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1774 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1775 break;
1776 }
1777 default: {
1778 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1779 if (svm->nested.intercept & exit_bits)
410e4d57 1780 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1781 }
1782 }
1783
b8e88bc8
JR		 1784 return vmexit;
1785}
1786
1787static int nested_svm_exit_handled(struct vcpu_svm *svm)
1788{
1789 int vmexit;
1790
1791 vmexit = nested_svm_intercept(svm);
1792
1793 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1794 nested_svm_vmexit(svm);
9c4e40b9
JR		 1795
1796 return vmexit;
cf74a78b
AG		 1797}
1798
0460a979
JR		 1799static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1800{
1801 struct vmcb_control_area *dst = &dst_vmcb->control;
1802 struct vmcb_control_area *from = &from_vmcb->control;
1803
1804 dst->intercept_cr_read = from->intercept_cr_read;
1805 dst->intercept_cr_write = from->intercept_cr_write;
1806 dst->intercept_dr_read = from->intercept_dr_read;
1807 dst->intercept_dr_write = from->intercept_dr_write;
1808 dst->intercept_exceptions = from->intercept_exceptions;
1809 dst->intercept = from->intercept;
1810 dst->iopm_base_pa = from->iopm_base_pa;
1811 dst->msrpm_base_pa = from->msrpm_base_pa;
1812 dst->tsc_offset = from->tsc_offset;
1813 dst->asid = from->asid;
1814 dst->tlb_ctl = from->tlb_ctl;
1815 dst->int_ctl = from->int_ctl;
1816 dst->int_vector = from->int_vector;
1817 dst->int_state = from->int_state;
1818 dst->exit_code = from->exit_code;
1819 dst->exit_code_hi = from->exit_code_hi;
1820 dst->exit_info_1 = from->exit_info_1;
1821 dst->exit_info_2 = from->exit_info_2;
1822 dst->exit_int_info = from->exit_int_info;
1823 dst->exit_int_info_err = from->exit_int_info_err;
1824 dst->nested_ctl = from->nested_ctl;
1825 dst->event_inj = from->event_inj;
1826 dst->event_inj_err = from->event_inj_err;
1827 dst->nested_cr3 = from->nested_cr3;
1828 dst->lbr_ctl = from->lbr_ctl;
1829}
1830
34f80cfa 1831static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1832{
34f80cfa 1833 struct vmcb *nested_vmcb;
e6aa9abd 1834 struct vmcb *hsave = svm->nested.hsave;
33740e40 1835 struct vmcb *vmcb = svm->vmcb;
7597f129 1836 struct page *page;
cf74a78b 1837
17897f36
JR		 1838 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1839 vmcb->control.exit_info_1,
1840 vmcb->control.exit_info_2,
1841 vmcb->control.exit_int_info,
1842 vmcb->control.exit_int_info_err);
1843
7597f129 1844 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1845 if (!nested_vmcb)
1846 return 1;
1847
06fc7772
JR		 1848 /* Exit nested SVM mode */
1849 svm->nested.vmcb = 0;
1850
cf74a78b 1851 /* Give the current vmcb to the guest */
33740e40
JR		 1852 disable_gif(svm);
1853
1854 nested_vmcb->save.es = vmcb->save.es;
1855 nested_vmcb->save.cs = vmcb->save.cs;
1856 nested_vmcb->save.ss = vmcb->save.ss;
1857 nested_vmcb->save.ds = vmcb->save.ds;
1858 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1859 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1860 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1861 if (npt_enabled)
1862 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1863 else
1864 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1865 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1866 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1867 nested_vmcb->save.rflags = vmcb->save.rflags;
1868 nested_vmcb->save.rip = vmcb->save.rip;
1869 nested_vmcb->save.rsp = vmcb->save.rsp;
1870 nested_vmcb->save.rax = vmcb->save.rax;
1871 nested_vmcb->save.dr7 = vmcb->save.dr7;
1872 nested_vmcb->save.dr6 = vmcb->save.dr6;
1873 nested_vmcb->save.cpl = vmcb->save.cpl;
1874
1875 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1876 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1877 nested_vmcb->control.int_state = vmcb->control.int_state;
1878 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1879 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1880 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1881 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1882 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1883 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1884
1885 /*
1886 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1887 * to make sure that we do not lose injected events. So check event_inj
1888 * here and copy it to exit_int_info if it is valid.
1889 * Exit_int_info and event_inj can't be both valid because the case
1890 * below only happens on a VMRUN instruction intercept which has
1891 * no valid exit_int_info set.
1892 */
1893 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1894 struct vmcb_control_area *nc = &nested_vmcb->control;
1895
1896 nc->exit_int_info = vmcb->control.event_inj;
1897 nc->exit_int_info_err = vmcb->control.event_inj_err;
1898 }
1899
33740e40
JR		 1900 nested_vmcb->control.tlb_ctl = 0;
1901 nested_vmcb->control.event_inj = 0;
1902 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1903
1904 /* We always set V_INTR_MASKING and remember the old value in hflags */
1905 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1906 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1907
cf74a78b 1908 /* Restore the original control entries */
0460a979 1909 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1910
219b65dc
AG		 1911 kvm_clear_exception_queue(&svm->vcpu);
1912 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1913
1914 /* Restore selected save entries */
1915 svm->vmcb->save.es = hsave->save.es;
1916 svm->vmcb->save.cs = hsave->save.cs;
1917 svm->vmcb->save.ss = hsave->save.ss;
1918 svm->vmcb->save.ds = hsave->save.ds;
1919 svm->vmcb->save.gdtr = hsave->save.gdtr;
1920 svm->vmcb->save.idtr = hsave->save.idtr;
1921 svm->vmcb->save.rflags = hsave->save.rflags;
1922 svm_set_efer(&svm->vcpu, hsave->save.efer);
1923 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1924 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1925 if (npt_enabled) {
1926 svm->vmcb->save.cr3 = hsave->save.cr3;
1927 svm->vcpu.arch.cr3 = hsave->save.cr3;
1928 } else {
1929 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1930 }
1931 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1932 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1933 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1934 svm->vmcb->save.dr7 = 0;
1935 svm->vmcb->save.cpl = 0;
1936 svm->vmcb->control.exit_int_info = 0;
1937
7597f129 1938 nested_svm_unmap(page);
cf74a78b
AG		 1939
1940 kvm_mmu_reset_context(&svm->vcpu);
1941 kvm_mmu_load(&svm->vcpu);
1942
1943 return 0;
1944}
3d6368ef 1945
9738b2c9 1946static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1947{
323c3d80
JR		 1948 /*
1949 * This function merges the msr permission bitmaps of kvm and the
1950 * nested vmcb. It is omptimized in that it only merges the parts where
1951 * the kvm msr permission bitmap may contain zero bits
1952 */
3d6368ef 1953 int i;
9738b2c9 1954
323c3d80
JR		 1955 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1956 return true;
9738b2c9 1957
323c3d80
JR		 1958 for (i = 0; i < MSRPM_OFFSETS; i++) {
1959 u32 value, p;
1960 u64 offset;
9738b2c9 1961
323c3d80
JR		 1962 if (msrpm_offsets[i] == 0xffffffff)
1963 break;
3d6368ef 1964
0d6b3537
JR		 1965 p = msrpm_offsets[i];
1966 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 1967
1968 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1969 return false;
1970
1971 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1972 }
1973
1974 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 1975
1976 return true;
3d6368ef
AG		 1977}
1978
9738b2c9 1979static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1980{
9738b2c9 1981 struct vmcb *nested_vmcb;
e6aa9abd 1982 struct vmcb *hsave = svm->nested.hsave;
defbba56 1983 struct vmcb *vmcb = svm->vmcb;
7597f129 1984 struct page *page;
06fc7772
JR		 1985 u64 vmcb_gpa;
1986
1987 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1988
7597f129 1989 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1990 if (!nested_vmcb)
1991 return false;
1992
ecf1405d 1993 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1994 nested_vmcb->save.rip,
1995 nested_vmcb->control.int_ctl,
1996 nested_vmcb->control.event_inj,
1997 nested_vmcb->control.nested_ctl);
1998
2e554e8d
JR		 1999 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2000 nested_vmcb->control.intercept_cr_write,
2001 nested_vmcb->control.intercept_exceptions,
2002 nested_vmcb->control.intercept);
2003
3d6368ef 2004 /* Clear internal status */
219b65dc
AG		 2005 kvm_clear_exception_queue(&svm->vcpu);
2006 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2007
e0231715
JR		 2008 /*
2009 * Save the old vmcb, so we don't need to pick what we save, but can
2010 * restore everything when a VMEXIT occurs
2011 */
defbba56
JR		 2012 hsave->save.es = vmcb->save.es;
2013 hsave->save.cs = vmcb->save.cs;
2014 hsave->save.ss = vmcb->save.ss;
2015 hsave->save.ds = vmcb->save.ds;
2016 hsave->save.gdtr = vmcb->save.gdtr;
2017 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2018 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2019 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2020 hsave->save.cr4 = svm->vcpu.arch.cr4;
2021 hsave->save.rflags = vmcb->save.rflags;
2022 hsave->save.rip = svm->next_rip;
2023 hsave->save.rsp = vmcb->save.rsp;
2024 hsave->save.rax = vmcb->save.rax;
2025 if (npt_enabled)
2026 hsave->save.cr3 = vmcb->save.cr3;
2027 else
2028 hsave->save.cr3 = svm->vcpu.arch.cr3;
2029
0460a979 2030 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2031
2032 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2033 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2034 else
2035 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2036
2037 /* Load the nested guest state */
2038 svm->vmcb->save.es = nested_vmcb->save.es;
2039 svm->vmcb->save.cs = nested_vmcb->save.cs;
2040 svm->vmcb->save.ss = nested_vmcb->save.ss;
2041 svm->vmcb->save.ds = nested_vmcb->save.ds;
2042 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2043 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2044 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2045 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2046 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2047 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2048 if (npt_enabled) {
2049 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2050 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2051 } else
3d6368ef 2052 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2053
2054 /* Guest paging mode is active - reset mmu */
2055 kvm_mmu_reset_context(&svm->vcpu);
2056
defbba56 2057 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2058 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2059 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2060 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2061
3d6368ef
AG		 2062 /* In case we don't even reach vcpu_run, the fields are not updated */
2063 svm->vmcb->save.rax = nested_vmcb->save.rax;
2064 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2065 svm->vmcb->save.rip = nested_vmcb->save.rip;
2066 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2067 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2068 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2069
f7138538 2070 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2071 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2072
aad42c64
JR		 2073 /* cache intercepts */
2074 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2075 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2076 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2077 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2078 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2079 svm->nested.intercept = nested_vmcb->control.intercept;
2080
3d6368ef 2081 force_new_asid(&svm->vcpu);
3d6368ef 2082 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2083 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2084 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2085 else
2086 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2087
88ab24ad
JR		 2088 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2089 /* We only want the cr8 intercept bits of the guest */
2090 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2091 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2092 }
2093
e0231715
JR		 2094 /*
2095 * We don't want a nested guest to be more powerful than the guest, so
2096 * all intercepts are ORed
2097 */
88ab24ad
JR		 2098 svm->vmcb->control.intercept_cr_read |=
2099 nested_vmcb->control.intercept_cr_read;
2100 svm->vmcb->control.intercept_cr_write |=
2101 nested_vmcb->control.intercept_cr_write;
2102 svm->vmcb->control.intercept_dr_read |=
2103 nested_vmcb->control.intercept_dr_read;
2104 svm->vmcb->control.intercept_dr_write |=
2105 nested_vmcb->control.intercept_dr_write;
2106 svm->vmcb->control.intercept_exceptions |=
2107 nested_vmcb->control.intercept_exceptions;
2108
2109 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2110
2111 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2112 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2113 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2114 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2115 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2116 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2117
7597f129 2118 nested_svm_unmap(page);
9738b2c9 2119
06fc7772
JR		 2120 /* nested_vmcb is our indicator if nested SVM is activated */
2121 svm->nested.vmcb = vmcb_gpa;
2122
2af9194d 2123 enable_gif(svm);
3d6368ef 2124
9738b2c9 2125 return true;
3d6368ef
AG		 2126}
2127
9966bf68 2128static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2129{
2130 to_vmcb->save.fs = from_vmcb->save.fs;
2131 to_vmcb->save.gs = from_vmcb->save.gs;
2132 to_vmcb->save.tr = from_vmcb->save.tr;
2133 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2134 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2135 to_vmcb->save.star = from_vmcb->save.star;
2136 to_vmcb->save.lstar = from_vmcb->save.lstar;
2137 to_vmcb->save.cstar = from_vmcb->save.cstar;
2138 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2139 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2140 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2141 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2142}
2143
851ba692 2144static int vmload_interception(struct vcpu_svm *svm)
5542675b 2145{
9966bf68 2146 struct vmcb *nested_vmcb;
7597f129 2147 struct page *page;
9966bf68 2148
5542675b
AG		 2149 if (nested_svm_check_permissions(svm))
2150 return 1;
2151
2152 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2153 skip_emulated_instruction(&svm->vcpu);
2154
7597f129 2155 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2156 if (!nested_vmcb)
2157 return 1;
2158
2159 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2160 nested_svm_unmap(page);
5542675b
AG		 2161
2162 return 1;
2163}
2164
851ba692 2165static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2166{
9966bf68 2167 struct vmcb *nested_vmcb;
7597f129 2168 struct page *page;
9966bf68 2169
5542675b
AG		 2170 if (nested_svm_check_permissions(svm))
2171 return 1;
2172
2173 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2174 skip_emulated_instruction(&svm->vcpu);
2175
7597f129 2176 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2177 if (!nested_vmcb)
2178 return 1;
2179
2180 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2181 nested_svm_unmap(page);
5542675b
AG		 2182
2183 return 1;
2184}
2185
851ba692 2186static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2187{
3d6368ef
AG		 2188 if (nested_svm_check_permissions(svm))
2189 return 1;
2190
2191 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2192 skip_emulated_instruction(&svm->vcpu);
2193
9738b2c9 2194 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2195 return 1;
2196
9738b2c9 2197 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2198 goto failed;
2199
2200 return 1;
2201
2202failed:
2203
2204 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2205 svm->vmcb->control.exit_code_hi = 0;
2206 svm->vmcb->control.exit_info_1 = 0;
2207 svm->vmcb->control.exit_info_2 = 0;
2208
2209 nested_svm_vmexit(svm);
3d6368ef
AG		 2210
2211 return 1;
2212}
2213
851ba692 2214static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2215{
2216 if (nested_svm_check_permissions(svm))
2217 return 1;
2218
2219 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2220 skip_emulated_instruction(&svm->vcpu);
2221
2af9194d 2222 enable_gif(svm);
1371d904
AG		 2223
2224 return 1;
2225}
2226
851ba692 2227static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2228{
2229 if (nested_svm_check_permissions(svm))
2230 return 1;
2231
2232 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2233 skip_emulated_instruction(&svm->vcpu);
2234
2af9194d 2235 disable_gif(svm);
1371d904
AG		 2236
2237 /* After a CLGI no interrupts should come */
2238 svm_clear_vintr(svm);
2239 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2240
2241 return 1;
2242}
2243
851ba692 2244static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2245{
2246 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2247
ec1ff790
JR		 2248 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2249 vcpu->arch.regs[VCPU_REGS_RAX]);
2250
ff092385
AG		 2251 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2252 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2253
2254 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2255 skip_emulated_instruction(&svm->vcpu);
2256 return 1;
2257}
2258
532a46b9
JR		 2259static int skinit_interception(struct vcpu_svm *svm)
2260{
2261 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2262
2263 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2264 return 1;
2265}
2266
851ba692 2267static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2268{
7ee5d940 2269 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2270 return 1;
2271}
2272
851ba692 2273static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2274{
37817f29 2275 u16 tss_selector;
64a7ec06
GN		 2276 int reason;
2277 int int_type = svm->vmcb->control.exit_int_info &
2278 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2279 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2280 uint32_t type =
2281 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2282 uint32_t idt_v =
2283 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2284
2285 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2286
37817f29
IE		 2287 if (svm->vmcb->control.exit_info_2 &
2288 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2289 reason = TASK_SWITCH_IRET;
2290 else if (svm->vmcb->control.exit_info_2 &
2291 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2292 reason = TASK_SWITCH_JMP;
fe8e7f83 2293 else if (idt_v)
64a7ec06
GN		 2294 reason = TASK_SWITCH_GATE;
2295 else
2296 reason = TASK_SWITCH_CALL;
2297
fe8e7f83
GN		 2298 if (reason == TASK_SWITCH_GATE) {
2299 switch (type) {
2300 case SVM_EXITINTINFO_TYPE_NMI:
2301 svm->vcpu.arch.nmi_injected = false;
2302 break;
2303 case SVM_EXITINTINFO_TYPE_EXEPT:
2304 kvm_clear_exception_queue(&svm->vcpu);
2305 break;
2306 case SVM_EXITINTINFO_TYPE_INTR:
2307 kvm_clear_interrupt_queue(&svm->vcpu);
2308 break;
2309 default:
2310 break;
2311 }
2312 }
64a7ec06 2313
8317c298
GN		 2314 if (reason != TASK_SWITCH_GATE ||
2315 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2316 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2317 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2318 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2319
2320 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2321}
2322
851ba692 2323static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2324{
5fdbf976 2325 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2326 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2327 return 1;
6aa8b732
AK		 2328}
2329
851ba692 2330static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2331{
2332 ++svm->vcpu.stat.nmi_window_exits;
2333 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2334 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2335 return 1;
2336}
2337
851ba692 2338static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2339{
851ba692 2340 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2341 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2342 return 1;
2343}
2344
851ba692 2345static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2346{
851ba692 2347 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2348 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2349 return 1;
2350}
2351
851ba692 2352static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2353{
851ba692
AK		 2354 struct kvm_run *kvm_run = svm->vcpu.run;
2355
0a5fff19
GN		 2356 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2357 /* instruction emulation calls kvm_set_cr8() */
851ba692 2358 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2359 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2360 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2361 return 1;
95ba8273 2362 }
0a5fff19
GN		 2363 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2364 return 1;
1d075434
JR		 2365 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2366 return 0;
2367}
2368
6aa8b732
AK		 2369static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2370{
a2fa3e9f
GH		 2371 struct vcpu_svm *svm = to_svm(vcpu);
2372
6aa8b732 2373 switch (ecx) {
af24a4e4 2374 case MSR_IA32_TSC: {
20824f30 2375 u64 tsc_offset;
6aa8b732 2376
20824f30
JR		 2377 if (is_nested(svm))
2378 tsc_offset = svm->nested.hsave->control.tsc_offset;
2379 else
2380 tsc_offset = svm->vmcb->control.tsc_offset;
2381
2382 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2383 break;
2384 }
0e859cac 2385 case MSR_K6_STAR:
a2fa3e9f 2386 *data = svm->vmcb->save.star;
6aa8b732 2387 break;
0e859cac 2388#ifdef CONFIG_X86_64
6aa8b732 2389 case MSR_LSTAR:
a2fa3e9f 2390 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2391 break;
2392 case MSR_CSTAR:
a2fa3e9f 2393 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2394 break;
2395 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2396 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2397 break;
2398 case MSR_SYSCALL_MASK:
a2fa3e9f 2399 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2400 break;
2401#endif
2402 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2403 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2404 break;
2405 case MSR_IA32_SYSENTER_EIP:
017cb99e 2406 *data = svm->sysenter_eip;
6aa8b732
AK		 2407 break;
2408 case MSR_IA32_SYSENTER_ESP:
017cb99e 2409 *data = svm->sysenter_esp;
6aa8b732 2410 break;
e0231715
JR		 2411 /*
2412 * Nobody will change the following 5 values in the VMCB so we can
2413 * safely return them on rdmsr. They will always be 0 until LBRV is
2414 * implemented.
2415 */
a2938c80
JR		 2416 case MSR_IA32_DEBUGCTLMSR:
2417 *data = svm->vmcb->save.dbgctl;
2418 break;
2419 case MSR_IA32_LASTBRANCHFROMIP:
2420 *data = svm->vmcb->save.br_from;
2421 break;
2422 case MSR_IA32_LASTBRANCHTOIP:
2423 *data = svm->vmcb->save.br_to;
2424 break;
2425 case MSR_IA32_LASTINTFROMIP:
2426 *data = svm->vmcb->save.last_excp_from;
2427 break;
2428 case MSR_IA32_LASTINTTOIP:
2429 *data = svm->vmcb->save.last_excp_to;
2430 break;
b286d5d8 2431 case MSR_VM_HSAVE_PA:
e6aa9abd 2432 *data = svm->nested.hsave_msr;
b286d5d8 2433 break;
eb6f302e 2434 case MSR_VM_CR:
4a810181 2435 *data = svm->nested.vm_cr_msr;
eb6f302e 2436 break;
c8a73f18
AG		 2437 case MSR_IA32_UCODE_REV:
2438 *data = 0x01000065;
2439 break;
6aa8b732 2440 default:
3bab1f5d 2441 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2442 }
2443 return 0;
2444}
2445
851ba692 2446static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2447{
ad312c7c 2448 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2449 u64 data;
2450
59200273
AK		 2451 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2452 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2453 kvm_inject_gp(&svm->vcpu, 0);
59200273 2454 } else {
229456fc 2455 trace_kvm_msr_read(ecx, data);
af9ca2d7 2456
5fdbf976 2457 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2458 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2459 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2460 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2461 }
2462 return 1;
2463}
2464
4a810181
JR		 2465static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2466{
2467 struct vcpu_svm *svm = to_svm(vcpu);
2468 int svm_dis, chg_mask;
2469
2470 if (data & ~SVM_VM_CR_VALID_MASK)
2471 return 1;
2472
2473 chg_mask = SVM_VM_CR_VALID_MASK;
2474
2475 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2476 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2477
2478 svm->nested.vm_cr_msr &= ~chg_mask;
2479 svm->nested.vm_cr_msr |= (data & chg_mask);
2480
2481 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2482
2483 /* check for svm_disable while efer.svme is set */
2484 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2485 return 1;
2486
2487 return 0;
2488}
2489
6aa8b732
AK		 2490static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2491{
a2fa3e9f
GH		 2492 struct vcpu_svm *svm = to_svm(vcpu);
2493
6aa8b732 2494 switch (ecx) {
af24a4e4 2495 case MSR_IA32_TSC: {
20824f30
JR		 2496 u64 tsc_offset = data - native_read_tsc();
2497 u64 g_tsc_offset = 0;
2498
2499 if (is_nested(svm)) {
2500 g_tsc_offset = svm->vmcb->control.tsc_offset -
2501 svm->nested.hsave->control.tsc_offset;
2502 svm->nested.hsave->control.tsc_offset = tsc_offset;
2503 }
2504
2505 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2506
6aa8b732
AK		 2507 break;
2508 }
0e859cac 2509 case MSR_K6_STAR:
a2fa3e9f 2510 svm->vmcb->save.star = data;
6aa8b732 2511 break;
49b14f24 2512#ifdef CONFIG_X86_64
6aa8b732 2513 case MSR_LSTAR:
a2fa3e9f 2514 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2515 break;
2516 case MSR_CSTAR:
a2fa3e9f 2517 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2518 break;
2519 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2520 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2521 break;
2522 case MSR_SYSCALL_MASK:
a2fa3e9f 2523 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2524 break;
2525#endif
2526 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2527 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2528 break;
2529 case MSR_IA32_SYSENTER_EIP:
017cb99e 2530 svm->sysenter_eip = data;
a2fa3e9f 2531 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2532 break;
2533 case MSR_IA32_SYSENTER_ESP:
017cb99e 2534 svm->sysenter_esp = data;
a2fa3e9f 2535 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2536 break;
a2938c80 2537 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2538 if (!svm_has(SVM_FEATURE_LBRV)) {
2539 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2540 __func__, data);
24e09cbf
JR		 2541 break;
2542 }
2543 if (data & DEBUGCTL_RESERVED_BITS)
2544 return 1;
2545
2546 svm->vmcb->save.dbgctl = data;
2547 if (data & (1ULL<<0))
2548 svm_enable_lbrv(svm);
2549 else
2550 svm_disable_lbrv(svm);
a2938c80 2551 break;
b286d5d8 2552 case MSR_VM_HSAVE_PA:
e6aa9abd 2553 svm->nested.hsave_msr = data;
62b9abaa 2554 break;
3c5d0a44 2555 case MSR_VM_CR:
4a810181 2556 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2557 case MSR_VM_IGNNE:
3c5d0a44
AG		 2558 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2559 break;
6aa8b732 2560 default:
3bab1f5d 2561 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2562 }
2563 return 0;
2564}
2565
851ba692 2566static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2567{
ad312c7c 2568 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2569 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2570 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2571
af9ca2d7 2572
5fdbf976 2573 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2574 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2575 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2576 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2577 } else {
2578 trace_kvm_msr_write(ecx, data);
e756fc62 2579 skip_emulated_instruction(&svm->vcpu);
59200273 2580 }
6aa8b732
AK		 2581 return 1;
2582}
2583
851ba692 2584static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2585{
e756fc62 2586 if (svm->vmcb->control.exit_info_1)
851ba692 2587 return wrmsr_interception(svm);
6aa8b732 2588 else
851ba692 2589 return rdmsr_interception(svm);
6aa8b732
AK		 2590}
2591
851ba692 2592static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2593{
851ba692
AK		 2594 struct kvm_run *kvm_run = svm->vcpu.run;
2595
f0b85051 2596 svm_clear_vintr(svm);
85f455f7 2597 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2598 /*
2599 * If the user space waits to inject interrupts, exit as soon as
2600 * possible
2601 */
8061823a
GN		 2602 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2603 kvm_run->request_interrupt_window &&
2604 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2605 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2606 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2607 return 0;
2608 }
2609
2610 return 1;
2611}
2612
565d0998
ML		 2613static int pause_interception(struct vcpu_svm *svm)
2614{
2615 kvm_vcpu_on_spin(&(svm->vcpu));
2616 return 1;
2617}
2618
851ba692 2619static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2620 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2621 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2622 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2623 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2624 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2625 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2626 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2627 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2628 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2629 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2630 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2631 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2632 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2633 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2634 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2635 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2636 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2637 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2638 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2639 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2640 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2641 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2642 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2643 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2644 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2645 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2646 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2647 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2648 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2649 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2650 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2651 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2652 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2653 [SVM_EXIT_SMI] = nop_on_interception,
2654 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2655 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2656 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2657 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2658 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2659 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2660 [SVM_EXIT_HLT] = halt_interception,
a7052897 2661 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2662 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2663 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2664 [SVM_EXIT_MSR] = msr_interception,
2665 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2666 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2667 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2668 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2669 [SVM_EXIT_VMLOAD] = vmload_interception,
2670 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2671 [SVM_EXIT_STGI] = stgi_interception,
2672 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2673 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2674 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2675 [SVM_EXIT_MONITOR] = invalid_op_interception,
2676 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2677 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2678};
2679
851ba692 2680static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2681{
04d2cc77 2682 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2683 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2684 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2685
5bfd8b54 2686 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2687
cd3ff653
JR		 2688 if (unlikely(svm->nested.exit_required)) {
2689 nested_svm_vmexit(svm);
2690 svm->nested.exit_required = false;
2691
2692 return 1;
2693 }
2694
cf74a78b 2695 if (is_nested(svm)) {
410e4d57
JR		 2696 int vmexit;
2697
d8cabddf
JR		 2698 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2699 svm->vmcb->control.exit_info_1,
2700 svm->vmcb->control.exit_info_2,
2701 svm->vmcb->control.exit_int_info,
2702 svm->vmcb->control.exit_int_info_err);
2703
410e4d57
JR		 2704 vmexit = nested_svm_exit_special(svm);
2705
2706 if (vmexit == NESTED_EXIT_CONTINUE)
2707 vmexit = nested_svm_exit_handled(svm);
2708
2709 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2710 return 1;
cf74a78b
AG		 2711 }
2712
a5c3832d
JR		 2713 svm_complete_interrupts(svm);
2714
888f9f3e 2715 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2716 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2717 if (npt_enabled)
709ddebf 2718 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2719
2720 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2721 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2722 kvm_run->fail_entry.hardware_entry_failure_reason
2723 = svm->vmcb->control.exit_code;
2724 return 0;
2725 }
2726
a2fa3e9f 2727 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2728 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2729 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2730 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2731 "exit_code 0x%x\n",
b8688d51 2732 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2733 exit_code);
2734
9d8f549d 2735 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2736 || !svm_exit_handlers[exit_code]) {
6aa8b732 2737 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2738 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2739 return 0;
2740 }
2741
851ba692 2742 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2743}
2744
2745static void reload_tss(struct kvm_vcpu *vcpu)
2746{
2747 int cpu = raw_smp_processor_id();
2748
0fe1e009
TH		 2749 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2750 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2751 load_TR_desc();
2752}
2753
e756fc62 2754static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2755{
2756 int cpu = raw_smp_processor_id();
2757
0fe1e009 2758 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2759
a2fa3e9f 2760 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2761 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2762 if (svm->asid_generation != sd->asid_generation)
2763 new_asid(svm, sd);
6aa8b732
AK		 2764}
2765
95ba8273
GN		 2766static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2767{
2768 struct vcpu_svm *svm = to_svm(vcpu);
2769
2770 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2771 vcpu->arch.hflags |= HF_NMI_MASK;
2772 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2773 ++vcpu->stat.nmi_injections;
2774}
6aa8b732 2775
85f455f7 2776static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2777{
2778 struct vmcb_control_area *control;
2779
229456fc 2780 trace_kvm_inj_virq(irq);
af9ca2d7 2781
fa89a817 2782 ++svm->vcpu.stat.irq_injections;
e756fc62 2783 control = &svm->vmcb->control;
85f455f7 2784 control->int_vector = irq;
6aa8b732
AK		 2785 control->int_ctl &= ~V_INTR_PRIO_MASK;
2786 control->int_ctl |= V_IRQ_MASK |
2787 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2788}
2789
66fd3f7f 2790static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2791{
2792 struct vcpu_svm *svm = to_svm(vcpu);
2793
2af9194d 2794 BUG_ON(!(gif_set(svm)));
cf74a78b 2795
219b65dc
AG		 2796 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2797 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2798}
2799
95ba8273 2800static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2801{
2802 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2803
88ab24ad
JR		 2804 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2805 return;
2806
95ba8273 2807 if (irr == -1)
aaacfc9a
JR		 2808 return;
2809
95ba8273
GN		 2810 if (tpr >= irr)
2811 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2812}
aaacfc9a 2813
95ba8273
GN		 2814static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2815{
2816 struct vcpu_svm *svm = to_svm(vcpu);
2817 struct vmcb *vmcb = svm->vmcb;
2818 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2819 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2820}
2821
3cfc3092
JK		 2822static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2823{
2824 struct vcpu_svm *svm = to_svm(vcpu);
2825
2826 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2827}
2828
2829static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2830{
2831 struct vcpu_svm *svm = to_svm(vcpu);
2832
2833 if (masked) {
2834 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2835 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2836 } else {
2837 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2838 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2839 }
2840}
2841
78646121
GN		 2842static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2843{
2844 struct vcpu_svm *svm = to_svm(vcpu);
2845 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2846 int ret;
2847
2848 if (!gif_set(svm) ||
2849 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2850 return 0;
2851
2852 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2853
2854 if (is_nested(svm))
2855 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2856
2857 return ret;
78646121
GN		 2858}
2859
9222be18 2860static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2861{
219b65dc 2862 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2863
e0231715
JR		 2864 /*
2865 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2866 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2867 * get that intercept, this function will be called again though and
2868 * we'll get the vintr intercept.
2869 */
8fe54654 2870 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2871 svm_set_vintr(svm);
2872 svm_inject_irq(svm, 0x0);
2873 }
85f455f7
ED		 2874}
2875
95ba8273 2876static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2877{
04d2cc77 2878 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2879
44c11430
GN		 2880 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2881 == HF_NMI_MASK)
2882 return; /* IRET will cause a vm exit */
2883
e0231715
JR		 2884 /*
2885 * Something prevents NMI from been injected. Single step over possible
2886 * problem (IRET or exception injection or interrupt shadow)
2887 */
887f500c
JR		 2888 if (gif_set(svm) && nested_svm_nmi(svm)) {
2889 svm->nmi_singlestep = true;
2890 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2891 update_db_intercept(vcpu);
2892 }
c1150d8c
DL		 2893}
2894
cbc94022
IE		 2895static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2896{
2897 return 0;
2898}
2899
d9e368d6
AK		 2900static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2901{
2902 force_new_asid(vcpu);
2903}
2904
04d2cc77
AK		 2905static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2906{
2907}
2908
d7bf8221
JR		 2909static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2910{
2911 struct vcpu_svm *svm = to_svm(vcpu);
2912
88ab24ad
JR		 2913 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2914 return;
2915
d7bf8221
JR		 2916 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2917 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2918 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2919 }
2920}
2921
649d6864
JR		 2922static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2923{
2924 struct vcpu_svm *svm = to_svm(vcpu);
2925 u64 cr8;
2926
88ab24ad
JR		 2927 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2928 return;
2929
649d6864
JR		 2930 cr8 = kvm_get_cr8(vcpu);
2931 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2932 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2933}
2934
9222be18
GN		 2935static void svm_complete_interrupts(struct vcpu_svm *svm)
2936{
2937 u8 vector;
2938 int type;
2939 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2940 unsigned int3_injected = svm->int3_injected;
2941
2942 svm->int3_injected = 0;
9222be18 2943
44c11430
GN		 2944 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2945 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2946
9222be18
GN		 2947 svm->vcpu.arch.nmi_injected = false;
2948 kvm_clear_exception_queue(&svm->vcpu);
2949 kvm_clear_interrupt_queue(&svm->vcpu);
2950
2951 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2952 return;
2953
2954 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2955 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2956
2957 switch (type) {
2958 case SVM_EXITINTINFO_TYPE_NMI:
2959 svm->vcpu.arch.nmi_injected = true;
2960 break;
2961 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2962 if (is_nested(svm))
2963 break;
66b7138f
JK		 2964 /*
2965 * In case of software exceptions, do not reinject the vector,
2966 * but re-execute the instruction instead. Rewind RIP first
2967 * if we emulated INT3 before.
2968 */
2969 if (kvm_exception_is_soft(vector)) {
2970 if (vector == BP_VECTOR && int3_injected &&
2971 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2972 kvm_rip_write(&svm->vcpu,
2973 kvm_rip_read(&svm->vcpu) -
2974 int3_injected);
9222be18 2975 break;
66b7138f 2976 }
9222be18
GN		 2977 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2978 u32 err = svm->vmcb->control.exit_int_info_err;
2979 kvm_queue_exception_e(&svm->vcpu, vector, err);
2980
2981 } else
2982 kvm_queue_exception(&svm->vcpu, vector);
2983 break;
2984 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2985 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2986 break;
2987 default:
2988 break;
2989 }
2990}
2991
80e31d4f
AK		 2992#ifdef CONFIG_X86_64
2993#define R "r"
2994#else
2995#define R "e"
2996#endif
2997
851ba692 2998static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2999{
a2fa3e9f 3000 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3001 u16 fs_selector;
3002 u16 gs_selector;
3003 u16 ldt_selector;
d9e368d6 3004
cd3ff653
JR		 3005 /*
3006 * A vmexit emulation is required before the vcpu can be executed
3007 * again.
3008 */
3009 if (unlikely(svm->nested.exit_required))
3010 return;
3011
5fdbf976
MT		 3012 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3013 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3014 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3015
e756fc62 3016 pre_svm_run(svm);
6aa8b732 3017
649d6864
JR		 3018 sync_lapic_to_cr8(vcpu);
3019
6aa8b732 3020 save_host_msrs(vcpu);
d6e88aec
AK		 3021 fs_selector = kvm_read_fs();
3022 gs_selector = kvm_read_gs();
3023 ldt_selector = kvm_read_ldt();
cda0ffdd 3024 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3025 /* required for live migration with NPT */
3026 if (npt_enabled)
3027 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3028
04d2cc77
AK		 3029 clgi();
3030
3031 local_irq_enable();
36241b8c 3032
6aa8b732 3033 asm volatile (
80e31d4f
AK		 3034 "push %%"R"bp; \n\t"
3035 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3036 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3037 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3038 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3039 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3040 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3041#ifdef CONFIG_X86_64
fb3f0f51
RR		 3042 "mov %c[r8](%[svm]), %%r8 \n\t"
3043 "mov %c[r9](%[svm]), %%r9 \n\t"
3044 "mov %c[r10](%[svm]), %%r10 \n\t"
3045 "mov %c[r11](%[svm]), %%r11 \n\t"
3046 "mov %c[r12](%[svm]), %%r12 \n\t"
3047 "mov %c[r13](%[svm]), %%r13 \n\t"
3048 "mov %c[r14](%[svm]), %%r14 \n\t"
3049 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3050#endif
3051
6aa8b732 3052 /* Enter guest mode */
80e31d4f
AK		 3053 "push %%"R"ax \n\t"
3054 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3055 __ex(SVM_VMLOAD) "\n\t"
3056 __ex(SVM_VMRUN) "\n\t"
3057 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3058 "pop %%"R"ax \n\t"
6aa8b732
AK		 3059
3060 /* Save guest registers, load host registers */
80e31d4f
AK		 3061 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3062 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3063 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3064 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3065 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3066 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3067#ifdef CONFIG_X86_64
fb3f0f51
RR		 3068 "mov %%r8, %c[r8](%[svm]) \n\t"
3069 "mov %%r9, %c[r9](%[svm]) \n\t"
3070 "mov %%r10, %c[r10](%[svm]) \n\t"
3071 "mov %%r11, %c[r11](%[svm]) \n\t"
3072 "mov %%r12, %c[r12](%[svm]) \n\t"
3073 "mov %%r13, %c[r13](%[svm]) \n\t"
3074 "mov %%r14, %c[r14](%[svm]) \n\t"
3075 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3076#endif
80e31d4f 3077 "pop %%"R"bp"
6aa8b732 3078 :
fb3f0f51 3079 : [svm]"a"(svm),
6aa8b732 3080 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3081 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3082 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3083 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3084 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3085 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3086 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3087#ifdef CONFIG_X86_64
ad312c7c
ZX		 3088 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3089 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3090 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3091 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3092 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3093 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3094 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3095 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3096#endif
54a08c04 3097 : "cc", "memory"
80e31d4f 3098 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3099#ifdef CONFIG_X86_64
54a08c04
LV		 3100 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3101#endif
3102 );
6aa8b732 3103
ad312c7c 3104 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3105 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3106 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3107 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3108
d6e88aec
AK		 3109 kvm_load_fs(fs_selector);
3110 kvm_load_gs(gs_selector);
3111 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3112 load_host_msrs(vcpu);
3113
3114 reload_tss(vcpu);
3115
56ba47dd
AK		 3116 local_irq_disable();
3117
3118 stgi();
3119
d7bf8221
JR		 3120 sync_cr8_to_lapic(vcpu);
3121
a2fa3e9f 3122 svm->next_rip = 0;
9222be18 3123
6de4f3ad
AK		 3124 if (npt_enabled) {
3125 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3126 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3127 }
6aa8b732
AK		 3128}
3129
80e31d4f
AK		 3130#undef R
3131
6aa8b732
AK		 3132static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3133{
a2fa3e9f
GH		 3134 struct vcpu_svm *svm = to_svm(vcpu);
3135
709ddebf
JR		 3136 if (npt_enabled) {
3137 svm->vmcb->control.nested_cr3 = root;
3138 force_new_asid(vcpu);
3139 return;
3140 }
3141
a2fa3e9f 3142 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3143 force_new_asid(vcpu);
3144}
3145
6aa8b732
AK		 3146static int is_disabled(void)
3147{
6031a61c
JR		 3148 u64 vm_cr;
3149
3150 rdmsrl(MSR_VM_CR, vm_cr);
3151 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3152 return 1;
3153
6aa8b732
AK		 3154 return 0;
3155}
3156
102d8325
IM		 3157static void
3158svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3159{
3160 /*
3161 * Patch in the VMMCALL instruction:
3162 */
3163 hypercall[0] = 0x0f;
3164 hypercall[1] = 0x01;
3165 hypercall[2] = 0xd9;
102d8325
IM		 3166}
3167
002c7f7c
YS		 3168static void svm_check_processor_compat(void *rtn)
3169{
3170 *(int *)rtn = 0;
3171}
3172
774ead3a
AK		 3173static bool svm_cpu_has_accelerated_tpr(void)
3174{
3175 return false;
3176}
3177
67253af5
SY		 3178static int get_npt_level(void)
3179{
3180#ifdef CONFIG_X86_64
3181 return PT64_ROOT_LEVEL;
3182#else
3183 return PT32E_ROOT_LEVEL;
3184#endif
3185}
3186
4b12f0de 3187static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3188{
3189 return 0;
3190}
3191
0e851880
SY		 3192static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3193{
3194}
3195
229456fc 3196static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3197 { SVM_EXIT_READ_CR0, "read_cr0" },
3198 { SVM_EXIT_READ_CR3, "read_cr3" },
3199 { SVM_EXIT_READ_CR4, "read_cr4" },
3200 { SVM_EXIT_READ_CR8, "read_cr8" },
3201 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3202 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3203 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3204 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3205 { SVM_EXIT_READ_DR0, "read_dr0" },
3206 { SVM_EXIT_READ_DR1, "read_dr1" },
3207 { SVM_EXIT_READ_DR2, "read_dr2" },
3208 { SVM_EXIT_READ_DR3, "read_dr3" },
3209 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3210 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3211 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3212 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3213 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3214 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3215 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3216 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3217 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3218 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3219 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3220 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3221 { SVM_EXIT_INTR, "interrupt" },
3222 { SVM_EXIT_NMI, "nmi" },
3223 { SVM_EXIT_SMI, "smi" },
3224 { SVM_EXIT_INIT, "init" },
3225 { SVM_EXIT_VINTR, "vintr" },
3226 { SVM_EXIT_CPUID, "cpuid" },
3227 { SVM_EXIT_INVD, "invd" },
3228 { SVM_EXIT_HLT, "hlt" },
3229 { SVM_EXIT_INVLPG, "invlpg" },
3230 { SVM_EXIT_INVLPGA, "invlpga" },
3231 { SVM_EXIT_IOIO, "io" },
3232 { SVM_EXIT_MSR, "msr" },
3233 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3234 { SVM_EXIT_SHUTDOWN, "shutdown" },
3235 { SVM_EXIT_VMRUN, "vmrun" },
3236 { SVM_EXIT_VMMCALL, "hypercall" },
3237 { SVM_EXIT_VMLOAD, "vmload" },
3238 { SVM_EXIT_VMSAVE, "vmsave" },
3239 { SVM_EXIT_STGI, "stgi" },
3240 { SVM_EXIT_CLGI, "clgi" },
3241 { SVM_EXIT_SKINIT, "skinit" },
3242 { SVM_EXIT_WBINVD, "wbinvd" },
3243 { SVM_EXIT_MONITOR, "monitor" },
3244 { SVM_EXIT_MWAIT, "mwait" },
3245 { SVM_EXIT_NPF, "npf" },
3246 { -1, NULL }
3247};
3248
17cc3935 3249static int svm_get_lpage_level(void)
344f414f 3250{
17cc3935 3251 return PT_PDPE_LEVEL;
344f414f
JR		 3252}
3253
4e47c7a6
SY		 3254static bool svm_rdtscp_supported(void)
3255{
3256 return false;
3257}
3258
02daab21
AK		 3259static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3260{
3261 struct vcpu_svm *svm = to_svm(vcpu);
3262
02daab21 3263 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3264 if (is_nested(svm))
3265 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3266 update_cr0_intercept(svm);
02daab21
AK		 3267}
3268
cbdd1bea 3269static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3270 .cpu_has_kvm_support = has_svm,
3271 .disabled_by_bios = is_disabled,
3272 .hardware_setup = svm_hardware_setup,
3273 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3274 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3275 .hardware_enable = svm_hardware_enable,
3276 .hardware_disable = svm_hardware_disable,
774ead3a 3277 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3278
3279 .vcpu_create = svm_create_vcpu,
3280 .vcpu_free = svm_free_vcpu,
04d2cc77 3281 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3282
04d2cc77 3283 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3284 .vcpu_load = svm_vcpu_load,
3285 .vcpu_put = svm_vcpu_put,
3286
3287 .set_guest_debug = svm_guest_debug,
3288 .get_msr = svm_get_msr,
3289 .set_msr = svm_set_msr,
3290 .get_segment_base = svm_get_segment_base,
3291 .get_segment = svm_get_segment,
3292 .set_segment = svm_set_segment,
2e4d2653 3293 .get_cpl = svm_get_cpl,
1747fb71 3294 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3295 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3296 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3297 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3298 .set_cr3 = svm_set_cr3,
3299 .set_cr4 = svm_set_cr4,
3300 .set_efer = svm_set_efer,
3301 .get_idt = svm_get_idt,
3302 .set_idt = svm_set_idt,
3303 .get_gdt = svm_get_gdt,
3304 .set_gdt = svm_set_gdt,
3305 .get_dr = svm_get_dr,
3306 .set_dr = svm_set_dr,
6de4f3ad 3307 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3308 .get_rflags = svm_get_rflags,
3309 .set_rflags = svm_set_rflags,
6b52d186 3310 .fpu_activate = svm_fpu_activate,
02daab21 3311 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3312
6aa8b732 3313 .tlb_flush = svm_flush_tlb,
6aa8b732 3314
6aa8b732 3315 .run = svm_vcpu_run,
04d2cc77 3316 .handle_exit = handle_exit,
6aa8b732 3317 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3318 .set_interrupt_shadow = svm_set_interrupt_shadow,
3319 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3320 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3321 .set_irq = svm_set_irq,
95ba8273 3322 .set_nmi = svm_inject_nmi,
298101da 3323 .queue_exception = svm_queue_exception,
78646121 3324 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3325 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3326 .get_nmi_mask = svm_get_nmi_mask,
3327 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3328 .enable_nmi_window = enable_nmi_window,
3329 .enable_irq_window = enable_irq_window,
3330 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3331
3332 .set_tss_addr = svm_set_tss_addr,
67253af5 3333 .get_tdp_level = get_npt_level,
4b12f0de 3334 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3335
3336 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3337 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3338
3339 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3340
3341 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3342};
3343
3344static int __init svm_init(void)
3345{
cb498ea2 3346 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3347 THIS_MODULE);
6aa8b732
AK		 3348}
3349
3350static void __exit svm_exit(void)
3351{
cb498ea2 3352 kvm_exit();
6aa8b732
AK		 3353}
3354
3355module_init(svm_init)
3356module_exit(svm_exit)
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